| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Target Instruction Enum Values and Descriptors *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_INSTRINFO_ENUM |
| 10 | #undef GET_INSTRINFO_ENUM |
| 11 | namespace llvm { |
| 12 | |
| 13 | namespace LoongArch { |
| 14 | enum { |
| 15 | PHI = 0, |
| 16 | INLINEASM = 1, |
| 17 | INLINEASM_BR = 2, |
| 18 | CFI_INSTRUCTION = 3, |
| 19 | EH_LABEL = 4, |
| 20 | GC_LABEL = 5, |
| 21 | ANNOTATION_LABEL = 6, |
| 22 | KILL = 7, |
| 23 | EXTRACT_SUBREG = 8, |
| 24 | INSERT_SUBREG = 9, |
| 25 | IMPLICIT_DEF = 10, |
| 26 | SUBREG_TO_REG = 11, |
| 27 | COPY_TO_REGCLASS = 12, |
| 28 | DBG_VALUE = 13, |
| 29 | DBG_VALUE_LIST = 14, |
| 30 | DBG_INSTR_REF = 15, |
| 31 | DBG_PHI = 16, |
| 32 | DBG_LABEL = 17, |
| 33 | REG_SEQUENCE = 18, |
| 34 | COPY = 19, |
| 35 | BUNDLE = 20, |
| 36 | LIFETIME_START = 21, |
| 37 | LIFETIME_END = 22, |
| 38 | PSEUDO_PROBE = 23, |
| 39 | ARITH_FENCE = 24, |
| 40 | STACKMAP = 25, |
| 41 | FENTRY_CALL = 26, |
| 42 | PATCHPOINT = 27, |
| 43 | LOAD_STACK_GUARD = 28, |
| 44 | PREALLOCATED_SETUP = 29, |
| 45 | PREALLOCATED_ARG = 30, |
| 46 | STATEPOINT = 31, |
| 47 | LOCAL_ESCAPE = 32, |
| 48 | FAULTING_OP = 33, |
| 49 | PATCHABLE_OP = 34, |
| 50 | PATCHABLE_FUNCTION_ENTER = 35, |
| 51 | PATCHABLE_RET = 36, |
| 52 | PATCHABLE_FUNCTION_EXIT = 37, |
| 53 | PATCHABLE_TAIL_CALL = 38, |
| 54 | PATCHABLE_EVENT_CALL = 39, |
| 55 | PATCHABLE_TYPED_EVENT_CALL = 40, |
| 56 | ICALL_BRANCH_FUNNEL = 41, |
| 57 | MEMBARRIER = 42, |
| 58 | JUMP_TABLE_DEBUG_INFO = 43, |
| 59 | CONVERGENCECTRL_ENTRY = 44, |
| 60 | CONVERGENCECTRL_ANCHOR = 45, |
| 61 | CONVERGENCECTRL_LOOP = 46, |
| 62 | CONVERGENCECTRL_GLUE = 47, |
| 63 | G_ASSERT_SEXT = 48, |
| 64 | G_ASSERT_ZEXT = 49, |
| 65 | G_ASSERT_ALIGN = 50, |
| 66 | G_ADD = 51, |
| 67 | G_SUB = 52, |
| 68 | G_MUL = 53, |
| 69 | G_SDIV = 54, |
| 70 | G_UDIV = 55, |
| 71 | G_SREM = 56, |
| 72 | G_UREM = 57, |
| 73 | G_SDIVREM = 58, |
| 74 | G_UDIVREM = 59, |
| 75 | G_AND = 60, |
| 76 | G_OR = 61, |
| 77 | G_XOR = 62, |
| 78 | G_IMPLICIT_DEF = 63, |
| 79 | G_PHI = 64, |
| 80 | G_FRAME_INDEX = 65, |
| 81 | G_GLOBAL_VALUE = 66, |
| 82 | G_PTRAUTH_GLOBAL_VALUE = 67, |
| 83 | G_CONSTANT_POOL = 68, |
| 84 | G_EXTRACT = 69, |
| 85 | G_UNMERGE_VALUES = 70, |
| 86 | G_INSERT = 71, |
| 87 | G_MERGE_VALUES = 72, |
| 88 | G_BUILD_VECTOR = 73, |
| 89 | G_BUILD_VECTOR_TRUNC = 74, |
| 90 | G_CONCAT_VECTORS = 75, |
| 91 | G_PTRTOINT = 76, |
| 92 | G_INTTOPTR = 77, |
| 93 | G_BITCAST = 78, |
| 94 | G_FREEZE = 79, |
| 95 | G_CONSTANT_FOLD_BARRIER = 80, |
| 96 | G_INTRINSIC_FPTRUNC_ROUND = 81, |
| 97 | G_INTRINSIC_TRUNC = 82, |
| 98 | G_INTRINSIC_ROUND = 83, |
| 99 | G_INTRINSIC_LRINT = 84, |
| 100 | G_INTRINSIC_LLRINT = 85, |
| 101 | G_INTRINSIC_ROUNDEVEN = 86, |
| 102 | G_READCYCLECOUNTER = 87, |
| 103 | G_READSTEADYCOUNTER = 88, |
| 104 | G_LOAD = 89, |
| 105 | G_SEXTLOAD = 90, |
| 106 | G_ZEXTLOAD = 91, |
| 107 | G_INDEXED_LOAD = 92, |
| 108 | G_INDEXED_SEXTLOAD = 93, |
| 109 | G_INDEXED_ZEXTLOAD = 94, |
| 110 | G_STORE = 95, |
| 111 | G_INDEXED_STORE = 96, |
| 112 | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97, |
| 113 | G_ATOMIC_CMPXCHG = 98, |
| 114 | G_ATOMICRMW_XCHG = 99, |
| 115 | G_ATOMICRMW_ADD = 100, |
| 116 | G_ATOMICRMW_SUB = 101, |
| 117 | G_ATOMICRMW_AND = 102, |
| 118 | G_ATOMICRMW_NAND = 103, |
| 119 | G_ATOMICRMW_OR = 104, |
| 120 | G_ATOMICRMW_XOR = 105, |
| 121 | G_ATOMICRMW_MAX = 106, |
| 122 | G_ATOMICRMW_MIN = 107, |
| 123 | G_ATOMICRMW_UMAX = 108, |
| 124 | G_ATOMICRMW_UMIN = 109, |
| 125 | G_ATOMICRMW_FADD = 110, |
| 126 | G_ATOMICRMW_FSUB = 111, |
| 127 | G_ATOMICRMW_FMAX = 112, |
| 128 | G_ATOMICRMW_FMIN = 113, |
| 129 | G_ATOMICRMW_UINC_WRAP = 114, |
| 130 | G_ATOMICRMW_UDEC_WRAP = 115, |
| 131 | G_FENCE = 116, |
| 132 | G_PREFETCH = 117, |
| 133 | G_BRCOND = 118, |
| 134 | G_BRINDIRECT = 119, |
| 135 | G_INVOKE_REGION_START = 120, |
| 136 | G_INTRINSIC = 121, |
| 137 | G_INTRINSIC_W_SIDE_EFFECTS = 122, |
| 138 | G_INTRINSIC_CONVERGENT = 123, |
| 139 | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124, |
| 140 | G_ANYEXT = 125, |
| 141 | G_TRUNC = 126, |
| 142 | G_CONSTANT = 127, |
| 143 | G_FCONSTANT = 128, |
| 144 | G_VASTART = 129, |
| 145 | G_VAARG = 130, |
| 146 | G_SEXT = 131, |
| 147 | G_SEXT_INREG = 132, |
| 148 | G_ZEXT = 133, |
| 149 | G_SHL = 134, |
| 150 | G_LSHR = 135, |
| 151 | G_ASHR = 136, |
| 152 | G_FSHL = 137, |
| 153 | G_FSHR = 138, |
| 154 | G_ROTR = 139, |
| 155 | G_ROTL = 140, |
| 156 | G_ICMP = 141, |
| 157 | G_FCMP = 142, |
| 158 | G_SCMP = 143, |
| 159 | G_UCMP = 144, |
| 160 | G_SELECT = 145, |
| 161 | G_UADDO = 146, |
| 162 | G_UADDE = 147, |
| 163 | G_USUBO = 148, |
| 164 | G_USUBE = 149, |
| 165 | G_SADDO = 150, |
| 166 | G_SADDE = 151, |
| 167 | G_SSUBO = 152, |
| 168 | G_SSUBE = 153, |
| 169 | G_UMULO = 154, |
| 170 | G_SMULO = 155, |
| 171 | G_UMULH = 156, |
| 172 | G_SMULH = 157, |
| 173 | G_UADDSAT = 158, |
| 174 | G_SADDSAT = 159, |
| 175 | G_USUBSAT = 160, |
| 176 | G_SSUBSAT = 161, |
| 177 | G_USHLSAT = 162, |
| 178 | G_SSHLSAT = 163, |
| 179 | G_SMULFIX = 164, |
| 180 | G_UMULFIX = 165, |
| 181 | G_SMULFIXSAT = 166, |
| 182 | G_UMULFIXSAT = 167, |
| 183 | G_SDIVFIX = 168, |
| 184 | G_UDIVFIX = 169, |
| 185 | G_SDIVFIXSAT = 170, |
| 186 | G_UDIVFIXSAT = 171, |
| 187 | G_FADD = 172, |
| 188 | G_FSUB = 173, |
| 189 | G_FMUL = 174, |
| 190 | G_FMA = 175, |
| 191 | G_FMAD = 176, |
| 192 | G_FDIV = 177, |
| 193 | G_FREM = 178, |
| 194 | G_FPOW = 179, |
| 195 | G_FPOWI = 180, |
| 196 | G_FEXP = 181, |
| 197 | G_FEXP2 = 182, |
| 198 | G_FEXP10 = 183, |
| 199 | G_FLOG = 184, |
| 200 | G_FLOG2 = 185, |
| 201 | G_FLOG10 = 186, |
| 202 | G_FLDEXP = 187, |
| 203 | G_FFREXP = 188, |
| 204 | G_FNEG = 189, |
| 205 | G_FPEXT = 190, |
| 206 | G_FPTRUNC = 191, |
| 207 | G_FPTOSI = 192, |
| 208 | G_FPTOUI = 193, |
| 209 | G_SITOFP = 194, |
| 210 | G_UITOFP = 195, |
| 211 | G_FABS = 196, |
| 212 | G_FCOPYSIGN = 197, |
| 213 | G_IS_FPCLASS = 198, |
| 214 | G_FCANONICALIZE = 199, |
| 215 | G_FMINNUM = 200, |
| 216 | G_FMAXNUM = 201, |
| 217 | G_FMINNUM_IEEE = 202, |
| 218 | G_FMAXNUM_IEEE = 203, |
| 219 | G_FMINIMUM = 204, |
| 220 | G_FMAXIMUM = 205, |
| 221 | G_GET_FPENV = 206, |
| 222 | G_SET_FPENV = 207, |
| 223 | G_RESET_FPENV = 208, |
| 224 | G_GET_FPMODE = 209, |
| 225 | G_SET_FPMODE = 210, |
| 226 | G_RESET_FPMODE = 211, |
| 227 | G_PTR_ADD = 212, |
| 228 | G_PTRMASK = 213, |
| 229 | G_SMIN = 214, |
| 230 | G_SMAX = 215, |
| 231 | G_UMIN = 216, |
| 232 | G_UMAX = 217, |
| 233 | G_ABS = 218, |
| 234 | G_LROUND = 219, |
| 235 | G_LLROUND = 220, |
| 236 | G_BR = 221, |
| 237 | G_BRJT = 222, |
| 238 | G_VSCALE = 223, |
| 239 | G_INSERT_SUBVECTOR = 224, |
| 240 | G_EXTRACT_SUBVECTOR = 225, |
| 241 | G_INSERT_VECTOR_ELT = 226, |
| 242 | G_EXTRACT_VECTOR_ELT = 227, |
| 243 | G_SHUFFLE_VECTOR = 228, |
| 244 | G_SPLAT_VECTOR = 229, |
| 245 | G_VECTOR_COMPRESS = 230, |
| 246 | G_CTTZ = 231, |
| 247 | G_CTTZ_ZERO_UNDEF = 232, |
| 248 | G_CTLZ = 233, |
| 249 | G_CTLZ_ZERO_UNDEF = 234, |
| 250 | G_CTPOP = 235, |
| 251 | G_BSWAP = 236, |
| 252 | G_BITREVERSE = 237, |
| 253 | G_FCEIL = 238, |
| 254 | G_FCOS = 239, |
| 255 | G_FSIN = 240, |
| 256 | G_FTAN = 241, |
| 257 | G_FACOS = 242, |
| 258 | G_FASIN = 243, |
| 259 | G_FATAN = 244, |
| 260 | G_FCOSH = 245, |
| 261 | G_FSINH = 246, |
| 262 | G_FTANH = 247, |
| 263 | G_FSQRT = 248, |
| 264 | G_FFLOOR = 249, |
| 265 | G_FRINT = 250, |
| 266 | G_FNEARBYINT = 251, |
| 267 | G_ADDRSPACE_CAST = 252, |
| 268 | G_BLOCK_ADDR = 253, |
| 269 | G_JUMP_TABLE = 254, |
| 270 | G_DYN_STACKALLOC = 255, |
| 271 | G_STACKSAVE = 256, |
| 272 | G_STACKRESTORE = 257, |
| 273 | G_STRICT_FADD = 258, |
| 274 | G_STRICT_FSUB = 259, |
| 275 | G_STRICT_FMUL = 260, |
| 276 | G_STRICT_FDIV = 261, |
| 277 | G_STRICT_FREM = 262, |
| 278 | G_STRICT_FMA = 263, |
| 279 | G_STRICT_FSQRT = 264, |
| 280 | G_STRICT_FLDEXP = 265, |
| 281 | G_READ_REGISTER = 266, |
| 282 | G_WRITE_REGISTER = 267, |
| 283 | G_MEMCPY = 268, |
| 284 | G_MEMCPY_INLINE = 269, |
| 285 | G_MEMMOVE = 270, |
| 286 | G_MEMSET = 271, |
| 287 | G_BZERO = 272, |
| 288 | G_TRAP = 273, |
| 289 | G_DEBUGTRAP = 274, |
| 290 | G_UBSANTRAP = 275, |
| 291 | G_VECREDUCE_SEQ_FADD = 276, |
| 292 | G_VECREDUCE_SEQ_FMUL = 277, |
| 293 | G_VECREDUCE_FADD = 278, |
| 294 | G_VECREDUCE_FMUL = 279, |
| 295 | G_VECREDUCE_FMAX = 280, |
| 296 | G_VECREDUCE_FMIN = 281, |
| 297 | G_VECREDUCE_FMAXIMUM = 282, |
| 298 | G_VECREDUCE_FMINIMUM = 283, |
| 299 | G_VECREDUCE_ADD = 284, |
| 300 | G_VECREDUCE_MUL = 285, |
| 301 | G_VECREDUCE_AND = 286, |
| 302 | G_VECREDUCE_OR = 287, |
| 303 | G_VECREDUCE_XOR = 288, |
| 304 | G_VECREDUCE_SMAX = 289, |
| 305 | G_VECREDUCE_SMIN = 290, |
| 306 | G_VECREDUCE_UMAX = 291, |
| 307 | G_VECREDUCE_UMIN = 292, |
| 308 | G_SBFX = 293, |
| 309 | G_UBFX = 294, |
| 310 | ADJCALLSTACKDOWN = 295, |
| 311 | ADJCALLSTACKUP = 296, |
| 312 | PseudoAddTPRel_D = 297, |
| 313 | PseudoAddTPRel_W = 298, |
| 314 | PseudoAtomicLoadAdd32 = 299, |
| 315 | PseudoAtomicLoadAnd32 = 300, |
| 316 | PseudoAtomicLoadNand32 = 301, |
| 317 | PseudoAtomicLoadNand64 = 302, |
| 318 | PseudoAtomicLoadOr32 = 303, |
| 319 | PseudoAtomicLoadSub32 = 304, |
| 320 | PseudoAtomicLoadXor32 = 305, |
| 321 | PseudoAtomicStoreD = 306, |
| 322 | PseudoAtomicStoreW = 307, |
| 323 | PseudoAtomicSwap32 = 308, |
| 324 | PseudoBR = 309, |
| 325 | PseudoBRIND = 310, |
| 326 | PseudoB_TAIL = 311, |
| 327 | PseudoCALL = 312, |
| 328 | PseudoCALL36 = 313, |
| 329 | PseudoCALLIndirect = 314, |
| 330 | PseudoCALL_LARGE = 315, |
| 331 | PseudoCALL_MEDIUM = 316, |
| 332 | PseudoCmpXchg32 = 317, |
| 333 | PseudoCmpXchg64 = 318, |
| 334 | PseudoCopyCFR = 319, |
| 335 | PseudoDESC_CALL = 320, |
| 336 | PseudoJIRL_CALL = 321, |
| 337 | PseudoJIRL_TAIL = 322, |
| 338 | PseudoLA_ABS = 323, |
| 339 | PseudoLA_ABS_LARGE = 324, |
| 340 | PseudoLA_GOT = 325, |
| 341 | PseudoLA_GOT_LARGE = 326, |
| 342 | PseudoLA_PCREL = 327, |
| 343 | PseudoLA_PCREL_LARGE = 328, |
| 344 | PseudoLA_TLS_DESC_ABS = 329, |
| 345 | PseudoLA_TLS_DESC_ABS_LARGE = 330, |
| 346 | PseudoLA_TLS_DESC_PC = 331, |
| 347 | PseudoLA_TLS_DESC_PC_LARGE = 332, |
| 348 | PseudoLA_TLS_GD = 333, |
| 349 | PseudoLA_TLS_GD_LARGE = 334, |
| 350 | PseudoLA_TLS_IE = 335, |
| 351 | PseudoLA_TLS_IE_LARGE = 336, |
| 352 | PseudoLA_TLS_LD = 337, |
| 353 | PseudoLA_TLS_LD_LARGE = 338, |
| 354 | PseudoLA_TLS_LE = 339, |
| 355 | PseudoLD_CFR = 340, |
| 356 | PseudoLI_D = 341, |
| 357 | PseudoLI_W = 342, |
| 358 | PseudoMaskedAtomicLoadAdd32 = 343, |
| 359 | PseudoMaskedAtomicLoadMax32 = 344, |
| 360 | PseudoMaskedAtomicLoadMin32 = 345, |
| 361 | PseudoMaskedAtomicLoadNand32 = 346, |
| 362 | PseudoMaskedAtomicLoadSub32 = 347, |
| 363 | PseudoMaskedAtomicLoadUMax32 = 348, |
| 364 | PseudoMaskedAtomicLoadUMin32 = 349, |
| 365 | PseudoMaskedAtomicSwap32 = 350, |
| 366 | PseudoMaskedCmpXchg32 = 351, |
| 367 | PseudoRET = 352, |
| 368 | PseudoST_CFR = 353, |
| 369 | PseudoTAIL = 354, |
| 370 | PseudoTAIL36 = 355, |
| 371 | PseudoTAILIndirect = 356, |
| 372 | PseudoTAIL_LARGE = 357, |
| 373 | PseudoTAIL_MEDIUM = 358, |
| 374 | PseudoUNIMP = 359, |
| 375 | PseudoVBNZ = 360, |
| 376 | PseudoVBNZ_B = 361, |
| 377 | PseudoVBNZ_D = 362, |
| 378 | PseudoVBNZ_H = 363, |
| 379 | PseudoVBNZ_W = 364, |
| 380 | PseudoVBZ = 365, |
| 381 | PseudoVBZ_B = 366, |
| 382 | PseudoVBZ_D = 367, |
| 383 | PseudoVBZ_H = 368, |
| 384 | PseudoVBZ_W = 369, |
| 385 | PseudoVREPLI_B = 370, |
| 386 | PseudoVREPLI_D = 371, |
| 387 | PseudoVREPLI_H = 372, |
| 388 | PseudoVREPLI_W = 373, |
| 389 | PseudoXVBNZ = 374, |
| 390 | PseudoXVBNZ_B = 375, |
| 391 | PseudoXVBNZ_D = 376, |
| 392 | PseudoXVBNZ_H = 377, |
| 393 | PseudoXVBNZ_W = 378, |
| 394 | PseudoXVBZ = 379, |
| 395 | PseudoXVBZ_B = 380, |
| 396 | PseudoXVBZ_D = 381, |
| 397 | PseudoXVBZ_H = 382, |
| 398 | PseudoXVBZ_W = 383, |
| 399 | PseudoXVINSGR2VR_B = 384, |
| 400 | PseudoXVINSGR2VR_H = 385, |
| 401 | PseudoXVREPLI_B = 386, |
| 402 | PseudoXVREPLI_D = 387, |
| 403 | PseudoXVREPLI_H = 388, |
| 404 | PseudoXVREPLI_W = 389, |
| 405 | RDFCSR = 390, |
| 406 | WRFCSR = 391, |
| 407 | ADC_B = 392, |
| 408 | ADC_D = 393, |
| 409 | ADC_H = 394, |
| 410 | ADC_W = 395, |
| 411 | ADDI_D = 396, |
| 412 | ADDI_W = 397, |
| 413 | ADDU12I_D = 398, |
| 414 | ADDU12I_W = 399, |
| 415 | ADDU16I_D = 400, |
| 416 | ADD_D = 401, |
| 417 | ADD_W = 402, |
| 418 | ALSL_D = 403, |
| 419 | ALSL_W = 404, |
| 420 | ALSL_WU = 405, |
| 421 | AMADD_B = 406, |
| 422 | AMADD_D = 407, |
| 423 | AMADD_H = 408, |
| 424 | AMADD_W = 409, |
| 425 | AMADD__DB_B = 410, |
| 426 | AMADD__DB_D = 411, |
| 427 | AMADD__DB_H = 412, |
| 428 | AMADD__DB_W = 413, |
| 429 | AMAND_D = 414, |
| 430 | AMAND_W = 415, |
| 431 | AMAND__DB_D = 416, |
| 432 | AMAND__DB_W = 417, |
| 433 | AMCAS_B = 418, |
| 434 | AMCAS_D = 419, |
| 435 | AMCAS_H = 420, |
| 436 | AMCAS_W = 421, |
| 437 | AMCAS__DB_B = 422, |
| 438 | AMCAS__DB_D = 423, |
| 439 | AMCAS__DB_H = 424, |
| 440 | AMCAS__DB_W = 425, |
| 441 | AMMAX_D = 426, |
| 442 | AMMAX_DU = 427, |
| 443 | AMMAX_W = 428, |
| 444 | AMMAX_WU = 429, |
| 445 | AMMAX__DB_D = 430, |
| 446 | AMMAX__DB_DU = 431, |
| 447 | AMMAX__DB_W = 432, |
| 448 | AMMAX__DB_WU = 433, |
| 449 | AMMIN_D = 434, |
| 450 | AMMIN_DU = 435, |
| 451 | AMMIN_W = 436, |
| 452 | AMMIN_WU = 437, |
| 453 | AMMIN__DB_D = 438, |
| 454 | AMMIN__DB_DU = 439, |
| 455 | AMMIN__DB_W = 440, |
| 456 | AMMIN__DB_WU = 441, |
| 457 | AMOR_D = 442, |
| 458 | AMOR_W = 443, |
| 459 | AMOR__DB_D = 444, |
| 460 | AMOR__DB_W = 445, |
| 461 | AMSWAP_B = 446, |
| 462 | AMSWAP_D = 447, |
| 463 | AMSWAP_H = 448, |
| 464 | AMSWAP_W = 449, |
| 465 | AMSWAP__DB_B = 450, |
| 466 | AMSWAP__DB_D = 451, |
| 467 | AMSWAP__DB_H = 452, |
| 468 | AMSWAP__DB_W = 453, |
| 469 | AMXOR_D = 454, |
| 470 | AMXOR_W = 455, |
| 471 | AMXOR__DB_D = 456, |
| 472 | AMXOR__DB_W = 457, |
| 473 | AND = 458, |
| 474 | ANDI = 459, |
| 475 | ANDN = 460, |
| 476 | ARMADC_W = 461, |
| 477 | ARMADD_W = 462, |
| 478 | ARMAND_W = 463, |
| 479 | ARMMFFLAG = 464, |
| 480 | ARMMOVE = 465, |
| 481 | ARMMOV_D = 466, |
| 482 | ARMMOV_W = 467, |
| 483 | ARMMTFLAG = 468, |
| 484 | ARMNOT_W = 469, |
| 485 | ARMOR_W = 470, |
| 486 | ARMROTRI_W = 471, |
| 487 | ARMROTR_W = 472, |
| 488 | ARMRRX_W = 473, |
| 489 | ARMSBC_W = 474, |
| 490 | ARMSLLI_W = 475, |
| 491 | ARMSLL_W = 476, |
| 492 | ARMSRAI_W = 477, |
| 493 | ARMSRA_W = 478, |
| 494 | ARMSRLI_W = 479, |
| 495 | ARMSRL_W = 480, |
| 496 | ARMSUB_W = 481, |
| 497 | ARMXOR_W = 482, |
| 498 | ASRTGT_D = 483, |
| 499 | ASRTLE_D = 484, |
| 500 | B = 485, |
| 501 | BCEQZ = 486, |
| 502 | BCNEZ = 487, |
| 503 | BEQ = 488, |
| 504 | BEQZ = 489, |
| 505 | BGE = 490, |
| 506 | BGEU = 491, |
| 507 | BITREV_4B = 492, |
| 508 | BITREV_8B = 493, |
| 509 | BITREV_D = 494, |
| 510 | BITREV_W = 495, |
| 511 | BL = 496, |
| 512 | BLT = 497, |
| 513 | BLTU = 498, |
| 514 | BNE = 499, |
| 515 | BNEZ = 500, |
| 516 | BREAK = 501, |
| 517 | BSTRINS_D = 502, |
| 518 | BSTRINS_W = 503, |
| 519 | BSTRPICK_D = 504, |
| 520 | BSTRPICK_W = 505, |
| 521 | BYTEPICK_D = 506, |
| 522 | BYTEPICK_W = 507, |
| 523 | CACOP = 508, |
| 524 | CLO_D = 509, |
| 525 | CLO_W = 510, |
| 526 | CLZ_D = 511, |
| 527 | CLZ_W = 512, |
| 528 | CPUCFG = 513, |
| 529 | CRCC_W_B_W = 514, |
| 530 | CRCC_W_D_W = 515, |
| 531 | CRCC_W_H_W = 516, |
| 532 | CRCC_W_W_W = 517, |
| 533 | CRC_W_B_W = 518, |
| 534 | CRC_W_D_W = 519, |
| 535 | CRC_W_H_W = 520, |
| 536 | CRC_W_W_W = 521, |
| 537 | CSRRD = 522, |
| 538 | CSRWR = 523, |
| 539 | CSRXCHG = 524, |
| 540 | CTO_D = 525, |
| 541 | CTO_W = 526, |
| 542 | CTZ_D = 527, |
| 543 | CTZ_W = 528, |
| 544 | DBAR = 529, |
| 545 | DBCL = 530, |
| 546 | DIV_D = 531, |
| 547 | DIV_DU = 532, |
| 548 | DIV_W = 533, |
| 549 | DIV_WU = 534, |
| 550 | ERTN = 535, |
| 551 | EXT_W_B = 536, |
| 552 | EXT_W_H = 537, |
| 553 | FABS_D = 538, |
| 554 | FABS_S = 539, |
| 555 | FADD_D = 540, |
| 556 | FADD_S = 541, |
| 557 | FCLASS_D = 542, |
| 558 | FCLASS_S = 543, |
| 559 | FCMP_CAF_D = 544, |
| 560 | FCMP_CAF_S = 545, |
| 561 | FCMP_CEQ_D = 546, |
| 562 | FCMP_CEQ_S = 547, |
| 563 | FCMP_CLE_D = 548, |
| 564 | FCMP_CLE_S = 549, |
| 565 | FCMP_CLT_D = 550, |
| 566 | FCMP_CLT_S = 551, |
| 567 | FCMP_CNE_D = 552, |
| 568 | FCMP_CNE_S = 553, |
| 569 | FCMP_COR_D = 554, |
| 570 | FCMP_COR_S = 555, |
| 571 | FCMP_CUEQ_D = 556, |
| 572 | FCMP_CUEQ_S = 557, |
| 573 | FCMP_CULE_D = 558, |
| 574 | FCMP_CULE_S = 559, |
| 575 | FCMP_CULT_D = 560, |
| 576 | FCMP_CULT_S = 561, |
| 577 | FCMP_CUNE_D = 562, |
| 578 | FCMP_CUNE_S = 563, |
| 579 | FCMP_CUN_D = 564, |
| 580 | FCMP_CUN_S = 565, |
| 581 | FCMP_SAF_D = 566, |
| 582 | FCMP_SAF_S = 567, |
| 583 | FCMP_SEQ_D = 568, |
| 584 | FCMP_SEQ_S = 569, |
| 585 | FCMP_SLE_D = 570, |
| 586 | FCMP_SLE_S = 571, |
| 587 | FCMP_SLT_D = 572, |
| 588 | FCMP_SLT_S = 573, |
| 589 | FCMP_SNE_D = 574, |
| 590 | FCMP_SNE_S = 575, |
| 591 | FCMP_SOR_D = 576, |
| 592 | FCMP_SOR_S = 577, |
| 593 | FCMP_SUEQ_D = 578, |
| 594 | FCMP_SUEQ_S = 579, |
| 595 | FCMP_SULE_D = 580, |
| 596 | FCMP_SULE_S = 581, |
| 597 | FCMP_SULT_D = 582, |
| 598 | FCMP_SULT_S = 583, |
| 599 | FCMP_SUNE_D = 584, |
| 600 | FCMP_SUNE_S = 585, |
| 601 | FCMP_SUN_D = 586, |
| 602 | FCMP_SUN_S = 587, |
| 603 | FCOPYSIGN_D = 588, |
| 604 | FCOPYSIGN_S = 589, |
| 605 | FCVT_D_LD = 590, |
| 606 | FCVT_D_S = 591, |
| 607 | FCVT_LD_D = 592, |
| 608 | FCVT_S_D = 593, |
| 609 | FCVT_UD_D = 594, |
| 610 | FDIV_D = 595, |
| 611 | FDIV_S = 596, |
| 612 | FFINT_D_L = 597, |
| 613 | FFINT_D_W = 598, |
| 614 | FFINT_S_L = 599, |
| 615 | FFINT_S_W = 600, |
| 616 | FLDGT_D = 601, |
| 617 | FLDGT_S = 602, |
| 618 | FLDLE_D = 603, |
| 619 | FLDLE_S = 604, |
| 620 | FLDX_D = 605, |
| 621 | FLDX_S = 606, |
| 622 | FLD_D = 607, |
| 623 | FLD_S = 608, |
| 624 | FLOGB_D = 609, |
| 625 | FLOGB_S = 610, |
| 626 | FMADD_D = 611, |
| 627 | FMADD_S = 612, |
| 628 | FMAXA_D = 613, |
| 629 | FMAXA_S = 614, |
| 630 | FMAX_D = 615, |
| 631 | FMAX_S = 616, |
| 632 | FMINA_D = 617, |
| 633 | FMINA_S = 618, |
| 634 | FMIN_D = 619, |
| 635 | FMIN_S = 620, |
| 636 | FMOV_D = 621, |
| 637 | FMOV_S = 622, |
| 638 | FMSUB_D = 623, |
| 639 | FMSUB_S = 624, |
| 640 | FMUL_D = 625, |
| 641 | FMUL_S = 626, |
| 642 | FNEG_D = 627, |
| 643 | FNEG_S = 628, |
| 644 | FNMADD_D = 629, |
| 645 | FNMADD_S = 630, |
| 646 | FNMSUB_D = 631, |
| 647 | FNMSUB_S = 632, |
| 648 | FRECIPE_D = 633, |
| 649 | FRECIPE_S = 634, |
| 650 | FRECIP_D = 635, |
| 651 | FRECIP_S = 636, |
| 652 | FRINT_D = 637, |
| 653 | FRINT_S = 638, |
| 654 | FRSQRTE_D = 639, |
| 655 | FRSQRTE_S = 640, |
| 656 | FRSQRT_D = 641, |
| 657 | FRSQRT_S = 642, |
| 658 | FSCALEB_D = 643, |
| 659 | FSCALEB_S = 644, |
| 660 | FSEL_xD = 645, |
| 661 | FSEL_xS = 646, |
| 662 | FSQRT_D = 647, |
| 663 | FSQRT_S = 648, |
| 664 | FSTGT_D = 649, |
| 665 | FSTGT_S = 650, |
| 666 | FSTLE_D = 651, |
| 667 | FSTLE_S = 652, |
| 668 | FSTX_D = 653, |
| 669 | FSTX_S = 654, |
| 670 | FST_D = 655, |
| 671 | FST_S = 656, |
| 672 | FSUB_D = 657, |
| 673 | FSUB_S = 658, |
| 674 | FTINTRM_L_D = 659, |
| 675 | FTINTRM_L_S = 660, |
| 676 | FTINTRM_W_D = 661, |
| 677 | FTINTRM_W_S = 662, |
| 678 | FTINTRNE_L_D = 663, |
| 679 | FTINTRNE_L_S = 664, |
| 680 | FTINTRNE_W_D = 665, |
| 681 | FTINTRNE_W_S = 666, |
| 682 | FTINTRP_L_D = 667, |
| 683 | FTINTRP_L_S = 668, |
| 684 | FTINTRP_W_D = 669, |
| 685 | FTINTRP_W_S = 670, |
| 686 | FTINTRZ_L_D = 671, |
| 687 | FTINTRZ_L_S = 672, |
| 688 | FTINTRZ_W_D = 673, |
| 689 | FTINTRZ_W_S = 674, |
| 690 | FTINT_L_D = 675, |
| 691 | FTINT_L_S = 676, |
| 692 | FTINT_W_D = 677, |
| 693 | FTINT_W_S = 678, |
| 694 | GCSRRD = 679, |
| 695 | GCSRWR = 680, |
| 696 | GCSRXCHG = 681, |
| 697 | GTLBFLUSH = 682, |
| 698 | HVCL = 683, |
| 699 | IBAR = 684, |
| 700 | IDLE = 685, |
| 701 | INVTLB = 686, |
| 702 | IOCSRRD_B = 687, |
| 703 | IOCSRRD_D = 688, |
| 704 | IOCSRRD_H = 689, |
| 705 | IOCSRRD_W = 690, |
| 706 | IOCSRWR_B = 691, |
| 707 | IOCSRWR_D = 692, |
| 708 | IOCSRWR_H = 693, |
| 709 | IOCSRWR_W = 694, |
| 710 | JIRL = 695, |
| 711 | JISCR0 = 696, |
| 712 | JISCR1 = 697, |
| 713 | LDDIR = 698, |
| 714 | LDGT_B = 699, |
| 715 | LDGT_D = 700, |
| 716 | LDGT_H = 701, |
| 717 | LDGT_W = 702, |
| 718 | LDLE_B = 703, |
| 719 | LDLE_D = 704, |
| 720 | LDLE_H = 705, |
| 721 | LDLE_W = 706, |
| 722 | LDL_D = 707, |
| 723 | LDL_W = 708, |
| 724 | LDPTE = 709, |
| 725 | LDPTR_D = 710, |
| 726 | LDPTR_W = 711, |
| 727 | LDR_D = 712, |
| 728 | LDR_W = 713, |
| 729 | LDX_B = 714, |
| 730 | LDX_BU = 715, |
| 731 | LDX_D = 716, |
| 732 | LDX_H = 717, |
| 733 | LDX_HU = 718, |
| 734 | LDX_W = 719, |
| 735 | LDX_WU = 720, |
| 736 | LD_B = 721, |
| 737 | LD_BU = 722, |
| 738 | LD_D = 723, |
| 739 | LD_H = 724, |
| 740 | LD_HU = 725, |
| 741 | LD_W = 726, |
| 742 | LD_WU = 727, |
| 743 | LLACQ_D = 728, |
| 744 | LLACQ_W = 729, |
| 745 | LL_D = 730, |
| 746 | LL_W = 731, |
| 747 | LU12I_W = 732, |
| 748 | LU32I_D = 733, |
| 749 | LU52I_D = 734, |
| 750 | MASKEQZ = 735, |
| 751 | MASKNEZ = 736, |
| 752 | MOD_D = 737, |
| 753 | MOD_DU = 738, |
| 754 | MOD_W = 739, |
| 755 | MOD_WU = 740, |
| 756 | MOVCF2FR_xS = 741, |
| 757 | MOVCF2GR = 742, |
| 758 | MOVFCSR2GR = 743, |
| 759 | MOVFR2CF_xS = 744, |
| 760 | MOVFR2GR_D = 745, |
| 761 | MOVFR2GR_S = 746, |
| 762 | MOVFR2GR_S_64 = 747, |
| 763 | MOVFRH2GR_S = 748, |
| 764 | MOVGR2CF = 749, |
| 765 | MOVGR2FCSR = 750, |
| 766 | MOVGR2FRH_W = 751, |
| 767 | MOVGR2FR_D = 752, |
| 768 | MOVGR2FR_W = 753, |
| 769 | MOVGR2FR_W_64 = 754, |
| 770 | MOVGR2SCR = 755, |
| 771 | MOVSCR2GR = 756, |
| 772 | MULH_D = 757, |
| 773 | MULH_DU = 758, |
| 774 | MULH_W = 759, |
| 775 | MULH_WU = 760, |
| 776 | MULW_D_W = 761, |
| 777 | MULW_D_WU = 762, |
| 778 | MUL_D = 763, |
| 779 | MUL_W = 764, |
| 780 | NOR = 765, |
| 781 | OR = 766, |
| 782 | ORI = 767, |
| 783 | ORN = 768, |
| 784 | PCADDI = 769, |
| 785 | PCADDU12I = 770, |
| 786 | PCADDU18I = 771, |
| 787 | PCALAU12I = 772, |
| 788 | PRELD = 773, |
| 789 | PRELDX = 774, |
| 790 | RCRI_B = 775, |
| 791 | RCRI_D = 776, |
| 792 | RCRI_H = 777, |
| 793 | RCRI_W = 778, |
| 794 | RCR_B = 779, |
| 795 | RCR_D = 780, |
| 796 | RCR_H = 781, |
| 797 | RCR_W = 782, |
| 798 | RDTIMEH_W = 783, |
| 799 | RDTIMEL_W = 784, |
| 800 | RDTIME_D = 785, |
| 801 | REVB_2H = 786, |
| 802 | REVB_2W = 787, |
| 803 | REVB_4H = 788, |
| 804 | REVB_D = 789, |
| 805 | REVH_2W = 790, |
| 806 | REVH_D = 791, |
| 807 | ROTRI_B = 792, |
| 808 | ROTRI_D = 793, |
| 809 | ROTRI_H = 794, |
| 810 | ROTRI_W = 795, |
| 811 | ROTR_B = 796, |
| 812 | ROTR_D = 797, |
| 813 | ROTR_H = 798, |
| 814 | ROTR_W = 799, |
| 815 | SBC_B = 800, |
| 816 | SBC_D = 801, |
| 817 | SBC_H = 802, |
| 818 | SBC_W = 803, |
| 819 | SCREL_D = 804, |
| 820 | SCREL_W = 805, |
| 821 | SC_D = 806, |
| 822 | SC_Q = 807, |
| 823 | SC_W = 808, |
| 824 | SETARMJ = 809, |
| 825 | SETX86J = 810, |
| 826 | SETX86LOOPE = 811, |
| 827 | SETX86LOOPNE = 812, |
| 828 | SET_CFR_FALSE = 813, |
| 829 | SET_CFR_TRUE = 814, |
| 830 | SLLI_D = 815, |
| 831 | SLLI_W = 816, |
| 832 | SLL_D = 817, |
| 833 | SLL_W = 818, |
| 834 | SLT = 819, |
| 835 | SLTI = 820, |
| 836 | SLTU = 821, |
| 837 | SLTUI = 822, |
| 838 | SRAI_D = 823, |
| 839 | SRAI_W = 824, |
| 840 | SRA_D = 825, |
| 841 | SRA_W = 826, |
| 842 | SRLI_D = 827, |
| 843 | SRLI_W = 828, |
| 844 | SRL_D = 829, |
| 845 | SRL_W = 830, |
| 846 | STGT_B = 831, |
| 847 | STGT_D = 832, |
| 848 | STGT_H = 833, |
| 849 | STGT_W = 834, |
| 850 | STLE_B = 835, |
| 851 | STLE_D = 836, |
| 852 | STLE_H = 837, |
| 853 | STLE_W = 838, |
| 854 | STL_D = 839, |
| 855 | STL_W = 840, |
| 856 | STPTR_D = 841, |
| 857 | STPTR_W = 842, |
| 858 | STR_D = 843, |
| 859 | STR_W = 844, |
| 860 | STX_B = 845, |
| 861 | STX_D = 846, |
| 862 | STX_H = 847, |
| 863 | STX_W = 848, |
| 864 | ST_B = 849, |
| 865 | ST_D = 850, |
| 866 | ST_H = 851, |
| 867 | ST_W = 852, |
| 868 | SUB_D = 853, |
| 869 | SUB_W = 854, |
| 870 | SYSCALL = 855, |
| 871 | TLBCLR = 856, |
| 872 | TLBFILL = 857, |
| 873 | TLBFLUSH = 858, |
| 874 | TLBRD = 859, |
| 875 | TLBSRCH = 860, |
| 876 | TLBWR = 861, |
| 877 | VABSD_B = 862, |
| 878 | VABSD_BU = 863, |
| 879 | VABSD_D = 864, |
| 880 | VABSD_DU = 865, |
| 881 | VABSD_H = 866, |
| 882 | VABSD_HU = 867, |
| 883 | VABSD_W = 868, |
| 884 | VABSD_WU = 869, |
| 885 | VADDA_B = 870, |
| 886 | VADDA_D = 871, |
| 887 | VADDA_H = 872, |
| 888 | VADDA_W = 873, |
| 889 | VADDI_BU = 874, |
| 890 | VADDI_DU = 875, |
| 891 | VADDI_HU = 876, |
| 892 | VADDI_WU = 877, |
| 893 | VADDWEV_D_W = 878, |
| 894 | VADDWEV_D_WU = 879, |
| 895 | VADDWEV_D_WU_W = 880, |
| 896 | VADDWEV_H_B = 881, |
| 897 | VADDWEV_H_BU = 882, |
| 898 | VADDWEV_H_BU_B = 883, |
| 899 | VADDWEV_Q_D = 884, |
| 900 | VADDWEV_Q_DU = 885, |
| 901 | VADDWEV_Q_DU_D = 886, |
| 902 | VADDWEV_W_H = 887, |
| 903 | VADDWEV_W_HU = 888, |
| 904 | VADDWEV_W_HU_H = 889, |
| 905 | VADDWOD_D_W = 890, |
| 906 | VADDWOD_D_WU = 891, |
| 907 | VADDWOD_D_WU_W = 892, |
| 908 | VADDWOD_H_B = 893, |
| 909 | VADDWOD_H_BU = 894, |
| 910 | VADDWOD_H_BU_B = 895, |
| 911 | VADDWOD_Q_D = 896, |
| 912 | VADDWOD_Q_DU = 897, |
| 913 | VADDWOD_Q_DU_D = 898, |
| 914 | VADDWOD_W_H = 899, |
| 915 | VADDWOD_W_HU = 900, |
| 916 | VADDWOD_W_HU_H = 901, |
| 917 | VADD_B = 902, |
| 918 | VADD_D = 903, |
| 919 | VADD_H = 904, |
| 920 | VADD_Q = 905, |
| 921 | VADD_W = 906, |
| 922 | VANDI_B = 907, |
| 923 | VANDN_V = 908, |
| 924 | VAND_V = 909, |
| 925 | VAVGR_B = 910, |
| 926 | VAVGR_BU = 911, |
| 927 | VAVGR_D = 912, |
| 928 | VAVGR_DU = 913, |
| 929 | VAVGR_H = 914, |
| 930 | VAVGR_HU = 915, |
| 931 | VAVGR_W = 916, |
| 932 | VAVGR_WU = 917, |
| 933 | VAVG_B = 918, |
| 934 | VAVG_BU = 919, |
| 935 | VAVG_D = 920, |
| 936 | VAVG_DU = 921, |
| 937 | VAVG_H = 922, |
| 938 | VAVG_HU = 923, |
| 939 | VAVG_W = 924, |
| 940 | VAVG_WU = 925, |
| 941 | VBITCLRI_B = 926, |
| 942 | VBITCLRI_D = 927, |
| 943 | VBITCLRI_H = 928, |
| 944 | VBITCLRI_W = 929, |
| 945 | VBITCLR_B = 930, |
| 946 | VBITCLR_D = 931, |
| 947 | VBITCLR_H = 932, |
| 948 | VBITCLR_W = 933, |
| 949 | VBITREVI_B = 934, |
| 950 | VBITREVI_D = 935, |
| 951 | VBITREVI_H = 936, |
| 952 | VBITREVI_W = 937, |
| 953 | VBITREV_B = 938, |
| 954 | VBITREV_D = 939, |
| 955 | VBITREV_H = 940, |
| 956 | VBITREV_W = 941, |
| 957 | VBITSELI_B = 942, |
| 958 | VBITSEL_V = 943, |
| 959 | VBITSETI_B = 944, |
| 960 | VBITSETI_D = 945, |
| 961 | VBITSETI_H = 946, |
| 962 | VBITSETI_W = 947, |
| 963 | VBITSET_B = 948, |
| 964 | VBITSET_D = 949, |
| 965 | VBITSET_H = 950, |
| 966 | VBITSET_W = 951, |
| 967 | VBSLL_V = 952, |
| 968 | VBSRL_V = 953, |
| 969 | VCLO_B = 954, |
| 970 | VCLO_D = 955, |
| 971 | VCLO_H = 956, |
| 972 | VCLO_W = 957, |
| 973 | VCLZ_B = 958, |
| 974 | VCLZ_D = 959, |
| 975 | VCLZ_H = 960, |
| 976 | VCLZ_W = 961, |
| 977 | VDIV_B = 962, |
| 978 | VDIV_BU = 963, |
| 979 | VDIV_D = 964, |
| 980 | VDIV_DU = 965, |
| 981 | VDIV_H = 966, |
| 982 | VDIV_HU = 967, |
| 983 | VDIV_W = 968, |
| 984 | VDIV_WU = 969, |
| 985 | VEXT2XV_DU_BU = 970, |
| 986 | VEXT2XV_DU_HU = 971, |
| 987 | VEXT2XV_DU_WU = 972, |
| 988 | VEXT2XV_D_B = 973, |
| 989 | VEXT2XV_D_H = 974, |
| 990 | VEXT2XV_D_W = 975, |
| 991 | VEXT2XV_HU_BU = 976, |
| 992 | VEXT2XV_H_B = 977, |
| 993 | VEXT2XV_WU_BU = 978, |
| 994 | VEXT2XV_WU_HU = 979, |
| 995 | VEXT2XV_W_B = 980, |
| 996 | VEXT2XV_W_H = 981, |
| 997 | VEXTH_DU_WU = 982, |
| 998 | VEXTH_D_W = 983, |
| 999 | VEXTH_HU_BU = 984, |
| 1000 | VEXTH_H_B = 985, |
| 1001 | VEXTH_QU_DU = 986, |
| 1002 | VEXTH_Q_D = 987, |
| 1003 | VEXTH_WU_HU = 988, |
| 1004 | VEXTH_W_H = 989, |
| 1005 | VEXTL_QU_DU = 990, |
| 1006 | VEXTL_Q_D = 991, |
| 1007 | VEXTRINS_B = 992, |
| 1008 | VEXTRINS_D = 993, |
| 1009 | VEXTRINS_H = 994, |
| 1010 | VEXTRINS_W = 995, |
| 1011 | VFADD_D = 996, |
| 1012 | VFADD_S = 997, |
| 1013 | VFCLASS_D = 998, |
| 1014 | VFCLASS_S = 999, |
| 1015 | VFCMP_CAF_D = 1000, |
| 1016 | VFCMP_CAF_S = 1001, |
| 1017 | VFCMP_CEQ_D = 1002, |
| 1018 | VFCMP_CEQ_S = 1003, |
| 1019 | VFCMP_CLE_D = 1004, |
| 1020 | VFCMP_CLE_S = 1005, |
| 1021 | VFCMP_CLT_D = 1006, |
| 1022 | VFCMP_CLT_S = 1007, |
| 1023 | VFCMP_CNE_D = 1008, |
| 1024 | VFCMP_CNE_S = 1009, |
| 1025 | VFCMP_COR_D = 1010, |
| 1026 | VFCMP_COR_S = 1011, |
| 1027 | VFCMP_CUEQ_D = 1012, |
| 1028 | VFCMP_CUEQ_S = 1013, |
| 1029 | VFCMP_CULE_D = 1014, |
| 1030 | VFCMP_CULE_S = 1015, |
| 1031 | VFCMP_CULT_D = 1016, |
| 1032 | VFCMP_CULT_S = 1017, |
| 1033 | VFCMP_CUNE_D = 1018, |
| 1034 | VFCMP_CUNE_S = 1019, |
| 1035 | VFCMP_CUN_D = 1020, |
| 1036 | VFCMP_CUN_S = 1021, |
| 1037 | VFCMP_SAF_D = 1022, |
| 1038 | VFCMP_SAF_S = 1023, |
| 1039 | VFCMP_SEQ_D = 1024, |
| 1040 | VFCMP_SEQ_S = 1025, |
| 1041 | VFCMP_SLE_D = 1026, |
| 1042 | VFCMP_SLE_S = 1027, |
| 1043 | VFCMP_SLT_D = 1028, |
| 1044 | VFCMP_SLT_S = 1029, |
| 1045 | VFCMP_SNE_D = 1030, |
| 1046 | VFCMP_SNE_S = 1031, |
| 1047 | VFCMP_SOR_D = 1032, |
| 1048 | VFCMP_SOR_S = 1033, |
| 1049 | VFCMP_SUEQ_D = 1034, |
| 1050 | VFCMP_SUEQ_S = 1035, |
| 1051 | VFCMP_SULE_D = 1036, |
| 1052 | VFCMP_SULE_S = 1037, |
| 1053 | VFCMP_SULT_D = 1038, |
| 1054 | VFCMP_SULT_S = 1039, |
| 1055 | VFCMP_SUNE_D = 1040, |
| 1056 | VFCMP_SUNE_S = 1041, |
| 1057 | VFCMP_SUN_D = 1042, |
| 1058 | VFCMP_SUN_S = 1043, |
| 1059 | VFCVTH_D_S = 1044, |
| 1060 | VFCVTH_S_H = 1045, |
| 1061 | VFCVTL_D_S = 1046, |
| 1062 | VFCVTL_S_H = 1047, |
| 1063 | VFCVT_H_S = 1048, |
| 1064 | VFCVT_S_D = 1049, |
| 1065 | VFDIV_D = 1050, |
| 1066 | VFDIV_S = 1051, |
| 1067 | VFFINTH_D_W = 1052, |
| 1068 | VFFINTL_D_W = 1053, |
| 1069 | VFFINT_D_L = 1054, |
| 1070 | VFFINT_D_LU = 1055, |
| 1071 | VFFINT_S_L = 1056, |
| 1072 | VFFINT_S_W = 1057, |
| 1073 | VFFINT_S_WU = 1058, |
| 1074 | VFLOGB_D = 1059, |
| 1075 | VFLOGB_S = 1060, |
| 1076 | VFMADD_D = 1061, |
| 1077 | VFMADD_S = 1062, |
| 1078 | VFMAXA_D = 1063, |
| 1079 | VFMAXA_S = 1064, |
| 1080 | VFMAX_D = 1065, |
| 1081 | VFMAX_S = 1066, |
| 1082 | VFMINA_D = 1067, |
| 1083 | VFMINA_S = 1068, |
| 1084 | VFMIN_D = 1069, |
| 1085 | VFMIN_S = 1070, |
| 1086 | VFMSUB_D = 1071, |
| 1087 | VFMSUB_S = 1072, |
| 1088 | VFMUL_D = 1073, |
| 1089 | VFMUL_S = 1074, |
| 1090 | VFNMADD_D = 1075, |
| 1091 | VFNMADD_S = 1076, |
| 1092 | VFNMSUB_D = 1077, |
| 1093 | VFNMSUB_S = 1078, |
| 1094 | VFRECIPE_D = 1079, |
| 1095 | VFRECIPE_S = 1080, |
| 1096 | VFRECIP_D = 1081, |
| 1097 | VFRECIP_S = 1082, |
| 1098 | VFRINTRM_D = 1083, |
| 1099 | VFRINTRM_S = 1084, |
| 1100 | VFRINTRNE_D = 1085, |
| 1101 | VFRINTRNE_S = 1086, |
| 1102 | VFRINTRP_D = 1087, |
| 1103 | VFRINTRP_S = 1088, |
| 1104 | VFRINTRZ_D = 1089, |
| 1105 | VFRINTRZ_S = 1090, |
| 1106 | VFRINT_D = 1091, |
| 1107 | VFRINT_S = 1092, |
| 1108 | VFRSQRTE_D = 1093, |
| 1109 | VFRSQRTE_S = 1094, |
| 1110 | VFRSQRT_D = 1095, |
| 1111 | VFRSQRT_S = 1096, |
| 1112 | VFRSTPI_B = 1097, |
| 1113 | VFRSTPI_H = 1098, |
| 1114 | VFRSTP_B = 1099, |
| 1115 | VFRSTP_H = 1100, |
| 1116 | VFSQRT_D = 1101, |
| 1117 | VFSQRT_S = 1102, |
| 1118 | VFSUB_D = 1103, |
| 1119 | VFSUB_S = 1104, |
| 1120 | VFTINTH_L_S = 1105, |
| 1121 | VFTINTL_L_S = 1106, |
| 1122 | VFTINTRMH_L_S = 1107, |
| 1123 | VFTINTRML_L_S = 1108, |
| 1124 | VFTINTRM_L_D = 1109, |
| 1125 | VFTINTRM_W_D = 1110, |
| 1126 | VFTINTRM_W_S = 1111, |
| 1127 | VFTINTRNEH_L_S = 1112, |
| 1128 | VFTINTRNEL_L_S = 1113, |
| 1129 | VFTINTRNE_L_D = 1114, |
| 1130 | VFTINTRNE_W_D = 1115, |
| 1131 | VFTINTRNE_W_S = 1116, |
| 1132 | VFTINTRPH_L_S = 1117, |
| 1133 | VFTINTRPL_L_S = 1118, |
| 1134 | VFTINTRP_L_D = 1119, |
| 1135 | VFTINTRP_W_D = 1120, |
| 1136 | VFTINTRP_W_S = 1121, |
| 1137 | VFTINTRZH_L_S = 1122, |
| 1138 | VFTINTRZL_L_S = 1123, |
| 1139 | VFTINTRZ_LU_D = 1124, |
| 1140 | VFTINTRZ_L_D = 1125, |
| 1141 | VFTINTRZ_WU_S = 1126, |
| 1142 | VFTINTRZ_W_D = 1127, |
| 1143 | VFTINTRZ_W_S = 1128, |
| 1144 | VFTINT_LU_D = 1129, |
| 1145 | VFTINT_L_D = 1130, |
| 1146 | VFTINT_WU_S = 1131, |
| 1147 | VFTINT_W_D = 1132, |
| 1148 | VFTINT_W_S = 1133, |
| 1149 | VHADDW_DU_WU = 1134, |
| 1150 | VHADDW_D_W = 1135, |
| 1151 | VHADDW_HU_BU = 1136, |
| 1152 | VHADDW_H_B = 1137, |
| 1153 | VHADDW_QU_DU = 1138, |
| 1154 | VHADDW_Q_D = 1139, |
| 1155 | VHADDW_WU_HU = 1140, |
| 1156 | VHADDW_W_H = 1141, |
| 1157 | VHSUBW_DU_WU = 1142, |
| 1158 | VHSUBW_D_W = 1143, |
| 1159 | VHSUBW_HU_BU = 1144, |
| 1160 | VHSUBW_H_B = 1145, |
| 1161 | VHSUBW_QU_DU = 1146, |
| 1162 | VHSUBW_Q_D = 1147, |
| 1163 | VHSUBW_WU_HU = 1148, |
| 1164 | VHSUBW_W_H = 1149, |
| 1165 | VILVH_B = 1150, |
| 1166 | VILVH_D = 1151, |
| 1167 | VILVH_H = 1152, |
| 1168 | VILVH_W = 1153, |
| 1169 | VILVL_B = 1154, |
| 1170 | VILVL_D = 1155, |
| 1171 | VILVL_H = 1156, |
| 1172 | VILVL_W = 1157, |
| 1173 | VINSGR2VR_B = 1158, |
| 1174 | VINSGR2VR_D = 1159, |
| 1175 | VINSGR2VR_H = 1160, |
| 1176 | VINSGR2VR_W = 1161, |
| 1177 | VLD = 1162, |
| 1178 | VLDI = 1163, |
| 1179 | VLDREPL_B = 1164, |
| 1180 | VLDREPL_D = 1165, |
| 1181 | VLDREPL_H = 1166, |
| 1182 | VLDREPL_W = 1167, |
| 1183 | VLDX = 1168, |
| 1184 | VMADDWEV_D_W = 1169, |
| 1185 | VMADDWEV_D_WU = 1170, |
| 1186 | VMADDWEV_D_WU_W = 1171, |
| 1187 | VMADDWEV_H_B = 1172, |
| 1188 | VMADDWEV_H_BU = 1173, |
| 1189 | VMADDWEV_H_BU_B = 1174, |
| 1190 | VMADDWEV_Q_D = 1175, |
| 1191 | VMADDWEV_Q_DU = 1176, |
| 1192 | VMADDWEV_Q_DU_D = 1177, |
| 1193 | VMADDWEV_W_H = 1178, |
| 1194 | VMADDWEV_W_HU = 1179, |
| 1195 | VMADDWEV_W_HU_H = 1180, |
| 1196 | VMADDWOD_D_W = 1181, |
| 1197 | VMADDWOD_D_WU = 1182, |
| 1198 | VMADDWOD_D_WU_W = 1183, |
| 1199 | VMADDWOD_H_B = 1184, |
| 1200 | VMADDWOD_H_BU = 1185, |
| 1201 | VMADDWOD_H_BU_B = 1186, |
| 1202 | VMADDWOD_Q_D = 1187, |
| 1203 | VMADDWOD_Q_DU = 1188, |
| 1204 | VMADDWOD_Q_DU_D = 1189, |
| 1205 | VMADDWOD_W_H = 1190, |
| 1206 | VMADDWOD_W_HU = 1191, |
| 1207 | VMADDWOD_W_HU_H = 1192, |
| 1208 | VMADD_B = 1193, |
| 1209 | VMADD_D = 1194, |
| 1210 | VMADD_H = 1195, |
| 1211 | VMADD_W = 1196, |
| 1212 | VMAXI_B = 1197, |
| 1213 | VMAXI_BU = 1198, |
| 1214 | VMAXI_D = 1199, |
| 1215 | VMAXI_DU = 1200, |
| 1216 | VMAXI_H = 1201, |
| 1217 | VMAXI_HU = 1202, |
| 1218 | VMAXI_W = 1203, |
| 1219 | VMAXI_WU = 1204, |
| 1220 | VMAX_B = 1205, |
| 1221 | VMAX_BU = 1206, |
| 1222 | VMAX_D = 1207, |
| 1223 | VMAX_DU = 1208, |
| 1224 | VMAX_H = 1209, |
| 1225 | VMAX_HU = 1210, |
| 1226 | VMAX_W = 1211, |
| 1227 | VMAX_WU = 1212, |
| 1228 | VMINI_B = 1213, |
| 1229 | VMINI_BU = 1214, |
| 1230 | VMINI_D = 1215, |
| 1231 | VMINI_DU = 1216, |
| 1232 | VMINI_H = 1217, |
| 1233 | VMINI_HU = 1218, |
| 1234 | VMINI_W = 1219, |
| 1235 | VMINI_WU = 1220, |
| 1236 | VMIN_B = 1221, |
| 1237 | VMIN_BU = 1222, |
| 1238 | VMIN_D = 1223, |
| 1239 | VMIN_DU = 1224, |
| 1240 | VMIN_H = 1225, |
| 1241 | VMIN_HU = 1226, |
| 1242 | VMIN_W = 1227, |
| 1243 | VMIN_WU = 1228, |
| 1244 | VMOD_B = 1229, |
| 1245 | VMOD_BU = 1230, |
| 1246 | VMOD_D = 1231, |
| 1247 | VMOD_DU = 1232, |
| 1248 | VMOD_H = 1233, |
| 1249 | VMOD_HU = 1234, |
| 1250 | VMOD_W = 1235, |
| 1251 | VMOD_WU = 1236, |
| 1252 | VMSKGEZ_B = 1237, |
| 1253 | VMSKLTZ_B = 1238, |
| 1254 | VMSKLTZ_D = 1239, |
| 1255 | VMSKLTZ_H = 1240, |
| 1256 | VMSKLTZ_W = 1241, |
| 1257 | VMSKNZ_B = 1242, |
| 1258 | VMSUB_B = 1243, |
| 1259 | VMSUB_D = 1244, |
| 1260 | VMSUB_H = 1245, |
| 1261 | VMSUB_W = 1246, |
| 1262 | VMUH_B = 1247, |
| 1263 | VMUH_BU = 1248, |
| 1264 | VMUH_D = 1249, |
| 1265 | VMUH_DU = 1250, |
| 1266 | VMUH_H = 1251, |
| 1267 | VMUH_HU = 1252, |
| 1268 | VMUH_W = 1253, |
| 1269 | VMUH_WU = 1254, |
| 1270 | VMULWEV_D_W = 1255, |
| 1271 | VMULWEV_D_WU = 1256, |
| 1272 | VMULWEV_D_WU_W = 1257, |
| 1273 | VMULWEV_H_B = 1258, |
| 1274 | VMULWEV_H_BU = 1259, |
| 1275 | VMULWEV_H_BU_B = 1260, |
| 1276 | VMULWEV_Q_D = 1261, |
| 1277 | VMULWEV_Q_DU = 1262, |
| 1278 | VMULWEV_Q_DU_D = 1263, |
| 1279 | VMULWEV_W_H = 1264, |
| 1280 | VMULWEV_W_HU = 1265, |
| 1281 | VMULWEV_W_HU_H = 1266, |
| 1282 | VMULWOD_D_W = 1267, |
| 1283 | VMULWOD_D_WU = 1268, |
| 1284 | VMULWOD_D_WU_W = 1269, |
| 1285 | VMULWOD_H_B = 1270, |
| 1286 | VMULWOD_H_BU = 1271, |
| 1287 | VMULWOD_H_BU_B = 1272, |
| 1288 | VMULWOD_Q_D = 1273, |
| 1289 | VMULWOD_Q_DU = 1274, |
| 1290 | VMULWOD_Q_DU_D = 1275, |
| 1291 | VMULWOD_W_H = 1276, |
| 1292 | VMULWOD_W_HU = 1277, |
| 1293 | VMULWOD_W_HU_H = 1278, |
| 1294 | VMUL_B = 1279, |
| 1295 | VMUL_D = 1280, |
| 1296 | VMUL_H = 1281, |
| 1297 | VMUL_W = 1282, |
| 1298 | VNEG_B = 1283, |
| 1299 | VNEG_D = 1284, |
| 1300 | VNEG_H = 1285, |
| 1301 | VNEG_W = 1286, |
| 1302 | VNORI_B = 1287, |
| 1303 | VNOR_V = 1288, |
| 1304 | VORI_B = 1289, |
| 1305 | VORN_V = 1290, |
| 1306 | VOR_V = 1291, |
| 1307 | VPACKEV_B = 1292, |
| 1308 | VPACKEV_D = 1293, |
| 1309 | VPACKEV_H = 1294, |
| 1310 | VPACKEV_W = 1295, |
| 1311 | VPACKOD_B = 1296, |
| 1312 | VPACKOD_D = 1297, |
| 1313 | VPACKOD_H = 1298, |
| 1314 | VPACKOD_W = 1299, |
| 1315 | VPCNT_B = 1300, |
| 1316 | VPCNT_D = 1301, |
| 1317 | VPCNT_H = 1302, |
| 1318 | VPCNT_W = 1303, |
| 1319 | VPERMI_W = 1304, |
| 1320 | VPICKEV_B = 1305, |
| 1321 | VPICKEV_D = 1306, |
| 1322 | VPICKEV_H = 1307, |
| 1323 | VPICKEV_W = 1308, |
| 1324 | VPICKOD_B = 1309, |
| 1325 | VPICKOD_D = 1310, |
| 1326 | VPICKOD_H = 1311, |
| 1327 | VPICKOD_W = 1312, |
| 1328 | VPICKVE2GR_B = 1313, |
| 1329 | VPICKVE2GR_BU = 1314, |
| 1330 | VPICKVE2GR_D = 1315, |
| 1331 | VPICKVE2GR_DU = 1316, |
| 1332 | VPICKVE2GR_H = 1317, |
| 1333 | VPICKVE2GR_HU = 1318, |
| 1334 | VPICKVE2GR_W = 1319, |
| 1335 | VPICKVE2GR_WU = 1320, |
| 1336 | VREPLGR2VR_B = 1321, |
| 1337 | VREPLGR2VR_D = 1322, |
| 1338 | VREPLGR2VR_H = 1323, |
| 1339 | VREPLGR2VR_W = 1324, |
| 1340 | VREPLVEI_B = 1325, |
| 1341 | VREPLVEI_D = 1326, |
| 1342 | VREPLVEI_H = 1327, |
| 1343 | VREPLVEI_W = 1328, |
| 1344 | VREPLVE_B = 1329, |
| 1345 | VREPLVE_D = 1330, |
| 1346 | VREPLVE_H = 1331, |
| 1347 | VREPLVE_W = 1332, |
| 1348 | VROTRI_B = 1333, |
| 1349 | VROTRI_D = 1334, |
| 1350 | VROTRI_H = 1335, |
| 1351 | VROTRI_W = 1336, |
| 1352 | VROTR_B = 1337, |
| 1353 | VROTR_D = 1338, |
| 1354 | VROTR_H = 1339, |
| 1355 | VROTR_W = 1340, |
| 1356 | VSADD_B = 1341, |
| 1357 | VSADD_BU = 1342, |
| 1358 | VSADD_D = 1343, |
| 1359 | VSADD_DU = 1344, |
| 1360 | VSADD_H = 1345, |
| 1361 | VSADD_HU = 1346, |
| 1362 | VSADD_W = 1347, |
| 1363 | VSADD_WU = 1348, |
| 1364 | VSAT_B = 1349, |
| 1365 | VSAT_BU = 1350, |
| 1366 | VSAT_D = 1351, |
| 1367 | VSAT_DU = 1352, |
| 1368 | VSAT_H = 1353, |
| 1369 | VSAT_HU = 1354, |
| 1370 | VSAT_W = 1355, |
| 1371 | VSAT_WU = 1356, |
| 1372 | VSEQI_B = 1357, |
| 1373 | VSEQI_D = 1358, |
| 1374 | VSEQI_H = 1359, |
| 1375 | VSEQI_W = 1360, |
| 1376 | VSEQ_B = 1361, |
| 1377 | VSEQ_D = 1362, |
| 1378 | VSEQ_H = 1363, |
| 1379 | VSEQ_W = 1364, |
| 1380 | VSETALLNEZ_B = 1365, |
| 1381 | VSETALLNEZ_D = 1366, |
| 1382 | VSETALLNEZ_H = 1367, |
| 1383 | VSETALLNEZ_W = 1368, |
| 1384 | VSETANYEQZ_B = 1369, |
| 1385 | VSETANYEQZ_D = 1370, |
| 1386 | VSETANYEQZ_H = 1371, |
| 1387 | VSETANYEQZ_W = 1372, |
| 1388 | VSETEQZ_V = 1373, |
| 1389 | VSETNEZ_V = 1374, |
| 1390 | VSHUF4I_B = 1375, |
| 1391 | VSHUF4I_D = 1376, |
| 1392 | VSHUF4I_H = 1377, |
| 1393 | VSHUF4I_W = 1378, |
| 1394 | VSHUF_B = 1379, |
| 1395 | VSHUF_D = 1380, |
| 1396 | VSHUF_H = 1381, |
| 1397 | VSHUF_W = 1382, |
| 1398 | VSIGNCOV_B = 1383, |
| 1399 | VSIGNCOV_D = 1384, |
| 1400 | VSIGNCOV_H = 1385, |
| 1401 | VSIGNCOV_W = 1386, |
| 1402 | VSLEI_B = 1387, |
| 1403 | VSLEI_BU = 1388, |
| 1404 | VSLEI_D = 1389, |
| 1405 | VSLEI_DU = 1390, |
| 1406 | VSLEI_H = 1391, |
| 1407 | VSLEI_HU = 1392, |
| 1408 | VSLEI_W = 1393, |
| 1409 | VSLEI_WU = 1394, |
| 1410 | VSLE_B = 1395, |
| 1411 | VSLE_BU = 1396, |
| 1412 | VSLE_D = 1397, |
| 1413 | VSLE_DU = 1398, |
| 1414 | VSLE_H = 1399, |
| 1415 | VSLE_HU = 1400, |
| 1416 | VSLE_W = 1401, |
| 1417 | VSLE_WU = 1402, |
| 1418 | VSLLI_B = 1403, |
| 1419 | VSLLI_D = 1404, |
| 1420 | VSLLI_H = 1405, |
| 1421 | VSLLI_W = 1406, |
| 1422 | VSLLWIL_DU_WU = 1407, |
| 1423 | VSLLWIL_D_W = 1408, |
| 1424 | VSLLWIL_HU_BU = 1409, |
| 1425 | VSLLWIL_H_B = 1410, |
| 1426 | VSLLWIL_WU_HU = 1411, |
| 1427 | VSLLWIL_W_H = 1412, |
| 1428 | VSLL_B = 1413, |
| 1429 | VSLL_D = 1414, |
| 1430 | VSLL_H = 1415, |
| 1431 | VSLL_W = 1416, |
| 1432 | VSLTI_B = 1417, |
| 1433 | VSLTI_BU = 1418, |
| 1434 | VSLTI_D = 1419, |
| 1435 | VSLTI_DU = 1420, |
| 1436 | VSLTI_H = 1421, |
| 1437 | VSLTI_HU = 1422, |
| 1438 | VSLTI_W = 1423, |
| 1439 | VSLTI_WU = 1424, |
| 1440 | VSLT_B = 1425, |
| 1441 | VSLT_BU = 1426, |
| 1442 | VSLT_D = 1427, |
| 1443 | VSLT_DU = 1428, |
| 1444 | VSLT_H = 1429, |
| 1445 | VSLT_HU = 1430, |
| 1446 | VSLT_W = 1431, |
| 1447 | VSLT_WU = 1432, |
| 1448 | VSRAI_B = 1433, |
| 1449 | VSRAI_D = 1434, |
| 1450 | VSRAI_H = 1435, |
| 1451 | VSRAI_W = 1436, |
| 1452 | VSRANI_B_H = 1437, |
| 1453 | VSRANI_D_Q = 1438, |
| 1454 | VSRANI_H_W = 1439, |
| 1455 | VSRANI_W_D = 1440, |
| 1456 | VSRAN_B_H = 1441, |
| 1457 | VSRAN_H_W = 1442, |
| 1458 | VSRAN_W_D = 1443, |
| 1459 | VSRARI_B = 1444, |
| 1460 | VSRARI_D = 1445, |
| 1461 | VSRARI_H = 1446, |
| 1462 | VSRARI_W = 1447, |
| 1463 | VSRARNI_B_H = 1448, |
| 1464 | VSRARNI_D_Q = 1449, |
| 1465 | VSRARNI_H_W = 1450, |
| 1466 | VSRARNI_W_D = 1451, |
| 1467 | VSRARN_B_H = 1452, |
| 1468 | VSRARN_H_W = 1453, |
| 1469 | VSRARN_W_D = 1454, |
| 1470 | VSRAR_B = 1455, |
| 1471 | VSRAR_D = 1456, |
| 1472 | VSRAR_H = 1457, |
| 1473 | VSRAR_W = 1458, |
| 1474 | VSRA_B = 1459, |
| 1475 | VSRA_D = 1460, |
| 1476 | VSRA_H = 1461, |
| 1477 | VSRA_W = 1462, |
| 1478 | VSRLI_B = 1463, |
| 1479 | VSRLI_D = 1464, |
| 1480 | VSRLI_H = 1465, |
| 1481 | VSRLI_W = 1466, |
| 1482 | VSRLNI_B_H = 1467, |
| 1483 | VSRLNI_D_Q = 1468, |
| 1484 | VSRLNI_H_W = 1469, |
| 1485 | VSRLNI_W_D = 1470, |
| 1486 | VSRLN_B_H = 1471, |
| 1487 | VSRLN_H_W = 1472, |
| 1488 | VSRLN_W_D = 1473, |
| 1489 | VSRLRI_B = 1474, |
| 1490 | VSRLRI_D = 1475, |
| 1491 | VSRLRI_H = 1476, |
| 1492 | VSRLRI_W = 1477, |
| 1493 | VSRLRNI_B_H = 1478, |
| 1494 | VSRLRNI_D_Q = 1479, |
| 1495 | VSRLRNI_H_W = 1480, |
| 1496 | VSRLRNI_W_D = 1481, |
| 1497 | VSRLRN_B_H = 1482, |
| 1498 | VSRLRN_H_W = 1483, |
| 1499 | VSRLRN_W_D = 1484, |
| 1500 | VSRLR_B = 1485, |
| 1501 | VSRLR_D = 1486, |
| 1502 | VSRLR_H = 1487, |
| 1503 | VSRLR_W = 1488, |
| 1504 | VSRL_B = 1489, |
| 1505 | VSRL_D = 1490, |
| 1506 | VSRL_H = 1491, |
| 1507 | VSRL_W = 1492, |
| 1508 | VSSRANI_BU_H = 1493, |
| 1509 | VSSRANI_B_H = 1494, |
| 1510 | VSSRANI_DU_Q = 1495, |
| 1511 | VSSRANI_D_Q = 1496, |
| 1512 | VSSRANI_HU_W = 1497, |
| 1513 | VSSRANI_H_W = 1498, |
| 1514 | VSSRANI_WU_D = 1499, |
| 1515 | VSSRANI_W_D = 1500, |
| 1516 | VSSRAN_BU_H = 1501, |
| 1517 | VSSRAN_B_H = 1502, |
| 1518 | VSSRAN_HU_W = 1503, |
| 1519 | VSSRAN_H_W = 1504, |
| 1520 | VSSRAN_WU_D = 1505, |
| 1521 | VSSRAN_W_D = 1506, |
| 1522 | VSSRARNI_BU_H = 1507, |
| 1523 | VSSRARNI_B_H = 1508, |
| 1524 | VSSRARNI_DU_Q = 1509, |
| 1525 | VSSRARNI_D_Q = 1510, |
| 1526 | VSSRARNI_HU_W = 1511, |
| 1527 | VSSRARNI_H_W = 1512, |
| 1528 | VSSRARNI_WU_D = 1513, |
| 1529 | VSSRARNI_W_D = 1514, |
| 1530 | VSSRARN_BU_H = 1515, |
| 1531 | VSSRARN_B_H = 1516, |
| 1532 | VSSRARN_HU_W = 1517, |
| 1533 | VSSRARN_H_W = 1518, |
| 1534 | VSSRARN_WU_D = 1519, |
| 1535 | VSSRARN_W_D = 1520, |
| 1536 | VSSRLNI_BU_H = 1521, |
| 1537 | VSSRLNI_B_H = 1522, |
| 1538 | VSSRLNI_DU_Q = 1523, |
| 1539 | VSSRLNI_D_Q = 1524, |
| 1540 | VSSRLNI_HU_W = 1525, |
| 1541 | VSSRLNI_H_W = 1526, |
| 1542 | VSSRLNI_WU_D = 1527, |
| 1543 | VSSRLNI_W_D = 1528, |
| 1544 | VSSRLN_BU_H = 1529, |
| 1545 | VSSRLN_B_H = 1530, |
| 1546 | VSSRLN_HU_W = 1531, |
| 1547 | VSSRLN_H_W = 1532, |
| 1548 | VSSRLN_WU_D = 1533, |
| 1549 | VSSRLN_W_D = 1534, |
| 1550 | VSSRLRNI_BU_H = 1535, |
| 1551 | VSSRLRNI_B_H = 1536, |
| 1552 | VSSRLRNI_DU_Q = 1537, |
| 1553 | VSSRLRNI_D_Q = 1538, |
| 1554 | VSSRLRNI_HU_W = 1539, |
| 1555 | VSSRLRNI_H_W = 1540, |
| 1556 | VSSRLRNI_WU_D = 1541, |
| 1557 | VSSRLRNI_W_D = 1542, |
| 1558 | VSSRLRN_BU_H = 1543, |
| 1559 | VSSRLRN_B_H = 1544, |
| 1560 | VSSRLRN_HU_W = 1545, |
| 1561 | VSSRLRN_H_W = 1546, |
| 1562 | VSSRLRN_WU_D = 1547, |
| 1563 | VSSRLRN_W_D = 1548, |
| 1564 | VSSUB_B = 1549, |
| 1565 | VSSUB_BU = 1550, |
| 1566 | VSSUB_D = 1551, |
| 1567 | VSSUB_DU = 1552, |
| 1568 | VSSUB_H = 1553, |
| 1569 | VSSUB_HU = 1554, |
| 1570 | VSSUB_W = 1555, |
| 1571 | VSSUB_WU = 1556, |
| 1572 | VST = 1557, |
| 1573 | VSTELM_B = 1558, |
| 1574 | VSTELM_D = 1559, |
| 1575 | VSTELM_H = 1560, |
| 1576 | VSTELM_W = 1561, |
| 1577 | VSTX = 1562, |
| 1578 | VSUBI_BU = 1563, |
| 1579 | VSUBI_DU = 1564, |
| 1580 | VSUBI_HU = 1565, |
| 1581 | VSUBI_WU = 1566, |
| 1582 | VSUBWEV_D_W = 1567, |
| 1583 | VSUBWEV_D_WU = 1568, |
| 1584 | VSUBWEV_H_B = 1569, |
| 1585 | VSUBWEV_H_BU = 1570, |
| 1586 | VSUBWEV_Q_D = 1571, |
| 1587 | VSUBWEV_Q_DU = 1572, |
| 1588 | VSUBWEV_W_H = 1573, |
| 1589 | VSUBWEV_W_HU = 1574, |
| 1590 | VSUBWOD_D_W = 1575, |
| 1591 | VSUBWOD_D_WU = 1576, |
| 1592 | VSUBWOD_H_B = 1577, |
| 1593 | VSUBWOD_H_BU = 1578, |
| 1594 | VSUBWOD_Q_D = 1579, |
| 1595 | VSUBWOD_Q_DU = 1580, |
| 1596 | VSUBWOD_W_H = 1581, |
| 1597 | VSUBWOD_W_HU = 1582, |
| 1598 | VSUB_B = 1583, |
| 1599 | VSUB_D = 1584, |
| 1600 | VSUB_H = 1585, |
| 1601 | VSUB_Q = 1586, |
| 1602 | VSUB_W = 1587, |
| 1603 | VXORI_B = 1588, |
| 1604 | VXOR_V = 1589, |
| 1605 | X86ADC_B = 1590, |
| 1606 | X86ADC_D = 1591, |
| 1607 | X86ADC_H = 1592, |
| 1608 | X86ADC_W = 1593, |
| 1609 | X86ADD_B = 1594, |
| 1610 | X86ADD_D = 1595, |
| 1611 | X86ADD_DU = 1596, |
| 1612 | X86ADD_H = 1597, |
| 1613 | X86ADD_W = 1598, |
| 1614 | X86ADD_WU = 1599, |
| 1615 | X86AND_B = 1600, |
| 1616 | X86AND_D = 1601, |
| 1617 | X86AND_H = 1602, |
| 1618 | X86AND_W = 1603, |
| 1619 | X86CLRTM = 1604, |
| 1620 | X86DECTOP = 1605, |
| 1621 | X86DEC_B = 1606, |
| 1622 | X86DEC_D = 1607, |
| 1623 | X86DEC_H = 1608, |
| 1624 | X86DEC_W = 1609, |
| 1625 | X86INCTOP = 1610, |
| 1626 | X86INC_B = 1611, |
| 1627 | X86INC_D = 1612, |
| 1628 | X86INC_H = 1613, |
| 1629 | X86INC_W = 1614, |
| 1630 | X86MFFLAG = 1615, |
| 1631 | X86MFTOP = 1616, |
| 1632 | X86MTFLAG = 1617, |
| 1633 | X86MTTOP = 1618, |
| 1634 | X86MUL_B = 1619, |
| 1635 | X86MUL_BU = 1620, |
| 1636 | X86MUL_D = 1621, |
| 1637 | X86MUL_DU = 1622, |
| 1638 | X86MUL_H = 1623, |
| 1639 | X86MUL_HU = 1624, |
| 1640 | X86MUL_W = 1625, |
| 1641 | X86MUL_WU = 1626, |
| 1642 | X86OR_B = 1627, |
| 1643 | X86OR_D = 1628, |
| 1644 | X86OR_H = 1629, |
| 1645 | X86OR_W = 1630, |
| 1646 | X86RCLI_B = 1631, |
| 1647 | X86RCLI_D = 1632, |
| 1648 | X86RCLI_H = 1633, |
| 1649 | X86RCLI_W = 1634, |
| 1650 | X86RCL_B = 1635, |
| 1651 | X86RCL_D = 1636, |
| 1652 | X86RCL_H = 1637, |
| 1653 | X86RCL_W = 1638, |
| 1654 | X86RCRI_B = 1639, |
| 1655 | X86RCRI_D = 1640, |
| 1656 | X86RCRI_H = 1641, |
| 1657 | X86RCRI_W = 1642, |
| 1658 | X86RCR_B = 1643, |
| 1659 | X86RCR_D = 1644, |
| 1660 | X86RCR_H = 1645, |
| 1661 | X86RCR_W = 1646, |
| 1662 | X86ROTLI_B = 1647, |
| 1663 | X86ROTLI_D = 1648, |
| 1664 | X86ROTLI_H = 1649, |
| 1665 | X86ROTLI_W = 1650, |
| 1666 | X86ROTL_B = 1651, |
| 1667 | X86ROTL_D = 1652, |
| 1668 | X86ROTL_H = 1653, |
| 1669 | X86ROTL_W = 1654, |
| 1670 | X86ROTRI_B = 1655, |
| 1671 | X86ROTRI_D = 1656, |
| 1672 | X86ROTRI_H = 1657, |
| 1673 | X86ROTRI_W = 1658, |
| 1674 | X86ROTR_B = 1659, |
| 1675 | X86ROTR_D = 1660, |
| 1676 | X86ROTR_H = 1661, |
| 1677 | X86ROTR_W = 1662, |
| 1678 | X86SBC_B = 1663, |
| 1679 | X86SBC_D = 1664, |
| 1680 | X86SBC_H = 1665, |
| 1681 | X86SBC_W = 1666, |
| 1682 | X86SETTAG = 1667, |
| 1683 | X86SETTM = 1668, |
| 1684 | X86SLLI_B = 1669, |
| 1685 | X86SLLI_D = 1670, |
| 1686 | X86SLLI_H = 1671, |
| 1687 | X86SLLI_W = 1672, |
| 1688 | X86SLL_B = 1673, |
| 1689 | X86SLL_D = 1674, |
| 1690 | X86SLL_H = 1675, |
| 1691 | X86SLL_W = 1676, |
| 1692 | X86SRAI_B = 1677, |
| 1693 | X86SRAI_D = 1678, |
| 1694 | X86SRAI_H = 1679, |
| 1695 | X86SRAI_W = 1680, |
| 1696 | X86SRA_B = 1681, |
| 1697 | X86SRA_D = 1682, |
| 1698 | X86SRA_H = 1683, |
| 1699 | X86SRA_W = 1684, |
| 1700 | X86SRLI_B = 1685, |
| 1701 | X86SRLI_D = 1686, |
| 1702 | X86SRLI_H = 1687, |
| 1703 | X86SRLI_W = 1688, |
| 1704 | X86SRL_B = 1689, |
| 1705 | X86SRL_D = 1690, |
| 1706 | X86SRL_H = 1691, |
| 1707 | X86SRL_W = 1692, |
| 1708 | X86SUB_B = 1693, |
| 1709 | X86SUB_D = 1694, |
| 1710 | X86SUB_DU = 1695, |
| 1711 | X86SUB_H = 1696, |
| 1712 | X86SUB_W = 1697, |
| 1713 | X86SUB_WU = 1698, |
| 1714 | X86XOR_B = 1699, |
| 1715 | X86XOR_D = 1700, |
| 1716 | X86XOR_H = 1701, |
| 1717 | X86XOR_W = 1702, |
| 1718 | XOR = 1703, |
| 1719 | XORI = 1704, |
| 1720 | XVABSD_B = 1705, |
| 1721 | XVABSD_BU = 1706, |
| 1722 | XVABSD_D = 1707, |
| 1723 | XVABSD_DU = 1708, |
| 1724 | XVABSD_H = 1709, |
| 1725 | XVABSD_HU = 1710, |
| 1726 | XVABSD_W = 1711, |
| 1727 | XVABSD_WU = 1712, |
| 1728 | XVADDA_B = 1713, |
| 1729 | XVADDA_D = 1714, |
| 1730 | XVADDA_H = 1715, |
| 1731 | XVADDA_W = 1716, |
| 1732 | XVADDI_BU = 1717, |
| 1733 | XVADDI_DU = 1718, |
| 1734 | XVADDI_HU = 1719, |
| 1735 | XVADDI_WU = 1720, |
| 1736 | XVADDWEV_D_W = 1721, |
| 1737 | XVADDWEV_D_WU = 1722, |
| 1738 | XVADDWEV_D_WU_W = 1723, |
| 1739 | XVADDWEV_H_B = 1724, |
| 1740 | XVADDWEV_H_BU = 1725, |
| 1741 | XVADDWEV_H_BU_B = 1726, |
| 1742 | XVADDWEV_Q_D = 1727, |
| 1743 | XVADDWEV_Q_DU = 1728, |
| 1744 | XVADDWEV_Q_DU_D = 1729, |
| 1745 | XVADDWEV_W_H = 1730, |
| 1746 | XVADDWEV_W_HU = 1731, |
| 1747 | XVADDWEV_W_HU_H = 1732, |
| 1748 | XVADDWOD_D_W = 1733, |
| 1749 | XVADDWOD_D_WU = 1734, |
| 1750 | XVADDWOD_D_WU_W = 1735, |
| 1751 | XVADDWOD_H_B = 1736, |
| 1752 | XVADDWOD_H_BU = 1737, |
| 1753 | XVADDWOD_H_BU_B = 1738, |
| 1754 | XVADDWOD_Q_D = 1739, |
| 1755 | XVADDWOD_Q_DU = 1740, |
| 1756 | XVADDWOD_Q_DU_D = 1741, |
| 1757 | XVADDWOD_W_H = 1742, |
| 1758 | XVADDWOD_W_HU = 1743, |
| 1759 | XVADDWOD_W_HU_H = 1744, |
| 1760 | XVADD_B = 1745, |
| 1761 | XVADD_D = 1746, |
| 1762 | XVADD_H = 1747, |
| 1763 | XVADD_Q = 1748, |
| 1764 | XVADD_W = 1749, |
| 1765 | XVANDI_B = 1750, |
| 1766 | XVANDN_V = 1751, |
| 1767 | XVAND_V = 1752, |
| 1768 | XVAVGR_B = 1753, |
| 1769 | XVAVGR_BU = 1754, |
| 1770 | XVAVGR_D = 1755, |
| 1771 | XVAVGR_DU = 1756, |
| 1772 | XVAVGR_H = 1757, |
| 1773 | XVAVGR_HU = 1758, |
| 1774 | XVAVGR_W = 1759, |
| 1775 | XVAVGR_WU = 1760, |
| 1776 | XVAVG_B = 1761, |
| 1777 | XVAVG_BU = 1762, |
| 1778 | XVAVG_D = 1763, |
| 1779 | XVAVG_DU = 1764, |
| 1780 | XVAVG_H = 1765, |
| 1781 | XVAVG_HU = 1766, |
| 1782 | XVAVG_W = 1767, |
| 1783 | XVAVG_WU = 1768, |
| 1784 | XVBITCLRI_B = 1769, |
| 1785 | XVBITCLRI_D = 1770, |
| 1786 | XVBITCLRI_H = 1771, |
| 1787 | XVBITCLRI_W = 1772, |
| 1788 | XVBITCLR_B = 1773, |
| 1789 | XVBITCLR_D = 1774, |
| 1790 | XVBITCLR_H = 1775, |
| 1791 | XVBITCLR_W = 1776, |
| 1792 | XVBITREVI_B = 1777, |
| 1793 | XVBITREVI_D = 1778, |
| 1794 | XVBITREVI_H = 1779, |
| 1795 | XVBITREVI_W = 1780, |
| 1796 | XVBITREV_B = 1781, |
| 1797 | XVBITREV_D = 1782, |
| 1798 | XVBITREV_H = 1783, |
| 1799 | XVBITREV_W = 1784, |
| 1800 | XVBITSELI_B = 1785, |
| 1801 | XVBITSEL_V = 1786, |
| 1802 | XVBITSETI_B = 1787, |
| 1803 | XVBITSETI_D = 1788, |
| 1804 | XVBITSETI_H = 1789, |
| 1805 | XVBITSETI_W = 1790, |
| 1806 | XVBITSET_B = 1791, |
| 1807 | XVBITSET_D = 1792, |
| 1808 | XVBITSET_H = 1793, |
| 1809 | XVBITSET_W = 1794, |
| 1810 | XVBSLL_V = 1795, |
| 1811 | XVBSRL_V = 1796, |
| 1812 | XVCLO_B = 1797, |
| 1813 | XVCLO_D = 1798, |
| 1814 | XVCLO_H = 1799, |
| 1815 | XVCLO_W = 1800, |
| 1816 | XVCLZ_B = 1801, |
| 1817 | XVCLZ_D = 1802, |
| 1818 | XVCLZ_H = 1803, |
| 1819 | XVCLZ_W = 1804, |
| 1820 | XVDIV_B = 1805, |
| 1821 | XVDIV_BU = 1806, |
| 1822 | XVDIV_D = 1807, |
| 1823 | XVDIV_DU = 1808, |
| 1824 | XVDIV_H = 1809, |
| 1825 | XVDIV_HU = 1810, |
| 1826 | XVDIV_W = 1811, |
| 1827 | XVDIV_WU = 1812, |
| 1828 | XVEXTH_DU_WU = 1813, |
| 1829 | XVEXTH_D_W = 1814, |
| 1830 | XVEXTH_HU_BU = 1815, |
| 1831 | XVEXTH_H_B = 1816, |
| 1832 | XVEXTH_QU_DU = 1817, |
| 1833 | XVEXTH_Q_D = 1818, |
| 1834 | XVEXTH_WU_HU = 1819, |
| 1835 | XVEXTH_W_H = 1820, |
| 1836 | XVEXTL_QU_DU = 1821, |
| 1837 | XVEXTL_Q_D = 1822, |
| 1838 | XVEXTRINS_B = 1823, |
| 1839 | XVEXTRINS_D = 1824, |
| 1840 | XVEXTRINS_H = 1825, |
| 1841 | XVEXTRINS_W = 1826, |
| 1842 | XVFADD_D = 1827, |
| 1843 | XVFADD_S = 1828, |
| 1844 | XVFCLASS_D = 1829, |
| 1845 | XVFCLASS_S = 1830, |
| 1846 | XVFCMP_CAF_D = 1831, |
| 1847 | XVFCMP_CAF_S = 1832, |
| 1848 | XVFCMP_CEQ_D = 1833, |
| 1849 | XVFCMP_CEQ_S = 1834, |
| 1850 | XVFCMP_CLE_D = 1835, |
| 1851 | XVFCMP_CLE_S = 1836, |
| 1852 | XVFCMP_CLT_D = 1837, |
| 1853 | XVFCMP_CLT_S = 1838, |
| 1854 | XVFCMP_CNE_D = 1839, |
| 1855 | XVFCMP_CNE_S = 1840, |
| 1856 | XVFCMP_COR_D = 1841, |
| 1857 | XVFCMP_COR_S = 1842, |
| 1858 | XVFCMP_CUEQ_D = 1843, |
| 1859 | XVFCMP_CUEQ_S = 1844, |
| 1860 | XVFCMP_CULE_D = 1845, |
| 1861 | XVFCMP_CULE_S = 1846, |
| 1862 | XVFCMP_CULT_D = 1847, |
| 1863 | XVFCMP_CULT_S = 1848, |
| 1864 | XVFCMP_CUNE_D = 1849, |
| 1865 | XVFCMP_CUNE_S = 1850, |
| 1866 | XVFCMP_CUN_D = 1851, |
| 1867 | XVFCMP_CUN_S = 1852, |
| 1868 | XVFCMP_SAF_D = 1853, |
| 1869 | XVFCMP_SAF_S = 1854, |
| 1870 | XVFCMP_SEQ_D = 1855, |
| 1871 | XVFCMP_SEQ_S = 1856, |
| 1872 | XVFCMP_SLE_D = 1857, |
| 1873 | XVFCMP_SLE_S = 1858, |
| 1874 | XVFCMP_SLT_D = 1859, |
| 1875 | XVFCMP_SLT_S = 1860, |
| 1876 | XVFCMP_SNE_D = 1861, |
| 1877 | XVFCMP_SNE_S = 1862, |
| 1878 | XVFCMP_SOR_D = 1863, |
| 1879 | XVFCMP_SOR_S = 1864, |
| 1880 | XVFCMP_SUEQ_D = 1865, |
| 1881 | XVFCMP_SUEQ_S = 1866, |
| 1882 | XVFCMP_SULE_D = 1867, |
| 1883 | XVFCMP_SULE_S = 1868, |
| 1884 | XVFCMP_SULT_D = 1869, |
| 1885 | XVFCMP_SULT_S = 1870, |
| 1886 | XVFCMP_SUNE_D = 1871, |
| 1887 | XVFCMP_SUNE_S = 1872, |
| 1888 | XVFCMP_SUN_D = 1873, |
| 1889 | XVFCMP_SUN_S = 1874, |
| 1890 | XVFCVTH_D_S = 1875, |
| 1891 | XVFCVTH_S_H = 1876, |
| 1892 | XVFCVTL_D_S = 1877, |
| 1893 | XVFCVTL_S_H = 1878, |
| 1894 | XVFCVT_H_S = 1879, |
| 1895 | XVFCVT_S_D = 1880, |
| 1896 | XVFDIV_D = 1881, |
| 1897 | XVFDIV_S = 1882, |
| 1898 | XVFFINTH_D_W = 1883, |
| 1899 | XVFFINTL_D_W = 1884, |
| 1900 | XVFFINT_D_L = 1885, |
| 1901 | XVFFINT_D_LU = 1886, |
| 1902 | XVFFINT_S_L = 1887, |
| 1903 | XVFFINT_S_W = 1888, |
| 1904 | XVFFINT_S_WU = 1889, |
| 1905 | XVFLOGB_D = 1890, |
| 1906 | XVFLOGB_S = 1891, |
| 1907 | XVFMADD_D = 1892, |
| 1908 | XVFMADD_S = 1893, |
| 1909 | XVFMAXA_D = 1894, |
| 1910 | XVFMAXA_S = 1895, |
| 1911 | XVFMAX_D = 1896, |
| 1912 | XVFMAX_S = 1897, |
| 1913 | XVFMINA_D = 1898, |
| 1914 | XVFMINA_S = 1899, |
| 1915 | XVFMIN_D = 1900, |
| 1916 | XVFMIN_S = 1901, |
| 1917 | XVFMSUB_D = 1902, |
| 1918 | XVFMSUB_S = 1903, |
| 1919 | XVFMUL_D = 1904, |
| 1920 | XVFMUL_S = 1905, |
| 1921 | XVFNMADD_D = 1906, |
| 1922 | XVFNMADD_S = 1907, |
| 1923 | XVFNMSUB_D = 1908, |
| 1924 | XVFNMSUB_S = 1909, |
| 1925 | XVFRECIPE_D = 1910, |
| 1926 | XVFRECIPE_S = 1911, |
| 1927 | XVFRECIP_D = 1912, |
| 1928 | XVFRECIP_S = 1913, |
| 1929 | XVFRINTRM_D = 1914, |
| 1930 | XVFRINTRM_S = 1915, |
| 1931 | XVFRINTRNE_D = 1916, |
| 1932 | XVFRINTRNE_S = 1917, |
| 1933 | XVFRINTRP_D = 1918, |
| 1934 | XVFRINTRP_S = 1919, |
| 1935 | XVFRINTRZ_D = 1920, |
| 1936 | XVFRINTRZ_S = 1921, |
| 1937 | XVFRINT_D = 1922, |
| 1938 | XVFRINT_S = 1923, |
| 1939 | XVFRSQRTE_D = 1924, |
| 1940 | XVFRSQRTE_S = 1925, |
| 1941 | XVFRSQRT_D = 1926, |
| 1942 | XVFRSQRT_S = 1927, |
| 1943 | XVFRSTPI_B = 1928, |
| 1944 | XVFRSTPI_H = 1929, |
| 1945 | XVFRSTP_B = 1930, |
| 1946 | XVFRSTP_H = 1931, |
| 1947 | XVFSQRT_D = 1932, |
| 1948 | XVFSQRT_S = 1933, |
| 1949 | XVFSUB_D = 1934, |
| 1950 | XVFSUB_S = 1935, |
| 1951 | XVFTINTH_L_S = 1936, |
| 1952 | XVFTINTL_L_S = 1937, |
| 1953 | XVFTINTRMH_L_S = 1938, |
| 1954 | XVFTINTRML_L_S = 1939, |
| 1955 | XVFTINTRM_L_D = 1940, |
| 1956 | XVFTINTRM_W_D = 1941, |
| 1957 | XVFTINTRM_W_S = 1942, |
| 1958 | XVFTINTRNEH_L_S = 1943, |
| 1959 | XVFTINTRNEL_L_S = 1944, |
| 1960 | XVFTINTRNE_L_D = 1945, |
| 1961 | XVFTINTRNE_W_D = 1946, |
| 1962 | XVFTINTRNE_W_S = 1947, |
| 1963 | XVFTINTRPH_L_S = 1948, |
| 1964 | XVFTINTRPL_L_S = 1949, |
| 1965 | XVFTINTRP_L_D = 1950, |
| 1966 | XVFTINTRP_W_D = 1951, |
| 1967 | XVFTINTRP_W_S = 1952, |
| 1968 | XVFTINTRZH_L_S = 1953, |
| 1969 | XVFTINTRZL_L_S = 1954, |
| 1970 | XVFTINTRZ_LU_D = 1955, |
| 1971 | XVFTINTRZ_L_D = 1956, |
| 1972 | XVFTINTRZ_WU_S = 1957, |
| 1973 | XVFTINTRZ_W_D = 1958, |
| 1974 | XVFTINTRZ_W_S = 1959, |
| 1975 | XVFTINT_LU_D = 1960, |
| 1976 | XVFTINT_L_D = 1961, |
| 1977 | XVFTINT_WU_S = 1962, |
| 1978 | XVFTINT_W_D = 1963, |
| 1979 | XVFTINT_W_S = 1964, |
| 1980 | XVHADDW_DU_WU = 1965, |
| 1981 | XVHADDW_D_W = 1966, |
| 1982 | XVHADDW_HU_BU = 1967, |
| 1983 | XVHADDW_H_B = 1968, |
| 1984 | XVHADDW_QU_DU = 1969, |
| 1985 | XVHADDW_Q_D = 1970, |
| 1986 | XVHADDW_WU_HU = 1971, |
| 1987 | XVHADDW_W_H = 1972, |
| 1988 | XVHSELI_D = 1973, |
| 1989 | XVHSUBW_DU_WU = 1974, |
| 1990 | XVHSUBW_D_W = 1975, |
| 1991 | XVHSUBW_HU_BU = 1976, |
| 1992 | XVHSUBW_H_B = 1977, |
| 1993 | XVHSUBW_QU_DU = 1978, |
| 1994 | XVHSUBW_Q_D = 1979, |
| 1995 | XVHSUBW_WU_HU = 1980, |
| 1996 | XVHSUBW_W_H = 1981, |
| 1997 | XVILVH_B = 1982, |
| 1998 | XVILVH_D = 1983, |
| 1999 | XVILVH_H = 1984, |
| 2000 | XVILVH_W = 1985, |
| 2001 | XVILVL_B = 1986, |
| 2002 | XVILVL_D = 1987, |
| 2003 | XVILVL_H = 1988, |
| 2004 | XVILVL_W = 1989, |
| 2005 | XVINSGR2VR_D = 1990, |
| 2006 | XVINSGR2VR_W = 1991, |
| 2007 | XVINSVE0_D = 1992, |
| 2008 | XVINSVE0_W = 1993, |
| 2009 | XVLD = 1994, |
| 2010 | XVLDI = 1995, |
| 2011 | XVLDREPL_B = 1996, |
| 2012 | XVLDREPL_D = 1997, |
| 2013 | XVLDREPL_H = 1998, |
| 2014 | XVLDREPL_W = 1999, |
| 2015 | XVLDX = 2000, |
| 2016 | XVMADDWEV_D_W = 2001, |
| 2017 | XVMADDWEV_D_WU = 2002, |
| 2018 | XVMADDWEV_D_WU_W = 2003, |
| 2019 | XVMADDWEV_H_B = 2004, |
| 2020 | XVMADDWEV_H_BU = 2005, |
| 2021 | XVMADDWEV_H_BU_B = 2006, |
| 2022 | XVMADDWEV_Q_D = 2007, |
| 2023 | XVMADDWEV_Q_DU = 2008, |
| 2024 | XVMADDWEV_Q_DU_D = 2009, |
| 2025 | XVMADDWEV_W_H = 2010, |
| 2026 | XVMADDWEV_W_HU = 2011, |
| 2027 | XVMADDWEV_W_HU_H = 2012, |
| 2028 | XVMADDWOD_D_W = 2013, |
| 2029 | XVMADDWOD_D_WU = 2014, |
| 2030 | XVMADDWOD_D_WU_W = 2015, |
| 2031 | XVMADDWOD_H_B = 2016, |
| 2032 | XVMADDWOD_H_BU = 2017, |
| 2033 | XVMADDWOD_H_BU_B = 2018, |
| 2034 | XVMADDWOD_Q_D = 2019, |
| 2035 | XVMADDWOD_Q_DU = 2020, |
| 2036 | XVMADDWOD_Q_DU_D = 2021, |
| 2037 | XVMADDWOD_W_H = 2022, |
| 2038 | XVMADDWOD_W_HU = 2023, |
| 2039 | XVMADDWOD_W_HU_H = 2024, |
| 2040 | XVMADD_B = 2025, |
| 2041 | XVMADD_D = 2026, |
| 2042 | XVMADD_H = 2027, |
| 2043 | XVMADD_W = 2028, |
| 2044 | XVMAXI_B = 2029, |
| 2045 | XVMAXI_BU = 2030, |
| 2046 | XVMAXI_D = 2031, |
| 2047 | XVMAXI_DU = 2032, |
| 2048 | XVMAXI_H = 2033, |
| 2049 | XVMAXI_HU = 2034, |
| 2050 | XVMAXI_W = 2035, |
| 2051 | XVMAXI_WU = 2036, |
| 2052 | XVMAX_B = 2037, |
| 2053 | XVMAX_BU = 2038, |
| 2054 | XVMAX_D = 2039, |
| 2055 | XVMAX_DU = 2040, |
| 2056 | XVMAX_H = 2041, |
| 2057 | XVMAX_HU = 2042, |
| 2058 | XVMAX_W = 2043, |
| 2059 | XVMAX_WU = 2044, |
| 2060 | XVMINI_B = 2045, |
| 2061 | XVMINI_BU = 2046, |
| 2062 | XVMINI_D = 2047, |
| 2063 | XVMINI_DU = 2048, |
| 2064 | XVMINI_H = 2049, |
| 2065 | XVMINI_HU = 2050, |
| 2066 | XVMINI_W = 2051, |
| 2067 | XVMINI_WU = 2052, |
| 2068 | XVMIN_B = 2053, |
| 2069 | XVMIN_BU = 2054, |
| 2070 | XVMIN_D = 2055, |
| 2071 | XVMIN_DU = 2056, |
| 2072 | XVMIN_H = 2057, |
| 2073 | XVMIN_HU = 2058, |
| 2074 | XVMIN_W = 2059, |
| 2075 | XVMIN_WU = 2060, |
| 2076 | XVMOD_B = 2061, |
| 2077 | XVMOD_BU = 2062, |
| 2078 | XVMOD_D = 2063, |
| 2079 | XVMOD_DU = 2064, |
| 2080 | XVMOD_H = 2065, |
| 2081 | XVMOD_HU = 2066, |
| 2082 | XVMOD_W = 2067, |
| 2083 | XVMOD_WU = 2068, |
| 2084 | XVMSKGEZ_B = 2069, |
| 2085 | XVMSKLTZ_B = 2070, |
| 2086 | XVMSKLTZ_D = 2071, |
| 2087 | XVMSKLTZ_H = 2072, |
| 2088 | XVMSKLTZ_W = 2073, |
| 2089 | XVMSKNZ_B = 2074, |
| 2090 | XVMSUB_B = 2075, |
| 2091 | XVMSUB_D = 2076, |
| 2092 | XVMSUB_H = 2077, |
| 2093 | XVMSUB_W = 2078, |
| 2094 | XVMUH_B = 2079, |
| 2095 | XVMUH_BU = 2080, |
| 2096 | XVMUH_D = 2081, |
| 2097 | XVMUH_DU = 2082, |
| 2098 | XVMUH_H = 2083, |
| 2099 | XVMUH_HU = 2084, |
| 2100 | XVMUH_W = 2085, |
| 2101 | XVMUH_WU = 2086, |
| 2102 | XVMULWEV_D_W = 2087, |
| 2103 | XVMULWEV_D_WU = 2088, |
| 2104 | XVMULWEV_D_WU_W = 2089, |
| 2105 | XVMULWEV_H_B = 2090, |
| 2106 | XVMULWEV_H_BU = 2091, |
| 2107 | XVMULWEV_H_BU_B = 2092, |
| 2108 | XVMULWEV_Q_D = 2093, |
| 2109 | XVMULWEV_Q_DU = 2094, |
| 2110 | XVMULWEV_Q_DU_D = 2095, |
| 2111 | XVMULWEV_W_H = 2096, |
| 2112 | XVMULWEV_W_HU = 2097, |
| 2113 | XVMULWEV_W_HU_H = 2098, |
| 2114 | XVMULWOD_D_W = 2099, |
| 2115 | XVMULWOD_D_WU = 2100, |
| 2116 | XVMULWOD_D_WU_W = 2101, |
| 2117 | XVMULWOD_H_B = 2102, |
| 2118 | XVMULWOD_H_BU = 2103, |
| 2119 | XVMULWOD_H_BU_B = 2104, |
| 2120 | XVMULWOD_Q_D = 2105, |
| 2121 | XVMULWOD_Q_DU = 2106, |
| 2122 | XVMULWOD_Q_DU_D = 2107, |
| 2123 | XVMULWOD_W_H = 2108, |
| 2124 | XVMULWOD_W_HU = 2109, |
| 2125 | XVMULWOD_W_HU_H = 2110, |
| 2126 | XVMUL_B = 2111, |
| 2127 | XVMUL_D = 2112, |
| 2128 | XVMUL_H = 2113, |
| 2129 | XVMUL_W = 2114, |
| 2130 | XVNEG_B = 2115, |
| 2131 | XVNEG_D = 2116, |
| 2132 | XVNEG_H = 2117, |
| 2133 | XVNEG_W = 2118, |
| 2134 | XVNORI_B = 2119, |
| 2135 | XVNOR_V = 2120, |
| 2136 | XVORI_B = 2121, |
| 2137 | XVORN_V = 2122, |
| 2138 | XVOR_V = 2123, |
| 2139 | XVPACKEV_B = 2124, |
| 2140 | XVPACKEV_D = 2125, |
| 2141 | XVPACKEV_H = 2126, |
| 2142 | XVPACKEV_W = 2127, |
| 2143 | XVPACKOD_B = 2128, |
| 2144 | XVPACKOD_D = 2129, |
| 2145 | XVPACKOD_H = 2130, |
| 2146 | XVPACKOD_W = 2131, |
| 2147 | XVPCNT_B = 2132, |
| 2148 | XVPCNT_D = 2133, |
| 2149 | XVPCNT_H = 2134, |
| 2150 | XVPCNT_W = 2135, |
| 2151 | XVPERMI_D = 2136, |
| 2152 | XVPERMI_Q = 2137, |
| 2153 | XVPERMI_W = 2138, |
| 2154 | XVPERM_W = 2139, |
| 2155 | XVPICKEV_B = 2140, |
| 2156 | XVPICKEV_D = 2141, |
| 2157 | XVPICKEV_H = 2142, |
| 2158 | XVPICKEV_W = 2143, |
| 2159 | XVPICKOD_B = 2144, |
| 2160 | XVPICKOD_D = 2145, |
| 2161 | XVPICKOD_H = 2146, |
| 2162 | XVPICKOD_W = 2147, |
| 2163 | XVPICKVE2GR_D = 2148, |
| 2164 | XVPICKVE2GR_DU = 2149, |
| 2165 | XVPICKVE2GR_W = 2150, |
| 2166 | XVPICKVE2GR_WU = 2151, |
| 2167 | XVPICKVE_D = 2152, |
| 2168 | XVPICKVE_W = 2153, |
| 2169 | XVREPL128VEI_B = 2154, |
| 2170 | XVREPL128VEI_D = 2155, |
| 2171 | XVREPL128VEI_H = 2156, |
| 2172 | XVREPL128VEI_W = 2157, |
| 2173 | XVREPLGR2VR_B = 2158, |
| 2174 | XVREPLGR2VR_D = 2159, |
| 2175 | XVREPLGR2VR_H = 2160, |
| 2176 | XVREPLGR2VR_W = 2161, |
| 2177 | XVREPLVE0_B = 2162, |
| 2178 | XVREPLVE0_D = 2163, |
| 2179 | XVREPLVE0_H = 2164, |
| 2180 | XVREPLVE0_Q = 2165, |
| 2181 | XVREPLVE0_W = 2166, |
| 2182 | XVREPLVE_B = 2167, |
| 2183 | XVREPLVE_D = 2168, |
| 2184 | XVREPLVE_H = 2169, |
| 2185 | XVREPLVE_W = 2170, |
| 2186 | XVROTRI_B = 2171, |
| 2187 | XVROTRI_D = 2172, |
| 2188 | XVROTRI_H = 2173, |
| 2189 | XVROTRI_W = 2174, |
| 2190 | XVROTR_B = 2175, |
| 2191 | XVROTR_D = 2176, |
| 2192 | XVROTR_H = 2177, |
| 2193 | XVROTR_W = 2178, |
| 2194 | XVSADD_B = 2179, |
| 2195 | XVSADD_BU = 2180, |
| 2196 | XVSADD_D = 2181, |
| 2197 | XVSADD_DU = 2182, |
| 2198 | XVSADD_H = 2183, |
| 2199 | XVSADD_HU = 2184, |
| 2200 | XVSADD_W = 2185, |
| 2201 | XVSADD_WU = 2186, |
| 2202 | XVSAT_B = 2187, |
| 2203 | XVSAT_BU = 2188, |
| 2204 | XVSAT_D = 2189, |
| 2205 | XVSAT_DU = 2190, |
| 2206 | XVSAT_H = 2191, |
| 2207 | XVSAT_HU = 2192, |
| 2208 | XVSAT_W = 2193, |
| 2209 | XVSAT_WU = 2194, |
| 2210 | XVSEQI_B = 2195, |
| 2211 | XVSEQI_D = 2196, |
| 2212 | XVSEQI_H = 2197, |
| 2213 | XVSEQI_W = 2198, |
| 2214 | XVSEQ_B = 2199, |
| 2215 | XVSEQ_D = 2200, |
| 2216 | XVSEQ_H = 2201, |
| 2217 | XVSEQ_W = 2202, |
| 2218 | XVSETALLNEZ_B = 2203, |
| 2219 | XVSETALLNEZ_D = 2204, |
| 2220 | XVSETALLNEZ_H = 2205, |
| 2221 | XVSETALLNEZ_W = 2206, |
| 2222 | XVSETANYEQZ_B = 2207, |
| 2223 | XVSETANYEQZ_D = 2208, |
| 2224 | XVSETANYEQZ_H = 2209, |
| 2225 | XVSETANYEQZ_W = 2210, |
| 2226 | XVSETEQZ_V = 2211, |
| 2227 | XVSETNEZ_V = 2212, |
| 2228 | XVSHUF4I_B = 2213, |
| 2229 | XVSHUF4I_D = 2214, |
| 2230 | XVSHUF4I_H = 2215, |
| 2231 | XVSHUF4I_W = 2216, |
| 2232 | XVSHUF_B = 2217, |
| 2233 | XVSHUF_D = 2218, |
| 2234 | XVSHUF_H = 2219, |
| 2235 | XVSHUF_W = 2220, |
| 2236 | XVSIGNCOV_B = 2221, |
| 2237 | XVSIGNCOV_D = 2222, |
| 2238 | XVSIGNCOV_H = 2223, |
| 2239 | XVSIGNCOV_W = 2224, |
| 2240 | XVSLEI_B = 2225, |
| 2241 | XVSLEI_BU = 2226, |
| 2242 | XVSLEI_D = 2227, |
| 2243 | XVSLEI_DU = 2228, |
| 2244 | XVSLEI_H = 2229, |
| 2245 | XVSLEI_HU = 2230, |
| 2246 | XVSLEI_W = 2231, |
| 2247 | XVSLEI_WU = 2232, |
| 2248 | XVSLE_B = 2233, |
| 2249 | XVSLE_BU = 2234, |
| 2250 | XVSLE_D = 2235, |
| 2251 | XVSLE_DU = 2236, |
| 2252 | XVSLE_H = 2237, |
| 2253 | XVSLE_HU = 2238, |
| 2254 | XVSLE_W = 2239, |
| 2255 | XVSLE_WU = 2240, |
| 2256 | XVSLLI_B = 2241, |
| 2257 | XVSLLI_D = 2242, |
| 2258 | XVSLLI_H = 2243, |
| 2259 | XVSLLI_W = 2244, |
| 2260 | XVSLLWIL_DU_WU = 2245, |
| 2261 | XVSLLWIL_D_W = 2246, |
| 2262 | XVSLLWIL_HU_BU = 2247, |
| 2263 | XVSLLWIL_H_B = 2248, |
| 2264 | XVSLLWIL_WU_HU = 2249, |
| 2265 | XVSLLWIL_W_H = 2250, |
| 2266 | XVSLL_B = 2251, |
| 2267 | XVSLL_D = 2252, |
| 2268 | XVSLL_H = 2253, |
| 2269 | XVSLL_W = 2254, |
| 2270 | XVSLTI_B = 2255, |
| 2271 | XVSLTI_BU = 2256, |
| 2272 | XVSLTI_D = 2257, |
| 2273 | XVSLTI_DU = 2258, |
| 2274 | XVSLTI_H = 2259, |
| 2275 | XVSLTI_HU = 2260, |
| 2276 | XVSLTI_W = 2261, |
| 2277 | XVSLTI_WU = 2262, |
| 2278 | XVSLT_B = 2263, |
| 2279 | XVSLT_BU = 2264, |
| 2280 | XVSLT_D = 2265, |
| 2281 | XVSLT_DU = 2266, |
| 2282 | XVSLT_H = 2267, |
| 2283 | XVSLT_HU = 2268, |
| 2284 | XVSLT_W = 2269, |
| 2285 | XVSLT_WU = 2270, |
| 2286 | XVSRAI_B = 2271, |
| 2287 | XVSRAI_D = 2272, |
| 2288 | XVSRAI_H = 2273, |
| 2289 | XVSRAI_W = 2274, |
| 2290 | XVSRANI_B_H = 2275, |
| 2291 | XVSRANI_D_Q = 2276, |
| 2292 | XVSRANI_H_W = 2277, |
| 2293 | XVSRANI_W_D = 2278, |
| 2294 | XVSRAN_B_H = 2279, |
| 2295 | XVSRAN_H_W = 2280, |
| 2296 | XVSRAN_W_D = 2281, |
| 2297 | XVSRARI_B = 2282, |
| 2298 | XVSRARI_D = 2283, |
| 2299 | XVSRARI_H = 2284, |
| 2300 | XVSRARI_W = 2285, |
| 2301 | XVSRARNI_B_H = 2286, |
| 2302 | XVSRARNI_D_Q = 2287, |
| 2303 | XVSRARNI_H_W = 2288, |
| 2304 | XVSRARNI_W_D = 2289, |
| 2305 | XVSRARN_B_H = 2290, |
| 2306 | XVSRARN_H_W = 2291, |
| 2307 | XVSRARN_W_D = 2292, |
| 2308 | XVSRAR_B = 2293, |
| 2309 | XVSRAR_D = 2294, |
| 2310 | XVSRAR_H = 2295, |
| 2311 | XVSRAR_W = 2296, |
| 2312 | XVSRA_B = 2297, |
| 2313 | XVSRA_D = 2298, |
| 2314 | XVSRA_H = 2299, |
| 2315 | XVSRA_W = 2300, |
| 2316 | XVSRLI_B = 2301, |
| 2317 | XVSRLI_D = 2302, |
| 2318 | XVSRLI_H = 2303, |
| 2319 | XVSRLI_W = 2304, |
| 2320 | XVSRLNI_B_H = 2305, |
| 2321 | XVSRLNI_D_Q = 2306, |
| 2322 | XVSRLNI_H_W = 2307, |
| 2323 | XVSRLNI_W_D = 2308, |
| 2324 | XVSRLN_B_H = 2309, |
| 2325 | XVSRLN_H_W = 2310, |
| 2326 | XVSRLN_W_D = 2311, |
| 2327 | XVSRLRI_B = 2312, |
| 2328 | XVSRLRI_D = 2313, |
| 2329 | XVSRLRI_H = 2314, |
| 2330 | XVSRLRI_W = 2315, |
| 2331 | XVSRLRNI_B_H = 2316, |
| 2332 | XVSRLRNI_D_Q = 2317, |
| 2333 | XVSRLRNI_H_W = 2318, |
| 2334 | XVSRLRNI_W_D = 2319, |
| 2335 | XVSRLRN_B_H = 2320, |
| 2336 | XVSRLRN_H_W = 2321, |
| 2337 | XVSRLRN_W_D = 2322, |
| 2338 | XVSRLR_B = 2323, |
| 2339 | XVSRLR_D = 2324, |
| 2340 | XVSRLR_H = 2325, |
| 2341 | XVSRLR_W = 2326, |
| 2342 | XVSRL_B = 2327, |
| 2343 | XVSRL_D = 2328, |
| 2344 | XVSRL_H = 2329, |
| 2345 | XVSRL_W = 2330, |
| 2346 | XVSSRANI_BU_H = 2331, |
| 2347 | XVSSRANI_B_H = 2332, |
| 2348 | XVSSRANI_DU_Q = 2333, |
| 2349 | XVSSRANI_D_Q = 2334, |
| 2350 | XVSSRANI_HU_W = 2335, |
| 2351 | XVSSRANI_H_W = 2336, |
| 2352 | XVSSRANI_WU_D = 2337, |
| 2353 | XVSSRANI_W_D = 2338, |
| 2354 | XVSSRAN_BU_H = 2339, |
| 2355 | XVSSRAN_B_H = 2340, |
| 2356 | XVSSRAN_HU_W = 2341, |
| 2357 | XVSSRAN_H_W = 2342, |
| 2358 | XVSSRAN_WU_D = 2343, |
| 2359 | XVSSRAN_W_D = 2344, |
| 2360 | XVSSRARNI_BU_H = 2345, |
| 2361 | XVSSRARNI_B_H = 2346, |
| 2362 | XVSSRARNI_DU_Q = 2347, |
| 2363 | XVSSRARNI_D_Q = 2348, |
| 2364 | XVSSRARNI_HU_W = 2349, |
| 2365 | XVSSRARNI_H_W = 2350, |
| 2366 | XVSSRARNI_WU_D = 2351, |
| 2367 | XVSSRARNI_W_D = 2352, |
| 2368 | XVSSRARN_BU_H = 2353, |
| 2369 | XVSSRARN_B_H = 2354, |
| 2370 | XVSSRARN_HU_W = 2355, |
| 2371 | XVSSRARN_H_W = 2356, |
| 2372 | XVSSRARN_WU_D = 2357, |
| 2373 | XVSSRARN_W_D = 2358, |
| 2374 | XVSSRLNI_BU_H = 2359, |
| 2375 | XVSSRLNI_B_H = 2360, |
| 2376 | XVSSRLNI_DU_Q = 2361, |
| 2377 | XVSSRLNI_D_Q = 2362, |
| 2378 | XVSSRLNI_HU_W = 2363, |
| 2379 | XVSSRLNI_H_W = 2364, |
| 2380 | XVSSRLNI_WU_D = 2365, |
| 2381 | XVSSRLNI_W_D = 2366, |
| 2382 | XVSSRLN_BU_H = 2367, |
| 2383 | XVSSRLN_B_H = 2368, |
| 2384 | XVSSRLN_HU_W = 2369, |
| 2385 | XVSSRLN_H_W = 2370, |
| 2386 | XVSSRLN_WU_D = 2371, |
| 2387 | XVSSRLN_W_D = 2372, |
| 2388 | XVSSRLRNI_BU_H = 2373, |
| 2389 | XVSSRLRNI_B_H = 2374, |
| 2390 | XVSSRLRNI_DU_Q = 2375, |
| 2391 | XVSSRLRNI_D_Q = 2376, |
| 2392 | XVSSRLRNI_HU_W = 2377, |
| 2393 | XVSSRLRNI_H_W = 2378, |
| 2394 | XVSSRLRNI_WU_D = 2379, |
| 2395 | XVSSRLRNI_W_D = 2380, |
| 2396 | XVSSRLRN_BU_H = 2381, |
| 2397 | XVSSRLRN_B_H = 2382, |
| 2398 | XVSSRLRN_HU_W = 2383, |
| 2399 | XVSSRLRN_H_W = 2384, |
| 2400 | XVSSRLRN_WU_D = 2385, |
| 2401 | XVSSRLRN_W_D = 2386, |
| 2402 | XVSSUB_B = 2387, |
| 2403 | XVSSUB_BU = 2388, |
| 2404 | XVSSUB_D = 2389, |
| 2405 | XVSSUB_DU = 2390, |
| 2406 | XVSSUB_H = 2391, |
| 2407 | XVSSUB_HU = 2392, |
| 2408 | XVSSUB_W = 2393, |
| 2409 | XVSSUB_WU = 2394, |
| 2410 | XVST = 2395, |
| 2411 | XVSTELM_B = 2396, |
| 2412 | XVSTELM_D = 2397, |
| 2413 | XVSTELM_H = 2398, |
| 2414 | XVSTELM_W = 2399, |
| 2415 | XVSTX = 2400, |
| 2416 | XVSUBI_BU = 2401, |
| 2417 | XVSUBI_DU = 2402, |
| 2418 | XVSUBI_HU = 2403, |
| 2419 | XVSUBI_WU = 2404, |
| 2420 | XVSUBWEV_D_W = 2405, |
| 2421 | XVSUBWEV_D_WU = 2406, |
| 2422 | XVSUBWEV_H_B = 2407, |
| 2423 | XVSUBWEV_H_BU = 2408, |
| 2424 | XVSUBWEV_Q_D = 2409, |
| 2425 | XVSUBWEV_Q_DU = 2410, |
| 2426 | XVSUBWEV_W_H = 2411, |
| 2427 | XVSUBWEV_W_HU = 2412, |
| 2428 | XVSUBWOD_D_W = 2413, |
| 2429 | XVSUBWOD_D_WU = 2414, |
| 2430 | XVSUBWOD_H_B = 2415, |
| 2431 | XVSUBWOD_H_BU = 2416, |
| 2432 | XVSUBWOD_Q_D = 2417, |
| 2433 | XVSUBWOD_Q_DU = 2418, |
| 2434 | XVSUBWOD_W_H = 2419, |
| 2435 | XVSUBWOD_W_HU = 2420, |
| 2436 | XVSUB_B = 2421, |
| 2437 | XVSUB_D = 2422, |
| 2438 | XVSUB_H = 2423, |
| 2439 | XVSUB_Q = 2424, |
| 2440 | XVSUB_W = 2425, |
| 2441 | XVXORI_B = 2426, |
| 2442 | XVXOR_V = 2427, |
| 2443 | INSTRUCTION_LIST_END = 2428 |
| 2444 | }; |
| 2445 | |
| 2446 | } // end namespace LoongArch |
| 2447 | } // end namespace llvm |
| 2448 | #endif // GET_INSTRINFO_ENUM |
| 2449 | |
| 2450 | #ifdef GET_INSTRINFO_SCHED_ENUM |
| 2451 | #undef GET_INSTRINFO_SCHED_ENUM |
| 2452 | namespace llvm { |
| 2453 | |
| 2454 | namespace LoongArch { |
| 2455 | namespace Sched { |
| 2456 | enum { |
| 2457 | NoInstrModel = 0, |
| 2458 | SCHED_LIST_END = 1 |
| 2459 | }; |
| 2460 | } // end namespace Sched |
| 2461 | } // end namespace LoongArch |
| 2462 | } // end namespace llvm |
| 2463 | #endif // GET_INSTRINFO_SCHED_ENUM |
| 2464 | |
| 2465 | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 2466 | namespace llvm { |
| 2467 | |
| 2468 | struct LoongArchInstrTable { |
| 2469 | MCInstrDesc Insts[2428]; |
| 2470 | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
| 2471 | MCOperandInfo OperandInfo[417]; |
| 2472 | static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); |
| 2473 | MCPhysReg ImplicitOps[17]; |
| 2474 | }; |
| 2475 | |
| 2476 | } // end namespace llvm |
| 2477 | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
| 2478 | |
| 2479 | #ifdef GET_INSTRINFO_MC_DESC |
| 2480 | #undef GET_INSTRINFO_MC_DESC |
| 2481 | namespace llvm { |
| 2482 | |
| 2483 | static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); |
| 2484 | static constexpr unsigned LoongArchImpOpBase = sizeof LoongArchInstrTable::OperandInfo / (sizeof(MCPhysReg)); |
| 2485 | |
| 2486 | extern const LoongArchInstrTable LoongArchDescs = { |
| 2487 | { |
| 2488 | { 2427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2427 = XVXOR_V |
| 2489 | { 2426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2426 = XVXORI_B |
| 2490 | { 2425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2425 = XVSUB_W |
| 2491 | { 2424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2424 = XVSUB_Q |
| 2492 | { 2423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2423 = XVSUB_H |
| 2493 | { 2422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2422 = XVSUB_D |
| 2494 | { 2421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2421 = XVSUB_B |
| 2495 | { 2420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2420 = XVSUBWOD_W_HU |
| 2496 | { 2419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2419 = XVSUBWOD_W_H |
| 2497 | { 2418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2418 = XVSUBWOD_Q_DU |
| 2498 | { 2417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2417 = XVSUBWOD_Q_D |
| 2499 | { 2416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2416 = XVSUBWOD_H_BU |
| 2500 | { 2415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2415 = XVSUBWOD_H_B |
| 2501 | { 2414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2414 = XVSUBWOD_D_WU |
| 2502 | { 2413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2413 = XVSUBWOD_D_W |
| 2503 | { 2412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2412 = XVSUBWEV_W_HU |
| 2504 | { 2411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2411 = XVSUBWEV_W_H |
| 2505 | { 2410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2410 = XVSUBWEV_Q_DU |
| 2506 | { 2409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2409 = XVSUBWEV_Q_D |
| 2507 | { 2408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2408 = XVSUBWEV_H_BU |
| 2508 | { 2407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2407 = XVSUBWEV_H_B |
| 2509 | { 2406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2406 = XVSUBWEV_D_WU |
| 2510 | { 2405, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2405 = XVSUBWEV_D_W |
| 2511 | { 2404, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2404 = XVSUBI_WU |
| 2512 | { 2403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2403 = XVSUBI_HU |
| 2513 | { 2402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2402 = XVSUBI_DU |
| 2514 | { 2401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2401 = XVSUBI_BU |
| 2515 | { 2400, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 400, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2400 = XVSTX |
| 2516 | { 2399, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2399 = XVSTELM_W |
| 2517 | { 2398, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2398 = XVSTELM_H |
| 2518 | { 2397, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2397 = XVSTELM_D |
| 2519 | { 2396, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 413, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2396 = XVSTELM_B |
| 2520 | { 2395, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2395 = XVST |
| 2521 | { 2394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2394 = XVSSUB_WU |
| 2522 | { 2393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2393 = XVSSUB_W |
| 2523 | { 2392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2392 = XVSSUB_HU |
| 2524 | { 2391, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2391 = XVSSUB_H |
| 2525 | { 2390, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2390 = XVSSUB_DU |
| 2526 | { 2389, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2389 = XVSSUB_D |
| 2527 | { 2388, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2388 = XVSSUB_BU |
| 2528 | { 2387, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2387 = XVSSUB_B |
| 2529 | { 2386, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2386 = XVSSRLRN_W_D |
| 2530 | { 2385, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2385 = XVSSRLRN_WU_D |
| 2531 | { 2384, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2384 = XVSSRLRN_H_W |
| 2532 | { 2383, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2383 = XVSSRLRN_HU_W |
| 2533 | { 2382, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2382 = XVSSRLRN_B_H |
| 2534 | { 2381, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2381 = XVSSRLRN_BU_H |
| 2535 | { 2380, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2380 = XVSSRLRNI_W_D |
| 2536 | { 2379, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2379 = XVSSRLRNI_WU_D |
| 2537 | { 2378, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2378 = XVSSRLRNI_H_W |
| 2538 | { 2377, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2377 = XVSSRLRNI_HU_W |
| 2539 | { 2376, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2376 = XVSSRLRNI_D_Q |
| 2540 | { 2375, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2375 = XVSSRLRNI_DU_Q |
| 2541 | { 2374, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2374 = XVSSRLRNI_B_H |
| 2542 | { 2373, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2373 = XVSSRLRNI_BU_H |
| 2543 | { 2372, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2372 = XVSSRLN_W_D |
| 2544 | { 2371, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2371 = XVSSRLN_WU_D |
| 2545 | { 2370, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2370 = XVSSRLN_H_W |
| 2546 | { 2369, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2369 = XVSSRLN_HU_W |
| 2547 | { 2368, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2368 = XVSSRLN_B_H |
| 2548 | { 2367, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2367 = XVSSRLN_BU_H |
| 2549 | { 2366, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2366 = XVSSRLNI_W_D |
| 2550 | { 2365, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2365 = XVSSRLNI_WU_D |
| 2551 | { 2364, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2364 = XVSSRLNI_H_W |
| 2552 | { 2363, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2363 = XVSSRLNI_HU_W |
| 2553 | { 2362, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2362 = XVSSRLNI_D_Q |
| 2554 | { 2361, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2361 = XVSSRLNI_DU_Q |
| 2555 | { 2360, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2360 = XVSSRLNI_B_H |
| 2556 | { 2359, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2359 = XVSSRLNI_BU_H |
| 2557 | { 2358, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2358 = XVSSRARN_W_D |
| 2558 | { 2357, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2357 = XVSSRARN_WU_D |
| 2559 | { 2356, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2356 = XVSSRARN_H_W |
| 2560 | { 2355, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2355 = XVSSRARN_HU_W |
| 2561 | { 2354, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2354 = XVSSRARN_B_H |
| 2562 | { 2353, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2353 = XVSSRARN_BU_H |
| 2563 | { 2352, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2352 = XVSSRARNI_W_D |
| 2564 | { 2351, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2351 = XVSSRARNI_WU_D |
| 2565 | { 2350, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2350 = XVSSRARNI_H_W |
| 2566 | { 2349, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2349 = XVSSRARNI_HU_W |
| 2567 | { 2348, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2348 = XVSSRARNI_D_Q |
| 2568 | { 2347, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2347 = XVSSRARNI_DU_Q |
| 2569 | { 2346, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2346 = XVSSRARNI_B_H |
| 2570 | { 2345, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2345 = XVSSRARNI_BU_H |
| 2571 | { 2344, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2344 = XVSSRAN_W_D |
| 2572 | { 2343, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2343 = XVSSRAN_WU_D |
| 2573 | { 2342, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2342 = XVSSRAN_H_W |
| 2574 | { 2341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2341 = XVSSRAN_HU_W |
| 2575 | { 2340, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2340 = XVSSRAN_B_H |
| 2576 | { 2339, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2339 = XVSSRAN_BU_H |
| 2577 | { 2338, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2338 = XVSSRANI_W_D |
| 2578 | { 2337, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2337 = XVSSRANI_WU_D |
| 2579 | { 2336, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2336 = XVSSRANI_H_W |
| 2580 | { 2335, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2335 = XVSSRANI_HU_W |
| 2581 | { 2334, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2334 = XVSSRANI_D_Q |
| 2582 | { 2333, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2333 = XVSSRANI_DU_Q |
| 2583 | { 2332, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2332 = XVSSRANI_B_H |
| 2584 | { 2331, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2331 = XVSSRANI_BU_H |
| 2585 | { 2330, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2330 = XVSRL_W |
| 2586 | { 2329, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2329 = XVSRL_H |
| 2587 | { 2328, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2328 = XVSRL_D |
| 2588 | { 2327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2327 = XVSRL_B |
| 2589 | { 2326, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2326 = XVSRLR_W |
| 2590 | { 2325, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2325 = XVSRLR_H |
| 2591 | { 2324, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2324 = XVSRLR_D |
| 2592 | { 2323, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2323 = XVSRLR_B |
| 2593 | { 2322, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2322 = XVSRLRN_W_D |
| 2594 | { 2321, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2321 = XVSRLRN_H_W |
| 2595 | { 2320, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2320 = XVSRLRN_B_H |
| 2596 | { 2319, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2319 = XVSRLRNI_W_D |
| 2597 | { 2318, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2318 = XVSRLRNI_H_W |
| 2598 | { 2317, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2317 = XVSRLRNI_D_Q |
| 2599 | { 2316, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2316 = XVSRLRNI_B_H |
| 2600 | { 2315, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2315 = XVSRLRI_W |
| 2601 | { 2314, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2314 = XVSRLRI_H |
| 2602 | { 2313, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2313 = XVSRLRI_D |
| 2603 | { 2312, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2312 = XVSRLRI_B |
| 2604 | { 2311, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2311 = XVSRLN_W_D |
| 2605 | { 2310, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2310 = XVSRLN_H_W |
| 2606 | { 2309, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2309 = XVSRLN_B_H |
| 2607 | { 2308, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2308 = XVSRLNI_W_D |
| 2608 | { 2307, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2307 = XVSRLNI_H_W |
| 2609 | { 2306, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2306 = XVSRLNI_D_Q |
| 2610 | { 2305, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2305 = XVSRLNI_B_H |
| 2611 | { 2304, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2304 = XVSRLI_W |
| 2612 | { 2303, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2303 = XVSRLI_H |
| 2613 | { 2302, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2302 = XVSRLI_D |
| 2614 | { 2301, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2301 = XVSRLI_B |
| 2615 | { 2300, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2300 = XVSRA_W |
| 2616 | { 2299, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2299 = XVSRA_H |
| 2617 | { 2298, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2298 = XVSRA_D |
| 2618 | { 2297, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2297 = XVSRA_B |
| 2619 | { 2296, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2296 = XVSRAR_W |
| 2620 | { 2295, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2295 = XVSRAR_H |
| 2621 | { 2294, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2294 = XVSRAR_D |
| 2622 | { 2293, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2293 = XVSRAR_B |
| 2623 | { 2292, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2292 = XVSRARN_W_D |
| 2624 | { 2291, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2291 = XVSRARN_H_W |
| 2625 | { 2290, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2290 = XVSRARN_B_H |
| 2626 | { 2289, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2289 = XVSRARNI_W_D |
| 2627 | { 2288, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2288 = XVSRARNI_H_W |
| 2628 | { 2287, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2287 = XVSRARNI_D_Q |
| 2629 | { 2286, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2286 = XVSRARNI_B_H |
| 2630 | { 2285, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2285 = XVSRARI_W |
| 2631 | { 2284, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2284 = XVSRARI_H |
| 2632 | { 2283, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2283 = XVSRARI_D |
| 2633 | { 2282, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2282 = XVSRARI_B |
| 2634 | { 2281, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2281 = XVSRAN_W_D |
| 2635 | { 2280, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2280 = XVSRAN_H_W |
| 2636 | { 2279, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2279 = XVSRAN_B_H |
| 2637 | { 2278, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2278 = XVSRANI_W_D |
| 2638 | { 2277, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2277 = XVSRANI_H_W |
| 2639 | { 2276, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2276 = XVSRANI_D_Q |
| 2640 | { 2275, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2275 = XVSRANI_B_H |
| 2641 | { 2274, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2274 = XVSRAI_W |
| 2642 | { 2273, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2273 = XVSRAI_H |
| 2643 | { 2272, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2272 = XVSRAI_D |
| 2644 | { 2271, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2271 = XVSRAI_B |
| 2645 | { 2270, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2270 = XVSLT_WU |
| 2646 | { 2269, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2269 = XVSLT_W |
| 2647 | { 2268, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2268 = XVSLT_HU |
| 2648 | { 2267, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2267 = XVSLT_H |
| 2649 | { 2266, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2266 = XVSLT_DU |
| 2650 | { 2265, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2265 = XVSLT_D |
| 2651 | { 2264, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2264 = XVSLT_BU |
| 2652 | { 2263, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2263 = XVSLT_B |
| 2653 | { 2262, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2262 = XVSLTI_WU |
| 2654 | { 2261, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2261 = XVSLTI_W |
| 2655 | { 2260, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2260 = XVSLTI_HU |
| 2656 | { 2259, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2259 = XVSLTI_H |
| 2657 | { 2258, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2258 = XVSLTI_DU |
| 2658 | { 2257, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2257 = XVSLTI_D |
| 2659 | { 2256, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2256 = XVSLTI_BU |
| 2660 | { 2255, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2255 = XVSLTI_B |
| 2661 | { 2254, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2254 = XVSLL_W |
| 2662 | { 2253, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2253 = XVSLL_H |
| 2663 | { 2252, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2252 = XVSLL_D |
| 2664 | { 2251, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2251 = XVSLL_B |
| 2665 | { 2250, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2250 = XVSLLWIL_W_H |
| 2666 | { 2249, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2249 = XVSLLWIL_WU_HU |
| 2667 | { 2248, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2248 = XVSLLWIL_H_B |
| 2668 | { 2247, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2247 = XVSLLWIL_HU_BU |
| 2669 | { 2246, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2246 = XVSLLWIL_D_W |
| 2670 | { 2245, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2245 = XVSLLWIL_DU_WU |
| 2671 | { 2244, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2244 = XVSLLI_W |
| 2672 | { 2243, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2243 = XVSLLI_H |
| 2673 | { 2242, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2242 = XVSLLI_D |
| 2674 | { 2241, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2241 = XVSLLI_B |
| 2675 | { 2240, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2240 = XVSLE_WU |
| 2676 | { 2239, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2239 = XVSLE_W |
| 2677 | { 2238, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2238 = XVSLE_HU |
| 2678 | { 2237, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2237 = XVSLE_H |
| 2679 | { 2236, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2236 = XVSLE_DU |
| 2680 | { 2235, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2235 = XVSLE_D |
| 2681 | { 2234, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2234 = XVSLE_BU |
| 2682 | { 2233, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2233 = XVSLE_B |
| 2683 | { 2232, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2232 = XVSLEI_WU |
| 2684 | { 2231, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2231 = XVSLEI_W |
| 2685 | { 2230, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2230 = XVSLEI_HU |
| 2686 | { 2229, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2229 = XVSLEI_H |
| 2687 | { 2228, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2228 = XVSLEI_DU |
| 2688 | { 2227, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2227 = XVSLEI_D |
| 2689 | { 2226, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2226 = XVSLEI_BU |
| 2690 | { 2225, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2225 = XVSLEI_B |
| 2691 | { 2224, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2224 = XVSIGNCOV_W |
| 2692 | { 2223, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2223 = XVSIGNCOV_H |
| 2693 | { 2222, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2222 = XVSIGNCOV_D |
| 2694 | { 2221, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2221 = XVSIGNCOV_B |
| 2695 | { 2220, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2220 = XVSHUF_W |
| 2696 | { 2219, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2219 = XVSHUF_H |
| 2697 | { 2218, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2218 = XVSHUF_D |
| 2698 | { 2217, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #2217 = XVSHUF_B |
| 2699 | { 2216, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2216 = XVSHUF4I_W |
| 2700 | { 2215, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2215 = XVSHUF4I_H |
| 2701 | { 2214, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2214 = XVSHUF4I_D |
| 2702 | { 2213, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2213 = XVSHUF4I_B |
| 2703 | { 2212, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2212 = XVSETNEZ_V |
| 2704 | { 2211, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2211 = XVSETEQZ_V |
| 2705 | { 2210, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2210 = XVSETANYEQZ_W |
| 2706 | { 2209, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2209 = XVSETANYEQZ_H |
| 2707 | { 2208, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2208 = XVSETANYEQZ_D |
| 2708 | { 2207, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2207 = XVSETANYEQZ_B |
| 2709 | { 2206, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2206 = XVSETALLNEZ_W |
| 2710 | { 2205, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2205 = XVSETALLNEZ_H |
| 2711 | { 2204, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2204 = XVSETALLNEZ_D |
| 2712 | { 2203, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 411, 0, 0x0ULL }, // Inst #2203 = XVSETALLNEZ_B |
| 2713 | { 2202, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2202 = XVSEQ_W |
| 2714 | { 2201, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2201 = XVSEQ_H |
| 2715 | { 2200, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2200 = XVSEQ_D |
| 2716 | { 2199, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2199 = XVSEQ_B |
| 2717 | { 2198, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2198 = XVSEQI_W |
| 2718 | { 2197, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2197 = XVSEQI_H |
| 2719 | { 2196, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2196 = XVSEQI_D |
| 2720 | { 2195, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2195 = XVSEQI_B |
| 2721 | { 2194, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2194 = XVSAT_WU |
| 2722 | { 2193, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2193 = XVSAT_W |
| 2723 | { 2192, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2192 = XVSAT_HU |
| 2724 | { 2191, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2191 = XVSAT_H |
| 2725 | { 2190, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2190 = XVSAT_DU |
| 2726 | { 2189, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2189 = XVSAT_D |
| 2727 | { 2188, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2188 = XVSAT_BU |
| 2728 | { 2187, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2187 = XVSAT_B |
| 2729 | { 2186, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2186 = XVSADD_WU |
| 2730 | { 2185, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2185 = XVSADD_W |
| 2731 | { 2184, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2184 = XVSADD_HU |
| 2732 | { 2183, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2183 = XVSADD_H |
| 2733 | { 2182, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2182 = XVSADD_DU |
| 2734 | { 2181, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2181 = XVSADD_D |
| 2735 | { 2180, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2180 = XVSADD_BU |
| 2736 | { 2179, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2179 = XVSADD_B |
| 2737 | { 2178, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2178 = XVROTR_W |
| 2738 | { 2177, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2177 = XVROTR_H |
| 2739 | { 2176, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2176 = XVROTR_D |
| 2740 | { 2175, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2175 = XVROTR_B |
| 2741 | { 2174, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2174 = XVROTRI_W |
| 2742 | { 2173, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2173 = XVROTRI_H |
| 2743 | { 2172, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2172 = XVROTRI_D |
| 2744 | { 2171, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2171 = XVROTRI_B |
| 2745 | { 2170, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2170 = XVREPLVE_W |
| 2746 | { 2169, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2169 = XVREPLVE_H |
| 2747 | { 2168, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2168 = XVREPLVE_D |
| 2748 | { 2167, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 408, 0, 0x0ULL }, // Inst #2167 = XVREPLVE_B |
| 2749 | { 2166, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2166 = XVREPLVE0_W |
| 2750 | { 2165, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2165 = XVREPLVE0_Q |
| 2751 | { 2164, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2164 = XVREPLVE0_H |
| 2752 | { 2163, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2163 = XVREPLVE0_D |
| 2753 | { 2162, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2162 = XVREPLVE0_B |
| 2754 | { 2161, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2161 = XVREPLGR2VR_W |
| 2755 | { 2160, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2160 = XVREPLGR2VR_H |
| 2756 | { 2159, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2159 = XVREPLGR2VR_D |
| 2757 | { 2158, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 406, 0, 0x0ULL }, // Inst #2158 = XVREPLGR2VR_B |
| 2758 | { 2157, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2157 = XVREPL128VEI_W |
| 2759 | { 2156, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2156 = XVREPL128VEI_H |
| 2760 | { 2155, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2155 = XVREPL128VEI_D |
| 2761 | { 2154, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2154 = XVREPL128VEI_B |
| 2762 | { 2153, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2153 = XVPICKVE_W |
| 2763 | { 2152, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2152 = XVPICKVE_D |
| 2764 | { 2151, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2151 = XVPICKVE2GR_WU |
| 2765 | { 2150, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2150 = XVPICKVE2GR_W |
| 2766 | { 2149, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2149 = XVPICKVE2GR_DU |
| 2767 | { 2148, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 403, 0, 0x0ULL }, // Inst #2148 = XVPICKVE2GR_D |
| 2768 | { 2147, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2147 = XVPICKOD_W |
| 2769 | { 2146, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2146 = XVPICKOD_H |
| 2770 | { 2145, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2145 = XVPICKOD_D |
| 2771 | { 2144, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2144 = XVPICKOD_B |
| 2772 | { 2143, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2143 = XVPICKEV_W |
| 2773 | { 2142, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2142 = XVPICKEV_H |
| 2774 | { 2141, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2141 = XVPICKEV_D |
| 2775 | { 2140, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2140 = XVPICKEV_B |
| 2776 | { 2139, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2139 = XVPERM_W |
| 2777 | { 2138, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2138 = XVPERMI_W |
| 2778 | { 2137, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #2137 = XVPERMI_Q |
| 2779 | { 2136, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2136 = XVPERMI_D |
| 2780 | { 2135, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2135 = XVPCNT_W |
| 2781 | { 2134, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2134 = XVPCNT_H |
| 2782 | { 2133, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2133 = XVPCNT_D |
| 2783 | { 2132, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2132 = XVPCNT_B |
| 2784 | { 2131, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2131 = XVPACKOD_W |
| 2785 | { 2130, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2130 = XVPACKOD_H |
| 2786 | { 2129, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2129 = XVPACKOD_D |
| 2787 | { 2128, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2128 = XVPACKOD_B |
| 2788 | { 2127, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2127 = XVPACKEV_W |
| 2789 | { 2126, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2126 = XVPACKEV_H |
| 2790 | { 2125, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2125 = XVPACKEV_D |
| 2791 | { 2124, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2124 = XVPACKEV_B |
| 2792 | { 2123, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2123 = XVOR_V |
| 2793 | { 2122, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2122 = XVORN_V |
| 2794 | { 2121, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2121 = XVORI_B |
| 2795 | { 2120, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2120 = XVNOR_V |
| 2796 | { 2119, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2119 = XVNORI_B |
| 2797 | { 2118, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2118 = XVNEG_W |
| 2798 | { 2117, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2117 = XVNEG_H |
| 2799 | { 2116, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2116 = XVNEG_D |
| 2800 | { 2115, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2115 = XVNEG_B |
| 2801 | { 2114, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2114 = XVMUL_W |
| 2802 | { 2113, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2113 = XVMUL_H |
| 2803 | { 2112, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2112 = XVMUL_D |
| 2804 | { 2111, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2111 = XVMUL_B |
| 2805 | { 2110, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2110 = XVMULWOD_W_HU_H |
| 2806 | { 2109, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2109 = XVMULWOD_W_HU |
| 2807 | { 2108, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2108 = XVMULWOD_W_H |
| 2808 | { 2107, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2107 = XVMULWOD_Q_DU_D |
| 2809 | { 2106, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2106 = XVMULWOD_Q_DU |
| 2810 | { 2105, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2105 = XVMULWOD_Q_D |
| 2811 | { 2104, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2104 = XVMULWOD_H_BU_B |
| 2812 | { 2103, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2103 = XVMULWOD_H_BU |
| 2813 | { 2102, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2102 = XVMULWOD_H_B |
| 2814 | { 2101, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2101 = XVMULWOD_D_WU_W |
| 2815 | { 2100, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2100 = XVMULWOD_D_WU |
| 2816 | { 2099, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2099 = XVMULWOD_D_W |
| 2817 | { 2098, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2098 = XVMULWEV_W_HU_H |
| 2818 | { 2097, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2097 = XVMULWEV_W_HU |
| 2819 | { 2096, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2096 = XVMULWEV_W_H |
| 2820 | { 2095, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2095 = XVMULWEV_Q_DU_D |
| 2821 | { 2094, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2094 = XVMULWEV_Q_DU |
| 2822 | { 2093, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2093 = XVMULWEV_Q_D |
| 2823 | { 2092, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2092 = XVMULWEV_H_BU_B |
| 2824 | { 2091, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2091 = XVMULWEV_H_BU |
| 2825 | { 2090, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2090 = XVMULWEV_H_B |
| 2826 | { 2089, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2089 = XVMULWEV_D_WU_W |
| 2827 | { 2088, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2088 = XVMULWEV_D_WU |
| 2828 | { 2087, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2087 = XVMULWEV_D_W |
| 2829 | { 2086, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2086 = XVMUH_WU |
| 2830 | { 2085, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2085 = XVMUH_W |
| 2831 | { 2084, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2084 = XVMUH_HU |
| 2832 | { 2083, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2083 = XVMUH_H |
| 2833 | { 2082, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2082 = XVMUH_DU |
| 2834 | { 2081, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2081 = XVMUH_D |
| 2835 | { 2080, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2080 = XVMUH_BU |
| 2836 | { 2079, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2079 = XVMUH_B |
| 2837 | { 2078, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2078 = XVMSUB_W |
| 2838 | { 2077, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2077 = XVMSUB_H |
| 2839 | { 2076, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2076 = XVMSUB_D |
| 2840 | { 2075, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2075 = XVMSUB_B |
| 2841 | { 2074, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2074 = XVMSKNZ_B |
| 2842 | { 2073, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2073 = XVMSKLTZ_W |
| 2843 | { 2072, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2072 = XVMSKLTZ_H |
| 2844 | { 2071, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2071 = XVMSKLTZ_D |
| 2845 | { 2070, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2070 = XVMSKLTZ_B |
| 2846 | { 2069, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #2069 = XVMSKGEZ_B |
| 2847 | { 2068, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2068 = XVMOD_WU |
| 2848 | { 2067, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2067 = XVMOD_W |
| 2849 | { 2066, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2066 = XVMOD_HU |
| 2850 | { 2065, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2065 = XVMOD_H |
| 2851 | { 2064, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2064 = XVMOD_DU |
| 2852 | { 2063, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2063 = XVMOD_D |
| 2853 | { 2062, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2062 = XVMOD_BU |
| 2854 | { 2061, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2061 = XVMOD_B |
| 2855 | { 2060, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2060 = XVMIN_WU |
| 2856 | { 2059, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2059 = XVMIN_W |
| 2857 | { 2058, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2058 = XVMIN_HU |
| 2858 | { 2057, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2057 = XVMIN_H |
| 2859 | { 2056, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2056 = XVMIN_DU |
| 2860 | { 2055, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2055 = XVMIN_D |
| 2861 | { 2054, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2054 = XVMIN_BU |
| 2862 | { 2053, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2053 = XVMIN_B |
| 2863 | { 2052, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2052 = XVMINI_WU |
| 2864 | { 2051, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2051 = XVMINI_W |
| 2865 | { 2050, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2050 = XVMINI_HU |
| 2866 | { 2049, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2049 = XVMINI_H |
| 2867 | { 2048, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2048 = XVMINI_DU |
| 2868 | { 2047, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2047 = XVMINI_D |
| 2869 | { 2046, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2046 = XVMINI_BU |
| 2870 | { 2045, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2045 = XVMINI_B |
| 2871 | { 2044, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2044 = XVMAX_WU |
| 2872 | { 2043, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2043 = XVMAX_W |
| 2873 | { 2042, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2042 = XVMAX_HU |
| 2874 | { 2041, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2041 = XVMAX_H |
| 2875 | { 2040, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2040 = XVMAX_DU |
| 2876 | { 2039, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2039 = XVMAX_D |
| 2877 | { 2038, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2038 = XVMAX_BU |
| 2878 | { 2037, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #2037 = XVMAX_B |
| 2879 | { 2036, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2036 = XVMAXI_WU |
| 2880 | { 2035, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2035 = XVMAXI_W |
| 2881 | { 2034, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2034 = XVMAXI_HU |
| 2882 | { 2033, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2033 = XVMAXI_H |
| 2883 | { 2032, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2032 = XVMAXI_DU |
| 2884 | { 2031, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2031 = XVMAXI_D |
| 2885 | { 2030, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2030 = XVMAXI_BU |
| 2886 | { 2029, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #2029 = XVMAXI_B |
| 2887 | { 2028, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2028 = XVMADD_W |
| 2888 | { 2027, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2027 = XVMADD_H |
| 2889 | { 2026, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2026 = XVMADD_D |
| 2890 | { 2025, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2025 = XVMADD_B |
| 2891 | { 2024, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2024 = XVMADDWOD_W_HU_H |
| 2892 | { 2023, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2023 = XVMADDWOD_W_HU |
| 2893 | { 2022, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2022 = XVMADDWOD_W_H |
| 2894 | { 2021, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2021 = XVMADDWOD_Q_DU_D |
| 2895 | { 2020, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2020 = XVMADDWOD_Q_DU |
| 2896 | { 2019, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2019 = XVMADDWOD_Q_D |
| 2897 | { 2018, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2018 = XVMADDWOD_H_BU_B |
| 2898 | { 2017, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2017 = XVMADDWOD_H_BU |
| 2899 | { 2016, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2016 = XVMADDWOD_H_B |
| 2900 | { 2015, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2015 = XVMADDWOD_D_WU_W |
| 2901 | { 2014, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2014 = XVMADDWOD_D_WU |
| 2902 | { 2013, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2013 = XVMADDWOD_D_W |
| 2903 | { 2012, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2012 = XVMADDWEV_W_HU_H |
| 2904 | { 2011, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2011 = XVMADDWEV_W_HU |
| 2905 | { 2010, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2010 = XVMADDWEV_W_H |
| 2906 | { 2009, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2009 = XVMADDWEV_Q_DU_D |
| 2907 | { 2008, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2008 = XVMADDWEV_Q_DU |
| 2908 | { 2007, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2007 = XVMADDWEV_Q_D |
| 2909 | { 2006, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2006 = XVMADDWEV_H_BU_B |
| 2910 | { 2005, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2005 = XVMADDWEV_H_BU |
| 2911 | { 2004, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2004 = XVMADDWEV_H_B |
| 2912 | { 2003, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2003 = XVMADDWEV_D_WU_W |
| 2913 | { 2002, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2002 = XVMADDWEV_D_WU |
| 2914 | { 2001, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #2001 = XVMADDWEV_D_W |
| 2915 | { 2000, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 400, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #2000 = XVLDX |
| 2916 | { 1999, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1999 = XVLDREPL_W |
| 2917 | { 1998, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1998 = XVLDREPL_H |
| 2918 | { 1997, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1997 = XVLDREPL_D |
| 2919 | { 1996, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1996 = XVLDREPL_B |
| 2920 | { 1995, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0, 0x0ULL }, // Inst #1995 = XVLDI |
| 2921 | { 1994, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 397, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1994 = XVLD |
| 2922 | { 1993, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1993 = XVINSVE0_W |
| 2923 | { 1992, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1992 = XVINSVE0_D |
| 2924 | { 1991, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0, 0x0ULL }, // Inst #1991 = XVINSGR2VR_W |
| 2925 | { 1990, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0, 0x0ULL }, // Inst #1990 = XVINSGR2VR_D |
| 2926 | { 1989, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1989 = XVILVL_W |
| 2927 | { 1988, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1988 = XVILVL_H |
| 2928 | { 1987, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1987 = XVILVL_D |
| 2929 | { 1986, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1986 = XVILVL_B |
| 2930 | { 1985, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1985 = XVILVH_W |
| 2931 | { 1984, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1984 = XVILVH_H |
| 2932 | { 1983, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1983 = XVILVH_D |
| 2933 | { 1982, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1982 = XVILVH_B |
| 2934 | { 1981, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1981 = XVHSUBW_W_H |
| 2935 | { 1980, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1980 = XVHSUBW_WU_HU |
| 2936 | { 1979, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1979 = XVHSUBW_Q_D |
| 2937 | { 1978, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1978 = XVHSUBW_QU_DU |
| 2938 | { 1977, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1977 = XVHSUBW_H_B |
| 2939 | { 1976, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1976 = XVHSUBW_HU_BU |
| 2940 | { 1975, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1975 = XVHSUBW_D_W |
| 2941 | { 1974, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1974 = XVHSUBW_DU_WU |
| 2942 | { 1973, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1973 = XVHSELI_D |
| 2943 | { 1972, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1972 = XVHADDW_W_H |
| 2944 | { 1971, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1971 = XVHADDW_WU_HU |
| 2945 | { 1970, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1970 = XVHADDW_Q_D |
| 2946 | { 1969, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1969 = XVHADDW_QU_DU |
| 2947 | { 1968, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1968 = XVHADDW_H_B |
| 2948 | { 1967, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1967 = XVHADDW_HU_BU |
| 2949 | { 1966, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1966 = XVHADDW_D_W |
| 2950 | { 1965, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1965 = XVHADDW_DU_WU |
| 2951 | { 1964, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1964 = XVFTINT_W_S |
| 2952 | { 1963, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1963 = XVFTINT_W_D |
| 2953 | { 1962, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1962 = XVFTINT_WU_S |
| 2954 | { 1961, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1961 = XVFTINT_L_D |
| 2955 | { 1960, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1960 = XVFTINT_LU_D |
| 2956 | { 1959, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1959 = XVFTINTRZ_W_S |
| 2957 | { 1958, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1958 = XVFTINTRZ_W_D |
| 2958 | { 1957, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1957 = XVFTINTRZ_WU_S |
| 2959 | { 1956, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1956 = XVFTINTRZ_L_D |
| 2960 | { 1955, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1955 = XVFTINTRZ_LU_D |
| 2961 | { 1954, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1954 = XVFTINTRZL_L_S |
| 2962 | { 1953, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1953 = XVFTINTRZH_L_S |
| 2963 | { 1952, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1952 = XVFTINTRP_W_S |
| 2964 | { 1951, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1951 = XVFTINTRP_W_D |
| 2965 | { 1950, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1950 = XVFTINTRP_L_D |
| 2966 | { 1949, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1949 = XVFTINTRPL_L_S |
| 2967 | { 1948, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1948 = XVFTINTRPH_L_S |
| 2968 | { 1947, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1947 = XVFTINTRNE_W_S |
| 2969 | { 1946, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1946 = XVFTINTRNE_W_D |
| 2970 | { 1945, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1945 = XVFTINTRNE_L_D |
| 2971 | { 1944, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1944 = XVFTINTRNEL_L_S |
| 2972 | { 1943, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1943 = XVFTINTRNEH_L_S |
| 2973 | { 1942, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1942 = XVFTINTRM_W_S |
| 2974 | { 1941, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1941 = XVFTINTRM_W_D |
| 2975 | { 1940, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1940 = XVFTINTRM_L_D |
| 2976 | { 1939, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1939 = XVFTINTRML_L_S |
| 2977 | { 1938, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1938 = XVFTINTRMH_L_S |
| 2978 | { 1937, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1937 = XVFTINTL_L_S |
| 2979 | { 1936, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1936 = XVFTINTH_L_S |
| 2980 | { 1935, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1935 = XVFSUB_S |
| 2981 | { 1934, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1934 = XVFSUB_D |
| 2982 | { 1933, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1933 = XVFSQRT_S |
| 2983 | { 1932, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1932 = XVFSQRT_D |
| 2984 | { 1931, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #1931 = XVFRSTP_H |
| 2985 | { 1930, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 393, 0, 0x0ULL }, // Inst #1930 = XVFRSTP_B |
| 2986 | { 1929, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1929 = XVFRSTPI_H |
| 2987 | { 1928, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1928 = XVFRSTPI_B |
| 2988 | { 1927, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1927 = XVFRSQRT_S |
| 2989 | { 1926, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1926 = XVFRSQRT_D |
| 2990 | { 1925, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1925 = XVFRSQRTE_S |
| 2991 | { 1924, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1924 = XVFRSQRTE_D |
| 2992 | { 1923, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1923 = XVFRINT_S |
| 2993 | { 1922, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1922 = XVFRINT_D |
| 2994 | { 1921, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1921 = XVFRINTRZ_S |
| 2995 | { 1920, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1920 = XVFRINTRZ_D |
| 2996 | { 1919, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1919 = XVFRINTRP_S |
| 2997 | { 1918, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1918 = XVFRINTRP_D |
| 2998 | { 1917, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1917 = XVFRINTRNE_S |
| 2999 | { 1916, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1916 = XVFRINTRNE_D |
| 3000 | { 1915, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1915 = XVFRINTRM_S |
| 3001 | { 1914, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1914 = XVFRINTRM_D |
| 3002 | { 1913, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1913 = XVFRECIP_S |
| 3003 | { 1912, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1912 = XVFRECIP_D |
| 3004 | { 1911, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1911 = XVFRECIPE_S |
| 3005 | { 1910, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1910 = XVFRECIPE_D |
| 3006 | { 1909, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1909 = XVFNMSUB_S |
| 3007 | { 1908, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1908 = XVFNMSUB_D |
| 3008 | { 1907, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1907 = XVFNMADD_S |
| 3009 | { 1906, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1906 = XVFNMADD_D |
| 3010 | { 1905, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1905 = XVFMUL_S |
| 3011 | { 1904, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1904 = XVFMUL_D |
| 3012 | { 1903, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1903 = XVFMSUB_S |
| 3013 | { 1902, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1902 = XVFMSUB_D |
| 3014 | { 1901, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1901 = XVFMIN_S |
| 3015 | { 1900, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1900 = XVFMIN_D |
| 3016 | { 1899, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1899 = XVFMINA_S |
| 3017 | { 1898, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1898 = XVFMINA_D |
| 3018 | { 1897, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1897 = XVFMAX_S |
| 3019 | { 1896, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1896 = XVFMAX_D |
| 3020 | { 1895, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1895 = XVFMAXA_S |
| 3021 | { 1894, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1894 = XVFMAXA_D |
| 3022 | { 1893, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1893 = XVFMADD_S |
| 3023 | { 1892, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1892 = XVFMADD_D |
| 3024 | { 1891, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1891 = XVFLOGB_S |
| 3025 | { 1890, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1890 = XVFLOGB_D |
| 3026 | { 1889, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1889 = XVFFINT_S_WU |
| 3027 | { 1888, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1888 = XVFFINT_S_W |
| 3028 | { 1887, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1887 = XVFFINT_S_L |
| 3029 | { 1886, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1886 = XVFFINT_D_LU |
| 3030 | { 1885, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1885 = XVFFINT_D_L |
| 3031 | { 1884, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1884 = XVFFINTL_D_W |
| 3032 | { 1883, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1883 = XVFFINTH_D_W |
| 3033 | { 1882, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1882 = XVFDIV_S |
| 3034 | { 1881, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1881 = XVFDIV_D |
| 3035 | { 1880, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1880 = XVFCVT_S_D |
| 3036 | { 1879, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1879 = XVFCVT_H_S |
| 3037 | { 1878, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1878 = XVFCVTL_S_H |
| 3038 | { 1877, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1877 = XVFCVTL_D_S |
| 3039 | { 1876, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1876 = XVFCVTH_S_H |
| 3040 | { 1875, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1875 = XVFCVTH_D_S |
| 3041 | { 1874, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1874 = XVFCMP_SUN_S |
| 3042 | { 1873, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1873 = XVFCMP_SUN_D |
| 3043 | { 1872, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1872 = XVFCMP_SUNE_S |
| 3044 | { 1871, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1871 = XVFCMP_SUNE_D |
| 3045 | { 1870, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1870 = XVFCMP_SULT_S |
| 3046 | { 1869, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1869 = XVFCMP_SULT_D |
| 3047 | { 1868, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1868 = XVFCMP_SULE_S |
| 3048 | { 1867, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1867 = XVFCMP_SULE_D |
| 3049 | { 1866, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1866 = XVFCMP_SUEQ_S |
| 3050 | { 1865, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1865 = XVFCMP_SUEQ_D |
| 3051 | { 1864, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1864 = XVFCMP_SOR_S |
| 3052 | { 1863, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1863 = XVFCMP_SOR_D |
| 3053 | { 1862, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1862 = XVFCMP_SNE_S |
| 3054 | { 1861, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1861 = XVFCMP_SNE_D |
| 3055 | { 1860, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1860 = XVFCMP_SLT_S |
| 3056 | { 1859, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1859 = XVFCMP_SLT_D |
| 3057 | { 1858, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1858 = XVFCMP_SLE_S |
| 3058 | { 1857, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1857 = XVFCMP_SLE_D |
| 3059 | { 1856, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1856 = XVFCMP_SEQ_S |
| 3060 | { 1855, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1855 = XVFCMP_SEQ_D |
| 3061 | { 1854, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1854 = XVFCMP_SAF_S |
| 3062 | { 1853, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1853 = XVFCMP_SAF_D |
| 3063 | { 1852, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1852 = XVFCMP_CUN_S |
| 3064 | { 1851, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1851 = XVFCMP_CUN_D |
| 3065 | { 1850, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1850 = XVFCMP_CUNE_S |
| 3066 | { 1849, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1849 = XVFCMP_CUNE_D |
| 3067 | { 1848, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1848 = XVFCMP_CULT_S |
| 3068 | { 1847, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1847 = XVFCMP_CULT_D |
| 3069 | { 1846, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1846 = XVFCMP_CULE_S |
| 3070 | { 1845, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1845 = XVFCMP_CULE_D |
| 3071 | { 1844, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1844 = XVFCMP_CUEQ_S |
| 3072 | { 1843, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1843 = XVFCMP_CUEQ_D |
| 3073 | { 1842, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1842 = XVFCMP_COR_S |
| 3074 | { 1841, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1841 = XVFCMP_COR_D |
| 3075 | { 1840, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1840 = XVFCMP_CNE_S |
| 3076 | { 1839, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1839 = XVFCMP_CNE_D |
| 3077 | { 1838, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1838 = XVFCMP_CLT_S |
| 3078 | { 1837, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1837 = XVFCMP_CLT_D |
| 3079 | { 1836, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1836 = XVFCMP_CLE_S |
| 3080 | { 1835, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1835 = XVFCMP_CLE_D |
| 3081 | { 1834, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1834 = XVFCMP_CEQ_S |
| 3082 | { 1833, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1833 = XVFCMP_CEQ_D |
| 3083 | { 1832, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1832 = XVFCMP_CAF_S |
| 3084 | { 1831, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1831 = XVFCMP_CAF_D |
| 3085 | { 1830, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1830 = XVFCLASS_S |
| 3086 | { 1829, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1829 = XVFCLASS_D |
| 3087 | { 1828, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1828 = XVFADD_S |
| 3088 | { 1827, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1827 = XVFADD_D |
| 3089 | { 1826, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1826 = XVEXTRINS_W |
| 3090 | { 1825, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1825 = XVEXTRINS_H |
| 3091 | { 1824, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1824 = XVEXTRINS_D |
| 3092 | { 1823, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1823 = XVEXTRINS_B |
| 3093 | { 1822, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1822 = XVEXTL_Q_D |
| 3094 | { 1821, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1821 = XVEXTL_QU_DU |
| 3095 | { 1820, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1820 = XVEXTH_W_H |
| 3096 | { 1819, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1819 = XVEXTH_WU_HU |
| 3097 | { 1818, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1818 = XVEXTH_Q_D |
| 3098 | { 1817, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1817 = XVEXTH_QU_DU |
| 3099 | { 1816, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1816 = XVEXTH_H_B |
| 3100 | { 1815, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1815 = XVEXTH_HU_BU |
| 3101 | { 1814, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1814 = XVEXTH_D_W |
| 3102 | { 1813, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1813 = XVEXTH_DU_WU |
| 3103 | { 1812, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1812 = XVDIV_WU |
| 3104 | { 1811, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1811 = XVDIV_W |
| 3105 | { 1810, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1810 = XVDIV_HU |
| 3106 | { 1809, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1809 = XVDIV_H |
| 3107 | { 1808, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1808 = XVDIV_DU |
| 3108 | { 1807, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1807 = XVDIV_D |
| 3109 | { 1806, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1806 = XVDIV_BU |
| 3110 | { 1805, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1805 = XVDIV_B |
| 3111 | { 1804, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1804 = XVCLZ_W |
| 3112 | { 1803, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1803 = XVCLZ_H |
| 3113 | { 1802, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1802 = XVCLZ_D |
| 3114 | { 1801, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1801 = XVCLZ_B |
| 3115 | { 1800, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1800 = XVCLO_W |
| 3116 | { 1799, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1799 = XVCLO_H |
| 3117 | { 1798, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1798 = XVCLO_D |
| 3118 | { 1797, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #1797 = XVCLO_B |
| 3119 | { 1796, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1796 = XVBSRL_V |
| 3120 | { 1795, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1795 = XVBSLL_V |
| 3121 | { 1794, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1794 = XVBITSET_W |
| 3122 | { 1793, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1793 = XVBITSET_H |
| 3123 | { 1792, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1792 = XVBITSET_D |
| 3124 | { 1791, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1791 = XVBITSET_B |
| 3125 | { 1790, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1790 = XVBITSETI_W |
| 3126 | { 1789, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1789 = XVBITSETI_H |
| 3127 | { 1788, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1788 = XVBITSETI_D |
| 3128 | { 1787, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1787 = XVBITSETI_B |
| 3129 | { 1786, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 389, 0, 0x0ULL }, // Inst #1786 = XVBITSEL_V |
| 3130 | { 1785, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 385, 0, 0x0ULL }, // Inst #1785 = XVBITSELI_B |
| 3131 | { 1784, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1784 = XVBITREV_W |
| 3132 | { 1783, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1783 = XVBITREV_H |
| 3133 | { 1782, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1782 = XVBITREV_D |
| 3134 | { 1781, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1781 = XVBITREV_B |
| 3135 | { 1780, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1780 = XVBITREVI_W |
| 3136 | { 1779, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1779 = XVBITREVI_H |
| 3137 | { 1778, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1778 = XVBITREVI_D |
| 3138 | { 1777, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1777 = XVBITREVI_B |
| 3139 | { 1776, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1776 = XVBITCLR_W |
| 3140 | { 1775, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1775 = XVBITCLR_H |
| 3141 | { 1774, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1774 = XVBITCLR_D |
| 3142 | { 1773, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1773 = XVBITCLR_B |
| 3143 | { 1772, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1772 = XVBITCLRI_W |
| 3144 | { 1771, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1771 = XVBITCLRI_H |
| 3145 | { 1770, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1770 = XVBITCLRI_D |
| 3146 | { 1769, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1769 = XVBITCLRI_B |
| 3147 | { 1768, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1768 = XVAVG_WU |
| 3148 | { 1767, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1767 = XVAVG_W |
| 3149 | { 1766, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1766 = XVAVG_HU |
| 3150 | { 1765, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1765 = XVAVG_H |
| 3151 | { 1764, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1764 = XVAVG_DU |
| 3152 | { 1763, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1763 = XVAVG_D |
| 3153 | { 1762, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1762 = XVAVG_BU |
| 3154 | { 1761, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1761 = XVAVG_B |
| 3155 | { 1760, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1760 = XVAVGR_WU |
| 3156 | { 1759, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1759 = XVAVGR_W |
| 3157 | { 1758, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1758 = XVAVGR_HU |
| 3158 | { 1757, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1757 = XVAVGR_H |
| 3159 | { 1756, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1756 = XVAVGR_DU |
| 3160 | { 1755, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1755 = XVAVGR_D |
| 3161 | { 1754, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1754 = XVAVGR_BU |
| 3162 | { 1753, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1753 = XVAVGR_B |
| 3163 | { 1752, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1752 = XVAND_V |
| 3164 | { 1751, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1751 = XVANDN_V |
| 3165 | { 1750, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1750 = XVANDI_B |
| 3166 | { 1749, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1749 = XVADD_W |
| 3167 | { 1748, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1748 = XVADD_Q |
| 3168 | { 1747, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1747 = XVADD_H |
| 3169 | { 1746, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1746 = XVADD_D |
| 3170 | { 1745, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1745 = XVADD_B |
| 3171 | { 1744, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1744 = XVADDWOD_W_HU_H |
| 3172 | { 1743, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1743 = XVADDWOD_W_HU |
| 3173 | { 1742, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1742 = XVADDWOD_W_H |
| 3174 | { 1741, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1741 = XVADDWOD_Q_DU_D |
| 3175 | { 1740, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1740 = XVADDWOD_Q_DU |
| 3176 | { 1739, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1739 = XVADDWOD_Q_D |
| 3177 | { 1738, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1738 = XVADDWOD_H_BU_B |
| 3178 | { 1737, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1737 = XVADDWOD_H_BU |
| 3179 | { 1736, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1736 = XVADDWOD_H_B |
| 3180 | { 1735, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1735 = XVADDWOD_D_WU_W |
| 3181 | { 1734, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1734 = XVADDWOD_D_WU |
| 3182 | { 1733, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1733 = XVADDWOD_D_W |
| 3183 | { 1732, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1732 = XVADDWEV_W_HU_H |
| 3184 | { 1731, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1731 = XVADDWEV_W_HU |
| 3185 | { 1730, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1730 = XVADDWEV_W_H |
| 3186 | { 1729, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1729 = XVADDWEV_Q_DU_D |
| 3187 | { 1728, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1728 = XVADDWEV_Q_DU |
| 3188 | { 1727, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1727 = XVADDWEV_Q_D |
| 3189 | { 1726, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1726 = XVADDWEV_H_BU_B |
| 3190 | { 1725, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1725 = XVADDWEV_H_BU |
| 3191 | { 1724, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1724 = XVADDWEV_H_B |
| 3192 | { 1723, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1723 = XVADDWEV_D_WU_W |
| 3193 | { 1722, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1722 = XVADDWEV_D_WU |
| 3194 | { 1721, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1721 = XVADDWEV_D_W |
| 3195 | { 1720, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1720 = XVADDI_WU |
| 3196 | { 1719, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1719 = XVADDI_HU |
| 3197 | { 1718, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1718 = XVADDI_DU |
| 3198 | { 1717, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 382, 0, 0x0ULL }, // Inst #1717 = XVADDI_BU |
| 3199 | { 1716, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1716 = XVADDA_W |
| 3200 | { 1715, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1715 = XVADDA_H |
| 3201 | { 1714, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1714 = XVADDA_D |
| 3202 | { 1713, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1713 = XVADDA_B |
| 3203 | { 1712, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1712 = XVABSD_WU |
| 3204 | { 1711, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1711 = XVABSD_W |
| 3205 | { 1710, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1710 = XVABSD_HU |
| 3206 | { 1709, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1709 = XVABSD_H |
| 3207 | { 1708, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1708 = XVABSD_DU |
| 3208 | { 1707, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1707 = XVABSD_D |
| 3209 | { 1706, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1706 = XVABSD_BU |
| 3210 | { 1705, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 379, 0, 0x0ULL }, // Inst #1705 = XVABSD_B |
| 3211 | { 1704, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1704 = XORI |
| 3212 | { 1703, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #1703 = XOR |
| 3213 | { 1702, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1702 = X86XOR_W |
| 3214 | { 1701, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1701 = X86XOR_H |
| 3215 | { 1700, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1700 = X86XOR_D |
| 3216 | { 1699, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1699 = X86XOR_B |
| 3217 | { 1698, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1698 = X86SUB_WU |
| 3218 | { 1697, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1697 = X86SUB_W |
| 3219 | { 1696, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1696 = X86SUB_H |
| 3220 | { 1695, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1695 = X86SUB_DU |
| 3221 | { 1694, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1694 = X86SUB_D |
| 3222 | { 1693, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1693 = X86SUB_B |
| 3223 | { 1692, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1692 = X86SRL_W |
| 3224 | { 1691, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1691 = X86SRL_H |
| 3225 | { 1690, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1690 = X86SRL_D |
| 3226 | { 1689, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1689 = X86SRL_B |
| 3227 | { 1688, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1688 = X86SRLI_W |
| 3228 | { 1687, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1687 = X86SRLI_H |
| 3229 | { 1686, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1686 = X86SRLI_D |
| 3230 | { 1685, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1685 = X86SRLI_B |
| 3231 | { 1684, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1684 = X86SRA_W |
| 3232 | { 1683, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1683 = X86SRA_H |
| 3233 | { 1682, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1682 = X86SRA_D |
| 3234 | { 1681, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1681 = X86SRA_B |
| 3235 | { 1680, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1680 = X86SRAI_W |
| 3236 | { 1679, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1679 = X86SRAI_H |
| 3237 | { 1678, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1678 = X86SRAI_D |
| 3238 | { 1677, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1677 = X86SRAI_B |
| 3239 | { 1676, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1676 = X86SLL_W |
| 3240 | { 1675, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1675 = X86SLL_H |
| 3241 | { 1674, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1674 = X86SLL_D |
| 3242 | { 1673, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1673 = X86SLL_B |
| 3243 | { 1672, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1672 = X86SLLI_W |
| 3244 | { 1671, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1671 = X86SLLI_H |
| 3245 | { 1670, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1670 = X86SLLI_D |
| 3246 | { 1669, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1669 = X86SLLI_B |
| 3247 | { 1668, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1668 = X86SETTM |
| 3248 | { 1667, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #1667 = X86SETTAG |
| 3249 | { 1666, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1666 = X86SBC_W |
| 3250 | { 1665, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1665 = X86SBC_H |
| 3251 | { 1664, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1664 = X86SBC_D |
| 3252 | { 1663, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1663 = X86SBC_B |
| 3253 | { 1662, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1662 = X86ROTR_W |
| 3254 | { 1661, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1661 = X86ROTR_H |
| 3255 | { 1660, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1660 = X86ROTR_D |
| 3256 | { 1659, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1659 = X86ROTR_B |
| 3257 | { 1658, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1658 = X86ROTRI_W |
| 3258 | { 1657, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1657 = X86ROTRI_H |
| 3259 | { 1656, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1656 = X86ROTRI_D |
| 3260 | { 1655, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1655 = X86ROTRI_B |
| 3261 | { 1654, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1654 = X86ROTL_W |
| 3262 | { 1653, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1653 = X86ROTL_H |
| 3263 | { 1652, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1652 = X86ROTL_D |
| 3264 | { 1651, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1651 = X86ROTL_B |
| 3265 | { 1650, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1650 = X86ROTLI_W |
| 3266 | { 1649, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1649 = X86ROTLI_H |
| 3267 | { 1648, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1648 = X86ROTLI_D |
| 3268 | { 1647, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1647 = X86ROTLI_B |
| 3269 | { 1646, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1646 = X86RCR_W |
| 3270 | { 1645, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1645 = X86RCR_H |
| 3271 | { 1644, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1644 = X86RCR_D |
| 3272 | { 1643, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1643 = X86RCR_B |
| 3273 | { 1642, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1642 = X86RCRI_W |
| 3274 | { 1641, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1641 = X86RCRI_H |
| 3275 | { 1640, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1640 = X86RCRI_D |
| 3276 | { 1639, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1639 = X86RCRI_B |
| 3277 | { 1638, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1638 = X86RCL_W |
| 3278 | { 1637, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1637 = X86RCL_H |
| 3279 | { 1636, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1636 = X86RCL_D |
| 3280 | { 1635, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1635 = X86RCL_B |
| 3281 | { 1634, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1634 = X86RCLI_W |
| 3282 | { 1633, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1633 = X86RCLI_H |
| 3283 | { 1632, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1632 = X86RCLI_D |
| 3284 | { 1631, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1631 = X86RCLI_B |
| 3285 | { 1630, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1630 = X86OR_W |
| 3286 | { 1629, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1629 = X86OR_H |
| 3287 | { 1628, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1628 = X86OR_D |
| 3288 | { 1627, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1627 = X86OR_B |
| 3289 | { 1626, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1626 = X86MUL_WU |
| 3290 | { 1625, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1625 = X86MUL_W |
| 3291 | { 1624, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1624 = X86MUL_HU |
| 3292 | { 1623, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1623 = X86MUL_H |
| 3293 | { 1622, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1622 = X86MUL_DU |
| 3294 | { 1621, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1621 = X86MUL_D |
| 3295 | { 1620, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1620 = X86MUL_BU |
| 3296 | { 1619, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1619 = X86MUL_B |
| 3297 | { 1618, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #1618 = X86MTTOP |
| 3298 | { 1617, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1617 = X86MTFLAG |
| 3299 | { 1616, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1616 = X86MFTOP |
| 3300 | { 1615, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #1615 = X86MFFLAG |
| 3301 | { 1614, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1614 = X86INC_W |
| 3302 | { 1613, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1613 = X86INC_H |
| 3303 | { 1612, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1612 = X86INC_D |
| 3304 | { 1611, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1611 = X86INC_B |
| 3305 | { 1610, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1610 = X86INCTOP |
| 3306 | { 1609, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1609 = X86DEC_W |
| 3307 | { 1608, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1608 = X86DEC_H |
| 3308 | { 1607, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1607 = X86DEC_D |
| 3309 | { 1606, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 166, 0, 0x0ULL }, // Inst #1606 = X86DEC_B |
| 3310 | { 1605, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1605 = X86DECTOP |
| 3311 | { 1604, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0, 0x0ULL }, // Inst #1604 = X86CLRTM |
| 3312 | { 1603, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1603 = X86AND_W |
| 3313 | { 1602, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1602 = X86AND_H |
| 3314 | { 1601, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1601 = X86AND_D |
| 3315 | { 1600, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1600 = X86AND_B |
| 3316 | { 1599, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1599 = X86ADD_WU |
| 3317 | { 1598, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1598 = X86ADD_W |
| 3318 | { 1597, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1597 = X86ADD_H |
| 3319 | { 1596, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1596 = X86ADD_DU |
| 3320 | { 1595, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1595 = X86ADD_D |
| 3321 | { 1594, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1594 = X86ADD_B |
| 3322 | { 1593, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1593 = X86ADC_W |
| 3323 | { 1592, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1592 = X86ADC_H |
| 3324 | { 1591, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1591 = X86ADC_D |
| 3325 | { 1590, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #1590 = X86ADC_B |
| 3326 | { 1589, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1589 = VXOR_V |
| 3327 | { 1588, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1588 = VXORI_B |
| 3328 | { 1587, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1587 = VSUB_W |
| 3329 | { 1586, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1586 = VSUB_Q |
| 3330 | { 1585, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1585 = VSUB_H |
| 3331 | { 1584, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1584 = VSUB_D |
| 3332 | { 1583, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1583 = VSUB_B |
| 3333 | { 1582, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1582 = VSUBWOD_W_HU |
| 3334 | { 1581, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1581 = VSUBWOD_W_H |
| 3335 | { 1580, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1580 = VSUBWOD_Q_DU |
| 3336 | { 1579, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1579 = VSUBWOD_Q_D |
| 3337 | { 1578, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1578 = VSUBWOD_H_BU |
| 3338 | { 1577, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1577 = VSUBWOD_H_B |
| 3339 | { 1576, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1576 = VSUBWOD_D_WU |
| 3340 | { 1575, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1575 = VSUBWOD_D_W |
| 3341 | { 1574, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1574 = VSUBWEV_W_HU |
| 3342 | { 1573, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1573 = VSUBWEV_W_H |
| 3343 | { 1572, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1572 = VSUBWEV_Q_DU |
| 3344 | { 1571, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1571 = VSUBWEV_Q_D |
| 3345 | { 1570, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1570 = VSUBWEV_H_BU |
| 3346 | { 1569, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1569 = VSUBWEV_H_B |
| 3347 | { 1568, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1568 = VSUBWEV_D_WU |
| 3348 | { 1567, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1567 = VSUBWEV_D_W |
| 3349 | { 1566, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1566 = VSUBI_WU |
| 3350 | { 1565, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1565 = VSUBI_HU |
| 3351 | { 1564, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1564 = VSUBI_DU |
| 3352 | { 1563, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1563 = VSUBI_BU |
| 3353 | { 1562, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 362, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1562 = VSTX |
| 3354 | { 1561, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1561 = VSTELM_W |
| 3355 | { 1560, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1560 = VSTELM_H |
| 3356 | { 1559, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1559 = VSTELM_D |
| 3357 | { 1558, 4, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 375, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1558 = VSTELM_B |
| 3358 | { 1557, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #1557 = VST |
| 3359 | { 1556, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1556 = VSSUB_WU |
| 3360 | { 1555, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1555 = VSSUB_W |
| 3361 | { 1554, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1554 = VSSUB_HU |
| 3362 | { 1553, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1553 = VSSUB_H |
| 3363 | { 1552, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1552 = VSSUB_DU |
| 3364 | { 1551, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1551 = VSSUB_D |
| 3365 | { 1550, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1550 = VSSUB_BU |
| 3366 | { 1549, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1549 = VSSUB_B |
| 3367 | { 1548, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1548 = VSSRLRN_W_D |
| 3368 | { 1547, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1547 = VSSRLRN_WU_D |
| 3369 | { 1546, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1546 = VSSRLRN_H_W |
| 3370 | { 1545, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1545 = VSSRLRN_HU_W |
| 3371 | { 1544, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1544 = VSSRLRN_B_H |
| 3372 | { 1543, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1543 = VSSRLRN_BU_H |
| 3373 | { 1542, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1542 = VSSRLRNI_W_D |
| 3374 | { 1541, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1541 = VSSRLRNI_WU_D |
| 3375 | { 1540, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1540 = VSSRLRNI_H_W |
| 3376 | { 1539, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1539 = VSSRLRNI_HU_W |
| 3377 | { 1538, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1538 = VSSRLRNI_D_Q |
| 3378 | { 1537, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1537 = VSSRLRNI_DU_Q |
| 3379 | { 1536, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1536 = VSSRLRNI_B_H |
| 3380 | { 1535, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1535 = VSSRLRNI_BU_H |
| 3381 | { 1534, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1534 = VSSRLN_W_D |
| 3382 | { 1533, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1533 = VSSRLN_WU_D |
| 3383 | { 1532, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1532 = VSSRLN_H_W |
| 3384 | { 1531, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1531 = VSSRLN_HU_W |
| 3385 | { 1530, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1530 = VSSRLN_B_H |
| 3386 | { 1529, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1529 = VSSRLN_BU_H |
| 3387 | { 1528, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1528 = VSSRLNI_W_D |
| 3388 | { 1527, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1527 = VSSRLNI_WU_D |
| 3389 | { 1526, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1526 = VSSRLNI_H_W |
| 3390 | { 1525, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1525 = VSSRLNI_HU_W |
| 3391 | { 1524, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1524 = VSSRLNI_D_Q |
| 3392 | { 1523, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1523 = VSSRLNI_DU_Q |
| 3393 | { 1522, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1522 = VSSRLNI_B_H |
| 3394 | { 1521, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1521 = VSSRLNI_BU_H |
| 3395 | { 1520, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1520 = VSSRARN_W_D |
| 3396 | { 1519, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1519 = VSSRARN_WU_D |
| 3397 | { 1518, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1518 = VSSRARN_H_W |
| 3398 | { 1517, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1517 = VSSRARN_HU_W |
| 3399 | { 1516, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1516 = VSSRARN_B_H |
| 3400 | { 1515, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1515 = VSSRARN_BU_H |
| 3401 | { 1514, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1514 = VSSRARNI_W_D |
| 3402 | { 1513, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1513 = VSSRARNI_WU_D |
| 3403 | { 1512, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1512 = VSSRARNI_H_W |
| 3404 | { 1511, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1511 = VSSRARNI_HU_W |
| 3405 | { 1510, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1510 = VSSRARNI_D_Q |
| 3406 | { 1509, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1509 = VSSRARNI_DU_Q |
| 3407 | { 1508, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1508 = VSSRARNI_B_H |
| 3408 | { 1507, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1507 = VSSRARNI_BU_H |
| 3409 | { 1506, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1506 = VSSRAN_W_D |
| 3410 | { 1505, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1505 = VSSRAN_WU_D |
| 3411 | { 1504, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1504 = VSSRAN_H_W |
| 3412 | { 1503, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1503 = VSSRAN_HU_W |
| 3413 | { 1502, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1502 = VSSRAN_B_H |
| 3414 | { 1501, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1501 = VSSRAN_BU_H |
| 3415 | { 1500, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1500 = VSSRANI_W_D |
| 3416 | { 1499, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1499 = VSSRANI_WU_D |
| 3417 | { 1498, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1498 = VSSRANI_H_W |
| 3418 | { 1497, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1497 = VSSRANI_HU_W |
| 3419 | { 1496, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1496 = VSSRANI_D_Q |
| 3420 | { 1495, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1495 = VSSRANI_DU_Q |
| 3421 | { 1494, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1494 = VSSRANI_B_H |
| 3422 | { 1493, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1493 = VSSRANI_BU_H |
| 3423 | { 1492, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1492 = VSRL_W |
| 3424 | { 1491, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1491 = VSRL_H |
| 3425 | { 1490, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1490 = VSRL_D |
| 3426 | { 1489, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1489 = VSRL_B |
| 3427 | { 1488, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1488 = VSRLR_W |
| 3428 | { 1487, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1487 = VSRLR_H |
| 3429 | { 1486, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1486 = VSRLR_D |
| 3430 | { 1485, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1485 = VSRLR_B |
| 3431 | { 1484, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1484 = VSRLRN_W_D |
| 3432 | { 1483, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1483 = VSRLRN_H_W |
| 3433 | { 1482, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1482 = VSRLRN_B_H |
| 3434 | { 1481, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1481 = VSRLRNI_W_D |
| 3435 | { 1480, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1480 = VSRLRNI_H_W |
| 3436 | { 1479, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1479 = VSRLRNI_D_Q |
| 3437 | { 1478, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1478 = VSRLRNI_B_H |
| 3438 | { 1477, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1477 = VSRLRI_W |
| 3439 | { 1476, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1476 = VSRLRI_H |
| 3440 | { 1475, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1475 = VSRLRI_D |
| 3441 | { 1474, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1474 = VSRLRI_B |
| 3442 | { 1473, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1473 = VSRLN_W_D |
| 3443 | { 1472, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1472 = VSRLN_H_W |
| 3444 | { 1471, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1471 = VSRLN_B_H |
| 3445 | { 1470, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1470 = VSRLNI_W_D |
| 3446 | { 1469, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1469 = VSRLNI_H_W |
| 3447 | { 1468, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1468 = VSRLNI_D_Q |
| 3448 | { 1467, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1467 = VSRLNI_B_H |
| 3449 | { 1466, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1466 = VSRLI_W |
| 3450 | { 1465, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1465 = VSRLI_H |
| 3451 | { 1464, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1464 = VSRLI_D |
| 3452 | { 1463, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1463 = VSRLI_B |
| 3453 | { 1462, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1462 = VSRA_W |
| 3454 | { 1461, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1461 = VSRA_H |
| 3455 | { 1460, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1460 = VSRA_D |
| 3456 | { 1459, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1459 = VSRA_B |
| 3457 | { 1458, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1458 = VSRAR_W |
| 3458 | { 1457, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1457 = VSRAR_H |
| 3459 | { 1456, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1456 = VSRAR_D |
| 3460 | { 1455, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1455 = VSRAR_B |
| 3461 | { 1454, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1454 = VSRARN_W_D |
| 3462 | { 1453, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1453 = VSRARN_H_W |
| 3463 | { 1452, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1452 = VSRARN_B_H |
| 3464 | { 1451, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1451 = VSRARNI_W_D |
| 3465 | { 1450, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1450 = VSRARNI_H_W |
| 3466 | { 1449, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1449 = VSRARNI_D_Q |
| 3467 | { 1448, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1448 = VSRARNI_B_H |
| 3468 | { 1447, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1447 = VSRARI_W |
| 3469 | { 1446, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1446 = VSRARI_H |
| 3470 | { 1445, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1445 = VSRARI_D |
| 3471 | { 1444, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1444 = VSRARI_B |
| 3472 | { 1443, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1443 = VSRAN_W_D |
| 3473 | { 1442, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1442 = VSRAN_H_W |
| 3474 | { 1441, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1441 = VSRAN_B_H |
| 3475 | { 1440, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1440 = VSRANI_W_D |
| 3476 | { 1439, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1439 = VSRANI_H_W |
| 3477 | { 1438, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1438 = VSRANI_D_Q |
| 3478 | { 1437, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1437 = VSRANI_B_H |
| 3479 | { 1436, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1436 = VSRAI_W |
| 3480 | { 1435, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1435 = VSRAI_H |
| 3481 | { 1434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1434 = VSRAI_D |
| 3482 | { 1433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1433 = VSRAI_B |
| 3483 | { 1432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1432 = VSLT_WU |
| 3484 | { 1431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1431 = VSLT_W |
| 3485 | { 1430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1430 = VSLT_HU |
| 3486 | { 1429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1429 = VSLT_H |
| 3487 | { 1428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1428 = VSLT_DU |
| 3488 | { 1427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1427 = VSLT_D |
| 3489 | { 1426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1426 = VSLT_BU |
| 3490 | { 1425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1425 = VSLT_B |
| 3491 | { 1424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1424 = VSLTI_WU |
| 3492 | { 1423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1423 = VSLTI_W |
| 3493 | { 1422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1422 = VSLTI_HU |
| 3494 | { 1421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1421 = VSLTI_H |
| 3495 | { 1420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1420 = VSLTI_DU |
| 3496 | { 1419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1419 = VSLTI_D |
| 3497 | { 1418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1418 = VSLTI_BU |
| 3498 | { 1417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1417 = VSLTI_B |
| 3499 | { 1416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1416 = VSLL_W |
| 3500 | { 1415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1415 = VSLL_H |
| 3501 | { 1414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1414 = VSLL_D |
| 3502 | { 1413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1413 = VSLL_B |
| 3503 | { 1412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1412 = VSLLWIL_W_H |
| 3504 | { 1411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1411 = VSLLWIL_WU_HU |
| 3505 | { 1410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1410 = VSLLWIL_H_B |
| 3506 | { 1409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1409 = VSLLWIL_HU_BU |
| 3507 | { 1408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1408 = VSLLWIL_D_W |
| 3508 | { 1407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1407 = VSLLWIL_DU_WU |
| 3509 | { 1406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1406 = VSLLI_W |
| 3510 | { 1405, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1405 = VSLLI_H |
| 3511 | { 1404, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1404 = VSLLI_D |
| 3512 | { 1403, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1403 = VSLLI_B |
| 3513 | { 1402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1402 = VSLE_WU |
| 3514 | { 1401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1401 = VSLE_W |
| 3515 | { 1400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1400 = VSLE_HU |
| 3516 | { 1399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1399 = VSLE_H |
| 3517 | { 1398, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1398 = VSLE_DU |
| 3518 | { 1397, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1397 = VSLE_D |
| 3519 | { 1396, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1396 = VSLE_BU |
| 3520 | { 1395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1395 = VSLE_B |
| 3521 | { 1394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1394 = VSLEI_WU |
| 3522 | { 1393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1393 = VSLEI_W |
| 3523 | { 1392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1392 = VSLEI_HU |
| 3524 | { 1391, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1391 = VSLEI_H |
| 3525 | { 1390, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1390 = VSLEI_DU |
| 3526 | { 1389, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1389 = VSLEI_D |
| 3527 | { 1388, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1388 = VSLEI_BU |
| 3528 | { 1387, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1387 = VSLEI_B |
| 3529 | { 1386, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1386 = VSIGNCOV_W |
| 3530 | { 1385, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1385 = VSIGNCOV_H |
| 3531 | { 1384, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1384 = VSIGNCOV_D |
| 3532 | { 1383, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1383 = VSIGNCOV_B |
| 3533 | { 1382, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1382 = VSHUF_W |
| 3534 | { 1381, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1381 = VSHUF_H |
| 3535 | { 1380, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1380 = VSHUF_D |
| 3536 | { 1379, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1379 = VSHUF_B |
| 3537 | { 1378, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1378 = VSHUF4I_W |
| 3538 | { 1377, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1377 = VSHUF4I_H |
| 3539 | { 1376, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1376 = VSHUF4I_D |
| 3540 | { 1375, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1375 = VSHUF4I_B |
| 3541 | { 1374, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1374 = VSETNEZ_V |
| 3542 | { 1373, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1373 = VSETEQZ_V |
| 3543 | { 1372, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1372 = VSETANYEQZ_W |
| 3544 | { 1371, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1371 = VSETANYEQZ_H |
| 3545 | { 1370, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1370 = VSETANYEQZ_D |
| 3546 | { 1369, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1369 = VSETANYEQZ_B |
| 3547 | { 1368, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1368 = VSETALLNEZ_W |
| 3548 | { 1367, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1367 = VSETALLNEZ_H |
| 3549 | { 1366, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1366 = VSETALLNEZ_D |
| 3550 | { 1365, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 373, 0, 0x0ULL }, // Inst #1365 = VSETALLNEZ_B |
| 3551 | { 1364, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1364 = VSEQ_W |
| 3552 | { 1363, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1363 = VSEQ_H |
| 3553 | { 1362, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1362 = VSEQ_D |
| 3554 | { 1361, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1361 = VSEQ_B |
| 3555 | { 1360, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1360 = VSEQI_W |
| 3556 | { 1359, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1359 = VSEQI_H |
| 3557 | { 1358, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1358 = VSEQI_D |
| 3558 | { 1357, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1357 = VSEQI_B |
| 3559 | { 1356, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1356 = VSAT_WU |
| 3560 | { 1355, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1355 = VSAT_W |
| 3561 | { 1354, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1354 = VSAT_HU |
| 3562 | { 1353, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1353 = VSAT_H |
| 3563 | { 1352, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1352 = VSAT_DU |
| 3564 | { 1351, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1351 = VSAT_D |
| 3565 | { 1350, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1350 = VSAT_BU |
| 3566 | { 1349, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1349 = VSAT_B |
| 3567 | { 1348, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1348 = VSADD_WU |
| 3568 | { 1347, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1347 = VSADD_W |
| 3569 | { 1346, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1346 = VSADD_HU |
| 3570 | { 1345, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1345 = VSADD_H |
| 3571 | { 1344, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1344 = VSADD_DU |
| 3572 | { 1343, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1343 = VSADD_D |
| 3573 | { 1342, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1342 = VSADD_BU |
| 3574 | { 1341, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1341 = VSADD_B |
| 3575 | { 1340, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1340 = VROTR_W |
| 3576 | { 1339, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1339 = VROTR_H |
| 3577 | { 1338, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1338 = VROTR_D |
| 3578 | { 1337, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1337 = VROTR_B |
| 3579 | { 1336, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1336 = VROTRI_W |
| 3580 | { 1335, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1335 = VROTRI_H |
| 3581 | { 1334, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1334 = VROTRI_D |
| 3582 | { 1333, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1333 = VROTRI_B |
| 3583 | { 1332, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1332 = VREPLVE_W |
| 3584 | { 1331, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1331 = VREPLVE_H |
| 3585 | { 1330, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1330 = VREPLVE_D |
| 3586 | { 1329, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 370, 0, 0x0ULL }, // Inst #1329 = VREPLVE_B |
| 3587 | { 1328, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1328 = VREPLVEI_W |
| 3588 | { 1327, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1327 = VREPLVEI_H |
| 3589 | { 1326, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1326 = VREPLVEI_D |
| 3590 | { 1325, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1325 = VREPLVEI_B |
| 3591 | { 1324, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1324 = VREPLGR2VR_W |
| 3592 | { 1323, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1323 = VREPLGR2VR_H |
| 3593 | { 1322, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1322 = VREPLGR2VR_D |
| 3594 | { 1321, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 368, 0, 0x0ULL }, // Inst #1321 = VREPLGR2VR_B |
| 3595 | { 1320, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1320 = VPICKVE2GR_WU |
| 3596 | { 1319, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1319 = VPICKVE2GR_W |
| 3597 | { 1318, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1318 = VPICKVE2GR_HU |
| 3598 | { 1317, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1317 = VPICKVE2GR_H |
| 3599 | { 1316, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1316 = VPICKVE2GR_DU |
| 3600 | { 1315, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1315 = VPICKVE2GR_D |
| 3601 | { 1314, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1314 = VPICKVE2GR_BU |
| 3602 | { 1313, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 365, 0, 0x0ULL }, // Inst #1313 = VPICKVE2GR_B |
| 3603 | { 1312, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1312 = VPICKOD_W |
| 3604 | { 1311, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1311 = VPICKOD_H |
| 3605 | { 1310, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1310 = VPICKOD_D |
| 3606 | { 1309, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1309 = VPICKOD_B |
| 3607 | { 1308, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1308 = VPICKEV_W |
| 3608 | { 1307, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1307 = VPICKEV_H |
| 3609 | { 1306, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1306 = VPICKEV_D |
| 3610 | { 1305, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1305 = VPICKEV_B |
| 3611 | { 1304, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1304 = VPERMI_W |
| 3612 | { 1303, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1303 = VPCNT_W |
| 3613 | { 1302, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1302 = VPCNT_H |
| 3614 | { 1301, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1301 = VPCNT_D |
| 3615 | { 1300, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1300 = VPCNT_B |
| 3616 | { 1299, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1299 = VPACKOD_W |
| 3617 | { 1298, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1298 = VPACKOD_H |
| 3618 | { 1297, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1297 = VPACKOD_D |
| 3619 | { 1296, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1296 = VPACKOD_B |
| 3620 | { 1295, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1295 = VPACKEV_W |
| 3621 | { 1294, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1294 = VPACKEV_H |
| 3622 | { 1293, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1293 = VPACKEV_D |
| 3623 | { 1292, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1292 = VPACKEV_B |
| 3624 | { 1291, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1291 = VOR_V |
| 3625 | { 1290, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1290 = VORN_V |
| 3626 | { 1289, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1289 = VORI_B |
| 3627 | { 1288, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1288 = VNOR_V |
| 3628 | { 1287, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1287 = VNORI_B |
| 3629 | { 1286, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1286 = VNEG_W |
| 3630 | { 1285, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1285 = VNEG_H |
| 3631 | { 1284, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1284 = VNEG_D |
| 3632 | { 1283, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1283 = VNEG_B |
| 3633 | { 1282, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1282 = VMUL_W |
| 3634 | { 1281, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1281 = VMUL_H |
| 3635 | { 1280, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1280 = VMUL_D |
| 3636 | { 1279, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1279 = VMUL_B |
| 3637 | { 1278, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1278 = VMULWOD_W_HU_H |
| 3638 | { 1277, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1277 = VMULWOD_W_HU |
| 3639 | { 1276, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1276 = VMULWOD_W_H |
| 3640 | { 1275, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1275 = VMULWOD_Q_DU_D |
| 3641 | { 1274, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1274 = VMULWOD_Q_DU |
| 3642 | { 1273, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1273 = VMULWOD_Q_D |
| 3643 | { 1272, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1272 = VMULWOD_H_BU_B |
| 3644 | { 1271, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1271 = VMULWOD_H_BU |
| 3645 | { 1270, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1270 = VMULWOD_H_B |
| 3646 | { 1269, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1269 = VMULWOD_D_WU_W |
| 3647 | { 1268, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1268 = VMULWOD_D_WU |
| 3648 | { 1267, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1267 = VMULWOD_D_W |
| 3649 | { 1266, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1266 = VMULWEV_W_HU_H |
| 3650 | { 1265, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1265 = VMULWEV_W_HU |
| 3651 | { 1264, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1264 = VMULWEV_W_H |
| 3652 | { 1263, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1263 = VMULWEV_Q_DU_D |
| 3653 | { 1262, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1262 = VMULWEV_Q_DU |
| 3654 | { 1261, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1261 = VMULWEV_Q_D |
| 3655 | { 1260, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1260 = VMULWEV_H_BU_B |
| 3656 | { 1259, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1259 = VMULWEV_H_BU |
| 3657 | { 1258, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1258 = VMULWEV_H_B |
| 3658 | { 1257, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1257 = VMULWEV_D_WU_W |
| 3659 | { 1256, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1256 = VMULWEV_D_WU |
| 3660 | { 1255, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1255 = VMULWEV_D_W |
| 3661 | { 1254, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1254 = VMUH_WU |
| 3662 | { 1253, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1253 = VMUH_W |
| 3663 | { 1252, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1252 = VMUH_HU |
| 3664 | { 1251, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1251 = VMUH_H |
| 3665 | { 1250, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1250 = VMUH_DU |
| 3666 | { 1249, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1249 = VMUH_D |
| 3667 | { 1248, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1248 = VMUH_BU |
| 3668 | { 1247, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1247 = VMUH_B |
| 3669 | { 1246, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1246 = VMSUB_W |
| 3670 | { 1245, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1245 = VMSUB_H |
| 3671 | { 1244, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1244 = VMSUB_D |
| 3672 | { 1243, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1243 = VMSUB_B |
| 3673 | { 1242, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1242 = VMSKNZ_B |
| 3674 | { 1241, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1241 = VMSKLTZ_W |
| 3675 | { 1240, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1240 = VMSKLTZ_H |
| 3676 | { 1239, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1239 = VMSKLTZ_D |
| 3677 | { 1238, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1238 = VMSKLTZ_B |
| 3678 | { 1237, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1237 = VMSKGEZ_B |
| 3679 | { 1236, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1236 = VMOD_WU |
| 3680 | { 1235, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1235 = VMOD_W |
| 3681 | { 1234, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1234 = VMOD_HU |
| 3682 | { 1233, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1233 = VMOD_H |
| 3683 | { 1232, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1232 = VMOD_DU |
| 3684 | { 1231, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1231 = VMOD_D |
| 3685 | { 1230, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1230 = VMOD_BU |
| 3686 | { 1229, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1229 = VMOD_B |
| 3687 | { 1228, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1228 = VMIN_WU |
| 3688 | { 1227, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1227 = VMIN_W |
| 3689 | { 1226, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1226 = VMIN_HU |
| 3690 | { 1225, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1225 = VMIN_H |
| 3691 | { 1224, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1224 = VMIN_DU |
| 3692 | { 1223, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1223 = VMIN_D |
| 3693 | { 1222, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1222 = VMIN_BU |
| 3694 | { 1221, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1221 = VMIN_B |
| 3695 | { 1220, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1220 = VMINI_WU |
| 3696 | { 1219, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1219 = VMINI_W |
| 3697 | { 1218, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1218 = VMINI_HU |
| 3698 | { 1217, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1217 = VMINI_H |
| 3699 | { 1216, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1216 = VMINI_DU |
| 3700 | { 1215, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1215 = VMINI_D |
| 3701 | { 1214, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1214 = VMINI_BU |
| 3702 | { 1213, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1213 = VMINI_B |
| 3703 | { 1212, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1212 = VMAX_WU |
| 3704 | { 1211, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1211 = VMAX_W |
| 3705 | { 1210, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1210 = VMAX_HU |
| 3706 | { 1209, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1209 = VMAX_H |
| 3707 | { 1208, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1208 = VMAX_DU |
| 3708 | { 1207, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1207 = VMAX_D |
| 3709 | { 1206, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1206 = VMAX_BU |
| 3710 | { 1205, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1205 = VMAX_B |
| 3711 | { 1204, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1204 = VMAXI_WU |
| 3712 | { 1203, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1203 = VMAXI_W |
| 3713 | { 1202, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1202 = VMAXI_HU |
| 3714 | { 1201, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1201 = VMAXI_H |
| 3715 | { 1200, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1200 = VMAXI_DU |
| 3716 | { 1199, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1199 = VMAXI_D |
| 3717 | { 1198, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1198 = VMAXI_BU |
| 3718 | { 1197, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #1197 = VMAXI_B |
| 3719 | { 1196, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1196 = VMADD_W |
| 3720 | { 1195, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1195 = VMADD_H |
| 3721 | { 1194, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1194 = VMADD_D |
| 3722 | { 1193, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1193 = VMADD_B |
| 3723 | { 1192, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1192 = VMADDWOD_W_HU_H |
| 3724 | { 1191, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1191 = VMADDWOD_W_HU |
| 3725 | { 1190, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1190 = VMADDWOD_W_H |
| 3726 | { 1189, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1189 = VMADDWOD_Q_DU_D |
| 3727 | { 1188, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1188 = VMADDWOD_Q_DU |
| 3728 | { 1187, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1187 = VMADDWOD_Q_D |
| 3729 | { 1186, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1186 = VMADDWOD_H_BU_B |
| 3730 | { 1185, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1185 = VMADDWOD_H_BU |
| 3731 | { 1184, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1184 = VMADDWOD_H_B |
| 3732 | { 1183, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1183 = VMADDWOD_D_WU_W |
| 3733 | { 1182, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1182 = VMADDWOD_D_WU |
| 3734 | { 1181, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1181 = VMADDWOD_D_W |
| 3735 | { 1180, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1180 = VMADDWEV_W_HU_H |
| 3736 | { 1179, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1179 = VMADDWEV_W_HU |
| 3737 | { 1178, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1178 = VMADDWEV_W_H |
| 3738 | { 1177, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1177 = VMADDWEV_Q_DU_D |
| 3739 | { 1176, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1176 = VMADDWEV_Q_DU |
| 3740 | { 1175, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1175 = VMADDWEV_Q_D |
| 3741 | { 1174, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1174 = VMADDWEV_H_BU_B |
| 3742 | { 1173, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1173 = VMADDWEV_H_BU |
| 3743 | { 1172, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1172 = VMADDWEV_H_B |
| 3744 | { 1171, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1171 = VMADDWEV_D_WU_W |
| 3745 | { 1170, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1170 = VMADDWEV_D_WU |
| 3746 | { 1169, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1169 = VMADDWEV_D_W |
| 3747 | { 1168, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 362, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1168 = VLDX |
| 3748 | { 1167, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1167 = VLDREPL_W |
| 3749 | { 1166, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1166 = VLDREPL_H |
| 3750 | { 1165, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1165 = VLDREPL_D |
| 3751 | { 1164, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1164 = VLDREPL_B |
| 3752 | { 1163, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0, 0x0ULL }, // Inst #1163 = VLDI |
| 3753 | { 1162, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1162 = VLD |
| 3754 | { 1161, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1161 = VINSGR2VR_W |
| 3755 | { 1160, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1160 = VINSGR2VR_H |
| 3756 | { 1159, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1159 = VINSGR2VR_D |
| 3757 | { 1158, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 355, 0, 0x0ULL }, // Inst #1158 = VINSGR2VR_B |
| 3758 | { 1157, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1157 = VILVL_W |
| 3759 | { 1156, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1156 = VILVL_H |
| 3760 | { 1155, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1155 = VILVL_D |
| 3761 | { 1154, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1154 = VILVL_B |
| 3762 | { 1153, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1153 = VILVH_W |
| 3763 | { 1152, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1152 = VILVH_H |
| 3764 | { 1151, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1151 = VILVH_D |
| 3765 | { 1150, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1150 = VILVH_B |
| 3766 | { 1149, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1149 = VHSUBW_W_H |
| 3767 | { 1148, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1148 = VHSUBW_WU_HU |
| 3768 | { 1147, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1147 = VHSUBW_Q_D |
| 3769 | { 1146, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1146 = VHSUBW_QU_DU |
| 3770 | { 1145, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1145 = VHSUBW_H_B |
| 3771 | { 1144, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1144 = VHSUBW_HU_BU |
| 3772 | { 1143, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1143 = VHSUBW_D_W |
| 3773 | { 1142, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1142 = VHSUBW_DU_WU |
| 3774 | { 1141, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1141 = VHADDW_W_H |
| 3775 | { 1140, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1140 = VHADDW_WU_HU |
| 3776 | { 1139, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1139 = VHADDW_Q_D |
| 3777 | { 1138, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1138 = VHADDW_QU_DU |
| 3778 | { 1137, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1137 = VHADDW_H_B |
| 3779 | { 1136, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1136 = VHADDW_HU_BU |
| 3780 | { 1135, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1135 = VHADDW_D_W |
| 3781 | { 1134, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1134 = VHADDW_DU_WU |
| 3782 | { 1133, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1133 = VFTINT_W_S |
| 3783 | { 1132, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1132 = VFTINT_W_D |
| 3784 | { 1131, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1131 = VFTINT_WU_S |
| 3785 | { 1130, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1130 = VFTINT_L_D |
| 3786 | { 1129, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1129 = VFTINT_LU_D |
| 3787 | { 1128, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1128 = VFTINTRZ_W_S |
| 3788 | { 1127, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1127 = VFTINTRZ_W_D |
| 3789 | { 1126, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1126 = VFTINTRZ_WU_S |
| 3790 | { 1125, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1125 = VFTINTRZ_L_D |
| 3791 | { 1124, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1124 = VFTINTRZ_LU_D |
| 3792 | { 1123, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1123 = VFTINTRZL_L_S |
| 3793 | { 1122, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1122 = VFTINTRZH_L_S |
| 3794 | { 1121, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1121 = VFTINTRP_W_S |
| 3795 | { 1120, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1120 = VFTINTRP_W_D |
| 3796 | { 1119, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1119 = VFTINTRP_L_D |
| 3797 | { 1118, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1118 = VFTINTRPL_L_S |
| 3798 | { 1117, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1117 = VFTINTRPH_L_S |
| 3799 | { 1116, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1116 = VFTINTRNE_W_S |
| 3800 | { 1115, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1115 = VFTINTRNE_W_D |
| 3801 | { 1114, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1114 = VFTINTRNE_L_D |
| 3802 | { 1113, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1113 = VFTINTRNEL_L_S |
| 3803 | { 1112, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1112 = VFTINTRNEH_L_S |
| 3804 | { 1111, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1111 = VFTINTRM_W_S |
| 3805 | { 1110, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1110 = VFTINTRM_W_D |
| 3806 | { 1109, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1109 = VFTINTRM_L_D |
| 3807 | { 1108, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1108 = VFTINTRML_L_S |
| 3808 | { 1107, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1107 = VFTINTRMH_L_S |
| 3809 | { 1106, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1106 = VFTINTL_L_S |
| 3810 | { 1105, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1105 = VFTINTH_L_S |
| 3811 | { 1104, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1104 = VFSUB_S |
| 3812 | { 1103, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1103 = VFSUB_D |
| 3813 | { 1102, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1102 = VFSQRT_S |
| 3814 | { 1101, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1101 = VFSQRT_D |
| 3815 | { 1100, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1100 = VFRSTP_H |
| 3816 | { 1099, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 351, 0, 0x0ULL }, // Inst #1099 = VFRSTP_B |
| 3817 | { 1098, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1098 = VFRSTPI_H |
| 3818 | { 1097, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #1097 = VFRSTPI_B |
| 3819 | { 1096, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1096 = VFRSQRT_S |
| 3820 | { 1095, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1095 = VFRSQRT_D |
| 3821 | { 1094, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1094 = VFRSQRTE_S |
| 3822 | { 1093, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1093 = VFRSQRTE_D |
| 3823 | { 1092, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1092 = VFRINT_S |
| 3824 | { 1091, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1091 = VFRINT_D |
| 3825 | { 1090, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1090 = VFRINTRZ_S |
| 3826 | { 1089, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1089 = VFRINTRZ_D |
| 3827 | { 1088, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1088 = VFRINTRP_S |
| 3828 | { 1087, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1087 = VFRINTRP_D |
| 3829 | { 1086, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1086 = VFRINTRNE_S |
| 3830 | { 1085, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1085 = VFRINTRNE_D |
| 3831 | { 1084, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1084 = VFRINTRM_S |
| 3832 | { 1083, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1083 = VFRINTRM_D |
| 3833 | { 1082, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1082 = VFRECIP_S |
| 3834 | { 1081, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1081 = VFRECIP_D |
| 3835 | { 1080, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1080 = VFRECIPE_S |
| 3836 | { 1079, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1079 = VFRECIPE_D |
| 3837 | { 1078, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1078 = VFNMSUB_S |
| 3838 | { 1077, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1077 = VFNMSUB_D |
| 3839 | { 1076, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1076 = VFNMADD_S |
| 3840 | { 1075, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1075 = VFNMADD_D |
| 3841 | { 1074, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1074 = VFMUL_S |
| 3842 | { 1073, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1073 = VFMUL_D |
| 3843 | { 1072, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1072 = VFMSUB_S |
| 3844 | { 1071, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1071 = VFMSUB_D |
| 3845 | { 1070, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1070 = VFMIN_S |
| 3846 | { 1069, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1069 = VFMIN_D |
| 3847 | { 1068, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1068 = VFMINA_S |
| 3848 | { 1067, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1067 = VFMINA_D |
| 3849 | { 1066, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1066 = VFMAX_S |
| 3850 | { 1065, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1065 = VFMAX_D |
| 3851 | { 1064, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1064 = VFMAXA_S |
| 3852 | { 1063, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1063 = VFMAXA_D |
| 3853 | { 1062, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1062 = VFMADD_S |
| 3854 | { 1061, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #1061 = VFMADD_D |
| 3855 | { 1060, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1060 = VFLOGB_S |
| 3856 | { 1059, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1059 = VFLOGB_D |
| 3857 | { 1058, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1058 = VFFINT_S_WU |
| 3858 | { 1057, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1057 = VFFINT_S_W |
| 3859 | { 1056, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1056 = VFFINT_S_L |
| 3860 | { 1055, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1055 = VFFINT_D_LU |
| 3861 | { 1054, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1054 = VFFINT_D_L |
| 3862 | { 1053, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1053 = VFFINTL_D_W |
| 3863 | { 1052, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1052 = VFFINTH_D_W |
| 3864 | { 1051, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1051 = VFDIV_S |
| 3865 | { 1050, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1050 = VFDIV_D |
| 3866 | { 1049, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1049 = VFCVT_S_D |
| 3867 | { 1048, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1048 = VFCVT_H_S |
| 3868 | { 1047, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1047 = VFCVTL_S_H |
| 3869 | { 1046, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1046 = VFCVTL_D_S |
| 3870 | { 1045, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1045 = VFCVTH_S_H |
| 3871 | { 1044, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #1044 = VFCVTH_D_S |
| 3872 | { 1043, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1043 = VFCMP_SUN_S |
| 3873 | { 1042, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1042 = VFCMP_SUN_D |
| 3874 | { 1041, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1041 = VFCMP_SUNE_S |
| 3875 | { 1040, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1040 = VFCMP_SUNE_D |
| 3876 | { 1039, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1039 = VFCMP_SULT_S |
| 3877 | { 1038, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1038 = VFCMP_SULT_D |
| 3878 | { 1037, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1037 = VFCMP_SULE_S |
| 3879 | { 1036, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1036 = VFCMP_SULE_D |
| 3880 | { 1035, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1035 = VFCMP_SUEQ_S |
| 3881 | { 1034, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1034 = VFCMP_SUEQ_D |
| 3882 | { 1033, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1033 = VFCMP_SOR_S |
| 3883 | { 1032, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1032 = VFCMP_SOR_D |
| 3884 | { 1031, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1031 = VFCMP_SNE_S |
| 3885 | { 1030, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1030 = VFCMP_SNE_D |
| 3886 | { 1029, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1029 = VFCMP_SLT_S |
| 3887 | { 1028, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1028 = VFCMP_SLT_D |
| 3888 | { 1027, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1027 = VFCMP_SLE_S |
| 3889 | { 1026, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1026 = VFCMP_SLE_D |
| 3890 | { 1025, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1025 = VFCMP_SEQ_S |
| 3891 | { 1024, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1024 = VFCMP_SEQ_D |
| 3892 | { 1023, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1023 = VFCMP_SAF_S |
| 3893 | { 1022, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1022 = VFCMP_SAF_D |
| 3894 | { 1021, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1021 = VFCMP_CUN_S |
| 3895 | { 1020, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1020 = VFCMP_CUN_D |
| 3896 | { 1019, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1019 = VFCMP_CUNE_S |
| 3897 | { 1018, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1018 = VFCMP_CUNE_D |
| 3898 | { 1017, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1017 = VFCMP_CULT_S |
| 3899 | { 1016, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1016 = VFCMP_CULT_D |
| 3900 | { 1015, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1015 = VFCMP_CULE_S |
| 3901 | { 1014, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1014 = VFCMP_CULE_D |
| 3902 | { 1013, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1013 = VFCMP_CUEQ_S |
| 3903 | { 1012, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1012 = VFCMP_CUEQ_D |
| 3904 | { 1011, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1011 = VFCMP_COR_S |
| 3905 | { 1010, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1010 = VFCMP_COR_D |
| 3906 | { 1009, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1009 = VFCMP_CNE_S |
| 3907 | { 1008, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1008 = VFCMP_CNE_D |
| 3908 | { 1007, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1007 = VFCMP_CLT_S |
| 3909 | { 1006, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1006 = VFCMP_CLT_D |
| 3910 | { 1005, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1005 = VFCMP_CLE_S |
| 3911 | { 1004, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1004 = VFCMP_CLE_D |
| 3912 | { 1003, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1003 = VFCMP_CEQ_S |
| 3913 | { 1002, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1002 = VFCMP_CEQ_D |
| 3914 | { 1001, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1001 = VFCMP_CAF_S |
| 3915 | { 1000, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #1000 = VFCMP_CAF_D |
| 3916 | { 999, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #999 = VFCLASS_S |
| 3917 | { 998, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #998 = VFCLASS_D |
| 3918 | { 997, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #997 = VFADD_S |
| 3919 | { 996, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #996 = VFADD_D |
| 3920 | { 995, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #995 = VEXTRINS_W |
| 3921 | { 994, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #994 = VEXTRINS_H |
| 3922 | { 993, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #993 = VEXTRINS_D |
| 3923 | { 992, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #992 = VEXTRINS_B |
| 3924 | { 991, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #991 = VEXTL_Q_D |
| 3925 | { 990, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #990 = VEXTL_QU_DU |
| 3926 | { 989, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #989 = VEXTH_W_H |
| 3927 | { 988, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #988 = VEXTH_WU_HU |
| 3928 | { 987, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #987 = VEXTH_Q_D |
| 3929 | { 986, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #986 = VEXTH_QU_DU |
| 3930 | { 985, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #985 = VEXTH_H_B |
| 3931 | { 984, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #984 = VEXTH_HU_BU |
| 3932 | { 983, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #983 = VEXTH_D_W |
| 3933 | { 982, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #982 = VEXTH_DU_WU |
| 3934 | { 981, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #981 = VEXT2XV_W_H |
| 3935 | { 980, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #980 = VEXT2XV_W_B |
| 3936 | { 979, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #979 = VEXT2XV_WU_HU |
| 3937 | { 978, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #978 = VEXT2XV_WU_BU |
| 3938 | { 977, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #977 = VEXT2XV_H_B |
| 3939 | { 976, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #976 = VEXT2XV_HU_BU |
| 3940 | { 975, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #975 = VEXT2XV_D_W |
| 3941 | { 974, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #974 = VEXT2XV_D_H |
| 3942 | { 973, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #973 = VEXT2XV_D_B |
| 3943 | { 972, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #972 = VEXT2XV_DU_WU |
| 3944 | { 971, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #971 = VEXT2XV_DU_HU |
| 3945 | { 970, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 349, 0, 0x0ULL }, // Inst #970 = VEXT2XV_DU_BU |
| 3946 | { 969, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #969 = VDIV_WU |
| 3947 | { 968, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #968 = VDIV_W |
| 3948 | { 967, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #967 = VDIV_HU |
| 3949 | { 966, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #966 = VDIV_H |
| 3950 | { 965, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #965 = VDIV_DU |
| 3951 | { 964, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #964 = VDIV_D |
| 3952 | { 963, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #963 = VDIV_BU |
| 3953 | { 962, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #962 = VDIV_B |
| 3954 | { 961, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #961 = VCLZ_W |
| 3955 | { 960, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #960 = VCLZ_H |
| 3956 | { 959, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #959 = VCLZ_D |
| 3957 | { 958, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #958 = VCLZ_B |
| 3958 | { 957, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #957 = VCLO_W |
| 3959 | { 956, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #956 = VCLO_H |
| 3960 | { 955, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #955 = VCLO_D |
| 3961 | { 954, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 347, 0, 0x0ULL }, // Inst #954 = VCLO_B |
| 3962 | { 953, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #953 = VBSRL_V |
| 3963 | { 952, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #952 = VBSLL_V |
| 3964 | { 951, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #951 = VBITSET_W |
| 3965 | { 950, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #950 = VBITSET_H |
| 3966 | { 949, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #949 = VBITSET_D |
| 3967 | { 948, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #948 = VBITSET_B |
| 3968 | { 947, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #947 = VBITSETI_W |
| 3969 | { 946, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #946 = VBITSETI_H |
| 3970 | { 945, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #945 = VBITSETI_D |
| 3971 | { 944, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #944 = VBITSETI_B |
| 3972 | { 943, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 343, 0, 0x0ULL }, // Inst #943 = VBITSEL_V |
| 3973 | { 942, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 339, 0, 0x0ULL }, // Inst #942 = VBITSELI_B |
| 3974 | { 941, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #941 = VBITREV_W |
| 3975 | { 940, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #940 = VBITREV_H |
| 3976 | { 939, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #939 = VBITREV_D |
| 3977 | { 938, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #938 = VBITREV_B |
| 3978 | { 937, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #937 = VBITREVI_W |
| 3979 | { 936, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #936 = VBITREVI_H |
| 3980 | { 935, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #935 = VBITREVI_D |
| 3981 | { 934, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #934 = VBITREVI_B |
| 3982 | { 933, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #933 = VBITCLR_W |
| 3983 | { 932, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #932 = VBITCLR_H |
| 3984 | { 931, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #931 = VBITCLR_D |
| 3985 | { 930, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #930 = VBITCLR_B |
| 3986 | { 929, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #929 = VBITCLRI_W |
| 3987 | { 928, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #928 = VBITCLRI_H |
| 3988 | { 927, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #927 = VBITCLRI_D |
| 3989 | { 926, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #926 = VBITCLRI_B |
| 3990 | { 925, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #925 = VAVG_WU |
| 3991 | { 924, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #924 = VAVG_W |
| 3992 | { 923, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #923 = VAVG_HU |
| 3993 | { 922, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #922 = VAVG_H |
| 3994 | { 921, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #921 = VAVG_DU |
| 3995 | { 920, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #920 = VAVG_D |
| 3996 | { 919, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #919 = VAVG_BU |
| 3997 | { 918, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #918 = VAVG_B |
| 3998 | { 917, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #917 = VAVGR_WU |
| 3999 | { 916, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #916 = VAVGR_W |
| 4000 | { 915, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #915 = VAVGR_HU |
| 4001 | { 914, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #914 = VAVGR_H |
| 4002 | { 913, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #913 = VAVGR_DU |
| 4003 | { 912, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #912 = VAVGR_D |
| 4004 | { 911, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #911 = VAVGR_BU |
| 4005 | { 910, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #910 = VAVGR_B |
| 4006 | { 909, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #909 = VAND_V |
| 4007 | { 908, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #908 = VANDN_V |
| 4008 | { 907, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #907 = VANDI_B |
| 4009 | { 906, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #906 = VADD_W |
| 4010 | { 905, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #905 = VADD_Q |
| 4011 | { 904, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #904 = VADD_H |
| 4012 | { 903, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #903 = VADD_D |
| 4013 | { 902, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #902 = VADD_B |
| 4014 | { 901, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #901 = VADDWOD_W_HU_H |
| 4015 | { 900, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #900 = VADDWOD_W_HU |
| 4016 | { 899, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #899 = VADDWOD_W_H |
| 4017 | { 898, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #898 = VADDWOD_Q_DU_D |
| 4018 | { 897, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #897 = VADDWOD_Q_DU |
| 4019 | { 896, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #896 = VADDWOD_Q_D |
| 4020 | { 895, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #895 = VADDWOD_H_BU_B |
| 4021 | { 894, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #894 = VADDWOD_H_BU |
| 4022 | { 893, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #893 = VADDWOD_H_B |
| 4023 | { 892, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #892 = VADDWOD_D_WU_W |
| 4024 | { 891, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #891 = VADDWOD_D_WU |
| 4025 | { 890, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #890 = VADDWOD_D_W |
| 4026 | { 889, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #889 = VADDWEV_W_HU_H |
| 4027 | { 888, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #888 = VADDWEV_W_HU |
| 4028 | { 887, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #887 = VADDWEV_W_H |
| 4029 | { 886, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #886 = VADDWEV_Q_DU_D |
| 4030 | { 885, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #885 = VADDWEV_Q_DU |
| 4031 | { 884, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #884 = VADDWEV_Q_D |
| 4032 | { 883, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #883 = VADDWEV_H_BU_B |
| 4033 | { 882, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #882 = VADDWEV_H_BU |
| 4034 | { 881, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #881 = VADDWEV_H_B |
| 4035 | { 880, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #880 = VADDWEV_D_WU_W |
| 4036 | { 879, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #879 = VADDWEV_D_WU |
| 4037 | { 878, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #878 = VADDWEV_D_W |
| 4038 | { 877, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #877 = VADDI_WU |
| 4039 | { 876, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #876 = VADDI_HU |
| 4040 | { 875, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #875 = VADDI_DU |
| 4041 | { 874, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 336, 0, 0x0ULL }, // Inst #874 = VADDI_BU |
| 4042 | { 873, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #873 = VADDA_W |
| 4043 | { 872, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #872 = VADDA_H |
| 4044 | { 871, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #871 = VADDA_D |
| 4045 | { 870, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #870 = VADDA_B |
| 4046 | { 869, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #869 = VABSD_WU |
| 4047 | { 868, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #868 = VABSD_W |
| 4048 | { 867, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #867 = VABSD_HU |
| 4049 | { 866, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #866 = VABSD_H |
| 4050 | { 865, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #865 = VABSD_DU |
| 4051 | { 864, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #864 = VABSD_D |
| 4052 | { 863, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #863 = VABSD_BU |
| 4053 | { 862, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 333, 0, 0x0ULL }, // Inst #862 = VABSD_B |
| 4054 | { 861, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #861 = TLBWR |
| 4055 | { 860, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #860 = TLBSRCH |
| 4056 | { 859, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #859 = TLBRD |
| 4057 | { 858, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #858 = TLBFLUSH |
| 4058 | { 857, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #857 = TLBFILL |
| 4059 | { 856, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #856 = TLBCLR |
| 4060 | { 855, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #855 = SYSCALL |
| 4061 | { 854, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #854 = SUB_W |
| 4062 | { 853, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #853 = SUB_D |
| 4063 | { 852, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #852 = ST_W |
| 4064 | { 851, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #851 = ST_H |
| 4065 | { 850, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #850 = ST_D |
| 4066 | { 849, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #849 = ST_B |
| 4067 | { 848, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #848 = STX_W |
| 4068 | { 847, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #847 = STX_H |
| 4069 | { 846, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #846 = STX_D |
| 4070 | { 845, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #845 = STX_B |
| 4071 | { 844, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #844 = STR_W |
| 4072 | { 843, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #843 = STR_D |
| 4073 | { 842, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #842 = STPTR_W |
| 4074 | { 841, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #841 = STPTR_D |
| 4075 | { 840, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #840 = STL_W |
| 4076 | { 839, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #839 = STL_D |
| 4077 | { 838, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #838 = STLE_W |
| 4078 | { 837, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #837 = STLE_H |
| 4079 | { 836, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #836 = STLE_D |
| 4080 | { 835, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #835 = STLE_B |
| 4081 | { 834, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #834 = STGT_W |
| 4082 | { 833, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #833 = STGT_H |
| 4083 | { 832, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #832 = STGT_D |
| 4084 | { 831, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #831 = STGT_B |
| 4085 | { 830, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #830 = SRL_W |
| 4086 | { 829, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #829 = SRL_D |
| 4087 | { 828, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #828 = SRLI_W |
| 4088 | { 827, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #827 = SRLI_D |
| 4089 | { 826, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #826 = SRA_W |
| 4090 | { 825, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #825 = SRA_D |
| 4091 | { 824, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #824 = SRAI_W |
| 4092 | { 823, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #823 = SRAI_D |
| 4093 | { 822, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #822 = SLTUI |
| 4094 | { 821, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #821 = SLTU |
| 4095 | { 820, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #820 = SLTI |
| 4096 | { 819, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #819 = SLT |
| 4097 | { 818, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #818 = SLL_W |
| 4098 | { 817, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #817 = SLL_D |
| 4099 | { 816, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #816 = SLLI_W |
| 4100 | { 815, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #815 = SLLI_D |
| 4101 | { 814, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 332, 0, 0x0ULL }, // Inst #814 = SET_CFR_TRUE |
| 4102 | { 813, 1, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 332, 0, 0x0ULL }, // Inst #813 = SET_CFR_FALSE |
| 4103 | { 812, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #812 = SETX86LOOPNE |
| 4104 | { 811, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #811 = SETX86LOOPE |
| 4105 | { 810, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #810 = SETX86J |
| 4106 | { 809, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #809 = SETARMJ |
| 4107 | { 808, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #808 = SC_W |
| 4108 | { 807, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 328, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #807 = SC_Q |
| 4109 | { 806, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #806 = SC_D |
| 4110 | { 805, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 325, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #805 = SCREL_W |
| 4111 | { 804, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 325, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #804 = SCREL_D |
| 4112 | { 803, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #803 = SBC_W |
| 4113 | { 802, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #802 = SBC_H |
| 4114 | { 801, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #801 = SBC_D |
| 4115 | { 800, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #800 = SBC_B |
| 4116 | { 799, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #799 = ROTR_W |
| 4117 | { 798, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #798 = ROTR_H |
| 4118 | { 797, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #797 = ROTR_D |
| 4119 | { 796, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #796 = ROTR_B |
| 4120 | { 795, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #795 = ROTRI_W |
| 4121 | { 794, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #794 = ROTRI_H |
| 4122 | { 793, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #793 = ROTRI_D |
| 4123 | { 792, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #792 = ROTRI_B |
| 4124 | { 791, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #791 = REVH_D |
| 4125 | { 790, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #790 = REVH_2W |
| 4126 | { 789, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #789 = REVB_D |
| 4127 | { 788, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #788 = REVB_4H |
| 4128 | { 787, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #787 = REVB_2W |
| 4129 | { 786, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #786 = REVB_2H |
| 4130 | { 785, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #785 = RDTIME_D |
| 4131 | { 784, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #784 = RDTIMEL_W |
| 4132 | { 783, 2, 2, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #783 = RDTIMEH_W |
| 4133 | { 782, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #782 = RCR_W |
| 4134 | { 781, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #781 = RCR_H |
| 4135 | { 780, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #780 = RCR_D |
| 4136 | { 779, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #779 = RCR_B |
| 4137 | { 778, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #778 = RCRI_W |
| 4138 | { 777, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #777 = RCRI_H |
| 4139 | { 776, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #776 = RCRI_D |
| 4140 | { 775, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #775 = RCRI_B |
| 4141 | { 774, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 322, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #774 = PRELDX |
| 4142 | { 773, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 237, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #773 = PRELD |
| 4143 | { 772, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #772 = PCALAU12I |
| 4144 | { 771, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #771 = PCADDU18I |
| 4145 | { 770, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #770 = PCADDU12I |
| 4146 | { 769, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #769 = PCADDI |
| 4147 | { 768, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #768 = ORN |
| 4148 | { 767, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #767 = ORI |
| 4149 | { 766, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #766 = OR |
| 4150 | { 765, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #765 = NOR |
| 4151 | { 764, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #764 = MUL_W |
| 4152 | { 763, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #763 = MUL_D |
| 4153 | { 762, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #762 = MULW_D_WU |
| 4154 | { 761, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #761 = MULW_D_W |
| 4155 | { 760, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #760 = MULH_WU |
| 4156 | { 759, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #759 = MULH_W |
| 4157 | { 758, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #758 = MULH_DU |
| 4158 | { 757, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #757 = MULH_D |
| 4159 | { 756, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 320, 0, 0x0ULL }, // Inst #756 = MOVSCR2GR |
| 4160 | { 755, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 318, 0, 0x0ULL }, // Inst #755 = MOVGR2SCR |
| 4161 | { 754, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 314, 0, 0x0ULL }, // Inst #754 = MOVGR2FR_W_64 |
| 4162 | { 753, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 316, 0, 0x0ULL }, // Inst #753 = MOVGR2FR_W |
| 4163 | { 752, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 314, 0, 0x0ULL }, // Inst #752 = MOVGR2FR_D |
| 4164 | { 751, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 311, 0, 0x0ULL }, // Inst #751 = MOVGR2FRH_W |
| 4165 | { 750, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #750 = MOVGR2FCSR |
| 4166 | { 749, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 307, 0, 0x0ULL }, // Inst #749 = MOVGR2CF |
| 4167 | { 748, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #748 = MOVFRH2GR_S |
| 4168 | { 747, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #747 = MOVFR2GR_S_64 |
| 4169 | { 746, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 305, 0, 0x0ULL }, // Inst #746 = MOVFR2GR_S |
| 4170 | { 745, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 303, 0, 0x0ULL }, // Inst #745 = MOVFR2GR_D |
| 4171 | { 744, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 301, 0, 0x0ULL }, // Inst #744 = MOVFR2CF_xS |
| 4172 | { 743, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #743 = MOVFCSR2GR |
| 4173 | { 742, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 297, 0, 0x0ULL }, // Inst #742 = MOVCF2GR |
| 4174 | { 741, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 295, 0, 0x0ULL }, // Inst #741 = MOVCF2FR_xS |
| 4175 | { 740, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #740 = MOD_WU |
| 4176 | { 739, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #739 = MOD_W |
| 4177 | { 738, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #738 = MOD_DU |
| 4178 | { 737, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #737 = MOD_D |
| 4179 | { 736, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #736 = MASKNEZ |
| 4180 | { 735, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #735 = MASKEQZ |
| 4181 | { 734, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #734 = LU52I_D |
| 4182 | { 733, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #733 = LU32I_D |
| 4183 | { 732, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #732 = LU12I_W |
| 4184 | { 731, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #731 = LL_W |
| 4185 | { 730, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #730 = LL_D |
| 4186 | { 729, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #729 = LLACQ_W |
| 4187 | { 728, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #728 = LLACQ_D |
| 4188 | { 727, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #727 = LD_WU |
| 4189 | { 726, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #726 = LD_W |
| 4190 | { 725, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #725 = LD_HU |
| 4191 | { 724, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #724 = LD_H |
| 4192 | { 723, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #723 = LD_D |
| 4193 | { 722, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #722 = LD_BU |
| 4194 | { 721, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #721 = LD_B |
| 4195 | { 720, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #720 = LDX_WU |
| 4196 | { 719, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #719 = LDX_W |
| 4197 | { 718, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #718 = LDX_HU |
| 4198 | { 717, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #717 = LDX_H |
| 4199 | { 716, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #716 = LDX_D |
| 4200 | { 715, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #715 = LDX_BU |
| 4201 | { 714, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #714 = LDX_B |
| 4202 | { 713, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #713 = LDR_W |
| 4203 | { 712, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #712 = LDR_D |
| 4204 | { 711, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #711 = LDPTR_W |
| 4205 | { 710, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #710 = LDPTR_D |
| 4206 | { 709, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #709 = LDPTE |
| 4207 | { 708, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #708 = LDL_W |
| 4208 | { 707, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #707 = LDL_D |
| 4209 | { 706, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #706 = LDLE_W |
| 4210 | { 705, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #705 = LDLE_H |
| 4211 | { 704, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #704 = LDLE_D |
| 4212 | { 703, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #703 = LDLE_B |
| 4213 | { 702, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #702 = LDGT_W |
| 4214 | { 701, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #701 = LDGT_H |
| 4215 | { 700, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #700 = LDGT_D |
| 4216 | { 699, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #699 = LDGT_B |
| 4217 | { 698, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #698 = LDDIR |
| 4218 | { 697, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #697 = JISCR1 |
| 4219 | { 696, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0, 0x0ULL }, // Inst #696 = JISCR0 |
| 4220 | { 695, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #695 = JIRL |
| 4221 | { 694, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = IOCSRWR_W |
| 4222 | { 693, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #693 = IOCSRWR_H |
| 4223 | { 692, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #692 = IOCSRWR_D |
| 4224 | { 691, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #691 = IOCSRWR_B |
| 4225 | { 690, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #690 = IOCSRRD_W |
| 4226 | { 689, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #689 = IOCSRRD_H |
| 4227 | { 688, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = IOCSRRD_D |
| 4228 | { 687, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = IOCSRRD_B |
| 4229 | { 686, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #686 = INVTLB |
| 4230 | { 685, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #685 = IDLE |
| 4231 | { 684, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #684 = IBAR |
| 4232 | { 683, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #683 = HVCL |
| 4233 | { 682, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #682 = GTLBFLUSH |
| 4234 | { 681, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = GCSRXCHG |
| 4235 | { 680, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = GCSRWR |
| 4236 | { 679, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #679 = GCSRRD |
| 4237 | { 678, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #678 = FTINT_W_S |
| 4238 | { 677, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #677 = FTINT_W_D |
| 4239 | { 676, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #676 = FTINT_L_S |
| 4240 | { 675, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #675 = FTINT_L_D |
| 4241 | { 674, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #674 = FTINTRZ_W_S |
| 4242 | { 673, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #673 = FTINTRZ_W_D |
| 4243 | { 672, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #672 = FTINTRZ_L_S |
| 4244 | { 671, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #671 = FTINTRZ_L_D |
| 4245 | { 670, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #670 = FTINTRP_W_S |
| 4246 | { 669, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #669 = FTINTRP_W_D |
| 4247 | { 668, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #668 = FTINTRP_L_S |
| 4248 | { 667, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #667 = FTINTRP_L_D |
| 4249 | { 666, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #666 = FTINTRNE_W_S |
| 4250 | { 665, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #665 = FTINTRNE_W_D |
| 4251 | { 664, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #664 = FTINTRNE_L_S |
| 4252 | { 663, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #663 = FTINTRNE_L_D |
| 4253 | { 662, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #662 = FTINTRM_W_S |
| 4254 | { 661, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #661 = FTINTRM_W_D |
| 4255 | { 660, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #660 = FTINTRM_L_S |
| 4256 | { 659, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #659 = FTINTRM_L_D |
| 4257 | { 658, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #658 = FSUB_S |
| 4258 | { 657, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #657 = FSUB_D |
| 4259 | { 656, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 276, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #656 = FST_S |
| 4260 | { 655, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 273, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #655 = FST_D |
| 4261 | { 654, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #654 = FSTX_S |
| 4262 | { 653, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #653 = FSTX_D |
| 4263 | { 652, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #652 = FSTLE_S |
| 4264 | { 651, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #651 = FSTLE_D |
| 4265 | { 650, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #650 = FSTGT_S |
| 4266 | { 649, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #649 = FSTGT_D |
| 4267 | { 648, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #648 = FSQRT_S |
| 4268 | { 647, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #647 = FSQRT_D |
| 4269 | { 646, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 291, 0, 0x0ULL }, // Inst #646 = FSEL_xS |
| 4270 | { 645, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 287, 0, 0x0ULL }, // Inst #645 = FSEL_xD |
| 4271 | { 644, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #644 = FSCALEB_S |
| 4272 | { 643, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #643 = FSCALEB_D |
| 4273 | { 642, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #642 = FRSQRT_S |
| 4274 | { 641, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #641 = FRSQRT_D |
| 4275 | { 640, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #640 = FRSQRTE_S |
| 4276 | { 639, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #639 = FRSQRTE_D |
| 4277 | { 638, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #638 = FRINT_S |
| 4278 | { 637, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #637 = FRINT_D |
| 4279 | { 636, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #636 = FRECIP_S |
| 4280 | { 635, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #635 = FRECIP_D |
| 4281 | { 634, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #634 = FRECIPE_S |
| 4282 | { 633, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #633 = FRECIPE_D |
| 4283 | { 632, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #632 = FNMSUB_S |
| 4284 | { 631, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #631 = FNMSUB_D |
| 4285 | { 630, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #630 = FNMADD_S |
| 4286 | { 629, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #629 = FNMADD_D |
| 4287 | { 628, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #628 = FNEG_S |
| 4288 | { 627, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #627 = FNEG_D |
| 4289 | { 626, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #626 = FMUL_S |
| 4290 | { 625, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #625 = FMUL_D |
| 4291 | { 624, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #624 = FMSUB_S |
| 4292 | { 623, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #623 = FMSUB_D |
| 4293 | { 622, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #622 = FMOV_S |
| 4294 | { 621, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #621 = FMOV_D |
| 4295 | { 620, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #620 = FMIN_S |
| 4296 | { 619, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #619 = FMIN_D |
| 4297 | { 618, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #618 = FMINA_S |
| 4298 | { 617, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #617 = FMINA_D |
| 4299 | { 616, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #616 = FMAX_S |
| 4300 | { 615, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #615 = FMAX_D |
| 4301 | { 614, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #614 = FMAXA_S |
| 4302 | { 613, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #613 = FMAXA_D |
| 4303 | { 612, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 283, 0, 0x0ULL }, // Inst #612 = FMADD_S |
| 4304 | { 611, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 279, 0, 0x0ULL }, // Inst #611 = FMADD_D |
| 4305 | { 610, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #610 = FLOGB_S |
| 4306 | { 609, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #609 = FLOGB_D |
| 4307 | { 608, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 276, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #608 = FLD_S |
| 4308 | { 607, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 273, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #607 = FLD_D |
| 4309 | { 606, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #606 = FLDX_S |
| 4310 | { 605, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #605 = FLDX_D |
| 4311 | { 604, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #604 = FLDLE_S |
| 4312 | { 603, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #603 = FLDLE_D |
| 4313 | { 602, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 270, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #602 = FLDGT_S |
| 4314 | { 601, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 267, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #601 = FLDGT_D |
| 4315 | { 600, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #600 = FFINT_S_W |
| 4316 | { 599, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #599 = FFINT_S_L |
| 4317 | { 598, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #598 = FFINT_D_W |
| 4318 | { 597, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #597 = FFINT_D_L |
| 4319 | { 596, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #596 = FDIV_S |
| 4320 | { 595, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #595 = FDIV_D |
| 4321 | { 594, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #594 = FCVT_UD_D |
| 4322 | { 593, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 265, 0, 0x0ULL }, // Inst #593 = FCVT_S_D |
| 4323 | { 592, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #592 = FCVT_LD_D |
| 4324 | { 591, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 263, 0, 0x0ULL }, // Inst #591 = FCVT_D_S |
| 4325 | { 590, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #590 = FCVT_D_LD |
| 4326 | { 589, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #589 = FCOPYSIGN_S |
| 4327 | { 588, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #588 = FCOPYSIGN_D |
| 4328 | { 587, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #587 = FCMP_SUN_S |
| 4329 | { 586, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #586 = FCMP_SUN_D |
| 4330 | { 585, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #585 = FCMP_SUNE_S |
| 4331 | { 584, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #584 = FCMP_SUNE_D |
| 4332 | { 583, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #583 = FCMP_SULT_S |
| 4333 | { 582, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #582 = FCMP_SULT_D |
| 4334 | { 581, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #581 = FCMP_SULE_S |
| 4335 | { 580, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #580 = FCMP_SULE_D |
| 4336 | { 579, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #579 = FCMP_SUEQ_S |
| 4337 | { 578, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #578 = FCMP_SUEQ_D |
| 4338 | { 577, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #577 = FCMP_SOR_S |
| 4339 | { 576, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #576 = FCMP_SOR_D |
| 4340 | { 575, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #575 = FCMP_SNE_S |
| 4341 | { 574, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #574 = FCMP_SNE_D |
| 4342 | { 573, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #573 = FCMP_SLT_S |
| 4343 | { 572, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #572 = FCMP_SLT_D |
| 4344 | { 571, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #571 = FCMP_SLE_S |
| 4345 | { 570, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #570 = FCMP_SLE_D |
| 4346 | { 569, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #569 = FCMP_SEQ_S |
| 4347 | { 568, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #568 = FCMP_SEQ_D |
| 4348 | { 567, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #567 = FCMP_SAF_S |
| 4349 | { 566, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #566 = FCMP_SAF_D |
| 4350 | { 565, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #565 = FCMP_CUN_S |
| 4351 | { 564, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #564 = FCMP_CUN_D |
| 4352 | { 563, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #563 = FCMP_CUNE_S |
| 4353 | { 562, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #562 = FCMP_CUNE_D |
| 4354 | { 561, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #561 = FCMP_CULT_S |
| 4355 | { 560, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #560 = FCMP_CULT_D |
| 4356 | { 559, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #559 = FCMP_CULE_S |
| 4357 | { 558, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #558 = FCMP_CULE_D |
| 4358 | { 557, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #557 = FCMP_CUEQ_S |
| 4359 | { 556, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #556 = FCMP_CUEQ_D |
| 4360 | { 555, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #555 = FCMP_COR_S |
| 4361 | { 554, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #554 = FCMP_COR_D |
| 4362 | { 553, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #553 = FCMP_CNE_S |
| 4363 | { 552, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #552 = FCMP_CNE_D |
| 4364 | { 551, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #551 = FCMP_CLT_S |
| 4365 | { 550, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #550 = FCMP_CLT_D |
| 4366 | { 549, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #549 = FCMP_CLE_S |
| 4367 | { 548, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #548 = FCMP_CLE_D |
| 4368 | { 547, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #547 = FCMP_CEQ_S |
| 4369 | { 546, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #546 = FCMP_CEQ_D |
| 4370 | { 545, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 260, 0, 0x0ULL }, // Inst #545 = FCMP_CAF_S |
| 4371 | { 544, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 257, 0, 0x0ULL }, // Inst #544 = FCMP_CAF_D |
| 4372 | { 543, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #543 = FCLASS_S |
| 4373 | { 542, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #542 = FCLASS_D |
| 4374 | { 541, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 254, 0, 0x0ULL }, // Inst #541 = FADD_S |
| 4375 | { 540, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 251, 0, 0x0ULL }, // Inst #540 = FADD_D |
| 4376 | { 539, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 249, 0, 0x0ULL }, // Inst #539 = FABS_S |
| 4377 | { 538, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 247, 0, 0x0ULL }, // Inst #538 = FABS_D |
| 4378 | { 537, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #537 = EXT_W_H |
| 4379 | { 536, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #536 = EXT_W_B |
| 4380 | { 535, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = ERTN |
| 4381 | { 534, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #534 = DIV_WU |
| 4382 | { 533, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #533 = DIV_W |
| 4383 | { 532, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #532 = DIV_DU |
| 4384 | { 531, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #531 = DIV_D |
| 4385 | { 530, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = DBCL |
| 4386 | { 529, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #529 = DBAR |
| 4387 | { 528, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #528 = CTZ_W |
| 4388 | { 527, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #527 = CTZ_D |
| 4389 | { 526, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #526 = CTO_W |
| 4390 | { 525, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #525 = CTO_D |
| 4391 | { 524, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #524 = CSRXCHG |
| 4392 | { 523, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = CSRWR |
| 4393 | { 522, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = CSRRD |
| 4394 | { 521, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #521 = CRC_W_W_W |
| 4395 | { 520, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #520 = CRC_W_H_W |
| 4396 | { 519, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #519 = CRC_W_D_W |
| 4397 | { 518, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #518 = CRC_W_B_W |
| 4398 | { 517, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #517 = CRCC_W_W_W |
| 4399 | { 516, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #516 = CRCC_W_H_W |
| 4400 | { 515, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #515 = CRCC_W_D_W |
| 4401 | { 514, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #514 = CRCC_W_B_W |
| 4402 | { 513, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #513 = CPUCFG |
| 4403 | { 512, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #512 = CLZ_W |
| 4404 | { 511, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #511 = CLZ_D |
| 4405 | { 510, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #510 = CLO_W |
| 4406 | { 509, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #509 = CLO_D |
| 4407 | { 508, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 237, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = CACOP |
| 4408 | { 507, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #507 = BYTEPICK_W |
| 4409 | { 506, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #506 = BYTEPICK_D |
| 4410 | { 505, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 233, 0, 0x0ULL }, // Inst #505 = BSTRPICK_W |
| 4411 | { 504, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 233, 0, 0x0ULL }, // Inst #504 = BSTRPICK_D |
| 4412 | { 503, 5, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #503 = BSTRINS_W |
| 4413 | { 502, 5, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 228, 0, 0x0ULL }, // Inst #502 = BSTRINS_D |
| 4414 | { 501, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = BREAK |
| 4415 | { 500, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #500 = BNEZ |
| 4416 | { 499, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #499 = BNE |
| 4417 | { 498, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #498 = BLTU |
| 4418 | { 497, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #497 = BLT |
| 4419 | { 496, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #496 = BL |
| 4420 | { 495, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #495 = BITREV_W |
| 4421 | { 494, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #494 = BITREV_D |
| 4422 | { 493, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #493 = BITREV_8B |
| 4423 | { 492, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0, 0x0ULL }, // Inst #492 = BITREV_4B |
| 4424 | { 491, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #491 = BGEU |
| 4425 | { 490, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #490 = BGE |
| 4426 | { 489, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #489 = BEQZ |
| 4427 | { 488, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #488 = BEQ |
| 4428 | { 487, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 226, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #487 = BCNEZ |
| 4429 | { 486, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 226, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #486 = BCEQZ |
| 4430 | { 485, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #485 = B |
| 4431 | { 484, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #484 = ASRTLE_D |
| 4432 | { 483, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 224, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #483 = ASRTGT_D |
| 4433 | { 482, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #482 = ARMXOR_W |
| 4434 | { 481, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #481 = ARMSUB_W |
| 4435 | { 480, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #480 = ARMSRL_W |
| 4436 | { 479, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #479 = ARMSRLI_W |
| 4437 | { 478, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #478 = ARMSRA_W |
| 4438 | { 477, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #477 = ARMSRAI_W |
| 4439 | { 476, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #476 = ARMSLL_W |
| 4440 | { 475, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #475 = ARMSLLI_W |
| 4441 | { 474, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #474 = ARMSBC_W |
| 4442 | { 473, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #473 = ARMRRX_W |
| 4443 | { 472, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #472 = ARMROTR_W |
| 4444 | { 471, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 221, 0, 0x0ULL }, // Inst #471 = ARMROTRI_W |
| 4445 | { 470, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #470 = ARMOR_W |
| 4446 | { 469, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #469 = ARMNOT_W |
| 4447 | { 468, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #468 = ARMMTFLAG |
| 4448 | { 467, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #467 = ARMMOV_W |
| 4449 | { 466, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #466 = ARMMOV_D |
| 4450 | { 465, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #465 = ARMMOVE |
| 4451 | { 464, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0, 0x0ULL }, // Inst #464 = ARMMFFLAG |
| 4452 | { 463, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #463 = ARMAND_W |
| 4453 | { 462, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #462 = ARMADD_W |
| 4454 | { 461, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #461 = ARMADC_W |
| 4455 | { 460, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #460 = ANDN |
| 4456 | { 459, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #459 = ANDI |
| 4457 | { 458, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #458 = AND |
| 4458 | { 457, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #457 = AMXOR__DB_W |
| 4459 | { 456, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #456 = AMXOR__DB_D |
| 4460 | { 455, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #455 = AMXOR_W |
| 4461 | { 454, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #454 = AMXOR_D |
| 4462 | { 453, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #453 = AMSWAP__DB_W |
| 4463 | { 452, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #452 = AMSWAP__DB_H |
| 4464 | { 451, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #451 = AMSWAP__DB_D |
| 4465 | { 450, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #450 = AMSWAP__DB_B |
| 4466 | { 449, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #449 = AMSWAP_W |
| 4467 | { 448, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #448 = AMSWAP_H |
| 4468 | { 447, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #447 = AMSWAP_D |
| 4469 | { 446, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #446 = AMSWAP_B |
| 4470 | { 445, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #445 = AMOR__DB_W |
| 4471 | { 444, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #444 = AMOR__DB_D |
| 4472 | { 443, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #443 = AMOR_W |
| 4473 | { 442, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #442 = AMOR_D |
| 4474 | { 441, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #441 = AMMIN__DB_WU |
| 4475 | { 440, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #440 = AMMIN__DB_W |
| 4476 | { 439, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #439 = AMMIN__DB_DU |
| 4477 | { 438, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #438 = AMMIN__DB_D |
| 4478 | { 437, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #437 = AMMIN_WU |
| 4479 | { 436, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #436 = AMMIN_W |
| 4480 | { 435, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #435 = AMMIN_DU |
| 4481 | { 434, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #434 = AMMIN_D |
| 4482 | { 433, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #433 = AMMAX__DB_WU |
| 4483 | { 432, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #432 = AMMAX__DB_W |
| 4484 | { 431, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #431 = AMMAX__DB_DU |
| 4485 | { 430, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #430 = AMMAX__DB_D |
| 4486 | { 429, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #429 = AMMAX_WU |
| 4487 | { 428, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #428 = AMMAX_W |
| 4488 | { 427, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #427 = AMMAX_DU |
| 4489 | { 426, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #426 = AMMAX_D |
| 4490 | { 425, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #425 = AMCAS__DB_W |
| 4491 | { 424, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #424 = AMCAS__DB_H |
| 4492 | { 423, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #423 = AMCAS__DB_D |
| 4493 | { 422, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #422 = AMCAS__DB_B |
| 4494 | { 421, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #421 = AMCAS_W |
| 4495 | { 420, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #420 = AMCAS_H |
| 4496 | { 419, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #419 = AMCAS_D |
| 4497 | { 418, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #418 = AMCAS_B |
| 4498 | { 417, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #417 = AMAND__DB_W |
| 4499 | { 416, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #416 = AMAND__DB_D |
| 4500 | { 415, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #415 = AMAND_W |
| 4501 | { 414, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #414 = AMAND_D |
| 4502 | { 413, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #413 = AMADD__DB_W |
| 4503 | { 412, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #412 = AMADD__DB_H |
| 4504 | { 411, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #411 = AMADD__DB_D |
| 4505 | { 410, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #410 = AMADD__DB_B |
| 4506 | { 409, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #409 = AMADD_W |
| 4507 | { 408, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #408 = AMADD_H |
| 4508 | { 407, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #407 = AMADD_D |
| 4509 | { 406, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #406 = AMADD_B |
| 4510 | { 405, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #405 = ALSL_WU |
| 4511 | { 404, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #404 = ALSL_W |
| 4512 | { 403, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0, 0x0ULL }, // Inst #403 = ALSL_D |
| 4513 | { 402, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #402 = ADD_W |
| 4514 | { 401, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #401 = ADD_D |
| 4515 | { 400, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #400 = ADDU16I_D |
| 4516 | { 399, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #399 = ADDU12I_W |
| 4517 | { 398, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #398 = ADDU12I_D |
| 4518 | { 397, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0, 0x0ULL }, // Inst #397 = ADDI_W |
| 4519 | { 396, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #396 = ADDI_D |
| 4520 | { 395, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #395 = ADC_W |
| 4521 | { 394, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #394 = ADC_H |
| 4522 | { 393, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #393 = ADC_D |
| 4523 | { 392, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0, 0x0ULL }, // Inst #392 = ADC_B |
| 4524 | { 391, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 216, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #391 = WRFCSR |
| 4525 | { 390, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #390 = RDFCSR |
| 4526 | { 389, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #389 = PseudoXVREPLI_W |
| 4527 | { 388, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #388 = PseudoXVREPLI_H |
| 4528 | { 387, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #387 = PseudoXVREPLI_D |
| 4529 | { 386, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 214, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #386 = PseudoXVREPLI_B |
| 4530 | { 385, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #385 = PseudoXVINSGR2VR_H |
| 4531 | { 384, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #384 = PseudoXVINSGR2VR_B |
| 4532 | { 383, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #383 = PseudoXVBZ_W |
| 4533 | { 382, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #382 = PseudoXVBZ_H |
| 4534 | { 381, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #381 = PseudoXVBZ_D |
| 4535 | { 380, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #380 = PseudoXVBZ_B |
| 4536 | { 379, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #379 = PseudoXVBZ |
| 4537 | { 378, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #378 = PseudoXVBNZ_W |
| 4538 | { 377, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #377 = PseudoXVBNZ_H |
| 4539 | { 376, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #376 = PseudoXVBNZ_D |
| 4540 | { 375, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #375 = PseudoXVBNZ_B |
| 4541 | { 374, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #374 = PseudoXVBNZ |
| 4542 | { 373, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #373 = PseudoVREPLI_W |
| 4543 | { 372, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #372 = PseudoVREPLI_H |
| 4544 | { 371, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #371 = PseudoVREPLI_D |
| 4545 | { 370, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 206, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #370 = PseudoVREPLI_B |
| 4546 | { 369, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #369 = PseudoVBZ_W |
| 4547 | { 368, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #368 = PseudoVBZ_H |
| 4548 | { 367, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #367 = PseudoVBZ_D |
| 4549 | { 366, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #366 = PseudoVBZ_B |
| 4550 | { 365, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #365 = PseudoVBZ |
| 4551 | { 364, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #364 = PseudoVBNZ_W |
| 4552 | { 363, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #363 = PseudoVBNZ_H |
| 4553 | { 362, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #362 = PseudoVBNZ_D |
| 4554 | { 361, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #361 = PseudoVBNZ_B |
| 4555 | { 360, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #360 = PseudoVBNZ |
| 4556 | { 359, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #359 = PseudoUNIMP |
| 4557 | { 358, 1, 0, 8, 0, 1, 1, LoongArchImpOpBase + 15, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #358 = PseudoTAIL_MEDIUM |
| 4558 | { 357, 1, 0, 24, 0, 1, 2, LoongArchImpOpBase + 12, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #357 = PseudoTAIL_LARGE |
| 4559 | { 356, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #356 = PseudoTAILIndirect |
| 4560 | { 355, 2, 0, 8, 0, 1, 0, LoongArchImpOpBase + 2, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #355 = PseudoTAIL36 |
| 4561 | { 354, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #354 = PseudoTAIL |
| 4562 | { 353, 3, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #353 = PseudoST_CFR |
| 4563 | { 352, 0, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #352 = PseudoRET |
| 4564 | { 351, 7, 2, 44, 0, 0, 0, LoongArchImpOpBase + 0, 196, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #351 = PseudoMaskedCmpXchg32 |
| 4565 | { 350, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #350 = PseudoMaskedAtomicSwap32 |
| 4566 | { 349, 7, 3, 48, 0, 0, 0, LoongArchImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #349 = PseudoMaskedAtomicLoadUMin32 |
| 4567 | { 348, 7, 3, 48, 0, 0, 0, LoongArchImpOpBase + 0, 189, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #348 = PseudoMaskedAtomicLoadUMax32 |
| 4568 | { 347, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #347 = PseudoMaskedAtomicLoadSub32 |
| 4569 | { 346, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #346 = PseudoMaskedAtomicLoadNand32 |
| 4570 | { 345, 8, 3, 56, 0, 0, 0, LoongArchImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #345 = PseudoMaskedAtomicLoadMin32 |
| 4571 | { 344, 8, 3, 56, 0, 0, 0, LoongArchImpOpBase + 0, 181, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #344 = PseudoMaskedAtomicLoadMax32 |
| 4572 | { 343, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #343 = PseudoMaskedAtomicLoadAdd32 |
| 4573 | { 342, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #342 = PseudoLI_W |
| 4574 | { 341, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #341 = PseudoLI_D |
| 4575 | { 340, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #340 = PseudoLD_CFR |
| 4576 | { 339, 2, 1, 20, 0, 0, 1, LoongArchImpOpBase + 8, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #339 = PseudoLA_TLS_LE |
| 4577 | { 338, 3, 1, 20, 0, 0, 1, LoongArchImpOpBase + 8, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #338 = PseudoLA_TLS_LD_LARGE |
| 4578 | { 337, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #337 = PseudoLA_TLS_LD |
| 4579 | { 336, 3, 1, 20, 0, 0, 1, LoongArchImpOpBase + 8, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #336 = PseudoLA_TLS_IE_LARGE |
| 4580 | { 335, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #335 = PseudoLA_TLS_IE |
| 4581 | { 334, 3, 1, 20, 0, 0, 1, LoongArchImpOpBase + 8, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #334 = PseudoLA_TLS_GD_LARGE |
| 4582 | { 333, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #333 = PseudoLA_TLS_GD |
| 4583 | { 332, 3, 1, 32, 0, 0, 3, LoongArchImpOpBase + 9, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #332 = PseudoLA_TLS_DESC_PC_LARGE |
| 4584 | { 331, 2, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #331 = PseudoLA_TLS_DESC_PC |
| 4585 | { 330, 3, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #330 = PseudoLA_TLS_DESC_ABS_LARGE |
| 4586 | { 329, 2, 1, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #329 = PseudoLA_TLS_DESC_ABS |
| 4587 | { 328, 3, 1, 20, 0, 0, 1, LoongArchImpOpBase + 8, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #328 = PseudoLA_PCREL_LARGE |
| 4588 | { 327, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #327 = PseudoLA_PCREL |
| 4589 | { 326, 3, 1, 20, 0, 0, 1, LoongArchImpOpBase + 8, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #326 = PseudoLA_GOT_LARGE |
| 4590 | { 325, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #325 = PseudoLA_GOT |
| 4591 | { 324, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #324 = PseudoLA_ABS_LARGE |
| 4592 | { 323, 2, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #323 = PseudoLA_ABS |
| 4593 | { 322, 2, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #322 = PseudoJIRL_TAIL |
| 4594 | { 321, 2, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #321 = PseudoJIRL_CALL |
| 4595 | { 320, 3, 1, 4, 0, 1, 1, LoongArchImpOpBase + 6, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #320 = PseudoDESC_CALL |
| 4596 | { 319, 2, 1, 12, 0, 0, 0, LoongArchImpOpBase + 0, 173, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #319 = PseudoCopyCFR |
| 4597 | { 318, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #318 = PseudoCmpXchg64 |
| 4598 | { 317, 6, 2, 36, 0, 0, 0, LoongArchImpOpBase + 0, 167, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #317 = PseudoCmpXchg32 |
| 4599 | { 316, 1, 0, 8, 0, 0, 2, LoongArchImpOpBase + 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #316 = PseudoCALL_MEDIUM |
| 4600 | { 315, 1, 0, 24, 0, 0, 2, LoongArchImpOpBase + 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #315 = PseudoCALL_LARGE |
| 4601 | { 314, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #314 = PseudoCALLIndirect |
| 4602 | { 313, 1, 0, 8, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #313 = PseudoCALL36 |
| 4603 | { 312, 1, 0, 4, 0, 0, 1, LoongArchImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL }, // Inst #312 = PseudoCALL |
| 4604 | { 311, 1, 0, 4, 0, 1, 0, LoongArchImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #311 = PseudoB_TAIL |
| 4605 | { 310, 2, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 164, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #310 = PseudoBRIND |
| 4606 | { 309, 1, 0, 4, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #309 = PseudoBR |
| 4607 | { 308, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #308 = PseudoAtomicSwap32 |
| 4608 | { 307, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #307 = PseudoAtomicStoreW |
| 4609 | { 306, 3, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 161, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #306 = PseudoAtomicStoreD |
| 4610 | { 305, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #305 = PseudoAtomicLoadXor32 |
| 4611 | { 304, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #304 = PseudoAtomicLoadSub32 |
| 4612 | { 303, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #303 = PseudoAtomicLoadOr32 |
| 4613 | { 302, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #302 = PseudoAtomicLoadNand64 |
| 4614 | { 301, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #301 = PseudoAtomicLoadNand32 |
| 4615 | { 300, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #300 = PseudoAtomicLoadAnd32 |
| 4616 | { 299, 5, 2, 24, 0, 0, 0, LoongArchImpOpBase + 0, 156, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #299 = PseudoAtomicLoadAdd32 |
| 4617 | { 298, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #298 = PseudoAddTPRel_W |
| 4618 | { 297, 4, 1, 4, 0, 0, 0, LoongArchImpOpBase + 0, 152, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #297 = PseudoAddTPRel_D |
| 4619 | { 296, 2, 0, 4, 0, 1, 1, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #296 = ADJCALLSTACKUP |
| 4620 | { 295, 2, 0, 4, 0, 1, 1, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #295 = ADJCALLSTACKDOWN |
| 4621 | { 294, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #294 = G_UBFX |
| 4622 | { 293, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #293 = G_SBFX |
| 4623 | { 292, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN |
| 4624 | { 291, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX |
| 4625 | { 290, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN |
| 4626 | { 289, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX |
| 4627 | { 288, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR |
| 4628 | { 287, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR |
| 4629 | { 286, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND |
| 4630 | { 285, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL |
| 4631 | { 284, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD |
| 4632 | { 283, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM |
| 4633 | { 282, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM |
| 4634 | { 281, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN |
| 4635 | { 280, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX |
| 4636 | { 279, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL |
| 4637 | { 278, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD |
| 4638 | { 277, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL |
| 4639 | { 276, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD |
| 4640 | { 275, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #275 = G_UBSANTRAP |
| 4641 | { 274, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #274 = G_DEBUGTRAP |
| 4642 | { 273, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = G_TRAP |
| 4643 | { 272, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #272 = G_BZERO |
| 4644 | { 271, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #271 = G_MEMSET |
| 4645 | { 270, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #270 = G_MEMMOVE |
| 4646 | { 269, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE |
| 4647 | { 268, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #268 = G_MEMCPY |
| 4648 | { 267, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER |
| 4649 | { 266, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER |
| 4650 | { 265, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP |
| 4651 | { 264, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT |
| 4652 | { 263, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #263 = G_STRICT_FMA |
| 4653 | { 262, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #262 = G_STRICT_FREM |
| 4654 | { 261, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #261 = G_STRICT_FDIV |
| 4655 | { 260, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #260 = G_STRICT_FMUL |
| 4656 | { 259, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #259 = G_STRICT_FSUB |
| 4657 | { 258, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #258 = G_STRICT_FADD |
| 4658 | { 257, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #257 = G_STACKRESTORE |
| 4659 | { 256, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #256 = G_STACKSAVE |
| 4660 | { 255, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC |
| 4661 | { 254, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_JUMP_TABLE |
| 4662 | { 253, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR |
| 4663 | { 252, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST |
| 4664 | { 251, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #251 = G_FNEARBYINT |
| 4665 | { 250, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #250 = G_FRINT |
| 4666 | { 249, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #249 = G_FFLOOR |
| 4667 | { 248, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #248 = G_FSQRT |
| 4668 | { 247, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #247 = G_FTANH |
| 4669 | { 246, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #246 = G_FSINH |
| 4670 | { 245, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #245 = G_FCOSH |
| 4671 | { 244, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #244 = G_FATAN |
| 4672 | { 243, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #243 = G_FASIN |
| 4673 | { 242, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #242 = G_FACOS |
| 4674 | { 241, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #241 = G_FTAN |
| 4675 | { 240, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #240 = G_FSIN |
| 4676 | { 239, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #239 = G_FCOS |
| 4677 | { 238, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #238 = G_FCEIL |
| 4678 | { 237, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #237 = G_BITREVERSE |
| 4679 | { 236, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #236 = G_BSWAP |
| 4680 | { 235, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #235 = G_CTPOP |
| 4681 | { 234, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF |
| 4682 | { 233, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_CTLZ |
| 4683 | { 232, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF |
| 4684 | { 231, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_CTTZ |
| 4685 | { 230, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS |
| 4686 | { 229, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR |
| 4687 | { 228, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR |
| 4688 | { 227, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT |
| 4689 | { 226, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT |
| 4690 | { 225, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR |
| 4691 | { 224, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR |
| 4692 | { 223, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_VSCALE |
| 4693 | { 222, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #222 = G_BRJT |
| 4694 | { 221, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #221 = G_BR |
| 4695 | { 220, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_LLROUND |
| 4696 | { 219, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_LROUND |
| 4697 | { 218, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_ABS |
| 4698 | { 217, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #217 = G_UMAX |
| 4699 | { 216, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #216 = G_UMIN |
| 4700 | { 215, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #215 = G_SMAX |
| 4701 | { 214, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #214 = G_SMIN |
| 4702 | { 213, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #213 = G_PTRMASK |
| 4703 | { 212, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #212 = G_PTR_ADD |
| 4704 | { 211, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #211 = G_RESET_FPMODE |
| 4705 | { 210, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #210 = G_SET_FPMODE |
| 4706 | { 209, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #209 = G_GET_FPMODE |
| 4707 | { 208, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #208 = G_RESET_FPENV |
| 4708 | { 207, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #207 = G_SET_FPENV |
| 4709 | { 206, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #206 = G_GET_FPENV |
| 4710 | { 205, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_FMAXIMUM |
| 4711 | { 204, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #204 = G_FMINIMUM |
| 4712 | { 203, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE |
| 4713 | { 202, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE |
| 4714 | { 201, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #201 = G_FMAXNUM |
| 4715 | { 200, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #200 = G_FMINNUM |
| 4716 | { 199, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #199 = G_FCANONICALIZE |
| 4717 | { 198, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #198 = G_IS_FPCLASS |
| 4718 | { 197, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #197 = G_FCOPYSIGN |
| 4719 | { 196, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #196 = G_FABS |
| 4720 | { 195, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #195 = G_UITOFP |
| 4721 | { 194, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #194 = G_SITOFP |
| 4722 | { 193, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #193 = G_FPTOUI |
| 4723 | { 192, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #192 = G_FPTOSI |
| 4724 | { 191, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #191 = G_FPTRUNC |
| 4725 | { 190, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FPEXT |
| 4726 | { 189, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_FNEG |
| 4727 | { 188, 3, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FFREXP |
| 4728 | { 187, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FLDEXP |
| 4729 | { 186, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_FLOG10 |
| 4730 | { 185, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_FLOG2 |
| 4731 | { 184, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FLOG |
| 4732 | { 183, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FEXP10 |
| 4733 | { 182, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FEXP2 |
| 4734 | { 181, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FEXP |
| 4735 | { 180, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FPOWI |
| 4736 | { 179, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FPOW |
| 4737 | { 178, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FREM |
| 4738 | { 177, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FDIV |
| 4739 | { 176, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FMAD |
| 4740 | { 175, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FMA |
| 4741 | { 174, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #174 = G_FMUL |
| 4742 | { 173, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FSUB |
| 4743 | { 172, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #172 = G_FADD |
| 4744 | { 171, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT |
| 4745 | { 170, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT |
| 4746 | { 169, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_UDIVFIX |
| 4747 | { 168, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_SDIVFIX |
| 4748 | { 167, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #167 = G_UMULFIXSAT |
| 4749 | { 166, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #166 = G_SMULFIXSAT |
| 4750 | { 165, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_UMULFIX |
| 4751 | { 164, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #164 = G_SMULFIX |
| 4752 | { 163, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #163 = G_SSHLSAT |
| 4753 | { 162, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_USHLSAT |
| 4754 | { 161, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SSUBSAT |
| 4755 | { 160, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_USUBSAT |
| 4756 | { 159, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #159 = G_SADDSAT |
| 4757 | { 158, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UADDSAT |
| 4758 | { 157, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULH |
| 4759 | { 156, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULH |
| 4760 | { 155, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULO |
| 4761 | { 154, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #154 = G_UMULO |
| 4762 | { 153, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_SSUBE |
| 4763 | { 152, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBO |
| 4764 | { 151, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_SADDE |
| 4765 | { 150, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDO |
| 4766 | { 149, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #149 = G_USUBE |
| 4767 | { 148, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #148 = G_USUBO |
| 4768 | { 147, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #147 = G_UADDE |
| 4769 | { 146, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_UADDO |
| 4770 | { 145, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #145 = G_SELECT |
| 4771 | { 144, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_UCMP |
| 4772 | { 143, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SCMP |
| 4773 | { 142, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_FCMP |
| 4774 | { 141, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #141 = G_ICMP |
| 4775 | { 140, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_ROTL |
| 4776 | { 139, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_ROTR |
| 4777 | { 138, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_FSHR |
| 4778 | { 137, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #137 = G_FSHL |
| 4779 | { 136, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_ASHR |
| 4780 | { 135, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_LSHR |
| 4781 | { 134, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_SHL |
| 4782 | { 133, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ZEXT |
| 4783 | { 132, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_SEXT_INREG |
| 4784 | { 131, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_SEXT |
| 4785 | { 130, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #130 = G_VAARG |
| 4786 | { 129, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #129 = G_VASTART |
| 4787 | { 128, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_FCONSTANT |
| 4788 | { 127, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_CONSTANT |
| 4789 | { 126, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_TRUNC |
| 4790 | { 125, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_ANYEXT |
| 4791 | { 124, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
| 4792 | { 123, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT |
| 4793 | { 122, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS |
| 4794 | { 121, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #121 = G_INTRINSIC |
| 4795 | { 120, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START |
| 4796 | { 119, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #119 = G_BRINDIRECT |
| 4797 | { 118, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #118 = G_BRCOND |
| 4798 | { 117, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #117 = G_PREFETCH |
| 4799 | { 116, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #116 = G_FENCE |
| 4800 | { 115, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP |
| 4801 | { 114, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP |
| 4802 | { 113, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN |
| 4803 | { 112, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX |
| 4804 | { 111, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB |
| 4805 | { 110, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD |
| 4806 | { 109, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN |
| 4807 | { 108, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX |
| 4808 | { 107, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN |
| 4809 | { 106, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX |
| 4810 | { 105, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR |
| 4811 | { 104, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR |
| 4812 | { 103, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND |
| 4813 | { 102, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND |
| 4814 | { 101, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB |
| 4815 | { 100, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD |
| 4816 | { 99, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG |
| 4817 | { 98, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG |
| 4818 | { 97, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 4819 | { 96, 5, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_INDEXED_STORE |
| 4820 | { 95, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_STORE |
| 4821 | { 94, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD |
| 4822 | { 93, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD |
| 4823 | { 92, 5, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD |
| 4824 | { 91, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #91 = G_ZEXTLOAD |
| 4825 | { 90, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #90 = G_SEXTLOAD |
| 4826 | { 89, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #89 = G_LOAD |
| 4827 | { 88, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER |
| 4828 | { 87, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER |
| 4829 | { 86, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN |
| 4830 | { 85, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT |
| 4831 | { 84, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT |
| 4832 | { 83, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND |
| 4833 | { 82, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC |
| 4834 | { 81, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND |
| 4835 | { 80, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER |
| 4836 | { 79, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_FREEZE |
| 4837 | { 78, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_BITCAST |
| 4838 | { 77, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTTOPTR |
| 4839 | { 76, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_PTRTOINT |
| 4840 | { 75, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS |
| 4841 | { 74, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC |
| 4842 | { 73, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR |
| 4843 | { 72, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #72 = G_MERGE_VALUES |
| 4844 | { 71, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_INSERT |
| 4845 | { 70, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES |
| 4846 | { 69, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #69 = G_EXTRACT |
| 4847 | { 68, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL |
| 4848 | { 67, 5, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE |
| 4849 | { 66, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE |
| 4850 | { 65, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #65 = G_FRAME_INDEX |
| 4851 | { 64, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #64 = G_PHI |
| 4852 | { 63, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF |
| 4853 | { 62, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #62 = G_XOR |
| 4854 | { 61, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #61 = G_OR |
| 4855 | { 60, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #60 = G_AND |
| 4856 | { 59, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_UDIVREM |
| 4857 | { 58, 4, 2, 0, 0, 0, 0, LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #58 = G_SDIVREM |
| 4858 | { 57, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #57 = G_UREM |
| 4859 | { 56, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #56 = G_SREM |
| 4860 | { 55, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIV |
| 4861 | { 54, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIV |
| 4862 | { 53, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #53 = G_MUL |
| 4863 | { 52, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SUB |
| 4864 | { 51, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #51 = G_ADD |
| 4865 | { 50, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN |
| 4866 | { 49, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT |
| 4867 | { 48, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT |
| 4868 | { 47, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE |
| 4869 | { 46, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP |
| 4870 | { 45, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR |
| 4871 | { 44, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY |
| 4872 | { 43, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO |
| 4873 | { 42, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER |
| 4874 | { 41, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL |
| 4875 | { 40, 3, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL |
| 4876 | { 39, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL |
| 4877 | { 38, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL |
| 4878 | { 37, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT |
| 4879 | { 36, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET |
| 4880 | { 35, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER |
| 4881 | { 34, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP |
| 4882 | { 33, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP |
| 4883 | { 32, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE |
| 4884 | { 31, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT |
| 4885 | { 30, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG |
| 4886 | { 29, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP |
| 4887 | { 28, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD |
| 4888 | { 27, 6, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT |
| 4889 | { 26, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL |
| 4890 | { 25, 2, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP |
| 4891 | { 24, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE |
| 4892 | { 23, 4, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE |
| 4893 | { 22, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END |
| 4894 | { 21, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START |
| 4895 | { 20, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE |
| 4896 | { 19, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY |
| 4897 | { 18, 2, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE |
| 4898 | { 17, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL |
| 4899 | { 16, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI |
| 4900 | { 15, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF |
| 4901 | { 14, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST |
| 4902 | { 13, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE |
| 4903 | { 12, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS |
| 4904 | { 11, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG |
| 4905 | { 10, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF |
| 4906 | { 9, 4, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG |
| 4907 | { 8, 3, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG |
| 4908 | { 7, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL |
| 4909 | { 6, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL |
| 4910 | { 5, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL |
| 4911 | { 4, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL |
| 4912 | { 3, 1, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION |
| 4913 | { 2, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR |
| 4914 | { 1, 0, 0, 0, 0, 0, 0, LoongArchImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM |
| 4915 | { 0, 1, 1, 0, 0, 0, 0, LoongArchImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI |
| 4916 | }, { |
| 4917 | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4918 | /* 1 */ |
| 4919 | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4920 | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4921 | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4922 | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4923 | /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4924 | /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4925 | /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
| 4926 | /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4927 | /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4928 | /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
| 4929 | /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4930 | /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4931 | /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4932 | /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4933 | /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4934 | /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4935 | /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4936 | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4937 | /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4938 | /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4939 | /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4940 | /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4941 | /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4942 | /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4943 | /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4944 | /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4945 | /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4946 | /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4947 | /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4948 | /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4949 | /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
| 4950 | /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4951 | /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4952 | /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4953 | /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4954 | /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4955 | /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4956 | /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4957 | /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4958 | /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 4959 | /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
| 4960 | /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4961 | /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4962 | /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
| 4963 | /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
| 4964 | /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
| 4965 | /* 152 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4966 | /* 156 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4967 | /* 161 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4968 | /* 164 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4969 | /* 166 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4970 | /* 167 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4971 | /* 173 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4972 | /* 175 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4973 | /* 178 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4974 | /* 181 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4975 | /* 189 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4976 | /* 196 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4977 | /* 203 */ { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4978 | /* 204 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4979 | /* 206 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4980 | /* 208 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4981 | /* 210 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4982 | /* 214 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4983 | /* 216 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4984 | /* 218 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4985 | /* 221 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4986 | /* 224 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4987 | /* 226 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4988 | /* 228 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4989 | /* 233 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4990 | /* 237 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4991 | /* 240 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4992 | /* 243 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 4993 | /* 247 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4994 | /* 249 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4995 | /* 251 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4996 | /* 254 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4997 | /* 257 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4998 | /* 260 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 4999 | /* 263 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5000 | /* 265 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5001 | /* 267 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5002 | /* 270 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5003 | /* 273 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5004 | /* 276 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5005 | /* 279 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5006 | /* 283 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5007 | /* 287 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5008 | /* 291 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5009 | /* 295 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5010 | /* 297 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5011 | /* 299 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5012 | /* 301 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5013 | /* 303 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5014 | /* 305 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5015 | /* 307 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5016 | /* 309 */ { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5017 | /* 311 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5018 | /* 314 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5019 | /* 316 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5020 | /* 318 */ { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5021 | /* 320 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5022 | /* 322 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5023 | /* 325 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5024 | /* 328 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5025 | /* 332 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5026 | /* 333 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5027 | /* 336 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5028 | /* 339 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5029 | /* 343 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5030 | /* 347 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5031 | /* 349 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5032 | /* 351 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5033 | /* 355 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5034 | /* 359 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5035 | /* 362 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5036 | /* 365 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5037 | /* 368 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5038 | /* 370 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5039 | /* 373 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5040 | /* 375 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5041 | /* 379 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5042 | /* 382 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5043 | /* 385 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5044 | /* 389 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5045 | /* 393 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5046 | /* 397 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5047 | /* 400 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5048 | /* 403 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5049 | /* 406 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5050 | /* 408 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5051 | /* 411 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
| 5052 | /* 413 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
| 5053 | }, { |
| 5054 | /* 0 */ |
| 5055 | /* 0 */ LoongArch::R3, LoongArch::R3, |
| 5056 | /* 2 */ LoongArch::R3, |
| 5057 | /* 3 */ LoongArch::R1, |
| 5058 | /* 4 */ LoongArch::R1, LoongArch::R20, |
| 5059 | /* 6 */ LoongArch::R4, LoongArch::R4, |
| 5060 | /* 8 */ LoongArch::R20, |
| 5061 | /* 9 */ LoongArch::R1, LoongArch::R4, LoongArch::R20, |
| 5062 | /* 12 */ LoongArch::R3, LoongArch::R19, LoongArch::R20, |
| 5063 | /* 15 */ LoongArch::R3, LoongArch::R20, |
| 5064 | } |
| 5065 | }; |
| 5066 | |
| 5067 | |
| 5068 | #ifdef __GNUC__ |
| 5069 | #pragma GCC diagnostic push |
| 5070 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 5071 | #endif |
| 5072 | extern const char LoongArchInstrNameData[] = { |
| 5073 | /* 0 */ "G_FLOG10\0" |
| 5074 | /* 9 */ "G_FEXP10\0" |
| 5075 | /* 18 */ "JISCR0\0" |
| 5076 | /* 25 */ "JISCR1\0" |
| 5077 | /* 32 */ "PseudoMaskedAtomicLoadSub32\0" |
| 5078 | /* 60 */ "PseudoAtomicLoadSub32\0" |
| 5079 | /* 82 */ "PseudoMaskedAtomicLoadAdd32\0" |
| 5080 | /* 110 */ "PseudoAtomicLoadAdd32\0" |
| 5081 | /* 132 */ "PseudoAtomicLoadAnd32\0" |
| 5082 | /* 154 */ "PseudoMaskedAtomicLoadNand32\0" |
| 5083 | /* 183 */ "PseudoAtomicLoadNand32\0" |
| 5084 | /* 206 */ "PseudoMaskedCmpXchg32\0" |
| 5085 | /* 228 */ "PseudoCmpXchg32\0" |
| 5086 | /* 244 */ "PseudoMaskedAtomicLoadUMin32\0" |
| 5087 | /* 273 */ "PseudoMaskedAtomicLoadMin32\0" |
| 5088 | /* 301 */ "PseudoMaskedAtomicSwap32\0" |
| 5089 | /* 326 */ "PseudoAtomicSwap32\0" |
| 5090 | /* 345 */ "PseudoAtomicLoadOr32\0" |
| 5091 | /* 366 */ "PseudoAtomicLoadXor32\0" |
| 5092 | /* 388 */ "PseudoMaskedAtomicLoadUMax32\0" |
| 5093 | /* 417 */ "PseudoMaskedAtomicLoadMax32\0" |
| 5094 | /* 445 */ "G_FLOG2\0" |
| 5095 | /* 453 */ "G_FEXP2\0" |
| 5096 | /* 461 */ "MOVFR2GR_S_64\0" |
| 5097 | /* 475 */ "MOVGR2FR_W_64\0" |
| 5098 | /* 489 */ "PseudoAtomicLoadNand64\0" |
| 5099 | /* 512 */ "PseudoCmpXchg64\0" |
| 5100 | /* 528 */ "PseudoTAIL36\0" |
| 5101 | /* 541 */ "PseudoCALL36\0" |
| 5102 | /* 554 */ "G_FMA\0" |
| 5103 | /* 560 */ "G_STRICT_FMA\0" |
| 5104 | /* 573 */ "BITREV_4B\0" |
| 5105 | /* 583 */ "BITREV_8B\0" |
| 5106 | /* 593 */ "INVTLB\0" |
| 5107 | /* 600 */ "G_FSUB\0" |
| 5108 | /* 607 */ "G_STRICT_FSUB\0" |
| 5109 | /* 621 */ "G_ATOMICRMW_FSUB\0" |
| 5110 | /* 638 */ "G_SUB\0" |
| 5111 | /* 644 */ "G_ATOMICRMW_SUB\0" |
| 5112 | /* 660 */ "XVREPLVE0_B\0" |
| 5113 | /* 672 */ "XVADDA_B\0" |
| 5114 | /* 681 */ "X86SRA_B\0" |
| 5115 | /* 690 */ "XVSRA_B\0" |
| 5116 | /* 698 */ "AMADD__DB_B\0" |
| 5117 | /* 710 */ "AMSWAP__DB_B\0" |
| 5118 | /* 723 */ "AMCAS__DB_B\0" |
| 5119 | /* 735 */ "X86SUB_B\0" |
| 5120 | /* 744 */ "XVMSUB_B\0" |
| 5121 | /* 753 */ "XVSSUB_B\0" |
| 5122 | /* 762 */ "XVSUB_B\0" |
| 5123 | /* 770 */ "X86SBC_B\0" |
| 5124 | /* 779 */ "X86ADC_B\0" |
| 5125 | /* 788 */ "X86DEC_B\0" |
| 5126 | /* 797 */ "X86INC_B\0" |
| 5127 | /* 806 */ "X86ADD_B\0" |
| 5128 | /* 815 */ "AMADD_B\0" |
| 5129 | /* 823 */ "XVMADD_B\0" |
| 5130 | /* 832 */ "XVSADD_B\0" |
| 5131 | /* 841 */ "XVADD_B\0" |
| 5132 | /* 849 */ "LD_B\0" |
| 5133 | /* 854 */ "X86AND_B\0" |
| 5134 | /* 863 */ "XVPACKOD_B\0" |
| 5135 | /* 874 */ "XVPICKOD_B\0" |
| 5136 | /* 885 */ "XVMOD_B\0" |
| 5137 | /* 893 */ "IOCSRRD_B\0" |
| 5138 | /* 903 */ "XVABSD_B\0" |
| 5139 | /* 912 */ "VEXT2XV_D_B\0" |
| 5140 | /* 924 */ "LDLE_B\0" |
| 5141 | /* 931 */ "XVSLE_B\0" |
| 5142 | /* 939 */ "STLE_B\0" |
| 5143 | /* 946 */ "XVREPLVE_B\0" |
| 5144 | /* 957 */ "XVSHUF_B\0" |
| 5145 | /* 966 */ "XVNEG_B\0" |
| 5146 | /* 974 */ "XVAVG_B\0" |
| 5147 | /* 982 */ "XVMUH_B\0" |
| 5148 | /* 990 */ "XVILVH_B\0" |
| 5149 | /* 999 */ "XVSUBWOD_H_B\0" |
| 5150 | /* 1012 */ "XVMADDWOD_H_B\0" |
| 5151 | /* 1026 */ "XVADDWOD_H_B\0" |
| 5152 | /* 1039 */ "XVMULWOD_H_B\0" |
| 5153 | /* 1052 */ "XVEXTH_H_B\0" |
| 5154 | /* 1063 */ "XVSLLWIL_H_B\0" |
| 5155 | /* 1076 */ "XVSUBWEV_H_B\0" |
| 5156 | /* 1089 */ "XVMADDWEV_H_B\0" |
| 5157 | /* 1103 */ "XVADDWEV_H_B\0" |
| 5158 | /* 1116 */ "XVMULWEV_H_B\0" |
| 5159 | /* 1129 */ "VEXT2XV_H_B\0" |
| 5160 | /* 1141 */ "XVHSUBW_H_B\0" |
| 5161 | /* 1153 */ "XVHADDW_H_B\0" |
| 5162 | /* 1165 */ "XVSHUF4I_B\0" |
| 5163 | /* 1176 */ "X86SRAI_B\0" |
| 5164 | /* 1186 */ "XVSRAI_B\0" |
| 5165 | /* 1195 */ "XVANDI_B\0" |
| 5166 | /* 1204 */ "XVSLEI_B\0" |
| 5167 | /* 1213 */ "XVREPL128VEI_B\0" |
| 5168 | /* 1228 */ "VREPLVEI_B\0" |
| 5169 | /* 1239 */ "X86RCLI_B\0" |
| 5170 | /* 1249 */ "XVBITSELI_B\0" |
| 5171 | /* 1261 */ "X86SLLI_B\0" |
| 5172 | /* 1271 */ "XVSLLI_B\0" |
| 5173 | /* 1280 */ "PseudoXVREPLI_B\0" |
| 5174 | /* 1296 */ "PseudoVREPLI_B\0" |
| 5175 | /* 1311 */ "X86SRLI_B\0" |
| 5176 | /* 1321 */ "XVSRLI_B\0" |
| 5177 | /* 1330 */ "X86ROTLI_B\0" |
| 5178 | /* 1341 */ "XVMINI_B\0" |
| 5179 | /* 1350 */ "XVFRSTPI_B\0" |
| 5180 | /* 1361 */ "XVSEQI_B\0" |
| 5181 | /* 1370 */ "XVSRARI_B\0" |
| 5182 | /* 1380 */ "X86RCRI_B\0" |
| 5183 | /* 1390 */ "XVBITCLRI_B\0" |
| 5184 | /* 1402 */ "XVSRLRI_B\0" |
| 5185 | /* 1412 */ "XVNORI_B\0" |
| 5186 | /* 1421 */ "XVORI_B\0" |
| 5187 | /* 1429 */ "XVXORI_B\0" |
| 5188 | /* 1438 */ "X86ROTRI_B\0" |
| 5189 | /* 1449 */ "XVROTRI_B\0" |
| 5190 | /* 1459 */ "XVBITSETI_B\0" |
| 5191 | /* 1471 */ "XVSLTI_B\0" |
| 5192 | /* 1480 */ "XVBITREVI_B\0" |
| 5193 | /* 1492 */ "XVMAXI_B\0" |
| 5194 | /* 1501 */ "X86RCL_B\0" |
| 5195 | /* 1510 */ "X86SLL_B\0" |
| 5196 | /* 1519 */ "XVSLL_B\0" |
| 5197 | /* 1527 */ "XVLDREPL_B\0" |
| 5198 | /* 1538 */ "X86SRL_B\0" |
| 5199 | /* 1547 */ "XVSRL_B\0" |
| 5200 | /* 1555 */ "X86ROTL_B\0" |
| 5201 | /* 1565 */ "X86MUL_B\0" |
| 5202 | /* 1574 */ "XVMUL_B\0" |
| 5203 | /* 1582 */ "XVILVL_B\0" |
| 5204 | /* 1591 */ "XVSTELM_B\0" |
| 5205 | /* 1601 */ "XVMIN_B\0" |
| 5206 | /* 1609 */ "XVCLO_B\0" |
| 5207 | /* 1617 */ "AMSWAP_B\0" |
| 5208 | /* 1626 */ "XVFRSTP_B\0" |
| 5209 | /* 1636 */ "XVSEQ_B\0" |
| 5210 | /* 1644 */ "XVSRAR_B\0" |
| 5211 | /* 1653 */ "X86RCR_B\0" |
| 5212 | /* 1662 */ "VPICKVE2GR_B\0" |
| 5213 | /* 1675 */ "XVAVGR_B\0" |
| 5214 | /* 1684 */ "XVBITCLR_B\0" |
| 5215 | /* 1695 */ "XVSRLR_B\0" |
| 5216 | /* 1704 */ "X86OR_B\0" |
| 5217 | /* 1712 */ "X86XOR_B\0" |
| 5218 | /* 1721 */ "X86ROTR_B\0" |
| 5219 | /* 1731 */ "XVROTR_B\0" |
| 5220 | /* 1740 */ "XVREPLGR2VR_B\0" |
| 5221 | /* 1754 */ "PseudoXVINSGR2VR_B\0" |
| 5222 | /* 1773 */ "IOCSRWR_B\0" |
| 5223 | /* 1783 */ "AMCAS_B\0" |
| 5224 | /* 1791 */ "XVEXTRINS_B\0" |
| 5225 | /* 1803 */ "XVSAT_B\0" |
| 5226 | /* 1811 */ "XVBITSET_B\0" |
| 5227 | /* 1822 */ "LDGT_B\0" |
| 5228 | /* 1829 */ "STGT_B\0" |
| 5229 | /* 1836 */ "XVSLT_B\0" |
| 5230 | /* 1844 */ "XVPCNT_B\0" |
| 5231 | /* 1853 */ "ST_B\0" |
| 5232 | /* 1858 */ "XVMADDWOD_H_BU_B\0" |
| 5233 | /* 1875 */ "XVADDWOD_H_BU_B\0" |
| 5234 | /* 1891 */ "XVMULWOD_H_BU_B\0" |
| 5235 | /* 1907 */ "XVMADDWEV_H_BU_B\0" |
| 5236 | /* 1924 */ "XVADDWEV_H_BU_B\0" |
| 5237 | /* 1940 */ "XVMULWEV_H_BU_B\0" |
| 5238 | /* 1956 */ "XVPACKEV_B\0" |
| 5239 | /* 1967 */ "XVPICKEV_B\0" |
| 5240 | /* 1978 */ "XVBITREV_B\0" |
| 5241 | /* 1989 */ "XVDIV_B\0" |
| 5242 | /* 1997 */ "XVSIGNCOV_B\0" |
| 5243 | /* 2009 */ "EXT_W_B\0" |
| 5244 | /* 2017 */ "VEXT2XV_W_B\0" |
| 5245 | /* 2029 */ "XVMAX_B\0" |
| 5246 | /* 2037 */ "LDX_B\0" |
| 5247 | /* 2043 */ "STX_B\0" |
| 5248 | /* 2049 */ "PseudoXVBZ_B\0" |
| 5249 | /* 2062 */ "PseudoVBZ_B\0" |
| 5250 | /* 2074 */ "XVMSKGEZ_B\0" |
| 5251 | /* 2085 */ "XVSETALLNEZ_B\0" |
| 5252 | /* 2099 */ "XVCLZ_B\0" |
| 5253 | /* 2107 */ "PseudoXVBNZ_B\0" |
| 5254 | /* 2121 */ "PseudoVBNZ_B\0" |
| 5255 | /* 2134 */ "XVMSKNZ_B\0" |
| 5256 | /* 2144 */ "XVSETANYEQZ_B\0" |
| 5257 | /* 2158 */ "XVMSKLTZ_B\0" |
| 5258 | /* 2169 */ "G_INTRINSIC\0" |
| 5259 | /* 2181 */ "G_FPTRUNC\0" |
| 5260 | /* 2191 */ "G_INTRINSIC_TRUNC\0" |
| 5261 | /* 2209 */ "G_TRUNC\0" |
| 5262 | /* 2217 */ "G_BUILD_VECTOR_TRUNC\0" |
| 5263 | /* 2238 */ "G_DYN_STACKALLOC\0" |
| 5264 | /* 2255 */ "PseudoLA_TLS_DESC_PC\0" |
| 5265 | /* 2276 */ "G_FMAD\0" |
| 5266 | /* 2283 */ "G_INDEXED_SEXTLOAD\0" |
| 5267 | /* 2302 */ "G_SEXTLOAD\0" |
| 5268 | /* 2313 */ "G_INDEXED_ZEXTLOAD\0" |
| 5269 | /* 2332 */ "G_ZEXTLOAD\0" |
| 5270 | /* 2343 */ "G_INDEXED_LOAD\0" |
| 5271 | /* 2358 */ "G_LOAD\0" |
| 5272 | /* 2365 */ "G_VECREDUCE_FADD\0" |
| 5273 | /* 2382 */ "G_FADD\0" |
| 5274 | /* 2389 */ "G_VECREDUCE_SEQ_FADD\0" |
| 5275 | /* 2410 */ "G_STRICT_FADD\0" |
| 5276 | /* 2424 */ "G_ATOMICRMW_FADD\0" |
| 5277 | /* 2441 */ "G_VECREDUCE_ADD\0" |
| 5278 | /* 2457 */ "G_ADD\0" |
| 5279 | /* 2463 */ "G_PTR_ADD\0" |
| 5280 | /* 2473 */ "G_ATOMICRMW_ADD\0" |
| 5281 | /* 2489 */ "PseudoLA_TLS_GD\0" |
| 5282 | /* 2505 */ "PRELD\0" |
| 5283 | /* 2511 */ "XVLD\0" |
| 5284 | /* 2516 */ "FCVT_D_LD\0" |
| 5285 | /* 2526 */ "PseudoLA_TLS_LD\0" |
| 5286 | /* 2542 */ "G_ATOMICRMW_NAND\0" |
| 5287 | /* 2559 */ "G_VECREDUCE_AND\0" |
| 5288 | /* 2575 */ "G_AND\0" |
| 5289 | /* 2581 */ "G_ATOMICRMW_AND\0" |
| 5290 | /* 2597 */ "LIFETIME_END\0" |
| 5291 | /* 2610 */ "PseudoBRIND\0" |
| 5292 | /* 2622 */ "G_BRCOND\0" |
| 5293 | /* 2631 */ "G_LLROUND\0" |
| 5294 | /* 2641 */ "G_LROUND\0" |
| 5295 | /* 2650 */ "G_INTRINSIC_ROUND\0" |
| 5296 | /* 2668 */ "G_INTRINSIC_FPTRUNC_ROUND\0" |
| 5297 | /* 2694 */ "LOAD_STACK_GUARD\0" |
| 5298 | /* 2711 */ "TLBRD\0" |
| 5299 | /* 2717 */ "GCSRRD\0" |
| 5300 | /* 2724 */ "XVREPLVE0_D\0" |
| 5301 | /* 2736 */ "XVINSVE0_D\0" |
| 5302 | /* 2747 */ "XVADDA_D\0" |
| 5303 | /* 2756 */ "XVFMINA_D\0" |
| 5304 | /* 2766 */ "X86SRA_D\0" |
| 5305 | /* 2775 */ "XVSRA_D\0" |
| 5306 | /* 2783 */ "XVFMAXA_D\0" |
| 5307 | /* 2793 */ "AMADD__DB_D\0" |
| 5308 | /* 2805 */ "AMAND__DB_D\0" |
| 5309 | /* 2817 */ "AMMIN__DB_D\0" |
| 5310 | /* 2829 */ "AMSWAP__DB_D\0" |
| 5311 | /* 2842 */ "AMOR__DB_D\0" |
| 5312 | /* 2853 */ "AMXOR__DB_D\0" |
| 5313 | /* 2865 */ "AMCAS__DB_D\0" |
| 5314 | /* 2877 */ "AMMAX__DB_D\0" |
| 5315 | /* 2889 */ "FSCALEB_D\0" |
| 5316 | /* 2899 */ "XVFLOGB_D\0" |
| 5317 | /* 2909 */ "X86SUB_D\0" |
| 5318 | /* 2918 */ "XVFSUB_D\0" |
| 5319 | /* 2927 */ "XVFMSUB_D\0" |
| 5320 | /* 2937 */ "XVFNMSUB_D\0" |
| 5321 | /* 2948 */ "XVMSUB_D\0" |
| 5322 | /* 2957 */ "XVSSUB_D\0" |
| 5323 | /* 2966 */ "XVSUB_D\0" |
| 5324 | /* 2974 */ "REVB_D\0" |
| 5325 | /* 2981 */ "X86SBC_D\0" |
| 5326 | /* 2990 */ "X86ADC_D\0" |
| 5327 | /* 2999 */ "X86DEC_D\0" |
| 5328 | /* 3008 */ "X86INC_D\0" |
| 5329 | /* 3017 */ "SC_D\0" |
| 5330 | /* 3022 */ "X86ADD_D\0" |
| 5331 | /* 3031 */ "XVFADD_D\0" |
| 5332 | /* 3040 */ "AMADD_D\0" |
| 5333 | /* 3048 */ "XVFMADD_D\0" |
| 5334 | /* 3058 */ "XVFNMADD_D\0" |
| 5335 | /* 3069 */ "XVMADD_D\0" |
| 5336 | /* 3078 */ "XVSADD_D\0" |
| 5337 | /* 3087 */ "XVADD_D\0" |
| 5338 | /* 3095 */ "FLD_D\0" |
| 5339 | /* 3101 */ "FCVT_LD_D\0" |
| 5340 | /* 3111 */ "X86AND_D\0" |
| 5341 | /* 3120 */ "AMAND_D\0" |
| 5342 | /* 3128 */ "XVPACKOD_D\0" |
| 5343 | /* 3139 */ "XVPICKOD_D\0" |
| 5344 | /* 3150 */ "XVMOD_D\0" |
| 5345 | /* 3158 */ "IOCSRRD_D\0" |
| 5346 | /* 3168 */ "XVABSD_D\0" |
| 5347 | /* 3177 */ "FCVT_UD_D\0" |
| 5348 | /* 3187 */ "XVFCMP_CLE_D\0" |
| 5349 | /* 3200 */ "FLDLE_D\0" |
| 5350 | /* 3208 */ "XVSLE_D\0" |
| 5351 | /* 3216 */ "XVFCMP_SLE_D\0" |
| 5352 | /* 3229 */ "ASRTLE_D\0" |
| 5353 | /* 3238 */ "FSTLE_D\0" |
| 5354 | /* 3246 */ "XVFCMP_CULE_D\0" |
| 5355 | /* 3260 */ "XVFCMP_SULE_D\0" |
| 5356 | /* 3274 */ "RDTIME_D\0" |
| 5357 | /* 3283 */ "XVFCMP_CNE_D\0" |
| 5358 | /* 3296 */ "XVFRINTRNE_D\0" |
| 5359 | /* 3309 */ "XVFCMP_SNE_D\0" |
| 5360 | /* 3322 */ "XVFCMP_CUNE_D\0" |
| 5361 | /* 3336 */ "XVFCMP_SUNE_D\0" |
| 5362 | /* 3350 */ "XVFRECIPE_D\0" |
| 5363 | /* 3362 */ "XVFRSQRTE_D\0" |
| 5364 | /* 3374 */ "XVPICKVE_D\0" |
| 5365 | /* 3385 */ "XVREPLVE_D\0" |
| 5366 | /* 3396 */ "XVFCMP_CAF_D\0" |
| 5367 | /* 3409 */ "XVFCMP_SAF_D\0" |
| 5368 | /* 3422 */ "XVSHUF_D\0" |
| 5369 | /* 3431 */ "FNEG_D\0" |
| 5370 | /* 3438 */ "XVNEG_D\0" |
| 5371 | /* 3446 */ "XVAVG_D\0" |
| 5372 | /* 3454 */ "MULH_D\0" |
| 5373 | /* 3461 */ "XVMUH_D\0" |
| 5374 | /* 3469 */ "REVH_D\0" |
| 5375 | /* 3476 */ "XVILVH_D\0" |
| 5376 | /* 3485 */ "ADDU12I_D\0" |
| 5377 | /* 3495 */ "LU32I_D\0" |
| 5378 | /* 3503 */ "LU52I_D\0" |
| 5379 | /* 3511 */ "XVSHUF4I_D\0" |
| 5380 | /* 3522 */ "ADDU16I_D\0" |
| 5381 | /* 3532 */ "X86SRAI_D\0" |
| 5382 | /* 3542 */ "XVSRAI_D\0" |
| 5383 | /* 3551 */ "ADDI_D\0" |
| 5384 | /* 3558 */ "XVSLEI_D\0" |
| 5385 | /* 3567 */ "XVREPL128VEI_D\0" |
| 5386 | /* 3582 */ "VREPLVEI_D\0" |
| 5387 | /* 3593 */ "X86RCLI_D\0" |
| 5388 | /* 3603 */ "XVHSELI_D\0" |
| 5389 | /* 3613 */ "X86SLLI_D\0" |
| 5390 | /* 3623 */ "XVSLLI_D\0" |
| 5391 | /* 3632 */ "PseudoXVREPLI_D\0" |
| 5392 | /* 3648 */ "PseudoVREPLI_D\0" |
| 5393 | /* 3663 */ "X86SRLI_D\0" |
| 5394 | /* 3673 */ "XVSRLI_D\0" |
| 5395 | /* 3682 */ "X86ROTLI_D\0" |
| 5396 | /* 3693 */ "PseudoLI_D\0" |
| 5397 | /* 3704 */ "XVPERMI_D\0" |
| 5398 | /* 3714 */ "XVMINI_D\0" |
| 5399 | /* 3723 */ "XVSEQI_D\0" |
| 5400 | /* 3732 */ "XVSRARI_D\0" |
| 5401 | /* 3742 */ "X86RCRI_D\0" |
| 5402 | /* 3752 */ "XVBITCLRI_D\0" |
| 5403 | /* 3764 */ "XVSRLRI_D\0" |
| 5404 | /* 3774 */ "X86ROTRI_D\0" |
| 5405 | /* 3785 */ "XVROTRI_D\0" |
| 5406 | /* 3795 */ "XVBITSETI_D\0" |
| 5407 | /* 3807 */ "XVSLTI_D\0" |
| 5408 | /* 3816 */ "XVBITREVI_D\0" |
| 5409 | /* 3828 */ "XVMAXI_D\0" |
| 5410 | /* 3837 */ "BYTEPICK_D\0" |
| 5411 | /* 3848 */ "BSTRPICK_D\0" |
| 5412 | /* 3859 */ "X86RCL_D\0" |
| 5413 | /* 3868 */ "LDL_D\0" |
| 5414 | /* 3874 */ "SCREL_D\0" |
| 5415 | /* 3882 */ "X86SLL_D\0" |
| 5416 | /* 3891 */ "XVSLL_D\0" |
| 5417 | /* 3899 */ "XVLDREPL_D\0" |
| 5418 | /* 3910 */ "X86SRL_D\0" |
| 5419 | /* 3919 */ "XVSRL_D\0" |
| 5420 | /* 3927 */ "ALSL_D\0" |
| 5421 | /* 3934 */ "X86ROTL_D\0" |
| 5422 | /* 3944 */ "STL_D\0" |
| 5423 | /* 3950 */ "X86MUL_D\0" |
| 5424 | /* 3959 */ "XVFMUL_D\0" |
| 5425 | /* 3968 */ "XVMUL_D\0" |
| 5426 | /* 3976 */ "XVILVL_D\0" |
| 5427 | /* 3985 */ "XVFTINTRNE_L_D\0" |
| 5428 | /* 4000 */ "XVFTINTRM_L_D\0" |
| 5429 | /* 4014 */ "XVFTINTRP_L_D\0" |
| 5430 | /* 4028 */ "XVFTINT_L_D\0" |
| 5431 | /* 4040 */ "XVFTINTRZ_L_D\0" |
| 5432 | /* 4054 */ "XVSTELM_D\0" |
| 5433 | /* 4064 */ "XVFRINTRM_D\0" |
| 5434 | /* 4076 */ "FCOPYSIGN_D\0" |
| 5435 | /* 4088 */ "XVFMIN_D\0" |
| 5436 | /* 4097 */ "AMMIN_D\0" |
| 5437 | /* 4105 */ "XVMIN_D\0" |
| 5438 | /* 4113 */ "XVFCMP_CUN_D\0" |
| 5439 | /* 4126 */ "XVFCMP_SUN_D\0" |
| 5440 | /* 4139 */ "XVCLO_D\0" |
| 5441 | /* 4147 */ "CTO_D\0" |
| 5442 | /* 4153 */ "AMSWAP_D\0" |
| 5443 | /* 4162 */ "XVFRECIP_D\0" |
| 5444 | /* 4173 */ "XVFRINTRP_D\0" |
| 5445 | /* 4185 */ "LLACQ_D\0" |
| 5446 | /* 4193 */ "XVFCMP_CEQ_D\0" |
| 5447 | /* 4206 */ "XVSEQ_D\0" |
| 5448 | /* 4214 */ "XVFCMP_SEQ_D\0" |
| 5449 | /* 4227 */ "XVFCMP_CUEQ_D\0" |
| 5450 | /* 4241 */ "XVFCMP_SUEQ_D\0" |
| 5451 | /* 4255 */ "XVSUBWOD_Q_D\0" |
| 5452 | /* 4268 */ "XVMADDWOD_Q_D\0" |
| 5453 | /* 4282 */ "XVADDWOD_Q_D\0" |
| 5454 | /* 4295 */ "XVMULWOD_Q_D\0" |
| 5455 | /* 4308 */ "XVEXTH_Q_D\0" |
| 5456 | /* 4319 */ "XVEXTL_Q_D\0" |
| 5457 | /* 4330 */ "XVSUBWEV_Q_D\0" |
| 5458 | /* 4343 */ "XVMADDWEV_Q_D\0" |
| 5459 | /* 4357 */ "XVADDWEV_Q_D\0" |
| 5460 | /* 4370 */ "XVMULWEV_Q_D\0" |
| 5461 | /* 4383 */ "XVHSUBW_Q_D\0" |
| 5462 | /* 4395 */ "XVHADDW_Q_D\0" |
| 5463 | /* 4407 */ "XVSRAR_D\0" |
| 5464 | /* 4416 */ "X86RCR_D\0" |
| 5465 | /* 4425 */ "LDR_D\0" |
| 5466 | /* 4431 */ "MOVGR2FR_D\0" |
| 5467 | /* 4442 */ "XVPICKVE2GR_D\0" |
| 5468 | /* 4456 */ "MOVFR2GR_D\0" |
| 5469 | /* 4467 */ "XVAVGR_D\0" |
| 5470 | /* 4476 */ "XVBITCLR_D\0" |
| 5471 | /* 4487 */ "XVSRLR_D\0" |
| 5472 | /* 4496 */ "X86OR_D\0" |
| 5473 | /* 4504 */ "XVFCMP_COR_D\0" |
| 5474 | /* 4517 */ "AMOR_D\0" |
| 5475 | /* 4524 */ "XVFCMP_SOR_D\0" |
| 5476 | /* 4537 */ "X86XOR_D\0" |
| 5477 | /* 4546 */ "AMXOR_D\0" |
| 5478 | /* 4554 */ "X86ROTR_D\0" |
| 5479 | /* 4564 */ "XVROTR_D\0" |
| 5480 | /* 4573 */ "LDPTR_D\0" |
| 5481 | /* 4581 */ "STPTR_D\0" |
| 5482 | /* 4589 */ "STR_D\0" |
| 5483 | /* 4595 */ "XVREPLGR2VR_D\0" |
| 5484 | /* 4609 */ "XVINSGR2VR_D\0" |
| 5485 | /* 4622 */ "IOCSRWR_D\0" |
| 5486 | /* 4632 */ "AMCAS_D\0" |
| 5487 | /* 4640 */ "FABS_D\0" |
| 5488 | /* 4647 */ "BSTRINS_D\0" |
| 5489 | /* 4657 */ "XVEXTRINS_D\0" |
| 5490 | /* 4669 */ "XVFCLASS_D\0" |
| 5491 | /* 4680 */ "XVFCVT_S_D\0" |
| 5492 | /* 4691 */ "XVSAT_D\0" |
| 5493 | /* 4699 */ "XVBITSET_D\0" |
| 5494 | /* 4710 */ "FLDGT_D\0" |
| 5495 | /* 4718 */ "ASRTGT_D\0" |
| 5496 | /* 4727 */ "FSTGT_D\0" |
| 5497 | /* 4735 */ "XVFCMP_CLT_D\0" |
| 5498 | /* 4748 */ "XVSLT_D\0" |
| 5499 | /* 4756 */ "XVFCMP_SLT_D\0" |
| 5500 | /* 4769 */ "XVFCMP_CULT_D\0" |
| 5501 | /* 4783 */ "XVFCMP_SULT_D\0" |
| 5502 | /* 4797 */ "XVPCNT_D\0" |
| 5503 | /* 4806 */ "XVFRINT_D\0" |
| 5504 | /* 4816 */ "XVFSQRT_D\0" |
| 5505 | /* 4826 */ "XVFRSQRT_D\0" |
| 5506 | /* 4837 */ "FST_D\0" |
| 5507 | /* 4843 */ "XVMADDWOD_Q_DU_D\0" |
| 5508 | /* 4860 */ "XVADDWOD_Q_DU_D\0" |
| 5509 | /* 4876 */ "XVMULWOD_Q_DU_D\0" |
| 5510 | /* 4892 */ "XVMADDWEV_Q_DU_D\0" |
| 5511 | /* 4909 */ "XVADDWEV_Q_DU_D\0" |
| 5512 | /* 4925 */ "XVMULWEV_Q_DU_D\0" |
| 5513 | /* 4941 */ "XVFTINT_LU_D\0" |
| 5514 | /* 4954 */ "XVFTINTRZ_LU_D\0" |
| 5515 | /* 4969 */ "XVSSRANI_WU_D\0" |
| 5516 | /* 4983 */ "XVSSRLNI_WU_D\0" |
| 5517 | /* 4997 */ "XVSSRARNI_WU_D\0" |
| 5518 | /* 5012 */ "XVSSRLRNI_WU_D\0" |
| 5519 | /* 5027 */ "XVSSRAN_WU_D\0" |
| 5520 | /* 5040 */ "XVSSRLN_WU_D\0" |
| 5521 | /* 5053 */ "XVSSRARN_WU_D\0" |
| 5522 | /* 5067 */ "XVSSRLRN_WU_D\0" |
| 5523 | /* 5081 */ "XVPACKEV_D\0" |
| 5524 | /* 5092 */ "XVPICKEV_D\0" |
| 5525 | /* 5103 */ "XVBITREV_D\0" |
| 5526 | /* 5114 */ "XVFDIV_D\0" |
| 5527 | /* 5123 */ "XVDIV_D\0" |
| 5528 | /* 5131 */ "XVSIGNCOV_D\0" |
| 5529 | /* 5143 */ "FMOV_D\0" |
| 5530 | /* 5150 */ "ARMMOV_D\0" |
| 5531 | /* 5159 */ "XVFTINTRNE_W_D\0" |
| 5532 | /* 5174 */ "XVSSRANI_W_D\0" |
| 5533 | /* 5187 */ "XVSRANI_W_D\0" |
| 5534 | /* 5199 */ "XVSSRLNI_W_D\0" |
| 5535 | /* 5212 */ "XVSRLNI_W_D\0" |
| 5536 | /* 5224 */ "XVSSRARNI_W_D\0" |
| 5537 | /* 5238 */ "XVSRARNI_W_D\0" |
| 5538 | /* 5251 */ "XVSSRLRNI_W_D\0" |
| 5539 | /* 5265 */ "XVSRLRNI_W_D\0" |
| 5540 | /* 5278 */ "XVFTINTRM_W_D\0" |
| 5541 | /* 5292 */ "XVSSRAN_W_D\0" |
| 5542 | /* 5304 */ "XVSRAN_W_D\0" |
| 5543 | /* 5315 */ "XVSSRLN_W_D\0" |
| 5544 | /* 5327 */ "XVSRLN_W_D\0" |
| 5545 | /* 5338 */ "XVSSRARN_W_D\0" |
| 5546 | /* 5351 */ "XVSRARN_W_D\0" |
| 5547 | /* 5363 */ "XVSSRLRN_W_D\0" |
| 5548 | /* 5376 */ "XVSRLRN_W_D\0" |
| 5549 | /* 5388 */ "XVFTINTRP_W_D\0" |
| 5550 | /* 5402 */ "XVFTINT_W_D\0" |
| 5551 | /* 5414 */ "XVFTINTRZ_W_D\0" |
| 5552 | /* 5428 */ "XVFMAX_D\0" |
| 5553 | /* 5437 */ "AMMAX_D\0" |
| 5554 | /* 5445 */ "XVMAX_D\0" |
| 5555 | /* 5453 */ "FLDX_D\0" |
| 5556 | /* 5460 */ "FSTX_D\0" |
| 5557 | /* 5467 */ "PseudoXVBZ_D\0" |
| 5558 | /* 5480 */ "PseudoVBZ_D\0" |
| 5559 | /* 5492 */ "XVSETALLNEZ_D\0" |
| 5560 | /* 5506 */ "XVCLZ_D\0" |
| 5561 | /* 5514 */ "PseudoXVBNZ_D\0" |
| 5562 | /* 5528 */ "PseudoVBNZ_D\0" |
| 5563 | /* 5541 */ "XVSETANYEQZ_D\0" |
| 5564 | /* 5555 */ "XVFRINTRZ_D\0" |
| 5565 | /* 5567 */ "CTZ_D\0" |
| 5566 | /* 5573 */ "XVMSKLTZ_D\0" |
| 5567 | /* 5584 */ "PseudoAddTPRel_D\0" |
| 5568 | /* 5601 */ "PseudoAtomicStoreD\0" |
| 5569 | /* 5620 */ "FSEL_xD\0" |
| 5570 | /* 5628 */ "PSEUDO_PROBE\0" |
| 5571 | /* 5641 */ "G_SSUBE\0" |
| 5572 | /* 5649 */ "G_USUBE\0" |
| 5573 | /* 5657 */ "G_FENCE\0" |
| 5574 | /* 5665 */ "ARITH_FENCE\0" |
| 5575 | /* 5677 */ "REG_SEQUENCE\0" |
| 5576 | /* 5690 */ "G_SADDE\0" |
| 5577 | /* 5698 */ "G_UADDE\0" |
| 5578 | /* 5706 */ "G_GET_FPMODE\0" |
| 5579 | /* 5719 */ "G_RESET_FPMODE\0" |
| 5580 | /* 5734 */ "G_SET_FPMODE\0" |
| 5581 | /* 5747 */ "G_FMINNUM_IEEE\0" |
| 5582 | /* 5762 */ "G_FMAXNUM_IEEE\0" |
| 5583 | /* 5777 */ "BGE\0" |
| 5584 | /* 5781 */ "PseudoLA_TLS_DESC_PC_LARGE\0" |
| 5585 | /* 5808 */ "PseudoLA_TLS_GD_LARGE\0" |
| 5586 | /* 5830 */ "PseudoLA_TLS_LD_LARGE\0" |
| 5587 | /* 5852 */ "PseudoLA_TLS_IE_LARGE\0" |
| 5588 | /* 5874 */ "PseudoLA_PCREL_LARGE\0" |
| 5589 | /* 5895 */ "PseudoTAIL_LARGE\0" |
| 5590 | /* 5912 */ "PseudoCALL_LARGE\0" |
| 5591 | /* 5929 */ "PseudoLA_ABS_LARGE\0" |
| 5592 | /* 5948 */ "PseudoLA_TLS_DESC_ABS_LARGE\0" |
| 5593 | /* 5976 */ "PseudoLA_GOT_LARGE\0" |
| 5594 | /* 5995 */ "PseudoLA_TLS_IE\0" |
| 5595 | /* 6011 */ "G_VSCALE\0" |
| 5596 | /* 6020 */ "G_JUMP_TABLE\0" |
| 5597 | /* 6033 */ "IDLE\0" |
| 5598 | /* 6038 */ "BUNDLE\0" |
| 5599 | /* 6045 */ "PseudoLA_TLS_LE\0" |
| 5600 | /* 6061 */ "BNE\0" |
| 5601 | /* 6065 */ "G_MEMCPY_INLINE\0" |
| 5602 | /* 6081 */ "SETX86LOOPNE\0" |
| 5603 | /* 6094 */ "LOCAL_ESCAPE\0" |
| 5604 | /* 6107 */ "SETX86LOOPE\0" |
| 5605 | /* 6119 */ "G_STACKRESTORE\0" |
| 5606 | /* 6134 */ "G_INDEXED_STORE\0" |
| 5607 | /* 6150 */ "G_STORE\0" |
| 5608 | /* 6158 */ "SET_CFR_FALSE\0" |
| 5609 | /* 6172 */ "G_BITREVERSE\0" |
| 5610 | /* 6185 */ "LDPTE\0" |
| 5611 | /* 6191 */ "DBG_VALUE\0" |
| 5612 | /* 6201 */ "G_GLOBAL_VALUE\0" |
| 5613 | /* 6216 */ "G_PTRAUTH_GLOBAL_VALUE\0" |
| 5614 | /* 6239 */ "CONVERGENCECTRL_GLUE\0" |
| 5615 | /* 6260 */ "SET_CFR_TRUE\0" |
| 5616 | /* 6273 */ "G_STACKSAVE\0" |
| 5617 | /* 6285 */ "G_MEMMOVE\0" |
| 5618 | /* 6295 */ "ARMMOVE\0" |
| 5619 | /* 6303 */ "G_FREEZE\0" |
| 5620 | /* 6312 */ "G_FCANONICALIZE\0" |
| 5621 | /* 6328 */ "MOVGR2CF\0" |
| 5622 | /* 6337 */ "G_CTLZ_ZERO_UNDEF\0" |
| 5623 | /* 6355 */ "G_CTTZ_ZERO_UNDEF\0" |
| 5624 | /* 6373 */ "G_IMPLICIT_DEF\0" |
| 5625 | /* 6388 */ "DBG_INSTR_REF\0" |
| 5626 | /* 6402 */ "X86MFFLAG\0" |
| 5627 | /* 6412 */ "ARMMFFLAG\0" |
| 5628 | /* 6422 */ "X86MTFLAG\0" |
| 5629 | /* 6432 */ "ARMMTFLAG\0" |
| 5630 | /* 6442 */ "X86SETTAG\0" |
| 5631 | /* 6452 */ "G_FNEG\0" |
| 5632 | /* 6459 */ "EXTRACT_SUBREG\0" |
| 5633 | /* 6474 */ "INSERT_SUBREG\0" |
| 5634 | /* 6488 */ "G_SEXT_INREG\0" |
| 5635 | /* 6501 */ "SUBREG_TO_REG\0" |
| 5636 | /* 6515 */ "CPUCFG\0" |
| 5637 | /* 6522 */ "G_ATOMIC_CMPXCHG\0" |
| 5638 | /* 6539 */ "GCSRXCHG\0" |
| 5639 | /* 6548 */ "G_ATOMICRMW_XCHG\0" |
| 5640 | /* 6565 */ "G_FLOG\0" |
| 5641 | /* 6572 */ "G_VAARG\0" |
| 5642 | /* 6580 */ "PREALLOCATED_ARG\0" |
| 5643 | /* 6597 */ "REVB_2H\0" |
| 5644 | /* 6605 */ "REVB_4H\0" |
| 5645 | /* 6613 */ "TLBSRCH\0" |
| 5646 | /* 6621 */ "G_PREFETCH\0" |
| 5647 | /* 6632 */ "G_SMULH\0" |
| 5648 | /* 6640 */ "G_UMULH\0" |
| 5649 | /* 6648 */ "G_FTANH\0" |
| 5650 | /* 6656 */ "G_FSINH\0" |
| 5651 | /* 6664 */ "G_FCOSH\0" |
| 5652 | /* 6672 */ "GTLBFLUSH\0" |
| 5653 | /* 6682 */ "XVREPLVE0_H\0" |
| 5654 | /* 6694 */ "XVADDA_H\0" |
| 5655 | /* 6703 */ "X86SRA_H\0" |
| 5656 | /* 6712 */ "XVSRA_H\0" |
| 5657 | /* 6720 */ "AMADD__DB_H\0" |
| 5658 | /* 6732 */ "AMSWAP__DB_H\0" |
| 5659 | /* 6745 */ "AMCAS__DB_H\0" |
| 5660 | /* 6757 */ "X86SUB_H\0" |
| 5661 | /* 6766 */ "XVMSUB_H\0" |
| 5662 | /* 6775 */ "XVSSUB_H\0" |
| 5663 | /* 6784 */ "XVSUB_H\0" |
| 5664 | /* 6792 */ "XVSSRANI_B_H\0" |
| 5665 | /* 6805 */ "XVSRANI_B_H\0" |
| 5666 | /* 6817 */ "XVSSRLNI_B_H\0" |
| 5667 | /* 6830 */ "XVSRLNI_B_H\0" |
| 5668 | /* 6842 */ "XVSSRARNI_B_H\0" |
| 5669 | /* 6856 */ "XVSRARNI_B_H\0" |
| 5670 | /* 6869 */ "XVSSRLRNI_B_H\0" |
| 5671 | /* 6883 */ "XVSRLRNI_B_H\0" |
| 5672 | /* 6896 */ "XVSSRAN_B_H\0" |
| 5673 | /* 6908 */ "XVSRAN_B_H\0" |
| 5674 | /* 6919 */ "XVSSRLN_B_H\0" |
| 5675 | /* 6931 */ "XVSRLN_B_H\0" |
| 5676 | /* 6942 */ "XVSSRARN_B_H\0" |
| 5677 | /* 6955 */ "XVSRARN_B_H\0" |
| 5678 | /* 6967 */ "XVSSRLRN_B_H\0" |
| 5679 | /* 6980 */ "XVSRLRN_B_H\0" |
| 5680 | /* 6992 */ "X86SBC_H\0" |
| 5681 | /* 7001 */ "X86ADC_H\0" |
| 5682 | /* 7010 */ "X86DEC_H\0" |
| 5683 | /* 7019 */ "X86INC_H\0" |
| 5684 | /* 7028 */ "X86ADD_H\0" |
| 5685 | /* 7037 */ "AMADD_H\0" |
| 5686 | /* 7045 */ "XVMADD_H\0" |
| 5687 | /* 7054 */ "XVSADD_H\0" |
| 5688 | /* 7063 */ "XVADD_H\0" |
| 5689 | /* 7071 */ "LD_H\0" |
| 5690 | /* 7076 */ "X86AND_H\0" |
| 5691 | /* 7085 */ "XVPACKOD_H\0" |
| 5692 | /* 7096 */ "XVPICKOD_H\0" |
| 5693 | /* 7107 */ "XVMOD_H\0" |
| 5694 | /* 7115 */ "IOCSRRD_H\0" |
| 5695 | /* 7125 */ "XVABSD_H\0" |
| 5696 | /* 7134 */ "VEXT2XV_D_H\0" |
| 5697 | /* 7146 */ "LDLE_H\0" |
| 5698 | /* 7153 */ "XVSLE_H\0" |
| 5699 | /* 7161 */ "STLE_H\0" |
| 5700 | /* 7168 */ "XVREPLVE_H\0" |
| 5701 | /* 7179 */ "XVSHUF_H\0" |
| 5702 | /* 7188 */ "XVNEG_H\0" |
| 5703 | /* 7196 */ "XVAVG_H\0" |
| 5704 | /* 7204 */ "XVMUH_H\0" |
| 5705 | /* 7212 */ "XVILVH_H\0" |
| 5706 | /* 7221 */ "XVSHUF4I_H\0" |
| 5707 | /* 7232 */ "X86SRAI_H\0" |
| 5708 | /* 7242 */ "XVSRAI_H\0" |
| 5709 | /* 7251 */ "XVSLEI_H\0" |
| 5710 | /* 7260 */ "XVREPL128VEI_H\0" |
| 5711 | /* 7275 */ "VREPLVEI_H\0" |
| 5712 | /* 7286 */ "X86RCLI_H\0" |
| 5713 | /* 7296 */ "X86SLLI_H\0" |
| 5714 | /* 7306 */ "XVSLLI_H\0" |
| 5715 | /* 7315 */ "PseudoXVREPLI_H\0" |
| 5716 | /* 7331 */ "PseudoVREPLI_H\0" |
| 5717 | /* 7346 */ "X86SRLI_H\0" |
| 5718 | /* 7356 */ "XVSRLI_H\0" |
| 5719 | /* 7365 */ "X86ROTLI_H\0" |
| 5720 | /* 7376 */ "XVMINI_H\0" |
| 5721 | /* 7385 */ "XVFRSTPI_H\0" |
| 5722 | /* 7396 */ "XVSEQI_H\0" |
| 5723 | /* 7405 */ "XVSRARI_H\0" |
| 5724 | /* 7415 */ "X86RCRI_H\0" |
| 5725 | /* 7425 */ "XVBITCLRI_H\0" |
| 5726 | /* 7437 */ "XVSRLRI_H\0" |
| 5727 | /* 7447 */ "X86ROTRI_H\0" |
| 5728 | /* 7458 */ "XVROTRI_H\0" |
| 5729 | /* 7468 */ "XVBITSETI_H\0" |
| 5730 | /* 7480 */ "XVSLTI_H\0" |
| 5731 | /* 7489 */ "XVBITREVI_H\0" |
| 5732 | /* 7501 */ "XVMAXI_H\0" |
| 5733 | /* 7510 */ "X86RCL_H\0" |
| 5734 | /* 7519 */ "X86SLL_H\0" |
| 5735 | /* 7528 */ "XVSLL_H\0" |
| 5736 | /* 7536 */ "XVLDREPL_H\0" |
| 5737 | /* 7547 */ "X86SRL_H\0" |
| 5738 | /* 7556 */ "XVSRL_H\0" |
| 5739 | /* 7564 */ "X86ROTL_H\0" |
| 5740 | /* 7574 */ "X86MUL_H\0" |
| 5741 | /* 7583 */ "XVMUL_H\0" |
| 5742 | /* 7591 */ "XVILVL_H\0" |
| 5743 | /* 7600 */ "XVSTELM_H\0" |
| 5744 | /* 7610 */ "XVMIN_H\0" |
| 5745 | /* 7618 */ "XVCLO_H\0" |
| 5746 | /* 7626 */ "AMSWAP_H\0" |
| 5747 | /* 7635 */ "XVFRSTP_H\0" |
| 5748 | /* 7645 */ "XVSEQ_H\0" |
| 5749 | /* 7653 */ "XVSRAR_H\0" |
| 5750 | /* 7662 */ "X86RCR_H\0" |
| 5751 | /* 7671 */ "VPICKVE2GR_H\0" |
| 5752 | /* 7684 */ "XVAVGR_H\0" |
| 5753 | /* 7693 */ "XVBITCLR_H\0" |
| 5754 | /* 7704 */ "XVSRLR_H\0" |
| 5755 | /* 7713 */ "X86OR_H\0" |
| 5756 | /* 7721 */ "X86XOR_H\0" |
| 5757 | /* 7730 */ "X86ROTR_H\0" |
| 5758 | /* 7740 */ "XVROTR_H\0" |
| 5759 | /* 7749 */ "XVREPLGR2VR_H\0" |
| 5760 | /* 7763 */ "PseudoXVINSGR2VR_H\0" |
| 5761 | /* 7782 */ "IOCSRWR_H\0" |
| 5762 | /* 7792 */ "AMCAS_H\0" |
| 5763 | /* 7800 */ "XVEXTRINS_H\0" |
| 5764 | /* 7812 */ "XVFCVTH_S_H\0" |
| 5765 | /* 7824 */ "XVFCVTL_S_H\0" |
| 5766 | /* 7836 */ "XVSAT_H\0" |
| 5767 | /* 7844 */ "XVBITSET_H\0" |
| 5768 | /* 7855 */ "LDGT_H\0" |
| 5769 | /* 7862 */ "STGT_H\0" |
| 5770 | /* 7869 */ "XVSLT_H\0" |
| 5771 | /* 7877 */ "XVPCNT_H\0" |
| 5772 | /* 7886 */ "ST_H\0" |
| 5773 | /* 7891 */ "XVSSRANI_BU_H\0" |
| 5774 | /* 7905 */ "XVSSRLNI_BU_H\0" |
| 5775 | /* 7919 */ "XVSSRARNI_BU_H\0" |
| 5776 | /* 7934 */ "XVSSRLRNI_BU_H\0" |
| 5777 | /* 7949 */ "XVSSRAN_BU_H\0" |
| 5778 | /* 7962 */ "XVSSRLN_BU_H\0" |
| 5779 | /* 7975 */ "XVSSRARN_BU_H\0" |
| 5780 | /* 7989 */ "XVSSRLRN_BU_H\0" |
| 5781 | /* 8003 */ "XVMADDWOD_W_HU_H\0" |
| 5782 | /* 8020 */ "XVADDWOD_W_HU_H\0" |
| 5783 | /* 8036 */ "XVMULWOD_W_HU_H\0" |
| 5784 | /* 8052 */ "XVMADDWEV_W_HU_H\0" |
| 5785 | /* 8069 */ "XVADDWEV_W_HU_H\0" |
| 5786 | /* 8085 */ "XVMULWEV_W_HU_H\0" |
| 5787 | /* 8101 */ "XVPACKEV_H\0" |
| 5788 | /* 8112 */ "XVPICKEV_H\0" |
| 5789 | /* 8123 */ "XVBITREV_H\0" |
| 5790 | /* 8134 */ "XVDIV_H\0" |
| 5791 | /* 8142 */ "XVSIGNCOV_H\0" |
| 5792 | /* 8154 */ "XVSUBWOD_W_H\0" |
| 5793 | /* 8167 */ "XVMADDWOD_W_H\0" |
| 5794 | /* 8181 */ "XVADDWOD_W_H\0" |
| 5795 | /* 8194 */ "XVMULWOD_W_H\0" |
| 5796 | /* 8207 */ "XVEXTH_W_H\0" |
| 5797 | /* 8218 */ "XVSLLWIL_W_H\0" |
| 5798 | /* 8231 */ "EXT_W_H\0" |
| 5799 | /* 8239 */ "XVSUBWEV_W_H\0" |
| 5800 | /* 8252 */ "XVMADDWEV_W_H\0" |
| 5801 | /* 8266 */ "XVADDWEV_W_H\0" |
| 5802 | /* 8279 */ "XVMULWEV_W_H\0" |
| 5803 | /* 8292 */ "VEXT2XV_W_H\0" |
| 5804 | /* 8304 */ "XVHSUBW_W_H\0" |
| 5805 | /* 8316 */ "XVHADDW_W_H\0" |
| 5806 | /* 8328 */ "XVMAX_H\0" |
| 5807 | /* 8336 */ "LDX_H\0" |
| 5808 | /* 8342 */ "STX_H\0" |
| 5809 | /* 8348 */ "PseudoXVBZ_H\0" |
| 5810 | /* 8361 */ "PseudoVBZ_H\0" |
| 5811 | /* 8373 */ "XVSETALLNEZ_H\0" |
| 5812 | /* 8387 */ "XVCLZ_H\0" |
| 5813 | /* 8395 */ "PseudoXVBNZ_H\0" |
| 5814 | /* 8409 */ "PseudoVBNZ_H\0" |
| 5815 | /* 8422 */ "XVSETANYEQZ_H\0" |
| 5816 | /* 8436 */ "XVMSKLTZ_H\0" |
| 5817 | /* 8447 */ "PCALAU12I\0" |
| 5818 | /* 8457 */ "PCADDU12I\0" |
| 5819 | /* 8467 */ "PCADDU18I\0" |
| 5820 | /* 8477 */ "PCADDI\0" |
| 5821 | /* 8484 */ "XVLDI\0" |
| 5822 | /* 8490 */ "ANDI\0" |
| 5823 | /* 8495 */ "DBG_PHI\0" |
| 5824 | /* 8503 */ "XORI\0" |
| 5825 | /* 8508 */ "G_FPTOSI\0" |
| 5826 | /* 8517 */ "SLTI\0" |
| 5827 | /* 8522 */ "G_FPTOUI\0" |
| 5828 | /* 8531 */ "SLTUI\0" |
| 5829 | /* 8537 */ "G_FPOWI\0" |
| 5830 | /* 8545 */ "SETX86J\0" |
| 5831 | /* 8553 */ "SETARMJ\0" |
| 5832 | /* 8561 */ "BREAK\0" |
| 5833 | /* 8567 */ "G_PTRMASK\0" |
| 5834 | /* 8577 */ "BL\0" |
| 5835 | /* 8580 */ "DBCL\0" |
| 5836 | /* 8585 */ "HVCL\0" |
| 5837 | /* 8590 */ "GC_LABEL\0" |
| 5838 | /* 8599 */ "DBG_LABEL\0" |
| 5839 | /* 8609 */ "EH_LABEL\0" |
| 5840 | /* 8618 */ "ANNOTATION_LABEL\0" |
| 5841 | /* 8635 */ "ICALL_BRANCH_FUNNEL\0" |
| 5842 | /* 8655 */ "PseudoLA_PCREL\0" |
| 5843 | /* 8670 */ "G_FSHL\0" |
| 5844 | /* 8677 */ "G_SHL\0" |
| 5845 | /* 8683 */ "PseudoB_TAIL\0" |
| 5846 | /* 8696 */ "PseudoJIRL_TAIL\0" |
| 5847 | /* 8712 */ "PseudoTAIL\0" |
| 5848 | /* 8723 */ "G_FCEIL\0" |
| 5849 | /* 8731 */ "SYSCALL\0" |
| 5850 | /* 8739 */ "PseudoDESC_CALL\0" |
| 5851 | /* 8755 */ "PATCHABLE_TAIL_CALL\0" |
| 5852 | /* 8775 */ "PseudoJIRL_CALL\0" |
| 5853 | /* 8791 */ "PATCHABLE_TYPED_EVENT_CALL\0" |
| 5854 | /* 8818 */ "PATCHABLE_EVENT_CALL\0" |
| 5855 | /* 8839 */ "FENTRY_CALL\0" |
| 5856 | /* 8851 */ "PseudoCALL\0" |
| 5857 | /* 8862 */ "TLBFILL\0" |
| 5858 | /* 8870 */ "KILL\0" |
| 5859 | /* 8875 */ "G_CONSTANT_POOL\0" |
| 5860 | /* 8891 */ "JIRL\0" |
| 5861 | /* 8896 */ "G_ROTL\0" |
| 5862 | /* 8903 */ "G_VECREDUCE_FMUL\0" |
| 5863 | /* 8920 */ "G_FMUL\0" |
| 5864 | /* 8927 */ "G_VECREDUCE_SEQ_FMUL\0" |
| 5865 | /* 8948 */ "G_STRICT_FMUL\0" |
| 5866 | /* 8962 */ "G_VECREDUCE_MUL\0" |
| 5867 | /* 8978 */ "G_MUL\0" |
| 5868 | /* 8984 */ "XVFFINT_D_L\0" |
| 5869 | /* 8996 */ "XVFFINT_S_L\0" |
| 5870 | /* 9008 */ "G_FREM\0" |
| 5871 | /* 9015 */ "G_STRICT_FREM\0" |
| 5872 | /* 9029 */ "G_SREM\0" |
| 5873 | /* 9036 */ "G_UREM\0" |
| 5874 | /* 9043 */ "G_SDIVREM\0" |
| 5875 | /* 9053 */ "G_UDIVREM\0" |
| 5876 | /* 9063 */ "INLINEASM\0" |
| 5877 | /* 9073 */ "X86CLRTM\0" |
| 5878 | /* 9082 */ "X86SETTM\0" |
| 5879 | /* 9091 */ "PseudoTAIL_MEDIUM\0" |
| 5880 | /* 9109 */ "PseudoCALL_MEDIUM\0" |
| 5881 | /* 9127 */ "G_VECREDUCE_FMINIMUM\0" |
| 5882 | /* 9148 */ "G_FMINIMUM\0" |
| 5883 | /* 9159 */ "G_VECREDUCE_FMAXIMUM\0" |
| 5884 | /* 9180 */ "G_FMAXIMUM\0" |
| 5885 | /* 9191 */ "G_FMINNUM\0" |
| 5886 | /* 9201 */ "G_FMAXNUM\0" |
| 5887 | /* 9211 */ "G_FATAN\0" |
| 5888 | /* 9219 */ "G_FTAN\0" |
| 5889 | /* 9226 */ "ANDN\0" |
| 5890 | /* 9231 */ "G_INTRINSIC_ROUNDEVEN\0" |
| 5891 | /* 9253 */ "G_ASSERT_ALIGN\0" |
| 5892 | /* 9268 */ "G_FCOPYSIGN\0" |
| 5893 | /* 9280 */ "G_VECREDUCE_FMIN\0" |
| 5894 | /* 9297 */ "G_ATOMICRMW_FMIN\0" |
| 5895 | /* 9314 */ "G_VECREDUCE_SMIN\0" |
| 5896 | /* 9331 */ "G_SMIN\0" |
| 5897 | /* 9338 */ "G_VECREDUCE_UMIN\0" |
| 5898 | /* 9355 */ "G_UMIN\0" |
| 5899 | /* 9362 */ "G_ATOMICRMW_UMIN\0" |
| 5900 | /* 9379 */ "G_ATOMICRMW_MIN\0" |
| 5901 | /* 9395 */ "G_FASIN\0" |
| 5902 | /* 9403 */ "G_FSIN\0" |
| 5903 | /* 9410 */ "CFI_INSTRUCTION\0" |
| 5904 | /* 9426 */ "ORN\0" |
| 5905 | /* 9430 */ "ERTN\0" |
| 5906 | /* 9435 */ "ADJCALLSTACKDOWN\0" |
| 5907 | /* 9452 */ "G_SSUBO\0" |
| 5908 | /* 9460 */ "G_USUBO\0" |
| 5909 | /* 9468 */ "G_SADDO\0" |
| 5910 | /* 9476 */ "G_UADDO\0" |
| 5911 | /* 9484 */ "JUMP_TABLE_DEBUG_INFO\0" |
| 5912 | /* 9506 */ "G_SMULO\0" |
| 5913 | /* 9514 */ "G_UMULO\0" |
| 5914 | /* 9522 */ "G_BZERO\0" |
| 5915 | /* 9530 */ "STACKMAP\0" |
| 5916 | /* 9539 */ "G_DEBUGTRAP\0" |
| 5917 | /* 9551 */ "G_UBSANTRAP\0" |
| 5918 | /* 9563 */ "G_TRAP\0" |
| 5919 | /* 9570 */ "G_ATOMICRMW_UDEC_WRAP\0" |
| 5920 | /* 9592 */ "G_ATOMICRMW_UINC_WRAP\0" |
| 5921 | /* 9614 */ "G_BSWAP\0" |
| 5922 | /* 9622 */ "G_SITOFP\0" |
| 5923 | /* 9631 */ "G_UITOFP\0" |
| 5924 | /* 9640 */ "G_FCMP\0" |
| 5925 | /* 9647 */ "G_ICMP\0" |
| 5926 | /* 9654 */ "G_SCMP\0" |
| 5927 | /* 9661 */ "G_UCMP\0" |
| 5928 | /* 9668 */ "PseudoUNIMP\0" |
| 5929 | /* 9680 */ "CACOP\0" |
| 5930 | /* 9686 */ "CONVERGENCECTRL_LOOP\0" |
| 5931 | /* 9707 */ "G_CTPOP\0" |
| 5932 | /* 9715 */ "X86DECTOP\0" |
| 5933 | /* 9725 */ "X86INCTOP\0" |
| 5934 | /* 9735 */ "X86MFTOP\0" |
| 5935 | /* 9744 */ "X86MTTOP\0" |
| 5936 | /* 9753 */ "PATCHABLE_OP\0" |
| 5937 | /* 9766 */ "FAULTING_OP\0" |
| 5938 | /* 9778 */ "ADJCALLSTACKUP\0" |
| 5939 | /* 9793 */ "PREALLOCATED_SETUP\0" |
| 5940 | /* 9812 */ "G_FLDEXP\0" |
| 5941 | /* 9821 */ "G_STRICT_FLDEXP\0" |
| 5942 | /* 9837 */ "G_FEXP\0" |
| 5943 | /* 9844 */ "G_FFREXP\0" |
| 5944 | /* 9853 */ "BEQ\0" |
| 5945 | /* 9857 */ "XVREPLVE0_Q\0" |
| 5946 | /* 9869 */ "XVSUB_Q\0" |
| 5947 | /* 9877 */ "SC_Q\0" |
| 5948 | /* 9882 */ "XVADD_Q\0" |
| 5949 | /* 9890 */ "XVSSRANI_D_Q\0" |
| 5950 | /* 9903 */ "XVSRANI_D_Q\0" |
| 5951 | /* 9915 */ "XVSSRLNI_D_Q\0" |
| 5952 | /* 9928 */ "XVSRLNI_D_Q\0" |
| 5953 | /* 9940 */ "XVSSRARNI_D_Q\0" |
| 5954 | /* 9954 */ "XVSRARNI_D_Q\0" |
| 5955 | /* 9967 */ "XVSSRLRNI_D_Q\0" |
| 5956 | /* 9981 */ "XVSRLRNI_D_Q\0" |
| 5957 | /* 9994 */ "XVPERMI_Q\0" |
| 5958 | /* 10004 */ "XVSSRANI_DU_Q\0" |
| 5959 | /* 10018 */ "XVSSRLNI_DU_Q\0" |
| 5960 | /* 10032 */ "XVSSRARNI_DU_Q\0" |
| 5961 | /* 10047 */ "XVSSRLRNI_DU_Q\0" |
| 5962 | /* 10062 */ "DBAR\0" |
| 5963 | /* 10067 */ "IBAR\0" |
| 5964 | /* 10072 */ "G_BR\0" |
| 5965 | /* 10077 */ "INLINEASM_BR\0" |
| 5966 | /* 10090 */ "PseudoBR\0" |
| 5967 | /* 10099 */ "MOVGR2SCR\0" |
| 5968 | /* 10109 */ "G_BLOCK_ADDR\0" |
| 5969 | /* 10122 */ "MEMBARRIER\0" |
| 5970 | /* 10133 */ "G_CONSTANT_FOLD_BARRIER\0" |
| 5971 | /* 10157 */ "PATCHABLE_FUNCTION_ENTER\0" |
| 5972 | /* 10182 */ "G_READCYCLECOUNTER\0" |
| 5973 | /* 10201 */ "G_READSTEADYCOUNTER\0" |
| 5974 | /* 10221 */ "G_READ_REGISTER\0" |
| 5975 | /* 10237 */ "G_WRITE_REGISTER\0" |
| 5976 | /* 10254 */ "PseudoLD_CFR\0" |
| 5977 | /* 10267 */ "PseudoST_CFR\0" |
| 5978 | /* 10280 */ "PseudoCopyCFR\0" |
| 5979 | /* 10294 */ "MOVCF2GR\0" |
| 5980 | /* 10303 */ "MOVSCR2GR\0" |
| 5981 | /* 10313 */ "MOVFCSR2GR\0" |
| 5982 | /* 10324 */ "G_ASHR\0" |
| 5983 | /* 10331 */ "G_FSHR\0" |
| 5984 | /* 10338 */ "G_LSHR\0" |
| 5985 | /* 10345 */ "LDDIR\0" |
| 5986 | /* 10351 */ "TLBCLR\0" |
| 5987 | /* 10358 */ "CONVERGENCECTRL_ANCHOR\0" |
| 5988 | /* 10381 */ "NOR\0" |
| 5989 | /* 10385 */ "G_FFLOOR\0" |
| 5990 | /* 10394 */ "G_EXTRACT_SUBVECTOR\0" |
| 5991 | /* 10414 */ "G_INSERT_SUBVECTOR\0" |
| 5992 | /* 10433 */ "G_BUILD_VECTOR\0" |
| 5993 | /* 10448 */ "G_SHUFFLE_VECTOR\0" |
| 5994 | /* 10465 */ "G_SPLAT_VECTOR\0" |
| 5995 | /* 10480 */ "G_VECREDUCE_XOR\0" |
| 5996 | /* 10496 */ "G_XOR\0" |
| 5997 | /* 10502 */ "G_ATOMICRMW_XOR\0" |
| 5998 | /* 10518 */ "G_VECREDUCE_OR\0" |
| 5999 | /* 10533 */ "G_OR\0" |
| 6000 | /* 10538 */ "G_ATOMICRMW_OR\0" |
| 6001 | /* 10553 */ "MOVGR2FCSR\0" |
| 6002 | /* 10564 */ "RDFCSR\0" |
| 6003 | /* 10571 */ "WRFCSR\0" |
| 6004 | /* 10578 */ "G_ROTR\0" |
| 6005 | /* 10585 */ "G_INTTOPTR\0" |
| 6006 | /* 10596 */ "TLBWR\0" |
| 6007 | /* 10602 */ "GCSRWR\0" |
| 6008 | /* 10609 */ "G_FABS\0" |
| 6009 | /* 10616 */ "PseudoLA_ABS\0" |
| 6010 | /* 10629 */ "PseudoLA_TLS_DESC_ABS\0" |
| 6011 | /* 10651 */ "G_ABS\0" |
| 6012 | /* 10657 */ "G_UNMERGE_VALUES\0" |
| 6013 | /* 10674 */ "G_MERGE_VALUES\0" |
| 6014 | /* 10689 */ "G_FACOS\0" |
| 6015 | /* 10697 */ "G_FCOS\0" |
| 6016 | /* 10704 */ "G_CONCAT_VECTORS\0" |
| 6017 | /* 10721 */ "COPY_TO_REGCLASS\0" |
| 6018 | /* 10738 */ "G_IS_FPCLASS\0" |
| 6019 | /* 10751 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" |
| 6020 | /* 10781 */ "G_VECTOR_COMPRESS\0" |
| 6021 | /* 10799 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" |
| 6022 | /* 10826 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" |
| 6023 | /* 10864 */ "XVFMINA_S\0" |
| 6024 | /* 10874 */ "XVFMAXA_S\0" |
| 6025 | /* 10884 */ "FSCALEB_S\0" |
| 6026 | /* 10894 */ "XVFLOGB_S\0" |
| 6027 | /* 10904 */ "XVFSUB_S\0" |
| 6028 | /* 10913 */ "XVFMSUB_S\0" |
| 6029 | /* 10923 */ "XVFNMSUB_S\0" |
| 6030 | /* 10934 */ "XVFADD_S\0" |
| 6031 | /* 10943 */ "XVFMADD_S\0" |
| 6032 | /* 10953 */ "XVFNMADD_S\0" |
| 6033 | /* 10964 */ "FLD_S\0" |
| 6034 | /* 10970 */ "XVFCVTH_D_S\0" |
| 6035 | /* 10982 */ "XVFCVTL_D_S\0" |
| 6036 | /* 10994 */ "FCVT_D_S\0" |
| 6037 | /* 11003 */ "XVFCMP_CLE_S\0" |
| 6038 | /* 11016 */ "FLDLE_S\0" |
| 6039 | /* 11024 */ "XVFCMP_SLE_S\0" |
| 6040 | /* 11037 */ "FSTLE_S\0" |
| 6041 | /* 11045 */ "XVFCMP_CULE_S\0" |
| 6042 | /* 11059 */ "XVFCMP_SULE_S\0" |
| 6043 | /* 11073 */ "XVFCMP_CNE_S\0" |
| 6044 | /* 11086 */ "XVFRINTRNE_S\0" |
| 6045 | /* 11099 */ "XVFCMP_SNE_S\0" |
| 6046 | /* 11112 */ "XVFCMP_CUNE_S\0" |
| 6047 | /* 11126 */ "XVFCMP_SUNE_S\0" |
| 6048 | /* 11140 */ "XVFRECIPE_S\0" |
| 6049 | /* 11152 */ "XVFRSQRTE_S\0" |
| 6050 | /* 11164 */ "XVFCMP_CAF_S\0" |
| 6051 | /* 11177 */ "XVFCMP_SAF_S\0" |
| 6052 | /* 11190 */ "FNEG_S\0" |
| 6053 | /* 11197 */ "XVFCVT_H_S\0" |
| 6054 | /* 11208 */ "XVFMUL_S\0" |
| 6055 | /* 11217 */ "FTINTRNE_L_S\0" |
| 6056 | /* 11230 */ "XVFTINTRNEH_L_S\0" |
| 6057 | /* 11246 */ "XVFTINTRMH_L_S\0" |
| 6058 | /* 11261 */ "XVFTINTRPH_L_S\0" |
| 6059 | /* 11276 */ "XVFTINTH_L_S\0" |
| 6060 | /* 11289 */ "XVFTINTRZH_L_S\0" |
| 6061 | /* 11304 */ "XVFTINTRNEL_L_S\0" |
| 6062 | /* 11320 */ "XVFTINTRML_L_S\0" |
| 6063 | /* 11335 */ "XVFTINTRPL_L_S\0" |
| 6064 | /* 11350 */ "XVFTINTL_L_S\0" |
| 6065 | /* 11363 */ "XVFTINTRZL_L_S\0" |
| 6066 | /* 11378 */ "FTINTRM_L_S\0" |
| 6067 | /* 11390 */ "FTINTRP_L_S\0" |
| 6068 | /* 11402 */ "FTINT_L_S\0" |
| 6069 | /* 11412 */ "FTINTRZ_L_S\0" |
| 6070 | /* 11424 */ "XVFRINTRM_S\0" |
| 6071 | /* 11436 */ "FCOPYSIGN_S\0" |
| 6072 | /* 11448 */ "XVFMIN_S\0" |
| 6073 | /* 11457 */ "XVFCMP_CUN_S\0" |
| 6074 | /* 11470 */ "XVFCMP_SUN_S\0" |
| 6075 | /* 11483 */ "XVFRECIP_S\0" |
| 6076 | /* 11494 */ "XVFRINTRP_S\0" |
| 6077 | /* 11506 */ "XVFCMP_CEQ_S\0" |
| 6078 | /* 11519 */ "XVFCMP_SEQ_S\0" |
| 6079 | /* 11532 */ "XVFCMP_CUEQ_S\0" |
| 6080 | /* 11546 */ "XVFCMP_SUEQ_S\0" |
| 6081 | /* 11560 */ "MOVFRH2GR_S\0" |
| 6082 | /* 11572 */ "MOVFR2GR_S\0" |
| 6083 | /* 11583 */ "XVFCMP_COR_S\0" |
| 6084 | /* 11596 */ "XVFCMP_SOR_S\0" |
| 6085 | /* 11609 */ "FABS_S\0" |
| 6086 | /* 11616 */ "XVFCLASS_S\0" |
| 6087 | /* 11627 */ "FLDGT_S\0" |
| 6088 | /* 11635 */ "FSTGT_S\0" |
| 6089 | /* 11643 */ "XVFCMP_CLT_S\0" |
| 6090 | /* 11656 */ "XVFCMP_SLT_S\0" |
| 6091 | /* 11669 */ "XVFCMP_CULT_S\0" |
| 6092 | /* 11683 */ "XVFCMP_SULT_S\0" |
| 6093 | /* 11697 */ "XVFRINT_S\0" |
| 6094 | /* 11707 */ "XVFSQRT_S\0" |
| 6095 | /* 11717 */ "XVFRSQRT_S\0" |
| 6096 | /* 11728 */ "FST_S\0" |
| 6097 | /* 11734 */ "XVFTINT_WU_S\0" |
| 6098 | /* 11747 */ "XVFTINTRZ_WU_S\0" |
| 6099 | /* 11762 */ "XVFDIV_S\0" |
| 6100 | /* 11771 */ "FMOV_S\0" |
| 6101 | /* 11778 */ "XVFTINTRNE_W_S\0" |
| 6102 | /* 11793 */ "XVFTINTRM_W_S\0" |
| 6103 | /* 11807 */ "XVFTINTRP_W_S\0" |
| 6104 | /* 11821 */ "XVFTINT_W_S\0" |
| 6105 | /* 11833 */ "XVFTINTRZ_W_S\0" |
| 6106 | /* 11847 */ "XVFMAX_S\0" |
| 6107 | /* 11856 */ "FLDX_S\0" |
| 6108 | /* 11863 */ "FSTX_S\0" |
| 6109 | /* 11870 */ "XVFRINTRZ_S\0" |
| 6110 | /* 11882 */ "MOVFR2CF_xS\0" |
| 6111 | /* 11894 */ "FSEL_xS\0" |
| 6112 | /* 11902 */ "MOVCF2FR_xS\0" |
| 6113 | /* 11914 */ "G_SSUBSAT\0" |
| 6114 | /* 11924 */ "G_USUBSAT\0" |
| 6115 | /* 11934 */ "G_SADDSAT\0" |
| 6116 | /* 11944 */ "G_UADDSAT\0" |
| 6117 | /* 11954 */ "G_SSHLSAT\0" |
| 6118 | /* 11964 */ "G_USHLSAT\0" |
| 6119 | /* 11974 */ "G_SMULFIXSAT\0" |
| 6120 | /* 11987 */ "G_UMULFIXSAT\0" |
| 6121 | /* 12000 */ "G_SDIVFIXSAT\0" |
| 6122 | /* 12013 */ "G_UDIVFIXSAT\0" |
| 6123 | /* 12026 */ "G_EXTRACT\0" |
| 6124 | /* 12036 */ "G_SELECT\0" |
| 6125 | /* 12045 */ "G_BRINDIRECT\0" |
| 6126 | /* 12058 */ "PATCHABLE_RET\0" |
| 6127 | /* 12072 */ "PseudoRET\0" |
| 6128 | /* 12082 */ "G_MEMSET\0" |
| 6129 | /* 12091 */ "PATCHABLE_FUNCTION_EXIT\0" |
| 6130 | /* 12115 */ "G_BRJT\0" |
| 6131 | /* 12122 */ "BLT\0" |
| 6132 | /* 12126 */ "G_EXTRACT_VECTOR_ELT\0" |
| 6133 | /* 12147 */ "G_INSERT_VECTOR_ELT\0" |
| 6134 | /* 12167 */ "SLT\0" |
| 6135 | /* 12171 */ "G_FCONSTANT\0" |
| 6136 | /* 12183 */ "G_CONSTANT\0" |
| 6137 | /* 12194 */ "G_INTRINSIC_CONVERGENT\0" |
| 6138 | /* 12217 */ "STATEPOINT\0" |
| 6139 | /* 12228 */ "PATCHPOINT\0" |
| 6140 | /* 12239 */ "G_PTRTOINT\0" |
| 6141 | /* 12250 */ "G_FRINT\0" |
| 6142 | /* 12258 */ "G_INTRINSIC_LLRINT\0" |
| 6143 | /* 12277 */ "G_INTRINSIC_LRINT\0" |
| 6144 | /* 12295 */ "G_FNEARBYINT\0" |
| 6145 | /* 12308 */ "PseudoLA_GOT\0" |
| 6146 | /* 12321 */ "G_VASTART\0" |
| 6147 | /* 12331 */ "LIFETIME_START\0" |
| 6148 | /* 12346 */ "G_INVOKE_REGION_START\0" |
| 6149 | /* 12368 */ "G_INSERT\0" |
| 6150 | /* 12377 */ "G_FSQRT\0" |
| 6151 | /* 12385 */ "G_STRICT_FSQRT\0" |
| 6152 | /* 12400 */ "G_BITCAST\0" |
| 6153 | /* 12410 */ "G_ADDRSPACE_CAST\0" |
| 6154 | /* 12427 */ "DBG_VALUE_LIST\0" |
| 6155 | /* 12442 */ "XVST\0" |
| 6156 | /* 12447 */ "G_FPEXT\0" |
| 6157 | /* 12455 */ "G_SEXT\0" |
| 6158 | /* 12462 */ "G_ASSERT_SEXT\0" |
| 6159 | /* 12476 */ "G_ANYEXT\0" |
| 6160 | /* 12485 */ "G_ZEXT\0" |
| 6161 | /* 12492 */ "G_ASSERT_ZEXT\0" |
| 6162 | /* 12506 */ "XVSSUB_BU\0" |
| 6163 | /* 12516 */ "XVSADD_BU\0" |
| 6164 | /* 12526 */ "LD_BU\0" |
| 6165 | /* 12532 */ "XVMOD_BU\0" |
| 6166 | /* 12541 */ "XVABSD_BU\0" |
| 6167 | /* 12551 */ "XVSLE_BU\0" |
| 6168 | /* 12560 */ "XVAVG_BU\0" |
| 6169 | /* 12569 */ "XVMUH_BU\0" |
| 6170 | /* 12578 */ "XVSUBWOD_H_BU\0" |
| 6171 | /* 12592 */ "XVMADDWOD_H_BU\0" |
| 6172 | /* 12607 */ "XVADDWOD_H_BU\0" |
| 6173 | /* 12621 */ "XVMULWOD_H_BU\0" |
| 6174 | /* 12635 */ "XVSUBWEV_H_BU\0" |
| 6175 | /* 12649 */ "XVMADDWEV_H_BU\0" |
| 6176 | /* 12664 */ "XVADDWEV_H_BU\0" |
| 6177 | /* 12678 */ "XVMULWEV_H_BU\0" |
| 6178 | /* 12692 */ "XVSUBI_BU\0" |
| 6179 | /* 12702 */ "XVADDI_BU\0" |
| 6180 | /* 12712 */ "XVSLEI_BU\0" |
| 6181 | /* 12722 */ "XVMINI_BU\0" |
| 6182 | /* 12732 */ "XVSLTI_BU\0" |
| 6183 | /* 12742 */ "XVMAXI_BU\0" |
| 6184 | /* 12752 */ "X86MUL_BU\0" |
| 6185 | /* 12762 */ "XVMIN_BU\0" |
| 6186 | /* 12771 */ "VPICKVE2GR_BU\0" |
| 6187 | /* 12785 */ "XVAVGR_BU\0" |
| 6188 | /* 12795 */ "XVSAT_BU\0" |
| 6189 | /* 12804 */ "XVSLT_BU\0" |
| 6190 | /* 12813 */ "VEXT2XV_DU_BU\0" |
| 6191 | /* 12827 */ "XVEXTH_HU_BU\0" |
| 6192 | /* 12840 */ "XVSLLWIL_HU_BU\0" |
| 6193 | /* 12855 */ "VEXT2XV_HU_BU\0" |
| 6194 | /* 12869 */ "XVHSUBW_HU_BU\0" |
| 6195 | /* 12883 */ "XVHADDW_HU_BU\0" |
| 6196 | /* 12897 */ "VEXT2XV_WU_BU\0" |
| 6197 | /* 12911 */ "XVDIV_BU\0" |
| 6198 | /* 12920 */ "XVMAX_BU\0" |
| 6199 | /* 12929 */ "LDX_BU\0" |
| 6200 | /* 12936 */ "AMMIN__DB_DU\0" |
| 6201 | /* 12949 */ "AMMAX__DB_DU\0" |
| 6202 | /* 12962 */ "X86SUB_DU\0" |
| 6203 | /* 12972 */ "XVSSUB_DU\0" |
| 6204 | /* 12982 */ "X86ADD_DU\0" |
| 6205 | /* 12992 */ "XVSADD_DU\0" |
| 6206 | /* 13002 */ "XVMOD_DU\0" |
| 6207 | /* 13011 */ "XVABSD_DU\0" |
| 6208 | /* 13021 */ "XVSLE_DU\0" |
| 6209 | /* 13030 */ "XVAVG_DU\0" |
| 6210 | /* 13039 */ "MULH_DU\0" |
| 6211 | /* 13047 */ "XVMUH_DU\0" |
| 6212 | /* 13056 */ "XVSUBI_DU\0" |
| 6213 | /* 13066 */ "XVADDI_DU\0" |
| 6214 | /* 13076 */ "XVSLEI_DU\0" |
| 6215 | /* 13086 */ "XVMINI_DU\0" |
| 6216 | /* 13096 */ "XVSLTI_DU\0" |
| 6217 | /* 13106 */ "XVMAXI_DU\0" |
| 6218 | /* 13116 */ "X86MUL_DU\0" |
| 6219 | /* 13126 */ "AMMIN_DU\0" |
| 6220 | /* 13135 */ "XVMIN_DU\0" |
| 6221 | /* 13144 */ "XVSUBWOD_Q_DU\0" |
| 6222 | /* 13158 */ "XVMADDWOD_Q_DU\0" |
| 6223 | /* 13173 */ "XVADDWOD_Q_DU\0" |
| 6224 | /* 13187 */ "XVMULWOD_Q_DU\0" |
| 6225 | /* 13201 */ "XVSUBWEV_Q_DU\0" |
| 6226 | /* 13215 */ "XVMADDWEV_Q_DU\0" |
| 6227 | /* 13230 */ "XVADDWEV_Q_DU\0" |
| 6228 | /* 13244 */ "XVMULWEV_Q_DU\0" |
| 6229 | /* 13258 */ "XVPICKVE2GR_DU\0" |
| 6230 | /* 13273 */ "XVAVGR_DU\0" |
| 6231 | /* 13283 */ "XVSAT_DU\0" |
| 6232 | /* 13292 */ "XVSLT_DU\0" |
| 6233 | /* 13301 */ "XVEXTH_QU_DU\0" |
| 6234 | /* 13314 */ "XVEXTL_QU_DU\0" |
| 6235 | /* 13327 */ "XVHSUBW_QU_DU\0" |
| 6236 | /* 13341 */ "XVHADDW_QU_DU\0" |
| 6237 | /* 13355 */ "XVDIV_DU\0" |
| 6238 | /* 13364 */ "AMMAX_DU\0" |
| 6239 | /* 13373 */ "XVMAX_DU\0" |
| 6240 | /* 13382 */ "BGEU\0" |
| 6241 | /* 13387 */ "XVSSUB_HU\0" |
| 6242 | /* 13397 */ "XVSADD_HU\0" |
| 6243 | /* 13407 */ "LD_HU\0" |
| 6244 | /* 13413 */ "XVMOD_HU\0" |
| 6245 | /* 13422 */ "XVABSD_HU\0" |
| 6246 | /* 13432 */ "XVSLE_HU\0" |
| 6247 | /* 13441 */ "XVAVG_HU\0" |
| 6248 | /* 13450 */ "XVMUH_HU\0" |
| 6249 | /* 13459 */ "XVSUBI_HU\0" |
| 6250 | /* 13469 */ "XVADDI_HU\0" |
| 6251 | /* 13479 */ "XVSLEI_HU\0" |
| 6252 | /* 13489 */ "XVMINI_HU\0" |
| 6253 | /* 13499 */ "XVSLTI_HU\0" |
| 6254 | /* 13509 */ "XVMAXI_HU\0" |
| 6255 | /* 13519 */ "X86MUL_HU\0" |
| 6256 | /* 13529 */ "XVMIN_HU\0" |
| 6257 | /* 13538 */ "VPICKVE2GR_HU\0" |
| 6258 | /* 13552 */ "XVAVGR_HU\0" |
| 6259 | /* 13562 */ "XVSAT_HU\0" |
| 6260 | /* 13571 */ "XVSLT_HU\0" |
| 6261 | /* 13580 */ "VEXT2XV_DU_HU\0" |
| 6262 | /* 13594 */ "XVEXTH_WU_HU\0" |
| 6263 | /* 13607 */ "XVSLLWIL_WU_HU\0" |
| 6264 | /* 13622 */ "VEXT2XV_WU_HU\0" |
| 6265 | /* 13636 */ "XVHSUBW_WU_HU\0" |
| 6266 | /* 13650 */ "XVHADDW_WU_HU\0" |
| 6267 | /* 13664 */ "XVDIV_HU\0" |
| 6268 | /* 13673 */ "XVSUBWOD_W_HU\0" |
| 6269 | /* 13687 */ "XVMADDWOD_W_HU\0" |
| 6270 | /* 13702 */ "XVADDWOD_W_HU\0" |
| 6271 | /* 13716 */ "XVMULWOD_W_HU\0" |
| 6272 | /* 13730 */ "XVSUBWEV_W_HU\0" |
| 6273 | /* 13744 */ "XVMADDWEV_W_HU\0" |
| 6274 | /* 13759 */ "XVADDWEV_W_HU\0" |
| 6275 | /* 13773 */ "XVMULWEV_W_HU\0" |
| 6276 | /* 13787 */ "XVMAX_HU\0" |
| 6277 | /* 13796 */ "LDX_HU\0" |
| 6278 | /* 13803 */ "XVFFINT_D_LU\0" |
| 6279 | /* 13816 */ "BLTU\0" |
| 6280 | /* 13821 */ "SLTU\0" |
| 6281 | /* 13826 */ "AMMIN__DB_WU\0" |
| 6282 | /* 13839 */ "AMMAX__DB_WU\0" |
| 6283 | /* 13852 */ "X86SUB_WU\0" |
| 6284 | /* 13862 */ "XVSSUB_WU\0" |
| 6285 | /* 13872 */ "X86ADD_WU\0" |
| 6286 | /* 13882 */ "XVSADD_WU\0" |
| 6287 | /* 13892 */ "LD_WU\0" |
| 6288 | /* 13898 */ "XVMOD_WU\0" |
| 6289 | /* 13907 */ "XVABSD_WU\0" |
| 6290 | /* 13917 */ "XVSUBWOD_D_WU\0" |
| 6291 | /* 13931 */ "XVMADDWOD_D_WU\0" |
| 6292 | /* 13946 */ "XVADDWOD_D_WU\0" |
| 6293 | /* 13960 */ "XVMULWOD_D_WU\0" |
| 6294 | /* 13974 */ "XVSUBWEV_D_WU\0" |
| 6295 | /* 13988 */ "XVMADDWEV_D_WU\0" |
| 6296 | /* 14003 */ "XVADDWEV_D_WU\0" |
| 6297 | /* 14017 */ "XVMULWEV_D_WU\0" |
| 6298 | /* 14031 */ "MULW_D_WU\0" |
| 6299 | /* 14041 */ "XVSLE_WU\0" |
| 6300 | /* 14050 */ "XVAVG_WU\0" |
| 6301 | /* 14059 */ "MULH_WU\0" |
| 6302 | /* 14067 */ "XVMUH_WU\0" |
| 6303 | /* 14076 */ "XVSUBI_WU\0" |
| 6304 | /* 14086 */ "XVADDI_WU\0" |
| 6305 | /* 14096 */ "XVSLEI_WU\0" |
| 6306 | /* 14106 */ "XVMINI_WU\0" |
| 6307 | /* 14116 */ "XVSLTI_WU\0" |
| 6308 | /* 14126 */ "XVMAXI_WU\0" |
| 6309 | /* 14136 */ "ALSL_WU\0" |
| 6310 | /* 14144 */ "X86MUL_WU\0" |
| 6311 | /* 14154 */ "AMMIN_WU\0" |
| 6312 | /* 14163 */ "XVMIN_WU\0" |
| 6313 | /* 14172 */ "XVPICKVE2GR_WU\0" |
| 6314 | /* 14187 */ "XVAVGR_WU\0" |
| 6315 | /* 14197 */ "XVFFINT_S_WU\0" |
| 6316 | /* 14210 */ "XVSAT_WU\0" |
| 6317 | /* 14219 */ "XVSLT_WU\0" |
| 6318 | /* 14228 */ "XVEXTH_DU_WU\0" |
| 6319 | /* 14241 */ "XVSLLWIL_DU_WU\0" |
| 6320 | /* 14256 */ "VEXT2XV_DU_WU\0" |
| 6321 | /* 14270 */ "XVHSUBW_DU_WU\0" |
| 6322 | /* 14284 */ "XVHADDW_DU_WU\0" |
| 6323 | /* 14298 */ "XVDIV_WU\0" |
| 6324 | /* 14307 */ "AMMAX_WU\0" |
| 6325 | /* 14316 */ "XVMAX_WU\0" |
| 6326 | /* 14325 */ "LDX_WU\0" |
| 6327 | /* 14332 */ "G_FDIV\0" |
| 6328 | /* 14339 */ "G_STRICT_FDIV\0" |
| 6329 | /* 14353 */ "G_SDIV\0" |
| 6330 | /* 14360 */ "G_UDIV\0" |
| 6331 | /* 14367 */ "G_GET_FPENV\0" |
| 6332 | /* 14379 */ "G_RESET_FPENV\0" |
| 6333 | /* 14393 */ "G_SET_FPENV\0" |
| 6334 | /* 14405 */ "XVAND_V\0" |
| 6335 | /* 14413 */ "XVBITSEL_V\0" |
| 6336 | /* 14424 */ "XVBSLL_V\0" |
| 6337 | /* 14433 */ "XVBSRL_V\0" |
| 6338 | /* 14442 */ "XVANDN_V\0" |
| 6339 | /* 14451 */ "XVORN_V\0" |
| 6340 | /* 14459 */ "XVNOR_V\0" |
| 6341 | /* 14467 */ "XVOR_V\0" |
| 6342 | /* 14474 */ "XVXOR_V\0" |
| 6343 | /* 14482 */ "XVSETNEZ_V\0" |
| 6344 | /* 14493 */ "XVSETEQZ_V\0" |
| 6345 | /* 14504 */ "REVB_2W\0" |
| 6346 | /* 14512 */ "REVH_2W\0" |
| 6347 | /* 14520 */ "G_FPOW\0" |
| 6348 | /* 14527 */ "XVREPLVE0_W\0" |
| 6349 | /* 14539 */ "XVINSVE0_W\0" |
| 6350 | /* 14550 */ "XVADDA_W\0" |
| 6351 | /* 14559 */ "X86SRA_W\0" |
| 6352 | /* 14568 */ "ARMSRA_W\0" |
| 6353 | /* 14577 */ "XVSRA_W\0" |
| 6354 | /* 14585 */ "AMADD__DB_W\0" |
| 6355 | /* 14597 */ "AMAND__DB_W\0" |
| 6356 | /* 14609 */ "AMMIN__DB_W\0" |
| 6357 | /* 14621 */ "AMSWAP__DB_W\0" |
| 6358 | /* 14634 */ "AMOR__DB_W\0" |
| 6359 | /* 14645 */ "AMXOR__DB_W\0" |
| 6360 | /* 14657 */ "AMCAS__DB_W\0" |
| 6361 | /* 14669 */ "AMMAX__DB_W\0" |
| 6362 | /* 14681 */ "X86SUB_W\0" |
| 6363 | /* 14690 */ "ARMSUB_W\0" |
| 6364 | /* 14699 */ "XVMSUB_W\0" |
| 6365 | /* 14708 */ "XVSSUB_W\0" |
| 6366 | /* 14717 */ "XVSUB_W\0" |
| 6367 | /* 14725 */ "CRCC_W_B_W\0" |
| 6368 | /* 14736 */ "CRC_W_B_W\0" |
| 6369 | /* 14746 */ "X86SBC_W\0" |
| 6370 | /* 14755 */ "ARMSBC_W\0" |
| 6371 | /* 14764 */ "X86ADC_W\0" |
| 6372 | /* 14773 */ "ARMADC_W\0" |
| 6373 | /* 14782 */ "X86DEC_W\0" |
| 6374 | /* 14791 */ "X86INC_W\0" |
| 6375 | /* 14800 */ "SC_W\0" |
| 6376 | /* 14805 */ "X86ADD_W\0" |
| 6377 | /* 14814 */ "AMADD_W\0" |
| 6378 | /* 14822 */ "ARMADD_W\0" |
| 6379 | /* 14831 */ "XVMADD_W\0" |
| 6380 | /* 14840 */ "XVSADD_W\0" |
| 6381 | /* 14849 */ "XVADD_W\0" |
| 6382 | /* 14857 */ "LD_W\0" |
| 6383 | /* 14862 */ "X86AND_W\0" |
| 6384 | /* 14871 */ "AMAND_W\0" |
| 6385 | /* 14879 */ "ARMAND_W\0" |
| 6386 | /* 14888 */ "XVPACKOD_W\0" |
| 6387 | /* 14899 */ "XVPICKOD_W\0" |
| 6388 | /* 14910 */ "XVMOD_W\0" |
| 6389 | /* 14918 */ "IOCSRRD_W\0" |
| 6390 | /* 14928 */ "XVABSD_W\0" |
| 6391 | /* 14937 */ "XVSUBWOD_D_W\0" |
| 6392 | /* 14950 */ "XVMADDWOD_D_W\0" |
| 6393 | /* 14964 */ "XVADDWOD_D_W\0" |
| 6394 | /* 14977 */ "XVMULWOD_D_W\0" |
| 6395 | /* 14990 */ "XVFFINTH_D_W\0" |
| 6396 | /* 15003 */ "XVEXTH_D_W\0" |
| 6397 | /* 15014 */ "XVSLLWIL_D_W\0" |
| 6398 | /* 15027 */ "XVFFINTL_D_W\0" |
| 6399 | /* 15040 */ "FFINT_D_W\0" |
| 6400 | /* 15050 */ "XVSUBWEV_D_W\0" |
| 6401 | /* 15063 */ "XVMADDWEV_D_W\0" |
| 6402 | /* 15077 */ "XVADDWEV_D_W\0" |
| 6403 | /* 15090 */ "XVMULWEV_D_W\0" |
| 6404 | /* 15103 */ "VEXT2XV_D_W\0" |
| 6405 | /* 15115 */ "XVHSUBW_D_W\0" |
| 6406 | /* 15127 */ "XVHADDW_D_W\0" |
| 6407 | /* 15139 */ "MULW_D_W\0" |
| 6408 | /* 15148 */ "CRCC_W_D_W\0" |
| 6409 | /* 15159 */ "CRC_W_D_W\0" |
| 6410 | /* 15169 */ "LDLE_W\0" |
| 6411 | /* 15176 */ "XVSLE_W\0" |
| 6412 | /* 15184 */ "STLE_W\0" |
| 6413 | /* 15191 */ "XVPICKVE_W\0" |
| 6414 | /* 15202 */ "XVREPLVE_W\0" |
| 6415 | /* 15213 */ "XVSHUF_W\0" |
| 6416 | /* 15222 */ "XVNEG_W\0" |
| 6417 | /* 15230 */ "XVAVG_W\0" |
| 6418 | /* 15238 */ "RDTIMEH_W\0" |
| 6419 | /* 15248 */ "MULH_W\0" |
| 6420 | /* 15255 */ "MOVGR2FRH_W\0" |
| 6421 | /* 15267 */ "XVMUH_W\0" |
| 6422 | /* 15275 */ "XVILVH_W\0" |
| 6423 | /* 15284 */ "XVSSRANI_H_W\0" |
| 6424 | /* 15297 */ "XVSRANI_H_W\0" |
| 6425 | /* 15309 */ "XVSSRLNI_H_W\0" |
| 6426 | /* 15322 */ "XVSRLNI_H_W\0" |
| 6427 | /* 15334 */ "XVSSRARNI_H_W\0" |
| 6428 | /* 15348 */ "XVSRARNI_H_W\0" |
| 6429 | /* 15361 */ "XVSSRLRNI_H_W\0" |
| 6430 | /* 15375 */ "XVSRLRNI_H_W\0" |
| 6431 | /* 15388 */ "XVSSRAN_H_W\0" |
| 6432 | /* 15400 */ "XVSRAN_H_W\0" |
| 6433 | /* 15411 */ "XVSSRLN_H_W\0" |
| 6434 | /* 15423 */ "XVSRLN_H_W\0" |
| 6435 | /* 15434 */ "XVSSRARN_H_W\0" |
| 6436 | /* 15447 */ "XVSRARN_H_W\0" |
| 6437 | /* 15459 */ "XVSSRLRN_H_W\0" |
| 6438 | /* 15472 */ "XVSRLRN_H_W\0" |
| 6439 | /* 15484 */ "CRCC_W_H_W\0" |
| 6440 | /* 15495 */ "CRC_W_H_W\0" |
| 6441 | /* 15505 */ "ADDU12I_W\0" |
| 6442 | /* 15515 */ "LU12I_W\0" |
| 6443 | /* 15523 */ "XVSHUF4I_W\0" |
| 6444 | /* 15534 */ "X86SRAI_W\0" |
| 6445 | /* 15544 */ "ARMSRAI_W\0" |
| 6446 | /* 15554 */ "XVSRAI_W\0" |
| 6447 | /* 15563 */ "ADDI_W\0" |
| 6448 | /* 15570 */ "XVSLEI_W\0" |
| 6449 | /* 15579 */ "XVREPL128VEI_W\0" |
| 6450 | /* 15594 */ "VREPLVEI_W\0" |
| 6451 | /* 15605 */ "X86RCLI_W\0" |
| 6452 | /* 15615 */ "X86SLLI_W\0" |
| 6453 | /* 15625 */ "ARMSLLI_W\0" |
| 6454 | /* 15635 */ "XVSLLI_W\0" |
| 6455 | /* 15644 */ "PseudoXVREPLI_W\0" |
| 6456 | /* 15660 */ "PseudoVREPLI_W\0" |
| 6457 | /* 15675 */ "X86SRLI_W\0" |
| 6458 | /* 15685 */ "ARMSRLI_W\0" |
| 6459 | /* 15695 */ "XVSRLI_W\0" |
| 6460 | /* 15704 */ "X86ROTLI_W\0" |
| 6461 | /* 15715 */ "PseudoLI_W\0" |
| 6462 | /* 15726 */ "XVPERMI_W\0" |
| 6463 | /* 15736 */ "XVMINI_W\0" |
| 6464 | /* 15745 */ "XVSEQI_W\0" |
| 6465 | /* 15754 */ "XVSRARI_W\0" |
| 6466 | /* 15764 */ "X86RCRI_W\0" |
| 6467 | /* 15774 */ "XVBITCLRI_W\0" |
| 6468 | /* 15786 */ "XVSRLRI_W\0" |
| 6469 | /* 15796 */ "X86ROTRI_W\0" |
| 6470 | /* 15807 */ "ARMROTRI_W\0" |
| 6471 | /* 15818 */ "XVROTRI_W\0" |
| 6472 | /* 15828 */ "XVBITSETI_W\0" |
| 6473 | /* 15840 */ "XVSLTI_W\0" |
| 6474 | /* 15849 */ "XVBITREVI_W\0" |
| 6475 | /* 15861 */ "XVMAXI_W\0" |
| 6476 | /* 15870 */ "BYTEPICK_W\0" |
| 6477 | /* 15881 */ "BSTRPICK_W\0" |
| 6478 | /* 15892 */ "X86RCL_W\0" |
| 6479 | /* 15901 */ "LDL_W\0" |
| 6480 | /* 15907 */ "RDTIMEL_W\0" |
| 6481 | /* 15917 */ "SCREL_W\0" |
| 6482 | /* 15925 */ "X86SLL_W\0" |
| 6483 | /* 15934 */ "ARMSLL_W\0" |
| 6484 | /* 15943 */ "XVSLL_W\0" |
| 6485 | /* 15951 */ "XVLDREPL_W\0" |
| 6486 | /* 15962 */ "X86SRL_W\0" |
| 6487 | /* 15971 */ "ARMSRL_W\0" |
| 6488 | /* 15980 */ "XVSRL_W\0" |
| 6489 | /* 15988 */ "ALSL_W\0" |
| 6490 | /* 15995 */ "X86ROTL_W\0" |
| 6491 | /* 16005 */ "STL_W\0" |
| 6492 | /* 16011 */ "X86MUL_W\0" |
| 6493 | /* 16020 */ "XVMUL_W\0" |
| 6494 | /* 16028 */ "XVILVL_W\0" |
| 6495 | /* 16037 */ "XVSTELM_W\0" |
| 6496 | /* 16047 */ "XVPERM_W\0" |
| 6497 | /* 16056 */ "AMMIN_W\0" |
| 6498 | /* 16064 */ "XVMIN_W\0" |
| 6499 | /* 16072 */ "XVCLO_W\0" |
| 6500 | /* 16080 */ "CTO_W\0" |
| 6501 | /* 16086 */ "AMSWAP_W\0" |
| 6502 | /* 16095 */ "LLACQ_W\0" |
| 6503 | /* 16103 */ "XVSEQ_W\0" |
| 6504 | /* 16111 */ "XVSRAR_W\0" |
| 6505 | /* 16120 */ "X86RCR_W\0" |
| 6506 | /* 16129 */ "LDR_W\0" |
| 6507 | /* 16135 */ "MOVGR2FR_W\0" |
| 6508 | /* 16146 */ "XVPICKVE2GR_W\0" |
| 6509 | /* 16160 */ "XVAVGR_W\0" |
| 6510 | /* 16169 */ "XVBITCLR_W\0" |
| 6511 | /* 16180 */ "XVSRLR_W\0" |
| 6512 | /* 16189 */ "X86OR_W\0" |
| 6513 | /* 16197 */ "AMOR_W\0" |
| 6514 | /* 16204 */ "ARMOR_W\0" |
| 6515 | /* 16212 */ "X86XOR_W\0" |
| 6516 | /* 16221 */ "AMXOR_W\0" |
| 6517 | /* 16229 */ "ARMXOR_W\0" |
| 6518 | /* 16238 */ "X86ROTR_W\0" |
| 6519 | /* 16248 */ "ARMROTR_W\0" |
| 6520 | /* 16258 */ "XVROTR_W\0" |
| 6521 | /* 16267 */ "LDPTR_W\0" |
| 6522 | /* 16275 */ "STPTR_W\0" |
| 6523 | /* 16283 */ "STR_W\0" |
| 6524 | /* 16289 */ "XVREPLGR2VR_W\0" |
| 6525 | /* 16303 */ "XVINSGR2VR_W\0" |
| 6526 | /* 16316 */ "IOCSRWR_W\0" |
| 6527 | /* 16326 */ "AMCAS_W\0" |
| 6528 | /* 16334 */ "BSTRINS_W\0" |
| 6529 | /* 16344 */ "XVEXTRINS_W\0" |
| 6530 | /* 16356 */ "XVFFINT_S_W\0" |
| 6531 | /* 16368 */ "XVSAT_W\0" |
| 6532 | /* 16376 */ "XVBITSET_W\0" |
| 6533 | /* 16387 */ "LDGT_W\0" |
| 6534 | /* 16394 */ "STGT_W\0" |
| 6535 | /* 16401 */ "XVSLT_W\0" |
| 6536 | /* 16409 */ "XVPCNT_W\0" |
| 6537 | /* 16418 */ "ARMNOT_W\0" |
| 6538 | /* 16427 */ "ST_W\0" |
| 6539 | /* 16432 */ "XVSSRANI_HU_W\0" |
| 6540 | /* 16446 */ "XVSSRLNI_HU_W\0" |
| 6541 | /* 16460 */ "XVSSRARNI_HU_W\0" |
| 6542 | /* 16475 */ "XVSSRLRNI_HU_W\0" |
| 6543 | /* 16490 */ "XVSSRAN_HU_W\0" |
| 6544 | /* 16503 */ "XVSSRLN_HU_W\0" |
| 6545 | /* 16516 */ "XVSSRARN_HU_W\0" |
| 6546 | /* 16530 */ "XVSSRLRN_HU_W\0" |
| 6547 | /* 16544 */ "XVMADDWOD_D_WU_W\0" |
| 6548 | /* 16561 */ "XVADDWOD_D_WU_W\0" |
| 6549 | /* 16577 */ "XVMULWOD_D_WU_W\0" |
| 6550 | /* 16593 */ "XVMADDWEV_D_WU_W\0" |
| 6551 | /* 16610 */ "XVADDWEV_D_WU_W\0" |
| 6552 | /* 16626 */ "XVMULWEV_D_WU_W\0" |
| 6553 | /* 16642 */ "XVPACKEV_W\0" |
| 6554 | /* 16653 */ "XVPICKEV_W\0" |
| 6555 | /* 16664 */ "XVBITREV_W\0" |
| 6556 | /* 16675 */ "XVDIV_W\0" |
| 6557 | /* 16683 */ "XVSIGNCOV_W\0" |
| 6558 | /* 16695 */ "ARMMOV_W\0" |
| 6559 | /* 16704 */ "CRCC_W_W_W\0" |
| 6560 | /* 16715 */ "CRC_W_W_W\0" |
| 6561 | /* 16725 */ "AMMAX_W\0" |
| 6562 | /* 16733 */ "XVMAX_W\0" |
| 6563 | /* 16741 */ "LDX_W\0" |
| 6564 | /* 16747 */ "ARMRRX_W\0" |
| 6565 | /* 16756 */ "STX_W\0" |
| 6566 | /* 16762 */ "PseudoXVBZ_W\0" |
| 6567 | /* 16775 */ "PseudoVBZ_W\0" |
| 6568 | /* 16787 */ "XVSETALLNEZ_W\0" |
| 6569 | /* 16801 */ "XVCLZ_W\0" |
| 6570 | /* 16809 */ "PseudoXVBNZ_W\0" |
| 6571 | /* 16823 */ "PseudoVBNZ_W\0" |
| 6572 | /* 16836 */ "XVSETANYEQZ_W\0" |
| 6573 | /* 16850 */ "CTZ_W\0" |
| 6574 | /* 16856 */ "XVMSKLTZ_W\0" |
| 6575 | /* 16867 */ "PseudoAddTPRel_W\0" |
| 6576 | /* 16884 */ "PseudoAtomicStoreW\0" |
| 6577 | /* 16903 */ "G_VECREDUCE_FMAX\0" |
| 6578 | /* 16920 */ "G_ATOMICRMW_FMAX\0" |
| 6579 | /* 16937 */ "G_VECREDUCE_SMAX\0" |
| 6580 | /* 16954 */ "G_SMAX\0" |
| 6581 | /* 16961 */ "G_VECREDUCE_UMAX\0" |
| 6582 | /* 16978 */ "G_UMAX\0" |
| 6583 | /* 16985 */ "G_ATOMICRMW_UMAX\0" |
| 6584 | /* 17002 */ "G_ATOMICRMW_MAX\0" |
| 6585 | /* 17018 */ "PRELDX\0" |
| 6586 | /* 17025 */ "XVLDX\0" |
| 6587 | /* 17031 */ "G_FRAME_INDEX\0" |
| 6588 | /* 17045 */ "G_SBFX\0" |
| 6589 | /* 17052 */ "G_UBFX\0" |
| 6590 | /* 17059 */ "G_SMULFIX\0" |
| 6591 | /* 17069 */ "G_UMULFIX\0" |
| 6592 | /* 17079 */ "G_SDIVFIX\0" |
| 6593 | /* 17089 */ "G_UDIVFIX\0" |
| 6594 | /* 17099 */ "XVSTX\0" |
| 6595 | /* 17105 */ "G_MEMCPY\0" |
| 6596 | /* 17114 */ "COPY\0" |
| 6597 | /* 17119 */ "CONVERGENCECTRL_ENTRY\0" |
| 6598 | /* 17141 */ "PseudoXVBZ\0" |
| 6599 | /* 17152 */ "PseudoVBZ\0" |
| 6600 | /* 17162 */ "BNEZ\0" |
| 6601 | /* 17167 */ "BCNEZ\0" |
| 6602 | /* 17173 */ "MASKNEZ\0" |
| 6603 | /* 17181 */ "G_CTLZ\0" |
| 6604 | /* 17188 */ "PseudoXVBNZ\0" |
| 6605 | /* 17200 */ "PseudoVBNZ\0" |
| 6606 | /* 17211 */ "BEQZ\0" |
| 6607 | /* 17216 */ "BCEQZ\0" |
| 6608 | /* 17222 */ "MASKEQZ\0" |
| 6609 | /* 17230 */ "G_CTTZ\0" |
| 6610 | /* 17237 */ "PseudoTAILIndirect\0" |
| 6611 | /* 17256 */ "PseudoCALLIndirect\0" |
| 6612 | }; |
| 6613 | #ifdef __GNUC__ |
| 6614 | #pragma GCC diagnostic pop |
| 6615 | #endif |
| 6616 | |
| 6617 | extern const unsigned LoongArchInstrNameIndices[] = { |
| 6618 | 8499U, 9063U, 10077U, 9410U, 8609U, 8590U, 8618U, 8870U, |
| 6619 | 6459U, 6474U, 6375U, 6501U, 10721U, 6191U, 12427U, 6388U, |
| 6620 | 8495U, 8599U, 5677U, 17114U, 6038U, 12331U, 2597U, 5628U, |
| 6621 | 5665U, 9530U, 8839U, 12228U, 2694U, 9793U, 6580U, 12217U, |
| 6622 | 6094U, 9766U, 9753U, 10157U, 12058U, 12091U, 8755U, 8818U, |
| 6623 | 8791U, 8635U, 10122U, 9484U, 17119U, 10358U, 9686U, 6239U, |
| 6624 | 12462U, 12492U, 9253U, 2457U, 638U, 8978U, 14353U, 14360U, |
| 6625 | 9029U, 9036U, 9043U, 9053U, 2575U, 10533U, 10496U, 6373U, |
| 6626 | 8497U, 17031U, 6201U, 6216U, 8875U, 12026U, 10657U, 12368U, |
| 6627 | 10674U, 10433U, 2217U, 10704U, 12239U, 10585U, 12400U, 6303U, |
| 6628 | 10133U, 2668U, 2191U, 2650U, 12277U, 12258U, 9231U, 10182U, |
| 6629 | 10201U, 2358U, 2302U, 2332U, 2343U, 2283U, 2313U, 6150U, |
| 6630 | 6134U, 10751U, 6522U, 6548U, 2473U, 644U, 2581U, 2542U, |
| 6631 | 10538U, 10502U, 17002U, 9379U, 16985U, 9362U, 2424U, 621U, |
| 6632 | 16920U, 9297U, 9592U, 9570U, 5657U, 6621U, 2622U, 12045U, |
| 6633 | 12346U, 2169U, 10799U, 12194U, 10826U, 12476U, 2209U, 12183U, |
| 6634 | 12171U, 12321U, 6572U, 12455U, 6488U, 12485U, 8677U, 10338U, |
| 6635 | 10324U, 8670U, 10331U, 10578U, 8896U, 9647U, 9640U, 9654U, |
| 6636 | 9661U, 12036U, 9476U, 5698U, 9460U, 5649U, 9468U, 5690U, |
| 6637 | 9452U, 5641U, 9514U, 9506U, 6640U, 6632U, 11944U, 11934U, |
| 6638 | 11924U, 11914U, 11964U, 11954U, 17059U, 17069U, 11974U, 11987U, |
| 6639 | 17079U, 17089U, 12000U, 12013U, 2382U, 600U, 8920U, 554U, |
| 6640 | 2276U, 14332U, 9008U, 14520U, 8537U, 9837U, 453U, 9U, |
| 6641 | 6565U, 445U, 0U, 9812U, 9844U, 6452U, 12447U, 2181U, |
| 6642 | 8508U, 8522U, 9622U, 9631U, 10609U, 9268U, 10738U, 6312U, |
| 6643 | 9191U, 9201U, 5747U, 5762U, 9148U, 9180U, 14367U, 14393U, |
| 6644 | 14379U, 5706U, 5734U, 5719U, 2463U, 8567U, 9331U, 16954U, |
| 6645 | 9355U, 16978U, 10651U, 2641U, 2631U, 10072U, 12115U, 6011U, |
| 6646 | 10414U, 10394U, 12147U, 12126U, 10448U, 10465U, 10781U, 17230U, |
| 6647 | 6355U, 17181U, 6337U, 9707U, 9614U, 6172U, 8723U, 10697U, |
| 6648 | 9403U, 9219U, 10689U, 9395U, 9211U, 6664U, 6656U, 6648U, |
| 6649 | 12377U, 10385U, 12250U, 12295U, 12410U, 10109U, 6020U, 2238U, |
| 6650 | 6273U, 6119U, 2410U, 607U, 8948U, 14339U, 9015U, 560U, |
| 6651 | 12385U, 9821U, 10221U, 10237U, 17105U, 6065U, 6285U, 12082U, |
| 6652 | 9522U, 9563U, 9539U, 9551U, 2389U, 8927U, 2365U, 8903U, |
| 6653 | 16903U, 9280U, 9159U, 9127U, 2441U, 8962U, 2559U, 10518U, |
| 6654 | 10480U, 16937U, 9314U, 16961U, 9338U, 17045U, 17052U, 9435U, |
| 6655 | 9778U, 5584U, 16867U, 110U, 132U, 183U, 489U, 345U, |
| 6656 | 60U, 366U, 5601U, 16884U, 326U, 10090U, 2610U, 8683U, |
| 6657 | 8851U, 541U, 17256U, 5912U, 9109U, 228U, 512U, 10280U, |
| 6658 | 8739U, 8775U, 8696U, 10616U, 5929U, 12308U, 5976U, 8655U, |
| 6659 | 5874U, 10629U, 5948U, 2255U, 5781U, 2489U, 5808U, 5995U, |
| 6660 | 5852U, 2526U, 5830U, 6045U, 10254U, 3693U, 15715U, 82U, |
| 6661 | 417U, 273U, 154U, 32U, 388U, 244U, 301U, 206U, |
| 6662 | 12072U, 10267U, 8712U, 528U, 17237U, 5895U, 9091U, 9668U, |
| 6663 | 17200U, 2121U, 5528U, 8409U, 16823U, 17152U, 2062U, 5480U, |
| 6664 | 8361U, 16775U, 1296U, 3648U, 7331U, 15660U, 17188U, 2107U, |
| 6665 | 5514U, 8395U, 16809U, 17141U, 2049U, 5467U, 8348U, 16762U, |
| 6666 | 1754U, 7763U, 1280U, 3632U, 7315U, 15644U, 10564U, 10571U, |
| 6667 | 782U, 2993U, 7004U, 14767U, 3551U, 15563U, 3485U, 15505U, |
| 6668 | 3522U, 3025U, 14808U, 3927U, 15988U, 14136U, 815U, 3040U, |
| 6669 | 7037U, 14814U, 698U, 2793U, 6720U, 14585U, 3120U, 14871U, |
| 6670 | 2805U, 14597U, 1783U, 4632U, 7792U, 16326U, 723U, 2865U, |
| 6671 | 6745U, 14657U, 5437U, 13364U, 16725U, 14307U, 2877U, 12949U, |
| 6672 | 14669U, 13839U, 4097U, 13126U, 16056U, 14154U, 2817U, 12936U, |
| 6673 | 14609U, 13826U, 4517U, 16197U, 2842U, 14634U, 1617U, 4153U, |
| 6674 | 7626U, 16086U, 710U, 2829U, 6732U, 14621U, 4546U, 16221U, |
| 6675 | 2853U, 14645U, 2555U, 8490U, 9226U, 14773U, 14822U, 14879U, |
| 6676 | 6412U, 6295U, 5150U, 16695U, 6432U, 16418U, 16204U, 15807U, |
| 6677 | 16248U, 16747U, 14755U, 15625U, 15934U, 15544U, 14568U, 15685U, |
| 6678 | 15971U, 14690U, 16229U, 4718U, 3229U, 581U, 17216U, 17167U, |
| 6679 | 9853U, 17211U, 5777U, 13382U, 573U, 583U, 5105U, 16666U, |
| 6680 | 8577U, 12122U, 13816U, 6061U, 17162U, 8561U, 4647U, 16334U, |
| 6681 | 3848U, 15881U, 3837U, 15870U, 9680U, 4141U, 16074U, 5508U, |
| 6682 | 16803U, 6515U, 14725U, 15148U, 15484U, 16704U, 14736U, 15159U, |
| 6683 | 15495U, 16715U, 2718U, 10603U, 6540U, 4147U, 16080U, 5567U, |
| 6684 | 16850U, 10062U, 8580U, 5117U, 13357U, 16677U, 14300U, 9430U, |
| 6685 | 2009U, 8231U, 4640U, 11609U, 3033U, 10936U, 4671U, 11618U, |
| 6686 | 3398U, 11166U, 4195U, 11508U, 3189U, 11005U, 4737U, 11645U, |
| 6687 | 3285U, 11075U, 4506U, 11585U, 4229U, 11534U, 3248U, 11047U, |
| 6688 | 4771U, 11671U, 3324U, 11114U, 4115U, 11459U, 3411U, 11179U, |
| 6689 | 4216U, 11521U, 3218U, 11026U, 4758U, 11658U, 3311U, 11101U, |
| 6690 | 4526U, 11598U, 4243U, 11548U, 3262U, 11061U, 4785U, 11685U, |
| 6691 | 3338U, 11128U, 4128U, 11472U, 4076U, 11436U, 2516U, 10994U, |
| 6692 | 3101U, 4682U, 3177U, 5116U, 11764U, 8986U, 15040U, 8998U, |
| 6693 | 16358U, 4710U, 11627U, 3200U, 11016U, 5453U, 11856U, 3095U, |
| 6694 | 10964U, 2901U, 10896U, 3050U, 10945U, 2785U, 10876U, 5430U, |
| 6695 | 11849U, 2758U, 10866U, 4090U, 11450U, 5143U, 11771U, 2929U, |
| 6696 | 10915U, 3961U, 11210U, 3431U, 11190U, 3060U, 10955U, 2939U, |
| 6697 | 10925U, 3352U, 11142U, 4164U, 11485U, 4808U, 11699U, 3364U, |
| 6698 | 11154U, 4828U, 11719U, 2889U, 10884U, 5620U, 11894U, 4818U, |
| 6699 | 11709U, 4727U, 11635U, 3238U, 11037U, 5460U, 11863U, 4837U, |
| 6700 | 11728U, 2920U, 10906U, 4002U, 11378U, 5280U, 11795U, 3987U, |
| 6701 | 11217U, 5161U, 11780U, 4016U, 11390U, 5390U, 11809U, 4042U, |
| 6702 | 11412U, 5416U, 11835U, 4030U, 11402U, 5404U, 11823U, 2717U, |
| 6703 | 10602U, 6539U, 6672U, 8585U, 10067U, 6033U, 593U, 893U, |
| 6704 | 3158U, 7115U, 14918U, 1773U, 4622U, 7782U, 16316U, 8891U, |
| 6705 | 18U, 25U, 10345U, 1822U, 4711U, 7855U, 16387U, 924U, |
| 6706 | 3201U, 7146U, 15169U, 3868U, 15901U, 6185U, 4573U, 16267U, |
| 6707 | 4425U, 16129U, 2037U, 12929U, 5454U, 8336U, 13796U, 16741U, |
| 6708 | 14325U, 849U, 12526U, 3096U, 7071U, 13407U, 14857U, 13892U, |
| 6709 | 4185U, 16095U, 3886U, 15929U, 15515U, 3495U, 3503U, 17222U, |
| 6710 | 17173U, 3152U, 13004U, 14912U, 13900U, 11902U, 10294U, 10313U, |
| 6711 | 11882U, 4456U, 11572U, 461U, 11560U, 6328U, 10553U, 15255U, |
| 6712 | 4431U, 16135U, 475U, 10099U, 10303U, 3454U, 13039U, 15248U, |
| 6713 | 14059U, 15139U, 14031U, 3953U, 16014U, 10381U, 10378U, 8504U, |
| 6714 | 9426U, 8477U, 8457U, 8467U, 8447U, 2505U, 17018U, 1383U, |
| 6715 | 3745U, 7418U, 15767U, 1656U, 4419U, 7665U, 16123U, 15238U, |
| 6716 | 15907U, 3274U, 6597U, 14504U, 6605U, 2974U, 14512U, 3469U, |
| 6717 | 1441U, 3777U, 7450U, 15799U, 1724U, 4557U, 7733U, 16241U, |
| 6718 | 773U, 2984U, 6995U, 14749U, 3874U, 15917U, 3017U, 9877U, |
| 6719 | 14800U, 8553U, 8545U, 6107U, 6081U, 6158U, 6260U, 3616U, |
| 6720 | 15618U, 3885U, 15928U, 12167U, 8517U, 13821U, 8531U, 3535U, |
| 6721 | 15537U, 2769U, 14562U, 3666U, 15678U, 3913U, 15965U, 1829U, |
| 6722 | 4728U, 7862U, 16394U, 939U, 3239U, 7161U, 15184U, 3944U, |
| 6723 | 16005U, 4581U, 16275U, 4589U, 16283U, 2043U, 5461U, 8342U, |
| 6724 | 16756U, 1853U, 4838U, 7886U, 16427U, 2912U, 14684U, 8731U, |
| 6725 | 10351U, 8862U, 6673U, 2711U, 6613U, 10596U, 904U, 12542U, |
| 6726 | 3169U, 13012U, 7126U, 13423U, 14929U, 13908U, 673U, 2748U, |
| 6727 | 6695U, 14551U, 12703U, 13067U, 13470U, 14087U, 15078U, 14004U, |
| 6728 | 16611U, 1104U, 12665U, 1925U, 4358U, 13231U, 4910U, 8267U, |
| 6729 | 13760U, 8070U, 14965U, 13947U, 16562U, 1027U, 12608U, 1876U, |
| 6730 | 4283U, 13174U, 4861U, 8182U, 13703U, 8021U, 842U, 3088U, |
| 6731 | 7064U, 9883U, 14850U, 1196U, 14443U, 14406U, 1676U, 12786U, |
| 6732 | 4468U, 13274U, 7685U, 13553U, 16161U, 14188U, 975U, 12561U, |
| 6733 | 3447U, 13031U, 7197U, 13442U, 15231U, 14051U, 1391U, 3753U, |
| 6734 | 7426U, 15775U, 1685U, 4477U, 7694U, 16170U, 1481U, 3817U, |
| 6735 | 7490U, 15850U, 1979U, 5104U, 8124U, 16665U, 1250U, 14414U, |
| 6736 | 1460U, 3796U, 7469U, 15829U, 1812U, 4700U, 7845U, 16377U, |
| 6737 | 14425U, 14434U, 1610U, 4140U, 7619U, 16073U, 2100U, 5507U, |
| 6738 | 8388U, 16802U, 1990U, 12912U, 5124U, 13356U, 8135U, 13665U, |
| 6739 | 16676U, 14299U, 12813U, 13580U, 14256U, 912U, 7134U, 15103U, |
| 6740 | 12855U, 1129U, 12897U, 13622U, 2017U, 8292U, 14229U, 15004U, |
| 6741 | 12828U, 1053U, 13302U, 4309U, 13595U, 8208U, 13315U, 4320U, |
| 6742 | 1792U, 4658U, 7801U, 16345U, 3032U, 10935U, 4670U, 11617U, |
| 6743 | 3397U, 11165U, 4194U, 11507U, 3188U, 11004U, 4736U, 11644U, |
| 6744 | 3284U, 11074U, 4505U, 11584U, 4228U, 11533U, 3247U, 11046U, |
| 6745 | 4770U, 11670U, 3323U, 11113U, 4114U, 11458U, 3410U, 11178U, |
| 6746 | 4215U, 11520U, 3217U, 11025U, 4757U, 11657U, 3310U, 11100U, |
| 6747 | 4525U, 11597U, 4242U, 11547U, 3261U, 11060U, 4784U, 11684U, |
| 6748 | 3337U, 11127U, 4127U, 11471U, 10971U, 7813U, 10983U, 7825U, |
| 6749 | 11198U, 4681U, 5115U, 11763U, 14991U, 15028U, 8985U, 13804U, |
| 6750 | 8997U, 16357U, 14198U, 2900U, 10895U, 3049U, 10944U, 2784U, |
| 6751 | 10875U, 5429U, 11848U, 2757U, 10865U, 4089U, 11449U, 2928U, |
| 6752 | 10914U, 3960U, 11209U, 3059U, 10954U, 2938U, 10924U, 3351U, |
| 6753 | 11141U, 4163U, 11484U, 4065U, 11425U, 3297U, 11087U, 4174U, |
| 6754 | 11495U, 5556U, 11871U, 4807U, 11698U, 3363U, 11153U, 4827U, |
| 6755 | 11718U, 1351U, 7386U, 1627U, 7636U, 4817U, 11708U, 2919U, |
| 6756 | 10905U, 11277U, 11351U, 11247U, 11321U, 4001U, 5279U, 11794U, |
| 6757 | 11231U, 11305U, 3986U, 5160U, 11779U, 11262U, 11336U, 4015U, |
| 6758 | 5389U, 11808U, 11290U, 11364U, 4955U, 4041U, 11748U, 5415U, |
| 6759 | 11834U, 4942U, 4029U, 11735U, 5403U, 11822U, 14285U, 15128U, |
| 6760 | 12884U, 1154U, 13342U, 4396U, 13651U, 8317U, 14271U, 15116U, |
| 6761 | 12870U, 1142U, 13328U, 4384U, 13637U, 8305U, 991U, 3477U, |
| 6762 | 7213U, 15276U, 1583U, 3977U, 7592U, 16029U, 1761U, 4610U, |
| 6763 | 7770U, 16304U, 2512U, 8485U, 1528U, 3900U, 7537U, 15952U, |
| 6764 | 17026U, 15064U, 13989U, 16594U, 1090U, 12650U, 1908U, 4344U, |
| 6765 | 13216U, 4893U, 8253U, 13745U, 8053U, 14951U, 13932U, 16545U, |
| 6766 | 1013U, 12593U, 1859U, 4269U, 13159U, 4844U, 8168U, 13688U, |
| 6767 | 8004U, 824U, 3070U, 7046U, 14832U, 1493U, 12743U, 3829U, |
| 6768 | 13107U, 7502U, 13510U, 15862U, 14127U, 2030U, 12921U, 5446U, |
| 6769 | 13374U, 8329U, 13788U, 16734U, 14317U, 1342U, 12723U, 3715U, |
| 6770 | 13087U, 7377U, 13490U, 15737U, 14107U, 1602U, 12763U, 4106U, |
| 6771 | 13136U, 7611U, 13530U, 16065U, 14164U, 886U, 12533U, 3151U, |
| 6772 | 13003U, 7108U, 13414U, 14911U, 13899U, 2075U, 2159U, 5574U, |
| 6773 | 8437U, 16857U, 2135U, 745U, 2949U, 6767U, 14700U, 983U, |
| 6774 | 12570U, 3462U, 13048U, 7205U, 13451U, 15268U, 14068U, 15091U, |
| 6775 | 14018U, 16627U, 1117U, 12679U, 1941U, 4371U, 13245U, 4926U, |
| 6776 | 8280U, 13774U, 8086U, 14978U, 13961U, 16578U, 1040U, 12622U, |
| 6777 | 1892U, 4296U, 13188U, 4877U, 8195U, 13717U, 8037U, 1575U, |
| 6778 | 3969U, 7584U, 16021U, 967U, 3439U, 7189U, 15223U, 1413U, |
| 6779 | 14460U, 1422U, 14452U, 14468U, 1957U, 5082U, 8102U, 16643U, |
| 6780 | 864U, 3129U, 7086U, 14889U, 1845U, 4798U, 7878U, 16410U, |
| 6781 | 15727U, 1968U, 5093U, 8113U, 16654U, 875U, 3140U, 7097U, |
| 6782 | 14900U, 1662U, 12771U, 4443U, 13259U, 7671U, 13538U, 16147U, |
| 6783 | 14173U, 1741U, 4596U, 7750U, 16290U, 1228U, 3582U, 7275U, |
| 6784 | 15594U, 947U, 3386U, 7169U, 15203U, 1450U, 3786U, 7459U, |
| 6785 | 15819U, 1732U, 4565U, 7741U, 16259U, 833U, 12517U, 3079U, |
| 6786 | 12993U, 7055U, 13398U, 14841U, 13883U, 1804U, 12796U, 4692U, |
| 6787 | 13284U, 7837U, 13563U, 16369U, 14211U, 1362U, 3724U, 7397U, |
| 6788 | 15746U, 1637U, 4207U, 7646U, 16104U, 2086U, 5493U, 8374U, |
| 6789 | 16788U, 2145U, 5542U, 8423U, 16837U, 14494U, 14483U, 1166U, |
| 6790 | 3512U, 7222U, 15524U, 958U, 3423U, 7180U, 15214U, 1998U, |
| 6791 | 5132U, 8143U, 16684U, 1205U, 12713U, 3559U, 13077U, 7252U, |
| 6792 | 13480U, 15571U, 14097U, 932U, 12552U, 3209U, 13022U, 7154U, |
| 6793 | 13433U, 15177U, 14042U, 1272U, 3624U, 7307U, 15636U, 14242U, |
| 6794 | 15015U, 12841U, 1064U, 13608U, 8219U, 1520U, 3892U, 7529U, |
| 6795 | 15944U, 1472U, 12733U, 3808U, 13097U, 7481U, 13500U, 15841U, |
| 6796 | 14117U, 1837U, 12805U, 4749U, 13293U, 7870U, 13572U, 16402U, |
| 6797 | 14220U, 1187U, 3543U, 7243U, 15555U, 6806U, 9904U, 15298U, |
| 6798 | 5188U, 6909U, 15401U, 5305U, 1371U, 3733U, 7406U, 15755U, |
| 6799 | 6857U, 9955U, 15349U, 5239U, 6956U, 15448U, 5352U, 1645U, |
| 6800 | 4408U, 7654U, 16112U, 691U, 2776U, 6713U, 14578U, 1322U, |
| 6801 | 3674U, 7357U, 15696U, 6831U, 9929U, 15323U, 5213U, 6932U, |
| 6802 | 15424U, 5328U, 1403U, 3765U, 7438U, 15787U, 6884U, 9982U, |
| 6803 | 15376U, 5266U, 6981U, 15473U, 5377U, 1696U, 4488U, 7705U, |
| 6804 | 16181U, 1548U, 3920U, 7557U, 15981U, 7892U, 6793U, 10005U, |
| 6805 | 9891U, 16433U, 15285U, 4970U, 5175U, 7950U, 6897U, 16491U, |
| 6806 | 15389U, 5028U, 5293U, 7920U, 6843U, 10033U, 9941U, 16461U, |
| 6807 | 15335U, 4998U, 5225U, 7976U, 6943U, 16517U, 15435U, 5054U, |
| 6808 | 5339U, 7906U, 6818U, 10019U, 9916U, 16447U, 15310U, 4984U, |
| 6809 | 5200U, 7963U, 6920U, 16504U, 15412U, 5041U, 5316U, 7935U, |
| 6810 | 6870U, 10048U, 9968U, 16476U, 15362U, 5013U, 5252U, 7990U, |
| 6811 | 6968U, 16531U, 15460U, 5068U, 5364U, 754U, 12507U, 2958U, |
| 6812 | 12973U, 6776U, 13388U, 14709U, 13863U, 12443U, 1592U, 4055U, |
| 6813 | 7601U, 16038U, 17100U, 12693U, 13057U, 13460U, 14077U, 15051U, |
| 6814 | 13975U, 1077U, 12636U, 4331U, 13202U, 8240U, 13731U, 14938U, |
| 6815 | 13918U, 1000U, 12579U, 4256U, 13145U, 8155U, 13674U, 763U, |
| 6816 | 2967U, 6785U, 9870U, 14718U, 1430U, 14475U, 779U, 2990U, |
| 6817 | 7001U, 14764U, 806U, 3022U, 12982U, 7028U, 14805U, 13872U, |
| 6818 | 854U, 3111U, 7076U, 14862U, 9073U, 9715U, 788U, 2999U, |
| 6819 | 7010U, 14782U, 9725U, 797U, 3008U, 7019U, 14791U, 6402U, |
| 6820 | 9735U, 6422U, 9744U, 1565U, 12752U, 3950U, 13116U, 7574U, |
| 6821 | 13519U, 16011U, 14144U, 1704U, 4496U, 7713U, 16189U, 1239U, |
| 6822 | 3593U, 7286U, 15605U, 1501U, 3859U, 7510U, 15892U, 1380U, |
| 6823 | 3742U, 7415U, 15764U, 1653U, 4416U, 7662U, 16120U, 1330U, |
| 6824 | 3682U, 7365U, 15704U, 1555U, 3934U, 7564U, 15995U, 1438U, |
| 6825 | 3774U, 7447U, 15796U, 1721U, 4554U, 7730U, 16238U, 770U, |
| 6826 | 2981U, 6992U, 14746U, 6442U, 9082U, 1261U, 3613U, 7296U, |
| 6827 | 15615U, 1510U, 3882U, 7519U, 15925U, 1176U, 3532U, 7232U, |
| 6828 | 15534U, 681U, 2766U, 6703U, 14559U, 1311U, 3663U, 7346U, |
| 6829 | 15675U, 1538U, 3910U, 7547U, 15962U, 735U, 2909U, 12962U, |
| 6830 | 6757U, 14681U, 13852U, 1712U, 4537U, 7721U, 16212U, 10492U, |
| 6831 | 8503U, 903U, 12541U, 3168U, 13011U, 7125U, 13422U, 14928U, |
| 6832 | 13907U, 672U, 2747U, 6694U, 14550U, 12702U, 13066U, 13469U, |
| 6833 | 14086U, 15077U, 14003U, 16610U, 1103U, 12664U, 1924U, 4357U, |
| 6834 | 13230U, 4909U, 8266U, 13759U, 8069U, 14964U, 13946U, 16561U, |
| 6835 | 1026U, 12607U, 1875U, 4282U, 13173U, 4860U, 8181U, 13702U, |
| 6836 | 8020U, 841U, 3087U, 7063U, 9882U, 14849U, 1195U, 14442U, |
| 6837 | 14405U, 1675U, 12785U, 4467U, 13273U, 7684U, 13552U, 16160U, |
| 6838 | 14187U, 974U, 12560U, 3446U, 13030U, 7196U, 13441U, 15230U, |
| 6839 | 14050U, 1390U, 3752U, 7425U, 15774U, 1684U, 4476U, 7693U, |
| 6840 | 16169U, 1480U, 3816U, 7489U, 15849U, 1978U, 5103U, 8123U, |
| 6841 | 16664U, 1249U, 14413U, 1459U, 3795U, 7468U, 15828U, 1811U, |
| 6842 | 4699U, 7844U, 16376U, 14424U, 14433U, 1609U, 4139U, 7618U, |
| 6843 | 16072U, 2099U, 5506U, 8387U, 16801U, 1989U, 12911U, 5123U, |
| 6844 | 13355U, 8134U, 13664U, 16675U, 14298U, 14228U, 15003U, 12827U, |
| 6845 | 1052U, 13301U, 4308U, 13594U, 8207U, 13314U, 4319U, 1791U, |
| 6846 | 4657U, 7800U, 16344U, 3031U, 10934U, 4669U, 11616U, 3396U, |
| 6847 | 11164U, 4193U, 11506U, 3187U, 11003U, 4735U, 11643U, 3283U, |
| 6848 | 11073U, 4504U, 11583U, 4227U, 11532U, 3246U, 11045U, 4769U, |
| 6849 | 11669U, 3322U, 11112U, 4113U, 11457U, 3409U, 11177U, 4214U, |
| 6850 | 11519U, 3216U, 11024U, 4756U, 11656U, 3309U, 11099U, 4524U, |
| 6851 | 11596U, 4241U, 11546U, 3260U, 11059U, 4783U, 11683U, 3336U, |
| 6852 | 11126U, 4126U, 11470U, 10970U, 7812U, 10982U, 7824U, 11197U, |
| 6853 | 4680U, 5114U, 11762U, 14990U, 15027U, 8984U, 13803U, 8996U, |
| 6854 | 16356U, 14197U, 2899U, 10894U, 3048U, 10943U, 2783U, 10874U, |
| 6855 | 5428U, 11847U, 2756U, 10864U, 4088U, 11448U, 2927U, 10913U, |
| 6856 | 3959U, 11208U, 3058U, 10953U, 2937U, 10923U, 3350U, 11140U, |
| 6857 | 4162U, 11483U, 4064U, 11424U, 3296U, 11086U, 4173U, 11494U, |
| 6858 | 5555U, 11870U, 4806U, 11697U, 3362U, 11152U, 4826U, 11717U, |
| 6859 | 1350U, 7385U, 1626U, 7635U, 4816U, 11707U, 2918U, 10904U, |
| 6860 | 11276U, 11350U, 11246U, 11320U, 4000U, 5278U, 11793U, 11230U, |
| 6861 | 11304U, 3985U, 5159U, 11778U, 11261U, 11335U, 4014U, 5388U, |
| 6862 | 11807U, 11289U, 11363U, 4954U, 4040U, 11747U, 5414U, 11833U, |
| 6863 | 4941U, 4028U, 11734U, 5402U, 11821U, 14284U, 15127U, 12883U, |
| 6864 | 1153U, 13341U, 4395U, 13650U, 8316U, 3603U, 14270U, 15115U, |
| 6865 | 12869U, 1141U, 13327U, 4383U, 13636U, 8304U, 990U, 3476U, |
| 6866 | 7212U, 15275U, 1582U, 3976U, 7591U, 16028U, 4609U, 16303U, |
| 6867 | 2736U, 14539U, 2511U, 8484U, 1527U, 3899U, 7536U, 15951U, |
| 6868 | 17025U, 15063U, 13988U, 16593U, 1089U, 12649U, 1907U, 4343U, |
| 6869 | 13215U, 4892U, 8252U, 13744U, 8052U, 14950U, 13931U, 16544U, |
| 6870 | 1012U, 12592U, 1858U, 4268U, 13158U, 4843U, 8167U, 13687U, |
| 6871 | 8003U, 823U, 3069U, 7045U, 14831U, 1492U, 12742U, 3828U, |
| 6872 | 13106U, 7501U, 13509U, 15861U, 14126U, 2029U, 12920U, 5445U, |
| 6873 | 13373U, 8328U, 13787U, 16733U, 14316U, 1341U, 12722U, 3714U, |
| 6874 | 13086U, 7376U, 13489U, 15736U, 14106U, 1601U, 12762U, 4105U, |
| 6875 | 13135U, 7610U, 13529U, 16064U, 14163U, 885U, 12532U, 3150U, |
| 6876 | 13002U, 7107U, 13413U, 14910U, 13898U, 2074U, 2158U, 5573U, |
| 6877 | 8436U, 16856U, 2134U, 744U, 2948U, 6766U, 14699U, 982U, |
| 6878 | 12569U, 3461U, 13047U, 7204U, 13450U, 15267U, 14067U, 15090U, |
| 6879 | 14017U, 16626U, 1116U, 12678U, 1940U, 4370U, 13244U, 4925U, |
| 6880 | 8279U, 13773U, 8085U, 14977U, 13960U, 16577U, 1039U, 12621U, |
| 6881 | 1891U, 4295U, 13187U, 4876U, 8194U, 13716U, 8036U, 1574U, |
| 6882 | 3968U, 7583U, 16020U, 966U, 3438U, 7188U, 15222U, 1412U, |
| 6883 | 14459U, 1421U, 14451U, 14467U, 1956U, 5081U, 8101U, 16642U, |
| 6884 | 863U, 3128U, 7085U, 14888U, 1844U, 4797U, 7877U, 16409U, |
| 6885 | 3704U, 9994U, 15726U, 16047U, 1967U, 5092U, 8112U, 16653U, |
| 6886 | 874U, 3139U, 7096U, 14899U, 4442U, 13258U, 16146U, 14172U, |
| 6887 | 3374U, 15191U, 1213U, 3567U, 7260U, 15579U, 1740U, 4595U, |
| 6888 | 7749U, 16289U, 660U, 2724U, 6682U, 9857U, 14527U, 946U, |
| 6889 | 3385U, 7168U, 15202U, 1449U, 3785U, 7458U, 15818U, 1731U, |
| 6890 | 4564U, 7740U, 16258U, 832U, 12516U, 3078U, 12992U, 7054U, |
| 6891 | 13397U, 14840U, 13882U, 1803U, 12795U, 4691U, 13283U, 7836U, |
| 6892 | 13562U, 16368U, 14210U, 1361U, 3723U, 7396U, 15745U, 1636U, |
| 6893 | 4206U, 7645U, 16103U, 2085U, 5492U, 8373U, 16787U, 2144U, |
| 6894 | 5541U, 8422U, 16836U, 14493U, 14482U, 1165U, 3511U, 7221U, |
| 6895 | 15523U, 957U, 3422U, 7179U, 15213U, 1997U, 5131U, 8142U, |
| 6896 | 16683U, 1204U, 12712U, 3558U, 13076U, 7251U, 13479U, 15570U, |
| 6897 | 14096U, 931U, 12551U, 3208U, 13021U, 7153U, 13432U, 15176U, |
| 6898 | 14041U, 1271U, 3623U, 7306U, 15635U, 14241U, 15014U, 12840U, |
| 6899 | 1063U, 13607U, 8218U, 1519U, 3891U, 7528U, 15943U, 1471U, |
| 6900 | 12732U, 3807U, 13096U, 7480U, 13499U, 15840U, 14116U, 1836U, |
| 6901 | 12804U, 4748U, 13292U, 7869U, 13571U, 16401U, 14219U, 1186U, |
| 6902 | 3542U, 7242U, 15554U, 6805U, 9903U, 15297U, 5187U, 6908U, |
| 6903 | 15400U, 5304U, 1370U, 3732U, 7405U, 15754U, 6856U, 9954U, |
| 6904 | 15348U, 5238U, 6955U, 15447U, 5351U, 1644U, 4407U, 7653U, |
| 6905 | 16111U, 690U, 2775U, 6712U, 14577U, 1321U, 3673U, 7356U, |
| 6906 | 15695U, 6830U, 9928U, 15322U, 5212U, 6931U, 15423U, 5327U, |
| 6907 | 1402U, 3764U, 7437U, 15786U, 6883U, 9981U, 15375U, 5265U, |
| 6908 | 6980U, 15472U, 5376U, 1695U, 4487U, 7704U, 16180U, 1547U, |
| 6909 | 3919U, 7556U, 15980U, 7891U, 6792U, 10004U, 9890U, 16432U, |
| 6910 | 15284U, 4969U, 5174U, 7949U, 6896U, 16490U, 15388U, 5027U, |
| 6911 | 5292U, 7919U, 6842U, 10032U, 9940U, 16460U, 15334U, 4997U, |
| 6912 | 5224U, 7975U, 6942U, 16516U, 15434U, 5053U, 5338U, 7905U, |
| 6913 | 6817U, 10018U, 9915U, 16446U, 15309U, 4983U, 5199U, 7962U, |
| 6914 | 6919U, 16503U, 15411U, 5040U, 5315U, 7934U, 6869U, 10047U, |
| 6915 | 9967U, 16475U, 15361U, 5012U, 5251U, 7989U, 6967U, 16530U, |
| 6916 | 15459U, 5067U, 5363U, 753U, 12506U, 2957U, 12972U, 6775U, |
| 6917 | 13387U, 14708U, 13862U, 12442U, 1591U, 4054U, 7600U, 16037U, |
| 6918 | 17099U, 12692U, 13056U, 13459U, 14076U, 15050U, 13974U, 1076U, |
| 6919 | 12635U, 4330U, 13201U, 8239U, 13730U, 14937U, 13917U, 999U, |
| 6920 | 12578U, 4255U, 13144U, 8154U, 13673U, 762U, 2966U, 6784U, |
| 6921 | 9869U, 14717U, 1429U, 14474U, |
| 6922 | }; |
| 6923 | |
| 6924 | static inline void InitLoongArchMCInstrInfo(MCInstrInfo *II) { |
| 6925 | II->InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2428); |
| 6926 | } |
| 6927 | |
| 6928 | } // end namespace llvm |
| 6929 | #endif // GET_INSTRINFO_MC_DESC |
| 6930 | |
| 6931 | #ifdef GET_INSTRINFO_HEADER |
| 6932 | #undef GET_INSTRINFO_HEADER |
| 6933 | namespace llvm { |
| 6934 | struct LoongArchGenInstrInfo : public TargetInstrInfo { |
| 6935 | explicit LoongArchGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| 6936 | ~LoongArchGenInstrInfo() override = default; |
| 6937 | |
| 6938 | }; |
| 6939 | } // end namespace llvm |
| 6940 | #endif // GET_INSTRINFO_HEADER |
| 6941 | |
| 6942 | #ifdef GET_INSTRINFO_HELPER_DECLS |
| 6943 | #undef GET_INSTRINFO_HELPER_DECLS |
| 6944 | |
| 6945 | |
| 6946 | #endif // GET_INSTRINFO_HELPER_DECLS |
| 6947 | |
| 6948 | #ifdef GET_INSTRINFO_HELPERS |
| 6949 | #undef GET_INSTRINFO_HELPERS |
| 6950 | |
| 6951 | #endif // GET_INSTRINFO_HELPERS |
| 6952 | |
| 6953 | #ifdef GET_INSTRINFO_CTOR_DTOR |
| 6954 | #undef GET_INSTRINFO_CTOR_DTOR |
| 6955 | namespace llvm { |
| 6956 | extern const LoongArchInstrTable LoongArchDescs; |
| 6957 | extern const unsigned LoongArchInstrNameIndices[]; |
| 6958 | extern const char LoongArchInstrNameData[]; |
| 6959 | LoongArchGenInstrInfo::LoongArchGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| 6960 | : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { |
| 6961 | InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2428); |
| 6962 | } |
| 6963 | } // end namespace llvm |
| 6964 | #endif // GET_INSTRINFO_CTOR_DTOR |
| 6965 | |
| 6966 | #ifdef GET_INSTRINFO_OPERAND_ENUM |
| 6967 | #undef GET_INSTRINFO_OPERAND_ENUM |
| 6968 | namespace llvm { |
| 6969 | namespace LoongArch { |
| 6970 | namespace OpName { |
| 6971 | enum { |
| 6972 | OPERAND_LAST |
| 6973 | }; |
| 6974 | } // end namespace OpName |
| 6975 | } // end namespace LoongArch |
| 6976 | } // end namespace llvm |
| 6977 | #endif //GET_INSTRINFO_OPERAND_ENUM |
| 6978 | |
| 6979 | #ifdef GET_INSTRINFO_NAMED_OPS |
| 6980 | #undef GET_INSTRINFO_NAMED_OPS |
| 6981 | namespace llvm { |
| 6982 | namespace LoongArch { |
| 6983 | LLVM_READONLY |
| 6984 | int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { |
| 6985 | return -1; |
| 6986 | } |
| 6987 | } // end namespace LoongArch |
| 6988 | } // end namespace llvm |
| 6989 | #endif //GET_INSTRINFO_NAMED_OPS |
| 6990 | |
| 6991 | #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| 6992 | #undef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| 6993 | namespace llvm { |
| 6994 | namespace LoongArch { |
| 6995 | namespace OpTypes { |
| 6996 | enum OperandType { |
| 6997 | bare_symbol = 0, |
| 6998 | f32imm = 1, |
| 6999 | f64imm = 2, |
| 7000 | grlenimm = 3, |
| 7001 | i1imm = 4, |
| 7002 | i8imm = 5, |
| 7003 | i16imm = 6, |
| 7004 | i32imm = 7, |
| 7005 | i64imm = 8, |
| 7006 | imm32 = 9, |
| 7007 | imm64 = 10, |
| 7008 | ptype0 = 11, |
| 7009 | ptype1 = 12, |
| 7010 | ptype2 = 13, |
| 7011 | ptype3 = 14, |
| 7012 | ptype4 = 15, |
| 7013 | ptype5 = 16, |
| 7014 | simm5 = 17, |
| 7015 | simm8 = 18, |
| 7016 | simm8_lsl1 = 19, |
| 7017 | simm8_lsl2 = 20, |
| 7018 | simm8_lsl3 = 21, |
| 7019 | simm9_lsl3 = 22, |
| 7020 | simm10 = 23, |
| 7021 | simm10_lsl2 = 24, |
| 7022 | simm11_lsl1 = 25, |
| 7023 | simm12 = 26, |
| 7024 | simm12_addlike = 27, |
| 7025 | simm12_lu52id = 28, |
| 7026 | simm13 = 29, |
| 7027 | simm14_lsl2 = 30, |
| 7028 | simm16 = 31, |
| 7029 | simm16_lsl2 = 32, |
| 7030 | simm16_lsl2_br = 33, |
| 7031 | simm16_lsl16 = 34, |
| 7032 | simm20 = 35, |
| 7033 | simm20_lu12iw = 36, |
| 7034 | simm20_lu32id = 37, |
| 7035 | simm20_pcaddi = 38, |
| 7036 | simm20_pcaddu18i = 39, |
| 7037 | simm20_pcalau12i = 40, |
| 7038 | simm21_lsl2 = 41, |
| 7039 | simm26_b = 42, |
| 7040 | simm26_symbol = 43, |
| 7041 | simm32_hi16_lo12 = 44, |
| 7042 | tprel_add_symbol = 45, |
| 7043 | type0 = 46, |
| 7044 | type1 = 47, |
| 7045 | type2 = 48, |
| 7046 | type3 = 49, |
| 7047 | type4 = 50, |
| 7048 | type5 = 51, |
| 7049 | uimm1 = 52, |
| 7050 | uimm2 = 53, |
| 7051 | uimm2_plus1 = 54, |
| 7052 | uimm3 = 55, |
| 7053 | uimm4 = 56, |
| 7054 | uimm5 = 57, |
| 7055 | uimm6 = 58, |
| 7056 | uimm7 = 59, |
| 7057 | uimm8 = 60, |
| 7058 | uimm12 = 61, |
| 7059 | uimm12_ori = 62, |
| 7060 | uimm14 = 63, |
| 7061 | uimm15 = 64, |
| 7062 | untyped_imm_0 = 65, |
| 7063 | GPRMemAtomic = 66, |
| 7064 | CFR = 67, |
| 7065 | FCSR = 68, |
| 7066 | FPR32 = 69, |
| 7067 | FPR64 = 70, |
| 7068 | GPR = 71, |
| 7069 | GPRT = 72, |
| 7070 | LASX256 = 73, |
| 7071 | LSX128 = 74, |
| 7072 | SCR = 75, |
| 7073 | OPERAND_TYPE_LIST_END |
| 7074 | }; |
| 7075 | } // end namespace OpTypes |
| 7076 | } // end namespace LoongArch |
| 7077 | } // end namespace llvm |
| 7078 | #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM |
| 7079 | |
| 7080 | #ifdef GET_INSTRINFO_OPERAND_TYPE |
| 7081 | #undef GET_INSTRINFO_OPERAND_TYPE |
| 7082 | namespace llvm { |
| 7083 | namespace LoongArch { |
| 7084 | LLVM_READONLY |
| 7085 | static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { |
| 7086 | static const uint16_t Offsets[] = { |
| 7087 | /* PHI */ |
| 7088 | 0, |
| 7089 | /* INLINEASM */ |
| 7090 | 1, |
| 7091 | /* INLINEASM_BR */ |
| 7092 | 1, |
| 7093 | /* CFI_INSTRUCTION */ |
| 7094 | 1, |
| 7095 | /* EH_LABEL */ |
| 7096 | 2, |
| 7097 | /* GC_LABEL */ |
| 7098 | 3, |
| 7099 | /* ANNOTATION_LABEL */ |
| 7100 | 4, |
| 7101 | /* KILL */ |
| 7102 | 5, |
| 7103 | /* EXTRACT_SUBREG */ |
| 7104 | 5, |
| 7105 | /* INSERT_SUBREG */ |
| 7106 | 8, |
| 7107 | /* IMPLICIT_DEF */ |
| 7108 | 12, |
| 7109 | /* SUBREG_TO_REG */ |
| 7110 | 13, |
| 7111 | /* COPY_TO_REGCLASS */ |
| 7112 | 17, |
| 7113 | /* DBG_VALUE */ |
| 7114 | 20, |
| 7115 | /* DBG_VALUE_LIST */ |
| 7116 | 20, |
| 7117 | /* DBG_INSTR_REF */ |
| 7118 | 20, |
| 7119 | /* DBG_PHI */ |
| 7120 | 20, |
| 7121 | /* DBG_LABEL */ |
| 7122 | 20, |
| 7123 | /* REG_SEQUENCE */ |
| 7124 | 21, |
| 7125 | /* COPY */ |
| 7126 | 23, |
| 7127 | /* BUNDLE */ |
| 7128 | 25, |
| 7129 | /* LIFETIME_START */ |
| 7130 | 25, |
| 7131 | /* LIFETIME_END */ |
| 7132 | 26, |
| 7133 | /* PSEUDO_PROBE */ |
| 7134 | 27, |
| 7135 | /* ARITH_FENCE */ |
| 7136 | 31, |
| 7137 | /* STACKMAP */ |
| 7138 | 33, |
| 7139 | /* FENTRY_CALL */ |
| 7140 | 35, |
| 7141 | /* PATCHPOINT */ |
| 7142 | 35, |
| 7143 | /* LOAD_STACK_GUARD */ |
| 7144 | 41, |
| 7145 | /* PREALLOCATED_SETUP */ |
| 7146 | 42, |
| 7147 | /* PREALLOCATED_ARG */ |
| 7148 | 43, |
| 7149 | /* STATEPOINT */ |
| 7150 | 46, |
| 7151 | /* LOCAL_ESCAPE */ |
| 7152 | 46, |
| 7153 | /* FAULTING_OP */ |
| 7154 | 48, |
| 7155 | /* PATCHABLE_OP */ |
| 7156 | 49, |
| 7157 | /* PATCHABLE_FUNCTION_ENTER */ |
| 7158 | 49, |
| 7159 | /* PATCHABLE_RET */ |
| 7160 | 49, |
| 7161 | /* PATCHABLE_FUNCTION_EXIT */ |
| 7162 | 49, |
| 7163 | /* PATCHABLE_TAIL_CALL */ |
| 7164 | 49, |
| 7165 | /* PATCHABLE_EVENT_CALL */ |
| 7166 | 49, |
| 7167 | /* PATCHABLE_TYPED_EVENT_CALL */ |
| 7168 | 51, |
| 7169 | /* ICALL_BRANCH_FUNNEL */ |
| 7170 | 54, |
| 7171 | /* MEMBARRIER */ |
| 7172 | 54, |
| 7173 | /* JUMP_TABLE_DEBUG_INFO */ |
| 7174 | 54, |
| 7175 | /* CONVERGENCECTRL_ENTRY */ |
| 7176 | 55, |
| 7177 | /* CONVERGENCECTRL_ANCHOR */ |
| 7178 | 56, |
| 7179 | /* CONVERGENCECTRL_LOOP */ |
| 7180 | 57, |
| 7181 | /* CONVERGENCECTRL_GLUE */ |
| 7182 | 59, |
| 7183 | /* G_ASSERT_SEXT */ |
| 7184 | 60, |
| 7185 | /* G_ASSERT_ZEXT */ |
| 7186 | 63, |
| 7187 | /* G_ASSERT_ALIGN */ |
| 7188 | 66, |
| 7189 | /* G_ADD */ |
| 7190 | 69, |
| 7191 | /* G_SUB */ |
| 7192 | 72, |
| 7193 | /* G_MUL */ |
| 7194 | 75, |
| 7195 | /* G_SDIV */ |
| 7196 | 78, |
| 7197 | /* G_UDIV */ |
| 7198 | 81, |
| 7199 | /* G_SREM */ |
| 7200 | 84, |
| 7201 | /* G_UREM */ |
| 7202 | 87, |
| 7203 | /* G_SDIVREM */ |
| 7204 | 90, |
| 7205 | /* G_UDIVREM */ |
| 7206 | 94, |
| 7207 | /* G_AND */ |
| 7208 | 98, |
| 7209 | /* G_OR */ |
| 7210 | 101, |
| 7211 | /* G_XOR */ |
| 7212 | 104, |
| 7213 | /* G_IMPLICIT_DEF */ |
| 7214 | 107, |
| 7215 | /* G_PHI */ |
| 7216 | 108, |
| 7217 | /* G_FRAME_INDEX */ |
| 7218 | 109, |
| 7219 | /* G_GLOBAL_VALUE */ |
| 7220 | 111, |
| 7221 | /* G_PTRAUTH_GLOBAL_VALUE */ |
| 7222 | 113, |
| 7223 | /* G_CONSTANT_POOL */ |
| 7224 | 118, |
| 7225 | /* G_EXTRACT */ |
| 7226 | 120, |
| 7227 | /* G_UNMERGE_VALUES */ |
| 7228 | 123, |
| 7229 | /* G_INSERT */ |
| 7230 | 125, |
| 7231 | /* G_MERGE_VALUES */ |
| 7232 | 129, |
| 7233 | /* G_BUILD_VECTOR */ |
| 7234 | 131, |
| 7235 | /* G_BUILD_VECTOR_TRUNC */ |
| 7236 | 133, |
| 7237 | /* G_CONCAT_VECTORS */ |
| 7238 | 135, |
| 7239 | /* G_PTRTOINT */ |
| 7240 | 137, |
| 7241 | /* G_INTTOPTR */ |
| 7242 | 139, |
| 7243 | /* G_BITCAST */ |
| 7244 | 141, |
| 7245 | /* G_FREEZE */ |
| 7246 | 143, |
| 7247 | /* G_CONSTANT_FOLD_BARRIER */ |
| 7248 | 145, |
| 7249 | /* G_INTRINSIC_FPTRUNC_ROUND */ |
| 7250 | 147, |
| 7251 | /* G_INTRINSIC_TRUNC */ |
| 7252 | 150, |
| 7253 | /* G_INTRINSIC_ROUND */ |
| 7254 | 152, |
| 7255 | /* G_INTRINSIC_LRINT */ |
| 7256 | 154, |
| 7257 | /* G_INTRINSIC_LLRINT */ |
| 7258 | 156, |
| 7259 | /* G_INTRINSIC_ROUNDEVEN */ |
| 7260 | 158, |
| 7261 | /* G_READCYCLECOUNTER */ |
| 7262 | 160, |
| 7263 | /* G_READSTEADYCOUNTER */ |
| 7264 | 161, |
| 7265 | /* G_LOAD */ |
| 7266 | 162, |
| 7267 | /* G_SEXTLOAD */ |
| 7268 | 164, |
| 7269 | /* G_ZEXTLOAD */ |
| 7270 | 166, |
| 7271 | /* G_INDEXED_LOAD */ |
| 7272 | 168, |
| 7273 | /* G_INDEXED_SEXTLOAD */ |
| 7274 | 173, |
| 7275 | /* G_INDEXED_ZEXTLOAD */ |
| 7276 | 178, |
| 7277 | /* G_STORE */ |
| 7278 | 183, |
| 7279 | /* G_INDEXED_STORE */ |
| 7280 | 185, |
| 7281 | /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
| 7282 | 190, |
| 7283 | /* G_ATOMIC_CMPXCHG */ |
| 7284 | 195, |
| 7285 | /* G_ATOMICRMW_XCHG */ |
| 7286 | 199, |
| 7287 | /* G_ATOMICRMW_ADD */ |
| 7288 | 202, |
| 7289 | /* G_ATOMICRMW_SUB */ |
| 7290 | 205, |
| 7291 | /* G_ATOMICRMW_AND */ |
| 7292 | 208, |
| 7293 | /* G_ATOMICRMW_NAND */ |
| 7294 | 211, |
| 7295 | /* G_ATOMICRMW_OR */ |
| 7296 | 214, |
| 7297 | /* G_ATOMICRMW_XOR */ |
| 7298 | 217, |
| 7299 | /* G_ATOMICRMW_MAX */ |
| 7300 | 220, |
| 7301 | /* G_ATOMICRMW_MIN */ |
| 7302 | 223, |
| 7303 | /* G_ATOMICRMW_UMAX */ |
| 7304 | 226, |
| 7305 | /* G_ATOMICRMW_UMIN */ |
| 7306 | 229, |
| 7307 | /* G_ATOMICRMW_FADD */ |
| 7308 | 232, |
| 7309 | /* G_ATOMICRMW_FSUB */ |
| 7310 | 235, |
| 7311 | /* G_ATOMICRMW_FMAX */ |
| 7312 | 238, |
| 7313 | /* G_ATOMICRMW_FMIN */ |
| 7314 | 241, |
| 7315 | /* G_ATOMICRMW_UINC_WRAP */ |
| 7316 | 244, |
| 7317 | /* G_ATOMICRMW_UDEC_WRAP */ |
| 7318 | 247, |
| 7319 | /* G_FENCE */ |
| 7320 | 250, |
| 7321 | /* G_PREFETCH */ |
| 7322 | 252, |
| 7323 | /* G_BRCOND */ |
| 7324 | 256, |
| 7325 | /* G_BRINDIRECT */ |
| 7326 | 258, |
| 7327 | /* G_INVOKE_REGION_START */ |
| 7328 | 259, |
| 7329 | /* G_INTRINSIC */ |
| 7330 | 259, |
| 7331 | /* G_INTRINSIC_W_SIDE_EFFECTS */ |
| 7332 | 260, |
| 7333 | /* G_INTRINSIC_CONVERGENT */ |
| 7334 | 261, |
| 7335 | /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ |
| 7336 | 262, |
| 7337 | /* G_ANYEXT */ |
| 7338 | 263, |
| 7339 | /* G_TRUNC */ |
| 7340 | 265, |
| 7341 | /* G_CONSTANT */ |
| 7342 | 267, |
| 7343 | /* G_FCONSTANT */ |
| 7344 | 269, |
| 7345 | /* G_VASTART */ |
| 7346 | 271, |
| 7347 | /* G_VAARG */ |
| 7348 | 272, |
| 7349 | /* G_SEXT */ |
| 7350 | 275, |
| 7351 | /* G_SEXT_INREG */ |
| 7352 | 277, |
| 7353 | /* G_ZEXT */ |
| 7354 | 280, |
| 7355 | /* G_SHL */ |
| 7356 | 282, |
| 7357 | /* G_LSHR */ |
| 7358 | 285, |
| 7359 | /* G_ASHR */ |
| 7360 | 288, |
| 7361 | /* G_FSHL */ |
| 7362 | 291, |
| 7363 | /* G_FSHR */ |
| 7364 | 295, |
| 7365 | /* G_ROTR */ |
| 7366 | 299, |
| 7367 | /* G_ROTL */ |
| 7368 | 302, |
| 7369 | /* G_ICMP */ |
| 7370 | 305, |
| 7371 | /* G_FCMP */ |
| 7372 | 309, |
| 7373 | /* G_SCMP */ |
| 7374 | 313, |
| 7375 | /* G_UCMP */ |
| 7376 | 316, |
| 7377 | /* G_SELECT */ |
| 7378 | 319, |
| 7379 | /* G_UADDO */ |
| 7380 | 323, |
| 7381 | /* G_UADDE */ |
| 7382 | 327, |
| 7383 | /* G_USUBO */ |
| 7384 | 332, |
| 7385 | /* G_USUBE */ |
| 7386 | 336, |
| 7387 | /* G_SADDO */ |
| 7388 | 341, |
| 7389 | /* G_SADDE */ |
| 7390 | 345, |
| 7391 | /* G_SSUBO */ |
| 7392 | 350, |
| 7393 | /* G_SSUBE */ |
| 7394 | 354, |
| 7395 | /* G_UMULO */ |
| 7396 | 359, |
| 7397 | /* G_SMULO */ |
| 7398 | 363, |
| 7399 | /* G_UMULH */ |
| 7400 | 367, |
| 7401 | /* G_SMULH */ |
| 7402 | 370, |
| 7403 | /* G_UADDSAT */ |
| 7404 | 373, |
| 7405 | /* G_SADDSAT */ |
| 7406 | 376, |
| 7407 | /* G_USUBSAT */ |
| 7408 | 379, |
| 7409 | /* G_SSUBSAT */ |
| 7410 | 382, |
| 7411 | /* G_USHLSAT */ |
| 7412 | 385, |
| 7413 | /* G_SSHLSAT */ |
| 7414 | 388, |
| 7415 | /* G_SMULFIX */ |
| 7416 | 391, |
| 7417 | /* G_UMULFIX */ |
| 7418 | 395, |
| 7419 | /* G_SMULFIXSAT */ |
| 7420 | 399, |
| 7421 | /* G_UMULFIXSAT */ |
| 7422 | 403, |
| 7423 | /* G_SDIVFIX */ |
| 7424 | 407, |
| 7425 | /* G_UDIVFIX */ |
| 7426 | 411, |
| 7427 | /* G_SDIVFIXSAT */ |
| 7428 | 415, |
| 7429 | /* G_UDIVFIXSAT */ |
| 7430 | 419, |
| 7431 | /* G_FADD */ |
| 7432 | 423, |
| 7433 | /* G_FSUB */ |
| 7434 | 426, |
| 7435 | /* G_FMUL */ |
| 7436 | 429, |
| 7437 | /* G_FMA */ |
| 7438 | 432, |
| 7439 | /* G_FMAD */ |
| 7440 | 436, |
| 7441 | /* G_FDIV */ |
| 7442 | 440, |
| 7443 | /* G_FREM */ |
| 7444 | 443, |
| 7445 | /* G_FPOW */ |
| 7446 | 446, |
| 7447 | /* G_FPOWI */ |
| 7448 | 449, |
| 7449 | /* G_FEXP */ |
| 7450 | 452, |
| 7451 | /* G_FEXP2 */ |
| 7452 | 454, |
| 7453 | /* G_FEXP10 */ |
| 7454 | 456, |
| 7455 | /* G_FLOG */ |
| 7456 | 458, |
| 7457 | /* G_FLOG2 */ |
| 7458 | 460, |
| 7459 | /* G_FLOG10 */ |
| 7460 | 462, |
| 7461 | /* G_FLDEXP */ |
| 7462 | 464, |
| 7463 | /* G_FFREXP */ |
| 7464 | 467, |
| 7465 | /* G_FNEG */ |
| 7466 | 470, |
| 7467 | /* G_FPEXT */ |
| 7468 | 472, |
| 7469 | /* G_FPTRUNC */ |
| 7470 | 474, |
| 7471 | /* G_FPTOSI */ |
| 7472 | 476, |
| 7473 | /* G_FPTOUI */ |
| 7474 | 478, |
| 7475 | /* G_SITOFP */ |
| 7476 | 480, |
| 7477 | /* G_UITOFP */ |
| 7478 | 482, |
| 7479 | /* G_FABS */ |
| 7480 | 484, |
| 7481 | /* G_FCOPYSIGN */ |
| 7482 | 486, |
| 7483 | /* G_IS_FPCLASS */ |
| 7484 | 489, |
| 7485 | /* G_FCANONICALIZE */ |
| 7486 | 492, |
| 7487 | /* G_FMINNUM */ |
| 7488 | 494, |
| 7489 | /* G_FMAXNUM */ |
| 7490 | 497, |
| 7491 | /* G_FMINNUM_IEEE */ |
| 7492 | 500, |
| 7493 | /* G_FMAXNUM_IEEE */ |
| 7494 | 503, |
| 7495 | /* G_FMINIMUM */ |
| 7496 | 506, |
| 7497 | /* G_FMAXIMUM */ |
| 7498 | 509, |
| 7499 | /* G_GET_FPENV */ |
| 7500 | 512, |
| 7501 | /* G_SET_FPENV */ |
| 7502 | 513, |
| 7503 | /* G_RESET_FPENV */ |
| 7504 | 514, |
| 7505 | /* G_GET_FPMODE */ |
| 7506 | 514, |
| 7507 | /* G_SET_FPMODE */ |
| 7508 | 515, |
| 7509 | /* G_RESET_FPMODE */ |
| 7510 | 516, |
| 7511 | /* G_PTR_ADD */ |
| 7512 | 516, |
| 7513 | /* G_PTRMASK */ |
| 7514 | 519, |
| 7515 | /* G_SMIN */ |
| 7516 | 522, |
| 7517 | /* G_SMAX */ |
| 7518 | 525, |
| 7519 | /* G_UMIN */ |
| 7520 | 528, |
| 7521 | /* G_UMAX */ |
| 7522 | 531, |
| 7523 | /* G_ABS */ |
| 7524 | 534, |
| 7525 | /* G_LROUND */ |
| 7526 | 536, |
| 7527 | /* G_LLROUND */ |
| 7528 | 538, |
| 7529 | /* G_BR */ |
| 7530 | 540, |
| 7531 | /* G_BRJT */ |
| 7532 | 541, |
| 7533 | /* G_VSCALE */ |
| 7534 | 544, |
| 7535 | /* G_INSERT_SUBVECTOR */ |
| 7536 | 546, |
| 7537 | /* G_EXTRACT_SUBVECTOR */ |
| 7538 | 550, |
| 7539 | /* G_INSERT_VECTOR_ELT */ |
| 7540 | 553, |
| 7541 | /* G_EXTRACT_VECTOR_ELT */ |
| 7542 | 557, |
| 7543 | /* G_SHUFFLE_VECTOR */ |
| 7544 | 560, |
| 7545 | /* G_SPLAT_VECTOR */ |
| 7546 | 564, |
| 7547 | /* G_VECTOR_COMPRESS */ |
| 7548 | 566, |
| 7549 | /* G_CTTZ */ |
| 7550 | 570, |
| 7551 | /* G_CTTZ_ZERO_UNDEF */ |
| 7552 | 572, |
| 7553 | /* G_CTLZ */ |
| 7554 | 574, |
| 7555 | /* G_CTLZ_ZERO_UNDEF */ |
| 7556 | 576, |
| 7557 | /* G_CTPOP */ |
| 7558 | 578, |
| 7559 | /* G_BSWAP */ |
| 7560 | 580, |
| 7561 | /* G_BITREVERSE */ |
| 7562 | 582, |
| 7563 | /* G_FCEIL */ |
| 7564 | 584, |
| 7565 | /* G_FCOS */ |
| 7566 | 586, |
| 7567 | /* G_FSIN */ |
| 7568 | 588, |
| 7569 | /* G_FTAN */ |
| 7570 | 590, |
| 7571 | /* G_FACOS */ |
| 7572 | 592, |
| 7573 | /* G_FASIN */ |
| 7574 | 594, |
| 7575 | /* G_FATAN */ |
| 7576 | 596, |
| 7577 | /* G_FCOSH */ |
| 7578 | 598, |
| 7579 | /* G_FSINH */ |
| 7580 | 600, |
| 7581 | /* G_FTANH */ |
| 7582 | 602, |
| 7583 | /* G_FSQRT */ |
| 7584 | 604, |
| 7585 | /* G_FFLOOR */ |
| 7586 | 606, |
| 7587 | /* G_FRINT */ |
| 7588 | 608, |
| 7589 | /* G_FNEARBYINT */ |
| 7590 | 610, |
| 7591 | /* G_ADDRSPACE_CAST */ |
| 7592 | 612, |
| 7593 | /* G_BLOCK_ADDR */ |
| 7594 | 614, |
| 7595 | /* G_JUMP_TABLE */ |
| 7596 | 616, |
| 7597 | /* G_DYN_STACKALLOC */ |
| 7598 | 618, |
| 7599 | /* G_STACKSAVE */ |
| 7600 | 621, |
| 7601 | /* G_STACKRESTORE */ |
| 7602 | 622, |
| 7603 | /* G_STRICT_FADD */ |
| 7604 | 623, |
| 7605 | /* G_STRICT_FSUB */ |
| 7606 | 626, |
| 7607 | /* G_STRICT_FMUL */ |
| 7608 | 629, |
| 7609 | /* G_STRICT_FDIV */ |
| 7610 | 632, |
| 7611 | /* G_STRICT_FREM */ |
| 7612 | 635, |
| 7613 | /* G_STRICT_FMA */ |
| 7614 | 638, |
| 7615 | /* G_STRICT_FSQRT */ |
| 7616 | 642, |
| 7617 | /* G_STRICT_FLDEXP */ |
| 7618 | 644, |
| 7619 | /* G_READ_REGISTER */ |
| 7620 | 647, |
| 7621 | /* G_WRITE_REGISTER */ |
| 7622 | 649, |
| 7623 | /* G_MEMCPY */ |
| 7624 | 651, |
| 7625 | /* G_MEMCPY_INLINE */ |
| 7626 | 655, |
| 7627 | /* G_MEMMOVE */ |
| 7628 | 658, |
| 7629 | /* G_MEMSET */ |
| 7630 | 662, |
| 7631 | /* G_BZERO */ |
| 7632 | 666, |
| 7633 | /* G_TRAP */ |
| 7634 | 669, |
| 7635 | /* G_DEBUGTRAP */ |
| 7636 | 669, |
| 7637 | /* G_UBSANTRAP */ |
| 7638 | 669, |
| 7639 | /* G_VECREDUCE_SEQ_FADD */ |
| 7640 | 670, |
| 7641 | /* G_VECREDUCE_SEQ_FMUL */ |
| 7642 | 673, |
| 7643 | /* G_VECREDUCE_FADD */ |
| 7644 | 676, |
| 7645 | /* G_VECREDUCE_FMUL */ |
| 7646 | 678, |
| 7647 | /* G_VECREDUCE_FMAX */ |
| 7648 | 680, |
| 7649 | /* G_VECREDUCE_FMIN */ |
| 7650 | 682, |
| 7651 | /* G_VECREDUCE_FMAXIMUM */ |
| 7652 | 684, |
| 7653 | /* G_VECREDUCE_FMINIMUM */ |
| 7654 | 686, |
| 7655 | /* G_VECREDUCE_ADD */ |
| 7656 | 688, |
| 7657 | /* G_VECREDUCE_MUL */ |
| 7658 | 690, |
| 7659 | /* G_VECREDUCE_AND */ |
| 7660 | 692, |
| 7661 | /* G_VECREDUCE_OR */ |
| 7662 | 694, |
| 7663 | /* G_VECREDUCE_XOR */ |
| 7664 | 696, |
| 7665 | /* G_VECREDUCE_SMAX */ |
| 7666 | 698, |
| 7667 | /* G_VECREDUCE_SMIN */ |
| 7668 | 700, |
| 7669 | /* G_VECREDUCE_UMAX */ |
| 7670 | 702, |
| 7671 | /* G_VECREDUCE_UMIN */ |
| 7672 | 704, |
| 7673 | /* G_SBFX */ |
| 7674 | 706, |
| 7675 | /* G_UBFX */ |
| 7676 | 710, |
| 7677 | /* ADJCALLSTACKDOWN */ |
| 7678 | 714, |
| 7679 | /* ADJCALLSTACKUP */ |
| 7680 | 716, |
| 7681 | /* PseudoAddTPRel_D */ |
| 7682 | 718, |
| 7683 | /* PseudoAddTPRel_W */ |
| 7684 | 722, |
| 7685 | /* PseudoAtomicLoadAdd32 */ |
| 7686 | 726, |
| 7687 | /* PseudoAtomicLoadAnd32 */ |
| 7688 | 731, |
| 7689 | /* PseudoAtomicLoadNand32 */ |
| 7690 | 736, |
| 7691 | /* PseudoAtomicLoadNand64 */ |
| 7692 | 741, |
| 7693 | /* PseudoAtomicLoadOr32 */ |
| 7694 | 746, |
| 7695 | /* PseudoAtomicLoadSub32 */ |
| 7696 | 751, |
| 7697 | /* PseudoAtomicLoadXor32 */ |
| 7698 | 756, |
| 7699 | /* PseudoAtomicStoreD */ |
| 7700 | 761, |
| 7701 | /* PseudoAtomicStoreW */ |
| 7702 | 764, |
| 7703 | /* PseudoAtomicSwap32 */ |
| 7704 | 767, |
| 7705 | /* PseudoBR */ |
| 7706 | 772, |
| 7707 | /* PseudoBRIND */ |
| 7708 | 773, |
| 7709 | /* PseudoB_TAIL */ |
| 7710 | 775, |
| 7711 | /* PseudoCALL */ |
| 7712 | 776, |
| 7713 | /* PseudoCALL36 */ |
| 7714 | 777, |
| 7715 | /* PseudoCALLIndirect */ |
| 7716 | 778, |
| 7717 | /* PseudoCALL_LARGE */ |
| 7718 | 779, |
| 7719 | /* PseudoCALL_MEDIUM */ |
| 7720 | 780, |
| 7721 | /* PseudoCmpXchg32 */ |
| 7722 | 781, |
| 7723 | /* PseudoCmpXchg64 */ |
| 7724 | 787, |
| 7725 | /* PseudoCopyCFR */ |
| 7726 | 793, |
| 7727 | /* PseudoDESC_CALL */ |
| 7728 | 795, |
| 7729 | /* PseudoJIRL_CALL */ |
| 7730 | 798, |
| 7731 | /* PseudoJIRL_TAIL */ |
| 7732 | 800, |
| 7733 | /* PseudoLA_ABS */ |
| 7734 | 802, |
| 7735 | /* PseudoLA_ABS_LARGE */ |
| 7736 | 804, |
| 7737 | /* PseudoLA_GOT */ |
| 7738 | 807, |
| 7739 | /* PseudoLA_GOT_LARGE */ |
| 7740 | 809, |
| 7741 | /* PseudoLA_PCREL */ |
| 7742 | 812, |
| 7743 | /* PseudoLA_PCREL_LARGE */ |
| 7744 | 814, |
| 7745 | /* PseudoLA_TLS_DESC_ABS */ |
| 7746 | 817, |
| 7747 | /* PseudoLA_TLS_DESC_ABS_LARGE */ |
| 7748 | 819, |
| 7749 | /* PseudoLA_TLS_DESC_PC */ |
| 7750 | 822, |
| 7751 | /* PseudoLA_TLS_DESC_PC_LARGE */ |
| 7752 | 824, |
| 7753 | /* PseudoLA_TLS_GD */ |
| 7754 | 827, |
| 7755 | /* PseudoLA_TLS_GD_LARGE */ |
| 7756 | 829, |
| 7757 | /* PseudoLA_TLS_IE */ |
| 7758 | 832, |
| 7759 | /* PseudoLA_TLS_IE_LARGE */ |
| 7760 | 834, |
| 7761 | /* PseudoLA_TLS_LD */ |
| 7762 | 837, |
| 7763 | /* PseudoLA_TLS_LD_LARGE */ |
| 7764 | 839, |
| 7765 | /* PseudoLA_TLS_LE */ |
| 7766 | 842, |
| 7767 | /* PseudoLD_CFR */ |
| 7768 | 844, |
| 7769 | /* PseudoLI_D */ |
| 7770 | 847, |
| 7771 | /* PseudoLI_W */ |
| 7772 | 849, |
| 7773 | /* PseudoMaskedAtomicLoadAdd32 */ |
| 7774 | 851, |
| 7775 | /* PseudoMaskedAtomicLoadMax32 */ |
| 7776 | 857, |
| 7777 | /* PseudoMaskedAtomicLoadMin32 */ |
| 7778 | 865, |
| 7779 | /* PseudoMaskedAtomicLoadNand32 */ |
| 7780 | 873, |
| 7781 | /* PseudoMaskedAtomicLoadSub32 */ |
| 7782 | 879, |
| 7783 | /* PseudoMaskedAtomicLoadUMax32 */ |
| 7784 | 885, |
| 7785 | /* PseudoMaskedAtomicLoadUMin32 */ |
| 7786 | 892, |
| 7787 | /* PseudoMaskedAtomicSwap32 */ |
| 7788 | 899, |
| 7789 | /* PseudoMaskedCmpXchg32 */ |
| 7790 | 905, |
| 7791 | /* PseudoRET */ |
| 7792 | 912, |
| 7793 | /* PseudoST_CFR */ |
| 7794 | 912, |
| 7795 | /* PseudoTAIL */ |
| 7796 | 915, |
| 7797 | /* PseudoTAIL36 */ |
| 7798 | 916, |
| 7799 | /* PseudoTAILIndirect */ |
| 7800 | 918, |
| 7801 | /* PseudoTAIL_LARGE */ |
| 7802 | 919, |
| 7803 | /* PseudoTAIL_MEDIUM */ |
| 7804 | 920, |
| 7805 | /* PseudoUNIMP */ |
| 7806 | 921, |
| 7807 | /* PseudoVBNZ */ |
| 7808 | 921, |
| 7809 | /* PseudoVBNZ_B */ |
| 7810 | 923, |
| 7811 | /* PseudoVBNZ_D */ |
| 7812 | 925, |
| 7813 | /* PseudoVBNZ_H */ |
| 7814 | 927, |
| 7815 | /* PseudoVBNZ_W */ |
| 7816 | 929, |
| 7817 | /* PseudoVBZ */ |
| 7818 | 931, |
| 7819 | /* PseudoVBZ_B */ |
| 7820 | 933, |
| 7821 | /* PseudoVBZ_D */ |
| 7822 | 935, |
| 7823 | /* PseudoVBZ_H */ |
| 7824 | 937, |
| 7825 | /* PseudoVBZ_W */ |
| 7826 | 939, |
| 7827 | /* PseudoVREPLI_B */ |
| 7828 | 941, |
| 7829 | /* PseudoVREPLI_D */ |
| 7830 | 943, |
| 7831 | /* PseudoVREPLI_H */ |
| 7832 | 945, |
| 7833 | /* PseudoVREPLI_W */ |
| 7834 | 947, |
| 7835 | /* PseudoXVBNZ */ |
| 7836 | 949, |
| 7837 | /* PseudoXVBNZ_B */ |
| 7838 | 951, |
| 7839 | /* PseudoXVBNZ_D */ |
| 7840 | 953, |
| 7841 | /* PseudoXVBNZ_H */ |
| 7842 | 955, |
| 7843 | /* PseudoXVBNZ_W */ |
| 7844 | 957, |
| 7845 | /* PseudoXVBZ */ |
| 7846 | 959, |
| 7847 | /* PseudoXVBZ_B */ |
| 7848 | 961, |
| 7849 | /* PseudoXVBZ_D */ |
| 7850 | 963, |
| 7851 | /* PseudoXVBZ_H */ |
| 7852 | 965, |
| 7853 | /* PseudoXVBZ_W */ |
| 7854 | 967, |
| 7855 | /* PseudoXVINSGR2VR_B */ |
| 7856 | 969, |
| 7857 | /* PseudoXVINSGR2VR_H */ |
| 7858 | 973, |
| 7859 | /* PseudoXVREPLI_B */ |
| 7860 | 977, |
| 7861 | /* PseudoXVREPLI_D */ |
| 7862 | 979, |
| 7863 | /* PseudoXVREPLI_H */ |
| 7864 | 981, |
| 7865 | /* PseudoXVREPLI_W */ |
| 7866 | 983, |
| 7867 | /* RDFCSR */ |
| 7868 | 985, |
| 7869 | /* WRFCSR */ |
| 7870 | 987, |
| 7871 | /* ADC_B */ |
| 7872 | 989, |
| 7873 | /* ADC_D */ |
| 7874 | 992, |
| 7875 | /* ADC_H */ |
| 7876 | 995, |
| 7877 | /* ADC_W */ |
| 7878 | 998, |
| 7879 | /* ADDI_D */ |
| 7880 | 1001, |
| 7881 | /* ADDI_W */ |
| 7882 | 1004, |
| 7883 | /* ADDU12I_D */ |
| 7884 | 1007, |
| 7885 | /* ADDU12I_W */ |
| 7886 | 1010, |
| 7887 | /* ADDU16I_D */ |
| 7888 | 1013, |
| 7889 | /* ADD_D */ |
| 7890 | 1016, |
| 7891 | /* ADD_W */ |
| 7892 | 1019, |
| 7893 | /* ALSL_D */ |
| 7894 | 1022, |
| 7895 | /* ALSL_W */ |
| 7896 | 1026, |
| 7897 | /* ALSL_WU */ |
| 7898 | 1030, |
| 7899 | /* AMADD_B */ |
| 7900 | 1034, |
| 7901 | /* AMADD_D */ |
| 7902 | 1037, |
| 7903 | /* AMADD_H */ |
| 7904 | 1040, |
| 7905 | /* AMADD_W */ |
| 7906 | 1043, |
| 7907 | /* AMADD__DB_B */ |
| 7908 | 1046, |
| 7909 | /* AMADD__DB_D */ |
| 7910 | 1049, |
| 7911 | /* AMADD__DB_H */ |
| 7912 | 1052, |
| 7913 | /* AMADD__DB_W */ |
| 7914 | 1055, |
| 7915 | /* AMAND_D */ |
| 7916 | 1058, |
| 7917 | /* AMAND_W */ |
| 7918 | 1061, |
| 7919 | /* AMAND__DB_D */ |
| 7920 | 1064, |
| 7921 | /* AMAND__DB_W */ |
| 7922 | 1067, |
| 7923 | /* AMCAS_B */ |
| 7924 | 1070, |
| 7925 | /* AMCAS_D */ |
| 7926 | 1073, |
| 7927 | /* AMCAS_H */ |
| 7928 | 1076, |
| 7929 | /* AMCAS_W */ |
| 7930 | 1079, |
| 7931 | /* AMCAS__DB_B */ |
| 7932 | 1082, |
| 7933 | /* AMCAS__DB_D */ |
| 7934 | 1085, |
| 7935 | /* AMCAS__DB_H */ |
| 7936 | 1088, |
| 7937 | /* AMCAS__DB_W */ |
| 7938 | 1091, |
| 7939 | /* AMMAX_D */ |
| 7940 | 1094, |
| 7941 | /* AMMAX_DU */ |
| 7942 | 1097, |
| 7943 | /* AMMAX_W */ |
| 7944 | 1100, |
| 7945 | /* AMMAX_WU */ |
| 7946 | 1103, |
| 7947 | /* AMMAX__DB_D */ |
| 7948 | 1106, |
| 7949 | /* AMMAX__DB_DU */ |
| 7950 | 1109, |
| 7951 | /* AMMAX__DB_W */ |
| 7952 | 1112, |
| 7953 | /* AMMAX__DB_WU */ |
| 7954 | 1115, |
| 7955 | /* AMMIN_D */ |
| 7956 | 1118, |
| 7957 | /* AMMIN_DU */ |
| 7958 | 1121, |
| 7959 | /* AMMIN_W */ |
| 7960 | 1124, |
| 7961 | /* AMMIN_WU */ |
| 7962 | 1127, |
| 7963 | /* AMMIN__DB_D */ |
| 7964 | 1130, |
| 7965 | /* AMMIN__DB_DU */ |
| 7966 | 1133, |
| 7967 | /* AMMIN__DB_W */ |
| 7968 | 1136, |
| 7969 | /* AMMIN__DB_WU */ |
| 7970 | 1139, |
| 7971 | /* AMOR_D */ |
| 7972 | 1142, |
| 7973 | /* AMOR_W */ |
| 7974 | 1145, |
| 7975 | /* AMOR__DB_D */ |
| 7976 | 1148, |
| 7977 | /* AMOR__DB_W */ |
| 7978 | 1151, |
| 7979 | /* AMSWAP_B */ |
| 7980 | 1154, |
| 7981 | /* AMSWAP_D */ |
| 7982 | 1157, |
| 7983 | /* AMSWAP_H */ |
| 7984 | 1160, |
| 7985 | /* AMSWAP_W */ |
| 7986 | 1163, |
| 7987 | /* AMSWAP__DB_B */ |
| 7988 | 1166, |
| 7989 | /* AMSWAP__DB_D */ |
| 7990 | 1169, |
| 7991 | /* AMSWAP__DB_H */ |
| 7992 | 1172, |
| 7993 | /* AMSWAP__DB_W */ |
| 7994 | 1175, |
| 7995 | /* AMXOR_D */ |
| 7996 | 1178, |
| 7997 | /* AMXOR_W */ |
| 7998 | 1181, |
| 7999 | /* AMXOR__DB_D */ |
| 8000 | 1184, |
| 8001 | /* AMXOR__DB_W */ |
| 8002 | 1187, |
| 8003 | /* AND */ |
| 8004 | 1190, |
| 8005 | /* ANDI */ |
| 8006 | 1193, |
| 8007 | /* ANDN */ |
| 8008 | 1196, |
| 8009 | /* ARMADC_W */ |
| 8010 | 1199, |
| 8011 | /* ARMADD_W */ |
| 8012 | 1202, |
| 8013 | /* ARMAND_W */ |
| 8014 | 1205, |
| 8015 | /* ARMMFFLAG */ |
| 8016 | 1208, |
| 8017 | /* ARMMOVE */ |
| 8018 | 1210, |
| 8019 | /* ARMMOV_D */ |
| 8020 | 1213, |
| 8021 | /* ARMMOV_W */ |
| 8022 | 1215, |
| 8023 | /* ARMMTFLAG */ |
| 8024 | 1217, |
| 8025 | /* ARMNOT_W */ |
| 8026 | 1219, |
| 8027 | /* ARMOR_W */ |
| 8028 | 1221, |
| 8029 | /* ARMROTRI_W */ |
| 8030 | 1224, |
| 8031 | /* ARMROTR_W */ |
| 8032 | 1227, |
| 8033 | /* ARMRRX_W */ |
| 8034 | 1230, |
| 8035 | /* ARMSBC_W */ |
| 8036 | 1232, |
| 8037 | /* ARMSLLI_W */ |
| 8038 | 1235, |
| 8039 | /* ARMSLL_W */ |
| 8040 | 1238, |
| 8041 | /* ARMSRAI_W */ |
| 8042 | 1241, |
| 8043 | /* ARMSRA_W */ |
| 8044 | 1244, |
| 8045 | /* ARMSRLI_W */ |
| 8046 | 1247, |
| 8047 | /* ARMSRL_W */ |
| 8048 | 1250, |
| 8049 | /* ARMSUB_W */ |
| 8050 | 1253, |
| 8051 | /* ARMXOR_W */ |
| 8052 | 1256, |
| 8053 | /* ASRTGT_D */ |
| 8054 | 1259, |
| 8055 | /* ASRTLE_D */ |
| 8056 | 1261, |
| 8057 | /* B */ |
| 8058 | 1263, |
| 8059 | /* BCEQZ */ |
| 8060 | 1264, |
| 8061 | /* BCNEZ */ |
| 8062 | 1266, |
| 8063 | /* BEQ */ |
| 8064 | 1268, |
| 8065 | /* BEQZ */ |
| 8066 | 1271, |
| 8067 | /* BGE */ |
| 8068 | 1273, |
| 8069 | /* BGEU */ |
| 8070 | 1276, |
| 8071 | /* BITREV_4B */ |
| 8072 | 1279, |
| 8073 | /* BITREV_8B */ |
| 8074 | 1281, |
| 8075 | /* BITREV_D */ |
| 8076 | 1283, |
| 8077 | /* BITREV_W */ |
| 8078 | 1285, |
| 8079 | /* BL */ |
| 8080 | 1287, |
| 8081 | /* BLT */ |
| 8082 | 1288, |
| 8083 | /* BLTU */ |
| 8084 | 1291, |
| 8085 | /* BNE */ |
| 8086 | 1294, |
| 8087 | /* BNEZ */ |
| 8088 | 1297, |
| 8089 | /* BREAK */ |
| 8090 | 1299, |
| 8091 | /* BSTRINS_D */ |
| 8092 | 1300, |
| 8093 | /* BSTRINS_W */ |
| 8094 | 1305, |
| 8095 | /* BSTRPICK_D */ |
| 8096 | 1310, |
| 8097 | /* BSTRPICK_W */ |
| 8098 | 1314, |
| 8099 | /* BYTEPICK_D */ |
| 8100 | 1318, |
| 8101 | /* BYTEPICK_W */ |
| 8102 | 1322, |
| 8103 | /* CACOP */ |
| 8104 | 1326, |
| 8105 | /* CLO_D */ |
| 8106 | 1329, |
| 8107 | /* CLO_W */ |
| 8108 | 1331, |
| 8109 | /* CLZ_D */ |
| 8110 | 1333, |
| 8111 | /* CLZ_W */ |
| 8112 | 1335, |
| 8113 | /* CPUCFG */ |
| 8114 | 1337, |
| 8115 | /* CRCC_W_B_W */ |
| 8116 | 1339, |
| 8117 | /* CRCC_W_D_W */ |
| 8118 | 1342, |
| 8119 | /* CRCC_W_H_W */ |
| 8120 | 1345, |
| 8121 | /* CRCC_W_W_W */ |
| 8122 | 1348, |
| 8123 | /* CRC_W_B_W */ |
| 8124 | 1351, |
| 8125 | /* CRC_W_D_W */ |
| 8126 | 1354, |
| 8127 | /* CRC_W_H_W */ |
| 8128 | 1357, |
| 8129 | /* CRC_W_W_W */ |
| 8130 | 1360, |
| 8131 | /* CSRRD */ |
| 8132 | 1363, |
| 8133 | /* CSRWR */ |
| 8134 | 1365, |
| 8135 | /* CSRXCHG */ |
| 8136 | 1368, |
| 8137 | /* CTO_D */ |
| 8138 | 1372, |
| 8139 | /* CTO_W */ |
| 8140 | 1374, |
| 8141 | /* CTZ_D */ |
| 8142 | 1376, |
| 8143 | /* CTZ_W */ |
| 8144 | 1378, |
| 8145 | /* DBAR */ |
| 8146 | 1380, |
| 8147 | /* DBCL */ |
| 8148 | 1381, |
| 8149 | /* DIV_D */ |
| 8150 | 1382, |
| 8151 | /* DIV_DU */ |
| 8152 | 1385, |
| 8153 | /* DIV_W */ |
| 8154 | 1388, |
| 8155 | /* DIV_WU */ |
| 8156 | 1391, |
| 8157 | /* ERTN */ |
| 8158 | 1394, |
| 8159 | /* EXT_W_B */ |
| 8160 | 1394, |
| 8161 | /* EXT_W_H */ |
| 8162 | 1396, |
| 8163 | /* FABS_D */ |
| 8164 | 1398, |
| 8165 | /* FABS_S */ |
| 8166 | 1400, |
| 8167 | /* FADD_D */ |
| 8168 | 1402, |
| 8169 | /* FADD_S */ |
| 8170 | 1405, |
| 8171 | /* FCLASS_D */ |
| 8172 | 1408, |
| 8173 | /* FCLASS_S */ |
| 8174 | 1410, |
| 8175 | /* FCMP_CAF_D */ |
| 8176 | 1412, |
| 8177 | /* FCMP_CAF_S */ |
| 8178 | 1415, |
| 8179 | /* FCMP_CEQ_D */ |
| 8180 | 1418, |
| 8181 | /* FCMP_CEQ_S */ |
| 8182 | 1421, |
| 8183 | /* FCMP_CLE_D */ |
| 8184 | 1424, |
| 8185 | /* FCMP_CLE_S */ |
| 8186 | 1427, |
| 8187 | /* FCMP_CLT_D */ |
| 8188 | 1430, |
| 8189 | /* FCMP_CLT_S */ |
| 8190 | 1433, |
| 8191 | /* FCMP_CNE_D */ |
| 8192 | 1436, |
| 8193 | /* FCMP_CNE_S */ |
| 8194 | 1439, |
| 8195 | /* FCMP_COR_D */ |
| 8196 | 1442, |
| 8197 | /* FCMP_COR_S */ |
| 8198 | 1445, |
| 8199 | /* FCMP_CUEQ_D */ |
| 8200 | 1448, |
| 8201 | /* FCMP_CUEQ_S */ |
| 8202 | 1451, |
| 8203 | /* FCMP_CULE_D */ |
| 8204 | 1454, |
| 8205 | /* FCMP_CULE_S */ |
| 8206 | 1457, |
| 8207 | /* FCMP_CULT_D */ |
| 8208 | 1460, |
| 8209 | /* FCMP_CULT_S */ |
| 8210 | 1463, |
| 8211 | /* FCMP_CUNE_D */ |
| 8212 | 1466, |
| 8213 | /* FCMP_CUNE_S */ |
| 8214 | 1469, |
| 8215 | /* FCMP_CUN_D */ |
| 8216 | 1472, |
| 8217 | /* FCMP_CUN_S */ |
| 8218 | 1475, |
| 8219 | /* FCMP_SAF_D */ |
| 8220 | 1478, |
| 8221 | /* FCMP_SAF_S */ |
| 8222 | 1481, |
| 8223 | /* FCMP_SEQ_D */ |
| 8224 | 1484, |
| 8225 | /* FCMP_SEQ_S */ |
| 8226 | 1487, |
| 8227 | /* FCMP_SLE_D */ |
| 8228 | 1490, |
| 8229 | /* FCMP_SLE_S */ |
| 8230 | 1493, |
| 8231 | /* FCMP_SLT_D */ |
| 8232 | 1496, |
| 8233 | /* FCMP_SLT_S */ |
| 8234 | 1499, |
| 8235 | /* FCMP_SNE_D */ |
| 8236 | 1502, |
| 8237 | /* FCMP_SNE_S */ |
| 8238 | 1505, |
| 8239 | /* FCMP_SOR_D */ |
| 8240 | 1508, |
| 8241 | /* FCMP_SOR_S */ |
| 8242 | 1511, |
| 8243 | /* FCMP_SUEQ_D */ |
| 8244 | 1514, |
| 8245 | /* FCMP_SUEQ_S */ |
| 8246 | 1517, |
| 8247 | /* FCMP_SULE_D */ |
| 8248 | 1520, |
| 8249 | /* FCMP_SULE_S */ |
| 8250 | 1523, |
| 8251 | /* FCMP_SULT_D */ |
| 8252 | 1526, |
| 8253 | /* FCMP_SULT_S */ |
| 8254 | 1529, |
| 8255 | /* FCMP_SUNE_D */ |
| 8256 | 1532, |
| 8257 | /* FCMP_SUNE_S */ |
| 8258 | 1535, |
| 8259 | /* FCMP_SUN_D */ |
| 8260 | 1538, |
| 8261 | /* FCMP_SUN_S */ |
| 8262 | 1541, |
| 8263 | /* FCOPYSIGN_D */ |
| 8264 | 1544, |
| 8265 | /* FCOPYSIGN_S */ |
| 8266 | 1547, |
| 8267 | /* FCVT_D_LD */ |
| 8268 | 1550, |
| 8269 | /* FCVT_D_S */ |
| 8270 | 1553, |
| 8271 | /* FCVT_LD_D */ |
| 8272 | 1555, |
| 8273 | /* FCVT_S_D */ |
| 8274 | 1557, |
| 8275 | /* FCVT_UD_D */ |
| 8276 | 1559, |
| 8277 | /* FDIV_D */ |
| 8278 | 1561, |
| 8279 | /* FDIV_S */ |
| 8280 | 1564, |
| 8281 | /* FFINT_D_L */ |
| 8282 | 1567, |
| 8283 | /* FFINT_D_W */ |
| 8284 | 1569, |
| 8285 | /* FFINT_S_L */ |
| 8286 | 1571, |
| 8287 | /* FFINT_S_W */ |
| 8288 | 1573, |
| 8289 | /* FLDGT_D */ |
| 8290 | 1575, |
| 8291 | /* FLDGT_S */ |
| 8292 | 1578, |
| 8293 | /* FLDLE_D */ |
| 8294 | 1581, |
| 8295 | /* FLDLE_S */ |
| 8296 | 1584, |
| 8297 | /* FLDX_D */ |
| 8298 | 1587, |
| 8299 | /* FLDX_S */ |
| 8300 | 1590, |
| 8301 | /* FLD_D */ |
| 8302 | 1593, |
| 8303 | /* FLD_S */ |
| 8304 | 1596, |
| 8305 | /* FLOGB_D */ |
| 8306 | 1599, |
| 8307 | /* FLOGB_S */ |
| 8308 | 1601, |
| 8309 | /* FMADD_D */ |
| 8310 | 1603, |
| 8311 | /* FMADD_S */ |
| 8312 | 1607, |
| 8313 | /* FMAXA_D */ |
| 8314 | 1611, |
| 8315 | /* FMAXA_S */ |
| 8316 | 1614, |
| 8317 | /* FMAX_D */ |
| 8318 | 1617, |
| 8319 | /* FMAX_S */ |
| 8320 | 1620, |
| 8321 | /* FMINA_D */ |
| 8322 | 1623, |
| 8323 | /* FMINA_S */ |
| 8324 | 1626, |
| 8325 | /* FMIN_D */ |
| 8326 | 1629, |
| 8327 | /* FMIN_S */ |
| 8328 | 1632, |
| 8329 | /* FMOV_D */ |
| 8330 | 1635, |
| 8331 | /* FMOV_S */ |
| 8332 | 1637, |
| 8333 | /* FMSUB_D */ |
| 8334 | 1639, |
| 8335 | /* FMSUB_S */ |
| 8336 | 1643, |
| 8337 | /* FMUL_D */ |
| 8338 | 1647, |
| 8339 | /* FMUL_S */ |
| 8340 | 1650, |
| 8341 | /* FNEG_D */ |
| 8342 | 1653, |
| 8343 | /* FNEG_S */ |
| 8344 | 1655, |
| 8345 | /* FNMADD_D */ |
| 8346 | 1657, |
| 8347 | /* FNMADD_S */ |
| 8348 | 1661, |
| 8349 | /* FNMSUB_D */ |
| 8350 | 1665, |
| 8351 | /* FNMSUB_S */ |
| 8352 | 1669, |
| 8353 | /* FRECIPE_D */ |
| 8354 | 1673, |
| 8355 | /* FRECIPE_S */ |
| 8356 | 1675, |
| 8357 | /* FRECIP_D */ |
| 8358 | 1677, |
| 8359 | /* FRECIP_S */ |
| 8360 | 1679, |
| 8361 | /* FRINT_D */ |
| 8362 | 1681, |
| 8363 | /* FRINT_S */ |
| 8364 | 1683, |
| 8365 | /* FRSQRTE_D */ |
| 8366 | 1685, |
| 8367 | /* FRSQRTE_S */ |
| 8368 | 1687, |
| 8369 | /* FRSQRT_D */ |
| 8370 | 1689, |
| 8371 | /* FRSQRT_S */ |
| 8372 | 1691, |
| 8373 | /* FSCALEB_D */ |
| 8374 | 1693, |
| 8375 | /* FSCALEB_S */ |
| 8376 | 1696, |
| 8377 | /* FSEL_xD */ |
| 8378 | 1699, |
| 8379 | /* FSEL_xS */ |
| 8380 | 1703, |
| 8381 | /* FSQRT_D */ |
| 8382 | 1707, |
| 8383 | /* FSQRT_S */ |
| 8384 | 1709, |
| 8385 | /* FSTGT_D */ |
| 8386 | 1711, |
| 8387 | /* FSTGT_S */ |
| 8388 | 1714, |
| 8389 | /* FSTLE_D */ |
| 8390 | 1717, |
| 8391 | /* FSTLE_S */ |
| 8392 | 1720, |
| 8393 | /* FSTX_D */ |
| 8394 | 1723, |
| 8395 | /* FSTX_S */ |
| 8396 | 1726, |
| 8397 | /* FST_D */ |
| 8398 | 1729, |
| 8399 | /* FST_S */ |
| 8400 | 1732, |
| 8401 | /* FSUB_D */ |
| 8402 | 1735, |
| 8403 | /* FSUB_S */ |
| 8404 | 1738, |
| 8405 | /* FTINTRM_L_D */ |
| 8406 | 1741, |
| 8407 | /* FTINTRM_L_S */ |
| 8408 | 1743, |
| 8409 | /* FTINTRM_W_D */ |
| 8410 | 1745, |
| 8411 | /* FTINTRM_W_S */ |
| 8412 | 1747, |
| 8413 | /* FTINTRNE_L_D */ |
| 8414 | 1749, |
| 8415 | /* FTINTRNE_L_S */ |
| 8416 | 1751, |
| 8417 | /* FTINTRNE_W_D */ |
| 8418 | 1753, |
| 8419 | /* FTINTRNE_W_S */ |
| 8420 | 1755, |
| 8421 | /* FTINTRP_L_D */ |
| 8422 | 1757, |
| 8423 | /* FTINTRP_L_S */ |
| 8424 | 1759, |
| 8425 | /* FTINTRP_W_D */ |
| 8426 | 1761, |
| 8427 | /* FTINTRP_W_S */ |
| 8428 | 1763, |
| 8429 | /* FTINTRZ_L_D */ |
| 8430 | 1765, |
| 8431 | /* FTINTRZ_L_S */ |
| 8432 | 1767, |
| 8433 | /* FTINTRZ_W_D */ |
| 8434 | 1769, |
| 8435 | /* FTINTRZ_W_S */ |
| 8436 | 1771, |
| 8437 | /* FTINT_L_D */ |
| 8438 | 1773, |
| 8439 | /* FTINT_L_S */ |
| 8440 | 1775, |
| 8441 | /* FTINT_W_D */ |
| 8442 | 1777, |
| 8443 | /* FTINT_W_S */ |
| 8444 | 1779, |
| 8445 | /* GCSRRD */ |
| 8446 | 1781, |
| 8447 | /* GCSRWR */ |
| 8448 | 1783, |
| 8449 | /* GCSRXCHG */ |
| 8450 | 1786, |
| 8451 | /* GTLBFLUSH */ |
| 8452 | 1790, |
| 8453 | /* HVCL */ |
| 8454 | 1790, |
| 8455 | /* IBAR */ |
| 8456 | 1791, |
| 8457 | /* IDLE */ |
| 8458 | 1792, |
| 8459 | /* INVTLB */ |
| 8460 | 1793, |
| 8461 | /* IOCSRRD_B */ |
| 8462 | 1796, |
| 8463 | /* IOCSRRD_D */ |
| 8464 | 1798, |
| 8465 | /* IOCSRRD_H */ |
| 8466 | 1800, |
| 8467 | /* IOCSRRD_W */ |
| 8468 | 1802, |
| 8469 | /* IOCSRWR_B */ |
| 8470 | 1804, |
| 8471 | /* IOCSRWR_D */ |
| 8472 | 1806, |
| 8473 | /* IOCSRWR_H */ |
| 8474 | 1808, |
| 8475 | /* IOCSRWR_W */ |
| 8476 | 1810, |
| 8477 | /* JIRL */ |
| 8478 | 1812, |
| 8479 | /* JISCR0 */ |
| 8480 | 1815, |
| 8481 | /* JISCR1 */ |
| 8482 | 1816, |
| 8483 | /* LDDIR */ |
| 8484 | 1817, |
| 8485 | /* LDGT_B */ |
| 8486 | 1820, |
| 8487 | /* LDGT_D */ |
| 8488 | 1823, |
| 8489 | /* LDGT_H */ |
| 8490 | 1826, |
| 8491 | /* LDGT_W */ |
| 8492 | 1829, |
| 8493 | /* LDLE_B */ |
| 8494 | 1832, |
| 8495 | /* LDLE_D */ |
| 8496 | 1835, |
| 8497 | /* LDLE_H */ |
| 8498 | 1838, |
| 8499 | /* LDLE_W */ |
| 8500 | 1841, |
| 8501 | /* LDL_D */ |
| 8502 | 1844, |
| 8503 | /* LDL_W */ |
| 8504 | 1847, |
| 8505 | /* LDPTE */ |
| 8506 | 1850, |
| 8507 | /* LDPTR_D */ |
| 8508 | 1852, |
| 8509 | /* LDPTR_W */ |
| 8510 | 1855, |
| 8511 | /* LDR_D */ |
| 8512 | 1858, |
| 8513 | /* LDR_W */ |
| 8514 | 1861, |
| 8515 | /* LDX_B */ |
| 8516 | 1864, |
| 8517 | /* LDX_BU */ |
| 8518 | 1867, |
| 8519 | /* LDX_D */ |
| 8520 | 1870, |
| 8521 | /* LDX_H */ |
| 8522 | 1873, |
| 8523 | /* LDX_HU */ |
| 8524 | 1876, |
| 8525 | /* LDX_W */ |
| 8526 | 1879, |
| 8527 | /* LDX_WU */ |
| 8528 | 1882, |
| 8529 | /* LD_B */ |
| 8530 | 1885, |
| 8531 | /* LD_BU */ |
| 8532 | 1888, |
| 8533 | /* LD_D */ |
| 8534 | 1891, |
| 8535 | /* LD_H */ |
| 8536 | 1894, |
| 8537 | /* LD_HU */ |
| 8538 | 1897, |
| 8539 | /* LD_W */ |
| 8540 | 1900, |
| 8541 | /* LD_WU */ |
| 8542 | 1903, |
| 8543 | /* LLACQ_D */ |
| 8544 | 1906, |
| 8545 | /* LLACQ_W */ |
| 8546 | 1908, |
| 8547 | /* LL_D */ |
| 8548 | 1910, |
| 8549 | /* LL_W */ |
| 8550 | 1913, |
| 8551 | /* LU12I_W */ |
| 8552 | 1916, |
| 8553 | /* LU32I_D */ |
| 8554 | 1918, |
| 8555 | /* LU52I_D */ |
| 8556 | 1921, |
| 8557 | /* MASKEQZ */ |
| 8558 | 1924, |
| 8559 | /* MASKNEZ */ |
| 8560 | 1927, |
| 8561 | /* MOD_D */ |
| 8562 | 1930, |
| 8563 | /* MOD_DU */ |
| 8564 | 1933, |
| 8565 | /* MOD_W */ |
| 8566 | 1936, |
| 8567 | /* MOD_WU */ |
| 8568 | 1939, |
| 8569 | /* MOVCF2FR_xS */ |
| 8570 | 1942, |
| 8571 | /* MOVCF2GR */ |
| 8572 | 1944, |
| 8573 | /* MOVFCSR2GR */ |
| 8574 | 1946, |
| 8575 | /* MOVFR2CF_xS */ |
| 8576 | 1948, |
| 8577 | /* MOVFR2GR_D */ |
| 8578 | 1950, |
| 8579 | /* MOVFR2GR_S */ |
| 8580 | 1952, |
| 8581 | /* MOVFR2GR_S_64 */ |
| 8582 | 1954, |
| 8583 | /* MOVFRH2GR_S */ |
| 8584 | 1956, |
| 8585 | /* MOVGR2CF */ |
| 8586 | 1958, |
| 8587 | /* MOVGR2FCSR */ |
| 8588 | 1960, |
| 8589 | /* MOVGR2FRH_W */ |
| 8590 | 1962, |
| 8591 | /* MOVGR2FR_D */ |
| 8592 | 1965, |
| 8593 | /* MOVGR2FR_W */ |
| 8594 | 1967, |
| 8595 | /* MOVGR2FR_W_64 */ |
| 8596 | 1969, |
| 8597 | /* MOVGR2SCR */ |
| 8598 | 1971, |
| 8599 | /* MOVSCR2GR */ |
| 8600 | 1973, |
| 8601 | /* MULH_D */ |
| 8602 | 1975, |
| 8603 | /* MULH_DU */ |
| 8604 | 1978, |
| 8605 | /* MULH_W */ |
| 8606 | 1981, |
| 8607 | /* MULH_WU */ |
| 8608 | 1984, |
| 8609 | /* MULW_D_W */ |
| 8610 | 1987, |
| 8611 | /* MULW_D_WU */ |
| 8612 | 1990, |
| 8613 | /* MUL_D */ |
| 8614 | 1993, |
| 8615 | /* MUL_W */ |
| 8616 | 1996, |
| 8617 | /* NOR */ |
| 8618 | 1999, |
| 8619 | /* OR */ |
| 8620 | 2002, |
| 8621 | /* ORI */ |
| 8622 | 2005, |
| 8623 | /* ORN */ |
| 8624 | 2008, |
| 8625 | /* PCADDI */ |
| 8626 | 2011, |
| 8627 | /* PCADDU12I */ |
| 8628 | 2013, |
| 8629 | /* PCADDU18I */ |
| 8630 | 2015, |
| 8631 | /* PCALAU12I */ |
| 8632 | 2017, |
| 8633 | /* PRELD */ |
| 8634 | 2019, |
| 8635 | /* PRELDX */ |
| 8636 | 2022, |
| 8637 | /* RCRI_B */ |
| 8638 | 2025, |
| 8639 | /* RCRI_D */ |
| 8640 | 2028, |
| 8641 | /* RCRI_H */ |
| 8642 | 2031, |
| 8643 | /* RCRI_W */ |
| 8644 | 2034, |
| 8645 | /* RCR_B */ |
| 8646 | 2037, |
| 8647 | /* RCR_D */ |
| 8648 | 2040, |
| 8649 | /* RCR_H */ |
| 8650 | 2043, |
| 8651 | /* RCR_W */ |
| 8652 | 2046, |
| 8653 | /* RDTIMEH_W */ |
| 8654 | 2049, |
| 8655 | /* RDTIMEL_W */ |
| 8656 | 2051, |
| 8657 | /* RDTIME_D */ |
| 8658 | 2053, |
| 8659 | /* REVB_2H */ |
| 8660 | 2055, |
| 8661 | /* REVB_2W */ |
| 8662 | 2057, |
| 8663 | /* REVB_4H */ |
| 8664 | 2059, |
| 8665 | /* REVB_D */ |
| 8666 | 2061, |
| 8667 | /* REVH_2W */ |
| 8668 | 2063, |
| 8669 | /* REVH_D */ |
| 8670 | 2065, |
| 8671 | /* ROTRI_B */ |
| 8672 | 2067, |
| 8673 | /* ROTRI_D */ |
| 8674 | 2070, |
| 8675 | /* ROTRI_H */ |
| 8676 | 2073, |
| 8677 | /* ROTRI_W */ |
| 8678 | 2076, |
| 8679 | /* ROTR_B */ |
| 8680 | 2079, |
| 8681 | /* ROTR_D */ |
| 8682 | 2082, |
| 8683 | /* ROTR_H */ |
| 8684 | 2085, |
| 8685 | /* ROTR_W */ |
| 8686 | 2088, |
| 8687 | /* SBC_B */ |
| 8688 | 2091, |
| 8689 | /* SBC_D */ |
| 8690 | 2094, |
| 8691 | /* SBC_H */ |
| 8692 | 2097, |
| 8693 | /* SBC_W */ |
| 8694 | 2100, |
| 8695 | /* SCREL_D */ |
| 8696 | 2103, |
| 8697 | /* SCREL_W */ |
| 8698 | 2106, |
| 8699 | /* SC_D */ |
| 8700 | 2109, |
| 8701 | /* SC_Q */ |
| 8702 | 2113, |
| 8703 | /* SC_W */ |
| 8704 | 2117, |
| 8705 | /* SETARMJ */ |
| 8706 | 2121, |
| 8707 | /* SETX86J */ |
| 8708 | 2123, |
| 8709 | /* SETX86LOOPE */ |
| 8710 | 2125, |
| 8711 | /* SETX86LOOPNE */ |
| 8712 | 2127, |
| 8713 | /* SET_CFR_FALSE */ |
| 8714 | 2129, |
| 8715 | /* SET_CFR_TRUE */ |
| 8716 | 2130, |
| 8717 | /* SLLI_D */ |
| 8718 | 2131, |
| 8719 | /* SLLI_W */ |
| 8720 | 2134, |
| 8721 | /* SLL_D */ |
| 8722 | 2137, |
| 8723 | /* SLL_W */ |
| 8724 | 2140, |
| 8725 | /* SLT */ |
| 8726 | 2143, |
| 8727 | /* SLTI */ |
| 8728 | 2146, |
| 8729 | /* SLTU */ |
| 8730 | 2149, |
| 8731 | /* SLTUI */ |
| 8732 | 2152, |
| 8733 | /* SRAI_D */ |
| 8734 | 2155, |
| 8735 | /* SRAI_W */ |
| 8736 | 2158, |
| 8737 | /* SRA_D */ |
| 8738 | 2161, |
| 8739 | /* SRA_W */ |
| 8740 | 2164, |
| 8741 | /* SRLI_D */ |
| 8742 | 2167, |
| 8743 | /* SRLI_W */ |
| 8744 | 2170, |
| 8745 | /* SRL_D */ |
| 8746 | 2173, |
| 8747 | /* SRL_W */ |
| 8748 | 2176, |
| 8749 | /* STGT_B */ |
| 8750 | 2179, |
| 8751 | /* STGT_D */ |
| 8752 | 2182, |
| 8753 | /* STGT_H */ |
| 8754 | 2185, |
| 8755 | /* STGT_W */ |
| 8756 | 2188, |
| 8757 | /* STLE_B */ |
| 8758 | 2191, |
| 8759 | /* STLE_D */ |
| 8760 | 2194, |
| 8761 | /* STLE_H */ |
| 8762 | 2197, |
| 8763 | /* STLE_W */ |
| 8764 | 2200, |
| 8765 | /* STL_D */ |
| 8766 | 2203, |
| 8767 | /* STL_W */ |
| 8768 | 2206, |
| 8769 | /* STPTR_D */ |
| 8770 | 2209, |
| 8771 | /* STPTR_W */ |
| 8772 | 2212, |
| 8773 | /* STR_D */ |
| 8774 | 2215, |
| 8775 | /* STR_W */ |
| 8776 | 2218, |
| 8777 | /* STX_B */ |
| 8778 | 2221, |
| 8779 | /* STX_D */ |
| 8780 | 2224, |
| 8781 | /* STX_H */ |
| 8782 | 2227, |
| 8783 | /* STX_W */ |
| 8784 | 2230, |
| 8785 | /* ST_B */ |
| 8786 | 2233, |
| 8787 | /* ST_D */ |
| 8788 | 2236, |
| 8789 | /* ST_H */ |
| 8790 | 2239, |
| 8791 | /* ST_W */ |
| 8792 | 2242, |
| 8793 | /* SUB_D */ |
| 8794 | 2245, |
| 8795 | /* SUB_W */ |
| 8796 | 2248, |
| 8797 | /* SYSCALL */ |
| 8798 | 2251, |
| 8799 | /* TLBCLR */ |
| 8800 | 2252, |
| 8801 | /* TLBFILL */ |
| 8802 | 2252, |
| 8803 | /* TLBFLUSH */ |
| 8804 | 2252, |
| 8805 | /* TLBRD */ |
| 8806 | 2252, |
| 8807 | /* TLBSRCH */ |
| 8808 | 2252, |
| 8809 | /* TLBWR */ |
| 8810 | 2252, |
| 8811 | /* VABSD_B */ |
| 8812 | 2252, |
| 8813 | /* VABSD_BU */ |
| 8814 | 2255, |
| 8815 | /* VABSD_D */ |
| 8816 | 2258, |
| 8817 | /* VABSD_DU */ |
| 8818 | 2261, |
| 8819 | /* VABSD_H */ |
| 8820 | 2264, |
| 8821 | /* VABSD_HU */ |
| 8822 | 2267, |
| 8823 | /* VABSD_W */ |
| 8824 | 2270, |
| 8825 | /* VABSD_WU */ |
| 8826 | 2273, |
| 8827 | /* VADDA_B */ |
| 8828 | 2276, |
| 8829 | /* VADDA_D */ |
| 8830 | 2279, |
| 8831 | /* VADDA_H */ |
| 8832 | 2282, |
| 8833 | /* VADDA_W */ |
| 8834 | 2285, |
| 8835 | /* VADDI_BU */ |
| 8836 | 2288, |
| 8837 | /* VADDI_DU */ |
| 8838 | 2291, |
| 8839 | /* VADDI_HU */ |
| 8840 | 2294, |
| 8841 | /* VADDI_WU */ |
| 8842 | 2297, |
| 8843 | /* VADDWEV_D_W */ |
| 8844 | 2300, |
| 8845 | /* VADDWEV_D_WU */ |
| 8846 | 2303, |
| 8847 | /* VADDWEV_D_WU_W */ |
| 8848 | 2306, |
| 8849 | /* VADDWEV_H_B */ |
| 8850 | 2309, |
| 8851 | /* VADDWEV_H_BU */ |
| 8852 | 2312, |
| 8853 | /* VADDWEV_H_BU_B */ |
| 8854 | 2315, |
| 8855 | /* VADDWEV_Q_D */ |
| 8856 | 2318, |
| 8857 | /* VADDWEV_Q_DU */ |
| 8858 | 2321, |
| 8859 | /* VADDWEV_Q_DU_D */ |
| 8860 | 2324, |
| 8861 | /* VADDWEV_W_H */ |
| 8862 | 2327, |
| 8863 | /* VADDWEV_W_HU */ |
| 8864 | 2330, |
| 8865 | /* VADDWEV_W_HU_H */ |
| 8866 | 2333, |
| 8867 | /* VADDWOD_D_W */ |
| 8868 | 2336, |
| 8869 | /* VADDWOD_D_WU */ |
| 8870 | 2339, |
| 8871 | /* VADDWOD_D_WU_W */ |
| 8872 | 2342, |
| 8873 | /* VADDWOD_H_B */ |
| 8874 | 2345, |
| 8875 | /* VADDWOD_H_BU */ |
| 8876 | 2348, |
| 8877 | /* VADDWOD_H_BU_B */ |
| 8878 | 2351, |
| 8879 | /* VADDWOD_Q_D */ |
| 8880 | 2354, |
| 8881 | /* VADDWOD_Q_DU */ |
| 8882 | 2357, |
| 8883 | /* VADDWOD_Q_DU_D */ |
| 8884 | 2360, |
| 8885 | /* VADDWOD_W_H */ |
| 8886 | 2363, |
| 8887 | /* VADDWOD_W_HU */ |
| 8888 | 2366, |
| 8889 | /* VADDWOD_W_HU_H */ |
| 8890 | 2369, |
| 8891 | /* VADD_B */ |
| 8892 | 2372, |
| 8893 | /* VADD_D */ |
| 8894 | 2375, |
| 8895 | /* VADD_H */ |
| 8896 | 2378, |
| 8897 | /* VADD_Q */ |
| 8898 | 2381, |
| 8899 | /* VADD_W */ |
| 8900 | 2384, |
| 8901 | /* VANDI_B */ |
| 8902 | 2387, |
| 8903 | /* VANDN_V */ |
| 8904 | 2390, |
| 8905 | /* VAND_V */ |
| 8906 | 2393, |
| 8907 | /* VAVGR_B */ |
| 8908 | 2396, |
| 8909 | /* VAVGR_BU */ |
| 8910 | 2399, |
| 8911 | /* VAVGR_D */ |
| 8912 | 2402, |
| 8913 | /* VAVGR_DU */ |
| 8914 | 2405, |
| 8915 | /* VAVGR_H */ |
| 8916 | 2408, |
| 8917 | /* VAVGR_HU */ |
| 8918 | 2411, |
| 8919 | /* VAVGR_W */ |
| 8920 | 2414, |
| 8921 | /* VAVGR_WU */ |
| 8922 | 2417, |
| 8923 | /* VAVG_B */ |
| 8924 | 2420, |
| 8925 | /* VAVG_BU */ |
| 8926 | 2423, |
| 8927 | /* VAVG_D */ |
| 8928 | 2426, |
| 8929 | /* VAVG_DU */ |
| 8930 | 2429, |
| 8931 | /* VAVG_H */ |
| 8932 | 2432, |
| 8933 | /* VAVG_HU */ |
| 8934 | 2435, |
| 8935 | /* VAVG_W */ |
| 8936 | 2438, |
| 8937 | /* VAVG_WU */ |
| 8938 | 2441, |
| 8939 | /* VBITCLRI_B */ |
| 8940 | 2444, |
| 8941 | /* VBITCLRI_D */ |
| 8942 | 2447, |
| 8943 | /* VBITCLRI_H */ |
| 8944 | 2450, |
| 8945 | /* VBITCLRI_W */ |
| 8946 | 2453, |
| 8947 | /* VBITCLR_B */ |
| 8948 | 2456, |
| 8949 | /* VBITCLR_D */ |
| 8950 | 2459, |
| 8951 | /* VBITCLR_H */ |
| 8952 | 2462, |
| 8953 | /* VBITCLR_W */ |
| 8954 | 2465, |
| 8955 | /* VBITREVI_B */ |
| 8956 | 2468, |
| 8957 | /* VBITREVI_D */ |
| 8958 | 2471, |
| 8959 | /* VBITREVI_H */ |
| 8960 | 2474, |
| 8961 | /* VBITREVI_W */ |
| 8962 | 2477, |
| 8963 | /* VBITREV_B */ |
| 8964 | 2480, |
| 8965 | /* VBITREV_D */ |
| 8966 | 2483, |
| 8967 | /* VBITREV_H */ |
| 8968 | 2486, |
| 8969 | /* VBITREV_W */ |
| 8970 | 2489, |
| 8971 | /* VBITSELI_B */ |
| 8972 | 2492, |
| 8973 | /* VBITSEL_V */ |
| 8974 | 2496, |
| 8975 | /* VBITSETI_B */ |
| 8976 | 2500, |
| 8977 | /* VBITSETI_D */ |
| 8978 | 2503, |
| 8979 | /* VBITSETI_H */ |
| 8980 | 2506, |
| 8981 | /* VBITSETI_W */ |
| 8982 | 2509, |
| 8983 | /* VBITSET_B */ |
| 8984 | 2512, |
| 8985 | /* VBITSET_D */ |
| 8986 | 2515, |
| 8987 | /* VBITSET_H */ |
| 8988 | 2518, |
| 8989 | /* VBITSET_W */ |
| 8990 | 2521, |
| 8991 | /* VBSLL_V */ |
| 8992 | 2524, |
| 8993 | /* VBSRL_V */ |
| 8994 | 2527, |
| 8995 | /* VCLO_B */ |
| 8996 | 2530, |
| 8997 | /* VCLO_D */ |
| 8998 | 2532, |
| 8999 | /* VCLO_H */ |
| 9000 | 2534, |
| 9001 | /* VCLO_W */ |
| 9002 | 2536, |
| 9003 | /* VCLZ_B */ |
| 9004 | 2538, |
| 9005 | /* VCLZ_D */ |
| 9006 | 2540, |
| 9007 | /* VCLZ_H */ |
| 9008 | 2542, |
| 9009 | /* VCLZ_W */ |
| 9010 | 2544, |
| 9011 | /* VDIV_B */ |
| 9012 | 2546, |
| 9013 | /* VDIV_BU */ |
| 9014 | 2549, |
| 9015 | /* VDIV_D */ |
| 9016 | 2552, |
| 9017 | /* VDIV_DU */ |
| 9018 | 2555, |
| 9019 | /* VDIV_H */ |
| 9020 | 2558, |
| 9021 | /* VDIV_HU */ |
| 9022 | 2561, |
| 9023 | /* VDIV_W */ |
| 9024 | 2564, |
| 9025 | /* VDIV_WU */ |
| 9026 | 2567, |
| 9027 | /* VEXT2XV_DU_BU */ |
| 9028 | 2570, |
| 9029 | /* VEXT2XV_DU_HU */ |
| 9030 | 2572, |
| 9031 | /* VEXT2XV_DU_WU */ |
| 9032 | 2574, |
| 9033 | /* VEXT2XV_D_B */ |
| 9034 | 2576, |
| 9035 | /* VEXT2XV_D_H */ |
| 9036 | 2578, |
| 9037 | /* VEXT2XV_D_W */ |
| 9038 | 2580, |
| 9039 | /* VEXT2XV_HU_BU */ |
| 9040 | 2582, |
| 9041 | /* VEXT2XV_H_B */ |
| 9042 | 2584, |
| 9043 | /* VEXT2XV_WU_BU */ |
| 9044 | 2586, |
| 9045 | /* VEXT2XV_WU_HU */ |
| 9046 | 2588, |
| 9047 | /* VEXT2XV_W_B */ |
| 9048 | 2590, |
| 9049 | /* VEXT2XV_W_H */ |
| 9050 | 2592, |
| 9051 | /* VEXTH_DU_WU */ |
| 9052 | 2594, |
| 9053 | /* VEXTH_D_W */ |
| 9054 | 2596, |
| 9055 | /* VEXTH_HU_BU */ |
| 9056 | 2598, |
| 9057 | /* VEXTH_H_B */ |
| 9058 | 2600, |
| 9059 | /* VEXTH_QU_DU */ |
| 9060 | 2602, |
| 9061 | /* VEXTH_Q_D */ |
| 9062 | 2604, |
| 9063 | /* VEXTH_WU_HU */ |
| 9064 | 2606, |
| 9065 | /* VEXTH_W_H */ |
| 9066 | 2608, |
| 9067 | /* VEXTL_QU_DU */ |
| 9068 | 2610, |
| 9069 | /* VEXTL_Q_D */ |
| 9070 | 2612, |
| 9071 | /* VEXTRINS_B */ |
| 9072 | 2614, |
| 9073 | /* VEXTRINS_D */ |
| 9074 | 2618, |
| 9075 | /* VEXTRINS_H */ |
| 9076 | 2622, |
| 9077 | /* VEXTRINS_W */ |
| 9078 | 2626, |
| 9079 | /* VFADD_D */ |
| 9080 | 2630, |
| 9081 | /* VFADD_S */ |
| 9082 | 2633, |
| 9083 | /* VFCLASS_D */ |
| 9084 | 2636, |
| 9085 | /* VFCLASS_S */ |
| 9086 | 2638, |
| 9087 | /* VFCMP_CAF_D */ |
| 9088 | 2640, |
| 9089 | /* VFCMP_CAF_S */ |
| 9090 | 2643, |
| 9091 | /* VFCMP_CEQ_D */ |
| 9092 | 2646, |
| 9093 | /* VFCMP_CEQ_S */ |
| 9094 | 2649, |
| 9095 | /* VFCMP_CLE_D */ |
| 9096 | 2652, |
| 9097 | /* VFCMP_CLE_S */ |
| 9098 | 2655, |
| 9099 | /* VFCMP_CLT_D */ |
| 9100 | 2658, |
| 9101 | /* VFCMP_CLT_S */ |
| 9102 | 2661, |
| 9103 | /* VFCMP_CNE_D */ |
| 9104 | 2664, |
| 9105 | /* VFCMP_CNE_S */ |
| 9106 | 2667, |
| 9107 | /* VFCMP_COR_D */ |
| 9108 | 2670, |
| 9109 | /* VFCMP_COR_S */ |
| 9110 | 2673, |
| 9111 | /* VFCMP_CUEQ_D */ |
| 9112 | 2676, |
| 9113 | /* VFCMP_CUEQ_S */ |
| 9114 | 2679, |
| 9115 | /* VFCMP_CULE_D */ |
| 9116 | 2682, |
| 9117 | /* VFCMP_CULE_S */ |
| 9118 | 2685, |
| 9119 | /* VFCMP_CULT_D */ |
| 9120 | 2688, |
| 9121 | /* VFCMP_CULT_S */ |
| 9122 | 2691, |
| 9123 | /* VFCMP_CUNE_D */ |
| 9124 | 2694, |
| 9125 | /* VFCMP_CUNE_S */ |
| 9126 | 2697, |
| 9127 | /* VFCMP_CUN_D */ |
| 9128 | 2700, |
| 9129 | /* VFCMP_CUN_S */ |
| 9130 | 2703, |
| 9131 | /* VFCMP_SAF_D */ |
| 9132 | 2706, |
| 9133 | /* VFCMP_SAF_S */ |
| 9134 | 2709, |
| 9135 | /* VFCMP_SEQ_D */ |
| 9136 | 2712, |
| 9137 | /* VFCMP_SEQ_S */ |
| 9138 | 2715, |
| 9139 | /* VFCMP_SLE_D */ |
| 9140 | 2718, |
| 9141 | /* VFCMP_SLE_S */ |
| 9142 | 2721, |
| 9143 | /* VFCMP_SLT_D */ |
| 9144 | 2724, |
| 9145 | /* VFCMP_SLT_S */ |
| 9146 | 2727, |
| 9147 | /* VFCMP_SNE_D */ |
| 9148 | 2730, |
| 9149 | /* VFCMP_SNE_S */ |
| 9150 | 2733, |
| 9151 | /* VFCMP_SOR_D */ |
| 9152 | 2736, |
| 9153 | /* VFCMP_SOR_S */ |
| 9154 | 2739, |
| 9155 | /* VFCMP_SUEQ_D */ |
| 9156 | 2742, |
| 9157 | /* VFCMP_SUEQ_S */ |
| 9158 | 2745, |
| 9159 | /* VFCMP_SULE_D */ |
| 9160 | 2748, |
| 9161 | /* VFCMP_SULE_S */ |
| 9162 | 2751, |
| 9163 | /* VFCMP_SULT_D */ |
| 9164 | 2754, |
| 9165 | /* VFCMP_SULT_S */ |
| 9166 | 2757, |
| 9167 | /* VFCMP_SUNE_D */ |
| 9168 | 2760, |
| 9169 | /* VFCMP_SUNE_S */ |
| 9170 | 2763, |
| 9171 | /* VFCMP_SUN_D */ |
| 9172 | 2766, |
| 9173 | /* VFCMP_SUN_S */ |
| 9174 | 2769, |
| 9175 | /* VFCVTH_D_S */ |
| 9176 | 2772, |
| 9177 | /* VFCVTH_S_H */ |
| 9178 | 2774, |
| 9179 | /* VFCVTL_D_S */ |
| 9180 | 2776, |
| 9181 | /* VFCVTL_S_H */ |
| 9182 | 2778, |
| 9183 | /* VFCVT_H_S */ |
| 9184 | 2780, |
| 9185 | /* VFCVT_S_D */ |
| 9186 | 2783, |
| 9187 | /* VFDIV_D */ |
| 9188 | 2786, |
| 9189 | /* VFDIV_S */ |
| 9190 | 2789, |
| 9191 | /* VFFINTH_D_W */ |
| 9192 | 2792, |
| 9193 | /* VFFINTL_D_W */ |
| 9194 | 2794, |
| 9195 | /* VFFINT_D_L */ |
| 9196 | 2796, |
| 9197 | /* VFFINT_D_LU */ |
| 9198 | 2798, |
| 9199 | /* VFFINT_S_L */ |
| 9200 | 2800, |
| 9201 | /* VFFINT_S_W */ |
| 9202 | 2803, |
| 9203 | /* VFFINT_S_WU */ |
| 9204 | 2805, |
| 9205 | /* VFLOGB_D */ |
| 9206 | 2807, |
| 9207 | /* VFLOGB_S */ |
| 9208 | 2809, |
| 9209 | /* VFMADD_D */ |
| 9210 | 2811, |
| 9211 | /* VFMADD_S */ |
| 9212 | 2815, |
| 9213 | /* VFMAXA_D */ |
| 9214 | 2819, |
| 9215 | /* VFMAXA_S */ |
| 9216 | 2822, |
| 9217 | /* VFMAX_D */ |
| 9218 | 2825, |
| 9219 | /* VFMAX_S */ |
| 9220 | 2828, |
| 9221 | /* VFMINA_D */ |
| 9222 | 2831, |
| 9223 | /* VFMINA_S */ |
| 9224 | 2834, |
| 9225 | /* VFMIN_D */ |
| 9226 | 2837, |
| 9227 | /* VFMIN_S */ |
| 9228 | 2840, |
| 9229 | /* VFMSUB_D */ |
| 9230 | 2843, |
| 9231 | /* VFMSUB_S */ |
| 9232 | 2847, |
| 9233 | /* VFMUL_D */ |
| 9234 | 2851, |
| 9235 | /* VFMUL_S */ |
| 9236 | 2854, |
| 9237 | /* VFNMADD_D */ |
| 9238 | 2857, |
| 9239 | /* VFNMADD_S */ |
| 9240 | 2861, |
| 9241 | /* VFNMSUB_D */ |
| 9242 | 2865, |
| 9243 | /* VFNMSUB_S */ |
| 9244 | 2869, |
| 9245 | /* VFRECIPE_D */ |
| 9246 | 2873, |
| 9247 | /* VFRECIPE_S */ |
| 9248 | 2875, |
| 9249 | /* VFRECIP_D */ |
| 9250 | 2877, |
| 9251 | /* VFRECIP_S */ |
| 9252 | 2879, |
| 9253 | /* VFRINTRM_D */ |
| 9254 | 2881, |
| 9255 | /* VFRINTRM_S */ |
| 9256 | 2883, |
| 9257 | /* VFRINTRNE_D */ |
| 9258 | 2885, |
| 9259 | /* VFRINTRNE_S */ |
| 9260 | 2887, |
| 9261 | /* VFRINTRP_D */ |
| 9262 | 2889, |
| 9263 | /* VFRINTRP_S */ |
| 9264 | 2891, |
| 9265 | /* VFRINTRZ_D */ |
| 9266 | 2893, |
| 9267 | /* VFRINTRZ_S */ |
| 9268 | 2895, |
| 9269 | /* VFRINT_D */ |
| 9270 | 2897, |
| 9271 | /* VFRINT_S */ |
| 9272 | 2899, |
| 9273 | /* VFRSQRTE_D */ |
| 9274 | 2901, |
| 9275 | /* VFRSQRTE_S */ |
| 9276 | 2903, |
| 9277 | /* VFRSQRT_D */ |
| 9278 | 2905, |
| 9279 | /* VFRSQRT_S */ |
| 9280 | 2907, |
| 9281 | /* VFRSTPI_B */ |
| 9282 | 2909, |
| 9283 | /* VFRSTPI_H */ |
| 9284 | 2913, |
| 9285 | /* VFRSTP_B */ |
| 9286 | 2917, |
| 9287 | /* VFRSTP_H */ |
| 9288 | 2921, |
| 9289 | /* VFSQRT_D */ |
| 9290 | 2925, |
| 9291 | /* VFSQRT_S */ |
| 9292 | 2927, |
| 9293 | /* VFSUB_D */ |
| 9294 | 2929, |
| 9295 | /* VFSUB_S */ |
| 9296 | 2932, |
| 9297 | /* VFTINTH_L_S */ |
| 9298 | 2935, |
| 9299 | /* VFTINTL_L_S */ |
| 9300 | 2937, |
| 9301 | /* VFTINTRMH_L_S */ |
| 9302 | 2939, |
| 9303 | /* VFTINTRML_L_S */ |
| 9304 | 2941, |
| 9305 | /* VFTINTRM_L_D */ |
| 9306 | 2943, |
| 9307 | /* VFTINTRM_W_D */ |
| 9308 | 2945, |
| 9309 | /* VFTINTRM_W_S */ |
| 9310 | 2948, |
| 9311 | /* VFTINTRNEH_L_S */ |
| 9312 | 2950, |
| 9313 | /* VFTINTRNEL_L_S */ |
| 9314 | 2952, |
| 9315 | /* VFTINTRNE_L_D */ |
| 9316 | 2954, |
| 9317 | /* VFTINTRNE_W_D */ |
| 9318 | 2956, |
| 9319 | /* VFTINTRNE_W_S */ |
| 9320 | 2959, |
| 9321 | /* VFTINTRPH_L_S */ |
| 9322 | 2961, |
| 9323 | /* VFTINTRPL_L_S */ |
| 9324 | 2963, |
| 9325 | /* VFTINTRP_L_D */ |
| 9326 | 2965, |
| 9327 | /* VFTINTRP_W_D */ |
| 9328 | 2967, |
| 9329 | /* VFTINTRP_W_S */ |
| 9330 | 2970, |
| 9331 | /* VFTINTRZH_L_S */ |
| 9332 | 2972, |
| 9333 | /* VFTINTRZL_L_S */ |
| 9334 | 2974, |
| 9335 | /* VFTINTRZ_LU_D */ |
| 9336 | 2976, |
| 9337 | /* VFTINTRZ_L_D */ |
| 9338 | 2978, |
| 9339 | /* VFTINTRZ_WU_S */ |
| 9340 | 2980, |
| 9341 | /* VFTINTRZ_W_D */ |
| 9342 | 2982, |
| 9343 | /* VFTINTRZ_W_S */ |
| 9344 | 2985, |
| 9345 | /* VFTINT_LU_D */ |
| 9346 | 2987, |
| 9347 | /* VFTINT_L_D */ |
| 9348 | 2989, |
| 9349 | /* VFTINT_WU_S */ |
| 9350 | 2991, |
| 9351 | /* VFTINT_W_D */ |
| 9352 | 2993, |
| 9353 | /* VFTINT_W_S */ |
| 9354 | 2996, |
| 9355 | /* VHADDW_DU_WU */ |
| 9356 | 2998, |
| 9357 | /* VHADDW_D_W */ |
| 9358 | 3001, |
| 9359 | /* VHADDW_HU_BU */ |
| 9360 | 3004, |
| 9361 | /* VHADDW_H_B */ |
| 9362 | 3007, |
| 9363 | /* VHADDW_QU_DU */ |
| 9364 | 3010, |
| 9365 | /* VHADDW_Q_D */ |
| 9366 | 3013, |
| 9367 | /* VHADDW_WU_HU */ |
| 9368 | 3016, |
| 9369 | /* VHADDW_W_H */ |
| 9370 | 3019, |
| 9371 | /* VHSUBW_DU_WU */ |
| 9372 | 3022, |
| 9373 | /* VHSUBW_D_W */ |
| 9374 | 3025, |
| 9375 | /* VHSUBW_HU_BU */ |
| 9376 | 3028, |
| 9377 | /* VHSUBW_H_B */ |
| 9378 | 3031, |
| 9379 | /* VHSUBW_QU_DU */ |
| 9380 | 3034, |
| 9381 | /* VHSUBW_Q_D */ |
| 9382 | 3037, |
| 9383 | /* VHSUBW_WU_HU */ |
| 9384 | 3040, |
| 9385 | /* VHSUBW_W_H */ |
| 9386 | 3043, |
| 9387 | /* VILVH_B */ |
| 9388 | 3046, |
| 9389 | /* VILVH_D */ |
| 9390 | 3049, |
| 9391 | /* VILVH_H */ |
| 9392 | 3052, |
| 9393 | /* VILVH_W */ |
| 9394 | 3055, |
| 9395 | /* VILVL_B */ |
| 9396 | 3058, |
| 9397 | /* VILVL_D */ |
| 9398 | 3061, |
| 9399 | /* VILVL_H */ |
| 9400 | 3064, |
| 9401 | /* VILVL_W */ |
| 9402 | 3067, |
| 9403 | /* VINSGR2VR_B */ |
| 9404 | 3070, |
| 9405 | /* VINSGR2VR_D */ |
| 9406 | 3074, |
| 9407 | /* VINSGR2VR_H */ |
| 9408 | 3078, |
| 9409 | /* VINSGR2VR_W */ |
| 9410 | 3082, |
| 9411 | /* VLD */ |
| 9412 | 3086, |
| 9413 | /* VLDI */ |
| 9414 | 3089, |
| 9415 | /* VLDREPL_B */ |
| 9416 | 3091, |
| 9417 | /* VLDREPL_D */ |
| 9418 | 3094, |
| 9419 | /* VLDREPL_H */ |
| 9420 | 3097, |
| 9421 | /* VLDREPL_W */ |
| 9422 | 3100, |
| 9423 | /* VLDX */ |
| 9424 | 3103, |
| 9425 | /* VMADDWEV_D_W */ |
| 9426 | 3106, |
| 9427 | /* VMADDWEV_D_WU */ |
| 9428 | 3110, |
| 9429 | /* VMADDWEV_D_WU_W */ |
| 9430 | 3114, |
| 9431 | /* VMADDWEV_H_B */ |
| 9432 | 3118, |
| 9433 | /* VMADDWEV_H_BU */ |
| 9434 | 3122, |
| 9435 | /* VMADDWEV_H_BU_B */ |
| 9436 | 3126, |
| 9437 | /* VMADDWEV_Q_D */ |
| 9438 | 3130, |
| 9439 | /* VMADDWEV_Q_DU */ |
| 9440 | 3134, |
| 9441 | /* VMADDWEV_Q_DU_D */ |
| 9442 | 3138, |
| 9443 | /* VMADDWEV_W_H */ |
| 9444 | 3142, |
| 9445 | /* VMADDWEV_W_HU */ |
| 9446 | 3146, |
| 9447 | /* VMADDWEV_W_HU_H */ |
| 9448 | 3150, |
| 9449 | /* VMADDWOD_D_W */ |
| 9450 | 3154, |
| 9451 | /* VMADDWOD_D_WU */ |
| 9452 | 3158, |
| 9453 | /* VMADDWOD_D_WU_W */ |
| 9454 | 3162, |
| 9455 | /* VMADDWOD_H_B */ |
| 9456 | 3166, |
| 9457 | /* VMADDWOD_H_BU */ |
| 9458 | 3170, |
| 9459 | /* VMADDWOD_H_BU_B */ |
| 9460 | 3174, |
| 9461 | /* VMADDWOD_Q_D */ |
| 9462 | 3178, |
| 9463 | /* VMADDWOD_Q_DU */ |
| 9464 | 3182, |
| 9465 | /* VMADDWOD_Q_DU_D */ |
| 9466 | 3186, |
| 9467 | /* VMADDWOD_W_H */ |
| 9468 | 3190, |
| 9469 | /* VMADDWOD_W_HU */ |
| 9470 | 3194, |
| 9471 | /* VMADDWOD_W_HU_H */ |
| 9472 | 3198, |
| 9473 | /* VMADD_B */ |
| 9474 | 3202, |
| 9475 | /* VMADD_D */ |
| 9476 | 3206, |
| 9477 | /* VMADD_H */ |
| 9478 | 3210, |
| 9479 | /* VMADD_W */ |
| 9480 | 3214, |
| 9481 | /* VMAXI_B */ |
| 9482 | 3218, |
| 9483 | /* VMAXI_BU */ |
| 9484 | 3221, |
| 9485 | /* VMAXI_D */ |
| 9486 | 3224, |
| 9487 | /* VMAXI_DU */ |
| 9488 | 3227, |
| 9489 | /* VMAXI_H */ |
| 9490 | 3230, |
| 9491 | /* VMAXI_HU */ |
| 9492 | 3233, |
| 9493 | /* VMAXI_W */ |
| 9494 | 3236, |
| 9495 | /* VMAXI_WU */ |
| 9496 | 3239, |
| 9497 | /* VMAX_B */ |
| 9498 | 3242, |
| 9499 | /* VMAX_BU */ |
| 9500 | 3245, |
| 9501 | /* VMAX_D */ |
| 9502 | 3248, |
| 9503 | /* VMAX_DU */ |
| 9504 | 3251, |
| 9505 | /* VMAX_H */ |
| 9506 | 3254, |
| 9507 | /* VMAX_HU */ |
| 9508 | 3257, |
| 9509 | /* VMAX_W */ |
| 9510 | 3260, |
| 9511 | /* VMAX_WU */ |
| 9512 | 3263, |
| 9513 | /* VMINI_B */ |
| 9514 | 3266, |
| 9515 | /* VMINI_BU */ |
| 9516 | 3269, |
| 9517 | /* VMINI_D */ |
| 9518 | 3272, |
| 9519 | /* VMINI_DU */ |
| 9520 | 3275, |
| 9521 | /* VMINI_H */ |
| 9522 | 3278, |
| 9523 | /* VMINI_HU */ |
| 9524 | 3281, |
| 9525 | /* VMINI_W */ |
| 9526 | 3284, |
| 9527 | /* VMINI_WU */ |
| 9528 | 3287, |
| 9529 | /* VMIN_B */ |
| 9530 | 3290, |
| 9531 | /* VMIN_BU */ |
| 9532 | 3293, |
| 9533 | /* VMIN_D */ |
| 9534 | 3296, |
| 9535 | /* VMIN_DU */ |
| 9536 | 3299, |
| 9537 | /* VMIN_H */ |
| 9538 | 3302, |
| 9539 | /* VMIN_HU */ |
| 9540 | 3305, |
| 9541 | /* VMIN_W */ |
| 9542 | 3308, |
| 9543 | /* VMIN_WU */ |
| 9544 | 3311, |
| 9545 | /* VMOD_B */ |
| 9546 | 3314, |
| 9547 | /* VMOD_BU */ |
| 9548 | 3317, |
| 9549 | /* VMOD_D */ |
| 9550 | 3320, |
| 9551 | /* VMOD_DU */ |
| 9552 | 3323, |
| 9553 | /* VMOD_H */ |
| 9554 | 3326, |
| 9555 | /* VMOD_HU */ |
| 9556 | 3329, |
| 9557 | /* VMOD_W */ |
| 9558 | 3332, |
| 9559 | /* VMOD_WU */ |
| 9560 | 3335, |
| 9561 | /* VMSKGEZ_B */ |
| 9562 | 3338, |
| 9563 | /* VMSKLTZ_B */ |
| 9564 | 3340, |
| 9565 | /* VMSKLTZ_D */ |
| 9566 | 3342, |
| 9567 | /* VMSKLTZ_H */ |
| 9568 | 3344, |
| 9569 | /* VMSKLTZ_W */ |
| 9570 | 3346, |
| 9571 | /* VMSKNZ_B */ |
| 9572 | 3348, |
| 9573 | /* VMSUB_B */ |
| 9574 | 3350, |
| 9575 | /* VMSUB_D */ |
| 9576 | 3354, |
| 9577 | /* VMSUB_H */ |
| 9578 | 3358, |
| 9579 | /* VMSUB_W */ |
| 9580 | 3362, |
| 9581 | /* VMUH_B */ |
| 9582 | 3366, |
| 9583 | /* VMUH_BU */ |
| 9584 | 3369, |
| 9585 | /* VMUH_D */ |
| 9586 | 3372, |
| 9587 | /* VMUH_DU */ |
| 9588 | 3375, |
| 9589 | /* VMUH_H */ |
| 9590 | 3378, |
| 9591 | /* VMUH_HU */ |
| 9592 | 3381, |
| 9593 | /* VMUH_W */ |
| 9594 | 3384, |
| 9595 | /* VMUH_WU */ |
| 9596 | 3387, |
| 9597 | /* VMULWEV_D_W */ |
| 9598 | 3390, |
| 9599 | /* VMULWEV_D_WU */ |
| 9600 | 3393, |
| 9601 | /* VMULWEV_D_WU_W */ |
| 9602 | 3396, |
| 9603 | /* VMULWEV_H_B */ |
| 9604 | 3399, |
| 9605 | /* VMULWEV_H_BU */ |
| 9606 | 3402, |
| 9607 | /* VMULWEV_H_BU_B */ |
| 9608 | 3405, |
| 9609 | /* VMULWEV_Q_D */ |
| 9610 | 3408, |
| 9611 | /* VMULWEV_Q_DU */ |
| 9612 | 3411, |
| 9613 | /* VMULWEV_Q_DU_D */ |
| 9614 | 3414, |
| 9615 | /* VMULWEV_W_H */ |
| 9616 | 3417, |
| 9617 | /* VMULWEV_W_HU */ |
| 9618 | 3420, |
| 9619 | /* VMULWEV_W_HU_H */ |
| 9620 | 3423, |
| 9621 | /* VMULWOD_D_W */ |
| 9622 | 3426, |
| 9623 | /* VMULWOD_D_WU */ |
| 9624 | 3429, |
| 9625 | /* VMULWOD_D_WU_W */ |
| 9626 | 3432, |
| 9627 | /* VMULWOD_H_B */ |
| 9628 | 3435, |
| 9629 | /* VMULWOD_H_BU */ |
| 9630 | 3438, |
| 9631 | /* VMULWOD_H_BU_B */ |
| 9632 | 3441, |
| 9633 | /* VMULWOD_Q_D */ |
| 9634 | 3444, |
| 9635 | /* VMULWOD_Q_DU */ |
| 9636 | 3447, |
| 9637 | /* VMULWOD_Q_DU_D */ |
| 9638 | 3450, |
| 9639 | /* VMULWOD_W_H */ |
| 9640 | 3453, |
| 9641 | /* VMULWOD_W_HU */ |
| 9642 | 3456, |
| 9643 | /* VMULWOD_W_HU_H */ |
| 9644 | 3459, |
| 9645 | /* VMUL_B */ |
| 9646 | 3462, |
| 9647 | /* VMUL_D */ |
| 9648 | 3465, |
| 9649 | /* VMUL_H */ |
| 9650 | 3468, |
| 9651 | /* VMUL_W */ |
| 9652 | 3471, |
| 9653 | /* VNEG_B */ |
| 9654 | 3474, |
| 9655 | /* VNEG_D */ |
| 9656 | 3476, |
| 9657 | /* VNEG_H */ |
| 9658 | 3478, |
| 9659 | /* VNEG_W */ |
| 9660 | 3480, |
| 9661 | /* VNORI_B */ |
| 9662 | 3482, |
| 9663 | /* VNOR_V */ |
| 9664 | 3485, |
| 9665 | /* VORI_B */ |
| 9666 | 3488, |
| 9667 | /* VORN_V */ |
| 9668 | 3491, |
| 9669 | /* VOR_V */ |
| 9670 | 3494, |
| 9671 | /* VPACKEV_B */ |
| 9672 | 3497, |
| 9673 | /* VPACKEV_D */ |
| 9674 | 3500, |
| 9675 | /* VPACKEV_H */ |
| 9676 | 3503, |
| 9677 | /* VPACKEV_W */ |
| 9678 | 3506, |
| 9679 | /* VPACKOD_B */ |
| 9680 | 3509, |
| 9681 | /* VPACKOD_D */ |
| 9682 | 3512, |
| 9683 | /* VPACKOD_H */ |
| 9684 | 3515, |
| 9685 | /* VPACKOD_W */ |
| 9686 | 3518, |
| 9687 | /* VPCNT_B */ |
| 9688 | 3521, |
| 9689 | /* VPCNT_D */ |
| 9690 | 3523, |
| 9691 | /* VPCNT_H */ |
| 9692 | 3525, |
| 9693 | /* VPCNT_W */ |
| 9694 | 3527, |
| 9695 | /* VPERMI_W */ |
| 9696 | 3529, |
| 9697 | /* VPICKEV_B */ |
| 9698 | 3533, |
| 9699 | /* VPICKEV_D */ |
| 9700 | 3536, |
| 9701 | /* VPICKEV_H */ |
| 9702 | 3539, |
| 9703 | /* VPICKEV_W */ |
| 9704 | 3542, |
| 9705 | /* VPICKOD_B */ |
| 9706 | 3545, |
| 9707 | /* VPICKOD_D */ |
| 9708 | 3548, |
| 9709 | /* VPICKOD_H */ |
| 9710 | 3551, |
| 9711 | /* VPICKOD_W */ |
| 9712 | 3554, |
| 9713 | /* VPICKVE2GR_B */ |
| 9714 | 3557, |
| 9715 | /* VPICKVE2GR_BU */ |
| 9716 | 3560, |
| 9717 | /* VPICKVE2GR_D */ |
| 9718 | 3563, |
| 9719 | /* VPICKVE2GR_DU */ |
| 9720 | 3566, |
| 9721 | /* VPICKVE2GR_H */ |
| 9722 | 3569, |
| 9723 | /* VPICKVE2GR_HU */ |
| 9724 | 3572, |
| 9725 | /* VPICKVE2GR_W */ |
| 9726 | 3575, |
| 9727 | /* VPICKVE2GR_WU */ |
| 9728 | 3578, |
| 9729 | /* VREPLGR2VR_B */ |
| 9730 | 3581, |
| 9731 | /* VREPLGR2VR_D */ |
| 9732 | 3583, |
| 9733 | /* VREPLGR2VR_H */ |
| 9734 | 3585, |
| 9735 | /* VREPLGR2VR_W */ |
| 9736 | 3587, |
| 9737 | /* VREPLVEI_B */ |
| 9738 | 3589, |
| 9739 | /* VREPLVEI_D */ |
| 9740 | 3592, |
| 9741 | /* VREPLVEI_H */ |
| 9742 | 3595, |
| 9743 | /* VREPLVEI_W */ |
| 9744 | 3598, |
| 9745 | /* VREPLVE_B */ |
| 9746 | 3601, |
| 9747 | /* VREPLVE_D */ |
| 9748 | 3604, |
| 9749 | /* VREPLVE_H */ |
| 9750 | 3607, |
| 9751 | /* VREPLVE_W */ |
| 9752 | 3610, |
| 9753 | /* VROTRI_B */ |
| 9754 | 3613, |
| 9755 | /* VROTRI_D */ |
| 9756 | 3616, |
| 9757 | /* VROTRI_H */ |
| 9758 | 3619, |
| 9759 | /* VROTRI_W */ |
| 9760 | 3622, |
| 9761 | /* VROTR_B */ |
| 9762 | 3625, |
| 9763 | /* VROTR_D */ |
| 9764 | 3628, |
| 9765 | /* VROTR_H */ |
| 9766 | 3631, |
| 9767 | /* VROTR_W */ |
| 9768 | 3634, |
| 9769 | /* VSADD_B */ |
| 9770 | 3637, |
| 9771 | /* VSADD_BU */ |
| 9772 | 3640, |
| 9773 | /* VSADD_D */ |
| 9774 | 3643, |
| 9775 | /* VSADD_DU */ |
| 9776 | 3646, |
| 9777 | /* VSADD_H */ |
| 9778 | 3649, |
| 9779 | /* VSADD_HU */ |
| 9780 | 3652, |
| 9781 | /* VSADD_W */ |
| 9782 | 3655, |
| 9783 | /* VSADD_WU */ |
| 9784 | 3658, |
| 9785 | /* VSAT_B */ |
| 9786 | 3661, |
| 9787 | /* VSAT_BU */ |
| 9788 | 3664, |
| 9789 | /* VSAT_D */ |
| 9790 | 3667, |
| 9791 | /* VSAT_DU */ |
| 9792 | 3670, |
| 9793 | /* VSAT_H */ |
| 9794 | 3673, |
| 9795 | /* VSAT_HU */ |
| 9796 | 3676, |
| 9797 | /* VSAT_W */ |
| 9798 | 3679, |
| 9799 | /* VSAT_WU */ |
| 9800 | 3682, |
| 9801 | /* VSEQI_B */ |
| 9802 | 3685, |
| 9803 | /* VSEQI_D */ |
| 9804 | 3688, |
| 9805 | /* VSEQI_H */ |
| 9806 | 3691, |
| 9807 | /* VSEQI_W */ |
| 9808 | 3694, |
| 9809 | /* VSEQ_B */ |
| 9810 | 3697, |
| 9811 | /* VSEQ_D */ |
| 9812 | 3700, |
| 9813 | /* VSEQ_H */ |
| 9814 | 3703, |
| 9815 | /* VSEQ_W */ |
| 9816 | 3706, |
| 9817 | /* VSETALLNEZ_B */ |
| 9818 | 3709, |
| 9819 | /* VSETALLNEZ_D */ |
| 9820 | 3711, |
| 9821 | /* VSETALLNEZ_H */ |
| 9822 | 3713, |
| 9823 | /* VSETALLNEZ_W */ |
| 9824 | 3715, |
| 9825 | /* VSETANYEQZ_B */ |
| 9826 | 3717, |
| 9827 | /* VSETANYEQZ_D */ |
| 9828 | 3719, |
| 9829 | /* VSETANYEQZ_H */ |
| 9830 | 3721, |
| 9831 | /* VSETANYEQZ_W */ |
| 9832 | 3723, |
| 9833 | /* VSETEQZ_V */ |
| 9834 | 3725, |
| 9835 | /* VSETNEZ_V */ |
| 9836 | 3727, |
| 9837 | /* VSHUF4I_B */ |
| 9838 | 3729, |
| 9839 | /* VSHUF4I_D */ |
| 9840 | 3732, |
| 9841 | /* VSHUF4I_H */ |
| 9842 | 3736, |
| 9843 | /* VSHUF4I_W */ |
| 9844 | 3739, |
| 9845 | /* VSHUF_B */ |
| 9846 | 3742, |
| 9847 | /* VSHUF_D */ |
| 9848 | 3746, |
| 9849 | /* VSHUF_H */ |
| 9850 | 3750, |
| 9851 | /* VSHUF_W */ |
| 9852 | 3754, |
| 9853 | /* VSIGNCOV_B */ |
| 9854 | 3758, |
| 9855 | /* VSIGNCOV_D */ |
| 9856 | 3761, |
| 9857 | /* VSIGNCOV_H */ |
| 9858 | 3764, |
| 9859 | /* VSIGNCOV_W */ |
| 9860 | 3767, |
| 9861 | /* VSLEI_B */ |
| 9862 | 3770, |
| 9863 | /* VSLEI_BU */ |
| 9864 | 3773, |
| 9865 | /* VSLEI_D */ |
| 9866 | 3776, |
| 9867 | /* VSLEI_DU */ |
| 9868 | 3779, |
| 9869 | /* VSLEI_H */ |
| 9870 | 3782, |
| 9871 | /* VSLEI_HU */ |
| 9872 | 3785, |
| 9873 | /* VSLEI_W */ |
| 9874 | 3788, |
| 9875 | /* VSLEI_WU */ |
| 9876 | 3791, |
| 9877 | /* VSLE_B */ |
| 9878 | 3794, |
| 9879 | /* VSLE_BU */ |
| 9880 | 3797, |
| 9881 | /* VSLE_D */ |
| 9882 | 3800, |
| 9883 | /* VSLE_DU */ |
| 9884 | 3803, |
| 9885 | /* VSLE_H */ |
| 9886 | 3806, |
| 9887 | /* VSLE_HU */ |
| 9888 | 3809, |
| 9889 | /* VSLE_W */ |
| 9890 | 3812, |
| 9891 | /* VSLE_WU */ |
| 9892 | 3815, |
| 9893 | /* VSLLI_B */ |
| 9894 | 3818, |
| 9895 | /* VSLLI_D */ |
| 9896 | 3821, |
| 9897 | /* VSLLI_H */ |
| 9898 | 3824, |
| 9899 | /* VSLLI_W */ |
| 9900 | 3827, |
| 9901 | /* VSLLWIL_DU_WU */ |
| 9902 | 3830, |
| 9903 | /* VSLLWIL_D_W */ |
| 9904 | 3833, |
| 9905 | /* VSLLWIL_HU_BU */ |
| 9906 | 3836, |
| 9907 | /* VSLLWIL_H_B */ |
| 9908 | 3839, |
| 9909 | /* VSLLWIL_WU_HU */ |
| 9910 | 3842, |
| 9911 | /* VSLLWIL_W_H */ |
| 9912 | 3845, |
| 9913 | /* VSLL_B */ |
| 9914 | 3848, |
| 9915 | /* VSLL_D */ |
| 9916 | 3851, |
| 9917 | /* VSLL_H */ |
| 9918 | 3854, |
| 9919 | /* VSLL_W */ |
| 9920 | 3857, |
| 9921 | /* VSLTI_B */ |
| 9922 | 3860, |
| 9923 | /* VSLTI_BU */ |
| 9924 | 3863, |
| 9925 | /* VSLTI_D */ |
| 9926 | 3866, |
| 9927 | /* VSLTI_DU */ |
| 9928 | 3869, |
| 9929 | /* VSLTI_H */ |
| 9930 | 3872, |
| 9931 | /* VSLTI_HU */ |
| 9932 | 3875, |
| 9933 | /* VSLTI_W */ |
| 9934 | 3878, |
| 9935 | /* VSLTI_WU */ |
| 9936 | 3881, |
| 9937 | /* VSLT_B */ |
| 9938 | 3884, |
| 9939 | /* VSLT_BU */ |
| 9940 | 3887, |
| 9941 | /* VSLT_D */ |
| 9942 | 3890, |
| 9943 | /* VSLT_DU */ |
| 9944 | 3893, |
| 9945 | /* VSLT_H */ |
| 9946 | 3896, |
| 9947 | /* VSLT_HU */ |
| 9948 | 3899, |
| 9949 | /* VSLT_W */ |
| 9950 | 3902, |
| 9951 | /* VSLT_WU */ |
| 9952 | 3905, |
| 9953 | /* VSRAI_B */ |
| 9954 | 3908, |
| 9955 | /* VSRAI_D */ |
| 9956 | 3911, |
| 9957 | /* VSRAI_H */ |
| 9958 | 3914, |
| 9959 | /* VSRAI_W */ |
| 9960 | 3917, |
| 9961 | /* VSRANI_B_H */ |
| 9962 | 3920, |
| 9963 | /* VSRANI_D_Q */ |
| 9964 | 3924, |
| 9965 | /* VSRANI_H_W */ |
| 9966 | 3928, |
| 9967 | /* VSRANI_W_D */ |
| 9968 | 3932, |
| 9969 | /* VSRAN_B_H */ |
| 9970 | 3936, |
| 9971 | /* VSRAN_H_W */ |
| 9972 | 3939, |
| 9973 | /* VSRAN_W_D */ |
| 9974 | 3942, |
| 9975 | /* VSRARI_B */ |
| 9976 | 3945, |
| 9977 | /* VSRARI_D */ |
| 9978 | 3948, |
| 9979 | /* VSRARI_H */ |
| 9980 | 3951, |
| 9981 | /* VSRARI_W */ |
| 9982 | 3954, |
| 9983 | /* VSRARNI_B_H */ |
| 9984 | 3957, |
| 9985 | /* VSRARNI_D_Q */ |
| 9986 | 3961, |
| 9987 | /* VSRARNI_H_W */ |
| 9988 | 3965, |
| 9989 | /* VSRARNI_W_D */ |
| 9990 | 3969, |
| 9991 | /* VSRARN_B_H */ |
| 9992 | 3973, |
| 9993 | /* VSRARN_H_W */ |
| 9994 | 3976, |
| 9995 | /* VSRARN_W_D */ |
| 9996 | 3979, |
| 9997 | /* VSRAR_B */ |
| 9998 | 3982, |
| 9999 | /* VSRAR_D */ |
| 10000 | 3985, |
| 10001 | /* VSRAR_H */ |
| 10002 | 3988, |
| 10003 | /* VSRAR_W */ |
| 10004 | 3991, |
| 10005 | /* VSRA_B */ |
| 10006 | 3994, |
| 10007 | /* VSRA_D */ |
| 10008 | 3997, |
| 10009 | /* VSRA_H */ |
| 10010 | 4000, |
| 10011 | /* VSRA_W */ |
| 10012 | 4003, |
| 10013 | /* VSRLI_B */ |
| 10014 | 4006, |
| 10015 | /* VSRLI_D */ |
| 10016 | 4009, |
| 10017 | /* VSRLI_H */ |
| 10018 | 4012, |
| 10019 | /* VSRLI_W */ |
| 10020 | 4015, |
| 10021 | /* VSRLNI_B_H */ |
| 10022 | 4018, |
| 10023 | /* VSRLNI_D_Q */ |
| 10024 | 4022, |
| 10025 | /* VSRLNI_H_W */ |
| 10026 | 4026, |
| 10027 | /* VSRLNI_W_D */ |
| 10028 | 4030, |
| 10029 | /* VSRLN_B_H */ |
| 10030 | 4034, |
| 10031 | /* VSRLN_H_W */ |
| 10032 | 4037, |
| 10033 | /* VSRLN_W_D */ |
| 10034 | 4040, |
| 10035 | /* VSRLRI_B */ |
| 10036 | 4043, |
| 10037 | /* VSRLRI_D */ |
| 10038 | 4046, |
| 10039 | /* VSRLRI_H */ |
| 10040 | 4049, |
| 10041 | /* VSRLRI_W */ |
| 10042 | 4052, |
| 10043 | /* VSRLRNI_B_H */ |
| 10044 | 4055, |
| 10045 | /* VSRLRNI_D_Q */ |
| 10046 | 4059, |
| 10047 | /* VSRLRNI_H_W */ |
| 10048 | 4063, |
| 10049 | /* VSRLRNI_W_D */ |
| 10050 | 4067, |
| 10051 | /* VSRLRN_B_H */ |
| 10052 | 4071, |
| 10053 | /* VSRLRN_H_W */ |
| 10054 | 4074, |
| 10055 | /* VSRLRN_W_D */ |
| 10056 | 4077, |
| 10057 | /* VSRLR_B */ |
| 10058 | 4080, |
| 10059 | /* VSRLR_D */ |
| 10060 | 4083, |
| 10061 | /* VSRLR_H */ |
| 10062 | 4086, |
| 10063 | /* VSRLR_W */ |
| 10064 | 4089, |
| 10065 | /* VSRL_B */ |
| 10066 | 4092, |
| 10067 | /* VSRL_D */ |
| 10068 | 4095, |
| 10069 | /* VSRL_H */ |
| 10070 | 4098, |
| 10071 | /* VSRL_W */ |
| 10072 | 4101, |
| 10073 | /* VSSRANI_BU_H */ |
| 10074 | 4104, |
| 10075 | /* VSSRANI_B_H */ |
| 10076 | 4108, |
| 10077 | /* VSSRANI_DU_Q */ |
| 10078 | 4112, |
| 10079 | /* VSSRANI_D_Q */ |
| 10080 | 4116, |
| 10081 | /* VSSRANI_HU_W */ |
| 10082 | 4120, |
| 10083 | /* VSSRANI_H_W */ |
| 10084 | 4124, |
| 10085 | /* VSSRANI_WU_D */ |
| 10086 | 4128, |
| 10087 | /* VSSRANI_W_D */ |
| 10088 | 4132, |
| 10089 | /* VSSRAN_BU_H */ |
| 10090 | 4136, |
| 10091 | /* VSSRAN_B_H */ |
| 10092 | 4139, |
| 10093 | /* VSSRAN_HU_W */ |
| 10094 | 4142, |
| 10095 | /* VSSRAN_H_W */ |
| 10096 | 4145, |
| 10097 | /* VSSRAN_WU_D */ |
| 10098 | 4148, |
| 10099 | /* VSSRAN_W_D */ |
| 10100 | 4151, |
| 10101 | /* VSSRARNI_BU_H */ |
| 10102 | 4154, |
| 10103 | /* VSSRARNI_B_H */ |
| 10104 | 4158, |
| 10105 | /* VSSRARNI_DU_Q */ |
| 10106 | 4162, |
| 10107 | /* VSSRARNI_D_Q */ |
| 10108 | 4166, |
| 10109 | /* VSSRARNI_HU_W */ |
| 10110 | 4170, |
| 10111 | /* VSSRARNI_H_W */ |
| 10112 | 4174, |
| 10113 | /* VSSRARNI_WU_D */ |
| 10114 | 4178, |
| 10115 | /* VSSRARNI_W_D */ |
| 10116 | 4182, |
| 10117 | /* VSSRARN_BU_H */ |
| 10118 | 4186, |
| 10119 | /* VSSRARN_B_H */ |
| 10120 | 4189, |
| 10121 | /* VSSRARN_HU_W */ |
| 10122 | 4192, |
| 10123 | /* VSSRARN_H_W */ |
| 10124 | 4195, |
| 10125 | /* VSSRARN_WU_D */ |
| 10126 | 4198, |
| 10127 | /* VSSRARN_W_D */ |
| 10128 | 4201, |
| 10129 | /* VSSRLNI_BU_H */ |
| 10130 | 4204, |
| 10131 | /* VSSRLNI_B_H */ |
| 10132 | 4208, |
| 10133 | /* VSSRLNI_DU_Q */ |
| 10134 | 4212, |
| 10135 | /* VSSRLNI_D_Q */ |
| 10136 | 4216, |
| 10137 | /* VSSRLNI_HU_W */ |
| 10138 | 4220, |
| 10139 | /* VSSRLNI_H_W */ |
| 10140 | 4224, |
| 10141 | /* VSSRLNI_WU_D */ |
| 10142 | 4228, |
| 10143 | /* VSSRLNI_W_D */ |
| 10144 | 4232, |
| 10145 | /* VSSRLN_BU_H */ |
| 10146 | 4236, |
| 10147 | /* VSSRLN_B_H */ |
| 10148 | 4239, |
| 10149 | /* VSSRLN_HU_W */ |
| 10150 | 4242, |
| 10151 | /* VSSRLN_H_W */ |
| 10152 | 4245, |
| 10153 | /* VSSRLN_WU_D */ |
| 10154 | 4248, |
| 10155 | /* VSSRLN_W_D */ |
| 10156 | 4251, |
| 10157 | /* VSSRLRNI_BU_H */ |
| 10158 | 4254, |
| 10159 | /* VSSRLRNI_B_H */ |
| 10160 | 4258, |
| 10161 | /* VSSRLRNI_DU_Q */ |
| 10162 | 4262, |
| 10163 | /* VSSRLRNI_D_Q */ |
| 10164 | 4266, |
| 10165 | /* VSSRLRNI_HU_W */ |
| 10166 | 4270, |
| 10167 | /* VSSRLRNI_H_W */ |
| 10168 | 4274, |
| 10169 | /* VSSRLRNI_WU_D */ |
| 10170 | 4278, |
| 10171 | /* VSSRLRNI_W_D */ |
| 10172 | 4282, |
| 10173 | /* VSSRLRN_BU_H */ |
| 10174 | 4286, |
| 10175 | /* VSSRLRN_B_H */ |
| 10176 | 4289, |
| 10177 | /* VSSRLRN_HU_W */ |
| 10178 | 4292, |
| 10179 | /* VSSRLRN_H_W */ |
| 10180 | 4295, |
| 10181 | /* VSSRLRN_WU_D */ |
| 10182 | 4298, |
| 10183 | /* VSSRLRN_W_D */ |
| 10184 | 4301, |
| 10185 | /* VSSUB_B */ |
| 10186 | 4304, |
| 10187 | /* VSSUB_BU */ |
| 10188 | 4307, |
| 10189 | /* VSSUB_D */ |
| 10190 | 4310, |
| 10191 | /* VSSUB_DU */ |
| 10192 | 4313, |
| 10193 | /* VSSUB_H */ |
| 10194 | 4316, |
| 10195 | /* VSSUB_HU */ |
| 10196 | 4319, |
| 10197 | /* VSSUB_W */ |
| 10198 | 4322, |
| 10199 | /* VSSUB_WU */ |
| 10200 | 4325, |
| 10201 | /* VST */ |
| 10202 | 4328, |
| 10203 | /* VSTELM_B */ |
| 10204 | 4331, |
| 10205 | /* VSTELM_D */ |
| 10206 | 4335, |
| 10207 | /* VSTELM_H */ |
| 10208 | 4339, |
| 10209 | /* VSTELM_W */ |
| 10210 | 4343, |
| 10211 | /* VSTX */ |
| 10212 | 4347, |
| 10213 | /* VSUBI_BU */ |
| 10214 | 4350, |
| 10215 | /* VSUBI_DU */ |
| 10216 | 4353, |
| 10217 | /* VSUBI_HU */ |
| 10218 | 4356, |
| 10219 | /* VSUBI_WU */ |
| 10220 | 4359, |
| 10221 | /* VSUBWEV_D_W */ |
| 10222 | 4362, |
| 10223 | /* VSUBWEV_D_WU */ |
| 10224 | 4365, |
| 10225 | /* VSUBWEV_H_B */ |
| 10226 | 4368, |
| 10227 | /* VSUBWEV_H_BU */ |
| 10228 | 4371, |
| 10229 | /* VSUBWEV_Q_D */ |
| 10230 | 4374, |
| 10231 | /* VSUBWEV_Q_DU */ |
| 10232 | 4377, |
| 10233 | /* VSUBWEV_W_H */ |
| 10234 | 4380, |
| 10235 | /* VSUBWEV_W_HU */ |
| 10236 | 4383, |
| 10237 | /* VSUBWOD_D_W */ |
| 10238 | 4386, |
| 10239 | /* VSUBWOD_D_WU */ |
| 10240 | 4389, |
| 10241 | /* VSUBWOD_H_B */ |
| 10242 | 4392, |
| 10243 | /* VSUBWOD_H_BU */ |
| 10244 | 4395, |
| 10245 | /* VSUBWOD_Q_D */ |
| 10246 | 4398, |
| 10247 | /* VSUBWOD_Q_DU */ |
| 10248 | 4401, |
| 10249 | /* VSUBWOD_W_H */ |
| 10250 | 4404, |
| 10251 | /* VSUBWOD_W_HU */ |
| 10252 | 4407, |
| 10253 | /* VSUB_B */ |
| 10254 | 4410, |
| 10255 | /* VSUB_D */ |
| 10256 | 4413, |
| 10257 | /* VSUB_H */ |
| 10258 | 4416, |
| 10259 | /* VSUB_Q */ |
| 10260 | 4419, |
| 10261 | /* VSUB_W */ |
| 10262 | 4422, |
| 10263 | /* VXORI_B */ |
| 10264 | 4425, |
| 10265 | /* VXOR_V */ |
| 10266 | 4428, |
| 10267 | /* X86ADC_B */ |
| 10268 | 4431, |
| 10269 | /* X86ADC_D */ |
| 10270 | 4433, |
| 10271 | /* X86ADC_H */ |
| 10272 | 4435, |
| 10273 | /* X86ADC_W */ |
| 10274 | 4437, |
| 10275 | /* X86ADD_B */ |
| 10276 | 4439, |
| 10277 | /* X86ADD_D */ |
| 10278 | 4441, |
| 10279 | /* X86ADD_DU */ |
| 10280 | 4443, |
| 10281 | /* X86ADD_H */ |
| 10282 | 4445, |
| 10283 | /* X86ADD_W */ |
| 10284 | 4447, |
| 10285 | /* X86ADD_WU */ |
| 10286 | 4449, |
| 10287 | /* X86AND_B */ |
| 10288 | 4451, |
| 10289 | /* X86AND_D */ |
| 10290 | 4453, |
| 10291 | /* X86AND_H */ |
| 10292 | 4455, |
| 10293 | /* X86AND_W */ |
| 10294 | 4457, |
| 10295 | /* X86CLRTM */ |
| 10296 | 4459, |
| 10297 | /* X86DECTOP */ |
| 10298 | 4459, |
| 10299 | /* X86DEC_B */ |
| 10300 | 4459, |
| 10301 | /* X86DEC_D */ |
| 10302 | 4460, |
| 10303 | /* X86DEC_H */ |
| 10304 | 4461, |
| 10305 | /* X86DEC_W */ |
| 10306 | 4462, |
| 10307 | /* X86INCTOP */ |
| 10308 | 4463, |
| 10309 | /* X86INC_B */ |
| 10310 | 4463, |
| 10311 | /* X86INC_D */ |
| 10312 | 4464, |
| 10313 | /* X86INC_H */ |
| 10314 | 4465, |
| 10315 | /* X86INC_W */ |
| 10316 | 4466, |
| 10317 | /* X86MFFLAG */ |
| 10318 | 4467, |
| 10319 | /* X86MFTOP */ |
| 10320 | 4469, |
| 10321 | /* X86MTFLAG */ |
| 10322 | 4470, |
| 10323 | /* X86MTTOP */ |
| 10324 | 4472, |
| 10325 | /* X86MUL_B */ |
| 10326 | 4473, |
| 10327 | /* X86MUL_BU */ |
| 10328 | 4475, |
| 10329 | /* X86MUL_D */ |
| 10330 | 4477, |
| 10331 | /* X86MUL_DU */ |
| 10332 | 4479, |
| 10333 | /* X86MUL_H */ |
| 10334 | 4481, |
| 10335 | /* X86MUL_HU */ |
| 10336 | 4483, |
| 10337 | /* X86MUL_W */ |
| 10338 | 4485, |
| 10339 | /* X86MUL_WU */ |
| 10340 | 4487, |
| 10341 | /* X86OR_B */ |
| 10342 | 4489, |
| 10343 | /* X86OR_D */ |
| 10344 | 4491, |
| 10345 | /* X86OR_H */ |
| 10346 | 4493, |
| 10347 | /* X86OR_W */ |
| 10348 | 4495, |
| 10349 | /* X86RCLI_B */ |
| 10350 | 4497, |
| 10351 | /* X86RCLI_D */ |
| 10352 | 4499, |
| 10353 | /* X86RCLI_H */ |
| 10354 | 4501, |
| 10355 | /* X86RCLI_W */ |
| 10356 | 4503, |
| 10357 | /* X86RCL_B */ |
| 10358 | 4505, |
| 10359 | /* X86RCL_D */ |
| 10360 | 4507, |
| 10361 | /* X86RCL_H */ |
| 10362 | 4509, |
| 10363 | /* X86RCL_W */ |
| 10364 | 4511, |
| 10365 | /* X86RCRI_B */ |
| 10366 | 4513, |
| 10367 | /* X86RCRI_D */ |
| 10368 | 4515, |
| 10369 | /* X86RCRI_H */ |
| 10370 | 4517, |
| 10371 | /* X86RCRI_W */ |
| 10372 | 4519, |
| 10373 | /* X86RCR_B */ |
| 10374 | 4521, |
| 10375 | /* X86RCR_D */ |
| 10376 | 4523, |
| 10377 | /* X86RCR_H */ |
| 10378 | 4525, |
| 10379 | /* X86RCR_W */ |
| 10380 | 4527, |
| 10381 | /* X86ROTLI_B */ |
| 10382 | 4529, |
| 10383 | /* X86ROTLI_D */ |
| 10384 | 4531, |
| 10385 | /* X86ROTLI_H */ |
| 10386 | 4533, |
| 10387 | /* X86ROTLI_W */ |
| 10388 | 4535, |
| 10389 | /* X86ROTL_B */ |
| 10390 | 4537, |
| 10391 | /* X86ROTL_D */ |
| 10392 | 4539, |
| 10393 | /* X86ROTL_H */ |
| 10394 | 4541, |
| 10395 | /* X86ROTL_W */ |
| 10396 | 4543, |
| 10397 | /* X86ROTRI_B */ |
| 10398 | 4545, |
| 10399 | /* X86ROTRI_D */ |
| 10400 | 4547, |
| 10401 | /* X86ROTRI_H */ |
| 10402 | 4549, |
| 10403 | /* X86ROTRI_W */ |
| 10404 | 4551, |
| 10405 | /* X86ROTR_B */ |
| 10406 | 4553, |
| 10407 | /* X86ROTR_D */ |
| 10408 | 4555, |
| 10409 | /* X86ROTR_H */ |
| 10410 | 4557, |
| 10411 | /* X86ROTR_W */ |
| 10412 | 4559, |
| 10413 | /* X86SBC_B */ |
| 10414 | 4561, |
| 10415 | /* X86SBC_D */ |
| 10416 | 4563, |
| 10417 | /* X86SBC_H */ |
| 10418 | 4565, |
| 10419 | /* X86SBC_W */ |
| 10420 | 4567, |
| 10421 | /* X86SETTAG */ |
| 10422 | 4569, |
| 10423 | /* X86SETTM */ |
| 10424 | 4572, |
| 10425 | /* X86SLLI_B */ |
| 10426 | 4572, |
| 10427 | /* X86SLLI_D */ |
| 10428 | 4574, |
| 10429 | /* X86SLLI_H */ |
| 10430 | 4576, |
| 10431 | /* X86SLLI_W */ |
| 10432 | 4578, |
| 10433 | /* X86SLL_B */ |
| 10434 | 4580, |
| 10435 | /* X86SLL_D */ |
| 10436 | 4582, |
| 10437 | /* X86SLL_H */ |
| 10438 | 4584, |
| 10439 | /* X86SLL_W */ |
| 10440 | 4586, |
| 10441 | /* X86SRAI_B */ |
| 10442 | 4588, |
| 10443 | /* X86SRAI_D */ |
| 10444 | 4590, |
| 10445 | /* X86SRAI_H */ |
| 10446 | 4592, |
| 10447 | /* X86SRAI_W */ |
| 10448 | 4594, |
| 10449 | /* X86SRA_B */ |
| 10450 | 4596, |
| 10451 | /* X86SRA_D */ |
| 10452 | 4598, |
| 10453 | /* X86SRA_H */ |
| 10454 | 4600, |
| 10455 | /* X86SRA_W */ |
| 10456 | 4602, |
| 10457 | /* X86SRLI_B */ |
| 10458 | 4604, |
| 10459 | /* X86SRLI_D */ |
| 10460 | 4606, |
| 10461 | /* X86SRLI_H */ |
| 10462 | 4608, |
| 10463 | /* X86SRLI_W */ |
| 10464 | 4610, |
| 10465 | /* X86SRL_B */ |
| 10466 | 4612, |
| 10467 | /* X86SRL_D */ |
| 10468 | 4614, |
| 10469 | /* X86SRL_H */ |
| 10470 | 4616, |
| 10471 | /* X86SRL_W */ |
| 10472 | 4618, |
| 10473 | /* X86SUB_B */ |
| 10474 | 4620, |
| 10475 | /* X86SUB_D */ |
| 10476 | 4622, |
| 10477 | /* X86SUB_DU */ |
| 10478 | 4624, |
| 10479 | /* X86SUB_H */ |
| 10480 | 4626, |
| 10481 | /* X86SUB_W */ |
| 10482 | 4628, |
| 10483 | /* X86SUB_WU */ |
| 10484 | 4630, |
| 10485 | /* X86XOR_B */ |
| 10486 | 4632, |
| 10487 | /* X86XOR_D */ |
| 10488 | 4634, |
| 10489 | /* X86XOR_H */ |
| 10490 | 4636, |
| 10491 | /* X86XOR_W */ |
| 10492 | 4638, |
| 10493 | /* XOR */ |
| 10494 | 4640, |
| 10495 | /* XORI */ |
| 10496 | 4643, |
| 10497 | /* XVABSD_B */ |
| 10498 | 4646, |
| 10499 | /* XVABSD_BU */ |
| 10500 | 4649, |
| 10501 | /* XVABSD_D */ |
| 10502 | 4652, |
| 10503 | /* XVABSD_DU */ |
| 10504 | 4655, |
| 10505 | /* XVABSD_H */ |
| 10506 | 4658, |
| 10507 | /* XVABSD_HU */ |
| 10508 | 4661, |
| 10509 | /* XVABSD_W */ |
| 10510 | 4664, |
| 10511 | /* XVABSD_WU */ |
| 10512 | 4667, |
| 10513 | /* XVADDA_B */ |
| 10514 | 4670, |
| 10515 | /* XVADDA_D */ |
| 10516 | 4673, |
| 10517 | /* XVADDA_H */ |
| 10518 | 4676, |
| 10519 | /* XVADDA_W */ |
| 10520 | 4679, |
| 10521 | /* XVADDI_BU */ |
| 10522 | 4682, |
| 10523 | /* XVADDI_DU */ |
| 10524 | 4685, |
| 10525 | /* XVADDI_HU */ |
| 10526 | 4688, |
| 10527 | /* XVADDI_WU */ |
| 10528 | 4691, |
| 10529 | /* XVADDWEV_D_W */ |
| 10530 | 4694, |
| 10531 | /* XVADDWEV_D_WU */ |
| 10532 | 4697, |
| 10533 | /* XVADDWEV_D_WU_W */ |
| 10534 | 4700, |
| 10535 | /* XVADDWEV_H_B */ |
| 10536 | 4703, |
| 10537 | /* XVADDWEV_H_BU */ |
| 10538 | 4706, |
| 10539 | /* XVADDWEV_H_BU_B */ |
| 10540 | 4709, |
| 10541 | /* XVADDWEV_Q_D */ |
| 10542 | 4712, |
| 10543 | /* XVADDWEV_Q_DU */ |
| 10544 | 4715, |
| 10545 | /* XVADDWEV_Q_DU_D */ |
| 10546 | 4718, |
| 10547 | /* XVADDWEV_W_H */ |
| 10548 | 4721, |
| 10549 | /* XVADDWEV_W_HU */ |
| 10550 | 4724, |
| 10551 | /* XVADDWEV_W_HU_H */ |
| 10552 | 4727, |
| 10553 | /* XVADDWOD_D_W */ |
| 10554 | 4730, |
| 10555 | /* XVADDWOD_D_WU */ |
| 10556 | 4733, |
| 10557 | /* XVADDWOD_D_WU_W */ |
| 10558 | 4736, |
| 10559 | /* XVADDWOD_H_B */ |
| 10560 | 4739, |
| 10561 | /* XVADDWOD_H_BU */ |
| 10562 | 4742, |
| 10563 | /* XVADDWOD_H_BU_B */ |
| 10564 | 4745, |
| 10565 | /* XVADDWOD_Q_D */ |
| 10566 | 4748, |
| 10567 | /* XVADDWOD_Q_DU */ |
| 10568 | 4751, |
| 10569 | /* XVADDWOD_Q_DU_D */ |
| 10570 | 4754, |
| 10571 | /* XVADDWOD_W_H */ |
| 10572 | 4757, |
| 10573 | /* XVADDWOD_W_HU */ |
| 10574 | 4760, |
| 10575 | /* XVADDWOD_W_HU_H */ |
| 10576 | 4763, |
| 10577 | /* XVADD_B */ |
| 10578 | 4766, |
| 10579 | /* XVADD_D */ |
| 10580 | 4769, |
| 10581 | /* XVADD_H */ |
| 10582 | 4772, |
| 10583 | /* XVADD_Q */ |
| 10584 | 4775, |
| 10585 | /* XVADD_W */ |
| 10586 | 4778, |
| 10587 | /* XVANDI_B */ |
| 10588 | 4781, |
| 10589 | /* XVANDN_V */ |
| 10590 | 4784, |
| 10591 | /* XVAND_V */ |
| 10592 | 4787, |
| 10593 | /* XVAVGR_B */ |
| 10594 | 4790, |
| 10595 | /* XVAVGR_BU */ |
| 10596 | 4793, |
| 10597 | /* XVAVGR_D */ |
| 10598 | 4796, |
| 10599 | /* XVAVGR_DU */ |
| 10600 | 4799, |
| 10601 | /* XVAVGR_H */ |
| 10602 | 4802, |
| 10603 | /* XVAVGR_HU */ |
| 10604 | 4805, |
| 10605 | /* XVAVGR_W */ |
| 10606 | 4808, |
| 10607 | /* XVAVGR_WU */ |
| 10608 | 4811, |
| 10609 | /* XVAVG_B */ |
| 10610 | 4814, |
| 10611 | /* XVAVG_BU */ |
| 10612 | 4817, |
| 10613 | /* XVAVG_D */ |
| 10614 | 4820, |
| 10615 | /* XVAVG_DU */ |
| 10616 | 4823, |
| 10617 | /* XVAVG_H */ |
| 10618 | 4826, |
| 10619 | /* XVAVG_HU */ |
| 10620 | 4829, |
| 10621 | /* XVAVG_W */ |
| 10622 | 4832, |
| 10623 | /* XVAVG_WU */ |
| 10624 | 4835, |
| 10625 | /* XVBITCLRI_B */ |
| 10626 | 4838, |
| 10627 | /* XVBITCLRI_D */ |
| 10628 | 4841, |
| 10629 | /* XVBITCLRI_H */ |
| 10630 | 4844, |
| 10631 | /* XVBITCLRI_W */ |
| 10632 | 4847, |
| 10633 | /* XVBITCLR_B */ |
| 10634 | 4850, |
| 10635 | /* XVBITCLR_D */ |
| 10636 | 4853, |
| 10637 | /* XVBITCLR_H */ |
| 10638 | 4856, |
| 10639 | /* XVBITCLR_W */ |
| 10640 | 4859, |
| 10641 | /* XVBITREVI_B */ |
| 10642 | 4862, |
| 10643 | /* XVBITREVI_D */ |
| 10644 | 4865, |
| 10645 | /* XVBITREVI_H */ |
| 10646 | 4868, |
| 10647 | /* XVBITREVI_W */ |
| 10648 | 4871, |
| 10649 | /* XVBITREV_B */ |
| 10650 | 4874, |
| 10651 | /* XVBITREV_D */ |
| 10652 | 4877, |
| 10653 | /* XVBITREV_H */ |
| 10654 | 4880, |
| 10655 | /* XVBITREV_W */ |
| 10656 | 4883, |
| 10657 | /* XVBITSELI_B */ |
| 10658 | 4886, |
| 10659 | /* XVBITSEL_V */ |
| 10660 | 4890, |
| 10661 | /* XVBITSETI_B */ |
| 10662 | 4894, |
| 10663 | /* XVBITSETI_D */ |
| 10664 | 4897, |
| 10665 | /* XVBITSETI_H */ |
| 10666 | 4900, |
| 10667 | /* XVBITSETI_W */ |
| 10668 | 4903, |
| 10669 | /* XVBITSET_B */ |
| 10670 | 4906, |
| 10671 | /* XVBITSET_D */ |
| 10672 | 4909, |
| 10673 | /* XVBITSET_H */ |
| 10674 | 4912, |
| 10675 | /* XVBITSET_W */ |
| 10676 | 4915, |
| 10677 | /* XVBSLL_V */ |
| 10678 | 4918, |
| 10679 | /* XVBSRL_V */ |
| 10680 | 4921, |
| 10681 | /* XVCLO_B */ |
| 10682 | 4924, |
| 10683 | /* XVCLO_D */ |
| 10684 | 4926, |
| 10685 | /* XVCLO_H */ |
| 10686 | 4928, |
| 10687 | /* XVCLO_W */ |
| 10688 | 4930, |
| 10689 | /* XVCLZ_B */ |
| 10690 | 4932, |
| 10691 | /* XVCLZ_D */ |
| 10692 | 4934, |
| 10693 | /* XVCLZ_H */ |
| 10694 | 4936, |
| 10695 | /* XVCLZ_W */ |
| 10696 | 4938, |
| 10697 | /* XVDIV_B */ |
| 10698 | 4940, |
| 10699 | /* XVDIV_BU */ |
| 10700 | 4943, |
| 10701 | /* XVDIV_D */ |
| 10702 | 4946, |
| 10703 | /* XVDIV_DU */ |
| 10704 | 4949, |
| 10705 | /* XVDIV_H */ |
| 10706 | 4952, |
| 10707 | /* XVDIV_HU */ |
| 10708 | 4955, |
| 10709 | /* XVDIV_W */ |
| 10710 | 4958, |
| 10711 | /* XVDIV_WU */ |
| 10712 | 4961, |
| 10713 | /* XVEXTH_DU_WU */ |
| 10714 | 4964, |
| 10715 | /* XVEXTH_D_W */ |
| 10716 | 4966, |
| 10717 | /* XVEXTH_HU_BU */ |
| 10718 | 4968, |
| 10719 | /* XVEXTH_H_B */ |
| 10720 | 4970, |
| 10721 | /* XVEXTH_QU_DU */ |
| 10722 | 4972, |
| 10723 | /* XVEXTH_Q_D */ |
| 10724 | 4974, |
| 10725 | /* XVEXTH_WU_HU */ |
| 10726 | 4976, |
| 10727 | /* XVEXTH_W_H */ |
| 10728 | 4978, |
| 10729 | /* XVEXTL_QU_DU */ |
| 10730 | 4980, |
| 10731 | /* XVEXTL_Q_D */ |
| 10732 | 4982, |
| 10733 | /* XVEXTRINS_B */ |
| 10734 | 4984, |
| 10735 | /* XVEXTRINS_D */ |
| 10736 | 4988, |
| 10737 | /* XVEXTRINS_H */ |
| 10738 | 4992, |
| 10739 | /* XVEXTRINS_W */ |
| 10740 | 4996, |
| 10741 | /* XVFADD_D */ |
| 10742 | 5000, |
| 10743 | /* XVFADD_S */ |
| 10744 | 5003, |
| 10745 | /* XVFCLASS_D */ |
| 10746 | 5006, |
| 10747 | /* XVFCLASS_S */ |
| 10748 | 5008, |
| 10749 | /* XVFCMP_CAF_D */ |
| 10750 | 5010, |
| 10751 | /* XVFCMP_CAF_S */ |
| 10752 | 5013, |
| 10753 | /* XVFCMP_CEQ_D */ |
| 10754 | 5016, |
| 10755 | /* XVFCMP_CEQ_S */ |
| 10756 | 5019, |
| 10757 | /* XVFCMP_CLE_D */ |
| 10758 | 5022, |
| 10759 | /* XVFCMP_CLE_S */ |
| 10760 | 5025, |
| 10761 | /* XVFCMP_CLT_D */ |
| 10762 | 5028, |
| 10763 | /* XVFCMP_CLT_S */ |
| 10764 | 5031, |
| 10765 | /* XVFCMP_CNE_D */ |
| 10766 | 5034, |
| 10767 | /* XVFCMP_CNE_S */ |
| 10768 | 5037, |
| 10769 | /* XVFCMP_COR_D */ |
| 10770 | 5040, |
| 10771 | /* XVFCMP_COR_S */ |
| 10772 | 5043, |
| 10773 | /* XVFCMP_CUEQ_D */ |
| 10774 | 5046, |
| 10775 | /* XVFCMP_CUEQ_S */ |
| 10776 | 5049, |
| 10777 | /* XVFCMP_CULE_D */ |
| 10778 | 5052, |
| 10779 | /* XVFCMP_CULE_S */ |
| 10780 | 5055, |
| 10781 | /* XVFCMP_CULT_D */ |
| 10782 | 5058, |
| 10783 | /* XVFCMP_CULT_S */ |
| 10784 | 5061, |
| 10785 | /* XVFCMP_CUNE_D */ |
| 10786 | 5064, |
| 10787 | /* XVFCMP_CUNE_S */ |
| 10788 | 5067, |
| 10789 | /* XVFCMP_CUN_D */ |
| 10790 | 5070, |
| 10791 | /* XVFCMP_CUN_S */ |
| 10792 | 5073, |
| 10793 | /* XVFCMP_SAF_D */ |
| 10794 | 5076, |
| 10795 | /* XVFCMP_SAF_S */ |
| 10796 | 5079, |
| 10797 | /* XVFCMP_SEQ_D */ |
| 10798 | 5082, |
| 10799 | /* XVFCMP_SEQ_S */ |
| 10800 | 5085, |
| 10801 | /* XVFCMP_SLE_D */ |
| 10802 | 5088, |
| 10803 | /* XVFCMP_SLE_S */ |
| 10804 | 5091, |
| 10805 | /* XVFCMP_SLT_D */ |
| 10806 | 5094, |
| 10807 | /* XVFCMP_SLT_S */ |
| 10808 | 5097, |
| 10809 | /* XVFCMP_SNE_D */ |
| 10810 | 5100, |
| 10811 | /* XVFCMP_SNE_S */ |
| 10812 | 5103, |
| 10813 | /* XVFCMP_SOR_D */ |
| 10814 | 5106, |
| 10815 | /* XVFCMP_SOR_S */ |
| 10816 | 5109, |
| 10817 | /* XVFCMP_SUEQ_D */ |
| 10818 | 5112, |
| 10819 | /* XVFCMP_SUEQ_S */ |
| 10820 | 5115, |
| 10821 | /* XVFCMP_SULE_D */ |
| 10822 | 5118, |
| 10823 | /* XVFCMP_SULE_S */ |
| 10824 | 5121, |
| 10825 | /* XVFCMP_SULT_D */ |
| 10826 | 5124, |
| 10827 | /* XVFCMP_SULT_S */ |
| 10828 | 5127, |
| 10829 | /* XVFCMP_SUNE_D */ |
| 10830 | 5130, |
| 10831 | /* XVFCMP_SUNE_S */ |
| 10832 | 5133, |
| 10833 | /* XVFCMP_SUN_D */ |
| 10834 | 5136, |
| 10835 | /* XVFCMP_SUN_S */ |
| 10836 | 5139, |
| 10837 | /* XVFCVTH_D_S */ |
| 10838 | 5142, |
| 10839 | /* XVFCVTH_S_H */ |
| 10840 | 5144, |
| 10841 | /* XVFCVTL_D_S */ |
| 10842 | 5146, |
| 10843 | /* XVFCVTL_S_H */ |
| 10844 | 5148, |
| 10845 | /* XVFCVT_H_S */ |
| 10846 | 5150, |
| 10847 | /* XVFCVT_S_D */ |
| 10848 | 5153, |
| 10849 | /* XVFDIV_D */ |
| 10850 | 5156, |
| 10851 | /* XVFDIV_S */ |
| 10852 | 5159, |
| 10853 | /* XVFFINTH_D_W */ |
| 10854 | 5162, |
| 10855 | /* XVFFINTL_D_W */ |
| 10856 | 5164, |
| 10857 | /* XVFFINT_D_L */ |
| 10858 | 5166, |
| 10859 | /* XVFFINT_D_LU */ |
| 10860 | 5168, |
| 10861 | /* XVFFINT_S_L */ |
| 10862 | 5170, |
| 10863 | /* XVFFINT_S_W */ |
| 10864 | 5173, |
| 10865 | /* XVFFINT_S_WU */ |
| 10866 | 5175, |
| 10867 | /* XVFLOGB_D */ |
| 10868 | 5177, |
| 10869 | /* XVFLOGB_S */ |
| 10870 | 5179, |
| 10871 | /* XVFMADD_D */ |
| 10872 | 5181, |
| 10873 | /* XVFMADD_S */ |
| 10874 | 5185, |
| 10875 | /* XVFMAXA_D */ |
| 10876 | 5189, |
| 10877 | /* XVFMAXA_S */ |
| 10878 | 5192, |
| 10879 | /* XVFMAX_D */ |
| 10880 | 5195, |
| 10881 | /* XVFMAX_S */ |
| 10882 | 5198, |
| 10883 | /* XVFMINA_D */ |
| 10884 | 5201, |
| 10885 | /* XVFMINA_S */ |
| 10886 | 5204, |
| 10887 | /* XVFMIN_D */ |
| 10888 | 5207, |
| 10889 | /* XVFMIN_S */ |
| 10890 | 5210, |
| 10891 | /* XVFMSUB_D */ |
| 10892 | 5213, |
| 10893 | /* XVFMSUB_S */ |
| 10894 | 5217, |
| 10895 | /* XVFMUL_D */ |
| 10896 | 5221, |
| 10897 | /* XVFMUL_S */ |
| 10898 | 5224, |
| 10899 | /* XVFNMADD_D */ |
| 10900 | 5227, |
| 10901 | /* XVFNMADD_S */ |
| 10902 | 5231, |
| 10903 | /* XVFNMSUB_D */ |
| 10904 | 5235, |
| 10905 | /* XVFNMSUB_S */ |
| 10906 | 5239, |
| 10907 | /* XVFRECIPE_D */ |
| 10908 | 5243, |
| 10909 | /* XVFRECIPE_S */ |
| 10910 | 5245, |
| 10911 | /* XVFRECIP_D */ |
| 10912 | 5247, |
| 10913 | /* XVFRECIP_S */ |
| 10914 | 5249, |
| 10915 | /* XVFRINTRM_D */ |
| 10916 | 5251, |
| 10917 | /* XVFRINTRM_S */ |
| 10918 | 5253, |
| 10919 | /* XVFRINTRNE_D */ |
| 10920 | 5255, |
| 10921 | /* XVFRINTRNE_S */ |
| 10922 | 5257, |
| 10923 | /* XVFRINTRP_D */ |
| 10924 | 5259, |
| 10925 | /* XVFRINTRP_S */ |
| 10926 | 5261, |
| 10927 | /* XVFRINTRZ_D */ |
| 10928 | 5263, |
| 10929 | /* XVFRINTRZ_S */ |
| 10930 | 5265, |
| 10931 | /* XVFRINT_D */ |
| 10932 | 5267, |
| 10933 | /* XVFRINT_S */ |
| 10934 | 5269, |
| 10935 | /* XVFRSQRTE_D */ |
| 10936 | 5271, |
| 10937 | /* XVFRSQRTE_S */ |
| 10938 | 5273, |
| 10939 | /* XVFRSQRT_D */ |
| 10940 | 5275, |
| 10941 | /* XVFRSQRT_S */ |
| 10942 | 5277, |
| 10943 | /* XVFRSTPI_B */ |
| 10944 | 5279, |
| 10945 | /* XVFRSTPI_H */ |
| 10946 | 5283, |
| 10947 | /* XVFRSTP_B */ |
| 10948 | 5287, |
| 10949 | /* XVFRSTP_H */ |
| 10950 | 5291, |
| 10951 | /* XVFSQRT_D */ |
| 10952 | 5295, |
| 10953 | /* XVFSQRT_S */ |
| 10954 | 5297, |
| 10955 | /* XVFSUB_D */ |
| 10956 | 5299, |
| 10957 | /* XVFSUB_S */ |
| 10958 | 5302, |
| 10959 | /* XVFTINTH_L_S */ |
| 10960 | 5305, |
| 10961 | /* XVFTINTL_L_S */ |
| 10962 | 5307, |
| 10963 | /* XVFTINTRMH_L_S */ |
| 10964 | 5309, |
| 10965 | /* XVFTINTRML_L_S */ |
| 10966 | 5311, |
| 10967 | /* XVFTINTRM_L_D */ |
| 10968 | 5313, |
| 10969 | /* XVFTINTRM_W_D */ |
| 10970 | 5315, |
| 10971 | /* XVFTINTRM_W_S */ |
| 10972 | 5318, |
| 10973 | /* XVFTINTRNEH_L_S */ |
| 10974 | 5320, |
| 10975 | /* XVFTINTRNEL_L_S */ |
| 10976 | 5322, |
| 10977 | /* XVFTINTRNE_L_D */ |
| 10978 | 5324, |
| 10979 | /* XVFTINTRNE_W_D */ |
| 10980 | 5326, |
| 10981 | /* XVFTINTRNE_W_S */ |
| 10982 | 5329, |
| 10983 | /* XVFTINTRPH_L_S */ |
| 10984 | 5331, |
| 10985 | /* XVFTINTRPL_L_S */ |
| 10986 | 5333, |
| 10987 | /* XVFTINTRP_L_D */ |
| 10988 | 5335, |
| 10989 | /* XVFTINTRP_W_D */ |
| 10990 | 5337, |
| 10991 | /* XVFTINTRP_W_S */ |
| 10992 | 5340, |
| 10993 | /* XVFTINTRZH_L_S */ |
| 10994 | 5342, |
| 10995 | /* XVFTINTRZL_L_S */ |
| 10996 | 5344, |
| 10997 | /* XVFTINTRZ_LU_D */ |
| 10998 | 5346, |
| 10999 | /* XVFTINTRZ_L_D */ |
| 11000 | 5348, |
| 11001 | /* XVFTINTRZ_WU_S */ |
| 11002 | 5350, |
| 11003 | /* XVFTINTRZ_W_D */ |
| 11004 | 5352, |
| 11005 | /* XVFTINTRZ_W_S */ |
| 11006 | 5355, |
| 11007 | /* XVFTINT_LU_D */ |
| 11008 | 5357, |
| 11009 | /* XVFTINT_L_D */ |
| 11010 | 5359, |
| 11011 | /* XVFTINT_WU_S */ |
| 11012 | 5361, |
| 11013 | /* XVFTINT_W_D */ |
| 11014 | 5363, |
| 11015 | /* XVFTINT_W_S */ |
| 11016 | 5366, |
| 11017 | /* XVHADDW_DU_WU */ |
| 11018 | 5368, |
| 11019 | /* XVHADDW_D_W */ |
| 11020 | 5371, |
| 11021 | /* XVHADDW_HU_BU */ |
| 11022 | 5374, |
| 11023 | /* XVHADDW_H_B */ |
| 11024 | 5377, |
| 11025 | /* XVHADDW_QU_DU */ |
| 11026 | 5380, |
| 11027 | /* XVHADDW_Q_D */ |
| 11028 | 5383, |
| 11029 | /* XVHADDW_WU_HU */ |
| 11030 | 5386, |
| 11031 | /* XVHADDW_W_H */ |
| 11032 | 5389, |
| 11033 | /* XVHSELI_D */ |
| 11034 | 5392, |
| 11035 | /* XVHSUBW_DU_WU */ |
| 11036 | 5395, |
| 11037 | /* XVHSUBW_D_W */ |
| 11038 | 5398, |
| 11039 | /* XVHSUBW_HU_BU */ |
| 11040 | 5401, |
| 11041 | /* XVHSUBW_H_B */ |
| 11042 | 5404, |
| 11043 | /* XVHSUBW_QU_DU */ |
| 11044 | 5407, |
| 11045 | /* XVHSUBW_Q_D */ |
| 11046 | 5410, |
| 11047 | /* XVHSUBW_WU_HU */ |
| 11048 | 5413, |
| 11049 | /* XVHSUBW_W_H */ |
| 11050 | 5416, |
| 11051 | /* XVILVH_B */ |
| 11052 | 5419, |
| 11053 | /* XVILVH_D */ |
| 11054 | 5422, |
| 11055 | /* XVILVH_H */ |
| 11056 | 5425, |
| 11057 | /* XVILVH_W */ |
| 11058 | 5428, |
| 11059 | /* XVILVL_B */ |
| 11060 | 5431, |
| 11061 | /* XVILVL_D */ |
| 11062 | 5434, |
| 11063 | /* XVILVL_H */ |
| 11064 | 5437, |
| 11065 | /* XVILVL_W */ |
| 11066 | 5440, |
| 11067 | /* XVINSGR2VR_D */ |
| 11068 | 5443, |
| 11069 | /* XVINSGR2VR_W */ |
| 11070 | 5447, |
| 11071 | /* XVINSVE0_D */ |
| 11072 | 5451, |
| 11073 | /* XVINSVE0_W */ |
| 11074 | 5455, |
| 11075 | /* XVLD */ |
| 11076 | 5459, |
| 11077 | /* XVLDI */ |
| 11078 | 5462, |
| 11079 | /* XVLDREPL_B */ |
| 11080 | 5464, |
| 11081 | /* XVLDREPL_D */ |
| 11082 | 5467, |
| 11083 | /* XVLDREPL_H */ |
| 11084 | 5470, |
| 11085 | /* XVLDREPL_W */ |
| 11086 | 5473, |
| 11087 | /* XVLDX */ |
| 11088 | 5476, |
| 11089 | /* XVMADDWEV_D_W */ |
| 11090 | 5479, |
| 11091 | /* XVMADDWEV_D_WU */ |
| 11092 | 5483, |
| 11093 | /* XVMADDWEV_D_WU_W */ |
| 11094 | 5487, |
| 11095 | /* XVMADDWEV_H_B */ |
| 11096 | 5491, |
| 11097 | /* XVMADDWEV_H_BU */ |
| 11098 | 5495, |
| 11099 | /* XVMADDWEV_H_BU_B */ |
| 11100 | 5499, |
| 11101 | /* XVMADDWEV_Q_D */ |
| 11102 | 5503, |
| 11103 | /* XVMADDWEV_Q_DU */ |
| 11104 | 5507, |
| 11105 | /* XVMADDWEV_Q_DU_D */ |
| 11106 | 5511, |
| 11107 | /* XVMADDWEV_W_H */ |
| 11108 | 5515, |
| 11109 | /* XVMADDWEV_W_HU */ |
| 11110 | 5519, |
| 11111 | /* XVMADDWEV_W_HU_H */ |
| 11112 | 5523, |
| 11113 | /* XVMADDWOD_D_W */ |
| 11114 | 5527, |
| 11115 | /* XVMADDWOD_D_WU */ |
| 11116 | 5531, |
| 11117 | /* XVMADDWOD_D_WU_W */ |
| 11118 | 5535, |
| 11119 | /* XVMADDWOD_H_B */ |
| 11120 | 5539, |
| 11121 | /* XVMADDWOD_H_BU */ |
| 11122 | 5543, |
| 11123 | /* XVMADDWOD_H_BU_B */ |
| 11124 | 5547, |
| 11125 | /* XVMADDWOD_Q_D */ |
| 11126 | 5551, |
| 11127 | /* XVMADDWOD_Q_DU */ |
| 11128 | 5555, |
| 11129 | /* XVMADDWOD_Q_DU_D */ |
| 11130 | 5559, |
| 11131 | /* XVMADDWOD_W_H */ |
| 11132 | 5563, |
| 11133 | /* XVMADDWOD_W_HU */ |
| 11134 | 5567, |
| 11135 | /* XVMADDWOD_W_HU_H */ |
| 11136 | 5571, |
| 11137 | /* XVMADD_B */ |
| 11138 | 5575, |
| 11139 | /* XVMADD_D */ |
| 11140 | 5579, |
| 11141 | /* XVMADD_H */ |
| 11142 | 5583, |
| 11143 | /* XVMADD_W */ |
| 11144 | 5587, |
| 11145 | /* XVMAXI_B */ |
| 11146 | 5591, |
| 11147 | /* XVMAXI_BU */ |
| 11148 | 5594, |
| 11149 | /* XVMAXI_D */ |
| 11150 | 5597, |
| 11151 | /* XVMAXI_DU */ |
| 11152 | 5600, |
| 11153 | /* XVMAXI_H */ |
| 11154 | 5603, |
| 11155 | /* XVMAXI_HU */ |
| 11156 | 5606, |
| 11157 | /* XVMAXI_W */ |
| 11158 | 5609, |
| 11159 | /* XVMAXI_WU */ |
| 11160 | 5612, |
| 11161 | /* XVMAX_B */ |
| 11162 | 5615, |
| 11163 | /* XVMAX_BU */ |
| 11164 | 5618, |
| 11165 | /* XVMAX_D */ |
| 11166 | 5621, |
| 11167 | /* XVMAX_DU */ |
| 11168 | 5624, |
| 11169 | /* XVMAX_H */ |
| 11170 | 5627, |
| 11171 | /* XVMAX_HU */ |
| 11172 | 5630, |
| 11173 | /* XVMAX_W */ |
| 11174 | 5633, |
| 11175 | /* XVMAX_WU */ |
| 11176 | 5636, |
| 11177 | /* XVMINI_B */ |
| 11178 | 5639, |
| 11179 | /* XVMINI_BU */ |
| 11180 | 5642, |
| 11181 | /* XVMINI_D */ |
| 11182 | 5645, |
| 11183 | /* XVMINI_DU */ |
| 11184 | 5648, |
| 11185 | /* XVMINI_H */ |
| 11186 | 5651, |
| 11187 | /* XVMINI_HU */ |
| 11188 | 5654, |
| 11189 | /* XVMINI_W */ |
| 11190 | 5657, |
| 11191 | /* XVMINI_WU */ |
| 11192 | 5660, |
| 11193 | /* XVMIN_B */ |
| 11194 | 5663, |
| 11195 | /* XVMIN_BU */ |
| 11196 | 5666, |
| 11197 | /* XVMIN_D */ |
| 11198 | 5669, |
| 11199 | /* XVMIN_DU */ |
| 11200 | 5672, |
| 11201 | /* XVMIN_H */ |
| 11202 | 5675, |
| 11203 | /* XVMIN_HU */ |
| 11204 | 5678, |
| 11205 | /* XVMIN_W */ |
| 11206 | 5681, |
| 11207 | /* XVMIN_WU */ |
| 11208 | 5684, |
| 11209 | /* XVMOD_B */ |
| 11210 | 5687, |
| 11211 | /* XVMOD_BU */ |
| 11212 | 5690, |
| 11213 | /* XVMOD_D */ |
| 11214 | 5693, |
| 11215 | /* XVMOD_DU */ |
| 11216 | 5696, |
| 11217 | /* XVMOD_H */ |
| 11218 | 5699, |
| 11219 | /* XVMOD_HU */ |
| 11220 | 5702, |
| 11221 | /* XVMOD_W */ |
| 11222 | 5705, |
| 11223 | /* XVMOD_WU */ |
| 11224 | 5708, |
| 11225 | /* XVMSKGEZ_B */ |
| 11226 | 5711, |
| 11227 | /* XVMSKLTZ_B */ |
| 11228 | 5713, |
| 11229 | /* XVMSKLTZ_D */ |
| 11230 | 5715, |
| 11231 | /* XVMSKLTZ_H */ |
| 11232 | 5717, |
| 11233 | /* XVMSKLTZ_W */ |
| 11234 | 5719, |
| 11235 | /* XVMSKNZ_B */ |
| 11236 | 5721, |
| 11237 | /* XVMSUB_B */ |
| 11238 | 5723, |
| 11239 | /* XVMSUB_D */ |
| 11240 | 5727, |
| 11241 | /* XVMSUB_H */ |
| 11242 | 5731, |
| 11243 | /* XVMSUB_W */ |
| 11244 | 5735, |
| 11245 | /* XVMUH_B */ |
| 11246 | 5739, |
| 11247 | /* XVMUH_BU */ |
| 11248 | 5742, |
| 11249 | /* XVMUH_D */ |
| 11250 | 5745, |
| 11251 | /* XVMUH_DU */ |
| 11252 | 5748, |
| 11253 | /* XVMUH_H */ |
| 11254 | 5751, |
| 11255 | /* XVMUH_HU */ |
| 11256 | 5754, |
| 11257 | /* XVMUH_W */ |
| 11258 | 5757, |
| 11259 | /* XVMUH_WU */ |
| 11260 | 5760, |
| 11261 | /* XVMULWEV_D_W */ |
| 11262 | 5763, |
| 11263 | /* XVMULWEV_D_WU */ |
| 11264 | 5766, |
| 11265 | /* XVMULWEV_D_WU_W */ |
| 11266 | 5769, |
| 11267 | /* XVMULWEV_H_B */ |
| 11268 | 5772, |
| 11269 | /* XVMULWEV_H_BU */ |
| 11270 | 5775, |
| 11271 | /* XVMULWEV_H_BU_B */ |
| 11272 | 5778, |
| 11273 | /* XVMULWEV_Q_D */ |
| 11274 | 5781, |
| 11275 | /* XVMULWEV_Q_DU */ |
| 11276 | 5784, |
| 11277 | /* XVMULWEV_Q_DU_D */ |
| 11278 | 5787, |
| 11279 | /* XVMULWEV_W_H */ |
| 11280 | 5790, |
| 11281 | /* XVMULWEV_W_HU */ |
| 11282 | 5793, |
| 11283 | /* XVMULWEV_W_HU_H */ |
| 11284 | 5796, |
| 11285 | /* XVMULWOD_D_W */ |
| 11286 | 5799, |
| 11287 | /* XVMULWOD_D_WU */ |
| 11288 | 5802, |
| 11289 | /* XVMULWOD_D_WU_W */ |
| 11290 | 5805, |
| 11291 | /* XVMULWOD_H_B */ |
| 11292 | 5808, |
| 11293 | /* XVMULWOD_H_BU */ |
| 11294 | 5811, |
| 11295 | /* XVMULWOD_H_BU_B */ |
| 11296 | 5814, |
| 11297 | /* XVMULWOD_Q_D */ |
| 11298 | 5817, |
| 11299 | /* XVMULWOD_Q_DU */ |
| 11300 | 5820, |
| 11301 | /* XVMULWOD_Q_DU_D */ |
| 11302 | 5823, |
| 11303 | /* XVMULWOD_W_H */ |
| 11304 | 5826, |
| 11305 | /* XVMULWOD_W_HU */ |
| 11306 | 5829, |
| 11307 | /* XVMULWOD_W_HU_H */ |
| 11308 | 5832, |
| 11309 | /* XVMUL_B */ |
| 11310 | 5835, |
| 11311 | /* XVMUL_D */ |
| 11312 | 5838, |
| 11313 | /* XVMUL_H */ |
| 11314 | 5841, |
| 11315 | /* XVMUL_W */ |
| 11316 | 5844, |
| 11317 | /* XVNEG_B */ |
| 11318 | 5847, |
| 11319 | /* XVNEG_D */ |
| 11320 | 5849, |
| 11321 | /* XVNEG_H */ |
| 11322 | 5851, |
| 11323 | /* XVNEG_W */ |
| 11324 | 5853, |
| 11325 | /* XVNORI_B */ |
| 11326 | 5855, |
| 11327 | /* XVNOR_V */ |
| 11328 | 5858, |
| 11329 | /* XVORI_B */ |
| 11330 | 5861, |
| 11331 | /* XVORN_V */ |
| 11332 | 5864, |
| 11333 | /* XVOR_V */ |
| 11334 | 5867, |
| 11335 | /* XVPACKEV_B */ |
| 11336 | 5870, |
| 11337 | /* XVPACKEV_D */ |
| 11338 | 5873, |
| 11339 | /* XVPACKEV_H */ |
| 11340 | 5876, |
| 11341 | /* XVPACKEV_W */ |
| 11342 | 5879, |
| 11343 | /* XVPACKOD_B */ |
| 11344 | 5882, |
| 11345 | /* XVPACKOD_D */ |
| 11346 | 5885, |
| 11347 | /* XVPACKOD_H */ |
| 11348 | 5888, |
| 11349 | /* XVPACKOD_W */ |
| 11350 | 5891, |
| 11351 | /* XVPCNT_B */ |
| 11352 | 5894, |
| 11353 | /* XVPCNT_D */ |
| 11354 | 5896, |
| 11355 | /* XVPCNT_H */ |
| 11356 | 5898, |
| 11357 | /* XVPCNT_W */ |
| 11358 | 5900, |
| 11359 | /* XVPERMI_D */ |
| 11360 | 5902, |
| 11361 | /* XVPERMI_Q */ |
| 11362 | 5905, |
| 11363 | /* XVPERMI_W */ |
| 11364 | 5909, |
| 11365 | /* XVPERM_W */ |
| 11366 | 5913, |
| 11367 | /* XVPICKEV_B */ |
| 11368 | 5916, |
| 11369 | /* XVPICKEV_D */ |
| 11370 | 5919, |
| 11371 | /* XVPICKEV_H */ |
| 11372 | 5922, |
| 11373 | /* XVPICKEV_W */ |
| 11374 | 5925, |
| 11375 | /* XVPICKOD_B */ |
| 11376 | 5928, |
| 11377 | /* XVPICKOD_D */ |
| 11378 | 5931, |
| 11379 | /* XVPICKOD_H */ |
| 11380 | 5934, |
| 11381 | /* XVPICKOD_W */ |
| 11382 | 5937, |
| 11383 | /* XVPICKVE2GR_D */ |
| 11384 | 5940, |
| 11385 | /* XVPICKVE2GR_DU */ |
| 11386 | 5943, |
| 11387 | /* XVPICKVE2GR_W */ |
| 11388 | 5946, |
| 11389 | /* XVPICKVE2GR_WU */ |
| 11390 | 5949, |
| 11391 | /* XVPICKVE_D */ |
| 11392 | 5952, |
| 11393 | /* XVPICKVE_W */ |
| 11394 | 5955, |
| 11395 | /* XVREPL128VEI_B */ |
| 11396 | 5958, |
| 11397 | /* XVREPL128VEI_D */ |
| 11398 | 5961, |
| 11399 | /* XVREPL128VEI_H */ |
| 11400 | 5964, |
| 11401 | /* XVREPL128VEI_W */ |
| 11402 | 5967, |
| 11403 | /* XVREPLGR2VR_B */ |
| 11404 | 5970, |
| 11405 | /* XVREPLGR2VR_D */ |
| 11406 | 5972, |
| 11407 | /* XVREPLGR2VR_H */ |
| 11408 | 5974, |
| 11409 | /* XVREPLGR2VR_W */ |
| 11410 | 5976, |
| 11411 | /* XVREPLVE0_B */ |
| 11412 | 5978, |
| 11413 | /* XVREPLVE0_D */ |
| 11414 | 5980, |
| 11415 | /* XVREPLVE0_H */ |
| 11416 | 5982, |
| 11417 | /* XVREPLVE0_Q */ |
| 11418 | 5984, |
| 11419 | /* XVREPLVE0_W */ |
| 11420 | 5986, |
| 11421 | /* XVREPLVE_B */ |
| 11422 | 5988, |
| 11423 | /* XVREPLVE_D */ |
| 11424 | 5991, |
| 11425 | /* XVREPLVE_H */ |
| 11426 | 5994, |
| 11427 | /* XVREPLVE_W */ |
| 11428 | 5997, |
| 11429 | /* XVROTRI_B */ |
| 11430 | 6000, |
| 11431 | /* XVROTRI_D */ |
| 11432 | 6003, |
| 11433 | /* XVROTRI_H */ |
| 11434 | 6006, |
| 11435 | /* XVROTRI_W */ |
| 11436 | 6009, |
| 11437 | /* XVROTR_B */ |
| 11438 | 6012, |
| 11439 | /* XVROTR_D */ |
| 11440 | 6015, |
| 11441 | /* XVROTR_H */ |
| 11442 | 6018, |
| 11443 | /* XVROTR_W */ |
| 11444 | 6021, |
| 11445 | /* XVSADD_B */ |
| 11446 | 6024, |
| 11447 | /* XVSADD_BU */ |
| 11448 | 6027, |
| 11449 | /* XVSADD_D */ |
| 11450 | 6030, |
| 11451 | /* XVSADD_DU */ |
| 11452 | 6033, |
| 11453 | /* XVSADD_H */ |
| 11454 | 6036, |
| 11455 | /* XVSADD_HU */ |
| 11456 | 6039, |
| 11457 | /* XVSADD_W */ |
| 11458 | 6042, |
| 11459 | /* XVSADD_WU */ |
| 11460 | 6045, |
| 11461 | /* XVSAT_B */ |
| 11462 | 6048, |
| 11463 | /* XVSAT_BU */ |
| 11464 | 6051, |
| 11465 | /* XVSAT_D */ |
| 11466 | 6054, |
| 11467 | /* XVSAT_DU */ |
| 11468 | 6057, |
| 11469 | /* XVSAT_H */ |
| 11470 | 6060, |
| 11471 | /* XVSAT_HU */ |
| 11472 | 6063, |
| 11473 | /* XVSAT_W */ |
| 11474 | 6066, |
| 11475 | /* XVSAT_WU */ |
| 11476 | 6069, |
| 11477 | /* XVSEQI_B */ |
| 11478 | 6072, |
| 11479 | /* XVSEQI_D */ |
| 11480 | 6075, |
| 11481 | /* XVSEQI_H */ |
| 11482 | 6078, |
| 11483 | /* XVSEQI_W */ |
| 11484 | 6081, |
| 11485 | /* XVSEQ_B */ |
| 11486 | 6084, |
| 11487 | /* XVSEQ_D */ |
| 11488 | 6087, |
| 11489 | /* XVSEQ_H */ |
| 11490 | 6090, |
| 11491 | /* XVSEQ_W */ |
| 11492 | 6093, |
| 11493 | /* XVSETALLNEZ_B */ |
| 11494 | 6096, |
| 11495 | /* XVSETALLNEZ_D */ |
| 11496 | 6098, |
| 11497 | /* XVSETALLNEZ_H */ |
| 11498 | 6100, |
| 11499 | /* XVSETALLNEZ_W */ |
| 11500 | 6102, |
| 11501 | /* XVSETANYEQZ_B */ |
| 11502 | 6104, |
| 11503 | /* XVSETANYEQZ_D */ |
| 11504 | 6106, |
| 11505 | /* XVSETANYEQZ_H */ |
| 11506 | 6108, |
| 11507 | /* XVSETANYEQZ_W */ |
| 11508 | 6110, |
| 11509 | /* XVSETEQZ_V */ |
| 11510 | 6112, |
| 11511 | /* XVSETNEZ_V */ |
| 11512 | 6114, |
| 11513 | /* XVSHUF4I_B */ |
| 11514 | 6116, |
| 11515 | /* XVSHUF4I_D */ |
| 11516 | 6119, |
| 11517 | /* XVSHUF4I_H */ |
| 11518 | 6123, |
| 11519 | /* XVSHUF4I_W */ |
| 11520 | 6126, |
| 11521 | /* XVSHUF_B */ |
| 11522 | 6129, |
| 11523 | /* XVSHUF_D */ |
| 11524 | 6133, |
| 11525 | /* XVSHUF_H */ |
| 11526 | 6137, |
| 11527 | /* XVSHUF_W */ |
| 11528 | 6141, |
| 11529 | /* XVSIGNCOV_B */ |
| 11530 | 6145, |
| 11531 | /* XVSIGNCOV_D */ |
| 11532 | 6148, |
| 11533 | /* XVSIGNCOV_H */ |
| 11534 | 6151, |
| 11535 | /* XVSIGNCOV_W */ |
| 11536 | 6154, |
| 11537 | /* XVSLEI_B */ |
| 11538 | 6157, |
| 11539 | /* XVSLEI_BU */ |
| 11540 | 6160, |
| 11541 | /* XVSLEI_D */ |
| 11542 | 6163, |
| 11543 | /* XVSLEI_DU */ |
| 11544 | 6166, |
| 11545 | /* XVSLEI_H */ |
| 11546 | 6169, |
| 11547 | /* XVSLEI_HU */ |
| 11548 | 6172, |
| 11549 | /* XVSLEI_W */ |
| 11550 | 6175, |
| 11551 | /* XVSLEI_WU */ |
| 11552 | 6178, |
| 11553 | /* XVSLE_B */ |
| 11554 | 6181, |
| 11555 | /* XVSLE_BU */ |
| 11556 | 6184, |
| 11557 | /* XVSLE_D */ |
| 11558 | 6187, |
| 11559 | /* XVSLE_DU */ |
| 11560 | 6190, |
| 11561 | /* XVSLE_H */ |
| 11562 | 6193, |
| 11563 | /* XVSLE_HU */ |
| 11564 | 6196, |
| 11565 | /* XVSLE_W */ |
| 11566 | 6199, |
| 11567 | /* XVSLE_WU */ |
| 11568 | 6202, |
| 11569 | /* XVSLLI_B */ |
| 11570 | 6205, |
| 11571 | /* XVSLLI_D */ |
| 11572 | 6208, |
| 11573 | /* XVSLLI_H */ |
| 11574 | 6211, |
| 11575 | /* XVSLLI_W */ |
| 11576 | 6214, |
| 11577 | /* XVSLLWIL_DU_WU */ |
| 11578 | 6217, |
| 11579 | /* XVSLLWIL_D_W */ |
| 11580 | 6220, |
| 11581 | /* XVSLLWIL_HU_BU */ |
| 11582 | 6223, |
| 11583 | /* XVSLLWIL_H_B */ |
| 11584 | 6226, |
| 11585 | /* XVSLLWIL_WU_HU */ |
| 11586 | 6229, |
| 11587 | /* XVSLLWIL_W_H */ |
| 11588 | 6232, |
| 11589 | /* XVSLL_B */ |
| 11590 | 6235, |
| 11591 | /* XVSLL_D */ |
| 11592 | 6238, |
| 11593 | /* XVSLL_H */ |
| 11594 | 6241, |
| 11595 | /* XVSLL_W */ |
| 11596 | 6244, |
| 11597 | /* XVSLTI_B */ |
| 11598 | 6247, |
| 11599 | /* XVSLTI_BU */ |
| 11600 | 6250, |
| 11601 | /* XVSLTI_D */ |
| 11602 | 6253, |
| 11603 | /* XVSLTI_DU */ |
| 11604 | 6256, |
| 11605 | /* XVSLTI_H */ |
| 11606 | 6259, |
| 11607 | /* XVSLTI_HU */ |
| 11608 | 6262, |
| 11609 | /* XVSLTI_W */ |
| 11610 | 6265, |
| 11611 | /* XVSLTI_WU */ |
| 11612 | 6268, |
| 11613 | /* XVSLT_B */ |
| 11614 | 6271, |
| 11615 | /* XVSLT_BU */ |
| 11616 | 6274, |
| 11617 | /* XVSLT_D */ |
| 11618 | 6277, |
| 11619 | /* XVSLT_DU */ |
| 11620 | 6280, |
| 11621 | /* XVSLT_H */ |
| 11622 | 6283, |
| 11623 | /* XVSLT_HU */ |
| 11624 | 6286, |
| 11625 | /* XVSLT_W */ |
| 11626 | 6289, |
| 11627 | /* XVSLT_WU */ |
| 11628 | 6292, |
| 11629 | /* XVSRAI_B */ |
| 11630 | 6295, |
| 11631 | /* XVSRAI_D */ |
| 11632 | 6298, |
| 11633 | /* XVSRAI_H */ |
| 11634 | 6301, |
| 11635 | /* XVSRAI_W */ |
| 11636 | 6304, |
| 11637 | /* XVSRANI_B_H */ |
| 11638 | 6307, |
| 11639 | /* XVSRANI_D_Q */ |
| 11640 | 6311, |
| 11641 | /* XVSRANI_H_W */ |
| 11642 | 6315, |
| 11643 | /* XVSRANI_W_D */ |
| 11644 | 6319, |
| 11645 | /* XVSRAN_B_H */ |
| 11646 | 6323, |
| 11647 | /* XVSRAN_H_W */ |
| 11648 | 6326, |
| 11649 | /* XVSRAN_W_D */ |
| 11650 | 6329, |
| 11651 | /* XVSRARI_B */ |
| 11652 | 6332, |
| 11653 | /* XVSRARI_D */ |
| 11654 | 6335, |
| 11655 | /* XVSRARI_H */ |
| 11656 | 6338, |
| 11657 | /* XVSRARI_W */ |
| 11658 | 6341, |
| 11659 | /* XVSRARNI_B_H */ |
| 11660 | 6344, |
| 11661 | /* XVSRARNI_D_Q */ |
| 11662 | 6348, |
| 11663 | /* XVSRARNI_H_W */ |
| 11664 | 6352, |
| 11665 | /* XVSRARNI_W_D */ |
| 11666 | 6356, |
| 11667 | /* XVSRARN_B_H */ |
| 11668 | 6360, |
| 11669 | /* XVSRARN_H_W */ |
| 11670 | 6363, |
| 11671 | /* XVSRARN_W_D */ |
| 11672 | 6366, |
| 11673 | /* XVSRAR_B */ |
| 11674 | 6369, |
| 11675 | /* XVSRAR_D */ |
| 11676 | 6372, |
| 11677 | /* XVSRAR_H */ |
| 11678 | 6375, |
| 11679 | /* XVSRAR_W */ |
| 11680 | 6378, |
| 11681 | /* XVSRA_B */ |
| 11682 | 6381, |
| 11683 | /* XVSRA_D */ |
| 11684 | 6384, |
| 11685 | /* XVSRA_H */ |
| 11686 | 6387, |
| 11687 | /* XVSRA_W */ |
| 11688 | 6390, |
| 11689 | /* XVSRLI_B */ |
| 11690 | 6393, |
| 11691 | /* XVSRLI_D */ |
| 11692 | 6396, |
| 11693 | /* XVSRLI_H */ |
| 11694 | 6399, |
| 11695 | /* XVSRLI_W */ |
| 11696 | 6402, |
| 11697 | /* XVSRLNI_B_H */ |
| 11698 | 6405, |
| 11699 | /* XVSRLNI_D_Q */ |
| 11700 | 6409, |
| 11701 | /* XVSRLNI_H_W */ |
| 11702 | 6413, |
| 11703 | /* XVSRLNI_W_D */ |
| 11704 | 6417, |
| 11705 | /* XVSRLN_B_H */ |
| 11706 | 6421, |
| 11707 | /* XVSRLN_H_W */ |
| 11708 | 6424, |
| 11709 | /* XVSRLN_W_D */ |
| 11710 | 6427, |
| 11711 | /* XVSRLRI_B */ |
| 11712 | 6430, |
| 11713 | /* XVSRLRI_D */ |
| 11714 | 6433, |
| 11715 | /* XVSRLRI_H */ |
| 11716 | 6436, |
| 11717 | /* XVSRLRI_W */ |
| 11718 | 6439, |
| 11719 | /* XVSRLRNI_B_H */ |
| 11720 | 6442, |
| 11721 | /* XVSRLRNI_D_Q */ |
| 11722 | 6446, |
| 11723 | /* XVSRLRNI_H_W */ |
| 11724 | 6450, |
| 11725 | /* XVSRLRNI_W_D */ |
| 11726 | 6454, |
| 11727 | /* XVSRLRN_B_H */ |
| 11728 | 6458, |
| 11729 | /* XVSRLRN_H_W */ |
| 11730 | 6461, |
| 11731 | /* XVSRLRN_W_D */ |
| 11732 | 6464, |
| 11733 | /* XVSRLR_B */ |
| 11734 | 6467, |
| 11735 | /* XVSRLR_D */ |
| 11736 | 6470, |
| 11737 | /* XVSRLR_H */ |
| 11738 | 6473, |
| 11739 | /* XVSRLR_W */ |
| 11740 | 6476, |
| 11741 | /* XVSRL_B */ |
| 11742 | 6479, |
| 11743 | /* XVSRL_D */ |
| 11744 | 6482, |
| 11745 | /* XVSRL_H */ |
| 11746 | 6485, |
| 11747 | /* XVSRL_W */ |
| 11748 | 6488, |
| 11749 | /* XVSSRANI_BU_H */ |
| 11750 | 6491, |
| 11751 | /* XVSSRANI_B_H */ |
| 11752 | 6495, |
| 11753 | /* XVSSRANI_DU_Q */ |
| 11754 | 6499, |
| 11755 | /* XVSSRANI_D_Q */ |
| 11756 | 6503, |
| 11757 | /* XVSSRANI_HU_W */ |
| 11758 | 6507, |
| 11759 | /* XVSSRANI_H_W */ |
| 11760 | 6511, |
| 11761 | /* XVSSRANI_WU_D */ |
| 11762 | 6515, |
| 11763 | /* XVSSRANI_W_D */ |
| 11764 | 6519, |
| 11765 | /* XVSSRAN_BU_H */ |
| 11766 | 6523, |
| 11767 | /* XVSSRAN_B_H */ |
| 11768 | 6526, |
| 11769 | /* XVSSRAN_HU_W */ |
| 11770 | 6529, |
| 11771 | /* XVSSRAN_H_W */ |
| 11772 | 6532, |
| 11773 | /* XVSSRAN_WU_D */ |
| 11774 | 6535, |
| 11775 | /* XVSSRAN_W_D */ |
| 11776 | 6538, |
| 11777 | /* XVSSRARNI_BU_H */ |
| 11778 | 6541, |
| 11779 | /* XVSSRARNI_B_H */ |
| 11780 | 6545, |
| 11781 | /* XVSSRARNI_DU_Q */ |
| 11782 | 6549, |
| 11783 | /* XVSSRARNI_D_Q */ |
| 11784 | 6553, |
| 11785 | /* XVSSRARNI_HU_W */ |
| 11786 | 6557, |
| 11787 | /* XVSSRARNI_H_W */ |
| 11788 | 6561, |
| 11789 | /* XVSSRARNI_WU_D */ |
| 11790 | 6565, |
| 11791 | /* XVSSRARNI_W_D */ |
| 11792 | 6569, |
| 11793 | /* XVSSRARN_BU_H */ |
| 11794 | 6573, |
| 11795 | /* XVSSRARN_B_H */ |
| 11796 | 6576, |
| 11797 | /* XVSSRARN_HU_W */ |
| 11798 | 6579, |
| 11799 | /* XVSSRARN_H_W */ |
| 11800 | 6582, |
| 11801 | /* XVSSRARN_WU_D */ |
| 11802 | 6585, |
| 11803 | /* XVSSRARN_W_D */ |
| 11804 | 6588, |
| 11805 | /* XVSSRLNI_BU_H */ |
| 11806 | 6591, |
| 11807 | /* XVSSRLNI_B_H */ |
| 11808 | 6595, |
| 11809 | /* XVSSRLNI_DU_Q */ |
| 11810 | 6599, |
| 11811 | /* XVSSRLNI_D_Q */ |
| 11812 | 6603, |
| 11813 | /* XVSSRLNI_HU_W */ |
| 11814 | 6607, |
| 11815 | /* XVSSRLNI_H_W */ |
| 11816 | 6611, |
| 11817 | /* XVSSRLNI_WU_D */ |
| 11818 | 6615, |
| 11819 | /* XVSSRLNI_W_D */ |
| 11820 | 6619, |
| 11821 | /* XVSSRLN_BU_H */ |
| 11822 | 6623, |
| 11823 | /* XVSSRLN_B_H */ |
| 11824 | 6626, |
| 11825 | /* XVSSRLN_HU_W */ |
| 11826 | 6629, |
| 11827 | /* XVSSRLN_H_W */ |
| 11828 | 6632, |
| 11829 | /* XVSSRLN_WU_D */ |
| 11830 | 6635, |
| 11831 | /* XVSSRLN_W_D */ |
| 11832 | 6638, |
| 11833 | /* XVSSRLRNI_BU_H */ |
| 11834 | 6641, |
| 11835 | /* XVSSRLRNI_B_H */ |
| 11836 | 6645, |
| 11837 | /* XVSSRLRNI_DU_Q */ |
| 11838 | 6649, |
| 11839 | /* XVSSRLRNI_D_Q */ |
| 11840 | 6653, |
| 11841 | /* XVSSRLRNI_HU_W */ |
| 11842 | 6657, |
| 11843 | /* XVSSRLRNI_H_W */ |
| 11844 | 6661, |
| 11845 | /* XVSSRLRNI_WU_D */ |
| 11846 | 6665, |
| 11847 | /* XVSSRLRNI_W_D */ |
| 11848 | 6669, |
| 11849 | /* XVSSRLRN_BU_H */ |
| 11850 | 6673, |
| 11851 | /* XVSSRLRN_B_H */ |
| 11852 | 6676, |
| 11853 | /* XVSSRLRN_HU_W */ |
| 11854 | 6679, |
| 11855 | /* XVSSRLRN_H_W */ |
| 11856 | 6682, |
| 11857 | /* XVSSRLRN_WU_D */ |
| 11858 | 6685, |
| 11859 | /* XVSSRLRN_W_D */ |
| 11860 | 6688, |
| 11861 | /* XVSSUB_B */ |
| 11862 | 6691, |
| 11863 | /* XVSSUB_BU */ |
| 11864 | 6694, |
| 11865 | /* XVSSUB_D */ |
| 11866 | 6697, |
| 11867 | /* XVSSUB_DU */ |
| 11868 | 6700, |
| 11869 | /* XVSSUB_H */ |
| 11870 | 6703, |
| 11871 | /* XVSSUB_HU */ |
| 11872 | 6706, |
| 11873 | /* XVSSUB_W */ |
| 11874 | 6709, |
| 11875 | /* XVSSUB_WU */ |
| 11876 | 6712, |
| 11877 | /* XVST */ |
| 11878 | 6715, |
| 11879 | /* XVSTELM_B */ |
| 11880 | 6718, |
| 11881 | /* XVSTELM_D */ |
| 11882 | 6722, |
| 11883 | /* XVSTELM_H */ |
| 11884 | 6726, |
| 11885 | /* XVSTELM_W */ |
| 11886 | 6730, |
| 11887 | /* XVSTX */ |
| 11888 | 6734, |
| 11889 | /* XVSUBI_BU */ |
| 11890 | 6737, |
| 11891 | /* XVSUBI_DU */ |
| 11892 | 6740, |
| 11893 | /* XVSUBI_HU */ |
| 11894 | 6743, |
| 11895 | /* XVSUBI_WU */ |
| 11896 | 6746, |
| 11897 | /* XVSUBWEV_D_W */ |
| 11898 | 6749, |
| 11899 | /* XVSUBWEV_D_WU */ |
| 11900 | 6752, |
| 11901 | /* XVSUBWEV_H_B */ |
| 11902 | 6755, |
| 11903 | /* XVSUBWEV_H_BU */ |
| 11904 | 6758, |
| 11905 | /* XVSUBWEV_Q_D */ |
| 11906 | 6761, |
| 11907 | /* XVSUBWEV_Q_DU */ |
| 11908 | 6764, |
| 11909 | /* XVSUBWEV_W_H */ |
| 11910 | 6767, |
| 11911 | /* XVSUBWEV_W_HU */ |
| 11912 | 6770, |
| 11913 | /* XVSUBWOD_D_W */ |
| 11914 | 6773, |
| 11915 | /* XVSUBWOD_D_WU */ |
| 11916 | 6776, |
| 11917 | /* XVSUBWOD_H_B */ |
| 11918 | 6779, |
| 11919 | /* XVSUBWOD_H_BU */ |
| 11920 | 6782, |
| 11921 | /* XVSUBWOD_Q_D */ |
| 11922 | 6785, |
| 11923 | /* XVSUBWOD_Q_DU */ |
| 11924 | 6788, |
| 11925 | /* XVSUBWOD_W_H */ |
| 11926 | 6791, |
| 11927 | /* XVSUBWOD_W_HU */ |
| 11928 | 6794, |
| 11929 | /* XVSUB_B */ |
| 11930 | 6797, |
| 11931 | /* XVSUB_D */ |
| 11932 | 6800, |
| 11933 | /* XVSUB_H */ |
| 11934 | 6803, |
| 11935 | /* XVSUB_Q */ |
| 11936 | 6806, |
| 11937 | /* XVSUB_W */ |
| 11938 | 6809, |
| 11939 | /* XVXORI_B */ |
| 11940 | 6812, |
| 11941 | /* XVXOR_V */ |
| 11942 | 6815, |
| 11943 | }; |
| 11944 | |
| 11945 | using namespace OpTypes; |
| 11946 | static const int8_t OpcodeOperandTypes[] = { |
| 11947 | |
| 11948 | /* PHI */ |
| 11949 | -1, |
| 11950 | /* INLINEASM */ |
| 11951 | /* INLINEASM_BR */ |
| 11952 | /* CFI_INSTRUCTION */ |
| 11953 | i32imm, |
| 11954 | /* EH_LABEL */ |
| 11955 | i32imm, |
| 11956 | /* GC_LABEL */ |
| 11957 | i32imm, |
| 11958 | /* ANNOTATION_LABEL */ |
| 11959 | i32imm, |
| 11960 | /* KILL */ |
| 11961 | /* EXTRACT_SUBREG */ |
| 11962 | -1, -1, i32imm, |
| 11963 | /* INSERT_SUBREG */ |
| 11964 | -1, -1, -1, i32imm, |
| 11965 | /* IMPLICIT_DEF */ |
| 11966 | -1, |
| 11967 | /* SUBREG_TO_REG */ |
| 11968 | -1, -1, -1, i32imm, |
| 11969 | /* COPY_TO_REGCLASS */ |
| 11970 | -1, -1, i32imm, |
| 11971 | /* DBG_VALUE */ |
| 11972 | /* DBG_VALUE_LIST */ |
| 11973 | /* DBG_INSTR_REF */ |
| 11974 | /* DBG_PHI */ |
| 11975 | /* DBG_LABEL */ |
| 11976 | -1, |
| 11977 | /* REG_SEQUENCE */ |
| 11978 | -1, -1, |
| 11979 | /* COPY */ |
| 11980 | -1, -1, |
| 11981 | /* BUNDLE */ |
| 11982 | /* LIFETIME_START */ |
| 11983 | i32imm, |
| 11984 | /* LIFETIME_END */ |
| 11985 | i32imm, |
| 11986 | /* PSEUDO_PROBE */ |
| 11987 | i64imm, i64imm, i8imm, i32imm, |
| 11988 | /* ARITH_FENCE */ |
| 11989 | -1, -1, |
| 11990 | /* STACKMAP */ |
| 11991 | i64imm, i32imm, |
| 11992 | /* FENTRY_CALL */ |
| 11993 | /* PATCHPOINT */ |
| 11994 | -1, i64imm, i32imm, -1, i32imm, i32imm, |
| 11995 | /* LOAD_STACK_GUARD */ |
| 11996 | -1, |
| 11997 | /* PREALLOCATED_SETUP */ |
| 11998 | i32imm, |
| 11999 | /* PREALLOCATED_ARG */ |
| 12000 | -1, i32imm, i32imm, |
| 12001 | /* STATEPOINT */ |
| 12002 | /* LOCAL_ESCAPE */ |
| 12003 | -1, i32imm, |
| 12004 | /* FAULTING_OP */ |
| 12005 | -1, |
| 12006 | /* PATCHABLE_OP */ |
| 12007 | /* PATCHABLE_FUNCTION_ENTER */ |
| 12008 | /* PATCHABLE_RET */ |
| 12009 | /* PATCHABLE_FUNCTION_EXIT */ |
| 12010 | /* PATCHABLE_TAIL_CALL */ |
| 12011 | /* PATCHABLE_EVENT_CALL */ |
| 12012 | -1, -1, |
| 12013 | /* PATCHABLE_TYPED_EVENT_CALL */ |
| 12014 | -1, -1, -1, |
| 12015 | /* ICALL_BRANCH_FUNNEL */ |
| 12016 | /* MEMBARRIER */ |
| 12017 | /* JUMP_TABLE_DEBUG_INFO */ |
| 12018 | i64imm, |
| 12019 | /* CONVERGENCECTRL_ENTRY */ |
| 12020 | -1, |
| 12021 | /* CONVERGENCECTRL_ANCHOR */ |
| 12022 | -1, |
| 12023 | /* CONVERGENCECTRL_LOOP */ |
| 12024 | -1, -1, |
| 12025 | /* CONVERGENCECTRL_GLUE */ |
| 12026 | -1, |
| 12027 | /* G_ASSERT_SEXT */ |
| 12028 | type0, type0, untyped_imm_0, |
| 12029 | /* G_ASSERT_ZEXT */ |
| 12030 | type0, type0, untyped_imm_0, |
| 12031 | /* G_ASSERT_ALIGN */ |
| 12032 | type0, type0, untyped_imm_0, |
| 12033 | /* G_ADD */ |
| 12034 | type0, type0, type0, |
| 12035 | /* G_SUB */ |
| 12036 | type0, type0, type0, |
| 12037 | /* G_MUL */ |
| 12038 | type0, type0, type0, |
| 12039 | /* G_SDIV */ |
| 12040 | type0, type0, type0, |
| 12041 | /* G_UDIV */ |
| 12042 | type0, type0, type0, |
| 12043 | /* G_SREM */ |
| 12044 | type0, type0, type0, |
| 12045 | /* G_UREM */ |
| 12046 | type0, type0, type0, |
| 12047 | /* G_SDIVREM */ |
| 12048 | type0, type0, type0, type0, |
| 12049 | /* G_UDIVREM */ |
| 12050 | type0, type0, type0, type0, |
| 12051 | /* G_AND */ |
| 12052 | type0, type0, type0, |
| 12053 | /* G_OR */ |
| 12054 | type0, type0, type0, |
| 12055 | /* G_XOR */ |
| 12056 | type0, type0, type0, |
| 12057 | /* G_IMPLICIT_DEF */ |
| 12058 | type0, |
| 12059 | /* G_PHI */ |
| 12060 | type0, |
| 12061 | /* G_FRAME_INDEX */ |
| 12062 | type0, -1, |
| 12063 | /* G_GLOBAL_VALUE */ |
| 12064 | type0, -1, |
| 12065 | /* G_PTRAUTH_GLOBAL_VALUE */ |
| 12066 | type0, -1, i32imm, type1, i64imm, |
| 12067 | /* G_CONSTANT_POOL */ |
| 12068 | type0, -1, |
| 12069 | /* G_EXTRACT */ |
| 12070 | type0, type1, untyped_imm_0, |
| 12071 | /* G_UNMERGE_VALUES */ |
| 12072 | type0, type1, |
| 12073 | /* G_INSERT */ |
| 12074 | type0, type0, type1, untyped_imm_0, |
| 12075 | /* G_MERGE_VALUES */ |
| 12076 | type0, type1, |
| 12077 | /* G_BUILD_VECTOR */ |
| 12078 | type0, type1, |
| 12079 | /* G_BUILD_VECTOR_TRUNC */ |
| 12080 | type0, type1, |
| 12081 | /* G_CONCAT_VECTORS */ |
| 12082 | type0, type1, |
| 12083 | /* G_PTRTOINT */ |
| 12084 | type0, type1, |
| 12085 | /* G_INTTOPTR */ |
| 12086 | type0, type1, |
| 12087 | /* G_BITCAST */ |
| 12088 | type0, type1, |
| 12089 | /* G_FREEZE */ |
| 12090 | type0, type0, |
| 12091 | /* G_CONSTANT_FOLD_BARRIER */ |
| 12092 | type0, type0, |
| 12093 | /* G_INTRINSIC_FPTRUNC_ROUND */ |
| 12094 | type0, type1, i32imm, |
| 12095 | /* G_INTRINSIC_TRUNC */ |
| 12096 | type0, type0, |
| 12097 | /* G_INTRINSIC_ROUND */ |
| 12098 | type0, type0, |
| 12099 | /* G_INTRINSIC_LRINT */ |
| 12100 | type0, type1, |
| 12101 | /* G_INTRINSIC_LLRINT */ |
| 12102 | type0, type1, |
| 12103 | /* G_INTRINSIC_ROUNDEVEN */ |
| 12104 | type0, type0, |
| 12105 | /* G_READCYCLECOUNTER */ |
| 12106 | type0, |
| 12107 | /* G_READSTEADYCOUNTER */ |
| 12108 | type0, |
| 12109 | /* G_LOAD */ |
| 12110 | type0, ptype1, |
| 12111 | /* G_SEXTLOAD */ |
| 12112 | type0, ptype1, |
| 12113 | /* G_ZEXTLOAD */ |
| 12114 | type0, ptype1, |
| 12115 | /* G_INDEXED_LOAD */ |
| 12116 | type0, ptype1, ptype1, type2, -1, |
| 12117 | /* G_INDEXED_SEXTLOAD */ |
| 12118 | type0, ptype1, ptype1, type2, -1, |
| 12119 | /* G_INDEXED_ZEXTLOAD */ |
| 12120 | type0, ptype1, ptype1, type2, -1, |
| 12121 | /* G_STORE */ |
| 12122 | type0, ptype1, |
| 12123 | /* G_INDEXED_STORE */ |
| 12124 | ptype0, type1, ptype0, ptype2, -1, |
| 12125 | /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
| 12126 | type0, type1, type2, type0, type0, |
| 12127 | /* G_ATOMIC_CMPXCHG */ |
| 12128 | type0, ptype1, type0, type0, |
| 12129 | /* G_ATOMICRMW_XCHG */ |
| 12130 | type0, ptype1, type0, |
| 12131 | /* G_ATOMICRMW_ADD */ |
| 12132 | type0, ptype1, type0, |
| 12133 | /* G_ATOMICRMW_SUB */ |
| 12134 | type0, ptype1, type0, |
| 12135 | /* G_ATOMICRMW_AND */ |
| 12136 | type0, ptype1, type0, |
| 12137 | /* G_ATOMICRMW_NAND */ |
| 12138 | type0, ptype1, type0, |
| 12139 | /* G_ATOMICRMW_OR */ |
| 12140 | type0, ptype1, type0, |
| 12141 | /* G_ATOMICRMW_XOR */ |
| 12142 | type0, ptype1, type0, |
| 12143 | /* G_ATOMICRMW_MAX */ |
| 12144 | type0, ptype1, type0, |
| 12145 | /* G_ATOMICRMW_MIN */ |
| 12146 | type0, ptype1, type0, |
| 12147 | /* G_ATOMICRMW_UMAX */ |
| 12148 | type0, ptype1, type0, |
| 12149 | /* G_ATOMICRMW_UMIN */ |
| 12150 | type0, ptype1, type0, |
| 12151 | /* G_ATOMICRMW_FADD */ |
| 12152 | type0, ptype1, type0, |
| 12153 | /* G_ATOMICRMW_FSUB */ |
| 12154 | type0, ptype1, type0, |
| 12155 | /* G_ATOMICRMW_FMAX */ |
| 12156 | type0, ptype1, type0, |
| 12157 | /* G_ATOMICRMW_FMIN */ |
| 12158 | type0, ptype1, type0, |
| 12159 | /* G_ATOMICRMW_UINC_WRAP */ |
| 12160 | type0, ptype1, type0, |
| 12161 | /* G_ATOMICRMW_UDEC_WRAP */ |
| 12162 | type0, ptype1, type0, |
| 12163 | /* G_FENCE */ |
| 12164 | i32imm, i32imm, |
| 12165 | /* G_PREFETCH */ |
| 12166 | ptype0, i32imm, i32imm, i32imm, |
| 12167 | /* G_BRCOND */ |
| 12168 | type0, -1, |
| 12169 | /* G_BRINDIRECT */ |
| 12170 | type0, |
| 12171 | /* G_INVOKE_REGION_START */ |
| 12172 | /* G_INTRINSIC */ |
| 12173 | -1, |
| 12174 | /* G_INTRINSIC_W_SIDE_EFFECTS */ |
| 12175 | -1, |
| 12176 | /* G_INTRINSIC_CONVERGENT */ |
| 12177 | -1, |
| 12178 | /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ |
| 12179 | -1, |
| 12180 | /* G_ANYEXT */ |
| 12181 | type0, type1, |
| 12182 | /* G_TRUNC */ |
| 12183 | type0, type1, |
| 12184 | /* G_CONSTANT */ |
| 12185 | type0, -1, |
| 12186 | /* G_FCONSTANT */ |
| 12187 | type0, -1, |
| 12188 | /* G_VASTART */ |
| 12189 | type0, |
| 12190 | /* G_VAARG */ |
| 12191 | type0, type1, -1, |
| 12192 | /* G_SEXT */ |
| 12193 | type0, type1, |
| 12194 | /* G_SEXT_INREG */ |
| 12195 | type0, type0, untyped_imm_0, |
| 12196 | /* G_ZEXT */ |
| 12197 | type0, type1, |
| 12198 | /* G_SHL */ |
| 12199 | type0, type0, type1, |
| 12200 | /* G_LSHR */ |
| 12201 | type0, type0, type1, |
| 12202 | /* G_ASHR */ |
| 12203 | type0, type0, type1, |
| 12204 | /* G_FSHL */ |
| 12205 | type0, type0, type0, type1, |
| 12206 | /* G_FSHR */ |
| 12207 | type0, type0, type0, type1, |
| 12208 | /* G_ROTR */ |
| 12209 | type0, type0, type1, |
| 12210 | /* G_ROTL */ |
| 12211 | type0, type0, type1, |
| 12212 | /* G_ICMP */ |
| 12213 | type0, -1, type1, type1, |
| 12214 | /* G_FCMP */ |
| 12215 | type0, -1, type1, type1, |
| 12216 | /* G_SCMP */ |
| 12217 | type0, type1, type1, |
| 12218 | /* G_UCMP */ |
| 12219 | type0, type1, type1, |
| 12220 | /* G_SELECT */ |
| 12221 | type0, type1, type0, type0, |
| 12222 | /* G_UADDO */ |
| 12223 | type0, type1, type0, type0, |
| 12224 | /* G_UADDE */ |
| 12225 | type0, type1, type0, type0, type1, |
| 12226 | /* G_USUBO */ |
| 12227 | type0, type1, type0, type0, |
| 12228 | /* G_USUBE */ |
| 12229 | type0, type1, type0, type0, type1, |
| 12230 | /* G_SADDO */ |
| 12231 | type0, type1, type0, type0, |
| 12232 | /* G_SADDE */ |
| 12233 | type0, type1, type0, type0, type1, |
| 12234 | /* G_SSUBO */ |
| 12235 | type0, type1, type0, type0, |
| 12236 | /* G_SSUBE */ |
| 12237 | type0, type1, type0, type0, type1, |
| 12238 | /* G_UMULO */ |
| 12239 | type0, type1, type0, type0, |
| 12240 | /* G_SMULO */ |
| 12241 | type0, type1, type0, type0, |
| 12242 | /* G_UMULH */ |
| 12243 | type0, type0, type0, |
| 12244 | /* G_SMULH */ |
| 12245 | type0, type0, type0, |
| 12246 | /* G_UADDSAT */ |
| 12247 | type0, type0, type0, |
| 12248 | /* G_SADDSAT */ |
| 12249 | type0, type0, type0, |
| 12250 | /* G_USUBSAT */ |
| 12251 | type0, type0, type0, |
| 12252 | /* G_SSUBSAT */ |
| 12253 | type0, type0, type0, |
| 12254 | /* G_USHLSAT */ |
| 12255 | type0, type0, type1, |
| 12256 | /* G_SSHLSAT */ |
| 12257 | type0, type0, type1, |
| 12258 | /* G_SMULFIX */ |
| 12259 | type0, type0, type0, untyped_imm_0, |
| 12260 | /* G_UMULFIX */ |
| 12261 | type0, type0, type0, untyped_imm_0, |
| 12262 | /* G_SMULFIXSAT */ |
| 12263 | type0, type0, type0, untyped_imm_0, |
| 12264 | /* G_UMULFIXSAT */ |
| 12265 | type0, type0, type0, untyped_imm_0, |
| 12266 | /* G_SDIVFIX */ |
| 12267 | type0, type0, type0, untyped_imm_0, |
| 12268 | /* G_UDIVFIX */ |
| 12269 | type0, type0, type0, untyped_imm_0, |
| 12270 | /* G_SDIVFIXSAT */ |
| 12271 | type0, type0, type0, untyped_imm_0, |
| 12272 | /* G_UDIVFIXSAT */ |
| 12273 | type0, type0, type0, untyped_imm_0, |
| 12274 | /* G_FADD */ |
| 12275 | type0, type0, type0, |
| 12276 | /* G_FSUB */ |
| 12277 | type0, type0, type0, |
| 12278 | /* G_FMUL */ |
| 12279 | type0, type0, type0, |
| 12280 | /* G_FMA */ |
| 12281 | type0, type0, type0, type0, |
| 12282 | /* G_FMAD */ |
| 12283 | type0, type0, type0, type0, |
| 12284 | /* G_FDIV */ |
| 12285 | type0, type0, type0, |
| 12286 | /* G_FREM */ |
| 12287 | type0, type0, type0, |
| 12288 | /* G_FPOW */ |
| 12289 | type0, type0, type0, |
| 12290 | /* G_FPOWI */ |
| 12291 | type0, type0, type1, |
| 12292 | /* G_FEXP */ |
| 12293 | type0, type0, |
| 12294 | /* G_FEXP2 */ |
| 12295 | type0, type0, |
| 12296 | /* G_FEXP10 */ |
| 12297 | type0, type0, |
| 12298 | /* G_FLOG */ |
| 12299 | type0, type0, |
| 12300 | /* G_FLOG2 */ |
| 12301 | type0, type0, |
| 12302 | /* G_FLOG10 */ |
| 12303 | type0, type0, |
| 12304 | /* G_FLDEXP */ |
| 12305 | type0, type0, type1, |
| 12306 | /* G_FFREXP */ |
| 12307 | type0, type1, type0, |
| 12308 | /* G_FNEG */ |
| 12309 | type0, type0, |
| 12310 | /* G_FPEXT */ |
| 12311 | type0, type1, |
| 12312 | /* G_FPTRUNC */ |
| 12313 | type0, type1, |
| 12314 | /* G_FPTOSI */ |
| 12315 | type0, type1, |
| 12316 | /* G_FPTOUI */ |
| 12317 | type0, type1, |
| 12318 | /* G_SITOFP */ |
| 12319 | type0, type1, |
| 12320 | /* G_UITOFP */ |
| 12321 | type0, type1, |
| 12322 | /* G_FABS */ |
| 12323 | type0, type0, |
| 12324 | /* G_FCOPYSIGN */ |
| 12325 | type0, type0, type1, |
| 12326 | /* G_IS_FPCLASS */ |
| 12327 | type0, type1, -1, |
| 12328 | /* G_FCANONICALIZE */ |
| 12329 | type0, type0, |
| 12330 | /* G_FMINNUM */ |
| 12331 | type0, type0, type0, |
| 12332 | /* G_FMAXNUM */ |
| 12333 | type0, type0, type0, |
| 12334 | /* G_FMINNUM_IEEE */ |
| 12335 | type0, type0, type0, |
| 12336 | /* G_FMAXNUM_IEEE */ |
| 12337 | type0, type0, type0, |
| 12338 | /* G_FMINIMUM */ |
| 12339 | type0, type0, type0, |
| 12340 | /* G_FMAXIMUM */ |
| 12341 | type0, type0, type0, |
| 12342 | /* G_GET_FPENV */ |
| 12343 | type0, |
| 12344 | /* G_SET_FPENV */ |
| 12345 | type0, |
| 12346 | /* G_RESET_FPENV */ |
| 12347 | /* G_GET_FPMODE */ |
| 12348 | type0, |
| 12349 | /* G_SET_FPMODE */ |
| 12350 | type0, |
| 12351 | /* G_RESET_FPMODE */ |
| 12352 | /* G_PTR_ADD */ |
| 12353 | ptype0, ptype0, type1, |
| 12354 | /* G_PTRMASK */ |
| 12355 | ptype0, ptype0, type1, |
| 12356 | /* G_SMIN */ |
| 12357 | type0, type0, type0, |
| 12358 | /* G_SMAX */ |
| 12359 | type0, type0, type0, |
| 12360 | /* G_UMIN */ |
| 12361 | type0, type0, type0, |
| 12362 | /* G_UMAX */ |
| 12363 | type0, type0, type0, |
| 12364 | /* G_ABS */ |
| 12365 | type0, type0, |
| 12366 | /* G_LROUND */ |
| 12367 | type0, type1, |
| 12368 | /* G_LLROUND */ |
| 12369 | type0, type1, |
| 12370 | /* G_BR */ |
| 12371 | -1, |
| 12372 | /* G_BRJT */ |
| 12373 | ptype0, -1, type1, |
| 12374 | /* G_VSCALE */ |
| 12375 | type0, -1, |
| 12376 | /* G_INSERT_SUBVECTOR */ |
| 12377 | type0, type0, type1, untyped_imm_0, |
| 12378 | /* G_EXTRACT_SUBVECTOR */ |
| 12379 | type0, type0, untyped_imm_0, |
| 12380 | /* G_INSERT_VECTOR_ELT */ |
| 12381 | type0, type0, type1, type2, |
| 12382 | /* G_EXTRACT_VECTOR_ELT */ |
| 12383 | type0, type1, type2, |
| 12384 | /* G_SHUFFLE_VECTOR */ |
| 12385 | type0, type1, type1, -1, |
| 12386 | /* G_SPLAT_VECTOR */ |
| 12387 | type0, type1, |
| 12388 | /* G_VECTOR_COMPRESS */ |
| 12389 | type0, type0, type1, type0, |
| 12390 | /* G_CTTZ */ |
| 12391 | type0, type1, |
| 12392 | /* G_CTTZ_ZERO_UNDEF */ |
| 12393 | type0, type1, |
| 12394 | /* G_CTLZ */ |
| 12395 | type0, type1, |
| 12396 | /* G_CTLZ_ZERO_UNDEF */ |
| 12397 | type0, type1, |
| 12398 | /* G_CTPOP */ |
| 12399 | type0, type1, |
| 12400 | /* G_BSWAP */ |
| 12401 | type0, type0, |
| 12402 | /* G_BITREVERSE */ |
| 12403 | type0, type0, |
| 12404 | /* G_FCEIL */ |
| 12405 | type0, type0, |
| 12406 | /* G_FCOS */ |
| 12407 | type0, type0, |
| 12408 | /* G_FSIN */ |
| 12409 | type0, type0, |
| 12410 | /* G_FTAN */ |
| 12411 | type0, type0, |
| 12412 | /* G_FACOS */ |
| 12413 | type0, type0, |
| 12414 | /* G_FASIN */ |
| 12415 | type0, type0, |
| 12416 | /* G_FATAN */ |
| 12417 | type0, type0, |
| 12418 | /* G_FCOSH */ |
| 12419 | type0, type0, |
| 12420 | /* G_FSINH */ |
| 12421 | type0, type0, |
| 12422 | /* G_FTANH */ |
| 12423 | type0, type0, |
| 12424 | /* G_FSQRT */ |
| 12425 | type0, type0, |
| 12426 | /* G_FFLOOR */ |
| 12427 | type0, type0, |
| 12428 | /* G_FRINT */ |
| 12429 | type0, type0, |
| 12430 | /* G_FNEARBYINT */ |
| 12431 | type0, type0, |
| 12432 | /* G_ADDRSPACE_CAST */ |
| 12433 | type0, type1, |
| 12434 | /* G_BLOCK_ADDR */ |
| 12435 | type0, -1, |
| 12436 | /* G_JUMP_TABLE */ |
| 12437 | type0, -1, |
| 12438 | /* G_DYN_STACKALLOC */ |
| 12439 | ptype0, type1, i32imm, |
| 12440 | /* G_STACKSAVE */ |
| 12441 | ptype0, |
| 12442 | /* G_STACKRESTORE */ |
| 12443 | ptype0, |
| 12444 | /* G_STRICT_FADD */ |
| 12445 | type0, type0, type0, |
| 12446 | /* G_STRICT_FSUB */ |
| 12447 | type0, type0, type0, |
| 12448 | /* G_STRICT_FMUL */ |
| 12449 | type0, type0, type0, |
| 12450 | /* G_STRICT_FDIV */ |
| 12451 | type0, type0, type0, |
| 12452 | /* G_STRICT_FREM */ |
| 12453 | type0, type0, type0, |
| 12454 | /* G_STRICT_FMA */ |
| 12455 | type0, type0, type0, type0, |
| 12456 | /* G_STRICT_FSQRT */ |
| 12457 | type0, type0, |
| 12458 | /* G_STRICT_FLDEXP */ |
| 12459 | type0, type0, type1, |
| 12460 | /* G_READ_REGISTER */ |
| 12461 | type0, -1, |
| 12462 | /* G_WRITE_REGISTER */ |
| 12463 | -1, type0, |
| 12464 | /* G_MEMCPY */ |
| 12465 | ptype0, ptype1, type2, untyped_imm_0, |
| 12466 | /* G_MEMCPY_INLINE */ |
| 12467 | ptype0, ptype1, type2, |
| 12468 | /* G_MEMMOVE */ |
| 12469 | ptype0, ptype1, type2, untyped_imm_0, |
| 12470 | /* G_MEMSET */ |
| 12471 | ptype0, type1, type2, untyped_imm_0, |
| 12472 | /* G_BZERO */ |
| 12473 | ptype0, type1, untyped_imm_0, |
| 12474 | /* G_TRAP */ |
| 12475 | /* G_DEBUGTRAP */ |
| 12476 | /* G_UBSANTRAP */ |
| 12477 | i8imm, |
| 12478 | /* G_VECREDUCE_SEQ_FADD */ |
| 12479 | type0, type1, type2, |
| 12480 | /* G_VECREDUCE_SEQ_FMUL */ |
| 12481 | type0, type1, type2, |
| 12482 | /* G_VECREDUCE_FADD */ |
| 12483 | type0, type1, |
| 12484 | /* G_VECREDUCE_FMUL */ |
| 12485 | type0, type1, |
| 12486 | /* G_VECREDUCE_FMAX */ |
| 12487 | type0, type1, |
| 12488 | /* G_VECREDUCE_FMIN */ |
| 12489 | type0, type1, |
| 12490 | /* G_VECREDUCE_FMAXIMUM */ |
| 12491 | type0, type1, |
| 12492 | /* G_VECREDUCE_FMINIMUM */ |
| 12493 | type0, type1, |
| 12494 | /* G_VECREDUCE_ADD */ |
| 12495 | type0, type1, |
| 12496 | /* G_VECREDUCE_MUL */ |
| 12497 | type0, type1, |
| 12498 | /* G_VECREDUCE_AND */ |
| 12499 | type0, type1, |
| 12500 | /* G_VECREDUCE_OR */ |
| 12501 | type0, type1, |
| 12502 | /* G_VECREDUCE_XOR */ |
| 12503 | type0, type1, |
| 12504 | /* G_VECREDUCE_SMAX */ |
| 12505 | type0, type1, |
| 12506 | /* G_VECREDUCE_SMIN */ |
| 12507 | type0, type1, |
| 12508 | /* G_VECREDUCE_UMAX */ |
| 12509 | type0, type1, |
| 12510 | /* G_VECREDUCE_UMIN */ |
| 12511 | type0, type1, |
| 12512 | /* G_SBFX */ |
| 12513 | type0, type0, type1, type1, |
| 12514 | /* G_UBFX */ |
| 12515 | type0, type0, type1, type1, |
| 12516 | /* ADJCALLSTACKDOWN */ |
| 12517 | i32imm, i32imm, |
| 12518 | /* ADJCALLSTACKUP */ |
| 12519 | i32imm, i32imm, |
| 12520 | /* PseudoAddTPRel_D */ |
| 12521 | GPR, GPR, GPR, tprel_add_symbol, |
| 12522 | /* PseudoAddTPRel_W */ |
| 12523 | GPR, GPR, GPR, tprel_add_symbol, |
| 12524 | /* PseudoAtomicLoadAdd32 */ |
| 12525 | GPR, GPR, GPR, GPR, grlenimm, |
| 12526 | /* PseudoAtomicLoadAnd32 */ |
| 12527 | GPR, GPR, GPR, GPR, grlenimm, |
| 12528 | /* PseudoAtomicLoadNand32 */ |
| 12529 | GPR, GPR, GPR, GPR, grlenimm, |
| 12530 | /* PseudoAtomicLoadNand64 */ |
| 12531 | GPR, GPR, GPR, GPR, grlenimm, |
| 12532 | /* PseudoAtomicLoadOr32 */ |
| 12533 | GPR, GPR, GPR, GPR, grlenimm, |
| 12534 | /* PseudoAtomicLoadSub32 */ |
| 12535 | GPR, GPR, GPR, GPR, grlenimm, |
| 12536 | /* PseudoAtomicLoadXor32 */ |
| 12537 | GPR, GPR, GPR, GPR, grlenimm, |
| 12538 | /* PseudoAtomicStoreD */ |
| 12539 | GPR, GPR, GPR, |
| 12540 | /* PseudoAtomicStoreW */ |
| 12541 | GPR, GPR, GPR, |
| 12542 | /* PseudoAtomicSwap32 */ |
| 12543 | GPR, GPR, GPR, GPR, grlenimm, |
| 12544 | /* PseudoBR */ |
| 12545 | simm26_b, |
| 12546 | /* PseudoBRIND */ |
| 12547 | GPR, simm16_lsl2, |
| 12548 | /* PseudoB_TAIL */ |
| 12549 | simm26_b, |
| 12550 | /* PseudoCALL */ |
| 12551 | bare_symbol, |
| 12552 | /* PseudoCALL36 */ |
| 12553 | bare_symbol, |
| 12554 | /* PseudoCALLIndirect */ |
| 12555 | GPR, |
| 12556 | /* PseudoCALL_LARGE */ |
| 12557 | bare_symbol, |
| 12558 | /* PseudoCALL_MEDIUM */ |
| 12559 | bare_symbol, |
| 12560 | /* PseudoCmpXchg32 */ |
| 12561 | GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12562 | /* PseudoCmpXchg64 */ |
| 12563 | GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12564 | /* PseudoCopyCFR */ |
| 12565 | CFR, CFR, |
| 12566 | /* PseudoDESC_CALL */ |
| 12567 | GPR, GPR, simm16_lsl2, |
| 12568 | /* PseudoJIRL_CALL */ |
| 12569 | GPR, simm16_lsl2, |
| 12570 | /* PseudoJIRL_TAIL */ |
| 12571 | GPR, simm16_lsl2, |
| 12572 | /* PseudoLA_ABS */ |
| 12573 | GPR, bare_symbol, |
| 12574 | /* PseudoLA_ABS_LARGE */ |
| 12575 | GPR, GPR, bare_symbol, |
| 12576 | /* PseudoLA_GOT */ |
| 12577 | GPR, bare_symbol, |
| 12578 | /* PseudoLA_GOT_LARGE */ |
| 12579 | GPR, GPR, bare_symbol, |
| 12580 | /* PseudoLA_PCREL */ |
| 12581 | GPR, bare_symbol, |
| 12582 | /* PseudoLA_PCREL_LARGE */ |
| 12583 | GPR, GPR, bare_symbol, |
| 12584 | /* PseudoLA_TLS_DESC_ABS */ |
| 12585 | GPR, bare_symbol, |
| 12586 | /* PseudoLA_TLS_DESC_ABS_LARGE */ |
| 12587 | GPR, GPR, bare_symbol, |
| 12588 | /* PseudoLA_TLS_DESC_PC */ |
| 12589 | GPR, bare_symbol, |
| 12590 | /* PseudoLA_TLS_DESC_PC_LARGE */ |
| 12591 | GPR, GPR, bare_symbol, |
| 12592 | /* PseudoLA_TLS_GD */ |
| 12593 | GPR, bare_symbol, |
| 12594 | /* PseudoLA_TLS_GD_LARGE */ |
| 12595 | GPR, GPR, bare_symbol, |
| 12596 | /* PseudoLA_TLS_IE */ |
| 12597 | GPR, bare_symbol, |
| 12598 | /* PseudoLA_TLS_IE_LARGE */ |
| 12599 | GPR, GPR, bare_symbol, |
| 12600 | /* PseudoLA_TLS_LD */ |
| 12601 | GPR, bare_symbol, |
| 12602 | /* PseudoLA_TLS_LD_LARGE */ |
| 12603 | GPR, GPR, bare_symbol, |
| 12604 | /* PseudoLA_TLS_LE */ |
| 12605 | GPR, bare_symbol, |
| 12606 | /* PseudoLD_CFR */ |
| 12607 | CFR, GPR, grlenimm, |
| 12608 | /* PseudoLI_D */ |
| 12609 | GPR, imm64, |
| 12610 | /* PseudoLI_W */ |
| 12611 | GPR, imm32, |
| 12612 | /* PseudoMaskedAtomicLoadAdd32 */ |
| 12613 | GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12614 | /* PseudoMaskedAtomicLoadMax32 */ |
| 12615 | GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, |
| 12616 | /* PseudoMaskedAtomicLoadMin32 */ |
| 12617 | GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, |
| 12618 | /* PseudoMaskedAtomicLoadNand32 */ |
| 12619 | GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12620 | /* PseudoMaskedAtomicLoadSub32 */ |
| 12621 | GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12622 | /* PseudoMaskedAtomicLoadUMax32 */ |
| 12623 | GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12624 | /* PseudoMaskedAtomicLoadUMin32 */ |
| 12625 | GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12626 | /* PseudoMaskedAtomicSwap32 */ |
| 12627 | GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12628 | /* PseudoMaskedCmpXchg32 */ |
| 12629 | GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, |
| 12630 | /* PseudoRET */ |
| 12631 | /* PseudoST_CFR */ |
| 12632 | CFR, GPR, grlenimm, |
| 12633 | /* PseudoTAIL */ |
| 12634 | bare_symbol, |
| 12635 | /* PseudoTAIL36 */ |
| 12636 | GPR, bare_symbol, |
| 12637 | /* PseudoTAILIndirect */ |
| 12638 | GPRT, |
| 12639 | /* PseudoTAIL_LARGE */ |
| 12640 | bare_symbol, |
| 12641 | /* PseudoTAIL_MEDIUM */ |
| 12642 | bare_symbol, |
| 12643 | /* PseudoUNIMP */ |
| 12644 | /* PseudoVBNZ */ |
| 12645 | GPR, LSX128, |
| 12646 | /* PseudoVBNZ_B */ |
| 12647 | GPR, LSX128, |
| 12648 | /* PseudoVBNZ_D */ |
| 12649 | GPR, LSX128, |
| 12650 | /* PseudoVBNZ_H */ |
| 12651 | GPR, LSX128, |
| 12652 | /* PseudoVBNZ_W */ |
| 12653 | GPR, LSX128, |
| 12654 | /* PseudoVBZ */ |
| 12655 | GPR, LSX128, |
| 12656 | /* PseudoVBZ_B */ |
| 12657 | GPR, LSX128, |
| 12658 | /* PseudoVBZ_D */ |
| 12659 | GPR, LSX128, |
| 12660 | /* PseudoVBZ_H */ |
| 12661 | GPR, LSX128, |
| 12662 | /* PseudoVBZ_W */ |
| 12663 | GPR, LSX128, |
| 12664 | /* PseudoVREPLI_B */ |
| 12665 | LSX128, simm10, |
| 12666 | /* PseudoVREPLI_D */ |
| 12667 | LSX128, simm10, |
| 12668 | /* PseudoVREPLI_H */ |
| 12669 | LSX128, simm10, |
| 12670 | /* PseudoVREPLI_W */ |
| 12671 | LSX128, simm10, |
| 12672 | /* PseudoXVBNZ */ |
| 12673 | GPR, LASX256, |
| 12674 | /* PseudoXVBNZ_B */ |
| 12675 | GPR, LASX256, |
| 12676 | /* PseudoXVBNZ_D */ |
| 12677 | GPR, LASX256, |
| 12678 | /* PseudoXVBNZ_H */ |
| 12679 | GPR, LASX256, |
| 12680 | /* PseudoXVBNZ_W */ |
| 12681 | GPR, LASX256, |
| 12682 | /* PseudoXVBZ */ |
| 12683 | GPR, LASX256, |
| 12684 | /* PseudoXVBZ_B */ |
| 12685 | GPR, LASX256, |
| 12686 | /* PseudoXVBZ_D */ |
| 12687 | GPR, LASX256, |
| 12688 | /* PseudoXVBZ_H */ |
| 12689 | GPR, LASX256, |
| 12690 | /* PseudoXVBZ_W */ |
| 12691 | GPR, LASX256, |
| 12692 | /* PseudoXVINSGR2VR_B */ |
| 12693 | LASX256, LASX256, GPR, uimm5, |
| 12694 | /* PseudoXVINSGR2VR_H */ |
| 12695 | LASX256, LASX256, GPR, uimm4, |
| 12696 | /* PseudoXVREPLI_B */ |
| 12697 | LASX256, simm10, |
| 12698 | /* PseudoXVREPLI_D */ |
| 12699 | LASX256, simm10, |
| 12700 | /* PseudoXVREPLI_H */ |
| 12701 | LASX256, simm10, |
| 12702 | /* PseudoXVREPLI_W */ |
| 12703 | LASX256, simm10, |
| 12704 | /* RDFCSR */ |
| 12705 | GPR, uimm2, |
| 12706 | /* WRFCSR */ |
| 12707 | uimm2, GPR, |
| 12708 | /* ADC_B */ |
| 12709 | GPR, GPR, GPR, |
| 12710 | /* ADC_D */ |
| 12711 | GPR, GPR, GPR, |
| 12712 | /* ADC_H */ |
| 12713 | GPR, GPR, GPR, |
| 12714 | /* ADC_W */ |
| 12715 | GPR, GPR, GPR, |
| 12716 | /* ADDI_D */ |
| 12717 | GPR, GPR, simm12_addlike, |
| 12718 | /* ADDI_W */ |
| 12719 | GPR, GPR, simm12_addlike, |
| 12720 | /* ADDU12I_D */ |
| 12721 | GPR, GPR, simm5, |
| 12722 | /* ADDU12I_W */ |
| 12723 | GPR, GPR, simm5, |
| 12724 | /* ADDU16I_D */ |
| 12725 | GPR, GPR, simm16, |
| 12726 | /* ADD_D */ |
| 12727 | GPR, GPR, GPR, |
| 12728 | /* ADD_W */ |
| 12729 | GPR, GPR, GPR, |
| 12730 | /* ALSL_D */ |
| 12731 | GPR, GPR, GPR, uimm2_plus1, |
| 12732 | /* ALSL_W */ |
| 12733 | GPR, GPR, GPR, uimm2_plus1, |
| 12734 | /* ALSL_WU */ |
| 12735 | GPR, GPR, GPR, uimm2_plus1, |
| 12736 | /* AMADD_B */ |
| 12737 | GPR, GPR, GPRMemAtomic, |
| 12738 | /* AMADD_D */ |
| 12739 | GPR, GPR, GPRMemAtomic, |
| 12740 | /* AMADD_H */ |
| 12741 | GPR, GPR, GPRMemAtomic, |
| 12742 | /* AMADD_W */ |
| 12743 | GPR, GPR, GPRMemAtomic, |
| 12744 | /* AMADD__DB_B */ |
| 12745 | GPR, GPR, GPRMemAtomic, |
| 12746 | /* AMADD__DB_D */ |
| 12747 | GPR, GPR, GPRMemAtomic, |
| 12748 | /* AMADD__DB_H */ |
| 12749 | GPR, GPR, GPRMemAtomic, |
| 12750 | /* AMADD__DB_W */ |
| 12751 | GPR, GPR, GPRMemAtomic, |
| 12752 | /* AMAND_D */ |
| 12753 | GPR, GPR, GPRMemAtomic, |
| 12754 | /* AMAND_W */ |
| 12755 | GPR, GPR, GPRMemAtomic, |
| 12756 | /* AMAND__DB_D */ |
| 12757 | GPR, GPR, GPRMemAtomic, |
| 12758 | /* AMAND__DB_W */ |
| 12759 | GPR, GPR, GPRMemAtomic, |
| 12760 | /* AMCAS_B */ |
| 12761 | GPR, GPR, GPRMemAtomic, |
| 12762 | /* AMCAS_D */ |
| 12763 | GPR, GPR, GPRMemAtomic, |
| 12764 | /* AMCAS_H */ |
| 12765 | GPR, GPR, GPRMemAtomic, |
| 12766 | /* AMCAS_W */ |
| 12767 | GPR, GPR, GPRMemAtomic, |
| 12768 | /* AMCAS__DB_B */ |
| 12769 | GPR, GPR, GPRMemAtomic, |
| 12770 | /* AMCAS__DB_D */ |
| 12771 | GPR, GPR, GPRMemAtomic, |
| 12772 | /* AMCAS__DB_H */ |
| 12773 | GPR, GPR, GPRMemAtomic, |
| 12774 | /* AMCAS__DB_W */ |
| 12775 | GPR, GPR, GPRMemAtomic, |
| 12776 | /* AMMAX_D */ |
| 12777 | GPR, GPR, GPRMemAtomic, |
| 12778 | /* AMMAX_DU */ |
| 12779 | GPR, GPR, GPRMemAtomic, |
| 12780 | /* AMMAX_W */ |
| 12781 | GPR, GPR, GPRMemAtomic, |
| 12782 | /* AMMAX_WU */ |
| 12783 | GPR, GPR, GPRMemAtomic, |
| 12784 | /* AMMAX__DB_D */ |
| 12785 | GPR, GPR, GPRMemAtomic, |
| 12786 | /* AMMAX__DB_DU */ |
| 12787 | GPR, GPR, GPRMemAtomic, |
| 12788 | /* AMMAX__DB_W */ |
| 12789 | GPR, GPR, GPRMemAtomic, |
| 12790 | /* AMMAX__DB_WU */ |
| 12791 | GPR, GPR, GPRMemAtomic, |
| 12792 | /* AMMIN_D */ |
| 12793 | GPR, GPR, GPRMemAtomic, |
| 12794 | /* AMMIN_DU */ |
| 12795 | GPR, GPR, GPRMemAtomic, |
| 12796 | /* AMMIN_W */ |
| 12797 | GPR, GPR, GPRMemAtomic, |
| 12798 | /* AMMIN_WU */ |
| 12799 | GPR, GPR, GPRMemAtomic, |
| 12800 | /* AMMIN__DB_D */ |
| 12801 | GPR, GPR, GPRMemAtomic, |
| 12802 | /* AMMIN__DB_DU */ |
| 12803 | GPR, GPR, GPRMemAtomic, |
| 12804 | /* AMMIN__DB_W */ |
| 12805 | GPR, GPR, GPRMemAtomic, |
| 12806 | /* AMMIN__DB_WU */ |
| 12807 | GPR, GPR, GPRMemAtomic, |
| 12808 | /* AMOR_D */ |
| 12809 | GPR, GPR, GPRMemAtomic, |
| 12810 | /* AMOR_W */ |
| 12811 | GPR, GPR, GPRMemAtomic, |
| 12812 | /* AMOR__DB_D */ |
| 12813 | GPR, GPR, GPRMemAtomic, |
| 12814 | /* AMOR__DB_W */ |
| 12815 | GPR, GPR, GPRMemAtomic, |
| 12816 | /* AMSWAP_B */ |
| 12817 | GPR, GPR, GPRMemAtomic, |
| 12818 | /* AMSWAP_D */ |
| 12819 | GPR, GPR, GPRMemAtomic, |
| 12820 | /* AMSWAP_H */ |
| 12821 | GPR, GPR, GPRMemAtomic, |
| 12822 | /* AMSWAP_W */ |
| 12823 | GPR, GPR, GPRMemAtomic, |
| 12824 | /* AMSWAP__DB_B */ |
| 12825 | GPR, GPR, GPRMemAtomic, |
| 12826 | /* AMSWAP__DB_D */ |
| 12827 | GPR, GPR, GPRMemAtomic, |
| 12828 | /* AMSWAP__DB_H */ |
| 12829 | GPR, GPR, GPRMemAtomic, |
| 12830 | /* AMSWAP__DB_W */ |
| 12831 | GPR, GPR, GPRMemAtomic, |
| 12832 | /* AMXOR_D */ |
| 12833 | GPR, GPR, GPRMemAtomic, |
| 12834 | /* AMXOR_W */ |
| 12835 | GPR, GPR, GPRMemAtomic, |
| 12836 | /* AMXOR__DB_D */ |
| 12837 | GPR, GPR, GPRMemAtomic, |
| 12838 | /* AMXOR__DB_W */ |
| 12839 | GPR, GPR, GPRMemAtomic, |
| 12840 | /* AND */ |
| 12841 | GPR, GPR, GPR, |
| 12842 | /* ANDI */ |
| 12843 | GPR, GPR, uimm12, |
| 12844 | /* ANDN */ |
| 12845 | GPR, GPR, GPR, |
| 12846 | /* ARMADC_W */ |
| 12847 | GPR, GPR, uimm4, |
| 12848 | /* ARMADD_W */ |
| 12849 | GPR, GPR, uimm4, |
| 12850 | /* ARMAND_W */ |
| 12851 | GPR, GPR, uimm4, |
| 12852 | /* ARMMFFLAG */ |
| 12853 | GPR, uimm8, |
| 12854 | /* ARMMOVE */ |
| 12855 | GPR, GPR, uimm4, |
| 12856 | /* ARMMOV_D */ |
| 12857 | GPR, uimm4, |
| 12858 | /* ARMMOV_W */ |
| 12859 | GPR, uimm4, |
| 12860 | /* ARMMTFLAG */ |
| 12861 | GPR, uimm8, |
| 12862 | /* ARMNOT_W */ |
| 12863 | GPR, uimm4, |
| 12864 | /* ARMOR_W */ |
| 12865 | GPR, GPR, uimm4, |
| 12866 | /* ARMROTRI_W */ |
| 12867 | GPR, uimm5, uimm4, |
| 12868 | /* ARMROTR_W */ |
| 12869 | GPR, GPR, uimm4, |
| 12870 | /* ARMRRX_W */ |
| 12871 | GPR, uimm4, |
| 12872 | /* ARMSBC_W */ |
| 12873 | GPR, GPR, uimm4, |
| 12874 | /* ARMSLLI_W */ |
| 12875 | GPR, uimm5, uimm4, |
| 12876 | /* ARMSLL_W */ |
| 12877 | GPR, GPR, uimm4, |
| 12878 | /* ARMSRAI_W */ |
| 12879 | GPR, uimm5, uimm4, |
| 12880 | /* ARMSRA_W */ |
| 12881 | GPR, GPR, uimm4, |
| 12882 | /* ARMSRLI_W */ |
| 12883 | GPR, uimm5, uimm4, |
| 12884 | /* ARMSRL_W */ |
| 12885 | GPR, GPR, uimm4, |
| 12886 | /* ARMSUB_W */ |
| 12887 | GPR, GPR, uimm4, |
| 12888 | /* ARMXOR_W */ |
| 12889 | GPR, GPR, uimm4, |
| 12890 | /* ASRTGT_D */ |
| 12891 | GPR, GPR, |
| 12892 | /* ASRTLE_D */ |
| 12893 | GPR, GPR, |
| 12894 | /* B */ |
| 12895 | simm26_b, |
| 12896 | /* BCEQZ */ |
| 12897 | CFR, simm21_lsl2, |
| 12898 | /* BCNEZ */ |
| 12899 | CFR, simm21_lsl2, |
| 12900 | /* BEQ */ |
| 12901 | GPR, GPR, simm16_lsl2_br, |
| 12902 | /* BEQZ */ |
| 12903 | GPR, simm21_lsl2, |
| 12904 | /* BGE */ |
| 12905 | GPR, GPR, simm16_lsl2_br, |
| 12906 | /* BGEU */ |
| 12907 | GPR, GPR, simm16_lsl2_br, |
| 12908 | /* BITREV_4B */ |
| 12909 | GPR, GPR, |
| 12910 | /* BITREV_8B */ |
| 12911 | GPR, GPR, |
| 12912 | /* BITREV_D */ |
| 12913 | GPR, GPR, |
| 12914 | /* BITREV_W */ |
| 12915 | GPR, GPR, |
| 12916 | /* BL */ |
| 12917 | simm26_symbol, |
| 12918 | /* BLT */ |
| 12919 | GPR, GPR, simm16_lsl2_br, |
| 12920 | /* BLTU */ |
| 12921 | GPR, GPR, simm16_lsl2_br, |
| 12922 | /* BNE */ |
| 12923 | GPR, GPR, simm16_lsl2_br, |
| 12924 | /* BNEZ */ |
| 12925 | GPR, simm21_lsl2, |
| 12926 | /* BREAK */ |
| 12927 | uimm15, |
| 12928 | /* BSTRINS_D */ |
| 12929 | GPR, GPR, GPR, uimm6, uimm6, |
| 12930 | /* BSTRINS_W */ |
| 12931 | GPR, GPR, GPR, uimm5, uimm5, |
| 12932 | /* BSTRPICK_D */ |
| 12933 | GPR, GPR, uimm6, uimm6, |
| 12934 | /* BSTRPICK_W */ |
| 12935 | GPR, GPR, uimm5, uimm5, |
| 12936 | /* BYTEPICK_D */ |
| 12937 | GPR, GPR, GPR, uimm3, |
| 12938 | /* BYTEPICK_W */ |
| 12939 | GPR, GPR, GPR, uimm2, |
| 12940 | /* CACOP */ |
| 12941 | uimm5, GPR, simm12, |
| 12942 | /* CLO_D */ |
| 12943 | GPR, GPR, |
| 12944 | /* CLO_W */ |
| 12945 | GPR, GPR, |
| 12946 | /* CLZ_D */ |
| 12947 | GPR, GPR, |
| 12948 | /* CLZ_W */ |
| 12949 | GPR, GPR, |
| 12950 | /* CPUCFG */ |
| 12951 | GPR, GPR, |
| 12952 | /* CRCC_W_B_W */ |
| 12953 | GPR, GPR, GPR, |
| 12954 | /* CRCC_W_D_W */ |
| 12955 | GPR, GPR, GPR, |
| 12956 | /* CRCC_W_H_W */ |
| 12957 | GPR, GPR, GPR, |
| 12958 | /* CRCC_W_W_W */ |
| 12959 | GPR, GPR, GPR, |
| 12960 | /* CRC_W_B_W */ |
| 12961 | GPR, GPR, GPR, |
| 12962 | /* CRC_W_D_W */ |
| 12963 | GPR, GPR, GPR, |
| 12964 | /* CRC_W_H_W */ |
| 12965 | GPR, GPR, GPR, |
| 12966 | /* CRC_W_W_W */ |
| 12967 | GPR, GPR, GPR, |
| 12968 | /* CSRRD */ |
| 12969 | GPR, uimm14, |
| 12970 | /* CSRWR */ |
| 12971 | GPR, GPR, uimm14, |
| 12972 | /* CSRXCHG */ |
| 12973 | GPR, GPR, GPR, uimm14, |
| 12974 | /* CTO_D */ |
| 12975 | GPR, GPR, |
| 12976 | /* CTO_W */ |
| 12977 | GPR, GPR, |
| 12978 | /* CTZ_D */ |
| 12979 | GPR, GPR, |
| 12980 | /* CTZ_W */ |
| 12981 | GPR, GPR, |
| 12982 | /* DBAR */ |
| 12983 | uimm15, |
| 12984 | /* DBCL */ |
| 12985 | uimm15, |
| 12986 | /* DIV_D */ |
| 12987 | GPR, GPR, GPR, |
| 12988 | /* DIV_DU */ |
| 12989 | GPR, GPR, GPR, |
| 12990 | /* DIV_W */ |
| 12991 | GPR, GPR, GPR, |
| 12992 | /* DIV_WU */ |
| 12993 | GPR, GPR, GPR, |
| 12994 | /* ERTN */ |
| 12995 | /* EXT_W_B */ |
| 12996 | GPR, GPR, |
| 12997 | /* EXT_W_H */ |
| 12998 | GPR, GPR, |
| 12999 | /* FABS_D */ |
| 13000 | FPR64, FPR64, |
| 13001 | /* FABS_S */ |
| 13002 | FPR32, FPR32, |
| 13003 | /* FADD_D */ |
| 13004 | FPR64, FPR64, FPR64, |
| 13005 | /* FADD_S */ |
| 13006 | FPR32, FPR32, FPR32, |
| 13007 | /* FCLASS_D */ |
| 13008 | FPR64, FPR64, |
| 13009 | /* FCLASS_S */ |
| 13010 | FPR32, FPR32, |
| 13011 | /* FCMP_CAF_D */ |
| 13012 | CFR, FPR64, FPR64, |
| 13013 | /* FCMP_CAF_S */ |
| 13014 | CFR, FPR32, FPR32, |
| 13015 | /* FCMP_CEQ_D */ |
| 13016 | CFR, FPR64, FPR64, |
| 13017 | /* FCMP_CEQ_S */ |
| 13018 | CFR, FPR32, FPR32, |
| 13019 | /* FCMP_CLE_D */ |
| 13020 | CFR, FPR64, FPR64, |
| 13021 | /* FCMP_CLE_S */ |
| 13022 | CFR, FPR32, FPR32, |
| 13023 | /* FCMP_CLT_D */ |
| 13024 | CFR, FPR64, FPR64, |
| 13025 | /* FCMP_CLT_S */ |
| 13026 | CFR, FPR32, FPR32, |
| 13027 | /* FCMP_CNE_D */ |
| 13028 | CFR, FPR64, FPR64, |
| 13029 | /* FCMP_CNE_S */ |
| 13030 | CFR, FPR32, FPR32, |
| 13031 | /* FCMP_COR_D */ |
| 13032 | CFR, FPR64, FPR64, |
| 13033 | /* FCMP_COR_S */ |
| 13034 | CFR, FPR32, FPR32, |
| 13035 | /* FCMP_CUEQ_D */ |
| 13036 | CFR, FPR64, FPR64, |
| 13037 | /* FCMP_CUEQ_S */ |
| 13038 | CFR, FPR32, FPR32, |
| 13039 | /* FCMP_CULE_D */ |
| 13040 | CFR, FPR64, FPR64, |
| 13041 | /* FCMP_CULE_S */ |
| 13042 | CFR, FPR32, FPR32, |
| 13043 | /* FCMP_CULT_D */ |
| 13044 | CFR, FPR64, FPR64, |
| 13045 | /* FCMP_CULT_S */ |
| 13046 | CFR, FPR32, FPR32, |
| 13047 | /* FCMP_CUNE_D */ |
| 13048 | CFR, FPR64, FPR64, |
| 13049 | /* FCMP_CUNE_S */ |
| 13050 | CFR, FPR32, FPR32, |
| 13051 | /* FCMP_CUN_D */ |
| 13052 | CFR, FPR64, FPR64, |
| 13053 | /* FCMP_CUN_S */ |
| 13054 | CFR, FPR32, FPR32, |
| 13055 | /* FCMP_SAF_D */ |
| 13056 | CFR, FPR64, FPR64, |
| 13057 | /* FCMP_SAF_S */ |
| 13058 | CFR, FPR32, FPR32, |
| 13059 | /* FCMP_SEQ_D */ |
| 13060 | CFR, FPR64, FPR64, |
| 13061 | /* FCMP_SEQ_S */ |
| 13062 | CFR, FPR32, FPR32, |
| 13063 | /* FCMP_SLE_D */ |
| 13064 | CFR, FPR64, FPR64, |
| 13065 | /* FCMP_SLE_S */ |
| 13066 | CFR, FPR32, FPR32, |
| 13067 | /* FCMP_SLT_D */ |
| 13068 | CFR, FPR64, FPR64, |
| 13069 | /* FCMP_SLT_S */ |
| 13070 | CFR, FPR32, FPR32, |
| 13071 | /* FCMP_SNE_D */ |
| 13072 | CFR, FPR64, FPR64, |
| 13073 | /* FCMP_SNE_S */ |
| 13074 | CFR, FPR32, FPR32, |
| 13075 | /* FCMP_SOR_D */ |
| 13076 | CFR, FPR64, FPR64, |
| 13077 | /* FCMP_SOR_S */ |
| 13078 | CFR, FPR32, FPR32, |
| 13079 | /* FCMP_SUEQ_D */ |
| 13080 | CFR, FPR64, FPR64, |
| 13081 | /* FCMP_SUEQ_S */ |
| 13082 | CFR, FPR32, FPR32, |
| 13083 | /* FCMP_SULE_D */ |
| 13084 | CFR, FPR64, FPR64, |
| 13085 | /* FCMP_SULE_S */ |
| 13086 | CFR, FPR32, FPR32, |
| 13087 | /* FCMP_SULT_D */ |
| 13088 | CFR, FPR64, FPR64, |
| 13089 | /* FCMP_SULT_S */ |
| 13090 | CFR, FPR32, FPR32, |
| 13091 | /* FCMP_SUNE_D */ |
| 13092 | CFR, FPR64, FPR64, |
| 13093 | /* FCMP_SUNE_S */ |
| 13094 | CFR, FPR32, FPR32, |
| 13095 | /* FCMP_SUN_D */ |
| 13096 | CFR, FPR64, FPR64, |
| 13097 | /* FCMP_SUN_S */ |
| 13098 | CFR, FPR32, FPR32, |
| 13099 | /* FCOPYSIGN_D */ |
| 13100 | FPR64, FPR64, FPR64, |
| 13101 | /* FCOPYSIGN_S */ |
| 13102 | FPR32, FPR32, FPR32, |
| 13103 | /* FCVT_D_LD */ |
| 13104 | FPR32, FPR32, FPR32, |
| 13105 | /* FCVT_D_S */ |
| 13106 | FPR64, FPR32, |
| 13107 | /* FCVT_LD_D */ |
| 13108 | FPR32, FPR32, |
| 13109 | /* FCVT_S_D */ |
| 13110 | FPR32, FPR64, |
| 13111 | /* FCVT_UD_D */ |
| 13112 | FPR32, FPR32, |
| 13113 | /* FDIV_D */ |
| 13114 | FPR64, FPR64, FPR64, |
| 13115 | /* FDIV_S */ |
| 13116 | FPR32, FPR32, FPR32, |
| 13117 | /* FFINT_D_L */ |
| 13118 | FPR64, FPR64, |
| 13119 | /* FFINT_D_W */ |
| 13120 | FPR64, FPR32, |
| 13121 | /* FFINT_S_L */ |
| 13122 | FPR32, FPR64, |
| 13123 | /* FFINT_S_W */ |
| 13124 | FPR32, FPR32, |
| 13125 | /* FLDGT_D */ |
| 13126 | FPR64, GPR, GPR, |
| 13127 | /* FLDGT_S */ |
| 13128 | FPR32, GPR, GPR, |
| 13129 | /* FLDLE_D */ |
| 13130 | FPR64, GPR, GPR, |
| 13131 | /* FLDLE_S */ |
| 13132 | FPR32, GPR, GPR, |
| 13133 | /* FLDX_D */ |
| 13134 | FPR64, GPR, GPR, |
| 13135 | /* FLDX_S */ |
| 13136 | FPR32, GPR, GPR, |
| 13137 | /* FLD_D */ |
| 13138 | FPR64, GPR, simm12, |
| 13139 | /* FLD_S */ |
| 13140 | FPR32, GPR, simm12, |
| 13141 | /* FLOGB_D */ |
| 13142 | FPR64, FPR64, |
| 13143 | /* FLOGB_S */ |
| 13144 | FPR32, FPR32, |
| 13145 | /* FMADD_D */ |
| 13146 | FPR64, FPR64, FPR64, FPR64, |
| 13147 | /* FMADD_S */ |
| 13148 | FPR32, FPR32, FPR32, FPR32, |
| 13149 | /* FMAXA_D */ |
| 13150 | FPR64, FPR64, FPR64, |
| 13151 | /* FMAXA_S */ |
| 13152 | FPR32, FPR32, FPR32, |
| 13153 | /* FMAX_D */ |
| 13154 | FPR64, FPR64, FPR64, |
| 13155 | /* FMAX_S */ |
| 13156 | FPR32, FPR32, FPR32, |
| 13157 | /* FMINA_D */ |
| 13158 | FPR64, FPR64, FPR64, |
| 13159 | /* FMINA_S */ |
| 13160 | FPR32, FPR32, FPR32, |
| 13161 | /* FMIN_D */ |
| 13162 | FPR64, FPR64, FPR64, |
| 13163 | /* FMIN_S */ |
| 13164 | FPR32, FPR32, FPR32, |
| 13165 | /* FMOV_D */ |
| 13166 | FPR64, FPR64, |
| 13167 | /* FMOV_S */ |
| 13168 | FPR32, FPR32, |
| 13169 | /* FMSUB_D */ |
| 13170 | FPR64, FPR64, FPR64, FPR64, |
| 13171 | /* FMSUB_S */ |
| 13172 | FPR32, FPR32, FPR32, FPR32, |
| 13173 | /* FMUL_D */ |
| 13174 | FPR64, FPR64, FPR64, |
| 13175 | /* FMUL_S */ |
| 13176 | FPR32, FPR32, FPR32, |
| 13177 | /* FNEG_D */ |
| 13178 | FPR64, FPR64, |
| 13179 | /* FNEG_S */ |
| 13180 | FPR32, FPR32, |
| 13181 | /* FNMADD_D */ |
| 13182 | FPR64, FPR64, FPR64, FPR64, |
| 13183 | /* FNMADD_S */ |
| 13184 | FPR32, FPR32, FPR32, FPR32, |
| 13185 | /* FNMSUB_D */ |
| 13186 | FPR64, FPR64, FPR64, FPR64, |
| 13187 | /* FNMSUB_S */ |
| 13188 | FPR32, FPR32, FPR32, FPR32, |
| 13189 | /* FRECIPE_D */ |
| 13190 | FPR64, FPR64, |
| 13191 | /* FRECIPE_S */ |
| 13192 | FPR32, FPR32, |
| 13193 | /* FRECIP_D */ |
| 13194 | FPR64, FPR64, |
| 13195 | /* FRECIP_S */ |
| 13196 | FPR32, FPR32, |
| 13197 | /* FRINT_D */ |
| 13198 | FPR64, FPR64, |
| 13199 | /* FRINT_S */ |
| 13200 | FPR32, FPR32, |
| 13201 | /* FRSQRTE_D */ |
| 13202 | FPR64, FPR64, |
| 13203 | /* FRSQRTE_S */ |
| 13204 | FPR32, FPR32, |
| 13205 | /* FRSQRT_D */ |
| 13206 | FPR64, FPR64, |
| 13207 | /* FRSQRT_S */ |
| 13208 | FPR32, FPR32, |
| 13209 | /* FSCALEB_D */ |
| 13210 | FPR64, FPR64, FPR64, |
| 13211 | /* FSCALEB_S */ |
| 13212 | FPR32, FPR32, FPR32, |
| 13213 | /* FSEL_xD */ |
| 13214 | FPR64, FPR64, FPR64, CFR, |
| 13215 | /* FSEL_xS */ |
| 13216 | FPR32, FPR32, FPR32, CFR, |
| 13217 | /* FSQRT_D */ |
| 13218 | FPR64, FPR64, |
| 13219 | /* FSQRT_S */ |
| 13220 | FPR32, FPR32, |
| 13221 | /* FSTGT_D */ |
| 13222 | FPR64, GPR, GPR, |
| 13223 | /* FSTGT_S */ |
| 13224 | FPR32, GPR, GPR, |
| 13225 | /* FSTLE_D */ |
| 13226 | FPR64, GPR, GPR, |
| 13227 | /* FSTLE_S */ |
| 13228 | FPR32, GPR, GPR, |
| 13229 | /* FSTX_D */ |
| 13230 | FPR64, GPR, GPR, |
| 13231 | /* FSTX_S */ |
| 13232 | FPR32, GPR, GPR, |
| 13233 | /* FST_D */ |
| 13234 | FPR64, GPR, simm12, |
| 13235 | /* FST_S */ |
| 13236 | FPR32, GPR, simm12, |
| 13237 | /* FSUB_D */ |
| 13238 | FPR64, FPR64, FPR64, |
| 13239 | /* FSUB_S */ |
| 13240 | FPR32, FPR32, FPR32, |
| 13241 | /* FTINTRM_L_D */ |
| 13242 | FPR64, FPR64, |
| 13243 | /* FTINTRM_L_S */ |
| 13244 | FPR64, FPR32, |
| 13245 | /* FTINTRM_W_D */ |
| 13246 | FPR32, FPR64, |
| 13247 | /* FTINTRM_W_S */ |
| 13248 | FPR32, FPR32, |
| 13249 | /* FTINTRNE_L_D */ |
| 13250 | FPR64, FPR64, |
| 13251 | /* FTINTRNE_L_S */ |
| 13252 | FPR64, FPR32, |
| 13253 | /* FTINTRNE_W_D */ |
| 13254 | FPR32, FPR64, |
| 13255 | /* FTINTRNE_W_S */ |
| 13256 | FPR32, FPR32, |
| 13257 | /* FTINTRP_L_D */ |
| 13258 | FPR64, FPR64, |
| 13259 | /* FTINTRP_L_S */ |
| 13260 | FPR64, FPR32, |
| 13261 | /* FTINTRP_W_D */ |
| 13262 | FPR32, FPR64, |
| 13263 | /* FTINTRP_W_S */ |
| 13264 | FPR32, FPR32, |
| 13265 | /* FTINTRZ_L_D */ |
| 13266 | FPR64, FPR64, |
| 13267 | /* FTINTRZ_L_S */ |
| 13268 | FPR64, FPR32, |
| 13269 | /* FTINTRZ_W_D */ |
| 13270 | FPR32, FPR64, |
| 13271 | /* FTINTRZ_W_S */ |
| 13272 | FPR32, FPR32, |
| 13273 | /* FTINT_L_D */ |
| 13274 | FPR64, FPR64, |
| 13275 | /* FTINT_L_S */ |
| 13276 | FPR64, FPR32, |
| 13277 | /* FTINT_W_D */ |
| 13278 | FPR32, FPR64, |
| 13279 | /* FTINT_W_S */ |
| 13280 | FPR32, FPR32, |
| 13281 | /* GCSRRD */ |
| 13282 | GPR, uimm14, |
| 13283 | /* GCSRWR */ |
| 13284 | GPR, GPR, uimm14, |
| 13285 | /* GCSRXCHG */ |
| 13286 | GPR, GPR, GPR, uimm14, |
| 13287 | /* GTLBFLUSH */ |
| 13288 | /* HVCL */ |
| 13289 | uimm15, |
| 13290 | /* IBAR */ |
| 13291 | uimm15, |
| 13292 | /* IDLE */ |
| 13293 | uimm15, |
| 13294 | /* INVTLB */ |
| 13295 | GPR, GPR, uimm5, |
| 13296 | /* IOCSRRD_B */ |
| 13297 | GPR, GPR, |
| 13298 | /* IOCSRRD_D */ |
| 13299 | GPR, GPR, |
| 13300 | /* IOCSRRD_H */ |
| 13301 | GPR, GPR, |
| 13302 | /* IOCSRRD_W */ |
| 13303 | GPR, GPR, |
| 13304 | /* IOCSRWR_B */ |
| 13305 | GPR, GPR, |
| 13306 | /* IOCSRWR_D */ |
| 13307 | GPR, GPR, |
| 13308 | /* IOCSRWR_H */ |
| 13309 | GPR, GPR, |
| 13310 | /* IOCSRWR_W */ |
| 13311 | GPR, GPR, |
| 13312 | /* JIRL */ |
| 13313 | GPR, GPR, simm16_lsl2, |
| 13314 | /* JISCR0 */ |
| 13315 | simm21_lsl2, |
| 13316 | /* JISCR1 */ |
| 13317 | simm21_lsl2, |
| 13318 | /* LDDIR */ |
| 13319 | GPR, GPR, uimm8, |
| 13320 | /* LDGT_B */ |
| 13321 | GPR, GPR, GPR, |
| 13322 | /* LDGT_D */ |
| 13323 | GPR, GPR, GPR, |
| 13324 | /* LDGT_H */ |
| 13325 | GPR, GPR, GPR, |
| 13326 | /* LDGT_W */ |
| 13327 | GPR, GPR, GPR, |
| 13328 | /* LDLE_B */ |
| 13329 | GPR, GPR, GPR, |
| 13330 | /* LDLE_D */ |
| 13331 | GPR, GPR, GPR, |
| 13332 | /* LDLE_H */ |
| 13333 | GPR, GPR, GPR, |
| 13334 | /* LDLE_W */ |
| 13335 | GPR, GPR, GPR, |
| 13336 | /* LDL_D */ |
| 13337 | GPR, GPR, simm12_addlike, |
| 13338 | /* LDL_W */ |
| 13339 | GPR, GPR, simm12_addlike, |
| 13340 | /* LDPTE */ |
| 13341 | GPR, uimm8, |
| 13342 | /* LDPTR_D */ |
| 13343 | GPR, GPR, simm14_lsl2, |
| 13344 | /* LDPTR_W */ |
| 13345 | GPR, GPR, simm14_lsl2, |
| 13346 | /* LDR_D */ |
| 13347 | GPR, GPR, simm12_addlike, |
| 13348 | /* LDR_W */ |
| 13349 | GPR, GPR, simm12_addlike, |
| 13350 | /* LDX_B */ |
| 13351 | GPR, GPR, GPR, |
| 13352 | /* LDX_BU */ |
| 13353 | GPR, GPR, GPR, |
| 13354 | /* LDX_D */ |
| 13355 | GPR, GPR, GPR, |
| 13356 | /* LDX_H */ |
| 13357 | GPR, GPR, GPR, |
| 13358 | /* LDX_HU */ |
| 13359 | GPR, GPR, GPR, |
| 13360 | /* LDX_W */ |
| 13361 | GPR, GPR, GPR, |
| 13362 | /* LDX_WU */ |
| 13363 | GPR, GPR, GPR, |
| 13364 | /* LD_B */ |
| 13365 | GPR, GPR, simm12_addlike, |
| 13366 | /* LD_BU */ |
| 13367 | GPR, GPR, simm12_addlike, |
| 13368 | /* LD_D */ |
| 13369 | GPR, GPR, simm12_addlike, |
| 13370 | /* LD_H */ |
| 13371 | GPR, GPR, simm12_addlike, |
| 13372 | /* LD_HU */ |
| 13373 | GPR, GPR, simm12_addlike, |
| 13374 | /* LD_W */ |
| 13375 | GPR, GPR, simm12_addlike, |
| 13376 | /* LD_WU */ |
| 13377 | GPR, GPR, simm12_addlike, |
| 13378 | /* LLACQ_D */ |
| 13379 | GPR, GPR, |
| 13380 | /* LLACQ_W */ |
| 13381 | GPR, GPR, |
| 13382 | /* LL_D */ |
| 13383 | GPR, GPR, simm14_lsl2, |
| 13384 | /* LL_W */ |
| 13385 | GPR, GPR, simm14_lsl2, |
| 13386 | /* LU12I_W */ |
| 13387 | GPR, simm20_lu12iw, |
| 13388 | /* LU32I_D */ |
| 13389 | GPR, GPR, simm20_lu32id, |
| 13390 | /* LU52I_D */ |
| 13391 | GPR, GPR, simm12_lu52id, |
| 13392 | /* MASKEQZ */ |
| 13393 | GPR, GPR, GPR, |
| 13394 | /* MASKNEZ */ |
| 13395 | GPR, GPR, GPR, |
| 13396 | /* MOD_D */ |
| 13397 | GPR, GPR, GPR, |
| 13398 | /* MOD_DU */ |
| 13399 | GPR, GPR, GPR, |
| 13400 | /* MOD_W */ |
| 13401 | GPR, GPR, GPR, |
| 13402 | /* MOD_WU */ |
| 13403 | GPR, GPR, GPR, |
| 13404 | /* MOVCF2FR_xS */ |
| 13405 | FPR32, CFR, |
| 13406 | /* MOVCF2GR */ |
| 13407 | GPR, CFR, |
| 13408 | /* MOVFCSR2GR */ |
| 13409 | GPR, FCSR, |
| 13410 | /* MOVFR2CF_xS */ |
| 13411 | CFR, FPR32, |
| 13412 | /* MOVFR2GR_D */ |
| 13413 | GPR, FPR64, |
| 13414 | /* MOVFR2GR_S */ |
| 13415 | GPR, FPR32, |
| 13416 | /* MOVFR2GR_S_64 */ |
| 13417 | GPR, FPR64, |
| 13418 | /* MOVFRH2GR_S */ |
| 13419 | GPR, FPR64, |
| 13420 | /* MOVGR2CF */ |
| 13421 | CFR, GPR, |
| 13422 | /* MOVGR2FCSR */ |
| 13423 | FCSR, GPR, |
| 13424 | /* MOVGR2FRH_W */ |
| 13425 | FPR64, FPR64, GPR, |
| 13426 | /* MOVGR2FR_D */ |
| 13427 | FPR64, GPR, |
| 13428 | /* MOVGR2FR_W */ |
| 13429 | FPR32, GPR, |
| 13430 | /* MOVGR2FR_W_64 */ |
| 13431 | FPR64, GPR, |
| 13432 | /* MOVGR2SCR */ |
| 13433 | SCR, GPR, |
| 13434 | /* MOVSCR2GR */ |
| 13435 | GPR, SCR, |
| 13436 | /* MULH_D */ |
| 13437 | GPR, GPR, GPR, |
| 13438 | /* MULH_DU */ |
| 13439 | GPR, GPR, GPR, |
| 13440 | /* MULH_W */ |
| 13441 | GPR, GPR, GPR, |
| 13442 | /* MULH_WU */ |
| 13443 | GPR, GPR, GPR, |
| 13444 | /* MULW_D_W */ |
| 13445 | GPR, GPR, GPR, |
| 13446 | /* MULW_D_WU */ |
| 13447 | GPR, GPR, GPR, |
| 13448 | /* MUL_D */ |
| 13449 | GPR, GPR, GPR, |
| 13450 | /* MUL_W */ |
| 13451 | GPR, GPR, GPR, |
| 13452 | /* NOR */ |
| 13453 | GPR, GPR, GPR, |
| 13454 | /* OR */ |
| 13455 | GPR, GPR, GPR, |
| 13456 | /* ORI */ |
| 13457 | GPR, GPR, uimm12_ori, |
| 13458 | /* ORN */ |
| 13459 | GPR, GPR, GPR, |
| 13460 | /* PCADDI */ |
| 13461 | GPR, simm20_pcaddi, |
| 13462 | /* PCADDU12I */ |
| 13463 | GPR, simm20, |
| 13464 | /* PCADDU18I */ |
| 13465 | GPR, simm20_pcaddu18i, |
| 13466 | /* PCALAU12I */ |
| 13467 | GPR, simm20_pcalau12i, |
| 13468 | /* PRELD */ |
| 13469 | uimm5, GPR, simm12, |
| 13470 | /* PRELDX */ |
| 13471 | uimm5, GPR, GPR, |
| 13472 | /* RCRI_B */ |
| 13473 | GPR, GPR, uimm3, |
| 13474 | /* RCRI_D */ |
| 13475 | GPR, GPR, uimm6, |
| 13476 | /* RCRI_H */ |
| 13477 | GPR, GPR, uimm4, |
| 13478 | /* RCRI_W */ |
| 13479 | GPR, GPR, uimm5, |
| 13480 | /* RCR_B */ |
| 13481 | GPR, GPR, GPR, |
| 13482 | /* RCR_D */ |
| 13483 | GPR, GPR, GPR, |
| 13484 | /* RCR_H */ |
| 13485 | GPR, GPR, GPR, |
| 13486 | /* RCR_W */ |
| 13487 | GPR, GPR, GPR, |
| 13488 | /* RDTIMEH_W */ |
| 13489 | GPR, GPR, |
| 13490 | /* RDTIMEL_W */ |
| 13491 | GPR, GPR, |
| 13492 | /* RDTIME_D */ |
| 13493 | GPR, GPR, |
| 13494 | /* REVB_2H */ |
| 13495 | GPR, GPR, |
| 13496 | /* REVB_2W */ |
| 13497 | GPR, GPR, |
| 13498 | /* REVB_4H */ |
| 13499 | GPR, GPR, |
| 13500 | /* REVB_D */ |
| 13501 | GPR, GPR, |
| 13502 | /* REVH_2W */ |
| 13503 | GPR, GPR, |
| 13504 | /* REVH_D */ |
| 13505 | GPR, GPR, |
| 13506 | /* ROTRI_B */ |
| 13507 | GPR, GPR, uimm3, |
| 13508 | /* ROTRI_D */ |
| 13509 | GPR, GPR, uimm6, |
| 13510 | /* ROTRI_H */ |
| 13511 | GPR, GPR, uimm4, |
| 13512 | /* ROTRI_W */ |
| 13513 | GPR, GPR, uimm5, |
| 13514 | /* ROTR_B */ |
| 13515 | GPR, GPR, GPR, |
| 13516 | /* ROTR_D */ |
| 13517 | GPR, GPR, GPR, |
| 13518 | /* ROTR_H */ |
| 13519 | GPR, GPR, GPR, |
| 13520 | /* ROTR_W */ |
| 13521 | GPR, GPR, GPR, |
| 13522 | /* SBC_B */ |
| 13523 | GPR, GPR, GPR, |
| 13524 | /* SBC_D */ |
| 13525 | GPR, GPR, GPR, |
| 13526 | /* SBC_H */ |
| 13527 | GPR, GPR, GPR, |
| 13528 | /* SBC_W */ |
| 13529 | GPR, GPR, GPR, |
| 13530 | /* SCREL_D */ |
| 13531 | GPR, GPR, GPR, |
| 13532 | /* SCREL_W */ |
| 13533 | GPR, GPR, GPR, |
| 13534 | /* SC_D */ |
| 13535 | GPR, GPR, GPR, simm14_lsl2, |
| 13536 | /* SC_Q */ |
| 13537 | GPR, GPR, GPR, GPR, |
| 13538 | /* SC_W */ |
| 13539 | GPR, GPR, GPR, simm14_lsl2, |
| 13540 | /* SETARMJ */ |
| 13541 | GPR, uimm4, |
| 13542 | /* SETX86J */ |
| 13543 | GPR, uimm4, |
| 13544 | /* SETX86LOOPE */ |
| 13545 | GPR, GPR, |
| 13546 | /* SETX86LOOPNE */ |
| 13547 | GPR, GPR, |
| 13548 | /* SET_CFR_FALSE */ |
| 13549 | CFR, |
| 13550 | /* SET_CFR_TRUE */ |
| 13551 | CFR, |
| 13552 | /* SLLI_D */ |
| 13553 | GPR, GPR, uimm6, |
| 13554 | /* SLLI_W */ |
| 13555 | GPR, GPR, uimm5, |
| 13556 | /* SLL_D */ |
| 13557 | GPR, GPR, GPR, |
| 13558 | /* SLL_W */ |
| 13559 | GPR, GPR, GPR, |
| 13560 | /* SLT */ |
| 13561 | GPR, GPR, GPR, |
| 13562 | /* SLTI */ |
| 13563 | GPR, GPR, simm12, |
| 13564 | /* SLTU */ |
| 13565 | GPR, GPR, GPR, |
| 13566 | /* SLTUI */ |
| 13567 | GPR, GPR, simm12, |
| 13568 | /* SRAI_D */ |
| 13569 | GPR, GPR, uimm6, |
| 13570 | /* SRAI_W */ |
| 13571 | GPR, GPR, uimm5, |
| 13572 | /* SRA_D */ |
| 13573 | GPR, GPR, GPR, |
| 13574 | /* SRA_W */ |
| 13575 | GPR, GPR, GPR, |
| 13576 | /* SRLI_D */ |
| 13577 | GPR, GPR, uimm6, |
| 13578 | /* SRLI_W */ |
| 13579 | GPR, GPR, uimm5, |
| 13580 | /* SRL_D */ |
| 13581 | GPR, GPR, GPR, |
| 13582 | /* SRL_W */ |
| 13583 | GPR, GPR, GPR, |
| 13584 | /* STGT_B */ |
| 13585 | GPR, GPR, GPR, |
| 13586 | /* STGT_D */ |
| 13587 | GPR, GPR, GPR, |
| 13588 | /* STGT_H */ |
| 13589 | GPR, GPR, GPR, |
| 13590 | /* STGT_W */ |
| 13591 | GPR, GPR, GPR, |
| 13592 | /* STLE_B */ |
| 13593 | GPR, GPR, GPR, |
| 13594 | /* STLE_D */ |
| 13595 | GPR, GPR, GPR, |
| 13596 | /* STLE_H */ |
| 13597 | GPR, GPR, GPR, |
| 13598 | /* STLE_W */ |
| 13599 | GPR, GPR, GPR, |
| 13600 | /* STL_D */ |
| 13601 | GPR, GPR, simm12_addlike, |
| 13602 | /* STL_W */ |
| 13603 | GPR, GPR, simm12_addlike, |
| 13604 | /* STPTR_D */ |
| 13605 | GPR, GPR, simm14_lsl2, |
| 13606 | /* STPTR_W */ |
| 13607 | GPR, GPR, simm14_lsl2, |
| 13608 | /* STR_D */ |
| 13609 | GPR, GPR, simm12_addlike, |
| 13610 | /* STR_W */ |
| 13611 | GPR, GPR, simm12_addlike, |
| 13612 | /* STX_B */ |
| 13613 | GPR, GPR, GPR, |
| 13614 | /* STX_D */ |
| 13615 | GPR, GPR, GPR, |
| 13616 | /* STX_H */ |
| 13617 | GPR, GPR, GPR, |
| 13618 | /* STX_W */ |
| 13619 | GPR, GPR, GPR, |
| 13620 | /* ST_B */ |
| 13621 | GPR, GPR, simm12_addlike, |
| 13622 | /* ST_D */ |
| 13623 | GPR, GPR, simm12_addlike, |
| 13624 | /* ST_H */ |
| 13625 | GPR, GPR, simm12_addlike, |
| 13626 | /* ST_W */ |
| 13627 | GPR, GPR, simm12_addlike, |
| 13628 | /* SUB_D */ |
| 13629 | GPR, GPR, GPR, |
| 13630 | /* SUB_W */ |
| 13631 | GPR, GPR, GPR, |
| 13632 | /* SYSCALL */ |
| 13633 | uimm15, |
| 13634 | /* TLBCLR */ |
| 13635 | /* TLBFILL */ |
| 13636 | /* TLBFLUSH */ |
| 13637 | /* TLBRD */ |
| 13638 | /* TLBSRCH */ |
| 13639 | /* TLBWR */ |
| 13640 | /* VABSD_B */ |
| 13641 | LSX128, LSX128, LSX128, |
| 13642 | /* VABSD_BU */ |
| 13643 | LSX128, LSX128, LSX128, |
| 13644 | /* VABSD_D */ |
| 13645 | LSX128, LSX128, LSX128, |
| 13646 | /* VABSD_DU */ |
| 13647 | LSX128, LSX128, LSX128, |
| 13648 | /* VABSD_H */ |
| 13649 | LSX128, LSX128, LSX128, |
| 13650 | /* VABSD_HU */ |
| 13651 | LSX128, LSX128, LSX128, |
| 13652 | /* VABSD_W */ |
| 13653 | LSX128, LSX128, LSX128, |
| 13654 | /* VABSD_WU */ |
| 13655 | LSX128, LSX128, LSX128, |
| 13656 | /* VADDA_B */ |
| 13657 | LSX128, LSX128, LSX128, |
| 13658 | /* VADDA_D */ |
| 13659 | LSX128, LSX128, LSX128, |
| 13660 | /* VADDA_H */ |
| 13661 | LSX128, LSX128, LSX128, |
| 13662 | /* VADDA_W */ |
| 13663 | LSX128, LSX128, LSX128, |
| 13664 | /* VADDI_BU */ |
| 13665 | LSX128, LSX128, uimm5, |
| 13666 | /* VADDI_DU */ |
| 13667 | LSX128, LSX128, uimm5, |
| 13668 | /* VADDI_HU */ |
| 13669 | LSX128, LSX128, uimm5, |
| 13670 | /* VADDI_WU */ |
| 13671 | LSX128, LSX128, uimm5, |
| 13672 | /* VADDWEV_D_W */ |
| 13673 | LSX128, LSX128, LSX128, |
| 13674 | /* VADDWEV_D_WU */ |
| 13675 | LSX128, LSX128, LSX128, |
| 13676 | /* VADDWEV_D_WU_W */ |
| 13677 | LSX128, LSX128, LSX128, |
| 13678 | /* VADDWEV_H_B */ |
| 13679 | LSX128, LSX128, LSX128, |
| 13680 | /* VADDWEV_H_BU */ |
| 13681 | LSX128, LSX128, LSX128, |
| 13682 | /* VADDWEV_H_BU_B */ |
| 13683 | LSX128, LSX128, LSX128, |
| 13684 | /* VADDWEV_Q_D */ |
| 13685 | LSX128, LSX128, LSX128, |
| 13686 | /* VADDWEV_Q_DU */ |
| 13687 | LSX128, LSX128, LSX128, |
| 13688 | /* VADDWEV_Q_DU_D */ |
| 13689 | LSX128, LSX128, LSX128, |
| 13690 | /* VADDWEV_W_H */ |
| 13691 | LSX128, LSX128, LSX128, |
| 13692 | /* VADDWEV_W_HU */ |
| 13693 | LSX128, LSX128, LSX128, |
| 13694 | /* VADDWEV_W_HU_H */ |
| 13695 | LSX128, LSX128, LSX128, |
| 13696 | /* VADDWOD_D_W */ |
| 13697 | LSX128, LSX128, LSX128, |
| 13698 | /* VADDWOD_D_WU */ |
| 13699 | LSX128, LSX128, LSX128, |
| 13700 | /* VADDWOD_D_WU_W */ |
| 13701 | LSX128, LSX128, LSX128, |
| 13702 | /* VADDWOD_H_B */ |
| 13703 | LSX128, LSX128, LSX128, |
| 13704 | /* VADDWOD_H_BU */ |
| 13705 | LSX128, LSX128, LSX128, |
| 13706 | /* VADDWOD_H_BU_B */ |
| 13707 | LSX128, LSX128, LSX128, |
| 13708 | /* VADDWOD_Q_D */ |
| 13709 | LSX128, LSX128, LSX128, |
| 13710 | /* VADDWOD_Q_DU */ |
| 13711 | LSX128, LSX128, LSX128, |
| 13712 | /* VADDWOD_Q_DU_D */ |
| 13713 | LSX128, LSX128, LSX128, |
| 13714 | /* VADDWOD_W_H */ |
| 13715 | LSX128, LSX128, LSX128, |
| 13716 | /* VADDWOD_W_HU */ |
| 13717 | LSX128, LSX128, LSX128, |
| 13718 | /* VADDWOD_W_HU_H */ |
| 13719 | LSX128, LSX128, LSX128, |
| 13720 | /* VADD_B */ |
| 13721 | LSX128, LSX128, LSX128, |
| 13722 | /* VADD_D */ |
| 13723 | LSX128, LSX128, LSX128, |
| 13724 | /* VADD_H */ |
| 13725 | LSX128, LSX128, LSX128, |
| 13726 | /* VADD_Q */ |
| 13727 | LSX128, LSX128, LSX128, |
| 13728 | /* VADD_W */ |
| 13729 | LSX128, LSX128, LSX128, |
| 13730 | /* VANDI_B */ |
| 13731 | LSX128, LSX128, uimm8, |
| 13732 | /* VANDN_V */ |
| 13733 | LSX128, LSX128, LSX128, |
| 13734 | /* VAND_V */ |
| 13735 | LSX128, LSX128, LSX128, |
| 13736 | /* VAVGR_B */ |
| 13737 | LSX128, LSX128, LSX128, |
| 13738 | /* VAVGR_BU */ |
| 13739 | LSX128, LSX128, LSX128, |
| 13740 | /* VAVGR_D */ |
| 13741 | LSX128, LSX128, LSX128, |
| 13742 | /* VAVGR_DU */ |
| 13743 | LSX128, LSX128, LSX128, |
| 13744 | /* VAVGR_H */ |
| 13745 | LSX128, LSX128, LSX128, |
| 13746 | /* VAVGR_HU */ |
| 13747 | LSX128, LSX128, LSX128, |
| 13748 | /* VAVGR_W */ |
| 13749 | LSX128, LSX128, LSX128, |
| 13750 | /* VAVGR_WU */ |
| 13751 | LSX128, LSX128, LSX128, |
| 13752 | /* VAVG_B */ |
| 13753 | LSX128, LSX128, LSX128, |
| 13754 | /* VAVG_BU */ |
| 13755 | LSX128, LSX128, LSX128, |
| 13756 | /* VAVG_D */ |
| 13757 | LSX128, LSX128, LSX128, |
| 13758 | /* VAVG_DU */ |
| 13759 | LSX128, LSX128, LSX128, |
| 13760 | /* VAVG_H */ |
| 13761 | LSX128, LSX128, LSX128, |
| 13762 | /* VAVG_HU */ |
| 13763 | LSX128, LSX128, LSX128, |
| 13764 | /* VAVG_W */ |
| 13765 | LSX128, LSX128, LSX128, |
| 13766 | /* VAVG_WU */ |
| 13767 | LSX128, LSX128, LSX128, |
| 13768 | /* VBITCLRI_B */ |
| 13769 | LSX128, LSX128, uimm3, |
| 13770 | /* VBITCLRI_D */ |
| 13771 | LSX128, LSX128, uimm6, |
| 13772 | /* VBITCLRI_H */ |
| 13773 | LSX128, LSX128, uimm4, |
| 13774 | /* VBITCLRI_W */ |
| 13775 | LSX128, LSX128, uimm5, |
| 13776 | /* VBITCLR_B */ |
| 13777 | LSX128, LSX128, LSX128, |
| 13778 | /* VBITCLR_D */ |
| 13779 | LSX128, LSX128, LSX128, |
| 13780 | /* VBITCLR_H */ |
| 13781 | LSX128, LSX128, LSX128, |
| 13782 | /* VBITCLR_W */ |
| 13783 | LSX128, LSX128, LSX128, |
| 13784 | /* VBITREVI_B */ |
| 13785 | LSX128, LSX128, uimm3, |
| 13786 | /* VBITREVI_D */ |
| 13787 | LSX128, LSX128, uimm6, |
| 13788 | /* VBITREVI_H */ |
| 13789 | LSX128, LSX128, uimm4, |
| 13790 | /* VBITREVI_W */ |
| 13791 | LSX128, LSX128, uimm5, |
| 13792 | /* VBITREV_B */ |
| 13793 | LSX128, LSX128, LSX128, |
| 13794 | /* VBITREV_D */ |
| 13795 | LSX128, LSX128, LSX128, |
| 13796 | /* VBITREV_H */ |
| 13797 | LSX128, LSX128, LSX128, |
| 13798 | /* VBITREV_W */ |
| 13799 | LSX128, LSX128, LSX128, |
| 13800 | /* VBITSELI_B */ |
| 13801 | LSX128, LSX128, LSX128, uimm8, |
| 13802 | /* VBITSEL_V */ |
| 13803 | LSX128, LSX128, LSX128, LSX128, |
| 13804 | /* VBITSETI_B */ |
| 13805 | LSX128, LSX128, uimm3, |
| 13806 | /* VBITSETI_D */ |
| 13807 | LSX128, LSX128, uimm6, |
| 13808 | /* VBITSETI_H */ |
| 13809 | LSX128, LSX128, uimm4, |
| 13810 | /* VBITSETI_W */ |
| 13811 | LSX128, LSX128, uimm5, |
| 13812 | /* VBITSET_B */ |
| 13813 | LSX128, LSX128, LSX128, |
| 13814 | /* VBITSET_D */ |
| 13815 | LSX128, LSX128, LSX128, |
| 13816 | /* VBITSET_H */ |
| 13817 | LSX128, LSX128, LSX128, |
| 13818 | /* VBITSET_W */ |
| 13819 | LSX128, LSX128, LSX128, |
| 13820 | /* VBSLL_V */ |
| 13821 | LSX128, LSX128, uimm5, |
| 13822 | /* VBSRL_V */ |
| 13823 | LSX128, LSX128, uimm5, |
| 13824 | /* VCLO_B */ |
| 13825 | LSX128, LSX128, |
| 13826 | /* VCLO_D */ |
| 13827 | LSX128, LSX128, |
| 13828 | /* VCLO_H */ |
| 13829 | LSX128, LSX128, |
| 13830 | /* VCLO_W */ |
| 13831 | LSX128, LSX128, |
| 13832 | /* VCLZ_B */ |
| 13833 | LSX128, LSX128, |
| 13834 | /* VCLZ_D */ |
| 13835 | LSX128, LSX128, |
| 13836 | /* VCLZ_H */ |
| 13837 | LSX128, LSX128, |
| 13838 | /* VCLZ_W */ |
| 13839 | LSX128, LSX128, |
| 13840 | /* VDIV_B */ |
| 13841 | LSX128, LSX128, LSX128, |
| 13842 | /* VDIV_BU */ |
| 13843 | LSX128, LSX128, LSX128, |
| 13844 | /* VDIV_D */ |
| 13845 | LSX128, LSX128, LSX128, |
| 13846 | /* VDIV_DU */ |
| 13847 | LSX128, LSX128, LSX128, |
| 13848 | /* VDIV_H */ |
| 13849 | LSX128, LSX128, LSX128, |
| 13850 | /* VDIV_HU */ |
| 13851 | LSX128, LSX128, LSX128, |
| 13852 | /* VDIV_W */ |
| 13853 | LSX128, LSX128, LSX128, |
| 13854 | /* VDIV_WU */ |
| 13855 | LSX128, LSX128, LSX128, |
| 13856 | /* VEXT2XV_DU_BU */ |
| 13857 | LASX256, LASX256, |
| 13858 | /* VEXT2XV_DU_HU */ |
| 13859 | LASX256, LASX256, |
| 13860 | /* VEXT2XV_DU_WU */ |
| 13861 | LASX256, LASX256, |
| 13862 | /* VEXT2XV_D_B */ |
| 13863 | LASX256, LASX256, |
| 13864 | /* VEXT2XV_D_H */ |
| 13865 | LASX256, LASX256, |
| 13866 | /* VEXT2XV_D_W */ |
| 13867 | LASX256, LASX256, |
| 13868 | /* VEXT2XV_HU_BU */ |
| 13869 | LASX256, LASX256, |
| 13870 | /* VEXT2XV_H_B */ |
| 13871 | LASX256, LASX256, |
| 13872 | /* VEXT2XV_WU_BU */ |
| 13873 | LASX256, LASX256, |
| 13874 | /* VEXT2XV_WU_HU */ |
| 13875 | LASX256, LASX256, |
| 13876 | /* VEXT2XV_W_B */ |
| 13877 | LASX256, LASX256, |
| 13878 | /* VEXT2XV_W_H */ |
| 13879 | LASX256, LASX256, |
| 13880 | /* VEXTH_DU_WU */ |
| 13881 | LSX128, LSX128, |
| 13882 | /* VEXTH_D_W */ |
| 13883 | LSX128, LSX128, |
| 13884 | /* VEXTH_HU_BU */ |
| 13885 | LSX128, LSX128, |
| 13886 | /* VEXTH_H_B */ |
| 13887 | LSX128, LSX128, |
| 13888 | /* VEXTH_QU_DU */ |
| 13889 | LSX128, LSX128, |
| 13890 | /* VEXTH_Q_D */ |
| 13891 | LSX128, LSX128, |
| 13892 | /* VEXTH_WU_HU */ |
| 13893 | LSX128, LSX128, |
| 13894 | /* VEXTH_W_H */ |
| 13895 | LSX128, LSX128, |
| 13896 | /* VEXTL_QU_DU */ |
| 13897 | LSX128, LSX128, |
| 13898 | /* VEXTL_Q_D */ |
| 13899 | LSX128, LSX128, |
| 13900 | /* VEXTRINS_B */ |
| 13901 | LSX128, LSX128, LSX128, uimm8, |
| 13902 | /* VEXTRINS_D */ |
| 13903 | LSX128, LSX128, LSX128, uimm8, |
| 13904 | /* VEXTRINS_H */ |
| 13905 | LSX128, LSX128, LSX128, uimm8, |
| 13906 | /* VEXTRINS_W */ |
| 13907 | LSX128, LSX128, LSX128, uimm8, |
| 13908 | /* VFADD_D */ |
| 13909 | LSX128, LSX128, LSX128, |
| 13910 | /* VFADD_S */ |
| 13911 | LSX128, LSX128, LSX128, |
| 13912 | /* VFCLASS_D */ |
| 13913 | LSX128, LSX128, |
| 13914 | /* VFCLASS_S */ |
| 13915 | LSX128, LSX128, |
| 13916 | /* VFCMP_CAF_D */ |
| 13917 | LSX128, LSX128, LSX128, |
| 13918 | /* VFCMP_CAF_S */ |
| 13919 | LSX128, LSX128, LSX128, |
| 13920 | /* VFCMP_CEQ_D */ |
| 13921 | LSX128, LSX128, LSX128, |
| 13922 | /* VFCMP_CEQ_S */ |
| 13923 | LSX128, LSX128, LSX128, |
| 13924 | /* VFCMP_CLE_D */ |
| 13925 | LSX128, LSX128, LSX128, |
| 13926 | /* VFCMP_CLE_S */ |
| 13927 | LSX128, LSX128, LSX128, |
| 13928 | /* VFCMP_CLT_D */ |
| 13929 | LSX128, LSX128, LSX128, |
| 13930 | /* VFCMP_CLT_S */ |
| 13931 | LSX128, LSX128, LSX128, |
| 13932 | /* VFCMP_CNE_D */ |
| 13933 | LSX128, LSX128, LSX128, |
| 13934 | /* VFCMP_CNE_S */ |
| 13935 | LSX128, LSX128, LSX128, |
| 13936 | /* VFCMP_COR_D */ |
| 13937 | LSX128, LSX128, LSX128, |
| 13938 | /* VFCMP_COR_S */ |
| 13939 | LSX128, LSX128, LSX128, |
| 13940 | /* VFCMP_CUEQ_D */ |
| 13941 | LSX128, LSX128, LSX128, |
| 13942 | /* VFCMP_CUEQ_S */ |
| 13943 | LSX128, LSX128, LSX128, |
| 13944 | /* VFCMP_CULE_D */ |
| 13945 | LSX128, LSX128, LSX128, |
| 13946 | /* VFCMP_CULE_S */ |
| 13947 | LSX128, LSX128, LSX128, |
| 13948 | /* VFCMP_CULT_D */ |
| 13949 | LSX128, LSX128, LSX128, |
| 13950 | /* VFCMP_CULT_S */ |
| 13951 | LSX128, LSX128, LSX128, |
| 13952 | /* VFCMP_CUNE_D */ |
| 13953 | LSX128, LSX128, LSX128, |
| 13954 | /* VFCMP_CUNE_S */ |
| 13955 | LSX128, LSX128, LSX128, |
| 13956 | /* VFCMP_CUN_D */ |
| 13957 | LSX128, LSX128, LSX128, |
| 13958 | /* VFCMP_CUN_S */ |
| 13959 | LSX128, LSX128, LSX128, |
| 13960 | /* VFCMP_SAF_D */ |
| 13961 | LSX128, LSX128, LSX128, |
| 13962 | /* VFCMP_SAF_S */ |
| 13963 | LSX128, LSX128, LSX128, |
| 13964 | /* VFCMP_SEQ_D */ |
| 13965 | LSX128, LSX128, LSX128, |
| 13966 | /* VFCMP_SEQ_S */ |
| 13967 | LSX128, LSX128, LSX128, |
| 13968 | /* VFCMP_SLE_D */ |
| 13969 | LSX128, LSX128, LSX128, |
| 13970 | /* VFCMP_SLE_S */ |
| 13971 | LSX128, LSX128, LSX128, |
| 13972 | /* VFCMP_SLT_D */ |
| 13973 | LSX128, LSX128, LSX128, |
| 13974 | /* VFCMP_SLT_S */ |
| 13975 | LSX128, LSX128, LSX128, |
| 13976 | /* VFCMP_SNE_D */ |
| 13977 | LSX128, LSX128, LSX128, |
| 13978 | /* VFCMP_SNE_S */ |
| 13979 | LSX128, LSX128, LSX128, |
| 13980 | /* VFCMP_SOR_D */ |
| 13981 | LSX128, LSX128, LSX128, |
| 13982 | /* VFCMP_SOR_S */ |
| 13983 | LSX128, LSX128, LSX128, |
| 13984 | /* VFCMP_SUEQ_D */ |
| 13985 | LSX128, LSX128, LSX128, |
| 13986 | /* VFCMP_SUEQ_S */ |
| 13987 | LSX128, LSX128, LSX128, |
| 13988 | /* VFCMP_SULE_D */ |
| 13989 | LSX128, LSX128, LSX128, |
| 13990 | /* VFCMP_SULE_S */ |
| 13991 | LSX128, LSX128, LSX128, |
| 13992 | /* VFCMP_SULT_D */ |
| 13993 | LSX128, LSX128, LSX128, |
| 13994 | /* VFCMP_SULT_S */ |
| 13995 | LSX128, LSX128, LSX128, |
| 13996 | /* VFCMP_SUNE_D */ |
| 13997 | LSX128, LSX128, LSX128, |
| 13998 | /* VFCMP_SUNE_S */ |
| 13999 | LSX128, LSX128, LSX128, |
| 14000 | /* VFCMP_SUN_D */ |
| 14001 | LSX128, LSX128, LSX128, |
| 14002 | /* VFCMP_SUN_S */ |
| 14003 | LSX128, LSX128, LSX128, |
| 14004 | /* VFCVTH_D_S */ |
| 14005 | LSX128, LSX128, |
| 14006 | /* VFCVTH_S_H */ |
| 14007 | LSX128, LSX128, |
| 14008 | /* VFCVTL_D_S */ |
| 14009 | LSX128, LSX128, |
| 14010 | /* VFCVTL_S_H */ |
| 14011 | LSX128, LSX128, |
| 14012 | /* VFCVT_H_S */ |
| 14013 | LSX128, LSX128, LSX128, |
| 14014 | /* VFCVT_S_D */ |
| 14015 | LSX128, LSX128, LSX128, |
| 14016 | /* VFDIV_D */ |
| 14017 | LSX128, LSX128, LSX128, |
| 14018 | /* VFDIV_S */ |
| 14019 | LSX128, LSX128, LSX128, |
| 14020 | /* VFFINTH_D_W */ |
| 14021 | LSX128, LSX128, |
| 14022 | /* VFFINTL_D_W */ |
| 14023 | LSX128, LSX128, |
| 14024 | /* VFFINT_D_L */ |
| 14025 | LSX128, LSX128, |
| 14026 | /* VFFINT_D_LU */ |
| 14027 | LSX128, LSX128, |
| 14028 | /* VFFINT_S_L */ |
| 14029 | LSX128, LSX128, LSX128, |
| 14030 | /* VFFINT_S_W */ |
| 14031 | LSX128, LSX128, |
| 14032 | /* VFFINT_S_WU */ |
| 14033 | LSX128, LSX128, |
| 14034 | /* VFLOGB_D */ |
| 14035 | LSX128, LSX128, |
| 14036 | /* VFLOGB_S */ |
| 14037 | LSX128, LSX128, |
| 14038 | /* VFMADD_D */ |
| 14039 | LSX128, LSX128, LSX128, LSX128, |
| 14040 | /* VFMADD_S */ |
| 14041 | LSX128, LSX128, LSX128, LSX128, |
| 14042 | /* VFMAXA_D */ |
| 14043 | LSX128, LSX128, LSX128, |
| 14044 | /* VFMAXA_S */ |
| 14045 | LSX128, LSX128, LSX128, |
| 14046 | /* VFMAX_D */ |
| 14047 | LSX128, LSX128, LSX128, |
| 14048 | /* VFMAX_S */ |
| 14049 | LSX128, LSX128, LSX128, |
| 14050 | /* VFMINA_D */ |
| 14051 | LSX128, LSX128, LSX128, |
| 14052 | /* VFMINA_S */ |
| 14053 | LSX128, LSX128, LSX128, |
| 14054 | /* VFMIN_D */ |
| 14055 | LSX128, LSX128, LSX128, |
| 14056 | /* VFMIN_S */ |
| 14057 | LSX128, LSX128, LSX128, |
| 14058 | /* VFMSUB_D */ |
| 14059 | LSX128, LSX128, LSX128, LSX128, |
| 14060 | /* VFMSUB_S */ |
| 14061 | LSX128, LSX128, LSX128, LSX128, |
| 14062 | /* VFMUL_D */ |
| 14063 | LSX128, LSX128, LSX128, |
| 14064 | /* VFMUL_S */ |
| 14065 | LSX128, LSX128, LSX128, |
| 14066 | /* VFNMADD_D */ |
| 14067 | LSX128, LSX128, LSX128, LSX128, |
| 14068 | /* VFNMADD_S */ |
| 14069 | LSX128, LSX128, LSX128, LSX128, |
| 14070 | /* VFNMSUB_D */ |
| 14071 | LSX128, LSX128, LSX128, LSX128, |
| 14072 | /* VFNMSUB_S */ |
| 14073 | LSX128, LSX128, LSX128, LSX128, |
| 14074 | /* VFRECIPE_D */ |
| 14075 | LSX128, LSX128, |
| 14076 | /* VFRECIPE_S */ |
| 14077 | LSX128, LSX128, |
| 14078 | /* VFRECIP_D */ |
| 14079 | LSX128, LSX128, |
| 14080 | /* VFRECIP_S */ |
| 14081 | LSX128, LSX128, |
| 14082 | /* VFRINTRM_D */ |
| 14083 | LSX128, LSX128, |
| 14084 | /* VFRINTRM_S */ |
| 14085 | LSX128, LSX128, |
| 14086 | /* VFRINTRNE_D */ |
| 14087 | LSX128, LSX128, |
| 14088 | /* VFRINTRNE_S */ |
| 14089 | LSX128, LSX128, |
| 14090 | /* VFRINTRP_D */ |
| 14091 | LSX128, LSX128, |
| 14092 | /* VFRINTRP_S */ |
| 14093 | LSX128, LSX128, |
| 14094 | /* VFRINTRZ_D */ |
| 14095 | LSX128, LSX128, |
| 14096 | /* VFRINTRZ_S */ |
| 14097 | LSX128, LSX128, |
| 14098 | /* VFRINT_D */ |
| 14099 | LSX128, LSX128, |
| 14100 | /* VFRINT_S */ |
| 14101 | LSX128, LSX128, |
| 14102 | /* VFRSQRTE_D */ |
| 14103 | LSX128, LSX128, |
| 14104 | /* VFRSQRTE_S */ |
| 14105 | LSX128, LSX128, |
| 14106 | /* VFRSQRT_D */ |
| 14107 | LSX128, LSX128, |
| 14108 | /* VFRSQRT_S */ |
| 14109 | LSX128, LSX128, |
| 14110 | /* VFRSTPI_B */ |
| 14111 | LSX128, LSX128, LSX128, uimm5, |
| 14112 | /* VFRSTPI_H */ |
| 14113 | LSX128, LSX128, LSX128, uimm5, |
| 14114 | /* VFRSTP_B */ |
| 14115 | LSX128, LSX128, LSX128, LSX128, |
| 14116 | /* VFRSTP_H */ |
| 14117 | LSX128, LSX128, LSX128, LSX128, |
| 14118 | /* VFSQRT_D */ |
| 14119 | LSX128, LSX128, |
| 14120 | /* VFSQRT_S */ |
| 14121 | LSX128, LSX128, |
| 14122 | /* VFSUB_D */ |
| 14123 | LSX128, LSX128, LSX128, |
| 14124 | /* VFSUB_S */ |
| 14125 | LSX128, LSX128, LSX128, |
| 14126 | /* VFTINTH_L_S */ |
| 14127 | LSX128, LSX128, |
| 14128 | /* VFTINTL_L_S */ |
| 14129 | LSX128, LSX128, |
| 14130 | /* VFTINTRMH_L_S */ |
| 14131 | LSX128, LSX128, |
| 14132 | /* VFTINTRML_L_S */ |
| 14133 | LSX128, LSX128, |
| 14134 | /* VFTINTRM_L_D */ |
| 14135 | LSX128, LSX128, |
| 14136 | /* VFTINTRM_W_D */ |
| 14137 | LSX128, LSX128, LSX128, |
| 14138 | /* VFTINTRM_W_S */ |
| 14139 | LSX128, LSX128, |
| 14140 | /* VFTINTRNEH_L_S */ |
| 14141 | LSX128, LSX128, |
| 14142 | /* VFTINTRNEL_L_S */ |
| 14143 | LSX128, LSX128, |
| 14144 | /* VFTINTRNE_L_D */ |
| 14145 | LSX128, LSX128, |
| 14146 | /* VFTINTRNE_W_D */ |
| 14147 | LSX128, LSX128, LSX128, |
| 14148 | /* VFTINTRNE_W_S */ |
| 14149 | LSX128, LSX128, |
| 14150 | /* VFTINTRPH_L_S */ |
| 14151 | LSX128, LSX128, |
| 14152 | /* VFTINTRPL_L_S */ |
| 14153 | LSX128, LSX128, |
| 14154 | /* VFTINTRP_L_D */ |
| 14155 | LSX128, LSX128, |
| 14156 | /* VFTINTRP_W_D */ |
| 14157 | LSX128, LSX128, LSX128, |
| 14158 | /* VFTINTRP_W_S */ |
| 14159 | LSX128, LSX128, |
| 14160 | /* VFTINTRZH_L_S */ |
| 14161 | LSX128, LSX128, |
| 14162 | /* VFTINTRZL_L_S */ |
| 14163 | LSX128, LSX128, |
| 14164 | /* VFTINTRZ_LU_D */ |
| 14165 | LSX128, LSX128, |
| 14166 | /* VFTINTRZ_L_D */ |
| 14167 | LSX128, LSX128, |
| 14168 | /* VFTINTRZ_WU_S */ |
| 14169 | LSX128, LSX128, |
| 14170 | /* VFTINTRZ_W_D */ |
| 14171 | LSX128, LSX128, LSX128, |
| 14172 | /* VFTINTRZ_W_S */ |
| 14173 | LSX128, LSX128, |
| 14174 | /* VFTINT_LU_D */ |
| 14175 | LSX128, LSX128, |
| 14176 | /* VFTINT_L_D */ |
| 14177 | LSX128, LSX128, |
| 14178 | /* VFTINT_WU_S */ |
| 14179 | LSX128, LSX128, |
| 14180 | /* VFTINT_W_D */ |
| 14181 | LSX128, LSX128, LSX128, |
| 14182 | /* VFTINT_W_S */ |
| 14183 | LSX128, LSX128, |
| 14184 | /* VHADDW_DU_WU */ |
| 14185 | LSX128, LSX128, LSX128, |
| 14186 | /* VHADDW_D_W */ |
| 14187 | LSX128, LSX128, LSX128, |
| 14188 | /* VHADDW_HU_BU */ |
| 14189 | LSX128, LSX128, LSX128, |
| 14190 | /* VHADDW_H_B */ |
| 14191 | LSX128, LSX128, LSX128, |
| 14192 | /* VHADDW_QU_DU */ |
| 14193 | LSX128, LSX128, LSX128, |
| 14194 | /* VHADDW_Q_D */ |
| 14195 | LSX128, LSX128, LSX128, |
| 14196 | /* VHADDW_WU_HU */ |
| 14197 | LSX128, LSX128, LSX128, |
| 14198 | /* VHADDW_W_H */ |
| 14199 | LSX128, LSX128, LSX128, |
| 14200 | /* VHSUBW_DU_WU */ |
| 14201 | LSX128, LSX128, LSX128, |
| 14202 | /* VHSUBW_D_W */ |
| 14203 | LSX128, LSX128, LSX128, |
| 14204 | /* VHSUBW_HU_BU */ |
| 14205 | LSX128, LSX128, LSX128, |
| 14206 | /* VHSUBW_H_B */ |
| 14207 | LSX128, LSX128, LSX128, |
| 14208 | /* VHSUBW_QU_DU */ |
| 14209 | LSX128, LSX128, LSX128, |
| 14210 | /* VHSUBW_Q_D */ |
| 14211 | LSX128, LSX128, LSX128, |
| 14212 | /* VHSUBW_WU_HU */ |
| 14213 | LSX128, LSX128, LSX128, |
| 14214 | /* VHSUBW_W_H */ |
| 14215 | LSX128, LSX128, LSX128, |
| 14216 | /* VILVH_B */ |
| 14217 | LSX128, LSX128, LSX128, |
| 14218 | /* VILVH_D */ |
| 14219 | LSX128, LSX128, LSX128, |
| 14220 | /* VILVH_H */ |
| 14221 | LSX128, LSX128, LSX128, |
| 14222 | /* VILVH_W */ |
| 14223 | LSX128, LSX128, LSX128, |
| 14224 | /* VILVL_B */ |
| 14225 | LSX128, LSX128, LSX128, |
| 14226 | /* VILVL_D */ |
| 14227 | LSX128, LSX128, LSX128, |
| 14228 | /* VILVL_H */ |
| 14229 | LSX128, LSX128, LSX128, |
| 14230 | /* VILVL_W */ |
| 14231 | LSX128, LSX128, LSX128, |
| 14232 | /* VINSGR2VR_B */ |
| 14233 | LSX128, LSX128, GPR, uimm4, |
| 14234 | /* VINSGR2VR_D */ |
| 14235 | LSX128, LSX128, GPR, uimm1, |
| 14236 | /* VINSGR2VR_H */ |
| 14237 | LSX128, LSX128, GPR, uimm3, |
| 14238 | /* VINSGR2VR_W */ |
| 14239 | LSX128, LSX128, GPR, uimm2, |
| 14240 | /* VLD */ |
| 14241 | LSX128, GPR, simm12, |
| 14242 | /* VLDI */ |
| 14243 | LSX128, simm13, |
| 14244 | /* VLDREPL_B */ |
| 14245 | LSX128, GPR, simm12, |
| 14246 | /* VLDREPL_D */ |
| 14247 | LSX128, GPR, simm9_lsl3, |
| 14248 | /* VLDREPL_H */ |
| 14249 | LSX128, GPR, simm11_lsl1, |
| 14250 | /* VLDREPL_W */ |
| 14251 | LSX128, GPR, simm10_lsl2, |
| 14252 | /* VLDX */ |
| 14253 | LSX128, GPR, GPR, |
| 14254 | /* VMADDWEV_D_W */ |
| 14255 | LSX128, LSX128, LSX128, LSX128, |
| 14256 | /* VMADDWEV_D_WU */ |
| 14257 | LSX128, LSX128, LSX128, LSX128, |
| 14258 | /* VMADDWEV_D_WU_W */ |
| 14259 | LSX128, LSX128, LSX128, LSX128, |
| 14260 | /* VMADDWEV_H_B */ |
| 14261 | LSX128, LSX128, LSX128, LSX128, |
| 14262 | /* VMADDWEV_H_BU */ |
| 14263 | LSX128, LSX128, LSX128, LSX128, |
| 14264 | /* VMADDWEV_H_BU_B */ |
| 14265 | LSX128, LSX128, LSX128, LSX128, |
| 14266 | /* VMADDWEV_Q_D */ |
| 14267 | LSX128, LSX128, LSX128, LSX128, |
| 14268 | /* VMADDWEV_Q_DU */ |
| 14269 | LSX128, LSX128, LSX128, LSX128, |
| 14270 | /* VMADDWEV_Q_DU_D */ |
| 14271 | LSX128, LSX128, LSX128, LSX128, |
| 14272 | /* VMADDWEV_W_H */ |
| 14273 | LSX128, LSX128, LSX128, LSX128, |
| 14274 | /* VMADDWEV_W_HU */ |
| 14275 | LSX128, LSX128, LSX128, LSX128, |
| 14276 | /* VMADDWEV_W_HU_H */ |
| 14277 | LSX128, LSX128, LSX128, LSX128, |
| 14278 | /* VMADDWOD_D_W */ |
| 14279 | LSX128, LSX128, LSX128, LSX128, |
| 14280 | /* VMADDWOD_D_WU */ |
| 14281 | LSX128, LSX128, LSX128, LSX128, |
| 14282 | /* VMADDWOD_D_WU_W */ |
| 14283 | LSX128, LSX128, LSX128, LSX128, |
| 14284 | /* VMADDWOD_H_B */ |
| 14285 | LSX128, LSX128, LSX128, LSX128, |
| 14286 | /* VMADDWOD_H_BU */ |
| 14287 | LSX128, LSX128, LSX128, LSX128, |
| 14288 | /* VMADDWOD_H_BU_B */ |
| 14289 | LSX128, LSX128, LSX128, LSX128, |
| 14290 | /* VMADDWOD_Q_D */ |
| 14291 | LSX128, LSX128, LSX128, LSX128, |
| 14292 | /* VMADDWOD_Q_DU */ |
| 14293 | LSX128, LSX128, LSX128, LSX128, |
| 14294 | /* VMADDWOD_Q_DU_D */ |
| 14295 | LSX128, LSX128, LSX128, LSX128, |
| 14296 | /* VMADDWOD_W_H */ |
| 14297 | LSX128, LSX128, LSX128, LSX128, |
| 14298 | /* VMADDWOD_W_HU */ |
| 14299 | LSX128, LSX128, LSX128, LSX128, |
| 14300 | /* VMADDWOD_W_HU_H */ |
| 14301 | LSX128, LSX128, LSX128, LSX128, |
| 14302 | /* VMADD_B */ |
| 14303 | LSX128, LSX128, LSX128, LSX128, |
| 14304 | /* VMADD_D */ |
| 14305 | LSX128, LSX128, LSX128, LSX128, |
| 14306 | /* VMADD_H */ |
| 14307 | LSX128, LSX128, LSX128, LSX128, |
| 14308 | /* VMADD_W */ |
| 14309 | LSX128, LSX128, LSX128, LSX128, |
| 14310 | /* VMAXI_B */ |
| 14311 | LSX128, LSX128, simm5, |
| 14312 | /* VMAXI_BU */ |
| 14313 | LSX128, LSX128, uimm5, |
| 14314 | /* VMAXI_D */ |
| 14315 | LSX128, LSX128, simm5, |
| 14316 | /* VMAXI_DU */ |
| 14317 | LSX128, LSX128, uimm5, |
| 14318 | /* VMAXI_H */ |
| 14319 | LSX128, LSX128, simm5, |
| 14320 | /* VMAXI_HU */ |
| 14321 | LSX128, LSX128, uimm5, |
| 14322 | /* VMAXI_W */ |
| 14323 | LSX128, LSX128, simm5, |
| 14324 | /* VMAXI_WU */ |
| 14325 | LSX128, LSX128, uimm5, |
| 14326 | /* VMAX_B */ |
| 14327 | LSX128, LSX128, LSX128, |
| 14328 | /* VMAX_BU */ |
| 14329 | LSX128, LSX128, LSX128, |
| 14330 | /* VMAX_D */ |
| 14331 | LSX128, LSX128, LSX128, |
| 14332 | /* VMAX_DU */ |
| 14333 | LSX128, LSX128, LSX128, |
| 14334 | /* VMAX_H */ |
| 14335 | LSX128, LSX128, LSX128, |
| 14336 | /* VMAX_HU */ |
| 14337 | LSX128, LSX128, LSX128, |
| 14338 | /* VMAX_W */ |
| 14339 | LSX128, LSX128, LSX128, |
| 14340 | /* VMAX_WU */ |
| 14341 | LSX128, LSX128, LSX128, |
| 14342 | /* VMINI_B */ |
| 14343 | LSX128, LSX128, simm5, |
| 14344 | /* VMINI_BU */ |
| 14345 | LSX128, LSX128, uimm5, |
| 14346 | /* VMINI_D */ |
| 14347 | LSX128, LSX128, simm5, |
| 14348 | /* VMINI_DU */ |
| 14349 | LSX128, LSX128, uimm5, |
| 14350 | /* VMINI_H */ |
| 14351 | LSX128, LSX128, simm5, |
| 14352 | /* VMINI_HU */ |
| 14353 | LSX128, LSX128, uimm5, |
| 14354 | /* VMINI_W */ |
| 14355 | LSX128, LSX128, simm5, |
| 14356 | /* VMINI_WU */ |
| 14357 | LSX128, LSX128, uimm5, |
| 14358 | /* VMIN_B */ |
| 14359 | LSX128, LSX128, LSX128, |
| 14360 | /* VMIN_BU */ |
| 14361 | LSX128, LSX128, LSX128, |
| 14362 | /* VMIN_D */ |
| 14363 | LSX128, LSX128, LSX128, |
| 14364 | /* VMIN_DU */ |
| 14365 | LSX128, LSX128, LSX128, |
| 14366 | /* VMIN_H */ |
| 14367 | LSX128, LSX128, LSX128, |
| 14368 | /* VMIN_HU */ |
| 14369 | LSX128, LSX128, LSX128, |
| 14370 | /* VMIN_W */ |
| 14371 | LSX128, LSX128, LSX128, |
| 14372 | /* VMIN_WU */ |
| 14373 | LSX128, LSX128, LSX128, |
| 14374 | /* VMOD_B */ |
| 14375 | LSX128, LSX128, LSX128, |
| 14376 | /* VMOD_BU */ |
| 14377 | LSX128, LSX128, LSX128, |
| 14378 | /* VMOD_D */ |
| 14379 | LSX128, LSX128, LSX128, |
| 14380 | /* VMOD_DU */ |
| 14381 | LSX128, LSX128, LSX128, |
| 14382 | /* VMOD_H */ |
| 14383 | LSX128, LSX128, LSX128, |
| 14384 | /* VMOD_HU */ |
| 14385 | LSX128, LSX128, LSX128, |
| 14386 | /* VMOD_W */ |
| 14387 | LSX128, LSX128, LSX128, |
| 14388 | /* VMOD_WU */ |
| 14389 | LSX128, LSX128, LSX128, |
| 14390 | /* VMSKGEZ_B */ |
| 14391 | LSX128, LSX128, |
| 14392 | /* VMSKLTZ_B */ |
| 14393 | LSX128, LSX128, |
| 14394 | /* VMSKLTZ_D */ |
| 14395 | LSX128, LSX128, |
| 14396 | /* VMSKLTZ_H */ |
| 14397 | LSX128, LSX128, |
| 14398 | /* VMSKLTZ_W */ |
| 14399 | LSX128, LSX128, |
| 14400 | /* VMSKNZ_B */ |
| 14401 | LSX128, LSX128, |
| 14402 | /* VMSUB_B */ |
| 14403 | LSX128, LSX128, LSX128, LSX128, |
| 14404 | /* VMSUB_D */ |
| 14405 | LSX128, LSX128, LSX128, LSX128, |
| 14406 | /* VMSUB_H */ |
| 14407 | LSX128, LSX128, LSX128, LSX128, |
| 14408 | /* VMSUB_W */ |
| 14409 | LSX128, LSX128, LSX128, LSX128, |
| 14410 | /* VMUH_B */ |
| 14411 | LSX128, LSX128, LSX128, |
| 14412 | /* VMUH_BU */ |
| 14413 | LSX128, LSX128, LSX128, |
| 14414 | /* VMUH_D */ |
| 14415 | LSX128, LSX128, LSX128, |
| 14416 | /* VMUH_DU */ |
| 14417 | LSX128, LSX128, LSX128, |
| 14418 | /* VMUH_H */ |
| 14419 | LSX128, LSX128, LSX128, |
| 14420 | /* VMUH_HU */ |
| 14421 | LSX128, LSX128, LSX128, |
| 14422 | /* VMUH_W */ |
| 14423 | LSX128, LSX128, LSX128, |
| 14424 | /* VMUH_WU */ |
| 14425 | LSX128, LSX128, LSX128, |
| 14426 | /* VMULWEV_D_W */ |
| 14427 | LSX128, LSX128, LSX128, |
| 14428 | /* VMULWEV_D_WU */ |
| 14429 | LSX128, LSX128, LSX128, |
| 14430 | /* VMULWEV_D_WU_W */ |
| 14431 | LSX128, LSX128, LSX128, |
| 14432 | /* VMULWEV_H_B */ |
| 14433 | LSX128, LSX128, LSX128, |
| 14434 | /* VMULWEV_H_BU */ |
| 14435 | LSX128, LSX128, LSX128, |
| 14436 | /* VMULWEV_H_BU_B */ |
| 14437 | LSX128, LSX128, LSX128, |
| 14438 | /* VMULWEV_Q_D */ |
| 14439 | LSX128, LSX128, LSX128, |
| 14440 | /* VMULWEV_Q_DU */ |
| 14441 | LSX128, LSX128, LSX128, |
| 14442 | /* VMULWEV_Q_DU_D */ |
| 14443 | LSX128, LSX128, LSX128, |
| 14444 | /* VMULWEV_W_H */ |
| 14445 | LSX128, LSX128, LSX128, |
| 14446 | /* VMULWEV_W_HU */ |
| 14447 | LSX128, LSX128, LSX128, |
| 14448 | /* VMULWEV_W_HU_H */ |
| 14449 | LSX128, LSX128, LSX128, |
| 14450 | /* VMULWOD_D_W */ |
| 14451 | LSX128, LSX128, LSX128, |
| 14452 | /* VMULWOD_D_WU */ |
| 14453 | LSX128, LSX128, LSX128, |
| 14454 | /* VMULWOD_D_WU_W */ |
| 14455 | LSX128, LSX128, LSX128, |
| 14456 | /* VMULWOD_H_B */ |
| 14457 | LSX128, LSX128, LSX128, |
| 14458 | /* VMULWOD_H_BU */ |
| 14459 | LSX128, LSX128, LSX128, |
| 14460 | /* VMULWOD_H_BU_B */ |
| 14461 | LSX128, LSX128, LSX128, |
| 14462 | /* VMULWOD_Q_D */ |
| 14463 | LSX128, LSX128, LSX128, |
| 14464 | /* VMULWOD_Q_DU */ |
| 14465 | LSX128, LSX128, LSX128, |
| 14466 | /* VMULWOD_Q_DU_D */ |
| 14467 | LSX128, LSX128, LSX128, |
| 14468 | /* VMULWOD_W_H */ |
| 14469 | LSX128, LSX128, LSX128, |
| 14470 | /* VMULWOD_W_HU */ |
| 14471 | LSX128, LSX128, LSX128, |
| 14472 | /* VMULWOD_W_HU_H */ |
| 14473 | LSX128, LSX128, LSX128, |
| 14474 | /* VMUL_B */ |
| 14475 | LSX128, LSX128, LSX128, |
| 14476 | /* VMUL_D */ |
| 14477 | LSX128, LSX128, LSX128, |
| 14478 | /* VMUL_H */ |
| 14479 | LSX128, LSX128, LSX128, |
| 14480 | /* VMUL_W */ |
| 14481 | LSX128, LSX128, LSX128, |
| 14482 | /* VNEG_B */ |
| 14483 | LSX128, LSX128, |
| 14484 | /* VNEG_D */ |
| 14485 | LSX128, LSX128, |
| 14486 | /* VNEG_H */ |
| 14487 | LSX128, LSX128, |
| 14488 | /* VNEG_W */ |
| 14489 | LSX128, LSX128, |
| 14490 | /* VNORI_B */ |
| 14491 | LSX128, LSX128, uimm8, |
| 14492 | /* VNOR_V */ |
| 14493 | LSX128, LSX128, LSX128, |
| 14494 | /* VORI_B */ |
| 14495 | LSX128, LSX128, uimm8, |
| 14496 | /* VORN_V */ |
| 14497 | LSX128, LSX128, LSX128, |
| 14498 | /* VOR_V */ |
| 14499 | LSX128, LSX128, LSX128, |
| 14500 | /* VPACKEV_B */ |
| 14501 | LSX128, LSX128, LSX128, |
| 14502 | /* VPACKEV_D */ |
| 14503 | LSX128, LSX128, LSX128, |
| 14504 | /* VPACKEV_H */ |
| 14505 | LSX128, LSX128, LSX128, |
| 14506 | /* VPACKEV_W */ |
| 14507 | LSX128, LSX128, LSX128, |
| 14508 | /* VPACKOD_B */ |
| 14509 | LSX128, LSX128, LSX128, |
| 14510 | /* VPACKOD_D */ |
| 14511 | LSX128, LSX128, LSX128, |
| 14512 | /* VPACKOD_H */ |
| 14513 | LSX128, LSX128, LSX128, |
| 14514 | /* VPACKOD_W */ |
| 14515 | LSX128, LSX128, LSX128, |
| 14516 | /* VPCNT_B */ |
| 14517 | LSX128, LSX128, |
| 14518 | /* VPCNT_D */ |
| 14519 | LSX128, LSX128, |
| 14520 | /* VPCNT_H */ |
| 14521 | LSX128, LSX128, |
| 14522 | /* VPCNT_W */ |
| 14523 | LSX128, LSX128, |
| 14524 | /* VPERMI_W */ |
| 14525 | LSX128, LSX128, LSX128, uimm8, |
| 14526 | /* VPICKEV_B */ |
| 14527 | LSX128, LSX128, LSX128, |
| 14528 | /* VPICKEV_D */ |
| 14529 | LSX128, LSX128, LSX128, |
| 14530 | /* VPICKEV_H */ |
| 14531 | LSX128, LSX128, LSX128, |
| 14532 | /* VPICKEV_W */ |
| 14533 | LSX128, LSX128, LSX128, |
| 14534 | /* VPICKOD_B */ |
| 14535 | LSX128, LSX128, LSX128, |
| 14536 | /* VPICKOD_D */ |
| 14537 | LSX128, LSX128, LSX128, |
| 14538 | /* VPICKOD_H */ |
| 14539 | LSX128, LSX128, LSX128, |
| 14540 | /* VPICKOD_W */ |
| 14541 | LSX128, LSX128, LSX128, |
| 14542 | /* VPICKVE2GR_B */ |
| 14543 | GPR, LSX128, uimm4, |
| 14544 | /* VPICKVE2GR_BU */ |
| 14545 | GPR, LSX128, uimm4, |
| 14546 | /* VPICKVE2GR_D */ |
| 14547 | GPR, LSX128, uimm1, |
| 14548 | /* VPICKVE2GR_DU */ |
| 14549 | GPR, LSX128, uimm1, |
| 14550 | /* VPICKVE2GR_H */ |
| 14551 | GPR, LSX128, uimm3, |
| 14552 | /* VPICKVE2GR_HU */ |
| 14553 | GPR, LSX128, uimm3, |
| 14554 | /* VPICKVE2GR_W */ |
| 14555 | GPR, LSX128, uimm2, |
| 14556 | /* VPICKVE2GR_WU */ |
| 14557 | GPR, LSX128, uimm2, |
| 14558 | /* VREPLGR2VR_B */ |
| 14559 | LSX128, GPR, |
| 14560 | /* VREPLGR2VR_D */ |
| 14561 | LSX128, GPR, |
| 14562 | /* VREPLGR2VR_H */ |
| 14563 | LSX128, GPR, |
| 14564 | /* VREPLGR2VR_W */ |
| 14565 | LSX128, GPR, |
| 14566 | /* VREPLVEI_B */ |
| 14567 | LSX128, LSX128, uimm4, |
| 14568 | /* VREPLVEI_D */ |
| 14569 | LSX128, LSX128, uimm1, |
| 14570 | /* VREPLVEI_H */ |
| 14571 | LSX128, LSX128, uimm3, |
| 14572 | /* VREPLVEI_W */ |
| 14573 | LSX128, LSX128, uimm2, |
| 14574 | /* VREPLVE_B */ |
| 14575 | LSX128, LSX128, GPR, |
| 14576 | /* VREPLVE_D */ |
| 14577 | LSX128, LSX128, GPR, |
| 14578 | /* VREPLVE_H */ |
| 14579 | LSX128, LSX128, GPR, |
| 14580 | /* VREPLVE_W */ |
| 14581 | LSX128, LSX128, GPR, |
| 14582 | /* VROTRI_B */ |
| 14583 | LSX128, LSX128, uimm3, |
| 14584 | /* VROTRI_D */ |
| 14585 | LSX128, LSX128, uimm6, |
| 14586 | /* VROTRI_H */ |
| 14587 | LSX128, LSX128, uimm4, |
| 14588 | /* VROTRI_W */ |
| 14589 | LSX128, LSX128, uimm5, |
| 14590 | /* VROTR_B */ |
| 14591 | LSX128, LSX128, LSX128, |
| 14592 | /* VROTR_D */ |
| 14593 | LSX128, LSX128, LSX128, |
| 14594 | /* VROTR_H */ |
| 14595 | LSX128, LSX128, LSX128, |
| 14596 | /* VROTR_W */ |
| 14597 | LSX128, LSX128, LSX128, |
| 14598 | /* VSADD_B */ |
| 14599 | LSX128, LSX128, LSX128, |
| 14600 | /* VSADD_BU */ |
| 14601 | LSX128, LSX128, LSX128, |
| 14602 | /* VSADD_D */ |
| 14603 | LSX128, LSX128, LSX128, |
| 14604 | /* VSADD_DU */ |
| 14605 | LSX128, LSX128, LSX128, |
| 14606 | /* VSADD_H */ |
| 14607 | LSX128, LSX128, LSX128, |
| 14608 | /* VSADD_HU */ |
| 14609 | LSX128, LSX128, LSX128, |
| 14610 | /* VSADD_W */ |
| 14611 | LSX128, LSX128, LSX128, |
| 14612 | /* VSADD_WU */ |
| 14613 | LSX128, LSX128, LSX128, |
| 14614 | /* VSAT_B */ |
| 14615 | LSX128, LSX128, uimm3, |
| 14616 | /* VSAT_BU */ |
| 14617 | LSX128, LSX128, uimm3, |
| 14618 | /* VSAT_D */ |
| 14619 | LSX128, LSX128, uimm6, |
| 14620 | /* VSAT_DU */ |
| 14621 | LSX128, LSX128, uimm6, |
| 14622 | /* VSAT_H */ |
| 14623 | LSX128, LSX128, uimm4, |
| 14624 | /* VSAT_HU */ |
| 14625 | LSX128, LSX128, uimm4, |
| 14626 | /* VSAT_W */ |
| 14627 | LSX128, LSX128, uimm5, |
| 14628 | /* VSAT_WU */ |
| 14629 | LSX128, LSX128, uimm5, |
| 14630 | /* VSEQI_B */ |
| 14631 | LSX128, LSX128, simm5, |
| 14632 | /* VSEQI_D */ |
| 14633 | LSX128, LSX128, simm5, |
| 14634 | /* VSEQI_H */ |
| 14635 | LSX128, LSX128, simm5, |
| 14636 | /* VSEQI_W */ |
| 14637 | LSX128, LSX128, simm5, |
| 14638 | /* VSEQ_B */ |
| 14639 | LSX128, LSX128, LSX128, |
| 14640 | /* VSEQ_D */ |
| 14641 | LSX128, LSX128, LSX128, |
| 14642 | /* VSEQ_H */ |
| 14643 | LSX128, LSX128, LSX128, |
| 14644 | /* VSEQ_W */ |
| 14645 | LSX128, LSX128, LSX128, |
| 14646 | /* VSETALLNEZ_B */ |
| 14647 | CFR, LSX128, |
| 14648 | /* VSETALLNEZ_D */ |
| 14649 | CFR, LSX128, |
| 14650 | /* VSETALLNEZ_H */ |
| 14651 | CFR, LSX128, |
| 14652 | /* VSETALLNEZ_W */ |
| 14653 | CFR, LSX128, |
| 14654 | /* VSETANYEQZ_B */ |
| 14655 | CFR, LSX128, |
| 14656 | /* VSETANYEQZ_D */ |
| 14657 | CFR, LSX128, |
| 14658 | /* VSETANYEQZ_H */ |
| 14659 | CFR, LSX128, |
| 14660 | /* VSETANYEQZ_W */ |
| 14661 | CFR, LSX128, |
| 14662 | /* VSETEQZ_V */ |
| 14663 | CFR, LSX128, |
| 14664 | /* VSETNEZ_V */ |
| 14665 | CFR, LSX128, |
| 14666 | /* VSHUF4I_B */ |
| 14667 | LSX128, LSX128, uimm8, |
| 14668 | /* VSHUF4I_D */ |
| 14669 | LSX128, LSX128, LSX128, uimm8, |
| 14670 | /* VSHUF4I_H */ |
| 14671 | LSX128, LSX128, uimm8, |
| 14672 | /* VSHUF4I_W */ |
| 14673 | LSX128, LSX128, uimm8, |
| 14674 | /* VSHUF_B */ |
| 14675 | LSX128, LSX128, LSX128, LSX128, |
| 14676 | /* VSHUF_D */ |
| 14677 | LSX128, LSX128, LSX128, LSX128, |
| 14678 | /* VSHUF_H */ |
| 14679 | LSX128, LSX128, LSX128, LSX128, |
| 14680 | /* VSHUF_W */ |
| 14681 | LSX128, LSX128, LSX128, LSX128, |
| 14682 | /* VSIGNCOV_B */ |
| 14683 | LSX128, LSX128, LSX128, |
| 14684 | /* VSIGNCOV_D */ |
| 14685 | LSX128, LSX128, LSX128, |
| 14686 | /* VSIGNCOV_H */ |
| 14687 | LSX128, LSX128, LSX128, |
| 14688 | /* VSIGNCOV_W */ |
| 14689 | LSX128, LSX128, LSX128, |
| 14690 | /* VSLEI_B */ |
| 14691 | LSX128, LSX128, simm5, |
| 14692 | /* VSLEI_BU */ |
| 14693 | LSX128, LSX128, uimm5, |
| 14694 | /* VSLEI_D */ |
| 14695 | LSX128, LSX128, simm5, |
| 14696 | /* VSLEI_DU */ |
| 14697 | LSX128, LSX128, uimm5, |
| 14698 | /* VSLEI_H */ |
| 14699 | LSX128, LSX128, simm5, |
| 14700 | /* VSLEI_HU */ |
| 14701 | LSX128, LSX128, uimm5, |
| 14702 | /* VSLEI_W */ |
| 14703 | LSX128, LSX128, simm5, |
| 14704 | /* VSLEI_WU */ |
| 14705 | LSX128, LSX128, uimm5, |
| 14706 | /* VSLE_B */ |
| 14707 | LSX128, LSX128, LSX128, |
| 14708 | /* VSLE_BU */ |
| 14709 | LSX128, LSX128, LSX128, |
| 14710 | /* VSLE_D */ |
| 14711 | LSX128, LSX128, LSX128, |
| 14712 | /* VSLE_DU */ |
| 14713 | LSX128, LSX128, LSX128, |
| 14714 | /* VSLE_H */ |
| 14715 | LSX128, LSX128, LSX128, |
| 14716 | /* VSLE_HU */ |
| 14717 | LSX128, LSX128, LSX128, |
| 14718 | /* VSLE_W */ |
| 14719 | LSX128, LSX128, LSX128, |
| 14720 | /* VSLE_WU */ |
| 14721 | LSX128, LSX128, LSX128, |
| 14722 | /* VSLLI_B */ |
| 14723 | LSX128, LSX128, uimm3, |
| 14724 | /* VSLLI_D */ |
| 14725 | LSX128, LSX128, uimm6, |
| 14726 | /* VSLLI_H */ |
| 14727 | LSX128, LSX128, uimm4, |
| 14728 | /* VSLLI_W */ |
| 14729 | LSX128, LSX128, uimm5, |
| 14730 | /* VSLLWIL_DU_WU */ |
| 14731 | LSX128, LSX128, uimm5, |
| 14732 | /* VSLLWIL_D_W */ |
| 14733 | LSX128, LSX128, uimm5, |
| 14734 | /* VSLLWIL_HU_BU */ |
| 14735 | LSX128, LSX128, uimm3, |
| 14736 | /* VSLLWIL_H_B */ |
| 14737 | LSX128, LSX128, uimm3, |
| 14738 | /* VSLLWIL_WU_HU */ |
| 14739 | LSX128, LSX128, uimm4, |
| 14740 | /* VSLLWIL_W_H */ |
| 14741 | LSX128, LSX128, uimm4, |
| 14742 | /* VSLL_B */ |
| 14743 | LSX128, LSX128, LSX128, |
| 14744 | /* VSLL_D */ |
| 14745 | LSX128, LSX128, LSX128, |
| 14746 | /* VSLL_H */ |
| 14747 | LSX128, LSX128, LSX128, |
| 14748 | /* VSLL_W */ |
| 14749 | LSX128, LSX128, LSX128, |
| 14750 | /* VSLTI_B */ |
| 14751 | LSX128, LSX128, simm5, |
| 14752 | /* VSLTI_BU */ |
| 14753 | LSX128, LSX128, uimm5, |
| 14754 | /* VSLTI_D */ |
| 14755 | LSX128, LSX128, simm5, |
| 14756 | /* VSLTI_DU */ |
| 14757 | LSX128, LSX128, uimm5, |
| 14758 | /* VSLTI_H */ |
| 14759 | LSX128, LSX128, simm5, |
| 14760 | /* VSLTI_HU */ |
| 14761 | LSX128, LSX128, uimm5, |
| 14762 | /* VSLTI_W */ |
| 14763 | LSX128, LSX128, simm5, |
| 14764 | /* VSLTI_WU */ |
| 14765 | LSX128, LSX128, uimm5, |
| 14766 | /* VSLT_B */ |
| 14767 | LSX128, LSX128, LSX128, |
| 14768 | /* VSLT_BU */ |
| 14769 | LSX128, LSX128, LSX128, |
| 14770 | /* VSLT_D */ |
| 14771 | LSX128, LSX128, LSX128, |
| 14772 | /* VSLT_DU */ |
| 14773 | LSX128, LSX128, LSX128, |
| 14774 | /* VSLT_H */ |
| 14775 | LSX128, LSX128, LSX128, |
| 14776 | /* VSLT_HU */ |
| 14777 | LSX128, LSX128, LSX128, |
| 14778 | /* VSLT_W */ |
| 14779 | LSX128, LSX128, LSX128, |
| 14780 | /* VSLT_WU */ |
| 14781 | LSX128, LSX128, LSX128, |
| 14782 | /* VSRAI_B */ |
| 14783 | LSX128, LSX128, uimm3, |
| 14784 | /* VSRAI_D */ |
| 14785 | LSX128, LSX128, uimm6, |
| 14786 | /* VSRAI_H */ |
| 14787 | LSX128, LSX128, uimm4, |
| 14788 | /* VSRAI_W */ |
| 14789 | LSX128, LSX128, uimm5, |
| 14790 | /* VSRANI_B_H */ |
| 14791 | LSX128, LSX128, LSX128, uimm4, |
| 14792 | /* VSRANI_D_Q */ |
| 14793 | LSX128, LSX128, LSX128, uimm7, |
| 14794 | /* VSRANI_H_W */ |
| 14795 | LSX128, LSX128, LSX128, uimm5, |
| 14796 | /* VSRANI_W_D */ |
| 14797 | LSX128, LSX128, LSX128, uimm6, |
| 14798 | /* VSRAN_B_H */ |
| 14799 | LSX128, LSX128, LSX128, |
| 14800 | /* VSRAN_H_W */ |
| 14801 | LSX128, LSX128, LSX128, |
| 14802 | /* VSRAN_W_D */ |
| 14803 | LSX128, LSX128, LSX128, |
| 14804 | /* VSRARI_B */ |
| 14805 | LSX128, LSX128, uimm3, |
| 14806 | /* VSRARI_D */ |
| 14807 | LSX128, LSX128, uimm6, |
| 14808 | /* VSRARI_H */ |
| 14809 | LSX128, LSX128, uimm4, |
| 14810 | /* VSRARI_W */ |
| 14811 | LSX128, LSX128, uimm5, |
| 14812 | /* VSRARNI_B_H */ |
| 14813 | LSX128, LSX128, LSX128, uimm4, |
| 14814 | /* VSRARNI_D_Q */ |
| 14815 | LSX128, LSX128, LSX128, uimm7, |
| 14816 | /* VSRARNI_H_W */ |
| 14817 | LSX128, LSX128, LSX128, uimm5, |
| 14818 | /* VSRARNI_W_D */ |
| 14819 | LSX128, LSX128, LSX128, uimm6, |
| 14820 | /* VSRARN_B_H */ |
| 14821 | LSX128, LSX128, LSX128, |
| 14822 | /* VSRARN_H_W */ |
| 14823 | LSX128, LSX128, LSX128, |
| 14824 | /* VSRARN_W_D */ |
| 14825 | LSX128, LSX128, LSX128, |
| 14826 | /* VSRAR_B */ |
| 14827 | LSX128, LSX128, LSX128, |
| 14828 | /* VSRAR_D */ |
| 14829 | LSX128, LSX128, LSX128, |
| 14830 | /* VSRAR_H */ |
| 14831 | LSX128, LSX128, LSX128, |
| 14832 | /* VSRAR_W */ |
| 14833 | LSX128, LSX128, LSX128, |
| 14834 | /* VSRA_B */ |
| 14835 | LSX128, LSX128, LSX128, |
| 14836 | /* VSRA_D */ |
| 14837 | LSX128, LSX128, LSX128, |
| 14838 | /* VSRA_H */ |
| 14839 | LSX128, LSX128, LSX128, |
| 14840 | /* VSRA_W */ |
| 14841 | LSX128, LSX128, LSX128, |
| 14842 | /* VSRLI_B */ |
| 14843 | LSX128, LSX128, uimm3, |
| 14844 | /* VSRLI_D */ |
| 14845 | LSX128, LSX128, uimm6, |
| 14846 | /* VSRLI_H */ |
| 14847 | LSX128, LSX128, uimm4, |
| 14848 | /* VSRLI_W */ |
| 14849 | LSX128, LSX128, uimm5, |
| 14850 | /* VSRLNI_B_H */ |
| 14851 | LSX128, LSX128, LSX128, uimm4, |
| 14852 | /* VSRLNI_D_Q */ |
| 14853 | LSX128, LSX128, LSX128, uimm7, |
| 14854 | /* VSRLNI_H_W */ |
| 14855 | LSX128, LSX128, LSX128, uimm5, |
| 14856 | /* VSRLNI_W_D */ |
| 14857 | LSX128, LSX128, LSX128, uimm6, |
| 14858 | /* VSRLN_B_H */ |
| 14859 | LSX128, LSX128, LSX128, |
| 14860 | /* VSRLN_H_W */ |
| 14861 | LSX128, LSX128, LSX128, |
| 14862 | /* VSRLN_W_D */ |
| 14863 | LSX128, LSX128, LSX128, |
| 14864 | /* VSRLRI_B */ |
| 14865 | LSX128, LSX128, uimm3, |
| 14866 | /* VSRLRI_D */ |
| 14867 | LSX128, LSX128, uimm6, |
| 14868 | /* VSRLRI_H */ |
| 14869 | LSX128, LSX128, uimm4, |
| 14870 | /* VSRLRI_W */ |
| 14871 | LSX128, LSX128, uimm5, |
| 14872 | /* VSRLRNI_B_H */ |
| 14873 | LSX128, LSX128, LSX128, uimm4, |
| 14874 | /* VSRLRNI_D_Q */ |
| 14875 | LSX128, LSX128, LSX128, uimm7, |
| 14876 | /* VSRLRNI_H_W */ |
| 14877 | LSX128, LSX128, LSX128, uimm5, |
| 14878 | /* VSRLRNI_W_D */ |
| 14879 | LSX128, LSX128, LSX128, uimm6, |
| 14880 | /* VSRLRN_B_H */ |
| 14881 | LSX128, LSX128, LSX128, |
| 14882 | /* VSRLRN_H_W */ |
| 14883 | LSX128, LSX128, LSX128, |
| 14884 | /* VSRLRN_W_D */ |
| 14885 | LSX128, LSX128, LSX128, |
| 14886 | /* VSRLR_B */ |
| 14887 | LSX128, LSX128, LSX128, |
| 14888 | /* VSRLR_D */ |
| 14889 | LSX128, LSX128, LSX128, |
| 14890 | /* VSRLR_H */ |
| 14891 | LSX128, LSX128, LSX128, |
| 14892 | /* VSRLR_W */ |
| 14893 | LSX128, LSX128, LSX128, |
| 14894 | /* VSRL_B */ |
| 14895 | LSX128, LSX128, LSX128, |
| 14896 | /* VSRL_D */ |
| 14897 | LSX128, LSX128, LSX128, |
| 14898 | /* VSRL_H */ |
| 14899 | LSX128, LSX128, LSX128, |
| 14900 | /* VSRL_W */ |
| 14901 | LSX128, LSX128, LSX128, |
| 14902 | /* VSSRANI_BU_H */ |
| 14903 | LSX128, LSX128, LSX128, uimm4, |
| 14904 | /* VSSRANI_B_H */ |
| 14905 | LSX128, LSX128, LSX128, uimm4, |
| 14906 | /* VSSRANI_DU_Q */ |
| 14907 | LSX128, LSX128, LSX128, uimm7, |
| 14908 | /* VSSRANI_D_Q */ |
| 14909 | LSX128, LSX128, LSX128, uimm7, |
| 14910 | /* VSSRANI_HU_W */ |
| 14911 | LSX128, LSX128, LSX128, uimm5, |
| 14912 | /* VSSRANI_H_W */ |
| 14913 | LSX128, LSX128, LSX128, uimm5, |
| 14914 | /* VSSRANI_WU_D */ |
| 14915 | LSX128, LSX128, LSX128, uimm6, |
| 14916 | /* VSSRANI_W_D */ |
| 14917 | LSX128, LSX128, LSX128, uimm6, |
| 14918 | /* VSSRAN_BU_H */ |
| 14919 | LSX128, LSX128, LSX128, |
| 14920 | /* VSSRAN_B_H */ |
| 14921 | LSX128, LSX128, LSX128, |
| 14922 | /* VSSRAN_HU_W */ |
| 14923 | LSX128, LSX128, LSX128, |
| 14924 | /* VSSRAN_H_W */ |
| 14925 | LSX128, LSX128, LSX128, |
| 14926 | /* VSSRAN_WU_D */ |
| 14927 | LSX128, LSX128, LSX128, |
| 14928 | /* VSSRAN_W_D */ |
| 14929 | LSX128, LSX128, LSX128, |
| 14930 | /* VSSRARNI_BU_H */ |
| 14931 | LSX128, LSX128, LSX128, uimm4, |
| 14932 | /* VSSRARNI_B_H */ |
| 14933 | LSX128, LSX128, LSX128, uimm4, |
| 14934 | /* VSSRARNI_DU_Q */ |
| 14935 | LSX128, LSX128, LSX128, uimm7, |
| 14936 | /* VSSRARNI_D_Q */ |
| 14937 | LSX128, LSX128, LSX128, uimm7, |
| 14938 | /* VSSRARNI_HU_W */ |
| 14939 | LSX128, LSX128, LSX128, uimm5, |
| 14940 | /* VSSRARNI_H_W */ |
| 14941 | LSX128, LSX128, LSX128, uimm5, |
| 14942 | /* VSSRARNI_WU_D */ |
| 14943 | LSX128, LSX128, LSX128, uimm6, |
| 14944 | /* VSSRARNI_W_D */ |
| 14945 | LSX128, LSX128, LSX128, uimm6, |
| 14946 | /* VSSRARN_BU_H */ |
| 14947 | LSX128, LSX128, LSX128, |
| 14948 | /* VSSRARN_B_H */ |
| 14949 | LSX128, LSX128, LSX128, |
| 14950 | /* VSSRARN_HU_W */ |
| 14951 | LSX128, LSX128, LSX128, |
| 14952 | /* VSSRARN_H_W */ |
| 14953 | LSX128, LSX128, LSX128, |
| 14954 | /* VSSRARN_WU_D */ |
| 14955 | LSX128, LSX128, LSX128, |
| 14956 | /* VSSRARN_W_D */ |
| 14957 | LSX128, LSX128, LSX128, |
| 14958 | /* VSSRLNI_BU_H */ |
| 14959 | LSX128, LSX128, LSX128, uimm4, |
| 14960 | /* VSSRLNI_B_H */ |
| 14961 | LSX128, LSX128, LSX128, uimm4, |
| 14962 | /* VSSRLNI_DU_Q */ |
| 14963 | LSX128, LSX128, LSX128, uimm7, |
| 14964 | /* VSSRLNI_D_Q */ |
| 14965 | LSX128, LSX128, LSX128, uimm7, |
| 14966 | /* VSSRLNI_HU_W */ |
| 14967 | LSX128, LSX128, LSX128, uimm5, |
| 14968 | /* VSSRLNI_H_W */ |
| 14969 | LSX128, LSX128, LSX128, uimm5, |
| 14970 | /* VSSRLNI_WU_D */ |
| 14971 | LSX128, LSX128, LSX128, uimm6, |
| 14972 | /* VSSRLNI_W_D */ |
| 14973 | LSX128, LSX128, LSX128, uimm6, |
| 14974 | /* VSSRLN_BU_H */ |
| 14975 | LSX128, LSX128, LSX128, |
| 14976 | /* VSSRLN_B_H */ |
| 14977 | LSX128, LSX128, LSX128, |
| 14978 | /* VSSRLN_HU_W */ |
| 14979 | LSX128, LSX128, LSX128, |
| 14980 | /* VSSRLN_H_W */ |
| 14981 | LSX128, LSX128, LSX128, |
| 14982 | /* VSSRLN_WU_D */ |
| 14983 | LSX128, LSX128, LSX128, |
| 14984 | /* VSSRLN_W_D */ |
| 14985 | LSX128, LSX128, LSX128, |
| 14986 | /* VSSRLRNI_BU_H */ |
| 14987 | LSX128, LSX128, LSX128, uimm4, |
| 14988 | /* VSSRLRNI_B_H */ |
| 14989 | LSX128, LSX128, LSX128, uimm4, |
| 14990 | /* VSSRLRNI_DU_Q */ |
| 14991 | LSX128, LSX128, LSX128, uimm7, |
| 14992 | /* VSSRLRNI_D_Q */ |
| 14993 | LSX128, LSX128, LSX128, uimm7, |
| 14994 | /* VSSRLRNI_HU_W */ |
| 14995 | LSX128, LSX128, LSX128, uimm5, |
| 14996 | /* VSSRLRNI_H_W */ |
| 14997 | LSX128, LSX128, LSX128, uimm5, |
| 14998 | /* VSSRLRNI_WU_D */ |
| 14999 | LSX128, LSX128, LSX128, uimm6, |
| 15000 | /* VSSRLRNI_W_D */ |
| 15001 | LSX128, LSX128, LSX128, uimm6, |
| 15002 | /* VSSRLRN_BU_H */ |
| 15003 | LSX128, LSX128, LSX128, |
| 15004 | /* VSSRLRN_B_H */ |
| 15005 | LSX128, LSX128, LSX128, |
| 15006 | /* VSSRLRN_HU_W */ |
| 15007 | LSX128, LSX128, LSX128, |
| 15008 | /* VSSRLRN_H_W */ |
| 15009 | LSX128, LSX128, LSX128, |
| 15010 | /* VSSRLRN_WU_D */ |
| 15011 | LSX128, LSX128, LSX128, |
| 15012 | /* VSSRLRN_W_D */ |
| 15013 | LSX128, LSX128, LSX128, |
| 15014 | /* VSSUB_B */ |
| 15015 | LSX128, LSX128, LSX128, |
| 15016 | /* VSSUB_BU */ |
| 15017 | LSX128, LSX128, LSX128, |
| 15018 | /* VSSUB_D */ |
| 15019 | LSX128, LSX128, LSX128, |
| 15020 | /* VSSUB_DU */ |
| 15021 | LSX128, LSX128, LSX128, |
| 15022 | /* VSSUB_H */ |
| 15023 | LSX128, LSX128, LSX128, |
| 15024 | /* VSSUB_HU */ |
| 15025 | LSX128, LSX128, LSX128, |
| 15026 | /* VSSUB_W */ |
| 15027 | LSX128, LSX128, LSX128, |
| 15028 | /* VSSUB_WU */ |
| 15029 | LSX128, LSX128, LSX128, |
| 15030 | /* VST */ |
| 15031 | LSX128, GPR, simm12, |
| 15032 | /* VSTELM_B */ |
| 15033 | LSX128, GPR, simm8, uimm4, |
| 15034 | /* VSTELM_D */ |
| 15035 | LSX128, GPR, simm8_lsl3, uimm1, |
| 15036 | /* VSTELM_H */ |
| 15037 | LSX128, GPR, simm8_lsl1, uimm3, |
| 15038 | /* VSTELM_W */ |
| 15039 | LSX128, GPR, simm8_lsl2, uimm2, |
| 15040 | /* VSTX */ |
| 15041 | LSX128, GPR, GPR, |
| 15042 | /* VSUBI_BU */ |
| 15043 | LSX128, LSX128, uimm5, |
| 15044 | /* VSUBI_DU */ |
| 15045 | LSX128, LSX128, uimm5, |
| 15046 | /* VSUBI_HU */ |
| 15047 | LSX128, LSX128, uimm5, |
| 15048 | /* VSUBI_WU */ |
| 15049 | LSX128, LSX128, uimm5, |
| 15050 | /* VSUBWEV_D_W */ |
| 15051 | LSX128, LSX128, LSX128, |
| 15052 | /* VSUBWEV_D_WU */ |
| 15053 | LSX128, LSX128, LSX128, |
| 15054 | /* VSUBWEV_H_B */ |
| 15055 | LSX128, LSX128, LSX128, |
| 15056 | /* VSUBWEV_H_BU */ |
| 15057 | LSX128, LSX128, LSX128, |
| 15058 | /* VSUBWEV_Q_D */ |
| 15059 | LSX128, LSX128, LSX128, |
| 15060 | /* VSUBWEV_Q_DU */ |
| 15061 | LSX128, LSX128, LSX128, |
| 15062 | /* VSUBWEV_W_H */ |
| 15063 | LSX128, LSX128, LSX128, |
| 15064 | /* VSUBWEV_W_HU */ |
| 15065 | LSX128, LSX128, LSX128, |
| 15066 | /* VSUBWOD_D_W */ |
| 15067 | LSX128, LSX128, LSX128, |
| 15068 | /* VSUBWOD_D_WU */ |
| 15069 | LSX128, LSX128, LSX128, |
| 15070 | /* VSUBWOD_H_B */ |
| 15071 | LSX128, LSX128, LSX128, |
| 15072 | /* VSUBWOD_H_BU */ |
| 15073 | LSX128, LSX128, LSX128, |
| 15074 | /* VSUBWOD_Q_D */ |
| 15075 | LSX128, LSX128, LSX128, |
| 15076 | /* VSUBWOD_Q_DU */ |
| 15077 | LSX128, LSX128, LSX128, |
| 15078 | /* VSUBWOD_W_H */ |
| 15079 | LSX128, LSX128, LSX128, |
| 15080 | /* VSUBWOD_W_HU */ |
| 15081 | LSX128, LSX128, LSX128, |
| 15082 | /* VSUB_B */ |
| 15083 | LSX128, LSX128, LSX128, |
| 15084 | /* VSUB_D */ |
| 15085 | LSX128, LSX128, LSX128, |
| 15086 | /* VSUB_H */ |
| 15087 | LSX128, LSX128, LSX128, |
| 15088 | /* VSUB_Q */ |
| 15089 | LSX128, LSX128, LSX128, |
| 15090 | /* VSUB_W */ |
| 15091 | LSX128, LSX128, LSX128, |
| 15092 | /* VXORI_B */ |
| 15093 | LSX128, LSX128, uimm8, |
| 15094 | /* VXOR_V */ |
| 15095 | LSX128, LSX128, LSX128, |
| 15096 | /* X86ADC_B */ |
| 15097 | GPR, GPR, |
| 15098 | /* X86ADC_D */ |
| 15099 | GPR, GPR, |
| 15100 | /* X86ADC_H */ |
| 15101 | GPR, GPR, |
| 15102 | /* X86ADC_W */ |
| 15103 | GPR, GPR, |
| 15104 | /* X86ADD_B */ |
| 15105 | GPR, GPR, |
| 15106 | /* X86ADD_D */ |
| 15107 | GPR, GPR, |
| 15108 | /* X86ADD_DU */ |
| 15109 | GPR, GPR, |
| 15110 | /* X86ADD_H */ |
| 15111 | GPR, GPR, |
| 15112 | /* X86ADD_W */ |
| 15113 | GPR, GPR, |
| 15114 | /* X86ADD_WU */ |
| 15115 | GPR, GPR, |
| 15116 | /* X86AND_B */ |
| 15117 | GPR, GPR, |
| 15118 | /* X86AND_D */ |
| 15119 | GPR, GPR, |
| 15120 | /* X86AND_H */ |
| 15121 | GPR, GPR, |
| 15122 | /* X86AND_W */ |
| 15123 | GPR, GPR, |
| 15124 | /* X86CLRTM */ |
| 15125 | /* X86DECTOP */ |
| 15126 | /* X86DEC_B */ |
| 15127 | GPR, |
| 15128 | /* X86DEC_D */ |
| 15129 | GPR, |
| 15130 | /* X86DEC_H */ |
| 15131 | GPR, |
| 15132 | /* X86DEC_W */ |
| 15133 | GPR, |
| 15134 | /* X86INCTOP */ |
| 15135 | /* X86INC_B */ |
| 15136 | GPR, |
| 15137 | /* X86INC_D */ |
| 15138 | GPR, |
| 15139 | /* X86INC_H */ |
| 15140 | GPR, |
| 15141 | /* X86INC_W */ |
| 15142 | GPR, |
| 15143 | /* X86MFFLAG */ |
| 15144 | GPR, uimm8, |
| 15145 | /* X86MFTOP */ |
| 15146 | GPR, |
| 15147 | /* X86MTFLAG */ |
| 15148 | GPR, uimm8, |
| 15149 | /* X86MTTOP */ |
| 15150 | uimm3, |
| 15151 | /* X86MUL_B */ |
| 15152 | GPR, GPR, |
| 15153 | /* X86MUL_BU */ |
| 15154 | GPR, GPR, |
| 15155 | /* X86MUL_D */ |
| 15156 | GPR, GPR, |
| 15157 | /* X86MUL_DU */ |
| 15158 | GPR, GPR, |
| 15159 | /* X86MUL_H */ |
| 15160 | GPR, GPR, |
| 15161 | /* X86MUL_HU */ |
| 15162 | GPR, GPR, |
| 15163 | /* X86MUL_W */ |
| 15164 | GPR, GPR, |
| 15165 | /* X86MUL_WU */ |
| 15166 | GPR, GPR, |
| 15167 | /* X86OR_B */ |
| 15168 | GPR, GPR, |
| 15169 | /* X86OR_D */ |
| 15170 | GPR, GPR, |
| 15171 | /* X86OR_H */ |
| 15172 | GPR, GPR, |
| 15173 | /* X86OR_W */ |
| 15174 | GPR, GPR, |
| 15175 | /* X86RCLI_B */ |
| 15176 | GPR, uimm3, |
| 15177 | /* X86RCLI_D */ |
| 15178 | GPR, uimm6, |
| 15179 | /* X86RCLI_H */ |
| 15180 | GPR, uimm4, |
| 15181 | /* X86RCLI_W */ |
| 15182 | GPR, uimm5, |
| 15183 | /* X86RCL_B */ |
| 15184 | GPR, GPR, |
| 15185 | /* X86RCL_D */ |
| 15186 | GPR, GPR, |
| 15187 | /* X86RCL_H */ |
| 15188 | GPR, GPR, |
| 15189 | /* X86RCL_W */ |
| 15190 | GPR, GPR, |
| 15191 | /* X86RCRI_B */ |
| 15192 | GPR, uimm3, |
| 15193 | /* X86RCRI_D */ |
| 15194 | GPR, uimm6, |
| 15195 | /* X86RCRI_H */ |
| 15196 | GPR, uimm4, |
| 15197 | /* X86RCRI_W */ |
| 15198 | GPR, uimm5, |
| 15199 | /* X86RCR_B */ |
| 15200 | GPR, GPR, |
| 15201 | /* X86RCR_D */ |
| 15202 | GPR, GPR, |
| 15203 | /* X86RCR_H */ |
| 15204 | GPR, GPR, |
| 15205 | /* X86RCR_W */ |
| 15206 | GPR, GPR, |
| 15207 | /* X86ROTLI_B */ |
| 15208 | GPR, uimm3, |
| 15209 | /* X86ROTLI_D */ |
| 15210 | GPR, uimm6, |
| 15211 | /* X86ROTLI_H */ |
| 15212 | GPR, uimm4, |
| 15213 | /* X86ROTLI_W */ |
| 15214 | GPR, uimm5, |
| 15215 | /* X86ROTL_B */ |
| 15216 | GPR, GPR, |
| 15217 | /* X86ROTL_D */ |
| 15218 | GPR, GPR, |
| 15219 | /* X86ROTL_H */ |
| 15220 | GPR, GPR, |
| 15221 | /* X86ROTL_W */ |
| 15222 | GPR, GPR, |
| 15223 | /* X86ROTRI_B */ |
| 15224 | GPR, uimm3, |
| 15225 | /* X86ROTRI_D */ |
| 15226 | GPR, uimm6, |
| 15227 | /* X86ROTRI_H */ |
| 15228 | GPR, uimm4, |
| 15229 | /* X86ROTRI_W */ |
| 15230 | GPR, uimm5, |
| 15231 | /* X86ROTR_B */ |
| 15232 | GPR, GPR, |
| 15233 | /* X86ROTR_D */ |
| 15234 | GPR, GPR, |
| 15235 | /* X86ROTR_H */ |
| 15236 | GPR, GPR, |
| 15237 | /* X86ROTR_W */ |
| 15238 | GPR, GPR, |
| 15239 | /* X86SBC_B */ |
| 15240 | GPR, GPR, |
| 15241 | /* X86SBC_D */ |
| 15242 | GPR, GPR, |
| 15243 | /* X86SBC_H */ |
| 15244 | GPR, GPR, |
| 15245 | /* X86SBC_W */ |
| 15246 | GPR, GPR, |
| 15247 | /* X86SETTAG */ |
| 15248 | GPR, uimm5, uimm8, |
| 15249 | /* X86SETTM */ |
| 15250 | /* X86SLLI_B */ |
| 15251 | GPR, uimm3, |
| 15252 | /* X86SLLI_D */ |
| 15253 | GPR, uimm6, |
| 15254 | /* X86SLLI_H */ |
| 15255 | GPR, uimm4, |
| 15256 | /* X86SLLI_W */ |
| 15257 | GPR, uimm5, |
| 15258 | /* X86SLL_B */ |
| 15259 | GPR, GPR, |
| 15260 | /* X86SLL_D */ |
| 15261 | GPR, GPR, |
| 15262 | /* X86SLL_H */ |
| 15263 | GPR, GPR, |
| 15264 | /* X86SLL_W */ |
| 15265 | GPR, GPR, |
| 15266 | /* X86SRAI_B */ |
| 15267 | GPR, uimm3, |
| 15268 | /* X86SRAI_D */ |
| 15269 | GPR, uimm6, |
| 15270 | /* X86SRAI_H */ |
| 15271 | GPR, uimm4, |
| 15272 | /* X86SRAI_W */ |
| 15273 | GPR, uimm5, |
| 15274 | /* X86SRA_B */ |
| 15275 | GPR, GPR, |
| 15276 | /* X86SRA_D */ |
| 15277 | GPR, GPR, |
| 15278 | /* X86SRA_H */ |
| 15279 | GPR, GPR, |
| 15280 | /* X86SRA_W */ |
| 15281 | GPR, GPR, |
| 15282 | /* X86SRLI_B */ |
| 15283 | GPR, uimm3, |
| 15284 | /* X86SRLI_D */ |
| 15285 | GPR, uimm6, |
| 15286 | /* X86SRLI_H */ |
| 15287 | GPR, uimm4, |
| 15288 | /* X86SRLI_W */ |
| 15289 | GPR, uimm5, |
| 15290 | /* X86SRL_B */ |
| 15291 | GPR, GPR, |
| 15292 | /* X86SRL_D */ |
| 15293 | GPR, GPR, |
| 15294 | /* X86SRL_H */ |
| 15295 | GPR, GPR, |
| 15296 | /* X86SRL_W */ |
| 15297 | GPR, GPR, |
| 15298 | /* X86SUB_B */ |
| 15299 | GPR, GPR, |
| 15300 | /* X86SUB_D */ |
| 15301 | GPR, GPR, |
| 15302 | /* X86SUB_DU */ |
| 15303 | GPR, GPR, |
| 15304 | /* X86SUB_H */ |
| 15305 | GPR, GPR, |
| 15306 | /* X86SUB_W */ |
| 15307 | GPR, GPR, |
| 15308 | /* X86SUB_WU */ |
| 15309 | GPR, GPR, |
| 15310 | /* X86XOR_B */ |
| 15311 | GPR, GPR, |
| 15312 | /* X86XOR_D */ |
| 15313 | GPR, GPR, |
| 15314 | /* X86XOR_H */ |
| 15315 | GPR, GPR, |
| 15316 | /* X86XOR_W */ |
| 15317 | GPR, GPR, |
| 15318 | /* XOR */ |
| 15319 | GPR, GPR, GPR, |
| 15320 | /* XORI */ |
| 15321 | GPR, GPR, uimm12, |
| 15322 | /* XVABSD_B */ |
| 15323 | LASX256, LASX256, LASX256, |
| 15324 | /* XVABSD_BU */ |
| 15325 | LASX256, LASX256, LASX256, |
| 15326 | /* XVABSD_D */ |
| 15327 | LASX256, LASX256, LASX256, |
| 15328 | /* XVABSD_DU */ |
| 15329 | LASX256, LASX256, LASX256, |
| 15330 | /* XVABSD_H */ |
| 15331 | LASX256, LASX256, LASX256, |
| 15332 | /* XVABSD_HU */ |
| 15333 | LASX256, LASX256, LASX256, |
| 15334 | /* XVABSD_W */ |
| 15335 | LASX256, LASX256, LASX256, |
| 15336 | /* XVABSD_WU */ |
| 15337 | LASX256, LASX256, LASX256, |
| 15338 | /* XVADDA_B */ |
| 15339 | LASX256, LASX256, LASX256, |
| 15340 | /* XVADDA_D */ |
| 15341 | LASX256, LASX256, LASX256, |
| 15342 | /* XVADDA_H */ |
| 15343 | LASX256, LASX256, LASX256, |
| 15344 | /* XVADDA_W */ |
| 15345 | LASX256, LASX256, LASX256, |
| 15346 | /* XVADDI_BU */ |
| 15347 | LASX256, LASX256, uimm5, |
| 15348 | /* XVADDI_DU */ |
| 15349 | LASX256, LASX256, uimm5, |
| 15350 | /* XVADDI_HU */ |
| 15351 | LASX256, LASX256, uimm5, |
| 15352 | /* XVADDI_WU */ |
| 15353 | LASX256, LASX256, uimm5, |
| 15354 | /* XVADDWEV_D_W */ |
| 15355 | LASX256, LASX256, LASX256, |
| 15356 | /* XVADDWEV_D_WU */ |
| 15357 | LASX256, LASX256, LASX256, |
| 15358 | /* XVADDWEV_D_WU_W */ |
| 15359 | LASX256, LASX256, LASX256, |
| 15360 | /* XVADDWEV_H_B */ |
| 15361 | LASX256, LASX256, LASX256, |
| 15362 | /* XVADDWEV_H_BU */ |
| 15363 | LASX256, LASX256, LASX256, |
| 15364 | /* XVADDWEV_H_BU_B */ |
| 15365 | LASX256, LASX256, LASX256, |
| 15366 | /* XVADDWEV_Q_D */ |
| 15367 | LASX256, LASX256, LASX256, |
| 15368 | /* XVADDWEV_Q_DU */ |
| 15369 | LASX256, LASX256, LASX256, |
| 15370 | /* XVADDWEV_Q_DU_D */ |
| 15371 | LASX256, LASX256, LASX256, |
| 15372 | /* XVADDWEV_W_H */ |
| 15373 | LASX256, LASX256, LASX256, |
| 15374 | /* XVADDWEV_W_HU */ |
| 15375 | LASX256, LASX256, LASX256, |
| 15376 | /* XVADDWEV_W_HU_H */ |
| 15377 | LASX256, LASX256, LASX256, |
| 15378 | /* XVADDWOD_D_W */ |
| 15379 | LASX256, LASX256, LASX256, |
| 15380 | /* XVADDWOD_D_WU */ |
| 15381 | LASX256, LASX256, LASX256, |
| 15382 | /* XVADDWOD_D_WU_W */ |
| 15383 | LASX256, LASX256, LASX256, |
| 15384 | /* XVADDWOD_H_B */ |
| 15385 | LASX256, LASX256, LASX256, |
| 15386 | /* XVADDWOD_H_BU */ |
| 15387 | LASX256, LASX256, LASX256, |
| 15388 | /* XVADDWOD_H_BU_B */ |
| 15389 | LASX256, LASX256, LASX256, |
| 15390 | /* XVADDWOD_Q_D */ |
| 15391 | LASX256, LASX256, LASX256, |
| 15392 | /* XVADDWOD_Q_DU */ |
| 15393 | LASX256, LASX256, LASX256, |
| 15394 | /* XVADDWOD_Q_DU_D */ |
| 15395 | LASX256, LASX256, LASX256, |
| 15396 | /* XVADDWOD_W_H */ |
| 15397 | LASX256, LASX256, LASX256, |
| 15398 | /* XVADDWOD_W_HU */ |
| 15399 | LASX256, LASX256, LASX256, |
| 15400 | /* XVADDWOD_W_HU_H */ |
| 15401 | LASX256, LASX256, LASX256, |
| 15402 | /* XVADD_B */ |
| 15403 | LASX256, LASX256, LASX256, |
| 15404 | /* XVADD_D */ |
| 15405 | LASX256, LASX256, LASX256, |
| 15406 | /* XVADD_H */ |
| 15407 | LASX256, LASX256, LASX256, |
| 15408 | /* XVADD_Q */ |
| 15409 | LASX256, LASX256, LASX256, |
| 15410 | /* XVADD_W */ |
| 15411 | LASX256, LASX256, LASX256, |
| 15412 | /* XVANDI_B */ |
| 15413 | LASX256, LASX256, uimm8, |
| 15414 | /* XVANDN_V */ |
| 15415 | LASX256, LASX256, LASX256, |
| 15416 | /* XVAND_V */ |
| 15417 | LASX256, LASX256, LASX256, |
| 15418 | /* XVAVGR_B */ |
| 15419 | LASX256, LASX256, LASX256, |
| 15420 | /* XVAVGR_BU */ |
| 15421 | LASX256, LASX256, LASX256, |
| 15422 | /* XVAVGR_D */ |
| 15423 | LASX256, LASX256, LASX256, |
| 15424 | /* XVAVGR_DU */ |
| 15425 | LASX256, LASX256, LASX256, |
| 15426 | /* XVAVGR_H */ |
| 15427 | LASX256, LASX256, LASX256, |
| 15428 | /* XVAVGR_HU */ |
| 15429 | LASX256, LASX256, LASX256, |
| 15430 | /* XVAVGR_W */ |
| 15431 | LASX256, LASX256, LASX256, |
| 15432 | /* XVAVGR_WU */ |
| 15433 | LASX256, LASX256, LASX256, |
| 15434 | /* XVAVG_B */ |
| 15435 | LASX256, LASX256, LASX256, |
| 15436 | /* XVAVG_BU */ |
| 15437 | LASX256, LASX256, LASX256, |
| 15438 | /* XVAVG_D */ |
| 15439 | LASX256, LASX256, LASX256, |
| 15440 | /* XVAVG_DU */ |
| 15441 | LASX256, LASX256, LASX256, |
| 15442 | /* XVAVG_H */ |
| 15443 | LASX256, LASX256, LASX256, |
| 15444 | /* XVAVG_HU */ |
| 15445 | LASX256, LASX256, LASX256, |
| 15446 | /* XVAVG_W */ |
| 15447 | LASX256, LASX256, LASX256, |
| 15448 | /* XVAVG_WU */ |
| 15449 | LASX256, LASX256, LASX256, |
| 15450 | /* XVBITCLRI_B */ |
| 15451 | LASX256, LASX256, uimm3, |
| 15452 | /* XVBITCLRI_D */ |
| 15453 | LASX256, LASX256, uimm6, |
| 15454 | /* XVBITCLRI_H */ |
| 15455 | LASX256, LASX256, uimm4, |
| 15456 | /* XVBITCLRI_W */ |
| 15457 | LASX256, LASX256, uimm5, |
| 15458 | /* XVBITCLR_B */ |
| 15459 | LASX256, LASX256, LASX256, |
| 15460 | /* XVBITCLR_D */ |
| 15461 | LASX256, LASX256, LASX256, |
| 15462 | /* XVBITCLR_H */ |
| 15463 | LASX256, LASX256, LASX256, |
| 15464 | /* XVBITCLR_W */ |
| 15465 | LASX256, LASX256, LASX256, |
| 15466 | /* XVBITREVI_B */ |
| 15467 | LASX256, LASX256, uimm3, |
| 15468 | /* XVBITREVI_D */ |
| 15469 | LASX256, LASX256, uimm6, |
| 15470 | /* XVBITREVI_H */ |
| 15471 | LASX256, LASX256, uimm4, |
| 15472 | /* XVBITREVI_W */ |
| 15473 | LASX256, LASX256, uimm5, |
| 15474 | /* XVBITREV_B */ |
| 15475 | LASX256, LASX256, LASX256, |
| 15476 | /* XVBITREV_D */ |
| 15477 | LASX256, LASX256, LASX256, |
| 15478 | /* XVBITREV_H */ |
| 15479 | LASX256, LASX256, LASX256, |
| 15480 | /* XVBITREV_W */ |
| 15481 | LASX256, LASX256, LASX256, |
| 15482 | /* XVBITSELI_B */ |
| 15483 | LASX256, LASX256, LASX256, uimm8, |
| 15484 | /* XVBITSEL_V */ |
| 15485 | LASX256, LASX256, LASX256, LASX256, |
| 15486 | /* XVBITSETI_B */ |
| 15487 | LASX256, LASX256, uimm3, |
| 15488 | /* XVBITSETI_D */ |
| 15489 | LASX256, LASX256, uimm6, |
| 15490 | /* XVBITSETI_H */ |
| 15491 | LASX256, LASX256, uimm4, |
| 15492 | /* XVBITSETI_W */ |
| 15493 | LASX256, LASX256, uimm5, |
| 15494 | /* XVBITSET_B */ |
| 15495 | LASX256, LASX256, LASX256, |
| 15496 | /* XVBITSET_D */ |
| 15497 | LASX256, LASX256, LASX256, |
| 15498 | /* XVBITSET_H */ |
| 15499 | LASX256, LASX256, LASX256, |
| 15500 | /* XVBITSET_W */ |
| 15501 | LASX256, LASX256, LASX256, |
| 15502 | /* XVBSLL_V */ |
| 15503 | LASX256, LASX256, uimm5, |
| 15504 | /* XVBSRL_V */ |
| 15505 | LASX256, LASX256, uimm5, |
| 15506 | /* XVCLO_B */ |
| 15507 | LASX256, LASX256, |
| 15508 | /* XVCLO_D */ |
| 15509 | LASX256, LASX256, |
| 15510 | /* XVCLO_H */ |
| 15511 | LASX256, LASX256, |
| 15512 | /* XVCLO_W */ |
| 15513 | LASX256, LASX256, |
| 15514 | /* XVCLZ_B */ |
| 15515 | LASX256, LASX256, |
| 15516 | /* XVCLZ_D */ |
| 15517 | LASX256, LASX256, |
| 15518 | /* XVCLZ_H */ |
| 15519 | LASX256, LASX256, |
| 15520 | /* XVCLZ_W */ |
| 15521 | LASX256, LASX256, |
| 15522 | /* XVDIV_B */ |
| 15523 | LASX256, LASX256, LASX256, |
| 15524 | /* XVDIV_BU */ |
| 15525 | LASX256, LASX256, LASX256, |
| 15526 | /* XVDIV_D */ |
| 15527 | LASX256, LASX256, LASX256, |
| 15528 | /* XVDIV_DU */ |
| 15529 | LASX256, LASX256, LASX256, |
| 15530 | /* XVDIV_H */ |
| 15531 | LASX256, LASX256, LASX256, |
| 15532 | /* XVDIV_HU */ |
| 15533 | LASX256, LASX256, LASX256, |
| 15534 | /* XVDIV_W */ |
| 15535 | LASX256, LASX256, LASX256, |
| 15536 | /* XVDIV_WU */ |
| 15537 | LASX256, LASX256, LASX256, |
| 15538 | /* XVEXTH_DU_WU */ |
| 15539 | LASX256, LASX256, |
| 15540 | /* XVEXTH_D_W */ |
| 15541 | LASX256, LASX256, |
| 15542 | /* XVEXTH_HU_BU */ |
| 15543 | LASX256, LASX256, |
| 15544 | /* XVEXTH_H_B */ |
| 15545 | LASX256, LASX256, |
| 15546 | /* XVEXTH_QU_DU */ |
| 15547 | LASX256, LASX256, |
| 15548 | /* XVEXTH_Q_D */ |
| 15549 | LASX256, LASX256, |
| 15550 | /* XVEXTH_WU_HU */ |
| 15551 | LASX256, LASX256, |
| 15552 | /* XVEXTH_W_H */ |
| 15553 | LASX256, LASX256, |
| 15554 | /* XVEXTL_QU_DU */ |
| 15555 | LASX256, LASX256, |
| 15556 | /* XVEXTL_Q_D */ |
| 15557 | LASX256, LASX256, |
| 15558 | /* XVEXTRINS_B */ |
| 15559 | LASX256, LASX256, LASX256, uimm8, |
| 15560 | /* XVEXTRINS_D */ |
| 15561 | LASX256, LASX256, LASX256, uimm8, |
| 15562 | /* XVEXTRINS_H */ |
| 15563 | LASX256, LASX256, LASX256, uimm8, |
| 15564 | /* XVEXTRINS_W */ |
| 15565 | LASX256, LASX256, LASX256, uimm8, |
| 15566 | /* XVFADD_D */ |
| 15567 | LASX256, LASX256, LASX256, |
| 15568 | /* XVFADD_S */ |
| 15569 | LASX256, LASX256, LASX256, |
| 15570 | /* XVFCLASS_D */ |
| 15571 | LASX256, LASX256, |
| 15572 | /* XVFCLASS_S */ |
| 15573 | LASX256, LASX256, |
| 15574 | /* XVFCMP_CAF_D */ |
| 15575 | LASX256, LASX256, LASX256, |
| 15576 | /* XVFCMP_CAF_S */ |
| 15577 | LASX256, LASX256, LASX256, |
| 15578 | /* XVFCMP_CEQ_D */ |
| 15579 | LASX256, LASX256, LASX256, |
| 15580 | /* XVFCMP_CEQ_S */ |
| 15581 | LASX256, LASX256, LASX256, |
| 15582 | /* XVFCMP_CLE_D */ |
| 15583 | LASX256, LASX256, LASX256, |
| 15584 | /* XVFCMP_CLE_S */ |
| 15585 | LASX256, LASX256, LASX256, |
| 15586 | /* XVFCMP_CLT_D */ |
| 15587 | LASX256, LASX256, LASX256, |
| 15588 | /* XVFCMP_CLT_S */ |
| 15589 | LASX256, LASX256, LASX256, |
| 15590 | /* XVFCMP_CNE_D */ |
| 15591 | LASX256, LASX256, LASX256, |
| 15592 | /* XVFCMP_CNE_S */ |
| 15593 | LASX256, LASX256, LASX256, |
| 15594 | /* XVFCMP_COR_D */ |
| 15595 | LASX256, LASX256, LASX256, |
| 15596 | /* XVFCMP_COR_S */ |
| 15597 | LASX256, LASX256, LASX256, |
| 15598 | /* XVFCMP_CUEQ_D */ |
| 15599 | LASX256, LASX256, LASX256, |
| 15600 | /* XVFCMP_CUEQ_S */ |
| 15601 | LASX256, LASX256, LASX256, |
| 15602 | /* XVFCMP_CULE_D */ |
| 15603 | LASX256, LASX256, LASX256, |
| 15604 | /* XVFCMP_CULE_S */ |
| 15605 | LASX256, LASX256, LASX256, |
| 15606 | /* XVFCMP_CULT_D */ |
| 15607 | LASX256, LASX256, LASX256, |
| 15608 | /* XVFCMP_CULT_S */ |
| 15609 | LASX256, LASX256, LASX256, |
| 15610 | /* XVFCMP_CUNE_D */ |
| 15611 | LASX256, LASX256, LASX256, |
| 15612 | /* XVFCMP_CUNE_S */ |
| 15613 | LASX256, LASX256, LASX256, |
| 15614 | /* XVFCMP_CUN_D */ |
| 15615 | LASX256, LASX256, LASX256, |
| 15616 | /* XVFCMP_CUN_S */ |
| 15617 | LASX256, LASX256, LASX256, |
| 15618 | /* XVFCMP_SAF_D */ |
| 15619 | LASX256, LASX256, LASX256, |
| 15620 | /* XVFCMP_SAF_S */ |
| 15621 | LASX256, LASX256, LASX256, |
| 15622 | /* XVFCMP_SEQ_D */ |
| 15623 | LASX256, LASX256, LASX256, |
| 15624 | /* XVFCMP_SEQ_S */ |
| 15625 | LASX256, LASX256, LASX256, |
| 15626 | /* XVFCMP_SLE_D */ |
| 15627 | LASX256, LASX256, LASX256, |
| 15628 | /* XVFCMP_SLE_S */ |
| 15629 | LASX256, LASX256, LASX256, |
| 15630 | /* XVFCMP_SLT_D */ |
| 15631 | LASX256, LASX256, LASX256, |
| 15632 | /* XVFCMP_SLT_S */ |
| 15633 | LASX256, LASX256, LASX256, |
| 15634 | /* XVFCMP_SNE_D */ |
| 15635 | LASX256, LASX256, LASX256, |
| 15636 | /* XVFCMP_SNE_S */ |
| 15637 | LASX256, LASX256, LASX256, |
| 15638 | /* XVFCMP_SOR_D */ |
| 15639 | LASX256, LASX256, LASX256, |
| 15640 | /* XVFCMP_SOR_S */ |
| 15641 | LASX256, LASX256, LASX256, |
| 15642 | /* XVFCMP_SUEQ_D */ |
| 15643 | LASX256, LASX256, LASX256, |
| 15644 | /* XVFCMP_SUEQ_S */ |
| 15645 | LASX256, LASX256, LASX256, |
| 15646 | /* XVFCMP_SULE_D */ |
| 15647 | LASX256, LASX256, LASX256, |
| 15648 | /* XVFCMP_SULE_S */ |
| 15649 | LASX256, LASX256, LASX256, |
| 15650 | /* XVFCMP_SULT_D */ |
| 15651 | LASX256, LASX256, LASX256, |
| 15652 | /* XVFCMP_SULT_S */ |
| 15653 | LASX256, LASX256, LASX256, |
| 15654 | /* XVFCMP_SUNE_D */ |
| 15655 | LASX256, LASX256, LASX256, |
| 15656 | /* XVFCMP_SUNE_S */ |
| 15657 | LASX256, LASX256, LASX256, |
| 15658 | /* XVFCMP_SUN_D */ |
| 15659 | LASX256, LASX256, LASX256, |
| 15660 | /* XVFCMP_SUN_S */ |
| 15661 | LASX256, LASX256, LASX256, |
| 15662 | /* XVFCVTH_D_S */ |
| 15663 | LASX256, LASX256, |
| 15664 | /* XVFCVTH_S_H */ |
| 15665 | LASX256, LASX256, |
| 15666 | /* XVFCVTL_D_S */ |
| 15667 | LASX256, LASX256, |
| 15668 | /* XVFCVTL_S_H */ |
| 15669 | LASX256, LASX256, |
| 15670 | /* XVFCVT_H_S */ |
| 15671 | LASX256, LASX256, LASX256, |
| 15672 | /* XVFCVT_S_D */ |
| 15673 | LASX256, LASX256, LASX256, |
| 15674 | /* XVFDIV_D */ |
| 15675 | LASX256, LASX256, LASX256, |
| 15676 | /* XVFDIV_S */ |
| 15677 | LASX256, LASX256, LASX256, |
| 15678 | /* XVFFINTH_D_W */ |
| 15679 | LASX256, LASX256, |
| 15680 | /* XVFFINTL_D_W */ |
| 15681 | LASX256, LASX256, |
| 15682 | /* XVFFINT_D_L */ |
| 15683 | LASX256, LASX256, |
| 15684 | /* XVFFINT_D_LU */ |
| 15685 | LASX256, LASX256, |
| 15686 | /* XVFFINT_S_L */ |
| 15687 | LASX256, LASX256, LASX256, |
| 15688 | /* XVFFINT_S_W */ |
| 15689 | LASX256, LASX256, |
| 15690 | /* XVFFINT_S_WU */ |
| 15691 | LASX256, LASX256, |
| 15692 | /* XVFLOGB_D */ |
| 15693 | LASX256, LASX256, |
| 15694 | /* XVFLOGB_S */ |
| 15695 | LASX256, LASX256, |
| 15696 | /* XVFMADD_D */ |
| 15697 | LASX256, LASX256, LASX256, LASX256, |
| 15698 | /* XVFMADD_S */ |
| 15699 | LASX256, LASX256, LASX256, LASX256, |
| 15700 | /* XVFMAXA_D */ |
| 15701 | LASX256, LASX256, LASX256, |
| 15702 | /* XVFMAXA_S */ |
| 15703 | LASX256, LASX256, LASX256, |
| 15704 | /* XVFMAX_D */ |
| 15705 | LASX256, LASX256, LASX256, |
| 15706 | /* XVFMAX_S */ |
| 15707 | LASX256, LASX256, LASX256, |
| 15708 | /* XVFMINA_D */ |
| 15709 | LASX256, LASX256, LASX256, |
| 15710 | /* XVFMINA_S */ |
| 15711 | LASX256, LASX256, LASX256, |
| 15712 | /* XVFMIN_D */ |
| 15713 | LASX256, LASX256, LASX256, |
| 15714 | /* XVFMIN_S */ |
| 15715 | LASX256, LASX256, LASX256, |
| 15716 | /* XVFMSUB_D */ |
| 15717 | LASX256, LASX256, LASX256, LASX256, |
| 15718 | /* XVFMSUB_S */ |
| 15719 | LASX256, LASX256, LASX256, LASX256, |
| 15720 | /* XVFMUL_D */ |
| 15721 | LASX256, LASX256, LASX256, |
| 15722 | /* XVFMUL_S */ |
| 15723 | LASX256, LASX256, LASX256, |
| 15724 | /* XVFNMADD_D */ |
| 15725 | LASX256, LASX256, LASX256, LASX256, |
| 15726 | /* XVFNMADD_S */ |
| 15727 | LASX256, LASX256, LASX256, LASX256, |
| 15728 | /* XVFNMSUB_D */ |
| 15729 | LASX256, LASX256, LASX256, LASX256, |
| 15730 | /* XVFNMSUB_S */ |
| 15731 | LASX256, LASX256, LASX256, LASX256, |
| 15732 | /* XVFRECIPE_D */ |
| 15733 | LASX256, LASX256, |
| 15734 | /* XVFRECIPE_S */ |
| 15735 | LASX256, LASX256, |
| 15736 | /* XVFRECIP_D */ |
| 15737 | LASX256, LASX256, |
| 15738 | /* XVFRECIP_S */ |
| 15739 | LASX256, LASX256, |
| 15740 | /* XVFRINTRM_D */ |
| 15741 | LASX256, LASX256, |
| 15742 | /* XVFRINTRM_S */ |
| 15743 | LASX256, LASX256, |
| 15744 | /* XVFRINTRNE_D */ |
| 15745 | LASX256, LASX256, |
| 15746 | /* XVFRINTRNE_S */ |
| 15747 | LASX256, LASX256, |
| 15748 | /* XVFRINTRP_D */ |
| 15749 | LASX256, LASX256, |
| 15750 | /* XVFRINTRP_S */ |
| 15751 | LASX256, LASX256, |
| 15752 | /* XVFRINTRZ_D */ |
| 15753 | LASX256, LASX256, |
| 15754 | /* XVFRINTRZ_S */ |
| 15755 | LASX256, LASX256, |
| 15756 | /* XVFRINT_D */ |
| 15757 | LASX256, LASX256, |
| 15758 | /* XVFRINT_S */ |
| 15759 | LASX256, LASX256, |
| 15760 | /* XVFRSQRTE_D */ |
| 15761 | LASX256, LASX256, |
| 15762 | /* XVFRSQRTE_S */ |
| 15763 | LASX256, LASX256, |
| 15764 | /* XVFRSQRT_D */ |
| 15765 | LASX256, LASX256, |
| 15766 | /* XVFRSQRT_S */ |
| 15767 | LASX256, LASX256, |
| 15768 | /* XVFRSTPI_B */ |
| 15769 | LASX256, LASX256, LASX256, uimm5, |
| 15770 | /* XVFRSTPI_H */ |
| 15771 | LASX256, LASX256, LASX256, uimm5, |
| 15772 | /* XVFRSTP_B */ |
| 15773 | LASX256, LASX256, LASX256, LASX256, |
| 15774 | /* XVFRSTP_H */ |
| 15775 | LASX256, LASX256, LASX256, LASX256, |
| 15776 | /* XVFSQRT_D */ |
| 15777 | LASX256, LASX256, |
| 15778 | /* XVFSQRT_S */ |
| 15779 | LASX256, LASX256, |
| 15780 | /* XVFSUB_D */ |
| 15781 | LASX256, LASX256, LASX256, |
| 15782 | /* XVFSUB_S */ |
| 15783 | LASX256, LASX256, LASX256, |
| 15784 | /* XVFTINTH_L_S */ |
| 15785 | LASX256, LASX256, |
| 15786 | /* XVFTINTL_L_S */ |
| 15787 | LASX256, LASX256, |
| 15788 | /* XVFTINTRMH_L_S */ |
| 15789 | LASX256, LASX256, |
| 15790 | /* XVFTINTRML_L_S */ |
| 15791 | LASX256, LASX256, |
| 15792 | /* XVFTINTRM_L_D */ |
| 15793 | LASX256, LASX256, |
| 15794 | /* XVFTINTRM_W_D */ |
| 15795 | LASX256, LASX256, LASX256, |
| 15796 | /* XVFTINTRM_W_S */ |
| 15797 | LASX256, LASX256, |
| 15798 | /* XVFTINTRNEH_L_S */ |
| 15799 | LASX256, LASX256, |
| 15800 | /* XVFTINTRNEL_L_S */ |
| 15801 | LASX256, LASX256, |
| 15802 | /* XVFTINTRNE_L_D */ |
| 15803 | LASX256, LASX256, |
| 15804 | /* XVFTINTRNE_W_D */ |
| 15805 | LASX256, LASX256, LASX256, |
| 15806 | /* XVFTINTRNE_W_S */ |
| 15807 | LASX256, LASX256, |
| 15808 | /* XVFTINTRPH_L_S */ |
| 15809 | LASX256, LASX256, |
| 15810 | /* XVFTINTRPL_L_S */ |
| 15811 | LASX256, LASX256, |
| 15812 | /* XVFTINTRP_L_D */ |
| 15813 | LASX256, LASX256, |
| 15814 | /* XVFTINTRP_W_D */ |
| 15815 | LASX256, LASX256, LASX256, |
| 15816 | /* XVFTINTRP_W_S */ |
| 15817 | LASX256, LASX256, |
| 15818 | /* XVFTINTRZH_L_S */ |
| 15819 | LASX256, LASX256, |
| 15820 | /* XVFTINTRZL_L_S */ |
| 15821 | LASX256, LASX256, |
| 15822 | /* XVFTINTRZ_LU_D */ |
| 15823 | LASX256, LASX256, |
| 15824 | /* XVFTINTRZ_L_D */ |
| 15825 | LASX256, LASX256, |
| 15826 | /* XVFTINTRZ_WU_S */ |
| 15827 | LASX256, LASX256, |
| 15828 | /* XVFTINTRZ_W_D */ |
| 15829 | LASX256, LASX256, LASX256, |
| 15830 | /* XVFTINTRZ_W_S */ |
| 15831 | LASX256, LASX256, |
| 15832 | /* XVFTINT_LU_D */ |
| 15833 | LASX256, LASX256, |
| 15834 | /* XVFTINT_L_D */ |
| 15835 | LASX256, LASX256, |
| 15836 | /* XVFTINT_WU_S */ |
| 15837 | LASX256, LASX256, |
| 15838 | /* XVFTINT_W_D */ |
| 15839 | LASX256, LASX256, LASX256, |
| 15840 | /* XVFTINT_W_S */ |
| 15841 | LASX256, LASX256, |
| 15842 | /* XVHADDW_DU_WU */ |
| 15843 | LASX256, LASX256, LASX256, |
| 15844 | /* XVHADDW_D_W */ |
| 15845 | LASX256, LASX256, LASX256, |
| 15846 | /* XVHADDW_HU_BU */ |
| 15847 | LASX256, LASX256, LASX256, |
| 15848 | /* XVHADDW_H_B */ |
| 15849 | LASX256, LASX256, LASX256, |
| 15850 | /* XVHADDW_QU_DU */ |
| 15851 | LASX256, LASX256, LASX256, |
| 15852 | /* XVHADDW_Q_D */ |
| 15853 | LASX256, LASX256, LASX256, |
| 15854 | /* XVHADDW_WU_HU */ |
| 15855 | LASX256, LASX256, LASX256, |
| 15856 | /* XVHADDW_W_H */ |
| 15857 | LASX256, LASX256, LASX256, |
| 15858 | /* XVHSELI_D */ |
| 15859 | LASX256, LASX256, uimm5, |
| 15860 | /* XVHSUBW_DU_WU */ |
| 15861 | LASX256, LASX256, LASX256, |
| 15862 | /* XVHSUBW_D_W */ |
| 15863 | LASX256, LASX256, LASX256, |
| 15864 | /* XVHSUBW_HU_BU */ |
| 15865 | LASX256, LASX256, LASX256, |
| 15866 | /* XVHSUBW_H_B */ |
| 15867 | LASX256, LASX256, LASX256, |
| 15868 | /* XVHSUBW_QU_DU */ |
| 15869 | LASX256, LASX256, LASX256, |
| 15870 | /* XVHSUBW_Q_D */ |
| 15871 | LASX256, LASX256, LASX256, |
| 15872 | /* XVHSUBW_WU_HU */ |
| 15873 | LASX256, LASX256, LASX256, |
| 15874 | /* XVHSUBW_W_H */ |
| 15875 | LASX256, LASX256, LASX256, |
| 15876 | /* XVILVH_B */ |
| 15877 | LASX256, LASX256, LASX256, |
| 15878 | /* XVILVH_D */ |
| 15879 | LASX256, LASX256, LASX256, |
| 15880 | /* XVILVH_H */ |
| 15881 | LASX256, LASX256, LASX256, |
| 15882 | /* XVILVH_W */ |
| 15883 | LASX256, LASX256, LASX256, |
| 15884 | /* XVILVL_B */ |
| 15885 | LASX256, LASX256, LASX256, |
| 15886 | /* XVILVL_D */ |
| 15887 | LASX256, LASX256, LASX256, |
| 15888 | /* XVILVL_H */ |
| 15889 | LASX256, LASX256, LASX256, |
| 15890 | /* XVILVL_W */ |
| 15891 | LASX256, LASX256, LASX256, |
| 15892 | /* XVINSGR2VR_D */ |
| 15893 | LASX256, LASX256, GPR, uimm2, |
| 15894 | /* XVINSGR2VR_W */ |
| 15895 | LASX256, LASX256, GPR, uimm3, |
| 15896 | /* XVINSVE0_D */ |
| 15897 | LASX256, LASX256, LASX256, uimm2, |
| 15898 | /* XVINSVE0_W */ |
| 15899 | LASX256, LASX256, LASX256, uimm3, |
| 15900 | /* XVLD */ |
| 15901 | LASX256, GPR, simm12, |
| 15902 | /* XVLDI */ |
| 15903 | LASX256, simm13, |
| 15904 | /* XVLDREPL_B */ |
| 15905 | LASX256, GPR, simm12, |
| 15906 | /* XVLDREPL_D */ |
| 15907 | LASX256, GPR, simm9_lsl3, |
| 15908 | /* XVLDREPL_H */ |
| 15909 | LASX256, GPR, simm11_lsl1, |
| 15910 | /* XVLDREPL_W */ |
| 15911 | LASX256, GPR, simm10_lsl2, |
| 15912 | /* XVLDX */ |
| 15913 | LASX256, GPR, GPR, |
| 15914 | /* XVMADDWEV_D_W */ |
| 15915 | LASX256, LASX256, LASX256, LASX256, |
| 15916 | /* XVMADDWEV_D_WU */ |
| 15917 | LASX256, LASX256, LASX256, LASX256, |
| 15918 | /* XVMADDWEV_D_WU_W */ |
| 15919 | LASX256, LASX256, LASX256, LASX256, |
| 15920 | /* XVMADDWEV_H_B */ |
| 15921 | LASX256, LASX256, LASX256, LASX256, |
| 15922 | /* XVMADDWEV_H_BU */ |
| 15923 | LASX256, LASX256, LASX256, LASX256, |
| 15924 | /* XVMADDWEV_H_BU_B */ |
| 15925 | LASX256, LASX256, LASX256, LASX256, |
| 15926 | /* XVMADDWEV_Q_D */ |
| 15927 | LASX256, LASX256, LASX256, LASX256, |
| 15928 | /* XVMADDWEV_Q_DU */ |
| 15929 | LASX256, LASX256, LASX256, LASX256, |
| 15930 | /* XVMADDWEV_Q_DU_D */ |
| 15931 | LASX256, LASX256, LASX256, LASX256, |
| 15932 | /* XVMADDWEV_W_H */ |
| 15933 | LASX256, LASX256, LASX256, LASX256, |
| 15934 | /* XVMADDWEV_W_HU */ |
| 15935 | LASX256, LASX256, LASX256, LASX256, |
| 15936 | /* XVMADDWEV_W_HU_H */ |
| 15937 | LASX256, LASX256, LASX256, LASX256, |
| 15938 | /* XVMADDWOD_D_W */ |
| 15939 | LASX256, LASX256, LASX256, LASX256, |
| 15940 | /* XVMADDWOD_D_WU */ |
| 15941 | LASX256, LASX256, LASX256, LASX256, |
| 15942 | /* XVMADDWOD_D_WU_W */ |
| 15943 | LASX256, LASX256, LASX256, LASX256, |
| 15944 | /* XVMADDWOD_H_B */ |
| 15945 | LASX256, LASX256, LASX256, LASX256, |
| 15946 | /* XVMADDWOD_H_BU */ |
| 15947 | LASX256, LASX256, LASX256, LASX256, |
| 15948 | /* XVMADDWOD_H_BU_B */ |
| 15949 | LASX256, LASX256, LASX256, LASX256, |
| 15950 | /* XVMADDWOD_Q_D */ |
| 15951 | LASX256, LASX256, LASX256, LASX256, |
| 15952 | /* XVMADDWOD_Q_DU */ |
| 15953 | LASX256, LASX256, LASX256, LASX256, |
| 15954 | /* XVMADDWOD_Q_DU_D */ |
| 15955 | LASX256, LASX256, LASX256, LASX256, |
| 15956 | /* XVMADDWOD_W_H */ |
| 15957 | LASX256, LASX256, LASX256, LASX256, |
| 15958 | /* XVMADDWOD_W_HU */ |
| 15959 | LASX256, LASX256, LASX256, LASX256, |
| 15960 | /* XVMADDWOD_W_HU_H */ |
| 15961 | LASX256, LASX256, LASX256, LASX256, |
| 15962 | /* XVMADD_B */ |
| 15963 | LASX256, LASX256, LASX256, LASX256, |
| 15964 | /* XVMADD_D */ |
| 15965 | LASX256, LASX256, LASX256, LASX256, |
| 15966 | /* XVMADD_H */ |
| 15967 | LASX256, LASX256, LASX256, LASX256, |
| 15968 | /* XVMADD_W */ |
| 15969 | LASX256, LASX256, LASX256, LASX256, |
| 15970 | /* XVMAXI_B */ |
| 15971 | LASX256, LASX256, simm5, |
| 15972 | /* XVMAXI_BU */ |
| 15973 | LASX256, LASX256, uimm5, |
| 15974 | /* XVMAXI_D */ |
| 15975 | LASX256, LASX256, simm5, |
| 15976 | /* XVMAXI_DU */ |
| 15977 | LASX256, LASX256, uimm5, |
| 15978 | /* XVMAXI_H */ |
| 15979 | LASX256, LASX256, simm5, |
| 15980 | /* XVMAXI_HU */ |
| 15981 | LASX256, LASX256, uimm5, |
| 15982 | /* XVMAXI_W */ |
| 15983 | LASX256, LASX256, simm5, |
| 15984 | /* XVMAXI_WU */ |
| 15985 | LASX256, LASX256, uimm5, |
| 15986 | /* XVMAX_B */ |
| 15987 | LASX256, LASX256, LASX256, |
| 15988 | /* XVMAX_BU */ |
| 15989 | LASX256, LASX256, LASX256, |
| 15990 | /* XVMAX_D */ |
| 15991 | LASX256, LASX256, LASX256, |
| 15992 | /* XVMAX_DU */ |
| 15993 | LASX256, LASX256, LASX256, |
| 15994 | /* XVMAX_H */ |
| 15995 | LASX256, LASX256, LASX256, |
| 15996 | /* XVMAX_HU */ |
| 15997 | LASX256, LASX256, LASX256, |
| 15998 | /* XVMAX_W */ |
| 15999 | LASX256, LASX256, LASX256, |
| 16000 | /* XVMAX_WU */ |
| 16001 | LASX256, LASX256, LASX256, |
| 16002 | /* XVMINI_B */ |
| 16003 | LASX256, LASX256, simm5, |
| 16004 | /* XVMINI_BU */ |
| 16005 | LASX256, LASX256, uimm5, |
| 16006 | /* XVMINI_D */ |
| 16007 | LASX256, LASX256, simm5, |
| 16008 | /* XVMINI_DU */ |
| 16009 | LASX256, LASX256, uimm5, |
| 16010 | /* XVMINI_H */ |
| 16011 | LASX256, LASX256, simm5, |
| 16012 | /* XVMINI_HU */ |
| 16013 | LASX256, LASX256, uimm5, |
| 16014 | /* XVMINI_W */ |
| 16015 | LASX256, LASX256, simm5, |
| 16016 | /* XVMINI_WU */ |
| 16017 | LASX256, LASX256, uimm5, |
| 16018 | /* XVMIN_B */ |
| 16019 | LASX256, LASX256, LASX256, |
| 16020 | /* XVMIN_BU */ |
| 16021 | LASX256, LASX256, LASX256, |
| 16022 | /* XVMIN_D */ |
| 16023 | LASX256, LASX256, LASX256, |
| 16024 | /* XVMIN_DU */ |
| 16025 | LASX256, LASX256, LASX256, |
| 16026 | /* XVMIN_H */ |
| 16027 | LASX256, LASX256, LASX256, |
| 16028 | /* XVMIN_HU */ |
| 16029 | LASX256, LASX256, LASX256, |
| 16030 | /* XVMIN_W */ |
| 16031 | LASX256, LASX256, LASX256, |
| 16032 | /* XVMIN_WU */ |
| 16033 | LASX256, LASX256, LASX256, |
| 16034 | /* XVMOD_B */ |
| 16035 | LASX256, LASX256, LASX256, |
| 16036 | /* XVMOD_BU */ |
| 16037 | LASX256, LASX256, LASX256, |
| 16038 | /* XVMOD_D */ |
| 16039 | LASX256, LASX256, LASX256, |
| 16040 | /* XVMOD_DU */ |
| 16041 | LASX256, LASX256, LASX256, |
| 16042 | /* XVMOD_H */ |
| 16043 | LASX256, LASX256, LASX256, |
| 16044 | /* XVMOD_HU */ |
| 16045 | LASX256, LASX256, LASX256, |
| 16046 | /* XVMOD_W */ |
| 16047 | LASX256, LASX256, LASX256, |
| 16048 | /* XVMOD_WU */ |
| 16049 | LASX256, LASX256, LASX256, |
| 16050 | /* XVMSKGEZ_B */ |
| 16051 | LASX256, LASX256, |
| 16052 | /* XVMSKLTZ_B */ |
| 16053 | LASX256, LASX256, |
| 16054 | /* XVMSKLTZ_D */ |
| 16055 | LASX256, LASX256, |
| 16056 | /* XVMSKLTZ_H */ |
| 16057 | LASX256, LASX256, |
| 16058 | /* XVMSKLTZ_W */ |
| 16059 | LASX256, LASX256, |
| 16060 | /* XVMSKNZ_B */ |
| 16061 | LASX256, LASX256, |
| 16062 | /* XVMSUB_B */ |
| 16063 | LASX256, LASX256, LASX256, LASX256, |
| 16064 | /* XVMSUB_D */ |
| 16065 | LASX256, LASX256, LASX256, LASX256, |
| 16066 | /* XVMSUB_H */ |
| 16067 | LASX256, LASX256, LASX256, LASX256, |
| 16068 | /* XVMSUB_W */ |
| 16069 | LASX256, LASX256, LASX256, LASX256, |
| 16070 | /* XVMUH_B */ |
| 16071 | LASX256, LASX256, LASX256, |
| 16072 | /* XVMUH_BU */ |
| 16073 | LASX256, LASX256, LASX256, |
| 16074 | /* XVMUH_D */ |
| 16075 | LASX256, LASX256, LASX256, |
| 16076 | /* XVMUH_DU */ |
| 16077 | LASX256, LASX256, LASX256, |
| 16078 | /* XVMUH_H */ |
| 16079 | LASX256, LASX256, LASX256, |
| 16080 | /* XVMUH_HU */ |
| 16081 | LASX256, LASX256, LASX256, |
| 16082 | /* XVMUH_W */ |
| 16083 | LASX256, LASX256, LASX256, |
| 16084 | /* XVMUH_WU */ |
| 16085 | LASX256, LASX256, LASX256, |
| 16086 | /* XVMULWEV_D_W */ |
| 16087 | LASX256, LASX256, LASX256, |
| 16088 | /* XVMULWEV_D_WU */ |
| 16089 | LASX256, LASX256, LASX256, |
| 16090 | /* XVMULWEV_D_WU_W */ |
| 16091 | LASX256, LASX256, LASX256, |
| 16092 | /* XVMULWEV_H_B */ |
| 16093 | LASX256, LASX256, LASX256, |
| 16094 | /* XVMULWEV_H_BU */ |
| 16095 | LASX256, LASX256, LASX256, |
| 16096 | /* XVMULWEV_H_BU_B */ |
| 16097 | LASX256, LASX256, LASX256, |
| 16098 | /* XVMULWEV_Q_D */ |
| 16099 | LASX256, LASX256, LASX256, |
| 16100 | /* XVMULWEV_Q_DU */ |
| 16101 | LASX256, LASX256, LASX256, |
| 16102 | /* XVMULWEV_Q_DU_D */ |
| 16103 | LASX256, LASX256, LASX256, |
| 16104 | /* XVMULWEV_W_H */ |
| 16105 | LASX256, LASX256, LASX256, |
| 16106 | /* XVMULWEV_W_HU */ |
| 16107 | LASX256, LASX256, LASX256, |
| 16108 | /* XVMULWEV_W_HU_H */ |
| 16109 | LASX256, LASX256, LASX256, |
| 16110 | /* XVMULWOD_D_W */ |
| 16111 | LASX256, LASX256, LASX256, |
| 16112 | /* XVMULWOD_D_WU */ |
| 16113 | LASX256, LASX256, LASX256, |
| 16114 | /* XVMULWOD_D_WU_W */ |
| 16115 | LASX256, LASX256, LASX256, |
| 16116 | /* XVMULWOD_H_B */ |
| 16117 | LASX256, LASX256, LASX256, |
| 16118 | /* XVMULWOD_H_BU */ |
| 16119 | LASX256, LASX256, LASX256, |
| 16120 | /* XVMULWOD_H_BU_B */ |
| 16121 | LASX256, LASX256, LASX256, |
| 16122 | /* XVMULWOD_Q_D */ |
| 16123 | LASX256, LASX256, LASX256, |
| 16124 | /* XVMULWOD_Q_DU */ |
| 16125 | LASX256, LASX256, LASX256, |
| 16126 | /* XVMULWOD_Q_DU_D */ |
| 16127 | LASX256, LASX256, LASX256, |
| 16128 | /* XVMULWOD_W_H */ |
| 16129 | LASX256, LASX256, LASX256, |
| 16130 | /* XVMULWOD_W_HU */ |
| 16131 | LASX256, LASX256, LASX256, |
| 16132 | /* XVMULWOD_W_HU_H */ |
| 16133 | LASX256, LASX256, LASX256, |
| 16134 | /* XVMUL_B */ |
| 16135 | LASX256, LASX256, LASX256, |
| 16136 | /* XVMUL_D */ |
| 16137 | LASX256, LASX256, LASX256, |
| 16138 | /* XVMUL_H */ |
| 16139 | LASX256, LASX256, LASX256, |
| 16140 | /* XVMUL_W */ |
| 16141 | LASX256, LASX256, LASX256, |
| 16142 | /* XVNEG_B */ |
| 16143 | LASX256, LASX256, |
| 16144 | /* XVNEG_D */ |
| 16145 | LASX256, LASX256, |
| 16146 | /* XVNEG_H */ |
| 16147 | LASX256, LASX256, |
| 16148 | /* XVNEG_W */ |
| 16149 | LASX256, LASX256, |
| 16150 | /* XVNORI_B */ |
| 16151 | LASX256, LASX256, uimm8, |
| 16152 | /* XVNOR_V */ |
| 16153 | LASX256, LASX256, LASX256, |
| 16154 | /* XVORI_B */ |
| 16155 | LASX256, LASX256, uimm8, |
| 16156 | /* XVORN_V */ |
| 16157 | LASX256, LASX256, LASX256, |
| 16158 | /* XVOR_V */ |
| 16159 | LASX256, LASX256, LASX256, |
| 16160 | /* XVPACKEV_B */ |
| 16161 | LASX256, LASX256, LASX256, |
| 16162 | /* XVPACKEV_D */ |
| 16163 | LASX256, LASX256, LASX256, |
| 16164 | /* XVPACKEV_H */ |
| 16165 | LASX256, LASX256, LASX256, |
| 16166 | /* XVPACKEV_W */ |
| 16167 | LASX256, LASX256, LASX256, |
| 16168 | /* XVPACKOD_B */ |
| 16169 | LASX256, LASX256, LASX256, |
| 16170 | /* XVPACKOD_D */ |
| 16171 | LASX256, LASX256, LASX256, |
| 16172 | /* XVPACKOD_H */ |
| 16173 | LASX256, LASX256, LASX256, |
| 16174 | /* XVPACKOD_W */ |
| 16175 | LASX256, LASX256, LASX256, |
| 16176 | /* XVPCNT_B */ |
| 16177 | LASX256, LASX256, |
| 16178 | /* XVPCNT_D */ |
| 16179 | LASX256, LASX256, |
| 16180 | /* XVPCNT_H */ |
| 16181 | LASX256, LASX256, |
| 16182 | /* XVPCNT_W */ |
| 16183 | LASX256, LASX256, |
| 16184 | /* XVPERMI_D */ |
| 16185 | LASX256, LASX256, uimm8, |
| 16186 | /* XVPERMI_Q */ |
| 16187 | LASX256, LASX256, LASX256, uimm8, |
| 16188 | /* XVPERMI_W */ |
| 16189 | LASX256, LASX256, LASX256, uimm8, |
| 16190 | /* XVPERM_W */ |
| 16191 | LASX256, LASX256, LASX256, |
| 16192 | /* XVPICKEV_B */ |
| 16193 | LASX256, LASX256, LASX256, |
| 16194 | /* XVPICKEV_D */ |
| 16195 | LASX256, LASX256, LASX256, |
| 16196 | /* XVPICKEV_H */ |
| 16197 | LASX256, LASX256, LASX256, |
| 16198 | /* XVPICKEV_W */ |
| 16199 | LASX256, LASX256, LASX256, |
| 16200 | /* XVPICKOD_B */ |
| 16201 | LASX256, LASX256, LASX256, |
| 16202 | /* XVPICKOD_D */ |
| 16203 | LASX256, LASX256, LASX256, |
| 16204 | /* XVPICKOD_H */ |
| 16205 | LASX256, LASX256, LASX256, |
| 16206 | /* XVPICKOD_W */ |
| 16207 | LASX256, LASX256, LASX256, |
| 16208 | /* XVPICKVE2GR_D */ |
| 16209 | GPR, LASX256, uimm2, |
| 16210 | /* XVPICKVE2GR_DU */ |
| 16211 | GPR, LASX256, uimm2, |
| 16212 | /* XVPICKVE2GR_W */ |
| 16213 | GPR, LASX256, uimm3, |
| 16214 | /* XVPICKVE2GR_WU */ |
| 16215 | GPR, LASX256, uimm3, |
| 16216 | /* XVPICKVE_D */ |
| 16217 | LASX256, LASX256, uimm2, |
| 16218 | /* XVPICKVE_W */ |
| 16219 | LASX256, LASX256, uimm3, |
| 16220 | /* XVREPL128VEI_B */ |
| 16221 | LASX256, LASX256, uimm4, |
| 16222 | /* XVREPL128VEI_D */ |
| 16223 | LASX256, LASX256, uimm1, |
| 16224 | /* XVREPL128VEI_H */ |
| 16225 | LASX256, LASX256, uimm3, |
| 16226 | /* XVREPL128VEI_W */ |
| 16227 | LASX256, LASX256, uimm2, |
| 16228 | /* XVREPLGR2VR_B */ |
| 16229 | LASX256, GPR, |
| 16230 | /* XVREPLGR2VR_D */ |
| 16231 | LASX256, GPR, |
| 16232 | /* XVREPLGR2VR_H */ |
| 16233 | LASX256, GPR, |
| 16234 | /* XVREPLGR2VR_W */ |
| 16235 | LASX256, GPR, |
| 16236 | /* XVREPLVE0_B */ |
| 16237 | LASX256, LASX256, |
| 16238 | /* XVREPLVE0_D */ |
| 16239 | LASX256, LASX256, |
| 16240 | /* XVREPLVE0_H */ |
| 16241 | LASX256, LASX256, |
| 16242 | /* XVREPLVE0_Q */ |
| 16243 | LASX256, LASX256, |
| 16244 | /* XVREPLVE0_W */ |
| 16245 | LASX256, LASX256, |
| 16246 | /* XVREPLVE_B */ |
| 16247 | LASX256, LASX256, GPR, |
| 16248 | /* XVREPLVE_D */ |
| 16249 | LASX256, LASX256, GPR, |
| 16250 | /* XVREPLVE_H */ |
| 16251 | LASX256, LASX256, GPR, |
| 16252 | /* XVREPLVE_W */ |
| 16253 | LASX256, LASX256, GPR, |
| 16254 | /* XVROTRI_B */ |
| 16255 | LASX256, LASX256, uimm3, |
| 16256 | /* XVROTRI_D */ |
| 16257 | LASX256, LASX256, uimm6, |
| 16258 | /* XVROTRI_H */ |
| 16259 | LASX256, LASX256, uimm4, |
| 16260 | /* XVROTRI_W */ |
| 16261 | LASX256, LASX256, uimm5, |
| 16262 | /* XVROTR_B */ |
| 16263 | LASX256, LASX256, LASX256, |
| 16264 | /* XVROTR_D */ |
| 16265 | LASX256, LASX256, LASX256, |
| 16266 | /* XVROTR_H */ |
| 16267 | LASX256, LASX256, LASX256, |
| 16268 | /* XVROTR_W */ |
| 16269 | LASX256, LASX256, LASX256, |
| 16270 | /* XVSADD_B */ |
| 16271 | LASX256, LASX256, LASX256, |
| 16272 | /* XVSADD_BU */ |
| 16273 | LASX256, LASX256, LASX256, |
| 16274 | /* XVSADD_D */ |
| 16275 | LASX256, LASX256, LASX256, |
| 16276 | /* XVSADD_DU */ |
| 16277 | LASX256, LASX256, LASX256, |
| 16278 | /* XVSADD_H */ |
| 16279 | LASX256, LASX256, LASX256, |
| 16280 | /* XVSADD_HU */ |
| 16281 | LASX256, LASX256, LASX256, |
| 16282 | /* XVSADD_W */ |
| 16283 | LASX256, LASX256, LASX256, |
| 16284 | /* XVSADD_WU */ |
| 16285 | LASX256, LASX256, LASX256, |
| 16286 | /* XVSAT_B */ |
| 16287 | LASX256, LASX256, uimm3, |
| 16288 | /* XVSAT_BU */ |
| 16289 | LASX256, LASX256, uimm3, |
| 16290 | /* XVSAT_D */ |
| 16291 | LASX256, LASX256, uimm6, |
| 16292 | /* XVSAT_DU */ |
| 16293 | LASX256, LASX256, uimm6, |
| 16294 | /* XVSAT_H */ |
| 16295 | LASX256, LASX256, uimm4, |
| 16296 | /* XVSAT_HU */ |
| 16297 | LASX256, LASX256, uimm4, |
| 16298 | /* XVSAT_W */ |
| 16299 | LASX256, LASX256, uimm5, |
| 16300 | /* XVSAT_WU */ |
| 16301 | LASX256, LASX256, uimm5, |
| 16302 | /* XVSEQI_B */ |
| 16303 | LASX256, LASX256, simm5, |
| 16304 | /* XVSEQI_D */ |
| 16305 | LASX256, LASX256, simm5, |
| 16306 | /* XVSEQI_H */ |
| 16307 | LASX256, LASX256, simm5, |
| 16308 | /* XVSEQI_W */ |
| 16309 | LASX256, LASX256, simm5, |
| 16310 | /* XVSEQ_B */ |
| 16311 | LASX256, LASX256, LASX256, |
| 16312 | /* XVSEQ_D */ |
| 16313 | LASX256, LASX256, LASX256, |
| 16314 | /* XVSEQ_H */ |
| 16315 | LASX256, LASX256, LASX256, |
| 16316 | /* XVSEQ_W */ |
| 16317 | LASX256, LASX256, LASX256, |
| 16318 | /* XVSETALLNEZ_B */ |
| 16319 | CFR, LASX256, |
| 16320 | /* XVSETALLNEZ_D */ |
| 16321 | CFR, LASX256, |
| 16322 | /* XVSETALLNEZ_H */ |
| 16323 | CFR, LASX256, |
| 16324 | /* XVSETALLNEZ_W */ |
| 16325 | CFR, LASX256, |
| 16326 | /* XVSETANYEQZ_B */ |
| 16327 | CFR, LASX256, |
| 16328 | /* XVSETANYEQZ_D */ |
| 16329 | CFR, LASX256, |
| 16330 | /* XVSETANYEQZ_H */ |
| 16331 | CFR, LASX256, |
| 16332 | /* XVSETANYEQZ_W */ |
| 16333 | CFR, LASX256, |
| 16334 | /* XVSETEQZ_V */ |
| 16335 | CFR, LASX256, |
| 16336 | /* XVSETNEZ_V */ |
| 16337 | CFR, LASX256, |
| 16338 | /* XVSHUF4I_B */ |
| 16339 | LASX256, LASX256, uimm8, |
| 16340 | /* XVSHUF4I_D */ |
| 16341 | LASX256, LASX256, LASX256, uimm8, |
| 16342 | /* XVSHUF4I_H */ |
| 16343 | LASX256, LASX256, uimm8, |
| 16344 | /* XVSHUF4I_W */ |
| 16345 | LASX256, LASX256, uimm8, |
| 16346 | /* XVSHUF_B */ |
| 16347 | LASX256, LASX256, LASX256, LASX256, |
| 16348 | /* XVSHUF_D */ |
| 16349 | LASX256, LASX256, LASX256, LASX256, |
| 16350 | /* XVSHUF_H */ |
| 16351 | LASX256, LASX256, LASX256, LASX256, |
| 16352 | /* XVSHUF_W */ |
| 16353 | LASX256, LASX256, LASX256, LASX256, |
| 16354 | /* XVSIGNCOV_B */ |
| 16355 | LASX256, LASX256, LASX256, |
| 16356 | /* XVSIGNCOV_D */ |
| 16357 | LASX256, LASX256, LASX256, |
| 16358 | /* XVSIGNCOV_H */ |
| 16359 | LASX256, LASX256, LASX256, |
| 16360 | /* XVSIGNCOV_W */ |
| 16361 | LASX256, LASX256, LASX256, |
| 16362 | /* XVSLEI_B */ |
| 16363 | LASX256, LASX256, simm5, |
| 16364 | /* XVSLEI_BU */ |
| 16365 | LASX256, LASX256, uimm5, |
| 16366 | /* XVSLEI_D */ |
| 16367 | LASX256, LASX256, simm5, |
| 16368 | /* XVSLEI_DU */ |
| 16369 | LASX256, LASX256, uimm5, |
| 16370 | /* XVSLEI_H */ |
| 16371 | LASX256, LASX256, simm5, |
| 16372 | /* XVSLEI_HU */ |
| 16373 | LASX256, LASX256, uimm5, |
| 16374 | /* XVSLEI_W */ |
| 16375 | LASX256, LASX256, simm5, |
| 16376 | /* XVSLEI_WU */ |
| 16377 | LASX256, LASX256, uimm5, |
| 16378 | /* XVSLE_B */ |
| 16379 | LASX256, LASX256, LASX256, |
| 16380 | /* XVSLE_BU */ |
| 16381 | LASX256, LASX256, LASX256, |
| 16382 | /* XVSLE_D */ |
| 16383 | LASX256, LASX256, LASX256, |
| 16384 | /* XVSLE_DU */ |
| 16385 | LASX256, LASX256, LASX256, |
| 16386 | /* XVSLE_H */ |
| 16387 | LASX256, LASX256, LASX256, |
| 16388 | /* XVSLE_HU */ |
| 16389 | LASX256, LASX256, LASX256, |
| 16390 | /* XVSLE_W */ |
| 16391 | LASX256, LASX256, LASX256, |
| 16392 | /* XVSLE_WU */ |
| 16393 | LASX256, LASX256, LASX256, |
| 16394 | /* XVSLLI_B */ |
| 16395 | LASX256, LASX256, uimm3, |
| 16396 | /* XVSLLI_D */ |
| 16397 | LASX256, LASX256, uimm6, |
| 16398 | /* XVSLLI_H */ |
| 16399 | LASX256, LASX256, uimm4, |
| 16400 | /* XVSLLI_W */ |
| 16401 | LASX256, LASX256, uimm5, |
| 16402 | /* XVSLLWIL_DU_WU */ |
| 16403 | LASX256, LASX256, uimm5, |
| 16404 | /* XVSLLWIL_D_W */ |
| 16405 | LASX256, LASX256, uimm5, |
| 16406 | /* XVSLLWIL_HU_BU */ |
| 16407 | LASX256, LASX256, uimm3, |
| 16408 | /* XVSLLWIL_H_B */ |
| 16409 | LASX256, LASX256, uimm3, |
| 16410 | /* XVSLLWIL_WU_HU */ |
| 16411 | LASX256, LASX256, uimm4, |
| 16412 | /* XVSLLWIL_W_H */ |
| 16413 | LASX256, LASX256, uimm4, |
| 16414 | /* XVSLL_B */ |
| 16415 | LASX256, LASX256, LASX256, |
| 16416 | /* XVSLL_D */ |
| 16417 | LASX256, LASX256, LASX256, |
| 16418 | /* XVSLL_H */ |
| 16419 | LASX256, LASX256, LASX256, |
| 16420 | /* XVSLL_W */ |
| 16421 | LASX256, LASX256, LASX256, |
| 16422 | /* XVSLTI_B */ |
| 16423 | LASX256, LASX256, simm5, |
| 16424 | /* XVSLTI_BU */ |
| 16425 | LASX256, LASX256, uimm5, |
| 16426 | /* XVSLTI_D */ |
| 16427 | LASX256, LASX256, simm5, |
| 16428 | /* XVSLTI_DU */ |
| 16429 | LASX256, LASX256, uimm5, |
| 16430 | /* XVSLTI_H */ |
| 16431 | LASX256, LASX256, simm5, |
| 16432 | /* XVSLTI_HU */ |
| 16433 | LASX256, LASX256, uimm5, |
| 16434 | /* XVSLTI_W */ |
| 16435 | LASX256, LASX256, simm5, |
| 16436 | /* XVSLTI_WU */ |
| 16437 | LASX256, LASX256, uimm5, |
| 16438 | /* XVSLT_B */ |
| 16439 | LASX256, LASX256, LASX256, |
| 16440 | /* XVSLT_BU */ |
| 16441 | LASX256, LASX256, LASX256, |
| 16442 | /* XVSLT_D */ |
| 16443 | LASX256, LASX256, LASX256, |
| 16444 | /* XVSLT_DU */ |
| 16445 | LASX256, LASX256, LASX256, |
| 16446 | /* XVSLT_H */ |
| 16447 | LASX256, LASX256, LASX256, |
| 16448 | /* XVSLT_HU */ |
| 16449 | LASX256, LASX256, LASX256, |
| 16450 | /* XVSLT_W */ |
| 16451 | LASX256, LASX256, LASX256, |
| 16452 | /* XVSLT_WU */ |
| 16453 | LASX256, LASX256, LASX256, |
| 16454 | /* XVSRAI_B */ |
| 16455 | LASX256, LASX256, uimm3, |
| 16456 | /* XVSRAI_D */ |
| 16457 | LASX256, LASX256, uimm6, |
| 16458 | /* XVSRAI_H */ |
| 16459 | LASX256, LASX256, uimm4, |
| 16460 | /* XVSRAI_W */ |
| 16461 | LASX256, LASX256, uimm5, |
| 16462 | /* XVSRANI_B_H */ |
| 16463 | LASX256, LASX256, LASX256, uimm4, |
| 16464 | /* XVSRANI_D_Q */ |
| 16465 | LASX256, LASX256, LASX256, uimm7, |
| 16466 | /* XVSRANI_H_W */ |
| 16467 | LASX256, LASX256, LASX256, uimm5, |
| 16468 | /* XVSRANI_W_D */ |
| 16469 | LASX256, LASX256, LASX256, uimm6, |
| 16470 | /* XVSRAN_B_H */ |
| 16471 | LASX256, LASX256, LASX256, |
| 16472 | /* XVSRAN_H_W */ |
| 16473 | LASX256, LASX256, LASX256, |
| 16474 | /* XVSRAN_W_D */ |
| 16475 | LASX256, LASX256, LASX256, |
| 16476 | /* XVSRARI_B */ |
| 16477 | LASX256, LASX256, uimm3, |
| 16478 | /* XVSRARI_D */ |
| 16479 | LASX256, LASX256, uimm6, |
| 16480 | /* XVSRARI_H */ |
| 16481 | LASX256, LASX256, uimm4, |
| 16482 | /* XVSRARI_W */ |
| 16483 | LASX256, LASX256, uimm5, |
| 16484 | /* XVSRARNI_B_H */ |
| 16485 | LASX256, LASX256, LASX256, uimm4, |
| 16486 | /* XVSRARNI_D_Q */ |
| 16487 | LASX256, LASX256, LASX256, uimm7, |
| 16488 | /* XVSRARNI_H_W */ |
| 16489 | LASX256, LASX256, LASX256, uimm5, |
| 16490 | /* XVSRARNI_W_D */ |
| 16491 | LASX256, LASX256, LASX256, uimm6, |
| 16492 | /* XVSRARN_B_H */ |
| 16493 | LASX256, LASX256, LASX256, |
| 16494 | /* XVSRARN_H_W */ |
| 16495 | LASX256, LASX256, LASX256, |
| 16496 | /* XVSRARN_W_D */ |
| 16497 | LASX256, LASX256, LASX256, |
| 16498 | /* XVSRAR_B */ |
| 16499 | LASX256, LASX256, LASX256, |
| 16500 | /* XVSRAR_D */ |
| 16501 | LASX256, LASX256, LASX256, |
| 16502 | /* XVSRAR_H */ |
| 16503 | LASX256, LASX256, LASX256, |
| 16504 | /* XVSRAR_W */ |
| 16505 | LASX256, LASX256, LASX256, |
| 16506 | /* XVSRA_B */ |
| 16507 | LASX256, LASX256, LASX256, |
| 16508 | /* XVSRA_D */ |
| 16509 | LASX256, LASX256, LASX256, |
| 16510 | /* XVSRA_H */ |
| 16511 | LASX256, LASX256, LASX256, |
| 16512 | /* XVSRA_W */ |
| 16513 | LASX256, LASX256, LASX256, |
| 16514 | /* XVSRLI_B */ |
| 16515 | LASX256, LASX256, uimm3, |
| 16516 | /* XVSRLI_D */ |
| 16517 | LASX256, LASX256, uimm6, |
| 16518 | /* XVSRLI_H */ |
| 16519 | LASX256, LASX256, uimm4, |
| 16520 | /* XVSRLI_W */ |
| 16521 | LASX256, LASX256, uimm5, |
| 16522 | /* XVSRLNI_B_H */ |
| 16523 | LASX256, LASX256, LASX256, uimm4, |
| 16524 | /* XVSRLNI_D_Q */ |
| 16525 | LASX256, LASX256, LASX256, uimm7, |
| 16526 | /* XVSRLNI_H_W */ |
| 16527 | LASX256, LASX256, LASX256, uimm5, |
| 16528 | /* XVSRLNI_W_D */ |
| 16529 | LASX256, LASX256, LASX256, uimm6, |
| 16530 | /* XVSRLN_B_H */ |
| 16531 | LASX256, LASX256, LASX256, |
| 16532 | /* XVSRLN_H_W */ |
| 16533 | LASX256, LASX256, LASX256, |
| 16534 | /* XVSRLN_W_D */ |
| 16535 | LASX256, LASX256, LASX256, |
| 16536 | /* XVSRLRI_B */ |
| 16537 | LASX256, LASX256, uimm3, |
| 16538 | /* XVSRLRI_D */ |
| 16539 | LASX256, LASX256, uimm6, |
| 16540 | /* XVSRLRI_H */ |
| 16541 | LASX256, LASX256, uimm4, |
| 16542 | /* XVSRLRI_W */ |
| 16543 | LASX256, LASX256, uimm5, |
| 16544 | /* XVSRLRNI_B_H */ |
| 16545 | LASX256, LASX256, LASX256, uimm4, |
| 16546 | /* XVSRLRNI_D_Q */ |
| 16547 | LASX256, LASX256, LASX256, uimm7, |
| 16548 | /* XVSRLRNI_H_W */ |
| 16549 | LASX256, LASX256, LASX256, uimm5, |
| 16550 | /* XVSRLRNI_W_D */ |
| 16551 | LASX256, LASX256, LASX256, uimm6, |
| 16552 | /* XVSRLRN_B_H */ |
| 16553 | LASX256, LASX256, LASX256, |
| 16554 | /* XVSRLRN_H_W */ |
| 16555 | LASX256, LASX256, LASX256, |
| 16556 | /* XVSRLRN_W_D */ |
| 16557 | LASX256, LASX256, LASX256, |
| 16558 | /* XVSRLR_B */ |
| 16559 | LASX256, LASX256, LASX256, |
| 16560 | /* XVSRLR_D */ |
| 16561 | LASX256, LASX256, LASX256, |
| 16562 | /* XVSRLR_H */ |
| 16563 | LASX256, LASX256, LASX256, |
| 16564 | /* XVSRLR_W */ |
| 16565 | LASX256, LASX256, LASX256, |
| 16566 | /* XVSRL_B */ |
| 16567 | LASX256, LASX256, LASX256, |
| 16568 | /* XVSRL_D */ |
| 16569 | LASX256, LASX256, LASX256, |
| 16570 | /* XVSRL_H */ |
| 16571 | LASX256, LASX256, LASX256, |
| 16572 | /* XVSRL_W */ |
| 16573 | LASX256, LASX256, LASX256, |
| 16574 | /* XVSSRANI_BU_H */ |
| 16575 | LASX256, LASX256, LASX256, uimm4, |
| 16576 | /* XVSSRANI_B_H */ |
| 16577 | LASX256, LASX256, LASX256, uimm4, |
| 16578 | /* XVSSRANI_DU_Q */ |
| 16579 | LASX256, LASX256, LASX256, uimm7, |
| 16580 | /* XVSSRANI_D_Q */ |
| 16581 | LASX256, LASX256, LASX256, uimm7, |
| 16582 | /* XVSSRANI_HU_W */ |
| 16583 | LASX256, LASX256, LASX256, uimm5, |
| 16584 | /* XVSSRANI_H_W */ |
| 16585 | LASX256, LASX256, LASX256, uimm5, |
| 16586 | /* XVSSRANI_WU_D */ |
| 16587 | LASX256, LASX256, LASX256, uimm6, |
| 16588 | /* XVSSRANI_W_D */ |
| 16589 | LASX256, LASX256, LASX256, uimm6, |
| 16590 | /* XVSSRAN_BU_H */ |
| 16591 | LASX256, LASX256, LASX256, |
| 16592 | /* XVSSRAN_B_H */ |
| 16593 | LASX256, LASX256, LASX256, |
| 16594 | /* XVSSRAN_HU_W */ |
| 16595 | LASX256, LASX256, LASX256, |
| 16596 | /* XVSSRAN_H_W */ |
| 16597 | LASX256, LASX256, LASX256, |
| 16598 | /* XVSSRAN_WU_D */ |
| 16599 | LASX256, LASX256, LASX256, |
| 16600 | /* XVSSRAN_W_D */ |
| 16601 | LASX256, LASX256, LASX256, |
| 16602 | /* XVSSRARNI_BU_H */ |
| 16603 | LASX256, LASX256, LASX256, uimm4, |
| 16604 | /* XVSSRARNI_B_H */ |
| 16605 | LASX256, LASX256, LASX256, uimm4, |
| 16606 | /* XVSSRARNI_DU_Q */ |
| 16607 | LASX256, LASX256, LASX256, uimm7, |
| 16608 | /* XVSSRARNI_D_Q */ |
| 16609 | LASX256, LASX256, LASX256, uimm7, |
| 16610 | /* XVSSRARNI_HU_W */ |
| 16611 | LASX256, LASX256, LASX256, uimm5, |
| 16612 | /* XVSSRARNI_H_W */ |
| 16613 | LASX256, LASX256, LASX256, uimm5, |
| 16614 | /* XVSSRARNI_WU_D */ |
| 16615 | LASX256, LASX256, LASX256, uimm6, |
| 16616 | /* XVSSRARNI_W_D */ |
| 16617 | LASX256, LASX256, LASX256, uimm6, |
| 16618 | /* XVSSRARN_BU_H */ |
| 16619 | LASX256, LASX256, LASX256, |
| 16620 | /* XVSSRARN_B_H */ |
| 16621 | LASX256, LASX256, LASX256, |
| 16622 | /* XVSSRARN_HU_W */ |
| 16623 | LASX256, LASX256, LASX256, |
| 16624 | /* XVSSRARN_H_W */ |
| 16625 | LASX256, LASX256, LASX256, |
| 16626 | /* XVSSRARN_WU_D */ |
| 16627 | LASX256, LASX256, LASX256, |
| 16628 | /* XVSSRARN_W_D */ |
| 16629 | LASX256, LASX256, LASX256, |
| 16630 | /* XVSSRLNI_BU_H */ |
| 16631 | LASX256, LASX256, LASX256, uimm4, |
| 16632 | /* XVSSRLNI_B_H */ |
| 16633 | LASX256, LASX256, LASX256, uimm4, |
| 16634 | /* XVSSRLNI_DU_Q */ |
| 16635 | LASX256, LASX256, LASX256, uimm7, |
| 16636 | /* XVSSRLNI_D_Q */ |
| 16637 | LASX256, LASX256, LASX256, uimm7, |
| 16638 | /* XVSSRLNI_HU_W */ |
| 16639 | LASX256, LASX256, LASX256, uimm5, |
| 16640 | /* XVSSRLNI_H_W */ |
| 16641 | LASX256, LASX256, LASX256, uimm5, |
| 16642 | /* XVSSRLNI_WU_D */ |
| 16643 | LASX256, LASX256, LASX256, uimm6, |
| 16644 | /* XVSSRLNI_W_D */ |
| 16645 | LASX256, LASX256, LASX256, uimm6, |
| 16646 | /* XVSSRLN_BU_H */ |
| 16647 | LASX256, LASX256, LASX256, |
| 16648 | /* XVSSRLN_B_H */ |
| 16649 | LASX256, LASX256, LASX256, |
| 16650 | /* XVSSRLN_HU_W */ |
| 16651 | LASX256, LASX256, LASX256, |
| 16652 | /* XVSSRLN_H_W */ |
| 16653 | LASX256, LASX256, LASX256, |
| 16654 | /* XVSSRLN_WU_D */ |
| 16655 | LASX256, LASX256, LASX256, |
| 16656 | /* XVSSRLN_W_D */ |
| 16657 | LASX256, LASX256, LASX256, |
| 16658 | /* XVSSRLRNI_BU_H */ |
| 16659 | LASX256, LASX256, LASX256, uimm4, |
| 16660 | /* XVSSRLRNI_B_H */ |
| 16661 | LASX256, LASX256, LASX256, uimm4, |
| 16662 | /* XVSSRLRNI_DU_Q */ |
| 16663 | LASX256, LASX256, LASX256, uimm7, |
| 16664 | /* XVSSRLRNI_D_Q */ |
| 16665 | LASX256, LASX256, LASX256, uimm7, |
| 16666 | /* XVSSRLRNI_HU_W */ |
| 16667 | LASX256, LASX256, LASX256, uimm5, |
| 16668 | /* XVSSRLRNI_H_W */ |
| 16669 | LASX256, LASX256, LASX256, uimm5, |
| 16670 | /* XVSSRLRNI_WU_D */ |
| 16671 | LASX256, LASX256, LASX256, uimm6, |
| 16672 | /* XVSSRLRNI_W_D */ |
| 16673 | LASX256, LASX256, LASX256, uimm6, |
| 16674 | /* XVSSRLRN_BU_H */ |
| 16675 | LASX256, LASX256, LASX256, |
| 16676 | /* XVSSRLRN_B_H */ |
| 16677 | LASX256, LASX256, LASX256, |
| 16678 | /* XVSSRLRN_HU_W */ |
| 16679 | LASX256, LASX256, LASX256, |
| 16680 | /* XVSSRLRN_H_W */ |
| 16681 | LASX256, LASX256, LASX256, |
| 16682 | /* XVSSRLRN_WU_D */ |
| 16683 | LASX256, LASX256, LASX256, |
| 16684 | /* XVSSRLRN_W_D */ |
| 16685 | LASX256, LASX256, LASX256, |
| 16686 | /* XVSSUB_B */ |
| 16687 | LASX256, LASX256, LASX256, |
| 16688 | /* XVSSUB_BU */ |
| 16689 | LASX256, LASX256, LASX256, |
| 16690 | /* XVSSUB_D */ |
| 16691 | LASX256, LASX256, LASX256, |
| 16692 | /* XVSSUB_DU */ |
| 16693 | LASX256, LASX256, LASX256, |
| 16694 | /* XVSSUB_H */ |
| 16695 | LASX256, LASX256, LASX256, |
| 16696 | /* XVSSUB_HU */ |
| 16697 | LASX256, LASX256, LASX256, |
| 16698 | /* XVSSUB_W */ |
| 16699 | LASX256, LASX256, LASX256, |
| 16700 | /* XVSSUB_WU */ |
| 16701 | LASX256, LASX256, LASX256, |
| 16702 | /* XVST */ |
| 16703 | LASX256, GPR, simm12, |
| 16704 | /* XVSTELM_B */ |
| 16705 | LASX256, GPR, simm8, uimm5, |
| 16706 | /* XVSTELM_D */ |
| 16707 | LASX256, GPR, simm8_lsl3, uimm2, |
| 16708 | /* XVSTELM_H */ |
| 16709 | LASX256, GPR, simm8_lsl1, uimm4, |
| 16710 | /* XVSTELM_W */ |
| 16711 | LASX256, GPR, simm8_lsl2, uimm3, |
| 16712 | /* XVSTX */ |
| 16713 | LASX256, GPR, GPR, |
| 16714 | /* XVSUBI_BU */ |
| 16715 | LASX256, LASX256, uimm5, |
| 16716 | /* XVSUBI_DU */ |
| 16717 | LASX256, LASX256, uimm5, |
| 16718 | /* XVSUBI_HU */ |
| 16719 | LASX256, LASX256, uimm5, |
| 16720 | /* XVSUBI_WU */ |
| 16721 | LASX256, LASX256, uimm5, |
| 16722 | /* XVSUBWEV_D_W */ |
| 16723 | LASX256, LASX256, LASX256, |
| 16724 | /* XVSUBWEV_D_WU */ |
| 16725 | LASX256, LASX256, LASX256, |
| 16726 | /* XVSUBWEV_H_B */ |
| 16727 | LASX256, LASX256, LASX256, |
| 16728 | /* XVSUBWEV_H_BU */ |
| 16729 | LASX256, LASX256, LASX256, |
| 16730 | /* XVSUBWEV_Q_D */ |
| 16731 | LASX256, LASX256, LASX256, |
| 16732 | /* XVSUBWEV_Q_DU */ |
| 16733 | LASX256, LASX256, LASX256, |
| 16734 | /* XVSUBWEV_W_H */ |
| 16735 | LASX256, LASX256, LASX256, |
| 16736 | /* XVSUBWEV_W_HU */ |
| 16737 | LASX256, LASX256, LASX256, |
| 16738 | /* XVSUBWOD_D_W */ |
| 16739 | LASX256, LASX256, LASX256, |
| 16740 | /* XVSUBWOD_D_WU */ |
| 16741 | LASX256, LASX256, LASX256, |
| 16742 | /* XVSUBWOD_H_B */ |
| 16743 | LASX256, LASX256, LASX256, |
| 16744 | /* XVSUBWOD_H_BU */ |
| 16745 | LASX256, LASX256, LASX256, |
| 16746 | /* XVSUBWOD_Q_D */ |
| 16747 | LASX256, LASX256, LASX256, |
| 16748 | /* XVSUBWOD_Q_DU */ |
| 16749 | LASX256, LASX256, LASX256, |
| 16750 | /* XVSUBWOD_W_H */ |
| 16751 | LASX256, LASX256, LASX256, |
| 16752 | /* XVSUBWOD_W_HU */ |
| 16753 | LASX256, LASX256, LASX256, |
| 16754 | /* XVSUB_B */ |
| 16755 | LASX256, LASX256, LASX256, |
| 16756 | /* XVSUB_D */ |
| 16757 | LASX256, LASX256, LASX256, |
| 16758 | /* XVSUB_H */ |
| 16759 | LASX256, LASX256, LASX256, |
| 16760 | /* XVSUB_Q */ |
| 16761 | LASX256, LASX256, LASX256, |
| 16762 | /* XVSUB_W */ |
| 16763 | LASX256, LASX256, LASX256, |
| 16764 | /* XVXORI_B */ |
| 16765 | LASX256, LASX256, uimm8, |
| 16766 | /* XVXOR_V */ |
| 16767 | LASX256, LASX256, LASX256, |
| 16768 | }; |
| 16769 | return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; |
| 16770 | } |
| 16771 | } // end namespace LoongArch |
| 16772 | } // end namespace llvm |
| 16773 | #endif // GET_INSTRINFO_OPERAND_TYPE |
| 16774 | |
| 16775 | #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE |
| 16776 | #undef GET_INSTRINFO_MEM_OPERAND_SIZE |
| 16777 | namespace llvm { |
| 16778 | namespace LoongArch { |
| 16779 | LLVM_READONLY |
| 16780 | static int getMemOperandSize(int OpType) { |
| 16781 | switch (OpType) { |
| 16782 | default: return 0; |
| 16783 | } |
| 16784 | } |
| 16785 | } // end namespace LoongArch |
| 16786 | } // end namespace llvm |
| 16787 | #endif // GET_INSTRINFO_MEM_OPERAND_SIZE |
| 16788 | |
| 16789 | #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| 16790 | #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| 16791 | namespace llvm { |
| 16792 | namespace LoongArch { |
| 16793 | LLVM_READONLY static unsigned |
| 16794 | getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| 16795 | return LogicalOpIdx; |
| 16796 | } |
| 16797 | LLVM_READONLY static inline unsigned |
| 16798 | getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| 16799 | auto S = 0U; |
| 16800 | for (auto i = 0U; i < LogicalOpIdx; ++i) |
| 16801 | S += getLogicalOperandSize(Opcode, i); |
| 16802 | return S; |
| 16803 | } |
| 16804 | } // end namespace LoongArch |
| 16805 | } // end namespace llvm |
| 16806 | #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| 16807 | |
| 16808 | #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| 16809 | #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| 16810 | namespace llvm { |
| 16811 | namespace LoongArch { |
| 16812 | LLVM_READONLY static int |
| 16813 | getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| 16814 | return -1; |
| 16815 | } |
| 16816 | } // end namespace LoongArch |
| 16817 | } // end namespace llvm |
| 16818 | #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| 16819 | |
| 16820 | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| 16821 | #undef GET_INSTRINFO_MC_HELPER_DECLS |
| 16822 | |
| 16823 | namespace llvm { |
| 16824 | class MCInst; |
| 16825 | class FeatureBitset; |
| 16826 | |
| 16827 | namespace LoongArch_MC { |
| 16828 | |
| 16829 | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| 16830 | |
| 16831 | } // end namespace LoongArch_MC |
| 16832 | } // end namespace llvm |
| 16833 | |
| 16834 | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| 16835 | |
| 16836 | #ifdef GET_INSTRINFO_MC_HELPERS |
| 16837 | #undef GET_INSTRINFO_MC_HELPERS |
| 16838 | |
| 16839 | namespace llvm { |
| 16840 | namespace LoongArch_MC { |
| 16841 | |
| 16842 | } // end namespace LoongArch_MC |
| 16843 | } // end namespace llvm |
| 16844 | |
| 16845 | #endif // GET_GENISTRINFO_MC_HELPERS |
| 16846 | |
| 16847 | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
| 16848 | defined(GET_AVAILABLE_OPCODE_CHECKER) |
| 16849 | #define GET_COMPUTE_FEATURES |
| 16850 | #endif |
| 16851 | #ifdef GET_COMPUTE_FEATURES |
| 16852 | #undef GET_COMPUTE_FEATURES |
| 16853 | namespace llvm { |
| 16854 | namespace LoongArch_MC { |
| 16855 | |
| 16856 | // Bits for subtarget features that participate in instruction matching. |
| 16857 | enum SubtargetFeatureBits : uint8_t { |
| 16858 | Feature_IsLA64Bit = 4, |
| 16859 | Feature_IsLA32Bit = 3, |
| 16860 | Feature_HasLaGlobalWithPcrelBit = 1, |
| 16861 | Feature_HasLaGlobalWithAbsBit = 0, |
| 16862 | Feature_HasLaLocalWithAbsBit = 2, |
| 16863 | }; |
| 16864 | |
| 16865 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| 16866 | FeatureBitset Features; |
| 16867 | if (FB[LoongArch::Feature64Bit]) |
| 16868 | Features.set(Feature_IsLA64Bit); |
| 16869 | if (!FB[LoongArch::Feature64Bit]) |
| 16870 | Features.set(Feature_IsLA32Bit); |
| 16871 | if (FB[LoongArch::LaGlobalWithPcrel]) |
| 16872 | Features.set(Feature_HasLaGlobalWithPcrelBit); |
| 16873 | if (FB[LoongArch::LaGlobalWithAbs]) |
| 16874 | Features.set(Feature_HasLaGlobalWithAbsBit); |
| 16875 | if (FB[LoongArch::LaLocalWithAbs]) |
| 16876 | Features.set(Feature_HasLaLocalWithAbsBit); |
| 16877 | return Features; |
| 16878 | } |
| 16879 | |
| 16880 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
| 16881 | enum : uint8_t { |
| 16882 | CEFBS_None, |
| 16883 | CEFBS_IsLA32, |
| 16884 | CEFBS_IsLA64, |
| 16885 | CEFBS_IsLA32_HasLaGlobalWithAbs, |
| 16886 | CEFBS_IsLA64_HasLaGlobalWithAbs, |
| 16887 | }; |
| 16888 | |
| 16889 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 16890 | {}, // CEFBS_None |
| 16891 | {Feature_IsLA32Bit, }, |
| 16892 | {Feature_IsLA64Bit, }, |
| 16893 | {Feature_IsLA32Bit, Feature_HasLaGlobalWithAbsBit, }, |
| 16894 | {Feature_IsLA64Bit, Feature_HasLaGlobalWithAbsBit, }, |
| 16895 | }; |
| 16896 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
| 16897 | CEFBS_None, // PHI = 0 |
| 16898 | CEFBS_None, // INLINEASM = 1 |
| 16899 | CEFBS_None, // INLINEASM_BR = 2 |
| 16900 | CEFBS_None, // CFI_INSTRUCTION = 3 |
| 16901 | CEFBS_None, // EH_LABEL = 4 |
| 16902 | CEFBS_None, // GC_LABEL = 5 |
| 16903 | CEFBS_None, // ANNOTATION_LABEL = 6 |
| 16904 | CEFBS_None, // KILL = 7 |
| 16905 | CEFBS_None, // EXTRACT_SUBREG = 8 |
| 16906 | CEFBS_None, // INSERT_SUBREG = 9 |
| 16907 | CEFBS_None, // IMPLICIT_DEF = 10 |
| 16908 | CEFBS_None, // SUBREG_TO_REG = 11 |
| 16909 | CEFBS_None, // COPY_TO_REGCLASS = 12 |
| 16910 | CEFBS_None, // DBG_VALUE = 13 |
| 16911 | CEFBS_None, // DBG_VALUE_LIST = 14 |
| 16912 | CEFBS_None, // DBG_INSTR_REF = 15 |
| 16913 | CEFBS_None, // DBG_PHI = 16 |
| 16914 | CEFBS_None, // DBG_LABEL = 17 |
| 16915 | CEFBS_None, // REG_SEQUENCE = 18 |
| 16916 | CEFBS_None, // COPY = 19 |
| 16917 | CEFBS_None, // BUNDLE = 20 |
| 16918 | CEFBS_None, // LIFETIME_START = 21 |
| 16919 | CEFBS_None, // LIFETIME_END = 22 |
| 16920 | CEFBS_None, // PSEUDO_PROBE = 23 |
| 16921 | CEFBS_None, // ARITH_FENCE = 24 |
| 16922 | CEFBS_None, // STACKMAP = 25 |
| 16923 | CEFBS_None, // FENTRY_CALL = 26 |
| 16924 | CEFBS_None, // PATCHPOINT = 27 |
| 16925 | CEFBS_None, // LOAD_STACK_GUARD = 28 |
| 16926 | CEFBS_None, // PREALLOCATED_SETUP = 29 |
| 16927 | CEFBS_None, // PREALLOCATED_ARG = 30 |
| 16928 | CEFBS_None, // STATEPOINT = 31 |
| 16929 | CEFBS_None, // LOCAL_ESCAPE = 32 |
| 16930 | CEFBS_None, // FAULTING_OP = 33 |
| 16931 | CEFBS_None, // PATCHABLE_OP = 34 |
| 16932 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 |
| 16933 | CEFBS_None, // PATCHABLE_RET = 36 |
| 16934 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 |
| 16935 | CEFBS_None, // PATCHABLE_TAIL_CALL = 38 |
| 16936 | CEFBS_None, // PATCHABLE_EVENT_CALL = 39 |
| 16937 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 |
| 16938 | CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 |
| 16939 | CEFBS_None, // MEMBARRIER = 42 |
| 16940 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43 |
| 16941 | CEFBS_None, // CONVERGENCECTRL_ENTRY = 44 |
| 16942 | CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45 |
| 16943 | CEFBS_None, // CONVERGENCECTRL_LOOP = 46 |
| 16944 | CEFBS_None, // CONVERGENCECTRL_GLUE = 47 |
| 16945 | CEFBS_None, // G_ASSERT_SEXT = 48 |
| 16946 | CEFBS_None, // G_ASSERT_ZEXT = 49 |
| 16947 | CEFBS_None, // G_ASSERT_ALIGN = 50 |
| 16948 | CEFBS_None, // G_ADD = 51 |
| 16949 | CEFBS_None, // G_SUB = 52 |
| 16950 | CEFBS_None, // G_MUL = 53 |
| 16951 | CEFBS_None, // G_SDIV = 54 |
| 16952 | CEFBS_None, // G_UDIV = 55 |
| 16953 | CEFBS_None, // G_SREM = 56 |
| 16954 | CEFBS_None, // G_UREM = 57 |
| 16955 | CEFBS_None, // G_SDIVREM = 58 |
| 16956 | CEFBS_None, // G_UDIVREM = 59 |
| 16957 | CEFBS_None, // G_AND = 60 |
| 16958 | CEFBS_None, // G_OR = 61 |
| 16959 | CEFBS_None, // G_XOR = 62 |
| 16960 | CEFBS_None, // G_IMPLICIT_DEF = 63 |
| 16961 | CEFBS_None, // G_PHI = 64 |
| 16962 | CEFBS_None, // G_FRAME_INDEX = 65 |
| 16963 | CEFBS_None, // G_GLOBAL_VALUE = 66 |
| 16964 | CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67 |
| 16965 | CEFBS_None, // G_CONSTANT_POOL = 68 |
| 16966 | CEFBS_None, // G_EXTRACT = 69 |
| 16967 | CEFBS_None, // G_UNMERGE_VALUES = 70 |
| 16968 | CEFBS_None, // G_INSERT = 71 |
| 16969 | CEFBS_None, // G_MERGE_VALUES = 72 |
| 16970 | CEFBS_None, // G_BUILD_VECTOR = 73 |
| 16971 | CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74 |
| 16972 | CEFBS_None, // G_CONCAT_VECTORS = 75 |
| 16973 | CEFBS_None, // G_PTRTOINT = 76 |
| 16974 | CEFBS_None, // G_INTTOPTR = 77 |
| 16975 | CEFBS_None, // G_BITCAST = 78 |
| 16976 | CEFBS_None, // G_FREEZE = 79 |
| 16977 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80 |
| 16978 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81 |
| 16979 | CEFBS_None, // G_INTRINSIC_TRUNC = 82 |
| 16980 | CEFBS_None, // G_INTRINSIC_ROUND = 83 |
| 16981 | CEFBS_None, // G_INTRINSIC_LRINT = 84 |
| 16982 | CEFBS_None, // G_INTRINSIC_LLRINT = 85 |
| 16983 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86 |
| 16984 | CEFBS_None, // G_READCYCLECOUNTER = 87 |
| 16985 | CEFBS_None, // G_READSTEADYCOUNTER = 88 |
| 16986 | CEFBS_None, // G_LOAD = 89 |
| 16987 | CEFBS_None, // G_SEXTLOAD = 90 |
| 16988 | CEFBS_None, // G_ZEXTLOAD = 91 |
| 16989 | CEFBS_None, // G_INDEXED_LOAD = 92 |
| 16990 | CEFBS_None, // G_INDEXED_SEXTLOAD = 93 |
| 16991 | CEFBS_None, // G_INDEXED_ZEXTLOAD = 94 |
| 16992 | CEFBS_None, // G_STORE = 95 |
| 16993 | CEFBS_None, // G_INDEXED_STORE = 96 |
| 16994 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97 |
| 16995 | CEFBS_None, // G_ATOMIC_CMPXCHG = 98 |
| 16996 | CEFBS_None, // G_ATOMICRMW_XCHG = 99 |
| 16997 | CEFBS_None, // G_ATOMICRMW_ADD = 100 |
| 16998 | CEFBS_None, // G_ATOMICRMW_SUB = 101 |
| 16999 | CEFBS_None, // G_ATOMICRMW_AND = 102 |
| 17000 | CEFBS_None, // G_ATOMICRMW_NAND = 103 |
| 17001 | CEFBS_None, // G_ATOMICRMW_OR = 104 |
| 17002 | CEFBS_None, // G_ATOMICRMW_XOR = 105 |
| 17003 | CEFBS_None, // G_ATOMICRMW_MAX = 106 |
| 17004 | CEFBS_None, // G_ATOMICRMW_MIN = 107 |
| 17005 | CEFBS_None, // G_ATOMICRMW_UMAX = 108 |
| 17006 | CEFBS_None, // G_ATOMICRMW_UMIN = 109 |
| 17007 | CEFBS_None, // G_ATOMICRMW_FADD = 110 |
| 17008 | CEFBS_None, // G_ATOMICRMW_FSUB = 111 |
| 17009 | CEFBS_None, // G_ATOMICRMW_FMAX = 112 |
| 17010 | CEFBS_None, // G_ATOMICRMW_FMIN = 113 |
| 17011 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114 |
| 17012 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115 |
| 17013 | CEFBS_None, // G_FENCE = 116 |
| 17014 | CEFBS_None, // G_PREFETCH = 117 |
| 17015 | CEFBS_None, // G_BRCOND = 118 |
| 17016 | CEFBS_None, // G_BRINDIRECT = 119 |
| 17017 | CEFBS_None, // G_INVOKE_REGION_START = 120 |
| 17018 | CEFBS_None, // G_INTRINSIC = 121 |
| 17019 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122 |
| 17020 | CEFBS_None, // G_INTRINSIC_CONVERGENT = 123 |
| 17021 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124 |
| 17022 | CEFBS_None, // G_ANYEXT = 125 |
| 17023 | CEFBS_None, // G_TRUNC = 126 |
| 17024 | CEFBS_None, // G_CONSTANT = 127 |
| 17025 | CEFBS_None, // G_FCONSTANT = 128 |
| 17026 | CEFBS_None, // G_VASTART = 129 |
| 17027 | CEFBS_None, // G_VAARG = 130 |
| 17028 | CEFBS_None, // G_SEXT = 131 |
| 17029 | CEFBS_None, // G_SEXT_INREG = 132 |
| 17030 | CEFBS_None, // G_ZEXT = 133 |
| 17031 | CEFBS_None, // G_SHL = 134 |
| 17032 | CEFBS_None, // G_LSHR = 135 |
| 17033 | CEFBS_None, // G_ASHR = 136 |
| 17034 | CEFBS_None, // G_FSHL = 137 |
| 17035 | CEFBS_None, // G_FSHR = 138 |
| 17036 | CEFBS_None, // G_ROTR = 139 |
| 17037 | CEFBS_None, // G_ROTL = 140 |
| 17038 | CEFBS_None, // G_ICMP = 141 |
| 17039 | CEFBS_None, // G_FCMP = 142 |
| 17040 | CEFBS_None, // G_SCMP = 143 |
| 17041 | CEFBS_None, // G_UCMP = 144 |
| 17042 | CEFBS_None, // G_SELECT = 145 |
| 17043 | CEFBS_None, // G_UADDO = 146 |
| 17044 | CEFBS_None, // G_UADDE = 147 |
| 17045 | CEFBS_None, // G_USUBO = 148 |
| 17046 | CEFBS_None, // G_USUBE = 149 |
| 17047 | CEFBS_None, // G_SADDO = 150 |
| 17048 | CEFBS_None, // G_SADDE = 151 |
| 17049 | CEFBS_None, // G_SSUBO = 152 |
| 17050 | CEFBS_None, // G_SSUBE = 153 |
| 17051 | CEFBS_None, // G_UMULO = 154 |
| 17052 | CEFBS_None, // G_SMULO = 155 |
| 17053 | CEFBS_None, // G_UMULH = 156 |
| 17054 | CEFBS_None, // G_SMULH = 157 |
| 17055 | CEFBS_None, // G_UADDSAT = 158 |
| 17056 | CEFBS_None, // G_SADDSAT = 159 |
| 17057 | CEFBS_None, // G_USUBSAT = 160 |
| 17058 | CEFBS_None, // G_SSUBSAT = 161 |
| 17059 | CEFBS_None, // G_USHLSAT = 162 |
| 17060 | CEFBS_None, // G_SSHLSAT = 163 |
| 17061 | CEFBS_None, // G_SMULFIX = 164 |
| 17062 | CEFBS_None, // G_UMULFIX = 165 |
| 17063 | CEFBS_None, // G_SMULFIXSAT = 166 |
| 17064 | CEFBS_None, // G_UMULFIXSAT = 167 |
| 17065 | CEFBS_None, // G_SDIVFIX = 168 |
| 17066 | CEFBS_None, // G_UDIVFIX = 169 |
| 17067 | CEFBS_None, // G_SDIVFIXSAT = 170 |
| 17068 | CEFBS_None, // G_UDIVFIXSAT = 171 |
| 17069 | CEFBS_None, // G_FADD = 172 |
| 17070 | CEFBS_None, // G_FSUB = 173 |
| 17071 | CEFBS_None, // G_FMUL = 174 |
| 17072 | CEFBS_None, // G_FMA = 175 |
| 17073 | CEFBS_None, // G_FMAD = 176 |
| 17074 | CEFBS_None, // G_FDIV = 177 |
| 17075 | CEFBS_None, // G_FREM = 178 |
| 17076 | CEFBS_None, // G_FPOW = 179 |
| 17077 | CEFBS_None, // G_FPOWI = 180 |
| 17078 | CEFBS_None, // G_FEXP = 181 |
| 17079 | CEFBS_None, // G_FEXP2 = 182 |
| 17080 | CEFBS_None, // G_FEXP10 = 183 |
| 17081 | CEFBS_None, // G_FLOG = 184 |
| 17082 | CEFBS_None, // G_FLOG2 = 185 |
| 17083 | CEFBS_None, // G_FLOG10 = 186 |
| 17084 | CEFBS_None, // G_FLDEXP = 187 |
| 17085 | CEFBS_None, // G_FFREXP = 188 |
| 17086 | CEFBS_None, // G_FNEG = 189 |
| 17087 | CEFBS_None, // G_FPEXT = 190 |
| 17088 | CEFBS_None, // G_FPTRUNC = 191 |
| 17089 | CEFBS_None, // G_FPTOSI = 192 |
| 17090 | CEFBS_None, // G_FPTOUI = 193 |
| 17091 | CEFBS_None, // G_SITOFP = 194 |
| 17092 | CEFBS_None, // G_UITOFP = 195 |
| 17093 | CEFBS_None, // G_FABS = 196 |
| 17094 | CEFBS_None, // G_FCOPYSIGN = 197 |
| 17095 | CEFBS_None, // G_IS_FPCLASS = 198 |
| 17096 | CEFBS_None, // G_FCANONICALIZE = 199 |
| 17097 | CEFBS_None, // G_FMINNUM = 200 |
| 17098 | CEFBS_None, // G_FMAXNUM = 201 |
| 17099 | CEFBS_None, // G_FMINNUM_IEEE = 202 |
| 17100 | CEFBS_None, // G_FMAXNUM_IEEE = 203 |
| 17101 | CEFBS_None, // G_FMINIMUM = 204 |
| 17102 | CEFBS_None, // G_FMAXIMUM = 205 |
| 17103 | CEFBS_None, // G_GET_FPENV = 206 |
| 17104 | CEFBS_None, // G_SET_FPENV = 207 |
| 17105 | CEFBS_None, // G_RESET_FPENV = 208 |
| 17106 | CEFBS_None, // G_GET_FPMODE = 209 |
| 17107 | CEFBS_None, // G_SET_FPMODE = 210 |
| 17108 | CEFBS_None, // G_RESET_FPMODE = 211 |
| 17109 | CEFBS_None, // G_PTR_ADD = 212 |
| 17110 | CEFBS_None, // G_PTRMASK = 213 |
| 17111 | CEFBS_None, // G_SMIN = 214 |
| 17112 | CEFBS_None, // G_SMAX = 215 |
| 17113 | CEFBS_None, // G_UMIN = 216 |
| 17114 | CEFBS_None, // G_UMAX = 217 |
| 17115 | CEFBS_None, // G_ABS = 218 |
| 17116 | CEFBS_None, // G_LROUND = 219 |
| 17117 | CEFBS_None, // G_LLROUND = 220 |
| 17118 | CEFBS_None, // G_BR = 221 |
| 17119 | CEFBS_None, // G_BRJT = 222 |
| 17120 | CEFBS_None, // G_VSCALE = 223 |
| 17121 | CEFBS_None, // G_INSERT_SUBVECTOR = 224 |
| 17122 | CEFBS_None, // G_EXTRACT_SUBVECTOR = 225 |
| 17123 | CEFBS_None, // G_INSERT_VECTOR_ELT = 226 |
| 17124 | CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227 |
| 17125 | CEFBS_None, // G_SHUFFLE_VECTOR = 228 |
| 17126 | CEFBS_None, // G_SPLAT_VECTOR = 229 |
| 17127 | CEFBS_None, // G_VECTOR_COMPRESS = 230 |
| 17128 | CEFBS_None, // G_CTTZ = 231 |
| 17129 | CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232 |
| 17130 | CEFBS_None, // G_CTLZ = 233 |
| 17131 | CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234 |
| 17132 | CEFBS_None, // G_CTPOP = 235 |
| 17133 | CEFBS_None, // G_BSWAP = 236 |
| 17134 | CEFBS_None, // G_BITREVERSE = 237 |
| 17135 | CEFBS_None, // G_FCEIL = 238 |
| 17136 | CEFBS_None, // G_FCOS = 239 |
| 17137 | CEFBS_None, // G_FSIN = 240 |
| 17138 | CEFBS_None, // G_FTAN = 241 |
| 17139 | CEFBS_None, // G_FACOS = 242 |
| 17140 | CEFBS_None, // G_FASIN = 243 |
| 17141 | CEFBS_None, // G_FATAN = 244 |
| 17142 | CEFBS_None, // G_FCOSH = 245 |
| 17143 | CEFBS_None, // G_FSINH = 246 |
| 17144 | CEFBS_None, // G_FTANH = 247 |
| 17145 | CEFBS_None, // G_FSQRT = 248 |
| 17146 | CEFBS_None, // G_FFLOOR = 249 |
| 17147 | CEFBS_None, // G_FRINT = 250 |
| 17148 | CEFBS_None, // G_FNEARBYINT = 251 |
| 17149 | CEFBS_None, // G_ADDRSPACE_CAST = 252 |
| 17150 | CEFBS_None, // G_BLOCK_ADDR = 253 |
| 17151 | CEFBS_None, // G_JUMP_TABLE = 254 |
| 17152 | CEFBS_None, // G_DYN_STACKALLOC = 255 |
| 17153 | CEFBS_None, // G_STACKSAVE = 256 |
| 17154 | CEFBS_None, // G_STACKRESTORE = 257 |
| 17155 | CEFBS_None, // G_STRICT_FADD = 258 |
| 17156 | CEFBS_None, // G_STRICT_FSUB = 259 |
| 17157 | CEFBS_None, // G_STRICT_FMUL = 260 |
| 17158 | CEFBS_None, // G_STRICT_FDIV = 261 |
| 17159 | CEFBS_None, // G_STRICT_FREM = 262 |
| 17160 | CEFBS_None, // G_STRICT_FMA = 263 |
| 17161 | CEFBS_None, // G_STRICT_FSQRT = 264 |
| 17162 | CEFBS_None, // G_STRICT_FLDEXP = 265 |
| 17163 | CEFBS_None, // G_READ_REGISTER = 266 |
| 17164 | CEFBS_None, // G_WRITE_REGISTER = 267 |
| 17165 | CEFBS_None, // G_MEMCPY = 268 |
| 17166 | CEFBS_None, // G_MEMCPY_INLINE = 269 |
| 17167 | CEFBS_None, // G_MEMMOVE = 270 |
| 17168 | CEFBS_None, // G_MEMSET = 271 |
| 17169 | CEFBS_None, // G_BZERO = 272 |
| 17170 | CEFBS_None, // G_TRAP = 273 |
| 17171 | CEFBS_None, // G_DEBUGTRAP = 274 |
| 17172 | CEFBS_None, // G_UBSANTRAP = 275 |
| 17173 | CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276 |
| 17174 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277 |
| 17175 | CEFBS_None, // G_VECREDUCE_FADD = 278 |
| 17176 | CEFBS_None, // G_VECREDUCE_FMUL = 279 |
| 17177 | CEFBS_None, // G_VECREDUCE_FMAX = 280 |
| 17178 | CEFBS_None, // G_VECREDUCE_FMIN = 281 |
| 17179 | CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282 |
| 17180 | CEFBS_None, // G_VECREDUCE_FMINIMUM = 283 |
| 17181 | CEFBS_None, // G_VECREDUCE_ADD = 284 |
| 17182 | CEFBS_None, // G_VECREDUCE_MUL = 285 |
| 17183 | CEFBS_None, // G_VECREDUCE_AND = 286 |
| 17184 | CEFBS_None, // G_VECREDUCE_OR = 287 |
| 17185 | CEFBS_None, // G_VECREDUCE_XOR = 288 |
| 17186 | CEFBS_None, // G_VECREDUCE_SMAX = 289 |
| 17187 | CEFBS_None, // G_VECREDUCE_SMIN = 290 |
| 17188 | CEFBS_None, // G_VECREDUCE_UMAX = 291 |
| 17189 | CEFBS_None, // G_VECREDUCE_UMIN = 292 |
| 17190 | CEFBS_None, // G_SBFX = 293 |
| 17191 | CEFBS_None, // G_UBFX = 294 |
| 17192 | CEFBS_None, // ADJCALLSTACKDOWN = 295 |
| 17193 | CEFBS_None, // ADJCALLSTACKUP = 296 |
| 17194 | CEFBS_IsLA64, // PseudoAddTPRel_D = 297 |
| 17195 | CEFBS_IsLA32, // PseudoAddTPRel_W = 298 |
| 17196 | CEFBS_None, // PseudoAtomicLoadAdd32 = 299 |
| 17197 | CEFBS_None, // PseudoAtomicLoadAnd32 = 300 |
| 17198 | CEFBS_None, // PseudoAtomicLoadNand32 = 301 |
| 17199 | CEFBS_None, // PseudoAtomicLoadNand64 = 302 |
| 17200 | CEFBS_None, // PseudoAtomicLoadOr32 = 303 |
| 17201 | CEFBS_None, // PseudoAtomicLoadSub32 = 304 |
| 17202 | CEFBS_None, // PseudoAtomicLoadXor32 = 305 |
| 17203 | CEFBS_IsLA64, // PseudoAtomicStoreD = 306 |
| 17204 | CEFBS_None, // PseudoAtomicStoreW = 307 |
| 17205 | CEFBS_None, // PseudoAtomicSwap32 = 308 |
| 17206 | CEFBS_None, // PseudoBR = 309 |
| 17207 | CEFBS_None, // PseudoBRIND = 310 |
| 17208 | CEFBS_None, // PseudoB_TAIL = 311 |
| 17209 | CEFBS_None, // PseudoCALL = 312 |
| 17210 | CEFBS_IsLA64, // PseudoCALL36 = 313 |
| 17211 | CEFBS_None, // PseudoCALLIndirect = 314 |
| 17212 | CEFBS_None, // PseudoCALL_LARGE = 315 |
| 17213 | CEFBS_None, // PseudoCALL_MEDIUM = 316 |
| 17214 | CEFBS_None, // PseudoCmpXchg32 = 317 |
| 17215 | CEFBS_None, // PseudoCmpXchg64 = 318 |
| 17216 | CEFBS_None, // PseudoCopyCFR = 319 |
| 17217 | CEFBS_None, // PseudoDESC_CALL = 320 |
| 17218 | CEFBS_None, // PseudoJIRL_CALL = 321 |
| 17219 | CEFBS_None, // PseudoJIRL_TAIL = 322 |
| 17220 | CEFBS_None, // PseudoLA_ABS = 323 |
| 17221 | CEFBS_None, // PseudoLA_ABS_LARGE = 324 |
| 17222 | CEFBS_None, // PseudoLA_GOT = 325 |
| 17223 | CEFBS_IsLA64, // PseudoLA_GOT_LARGE = 326 |
| 17224 | CEFBS_None, // PseudoLA_PCREL = 327 |
| 17225 | CEFBS_IsLA64, // PseudoLA_PCREL_LARGE = 328 |
| 17226 | CEFBS_IsLA32_HasLaGlobalWithAbs, // PseudoLA_TLS_DESC_ABS = 329 |
| 17227 | CEFBS_IsLA64_HasLaGlobalWithAbs, // PseudoLA_TLS_DESC_ABS_LARGE = 330 |
| 17228 | CEFBS_None, // PseudoLA_TLS_DESC_PC = 331 |
| 17229 | CEFBS_IsLA64, // PseudoLA_TLS_DESC_PC_LARGE = 332 |
| 17230 | CEFBS_None, // PseudoLA_TLS_GD = 333 |
| 17231 | CEFBS_IsLA64, // PseudoLA_TLS_GD_LARGE = 334 |
| 17232 | CEFBS_None, // PseudoLA_TLS_IE = 335 |
| 17233 | CEFBS_IsLA64, // PseudoLA_TLS_IE_LARGE = 336 |
| 17234 | CEFBS_None, // PseudoLA_TLS_LD = 337 |
| 17235 | CEFBS_IsLA64, // PseudoLA_TLS_LD_LARGE = 338 |
| 17236 | CEFBS_None, // PseudoLA_TLS_LE = 339 |
| 17237 | CEFBS_None, // PseudoLD_CFR = 340 |
| 17238 | CEFBS_IsLA64, // PseudoLI_D = 341 |
| 17239 | CEFBS_None, // PseudoLI_W = 342 |
| 17240 | CEFBS_None, // PseudoMaskedAtomicLoadAdd32 = 343 |
| 17241 | CEFBS_None, // PseudoMaskedAtomicLoadMax32 = 344 |
| 17242 | CEFBS_None, // PseudoMaskedAtomicLoadMin32 = 345 |
| 17243 | CEFBS_None, // PseudoMaskedAtomicLoadNand32 = 346 |
| 17244 | CEFBS_None, // PseudoMaskedAtomicLoadSub32 = 347 |
| 17245 | CEFBS_None, // PseudoMaskedAtomicLoadUMax32 = 348 |
| 17246 | CEFBS_None, // PseudoMaskedAtomicLoadUMin32 = 349 |
| 17247 | CEFBS_None, // PseudoMaskedAtomicSwap32 = 350 |
| 17248 | CEFBS_None, // PseudoMaskedCmpXchg32 = 351 |
| 17249 | CEFBS_None, // PseudoRET = 352 |
| 17250 | CEFBS_None, // PseudoST_CFR = 353 |
| 17251 | CEFBS_None, // PseudoTAIL = 354 |
| 17252 | CEFBS_IsLA64, // PseudoTAIL36 = 355 |
| 17253 | CEFBS_None, // PseudoTAILIndirect = 356 |
| 17254 | CEFBS_None, // PseudoTAIL_LARGE = 357 |
| 17255 | CEFBS_None, // PseudoTAIL_MEDIUM = 358 |
| 17256 | CEFBS_None, // PseudoUNIMP = 359 |
| 17257 | CEFBS_None, // PseudoVBNZ = 360 |
| 17258 | CEFBS_None, // PseudoVBNZ_B = 361 |
| 17259 | CEFBS_None, // PseudoVBNZ_D = 362 |
| 17260 | CEFBS_None, // PseudoVBNZ_H = 363 |
| 17261 | CEFBS_None, // PseudoVBNZ_W = 364 |
| 17262 | CEFBS_None, // PseudoVBZ = 365 |
| 17263 | CEFBS_None, // PseudoVBZ_B = 366 |
| 17264 | CEFBS_None, // PseudoVBZ_D = 367 |
| 17265 | CEFBS_None, // PseudoVBZ_H = 368 |
| 17266 | CEFBS_None, // PseudoVBZ_W = 369 |
| 17267 | CEFBS_None, // PseudoVREPLI_B = 370 |
| 17268 | CEFBS_None, // PseudoVREPLI_D = 371 |
| 17269 | CEFBS_None, // PseudoVREPLI_H = 372 |
| 17270 | CEFBS_None, // PseudoVREPLI_W = 373 |
| 17271 | CEFBS_None, // PseudoXVBNZ = 374 |
| 17272 | CEFBS_None, // PseudoXVBNZ_B = 375 |
| 17273 | CEFBS_None, // PseudoXVBNZ_D = 376 |
| 17274 | CEFBS_None, // PseudoXVBNZ_H = 377 |
| 17275 | CEFBS_None, // PseudoXVBNZ_W = 378 |
| 17276 | CEFBS_None, // PseudoXVBZ = 379 |
| 17277 | CEFBS_None, // PseudoXVBZ_B = 380 |
| 17278 | CEFBS_None, // PseudoXVBZ_D = 381 |
| 17279 | CEFBS_None, // PseudoXVBZ_H = 382 |
| 17280 | CEFBS_None, // PseudoXVBZ_W = 383 |
| 17281 | CEFBS_None, // PseudoXVINSGR2VR_B = 384 |
| 17282 | CEFBS_None, // PseudoXVINSGR2VR_H = 385 |
| 17283 | CEFBS_None, // PseudoXVREPLI_B = 386 |
| 17284 | CEFBS_None, // PseudoXVREPLI_D = 387 |
| 17285 | CEFBS_None, // PseudoXVREPLI_H = 388 |
| 17286 | CEFBS_None, // PseudoXVREPLI_W = 389 |
| 17287 | CEFBS_None, // RDFCSR = 390 |
| 17288 | CEFBS_None, // WRFCSR = 391 |
| 17289 | CEFBS_None, // ADC_B = 392 |
| 17290 | CEFBS_IsLA64, // ADC_D = 393 |
| 17291 | CEFBS_None, // ADC_H = 394 |
| 17292 | CEFBS_None, // ADC_W = 395 |
| 17293 | CEFBS_IsLA64, // ADDI_D = 396 |
| 17294 | CEFBS_None, // ADDI_W = 397 |
| 17295 | CEFBS_IsLA64, // ADDU12I_D = 398 |
| 17296 | CEFBS_None, // ADDU12I_W = 399 |
| 17297 | CEFBS_IsLA64, // ADDU16I_D = 400 |
| 17298 | CEFBS_IsLA64, // ADD_D = 401 |
| 17299 | CEFBS_None, // ADD_W = 402 |
| 17300 | CEFBS_IsLA64, // ALSL_D = 403 |
| 17301 | CEFBS_None, // ALSL_W = 404 |
| 17302 | CEFBS_IsLA64, // ALSL_WU = 405 |
| 17303 | CEFBS_IsLA64, // AMADD_B = 406 |
| 17304 | CEFBS_IsLA64, // AMADD_D = 407 |
| 17305 | CEFBS_IsLA64, // AMADD_H = 408 |
| 17306 | CEFBS_IsLA64, // AMADD_W = 409 |
| 17307 | CEFBS_IsLA64, // AMADD__DB_B = 410 |
| 17308 | CEFBS_IsLA64, // AMADD__DB_D = 411 |
| 17309 | CEFBS_IsLA64, // AMADD__DB_H = 412 |
| 17310 | CEFBS_IsLA64, // AMADD__DB_W = 413 |
| 17311 | CEFBS_IsLA64, // AMAND_D = 414 |
| 17312 | CEFBS_IsLA64, // AMAND_W = 415 |
| 17313 | CEFBS_IsLA64, // AMAND__DB_D = 416 |
| 17314 | CEFBS_IsLA64, // AMAND__DB_W = 417 |
| 17315 | CEFBS_IsLA64, // AMCAS_B = 418 |
| 17316 | CEFBS_IsLA64, // AMCAS_D = 419 |
| 17317 | CEFBS_IsLA64, // AMCAS_H = 420 |
| 17318 | CEFBS_IsLA64, // AMCAS_W = 421 |
| 17319 | CEFBS_IsLA64, // AMCAS__DB_B = 422 |
| 17320 | CEFBS_IsLA64, // AMCAS__DB_D = 423 |
| 17321 | CEFBS_IsLA64, // AMCAS__DB_H = 424 |
| 17322 | CEFBS_IsLA64, // AMCAS__DB_W = 425 |
| 17323 | CEFBS_IsLA64, // AMMAX_D = 426 |
| 17324 | CEFBS_IsLA64, // AMMAX_DU = 427 |
| 17325 | CEFBS_IsLA64, // AMMAX_W = 428 |
| 17326 | CEFBS_IsLA64, // AMMAX_WU = 429 |
| 17327 | CEFBS_IsLA64, // AMMAX__DB_D = 430 |
| 17328 | CEFBS_IsLA64, // AMMAX__DB_DU = 431 |
| 17329 | CEFBS_IsLA64, // AMMAX__DB_W = 432 |
| 17330 | CEFBS_IsLA64, // AMMAX__DB_WU = 433 |
| 17331 | CEFBS_IsLA64, // AMMIN_D = 434 |
| 17332 | CEFBS_IsLA64, // AMMIN_DU = 435 |
| 17333 | CEFBS_IsLA64, // AMMIN_W = 436 |
| 17334 | CEFBS_IsLA64, // AMMIN_WU = 437 |
| 17335 | CEFBS_IsLA64, // AMMIN__DB_D = 438 |
| 17336 | CEFBS_IsLA64, // AMMIN__DB_DU = 439 |
| 17337 | CEFBS_IsLA64, // AMMIN__DB_W = 440 |
| 17338 | CEFBS_IsLA64, // AMMIN__DB_WU = 441 |
| 17339 | CEFBS_IsLA64, // AMOR_D = 442 |
| 17340 | CEFBS_IsLA64, // AMOR_W = 443 |
| 17341 | CEFBS_IsLA64, // AMOR__DB_D = 444 |
| 17342 | CEFBS_IsLA64, // AMOR__DB_W = 445 |
| 17343 | CEFBS_IsLA64, // AMSWAP_B = 446 |
| 17344 | CEFBS_IsLA64, // AMSWAP_D = 447 |
| 17345 | CEFBS_IsLA64, // AMSWAP_H = 448 |
| 17346 | CEFBS_IsLA64, // AMSWAP_W = 449 |
| 17347 | CEFBS_IsLA64, // AMSWAP__DB_B = 450 |
| 17348 | CEFBS_IsLA64, // AMSWAP__DB_D = 451 |
| 17349 | CEFBS_IsLA64, // AMSWAP__DB_H = 452 |
| 17350 | CEFBS_IsLA64, // AMSWAP__DB_W = 453 |
| 17351 | CEFBS_IsLA64, // AMXOR_D = 454 |
| 17352 | CEFBS_IsLA64, // AMXOR_W = 455 |
| 17353 | CEFBS_IsLA64, // AMXOR__DB_D = 456 |
| 17354 | CEFBS_IsLA64, // AMXOR__DB_W = 457 |
| 17355 | CEFBS_None, // AND = 458 |
| 17356 | CEFBS_None, // ANDI = 459 |
| 17357 | CEFBS_None, // ANDN = 460 |
| 17358 | CEFBS_None, // ARMADC_W = 461 |
| 17359 | CEFBS_None, // ARMADD_W = 462 |
| 17360 | CEFBS_None, // ARMAND_W = 463 |
| 17361 | CEFBS_None, // ARMMFFLAG = 464 |
| 17362 | CEFBS_None, // ARMMOVE = 465 |
| 17363 | CEFBS_IsLA64, // ARMMOV_D = 466 |
| 17364 | CEFBS_None, // ARMMOV_W = 467 |
| 17365 | CEFBS_None, // ARMMTFLAG = 468 |
| 17366 | CEFBS_None, // ARMNOT_W = 469 |
| 17367 | CEFBS_None, // ARMOR_W = 470 |
| 17368 | CEFBS_None, // ARMROTRI_W = 471 |
| 17369 | CEFBS_None, // ARMROTR_W = 472 |
| 17370 | CEFBS_None, // ARMRRX_W = 473 |
| 17371 | CEFBS_None, // ARMSBC_W = 474 |
| 17372 | CEFBS_None, // ARMSLLI_W = 475 |
| 17373 | CEFBS_None, // ARMSLL_W = 476 |
| 17374 | CEFBS_None, // ARMSRAI_W = 477 |
| 17375 | CEFBS_None, // ARMSRA_W = 478 |
| 17376 | CEFBS_None, // ARMSRLI_W = 479 |
| 17377 | CEFBS_None, // ARMSRL_W = 480 |
| 17378 | CEFBS_None, // ARMSUB_W = 481 |
| 17379 | CEFBS_None, // ARMXOR_W = 482 |
| 17380 | CEFBS_IsLA64, // ASRTGT_D = 483 |
| 17381 | CEFBS_IsLA64, // ASRTLE_D = 484 |
| 17382 | CEFBS_None, // B = 485 |
| 17383 | CEFBS_None, // BCEQZ = 486 |
| 17384 | CEFBS_None, // BCNEZ = 487 |
| 17385 | CEFBS_None, // BEQ = 488 |
| 17386 | CEFBS_None, // BEQZ = 489 |
| 17387 | CEFBS_None, // BGE = 490 |
| 17388 | CEFBS_None, // BGEU = 491 |
| 17389 | CEFBS_None, // BITREV_4B = 492 |
| 17390 | CEFBS_IsLA64, // BITREV_8B = 493 |
| 17391 | CEFBS_IsLA64, // BITREV_D = 494 |
| 17392 | CEFBS_None, // BITREV_W = 495 |
| 17393 | CEFBS_None, // BL = 496 |
| 17394 | CEFBS_None, // BLT = 497 |
| 17395 | CEFBS_None, // BLTU = 498 |
| 17396 | CEFBS_None, // BNE = 499 |
| 17397 | CEFBS_None, // BNEZ = 500 |
| 17398 | CEFBS_None, // BREAK = 501 |
| 17399 | CEFBS_IsLA64, // BSTRINS_D = 502 |
| 17400 | CEFBS_None, // BSTRINS_W = 503 |
| 17401 | CEFBS_IsLA64, // BSTRPICK_D = 504 |
| 17402 | CEFBS_None, // BSTRPICK_W = 505 |
| 17403 | CEFBS_IsLA64, // BYTEPICK_D = 506 |
| 17404 | CEFBS_None, // BYTEPICK_W = 507 |
| 17405 | CEFBS_None, // CACOP = 508 |
| 17406 | CEFBS_IsLA64, // CLO_D = 509 |
| 17407 | CEFBS_None, // CLO_W = 510 |
| 17408 | CEFBS_IsLA64, // CLZ_D = 511 |
| 17409 | CEFBS_None, // CLZ_W = 512 |
| 17410 | CEFBS_None, // CPUCFG = 513 |
| 17411 | CEFBS_IsLA64, // CRCC_W_B_W = 514 |
| 17412 | CEFBS_IsLA64, // CRCC_W_D_W = 515 |
| 17413 | CEFBS_IsLA64, // CRCC_W_H_W = 516 |
| 17414 | CEFBS_IsLA64, // CRCC_W_W_W = 517 |
| 17415 | CEFBS_IsLA64, // CRC_W_B_W = 518 |
| 17416 | CEFBS_IsLA64, // CRC_W_D_W = 519 |
| 17417 | CEFBS_IsLA64, // CRC_W_H_W = 520 |
| 17418 | CEFBS_IsLA64, // CRC_W_W_W = 521 |
| 17419 | CEFBS_None, // CSRRD = 522 |
| 17420 | CEFBS_None, // CSRWR = 523 |
| 17421 | CEFBS_None, // CSRXCHG = 524 |
| 17422 | CEFBS_IsLA64, // CTO_D = 525 |
| 17423 | CEFBS_None, // CTO_W = 526 |
| 17424 | CEFBS_IsLA64, // CTZ_D = 527 |
| 17425 | CEFBS_None, // CTZ_W = 528 |
| 17426 | CEFBS_None, // DBAR = 529 |
| 17427 | CEFBS_None, // DBCL = 530 |
| 17428 | CEFBS_IsLA64, // DIV_D = 531 |
| 17429 | CEFBS_IsLA64, // DIV_DU = 532 |
| 17430 | CEFBS_None, // DIV_W = 533 |
| 17431 | CEFBS_None, // DIV_WU = 534 |
| 17432 | CEFBS_None, // ERTN = 535 |
| 17433 | CEFBS_None, // EXT_W_B = 536 |
| 17434 | CEFBS_None, // EXT_W_H = 537 |
| 17435 | CEFBS_None, // FABS_D = 538 |
| 17436 | CEFBS_None, // FABS_S = 539 |
| 17437 | CEFBS_None, // FADD_D = 540 |
| 17438 | CEFBS_None, // FADD_S = 541 |
| 17439 | CEFBS_None, // FCLASS_D = 542 |
| 17440 | CEFBS_None, // FCLASS_S = 543 |
| 17441 | CEFBS_None, // FCMP_CAF_D = 544 |
| 17442 | CEFBS_None, // FCMP_CAF_S = 545 |
| 17443 | CEFBS_None, // FCMP_CEQ_D = 546 |
| 17444 | CEFBS_None, // FCMP_CEQ_S = 547 |
| 17445 | CEFBS_None, // FCMP_CLE_D = 548 |
| 17446 | CEFBS_None, // FCMP_CLE_S = 549 |
| 17447 | CEFBS_None, // FCMP_CLT_D = 550 |
| 17448 | CEFBS_None, // FCMP_CLT_S = 551 |
| 17449 | CEFBS_None, // FCMP_CNE_D = 552 |
| 17450 | CEFBS_None, // FCMP_CNE_S = 553 |
| 17451 | CEFBS_None, // FCMP_COR_D = 554 |
| 17452 | CEFBS_None, // FCMP_COR_S = 555 |
| 17453 | CEFBS_None, // FCMP_CUEQ_D = 556 |
| 17454 | CEFBS_None, // FCMP_CUEQ_S = 557 |
| 17455 | CEFBS_None, // FCMP_CULE_D = 558 |
| 17456 | CEFBS_None, // FCMP_CULE_S = 559 |
| 17457 | CEFBS_None, // FCMP_CULT_D = 560 |
| 17458 | CEFBS_None, // FCMP_CULT_S = 561 |
| 17459 | CEFBS_None, // FCMP_CUNE_D = 562 |
| 17460 | CEFBS_None, // FCMP_CUNE_S = 563 |
| 17461 | CEFBS_None, // FCMP_CUN_D = 564 |
| 17462 | CEFBS_None, // FCMP_CUN_S = 565 |
| 17463 | CEFBS_None, // FCMP_SAF_D = 566 |
| 17464 | CEFBS_None, // FCMP_SAF_S = 567 |
| 17465 | CEFBS_None, // FCMP_SEQ_D = 568 |
| 17466 | CEFBS_None, // FCMP_SEQ_S = 569 |
| 17467 | CEFBS_None, // FCMP_SLE_D = 570 |
| 17468 | CEFBS_None, // FCMP_SLE_S = 571 |
| 17469 | CEFBS_None, // FCMP_SLT_D = 572 |
| 17470 | CEFBS_None, // FCMP_SLT_S = 573 |
| 17471 | CEFBS_None, // FCMP_SNE_D = 574 |
| 17472 | CEFBS_None, // FCMP_SNE_S = 575 |
| 17473 | CEFBS_None, // FCMP_SOR_D = 576 |
| 17474 | CEFBS_None, // FCMP_SOR_S = 577 |
| 17475 | CEFBS_None, // FCMP_SUEQ_D = 578 |
| 17476 | CEFBS_None, // FCMP_SUEQ_S = 579 |
| 17477 | CEFBS_None, // FCMP_SULE_D = 580 |
| 17478 | CEFBS_None, // FCMP_SULE_S = 581 |
| 17479 | CEFBS_None, // FCMP_SULT_D = 582 |
| 17480 | CEFBS_None, // FCMP_SULT_S = 583 |
| 17481 | CEFBS_None, // FCMP_SUNE_D = 584 |
| 17482 | CEFBS_None, // FCMP_SUNE_S = 585 |
| 17483 | CEFBS_None, // FCMP_SUN_D = 586 |
| 17484 | CEFBS_None, // FCMP_SUN_S = 587 |
| 17485 | CEFBS_None, // FCOPYSIGN_D = 588 |
| 17486 | CEFBS_None, // FCOPYSIGN_S = 589 |
| 17487 | CEFBS_None, // FCVT_D_LD = 590 |
| 17488 | CEFBS_None, // FCVT_D_S = 591 |
| 17489 | CEFBS_None, // FCVT_LD_D = 592 |
| 17490 | CEFBS_None, // FCVT_S_D = 593 |
| 17491 | CEFBS_None, // FCVT_UD_D = 594 |
| 17492 | CEFBS_None, // FDIV_D = 595 |
| 17493 | CEFBS_None, // FDIV_S = 596 |
| 17494 | CEFBS_None, // FFINT_D_L = 597 |
| 17495 | CEFBS_None, // FFINT_D_W = 598 |
| 17496 | CEFBS_None, // FFINT_S_L = 599 |
| 17497 | CEFBS_None, // FFINT_S_W = 600 |
| 17498 | CEFBS_None, // FLDGT_D = 601 |
| 17499 | CEFBS_None, // FLDGT_S = 602 |
| 17500 | CEFBS_None, // FLDLE_D = 603 |
| 17501 | CEFBS_None, // FLDLE_S = 604 |
| 17502 | CEFBS_None, // FLDX_D = 605 |
| 17503 | CEFBS_None, // FLDX_S = 606 |
| 17504 | CEFBS_None, // FLD_D = 607 |
| 17505 | CEFBS_None, // FLD_S = 608 |
| 17506 | CEFBS_None, // FLOGB_D = 609 |
| 17507 | CEFBS_None, // FLOGB_S = 610 |
| 17508 | CEFBS_None, // FMADD_D = 611 |
| 17509 | CEFBS_None, // FMADD_S = 612 |
| 17510 | CEFBS_None, // FMAXA_D = 613 |
| 17511 | CEFBS_None, // FMAXA_S = 614 |
| 17512 | CEFBS_None, // FMAX_D = 615 |
| 17513 | CEFBS_None, // FMAX_S = 616 |
| 17514 | CEFBS_None, // FMINA_D = 617 |
| 17515 | CEFBS_None, // FMINA_S = 618 |
| 17516 | CEFBS_None, // FMIN_D = 619 |
| 17517 | CEFBS_None, // FMIN_S = 620 |
| 17518 | CEFBS_None, // FMOV_D = 621 |
| 17519 | CEFBS_None, // FMOV_S = 622 |
| 17520 | CEFBS_None, // FMSUB_D = 623 |
| 17521 | CEFBS_None, // FMSUB_S = 624 |
| 17522 | CEFBS_None, // FMUL_D = 625 |
| 17523 | CEFBS_None, // FMUL_S = 626 |
| 17524 | CEFBS_None, // FNEG_D = 627 |
| 17525 | CEFBS_None, // FNEG_S = 628 |
| 17526 | CEFBS_None, // FNMADD_D = 629 |
| 17527 | CEFBS_None, // FNMADD_S = 630 |
| 17528 | CEFBS_None, // FNMSUB_D = 631 |
| 17529 | CEFBS_None, // FNMSUB_S = 632 |
| 17530 | CEFBS_None, // FRECIPE_D = 633 |
| 17531 | CEFBS_None, // FRECIPE_S = 634 |
| 17532 | CEFBS_None, // FRECIP_D = 635 |
| 17533 | CEFBS_None, // FRECIP_S = 636 |
| 17534 | CEFBS_None, // FRINT_D = 637 |
| 17535 | CEFBS_None, // FRINT_S = 638 |
| 17536 | CEFBS_None, // FRSQRTE_D = 639 |
| 17537 | CEFBS_None, // FRSQRTE_S = 640 |
| 17538 | CEFBS_None, // FRSQRT_D = 641 |
| 17539 | CEFBS_None, // FRSQRT_S = 642 |
| 17540 | CEFBS_None, // FSCALEB_D = 643 |
| 17541 | CEFBS_None, // FSCALEB_S = 644 |
| 17542 | CEFBS_None, // FSEL_xD = 645 |
| 17543 | CEFBS_None, // FSEL_xS = 646 |
| 17544 | CEFBS_None, // FSQRT_D = 647 |
| 17545 | CEFBS_None, // FSQRT_S = 648 |
| 17546 | CEFBS_None, // FSTGT_D = 649 |
| 17547 | CEFBS_None, // FSTGT_S = 650 |
| 17548 | CEFBS_None, // FSTLE_D = 651 |
| 17549 | CEFBS_None, // FSTLE_S = 652 |
| 17550 | CEFBS_None, // FSTX_D = 653 |
| 17551 | CEFBS_None, // FSTX_S = 654 |
| 17552 | CEFBS_None, // FST_D = 655 |
| 17553 | CEFBS_None, // FST_S = 656 |
| 17554 | CEFBS_None, // FSUB_D = 657 |
| 17555 | CEFBS_None, // FSUB_S = 658 |
| 17556 | CEFBS_None, // FTINTRM_L_D = 659 |
| 17557 | CEFBS_None, // FTINTRM_L_S = 660 |
| 17558 | CEFBS_None, // FTINTRM_W_D = 661 |
| 17559 | CEFBS_None, // FTINTRM_W_S = 662 |
| 17560 | CEFBS_None, // FTINTRNE_L_D = 663 |
| 17561 | CEFBS_None, // FTINTRNE_L_S = 664 |
| 17562 | CEFBS_None, // FTINTRNE_W_D = 665 |
| 17563 | CEFBS_None, // FTINTRNE_W_S = 666 |
| 17564 | CEFBS_None, // FTINTRP_L_D = 667 |
| 17565 | CEFBS_None, // FTINTRP_L_S = 668 |
| 17566 | CEFBS_None, // FTINTRP_W_D = 669 |
| 17567 | CEFBS_None, // FTINTRP_W_S = 670 |
| 17568 | CEFBS_None, // FTINTRZ_L_D = 671 |
| 17569 | CEFBS_None, // FTINTRZ_L_S = 672 |
| 17570 | CEFBS_None, // FTINTRZ_W_D = 673 |
| 17571 | CEFBS_None, // FTINTRZ_W_S = 674 |
| 17572 | CEFBS_None, // FTINT_L_D = 675 |
| 17573 | CEFBS_None, // FTINT_L_S = 676 |
| 17574 | CEFBS_None, // FTINT_W_D = 677 |
| 17575 | CEFBS_None, // FTINT_W_S = 678 |
| 17576 | CEFBS_None, // GCSRRD = 679 |
| 17577 | CEFBS_None, // GCSRWR = 680 |
| 17578 | CEFBS_None, // GCSRXCHG = 681 |
| 17579 | CEFBS_None, // GTLBFLUSH = 682 |
| 17580 | CEFBS_None, // HVCL = 683 |
| 17581 | CEFBS_None, // IBAR = 684 |
| 17582 | CEFBS_None, // IDLE = 685 |
| 17583 | CEFBS_None, // INVTLB = 686 |
| 17584 | CEFBS_None, // IOCSRRD_B = 687 |
| 17585 | CEFBS_IsLA64, // IOCSRRD_D = 688 |
| 17586 | CEFBS_None, // IOCSRRD_H = 689 |
| 17587 | CEFBS_None, // IOCSRRD_W = 690 |
| 17588 | CEFBS_None, // IOCSRWR_B = 691 |
| 17589 | CEFBS_IsLA64, // IOCSRWR_D = 692 |
| 17590 | CEFBS_None, // IOCSRWR_H = 693 |
| 17591 | CEFBS_None, // IOCSRWR_W = 694 |
| 17592 | CEFBS_None, // JIRL = 695 |
| 17593 | CEFBS_None, // JISCR0 = 696 |
| 17594 | CEFBS_None, // JISCR1 = 697 |
| 17595 | CEFBS_None, // LDDIR = 698 |
| 17596 | CEFBS_IsLA64, // LDGT_B = 699 |
| 17597 | CEFBS_IsLA64, // LDGT_D = 700 |
| 17598 | CEFBS_IsLA64, // LDGT_H = 701 |
| 17599 | CEFBS_IsLA64, // LDGT_W = 702 |
| 17600 | CEFBS_IsLA64, // LDLE_B = 703 |
| 17601 | CEFBS_IsLA64, // LDLE_D = 704 |
| 17602 | CEFBS_IsLA64, // LDLE_H = 705 |
| 17603 | CEFBS_IsLA64, // LDLE_W = 706 |
| 17604 | CEFBS_IsLA64, // LDL_D = 707 |
| 17605 | CEFBS_None, // LDL_W = 708 |
| 17606 | CEFBS_None, // LDPTE = 709 |
| 17607 | CEFBS_IsLA64, // LDPTR_D = 710 |
| 17608 | CEFBS_IsLA64, // LDPTR_W = 711 |
| 17609 | CEFBS_IsLA64, // LDR_D = 712 |
| 17610 | CEFBS_None, // LDR_W = 713 |
| 17611 | CEFBS_IsLA64, // LDX_B = 714 |
| 17612 | CEFBS_IsLA64, // LDX_BU = 715 |
| 17613 | CEFBS_IsLA64, // LDX_D = 716 |
| 17614 | CEFBS_IsLA64, // LDX_H = 717 |
| 17615 | CEFBS_IsLA64, // LDX_HU = 718 |
| 17616 | CEFBS_IsLA64, // LDX_W = 719 |
| 17617 | CEFBS_IsLA64, // LDX_WU = 720 |
| 17618 | CEFBS_None, // LD_B = 721 |
| 17619 | CEFBS_None, // LD_BU = 722 |
| 17620 | CEFBS_IsLA64, // LD_D = 723 |
| 17621 | CEFBS_None, // LD_H = 724 |
| 17622 | CEFBS_None, // LD_HU = 725 |
| 17623 | CEFBS_None, // LD_W = 726 |
| 17624 | CEFBS_IsLA64, // LD_WU = 727 |
| 17625 | CEFBS_IsLA64, // LLACQ_D = 728 |
| 17626 | CEFBS_None, // LLACQ_W = 729 |
| 17627 | CEFBS_IsLA64, // LL_D = 730 |
| 17628 | CEFBS_None, // LL_W = 731 |
| 17629 | CEFBS_None, // LU12I_W = 732 |
| 17630 | CEFBS_IsLA64, // LU32I_D = 733 |
| 17631 | CEFBS_IsLA64, // LU52I_D = 734 |
| 17632 | CEFBS_None, // MASKEQZ = 735 |
| 17633 | CEFBS_None, // MASKNEZ = 736 |
| 17634 | CEFBS_IsLA64, // MOD_D = 737 |
| 17635 | CEFBS_IsLA64, // MOD_DU = 738 |
| 17636 | CEFBS_None, // MOD_W = 739 |
| 17637 | CEFBS_None, // MOD_WU = 740 |
| 17638 | CEFBS_None, // MOVCF2FR_xS = 741 |
| 17639 | CEFBS_None, // MOVCF2GR = 742 |
| 17640 | CEFBS_None, // MOVFCSR2GR = 743 |
| 17641 | CEFBS_None, // MOVFR2CF_xS = 744 |
| 17642 | CEFBS_IsLA64, // MOVFR2GR_D = 745 |
| 17643 | CEFBS_None, // MOVFR2GR_S = 746 |
| 17644 | CEFBS_None, // MOVFR2GR_S_64 = 747 |
| 17645 | CEFBS_None, // MOVFRH2GR_S = 748 |
| 17646 | CEFBS_None, // MOVGR2CF = 749 |
| 17647 | CEFBS_None, // MOVGR2FCSR = 750 |
| 17648 | CEFBS_None, // MOVGR2FRH_W = 751 |
| 17649 | CEFBS_IsLA64, // MOVGR2FR_D = 752 |
| 17650 | CEFBS_None, // MOVGR2FR_W = 753 |
| 17651 | CEFBS_IsLA32, // MOVGR2FR_W_64 = 754 |
| 17652 | CEFBS_None, // MOVGR2SCR = 755 |
| 17653 | CEFBS_None, // MOVSCR2GR = 756 |
| 17654 | CEFBS_IsLA64, // MULH_D = 757 |
| 17655 | CEFBS_IsLA64, // MULH_DU = 758 |
| 17656 | CEFBS_None, // MULH_W = 759 |
| 17657 | CEFBS_None, // MULH_WU = 760 |
| 17658 | CEFBS_IsLA64, // MULW_D_W = 761 |
| 17659 | CEFBS_IsLA64, // MULW_D_WU = 762 |
| 17660 | CEFBS_IsLA64, // MUL_D = 763 |
| 17661 | CEFBS_None, // MUL_W = 764 |
| 17662 | CEFBS_None, // NOR = 765 |
| 17663 | CEFBS_None, // OR = 766 |
| 17664 | CEFBS_None, // ORI = 767 |
| 17665 | CEFBS_None, // ORN = 768 |
| 17666 | CEFBS_None, // PCADDI = 769 |
| 17667 | CEFBS_None, // PCADDU12I = 770 |
| 17668 | CEFBS_IsLA64, // PCADDU18I = 771 |
| 17669 | CEFBS_None, // PCALAU12I = 772 |
| 17670 | CEFBS_None, // PRELD = 773 |
| 17671 | CEFBS_IsLA64, // PRELDX = 774 |
| 17672 | CEFBS_None, // RCRI_B = 775 |
| 17673 | CEFBS_IsLA64, // RCRI_D = 776 |
| 17674 | CEFBS_None, // RCRI_H = 777 |
| 17675 | CEFBS_None, // RCRI_W = 778 |
| 17676 | CEFBS_None, // RCR_B = 779 |
| 17677 | CEFBS_IsLA64, // RCR_D = 780 |
| 17678 | CEFBS_None, // RCR_H = 781 |
| 17679 | CEFBS_None, // RCR_W = 782 |
| 17680 | CEFBS_None, // RDTIMEH_W = 783 |
| 17681 | CEFBS_None, // RDTIMEL_W = 784 |
| 17682 | CEFBS_IsLA64, // RDTIME_D = 785 |
| 17683 | CEFBS_None, // REVB_2H = 786 |
| 17684 | CEFBS_IsLA64, // REVB_2W = 787 |
| 17685 | CEFBS_IsLA64, // REVB_4H = 788 |
| 17686 | CEFBS_IsLA64, // REVB_D = 789 |
| 17687 | CEFBS_IsLA64, // REVH_2W = 790 |
| 17688 | CEFBS_IsLA64, // REVH_D = 791 |
| 17689 | CEFBS_None, // ROTRI_B = 792 |
| 17690 | CEFBS_IsLA64, // ROTRI_D = 793 |
| 17691 | CEFBS_None, // ROTRI_H = 794 |
| 17692 | CEFBS_None, // ROTRI_W = 795 |
| 17693 | CEFBS_None, // ROTR_B = 796 |
| 17694 | CEFBS_IsLA64, // ROTR_D = 797 |
| 17695 | CEFBS_None, // ROTR_H = 798 |
| 17696 | CEFBS_None, // ROTR_W = 799 |
| 17697 | CEFBS_None, // SBC_B = 800 |
| 17698 | CEFBS_IsLA64, // SBC_D = 801 |
| 17699 | CEFBS_None, // SBC_H = 802 |
| 17700 | CEFBS_None, // SBC_W = 803 |
| 17701 | CEFBS_IsLA64, // SCREL_D = 804 |
| 17702 | CEFBS_None, // SCREL_W = 805 |
| 17703 | CEFBS_IsLA64, // SC_D = 806 |
| 17704 | CEFBS_IsLA64, // SC_Q = 807 |
| 17705 | CEFBS_None, // SC_W = 808 |
| 17706 | CEFBS_None, // SETARMJ = 809 |
| 17707 | CEFBS_None, // SETX86J = 810 |
| 17708 | CEFBS_None, // SETX86LOOPE = 811 |
| 17709 | CEFBS_None, // SETX86LOOPNE = 812 |
| 17710 | CEFBS_None, // SET_CFR_FALSE = 813 |
| 17711 | CEFBS_None, // SET_CFR_TRUE = 814 |
| 17712 | CEFBS_IsLA64, // SLLI_D = 815 |
| 17713 | CEFBS_None, // SLLI_W = 816 |
| 17714 | CEFBS_IsLA64, // SLL_D = 817 |
| 17715 | CEFBS_None, // SLL_W = 818 |
| 17716 | CEFBS_None, // SLT = 819 |
| 17717 | CEFBS_None, // SLTI = 820 |
| 17718 | CEFBS_None, // SLTU = 821 |
| 17719 | CEFBS_None, // SLTUI = 822 |
| 17720 | CEFBS_IsLA64, // SRAI_D = 823 |
| 17721 | CEFBS_None, // SRAI_W = 824 |
| 17722 | CEFBS_IsLA64, // SRA_D = 825 |
| 17723 | CEFBS_None, // SRA_W = 826 |
| 17724 | CEFBS_IsLA64, // SRLI_D = 827 |
| 17725 | CEFBS_None, // SRLI_W = 828 |
| 17726 | CEFBS_IsLA64, // SRL_D = 829 |
| 17727 | CEFBS_None, // SRL_W = 830 |
| 17728 | CEFBS_IsLA64, // STGT_B = 831 |
| 17729 | CEFBS_IsLA64, // STGT_D = 832 |
| 17730 | CEFBS_IsLA64, // STGT_H = 833 |
| 17731 | CEFBS_IsLA64, // STGT_W = 834 |
| 17732 | CEFBS_IsLA64, // STLE_B = 835 |
| 17733 | CEFBS_IsLA64, // STLE_D = 836 |
| 17734 | CEFBS_IsLA64, // STLE_H = 837 |
| 17735 | CEFBS_IsLA64, // STLE_W = 838 |
| 17736 | CEFBS_IsLA64, // STL_D = 839 |
| 17737 | CEFBS_None, // STL_W = 840 |
| 17738 | CEFBS_IsLA64, // STPTR_D = 841 |
| 17739 | CEFBS_IsLA64, // STPTR_W = 842 |
| 17740 | CEFBS_IsLA64, // STR_D = 843 |
| 17741 | CEFBS_None, // STR_W = 844 |
| 17742 | CEFBS_IsLA64, // STX_B = 845 |
| 17743 | CEFBS_IsLA64, // STX_D = 846 |
| 17744 | CEFBS_IsLA64, // STX_H = 847 |
| 17745 | CEFBS_IsLA64, // STX_W = 848 |
| 17746 | CEFBS_None, // ST_B = 849 |
| 17747 | CEFBS_IsLA64, // ST_D = 850 |
| 17748 | CEFBS_None, // ST_H = 851 |
| 17749 | CEFBS_None, // ST_W = 852 |
| 17750 | CEFBS_IsLA64, // SUB_D = 853 |
| 17751 | CEFBS_None, // SUB_W = 854 |
| 17752 | CEFBS_None, // SYSCALL = 855 |
| 17753 | CEFBS_None, // TLBCLR = 856 |
| 17754 | CEFBS_None, // TLBFILL = 857 |
| 17755 | CEFBS_None, // TLBFLUSH = 858 |
| 17756 | CEFBS_None, // TLBRD = 859 |
| 17757 | CEFBS_None, // TLBSRCH = 860 |
| 17758 | CEFBS_None, // TLBWR = 861 |
| 17759 | CEFBS_None, // VABSD_B = 862 |
| 17760 | CEFBS_None, // VABSD_BU = 863 |
| 17761 | CEFBS_None, // VABSD_D = 864 |
| 17762 | CEFBS_None, // VABSD_DU = 865 |
| 17763 | CEFBS_None, // VABSD_H = 866 |
| 17764 | CEFBS_None, // VABSD_HU = 867 |
| 17765 | CEFBS_None, // VABSD_W = 868 |
| 17766 | CEFBS_None, // VABSD_WU = 869 |
| 17767 | CEFBS_None, // VADDA_B = 870 |
| 17768 | CEFBS_None, // VADDA_D = 871 |
| 17769 | CEFBS_None, // VADDA_H = 872 |
| 17770 | CEFBS_None, // VADDA_W = 873 |
| 17771 | CEFBS_None, // VADDI_BU = 874 |
| 17772 | CEFBS_None, // VADDI_DU = 875 |
| 17773 | CEFBS_None, // VADDI_HU = 876 |
| 17774 | CEFBS_None, // VADDI_WU = 877 |
| 17775 | CEFBS_None, // VADDWEV_D_W = 878 |
| 17776 | CEFBS_None, // VADDWEV_D_WU = 879 |
| 17777 | CEFBS_None, // VADDWEV_D_WU_W = 880 |
| 17778 | CEFBS_None, // VADDWEV_H_B = 881 |
| 17779 | CEFBS_None, // VADDWEV_H_BU = 882 |
| 17780 | CEFBS_None, // VADDWEV_H_BU_B = 883 |
| 17781 | CEFBS_None, // VADDWEV_Q_D = 884 |
| 17782 | CEFBS_None, // VADDWEV_Q_DU = 885 |
| 17783 | CEFBS_None, // VADDWEV_Q_DU_D = 886 |
| 17784 | CEFBS_None, // VADDWEV_W_H = 887 |
| 17785 | CEFBS_None, // VADDWEV_W_HU = 888 |
| 17786 | CEFBS_None, // VADDWEV_W_HU_H = 889 |
| 17787 | CEFBS_None, // VADDWOD_D_W = 890 |
| 17788 | CEFBS_None, // VADDWOD_D_WU = 891 |
| 17789 | CEFBS_None, // VADDWOD_D_WU_W = 892 |
| 17790 | CEFBS_None, // VADDWOD_H_B = 893 |
| 17791 | CEFBS_None, // VADDWOD_H_BU = 894 |
| 17792 | CEFBS_None, // VADDWOD_H_BU_B = 895 |
| 17793 | CEFBS_None, // VADDWOD_Q_D = 896 |
| 17794 | CEFBS_None, // VADDWOD_Q_DU = 897 |
| 17795 | CEFBS_None, // VADDWOD_Q_DU_D = 898 |
| 17796 | CEFBS_None, // VADDWOD_W_H = 899 |
| 17797 | CEFBS_None, // VADDWOD_W_HU = 900 |
| 17798 | CEFBS_None, // VADDWOD_W_HU_H = 901 |
| 17799 | CEFBS_None, // VADD_B = 902 |
| 17800 | CEFBS_None, // VADD_D = 903 |
| 17801 | CEFBS_None, // VADD_H = 904 |
| 17802 | CEFBS_None, // VADD_Q = 905 |
| 17803 | CEFBS_None, // VADD_W = 906 |
| 17804 | CEFBS_None, // VANDI_B = 907 |
| 17805 | CEFBS_None, // VANDN_V = 908 |
| 17806 | CEFBS_None, // VAND_V = 909 |
| 17807 | CEFBS_None, // VAVGR_B = 910 |
| 17808 | CEFBS_None, // VAVGR_BU = 911 |
| 17809 | CEFBS_None, // VAVGR_D = 912 |
| 17810 | CEFBS_None, // VAVGR_DU = 913 |
| 17811 | CEFBS_None, // VAVGR_H = 914 |
| 17812 | CEFBS_None, // VAVGR_HU = 915 |
| 17813 | CEFBS_None, // VAVGR_W = 916 |
| 17814 | CEFBS_None, // VAVGR_WU = 917 |
| 17815 | CEFBS_None, // VAVG_B = 918 |
| 17816 | CEFBS_None, // VAVG_BU = 919 |
| 17817 | CEFBS_None, // VAVG_D = 920 |
| 17818 | CEFBS_None, // VAVG_DU = 921 |
| 17819 | CEFBS_None, // VAVG_H = 922 |
| 17820 | CEFBS_None, // VAVG_HU = 923 |
| 17821 | CEFBS_None, // VAVG_W = 924 |
| 17822 | CEFBS_None, // VAVG_WU = 925 |
| 17823 | CEFBS_None, // VBITCLRI_B = 926 |
| 17824 | CEFBS_None, // VBITCLRI_D = 927 |
| 17825 | CEFBS_None, // VBITCLRI_H = 928 |
| 17826 | CEFBS_None, // VBITCLRI_W = 929 |
| 17827 | CEFBS_None, // VBITCLR_B = 930 |
| 17828 | CEFBS_None, // VBITCLR_D = 931 |
| 17829 | CEFBS_None, // VBITCLR_H = 932 |
| 17830 | CEFBS_None, // VBITCLR_W = 933 |
| 17831 | CEFBS_None, // VBITREVI_B = 934 |
| 17832 | CEFBS_None, // VBITREVI_D = 935 |
| 17833 | CEFBS_None, // VBITREVI_H = 936 |
| 17834 | CEFBS_None, // VBITREVI_W = 937 |
| 17835 | CEFBS_None, // VBITREV_B = 938 |
| 17836 | CEFBS_None, // VBITREV_D = 939 |
| 17837 | CEFBS_None, // VBITREV_H = 940 |
| 17838 | CEFBS_None, // VBITREV_W = 941 |
| 17839 | CEFBS_None, // VBITSELI_B = 942 |
| 17840 | CEFBS_None, // VBITSEL_V = 943 |
| 17841 | CEFBS_None, // VBITSETI_B = 944 |
| 17842 | CEFBS_None, // VBITSETI_D = 945 |
| 17843 | CEFBS_None, // VBITSETI_H = 946 |
| 17844 | CEFBS_None, // VBITSETI_W = 947 |
| 17845 | CEFBS_None, // VBITSET_B = 948 |
| 17846 | CEFBS_None, // VBITSET_D = 949 |
| 17847 | CEFBS_None, // VBITSET_H = 950 |
| 17848 | CEFBS_None, // VBITSET_W = 951 |
| 17849 | CEFBS_None, // VBSLL_V = 952 |
| 17850 | CEFBS_None, // VBSRL_V = 953 |
| 17851 | CEFBS_None, // VCLO_B = 954 |
| 17852 | CEFBS_None, // VCLO_D = 955 |
| 17853 | CEFBS_None, // VCLO_H = 956 |
| 17854 | CEFBS_None, // VCLO_W = 957 |
| 17855 | CEFBS_None, // VCLZ_B = 958 |
| 17856 | CEFBS_None, // VCLZ_D = 959 |
| 17857 | CEFBS_None, // VCLZ_H = 960 |
| 17858 | CEFBS_None, // VCLZ_W = 961 |
| 17859 | CEFBS_None, // VDIV_B = 962 |
| 17860 | CEFBS_None, // VDIV_BU = 963 |
| 17861 | CEFBS_None, // VDIV_D = 964 |
| 17862 | CEFBS_None, // VDIV_DU = 965 |
| 17863 | CEFBS_None, // VDIV_H = 966 |
| 17864 | CEFBS_None, // VDIV_HU = 967 |
| 17865 | CEFBS_None, // VDIV_W = 968 |
| 17866 | CEFBS_None, // VDIV_WU = 969 |
| 17867 | CEFBS_None, // VEXT2XV_DU_BU = 970 |
| 17868 | CEFBS_None, // VEXT2XV_DU_HU = 971 |
| 17869 | CEFBS_None, // VEXT2XV_DU_WU = 972 |
| 17870 | CEFBS_None, // VEXT2XV_D_B = 973 |
| 17871 | CEFBS_None, // VEXT2XV_D_H = 974 |
| 17872 | CEFBS_None, // VEXT2XV_D_W = 975 |
| 17873 | CEFBS_None, // VEXT2XV_HU_BU = 976 |
| 17874 | CEFBS_None, // VEXT2XV_H_B = 977 |
| 17875 | CEFBS_None, // VEXT2XV_WU_BU = 978 |
| 17876 | CEFBS_None, // VEXT2XV_WU_HU = 979 |
| 17877 | CEFBS_None, // VEXT2XV_W_B = 980 |
| 17878 | CEFBS_None, // VEXT2XV_W_H = 981 |
| 17879 | CEFBS_None, // VEXTH_DU_WU = 982 |
| 17880 | CEFBS_None, // VEXTH_D_W = 983 |
| 17881 | CEFBS_None, // VEXTH_HU_BU = 984 |
| 17882 | CEFBS_None, // VEXTH_H_B = 985 |
| 17883 | CEFBS_None, // VEXTH_QU_DU = 986 |
| 17884 | CEFBS_None, // VEXTH_Q_D = 987 |
| 17885 | CEFBS_None, // VEXTH_WU_HU = 988 |
| 17886 | CEFBS_None, // VEXTH_W_H = 989 |
| 17887 | CEFBS_None, // VEXTL_QU_DU = 990 |
| 17888 | CEFBS_None, // VEXTL_Q_D = 991 |
| 17889 | CEFBS_None, // VEXTRINS_B = 992 |
| 17890 | CEFBS_None, // VEXTRINS_D = 993 |
| 17891 | CEFBS_None, // VEXTRINS_H = 994 |
| 17892 | CEFBS_None, // VEXTRINS_W = 995 |
| 17893 | CEFBS_None, // VFADD_D = 996 |
| 17894 | CEFBS_None, // VFADD_S = 997 |
| 17895 | CEFBS_None, // VFCLASS_D = 998 |
| 17896 | CEFBS_None, // VFCLASS_S = 999 |
| 17897 | CEFBS_None, // VFCMP_CAF_D = 1000 |
| 17898 | CEFBS_None, // VFCMP_CAF_S = 1001 |
| 17899 | CEFBS_None, // VFCMP_CEQ_D = 1002 |
| 17900 | CEFBS_None, // VFCMP_CEQ_S = 1003 |
| 17901 | CEFBS_None, // VFCMP_CLE_D = 1004 |
| 17902 | CEFBS_None, // VFCMP_CLE_S = 1005 |
| 17903 | CEFBS_None, // VFCMP_CLT_D = 1006 |
| 17904 | CEFBS_None, // VFCMP_CLT_S = 1007 |
| 17905 | CEFBS_None, // VFCMP_CNE_D = 1008 |
| 17906 | CEFBS_None, // VFCMP_CNE_S = 1009 |
| 17907 | CEFBS_None, // VFCMP_COR_D = 1010 |
| 17908 | CEFBS_None, // VFCMP_COR_S = 1011 |
| 17909 | CEFBS_None, // VFCMP_CUEQ_D = 1012 |
| 17910 | CEFBS_None, // VFCMP_CUEQ_S = 1013 |
| 17911 | CEFBS_None, // VFCMP_CULE_D = 1014 |
| 17912 | CEFBS_None, // VFCMP_CULE_S = 1015 |
| 17913 | CEFBS_None, // VFCMP_CULT_D = 1016 |
| 17914 | CEFBS_None, // VFCMP_CULT_S = 1017 |
| 17915 | CEFBS_None, // VFCMP_CUNE_D = 1018 |
| 17916 | CEFBS_None, // VFCMP_CUNE_S = 1019 |
| 17917 | CEFBS_None, // VFCMP_CUN_D = 1020 |
| 17918 | CEFBS_None, // VFCMP_CUN_S = 1021 |
| 17919 | CEFBS_None, // VFCMP_SAF_D = 1022 |
| 17920 | CEFBS_None, // VFCMP_SAF_S = 1023 |
| 17921 | CEFBS_None, // VFCMP_SEQ_D = 1024 |
| 17922 | CEFBS_None, // VFCMP_SEQ_S = 1025 |
| 17923 | CEFBS_None, // VFCMP_SLE_D = 1026 |
| 17924 | CEFBS_None, // VFCMP_SLE_S = 1027 |
| 17925 | CEFBS_None, // VFCMP_SLT_D = 1028 |
| 17926 | CEFBS_None, // VFCMP_SLT_S = 1029 |
| 17927 | CEFBS_None, // VFCMP_SNE_D = 1030 |
| 17928 | CEFBS_None, // VFCMP_SNE_S = 1031 |
| 17929 | CEFBS_None, // VFCMP_SOR_D = 1032 |
| 17930 | CEFBS_None, // VFCMP_SOR_S = 1033 |
| 17931 | CEFBS_None, // VFCMP_SUEQ_D = 1034 |
| 17932 | CEFBS_None, // VFCMP_SUEQ_S = 1035 |
| 17933 | CEFBS_None, // VFCMP_SULE_D = 1036 |
| 17934 | CEFBS_None, // VFCMP_SULE_S = 1037 |
| 17935 | CEFBS_None, // VFCMP_SULT_D = 1038 |
| 17936 | CEFBS_None, // VFCMP_SULT_S = 1039 |
| 17937 | CEFBS_None, // VFCMP_SUNE_D = 1040 |
| 17938 | CEFBS_None, // VFCMP_SUNE_S = 1041 |
| 17939 | CEFBS_None, // VFCMP_SUN_D = 1042 |
| 17940 | CEFBS_None, // VFCMP_SUN_S = 1043 |
| 17941 | CEFBS_None, // VFCVTH_D_S = 1044 |
| 17942 | CEFBS_None, // VFCVTH_S_H = 1045 |
| 17943 | CEFBS_None, // VFCVTL_D_S = 1046 |
| 17944 | CEFBS_None, // VFCVTL_S_H = 1047 |
| 17945 | CEFBS_None, // VFCVT_H_S = 1048 |
| 17946 | CEFBS_None, // VFCVT_S_D = 1049 |
| 17947 | CEFBS_None, // VFDIV_D = 1050 |
| 17948 | CEFBS_None, // VFDIV_S = 1051 |
| 17949 | CEFBS_None, // VFFINTH_D_W = 1052 |
| 17950 | CEFBS_None, // VFFINTL_D_W = 1053 |
| 17951 | CEFBS_None, // VFFINT_D_L = 1054 |
| 17952 | CEFBS_None, // VFFINT_D_LU = 1055 |
| 17953 | CEFBS_None, // VFFINT_S_L = 1056 |
| 17954 | CEFBS_None, // VFFINT_S_W = 1057 |
| 17955 | CEFBS_None, // VFFINT_S_WU = 1058 |
| 17956 | CEFBS_None, // VFLOGB_D = 1059 |
| 17957 | CEFBS_None, // VFLOGB_S = 1060 |
| 17958 | CEFBS_None, // VFMADD_D = 1061 |
| 17959 | CEFBS_None, // VFMADD_S = 1062 |
| 17960 | CEFBS_None, // VFMAXA_D = 1063 |
| 17961 | CEFBS_None, // VFMAXA_S = 1064 |
| 17962 | CEFBS_None, // VFMAX_D = 1065 |
| 17963 | CEFBS_None, // VFMAX_S = 1066 |
| 17964 | CEFBS_None, // VFMINA_D = 1067 |
| 17965 | CEFBS_None, // VFMINA_S = 1068 |
| 17966 | CEFBS_None, // VFMIN_D = 1069 |
| 17967 | CEFBS_None, // VFMIN_S = 1070 |
| 17968 | CEFBS_None, // VFMSUB_D = 1071 |
| 17969 | CEFBS_None, // VFMSUB_S = 1072 |
| 17970 | CEFBS_None, // VFMUL_D = 1073 |
| 17971 | CEFBS_None, // VFMUL_S = 1074 |
| 17972 | CEFBS_None, // VFNMADD_D = 1075 |
| 17973 | CEFBS_None, // VFNMADD_S = 1076 |
| 17974 | CEFBS_None, // VFNMSUB_D = 1077 |
| 17975 | CEFBS_None, // VFNMSUB_S = 1078 |
| 17976 | CEFBS_None, // VFRECIPE_D = 1079 |
| 17977 | CEFBS_None, // VFRECIPE_S = 1080 |
| 17978 | CEFBS_None, // VFRECIP_D = 1081 |
| 17979 | CEFBS_None, // VFRECIP_S = 1082 |
| 17980 | CEFBS_None, // VFRINTRM_D = 1083 |
| 17981 | CEFBS_None, // VFRINTRM_S = 1084 |
| 17982 | CEFBS_None, // VFRINTRNE_D = 1085 |
| 17983 | CEFBS_None, // VFRINTRNE_S = 1086 |
| 17984 | CEFBS_None, // VFRINTRP_D = 1087 |
| 17985 | CEFBS_None, // VFRINTRP_S = 1088 |
| 17986 | CEFBS_None, // VFRINTRZ_D = 1089 |
| 17987 | CEFBS_None, // VFRINTRZ_S = 1090 |
| 17988 | CEFBS_None, // VFRINT_D = 1091 |
| 17989 | CEFBS_None, // VFRINT_S = 1092 |
| 17990 | CEFBS_None, // VFRSQRTE_D = 1093 |
| 17991 | CEFBS_None, // VFRSQRTE_S = 1094 |
| 17992 | CEFBS_None, // VFRSQRT_D = 1095 |
| 17993 | CEFBS_None, // VFRSQRT_S = 1096 |
| 17994 | CEFBS_None, // VFRSTPI_B = 1097 |
| 17995 | CEFBS_None, // VFRSTPI_H = 1098 |
| 17996 | CEFBS_None, // VFRSTP_B = 1099 |
| 17997 | CEFBS_None, // VFRSTP_H = 1100 |
| 17998 | CEFBS_None, // VFSQRT_D = 1101 |
| 17999 | CEFBS_None, // VFSQRT_S = 1102 |
| 18000 | CEFBS_None, // VFSUB_D = 1103 |
| 18001 | CEFBS_None, // VFSUB_S = 1104 |
| 18002 | CEFBS_None, // VFTINTH_L_S = 1105 |
| 18003 | CEFBS_None, // VFTINTL_L_S = 1106 |
| 18004 | CEFBS_None, // VFTINTRMH_L_S = 1107 |
| 18005 | CEFBS_None, // VFTINTRML_L_S = 1108 |
| 18006 | CEFBS_None, // VFTINTRM_L_D = 1109 |
| 18007 | CEFBS_None, // VFTINTRM_W_D = 1110 |
| 18008 | CEFBS_None, // VFTINTRM_W_S = 1111 |
| 18009 | CEFBS_None, // VFTINTRNEH_L_S = 1112 |
| 18010 | CEFBS_None, // VFTINTRNEL_L_S = 1113 |
| 18011 | CEFBS_None, // VFTINTRNE_L_D = 1114 |
| 18012 | CEFBS_None, // VFTINTRNE_W_D = 1115 |
| 18013 | CEFBS_None, // VFTINTRNE_W_S = 1116 |
| 18014 | CEFBS_None, // VFTINTRPH_L_S = 1117 |
| 18015 | CEFBS_None, // VFTINTRPL_L_S = 1118 |
| 18016 | CEFBS_None, // VFTINTRP_L_D = 1119 |
| 18017 | CEFBS_None, // VFTINTRP_W_D = 1120 |
| 18018 | CEFBS_None, // VFTINTRP_W_S = 1121 |
| 18019 | CEFBS_None, // VFTINTRZH_L_S = 1122 |
| 18020 | CEFBS_None, // VFTINTRZL_L_S = 1123 |
| 18021 | CEFBS_None, // VFTINTRZ_LU_D = 1124 |
| 18022 | CEFBS_None, // VFTINTRZ_L_D = 1125 |
| 18023 | CEFBS_None, // VFTINTRZ_WU_S = 1126 |
| 18024 | CEFBS_None, // VFTINTRZ_W_D = 1127 |
| 18025 | CEFBS_None, // VFTINTRZ_W_S = 1128 |
| 18026 | CEFBS_None, // VFTINT_LU_D = 1129 |
| 18027 | CEFBS_None, // VFTINT_L_D = 1130 |
| 18028 | CEFBS_None, // VFTINT_WU_S = 1131 |
| 18029 | CEFBS_None, // VFTINT_W_D = 1132 |
| 18030 | CEFBS_None, // VFTINT_W_S = 1133 |
| 18031 | CEFBS_None, // VHADDW_DU_WU = 1134 |
| 18032 | CEFBS_None, // VHADDW_D_W = 1135 |
| 18033 | CEFBS_None, // VHADDW_HU_BU = 1136 |
| 18034 | CEFBS_None, // VHADDW_H_B = 1137 |
| 18035 | CEFBS_None, // VHADDW_QU_DU = 1138 |
| 18036 | CEFBS_None, // VHADDW_Q_D = 1139 |
| 18037 | CEFBS_None, // VHADDW_WU_HU = 1140 |
| 18038 | CEFBS_None, // VHADDW_W_H = 1141 |
| 18039 | CEFBS_None, // VHSUBW_DU_WU = 1142 |
| 18040 | CEFBS_None, // VHSUBW_D_W = 1143 |
| 18041 | CEFBS_None, // VHSUBW_HU_BU = 1144 |
| 18042 | CEFBS_None, // VHSUBW_H_B = 1145 |
| 18043 | CEFBS_None, // VHSUBW_QU_DU = 1146 |
| 18044 | CEFBS_None, // VHSUBW_Q_D = 1147 |
| 18045 | CEFBS_None, // VHSUBW_WU_HU = 1148 |
| 18046 | CEFBS_None, // VHSUBW_W_H = 1149 |
| 18047 | CEFBS_None, // VILVH_B = 1150 |
| 18048 | CEFBS_None, // VILVH_D = 1151 |
| 18049 | CEFBS_None, // VILVH_H = 1152 |
| 18050 | CEFBS_None, // VILVH_W = 1153 |
| 18051 | CEFBS_None, // VILVL_B = 1154 |
| 18052 | CEFBS_None, // VILVL_D = 1155 |
| 18053 | CEFBS_None, // VILVL_H = 1156 |
| 18054 | CEFBS_None, // VILVL_W = 1157 |
| 18055 | CEFBS_None, // VINSGR2VR_B = 1158 |
| 18056 | CEFBS_None, // VINSGR2VR_D = 1159 |
| 18057 | CEFBS_None, // VINSGR2VR_H = 1160 |
| 18058 | CEFBS_None, // VINSGR2VR_W = 1161 |
| 18059 | CEFBS_None, // VLD = 1162 |
| 18060 | CEFBS_None, // VLDI = 1163 |
| 18061 | CEFBS_None, // VLDREPL_B = 1164 |
| 18062 | CEFBS_None, // VLDREPL_D = 1165 |
| 18063 | CEFBS_None, // VLDREPL_H = 1166 |
| 18064 | CEFBS_None, // VLDREPL_W = 1167 |
| 18065 | CEFBS_None, // VLDX = 1168 |
| 18066 | CEFBS_None, // VMADDWEV_D_W = 1169 |
| 18067 | CEFBS_None, // VMADDWEV_D_WU = 1170 |
| 18068 | CEFBS_None, // VMADDWEV_D_WU_W = 1171 |
| 18069 | CEFBS_None, // VMADDWEV_H_B = 1172 |
| 18070 | CEFBS_None, // VMADDWEV_H_BU = 1173 |
| 18071 | CEFBS_None, // VMADDWEV_H_BU_B = 1174 |
| 18072 | CEFBS_None, // VMADDWEV_Q_D = 1175 |
| 18073 | CEFBS_None, // VMADDWEV_Q_DU = 1176 |
| 18074 | CEFBS_None, // VMADDWEV_Q_DU_D = 1177 |
| 18075 | CEFBS_None, // VMADDWEV_W_H = 1178 |
| 18076 | CEFBS_None, // VMADDWEV_W_HU = 1179 |
| 18077 | CEFBS_None, // VMADDWEV_W_HU_H = 1180 |
| 18078 | CEFBS_None, // VMADDWOD_D_W = 1181 |
| 18079 | CEFBS_None, // VMADDWOD_D_WU = 1182 |
| 18080 | CEFBS_None, // VMADDWOD_D_WU_W = 1183 |
| 18081 | CEFBS_None, // VMADDWOD_H_B = 1184 |
| 18082 | CEFBS_None, // VMADDWOD_H_BU = 1185 |
| 18083 | CEFBS_None, // VMADDWOD_H_BU_B = 1186 |
| 18084 | CEFBS_None, // VMADDWOD_Q_D = 1187 |
| 18085 | CEFBS_None, // VMADDWOD_Q_DU = 1188 |
| 18086 | CEFBS_None, // VMADDWOD_Q_DU_D = 1189 |
| 18087 | CEFBS_None, // VMADDWOD_W_H = 1190 |
| 18088 | CEFBS_None, // VMADDWOD_W_HU = 1191 |
| 18089 | CEFBS_None, // VMADDWOD_W_HU_H = 1192 |
| 18090 | CEFBS_None, // VMADD_B = 1193 |
| 18091 | CEFBS_None, // VMADD_D = 1194 |
| 18092 | CEFBS_None, // VMADD_H = 1195 |
| 18093 | CEFBS_None, // VMADD_W = 1196 |
| 18094 | CEFBS_None, // VMAXI_B = 1197 |
| 18095 | CEFBS_None, // VMAXI_BU = 1198 |
| 18096 | CEFBS_None, // VMAXI_D = 1199 |
| 18097 | CEFBS_None, // VMAXI_DU = 1200 |
| 18098 | CEFBS_None, // VMAXI_H = 1201 |
| 18099 | CEFBS_None, // VMAXI_HU = 1202 |
| 18100 | CEFBS_None, // VMAXI_W = 1203 |
| 18101 | CEFBS_None, // VMAXI_WU = 1204 |
| 18102 | CEFBS_None, // VMAX_B = 1205 |
| 18103 | CEFBS_None, // VMAX_BU = 1206 |
| 18104 | CEFBS_None, // VMAX_D = 1207 |
| 18105 | CEFBS_None, // VMAX_DU = 1208 |
| 18106 | CEFBS_None, // VMAX_H = 1209 |
| 18107 | CEFBS_None, // VMAX_HU = 1210 |
| 18108 | CEFBS_None, // VMAX_W = 1211 |
| 18109 | CEFBS_None, // VMAX_WU = 1212 |
| 18110 | CEFBS_None, // VMINI_B = 1213 |
| 18111 | CEFBS_None, // VMINI_BU = 1214 |
| 18112 | CEFBS_None, // VMINI_D = 1215 |
| 18113 | CEFBS_None, // VMINI_DU = 1216 |
| 18114 | CEFBS_None, // VMINI_H = 1217 |
| 18115 | CEFBS_None, // VMINI_HU = 1218 |
| 18116 | CEFBS_None, // VMINI_W = 1219 |
| 18117 | CEFBS_None, // VMINI_WU = 1220 |
| 18118 | CEFBS_None, // VMIN_B = 1221 |
| 18119 | CEFBS_None, // VMIN_BU = 1222 |
| 18120 | CEFBS_None, // VMIN_D = 1223 |
| 18121 | CEFBS_None, // VMIN_DU = 1224 |
| 18122 | CEFBS_None, // VMIN_H = 1225 |
| 18123 | CEFBS_None, // VMIN_HU = 1226 |
| 18124 | CEFBS_None, // VMIN_W = 1227 |
| 18125 | CEFBS_None, // VMIN_WU = 1228 |
| 18126 | CEFBS_None, // VMOD_B = 1229 |
| 18127 | CEFBS_None, // VMOD_BU = 1230 |
| 18128 | CEFBS_None, // VMOD_D = 1231 |
| 18129 | CEFBS_None, // VMOD_DU = 1232 |
| 18130 | CEFBS_None, // VMOD_H = 1233 |
| 18131 | CEFBS_None, // VMOD_HU = 1234 |
| 18132 | CEFBS_None, // VMOD_W = 1235 |
| 18133 | CEFBS_None, // VMOD_WU = 1236 |
| 18134 | CEFBS_None, // VMSKGEZ_B = 1237 |
| 18135 | CEFBS_None, // VMSKLTZ_B = 1238 |
| 18136 | CEFBS_None, // VMSKLTZ_D = 1239 |
| 18137 | CEFBS_None, // VMSKLTZ_H = 1240 |
| 18138 | CEFBS_None, // VMSKLTZ_W = 1241 |
| 18139 | CEFBS_None, // VMSKNZ_B = 1242 |
| 18140 | CEFBS_None, // VMSUB_B = 1243 |
| 18141 | CEFBS_None, // VMSUB_D = 1244 |
| 18142 | CEFBS_None, // VMSUB_H = 1245 |
| 18143 | CEFBS_None, // VMSUB_W = 1246 |
| 18144 | CEFBS_None, // VMUH_B = 1247 |
| 18145 | CEFBS_None, // VMUH_BU = 1248 |
| 18146 | CEFBS_None, // VMUH_D = 1249 |
| 18147 | CEFBS_None, // VMUH_DU = 1250 |
| 18148 | CEFBS_None, // VMUH_H = 1251 |
| 18149 | CEFBS_None, // VMUH_HU = 1252 |
| 18150 | CEFBS_None, // VMUH_W = 1253 |
| 18151 | CEFBS_None, // VMUH_WU = 1254 |
| 18152 | CEFBS_None, // VMULWEV_D_W = 1255 |
| 18153 | CEFBS_None, // VMULWEV_D_WU = 1256 |
| 18154 | CEFBS_None, // VMULWEV_D_WU_W = 1257 |
| 18155 | CEFBS_None, // VMULWEV_H_B = 1258 |
| 18156 | CEFBS_None, // VMULWEV_H_BU = 1259 |
| 18157 | CEFBS_None, // VMULWEV_H_BU_B = 1260 |
| 18158 | CEFBS_None, // VMULWEV_Q_D = 1261 |
| 18159 | CEFBS_None, // VMULWEV_Q_DU = 1262 |
| 18160 | CEFBS_None, // VMULWEV_Q_DU_D = 1263 |
| 18161 | CEFBS_None, // VMULWEV_W_H = 1264 |
| 18162 | CEFBS_None, // VMULWEV_W_HU = 1265 |
| 18163 | CEFBS_None, // VMULWEV_W_HU_H = 1266 |
| 18164 | CEFBS_None, // VMULWOD_D_W = 1267 |
| 18165 | CEFBS_None, // VMULWOD_D_WU = 1268 |
| 18166 | CEFBS_None, // VMULWOD_D_WU_W = 1269 |
| 18167 | CEFBS_None, // VMULWOD_H_B = 1270 |
| 18168 | CEFBS_None, // VMULWOD_H_BU = 1271 |
| 18169 | CEFBS_None, // VMULWOD_H_BU_B = 1272 |
| 18170 | CEFBS_None, // VMULWOD_Q_D = 1273 |
| 18171 | CEFBS_None, // VMULWOD_Q_DU = 1274 |
| 18172 | CEFBS_None, // VMULWOD_Q_DU_D = 1275 |
| 18173 | CEFBS_None, // VMULWOD_W_H = 1276 |
| 18174 | CEFBS_None, // VMULWOD_W_HU = 1277 |
| 18175 | CEFBS_None, // VMULWOD_W_HU_H = 1278 |
| 18176 | CEFBS_None, // VMUL_B = 1279 |
| 18177 | CEFBS_None, // VMUL_D = 1280 |
| 18178 | CEFBS_None, // VMUL_H = 1281 |
| 18179 | CEFBS_None, // VMUL_W = 1282 |
| 18180 | CEFBS_None, // VNEG_B = 1283 |
| 18181 | CEFBS_None, // VNEG_D = 1284 |
| 18182 | CEFBS_None, // VNEG_H = 1285 |
| 18183 | CEFBS_None, // VNEG_W = 1286 |
| 18184 | CEFBS_None, // VNORI_B = 1287 |
| 18185 | CEFBS_None, // VNOR_V = 1288 |
| 18186 | CEFBS_None, // VORI_B = 1289 |
| 18187 | CEFBS_None, // VORN_V = 1290 |
| 18188 | CEFBS_None, // VOR_V = 1291 |
| 18189 | CEFBS_None, // VPACKEV_B = 1292 |
| 18190 | CEFBS_None, // VPACKEV_D = 1293 |
| 18191 | CEFBS_None, // VPACKEV_H = 1294 |
| 18192 | CEFBS_None, // VPACKEV_W = 1295 |
| 18193 | CEFBS_None, // VPACKOD_B = 1296 |
| 18194 | CEFBS_None, // VPACKOD_D = 1297 |
| 18195 | CEFBS_None, // VPACKOD_H = 1298 |
| 18196 | CEFBS_None, // VPACKOD_W = 1299 |
| 18197 | CEFBS_None, // VPCNT_B = 1300 |
| 18198 | CEFBS_None, // VPCNT_D = 1301 |
| 18199 | CEFBS_None, // VPCNT_H = 1302 |
| 18200 | CEFBS_None, // VPCNT_W = 1303 |
| 18201 | CEFBS_None, // VPERMI_W = 1304 |
| 18202 | CEFBS_None, // VPICKEV_B = 1305 |
| 18203 | CEFBS_None, // VPICKEV_D = 1306 |
| 18204 | CEFBS_None, // VPICKEV_H = 1307 |
| 18205 | CEFBS_None, // VPICKEV_W = 1308 |
| 18206 | CEFBS_None, // VPICKOD_B = 1309 |
| 18207 | CEFBS_None, // VPICKOD_D = 1310 |
| 18208 | CEFBS_None, // VPICKOD_H = 1311 |
| 18209 | CEFBS_None, // VPICKOD_W = 1312 |
| 18210 | CEFBS_None, // VPICKVE2GR_B = 1313 |
| 18211 | CEFBS_None, // VPICKVE2GR_BU = 1314 |
| 18212 | CEFBS_None, // VPICKVE2GR_D = 1315 |
| 18213 | CEFBS_None, // VPICKVE2GR_DU = 1316 |
| 18214 | CEFBS_None, // VPICKVE2GR_H = 1317 |
| 18215 | CEFBS_None, // VPICKVE2GR_HU = 1318 |
| 18216 | CEFBS_None, // VPICKVE2GR_W = 1319 |
| 18217 | CEFBS_None, // VPICKVE2GR_WU = 1320 |
| 18218 | CEFBS_None, // VREPLGR2VR_B = 1321 |
| 18219 | CEFBS_None, // VREPLGR2VR_D = 1322 |
| 18220 | CEFBS_None, // VREPLGR2VR_H = 1323 |
| 18221 | CEFBS_None, // VREPLGR2VR_W = 1324 |
| 18222 | CEFBS_None, // VREPLVEI_B = 1325 |
| 18223 | CEFBS_None, // VREPLVEI_D = 1326 |
| 18224 | CEFBS_None, // VREPLVEI_H = 1327 |
| 18225 | CEFBS_None, // VREPLVEI_W = 1328 |
| 18226 | CEFBS_None, // VREPLVE_B = 1329 |
| 18227 | CEFBS_None, // VREPLVE_D = 1330 |
| 18228 | CEFBS_None, // VREPLVE_H = 1331 |
| 18229 | CEFBS_None, // VREPLVE_W = 1332 |
| 18230 | CEFBS_None, // VROTRI_B = 1333 |
| 18231 | CEFBS_None, // VROTRI_D = 1334 |
| 18232 | CEFBS_None, // VROTRI_H = 1335 |
| 18233 | CEFBS_None, // VROTRI_W = 1336 |
| 18234 | CEFBS_None, // VROTR_B = 1337 |
| 18235 | CEFBS_None, // VROTR_D = 1338 |
| 18236 | CEFBS_None, // VROTR_H = 1339 |
| 18237 | CEFBS_None, // VROTR_W = 1340 |
| 18238 | CEFBS_None, // VSADD_B = 1341 |
| 18239 | CEFBS_None, // VSADD_BU = 1342 |
| 18240 | CEFBS_None, // VSADD_D = 1343 |
| 18241 | CEFBS_None, // VSADD_DU = 1344 |
| 18242 | CEFBS_None, // VSADD_H = 1345 |
| 18243 | CEFBS_None, // VSADD_HU = 1346 |
| 18244 | CEFBS_None, // VSADD_W = 1347 |
| 18245 | CEFBS_None, // VSADD_WU = 1348 |
| 18246 | CEFBS_None, // VSAT_B = 1349 |
| 18247 | CEFBS_None, // VSAT_BU = 1350 |
| 18248 | CEFBS_None, // VSAT_D = 1351 |
| 18249 | CEFBS_None, // VSAT_DU = 1352 |
| 18250 | CEFBS_None, // VSAT_H = 1353 |
| 18251 | CEFBS_None, // VSAT_HU = 1354 |
| 18252 | CEFBS_None, // VSAT_W = 1355 |
| 18253 | CEFBS_None, // VSAT_WU = 1356 |
| 18254 | CEFBS_None, // VSEQI_B = 1357 |
| 18255 | CEFBS_None, // VSEQI_D = 1358 |
| 18256 | CEFBS_None, // VSEQI_H = 1359 |
| 18257 | CEFBS_None, // VSEQI_W = 1360 |
| 18258 | CEFBS_None, // VSEQ_B = 1361 |
| 18259 | CEFBS_None, // VSEQ_D = 1362 |
| 18260 | CEFBS_None, // VSEQ_H = 1363 |
| 18261 | CEFBS_None, // VSEQ_W = 1364 |
| 18262 | CEFBS_None, // VSETALLNEZ_B = 1365 |
| 18263 | CEFBS_None, // VSETALLNEZ_D = 1366 |
| 18264 | CEFBS_None, // VSETALLNEZ_H = 1367 |
| 18265 | CEFBS_None, // VSETALLNEZ_W = 1368 |
| 18266 | CEFBS_None, // VSETANYEQZ_B = 1369 |
| 18267 | CEFBS_None, // VSETANYEQZ_D = 1370 |
| 18268 | CEFBS_None, // VSETANYEQZ_H = 1371 |
| 18269 | CEFBS_None, // VSETANYEQZ_W = 1372 |
| 18270 | CEFBS_None, // VSETEQZ_V = 1373 |
| 18271 | CEFBS_None, // VSETNEZ_V = 1374 |
| 18272 | CEFBS_None, // VSHUF4I_B = 1375 |
| 18273 | CEFBS_None, // VSHUF4I_D = 1376 |
| 18274 | CEFBS_None, // VSHUF4I_H = 1377 |
| 18275 | CEFBS_None, // VSHUF4I_W = 1378 |
| 18276 | CEFBS_None, // VSHUF_B = 1379 |
| 18277 | CEFBS_None, // VSHUF_D = 1380 |
| 18278 | CEFBS_None, // VSHUF_H = 1381 |
| 18279 | CEFBS_None, // VSHUF_W = 1382 |
| 18280 | CEFBS_None, // VSIGNCOV_B = 1383 |
| 18281 | CEFBS_None, // VSIGNCOV_D = 1384 |
| 18282 | CEFBS_None, // VSIGNCOV_H = 1385 |
| 18283 | CEFBS_None, // VSIGNCOV_W = 1386 |
| 18284 | CEFBS_None, // VSLEI_B = 1387 |
| 18285 | CEFBS_None, // VSLEI_BU = 1388 |
| 18286 | CEFBS_None, // VSLEI_D = 1389 |
| 18287 | CEFBS_None, // VSLEI_DU = 1390 |
| 18288 | CEFBS_None, // VSLEI_H = 1391 |
| 18289 | CEFBS_None, // VSLEI_HU = 1392 |
| 18290 | CEFBS_None, // VSLEI_W = 1393 |
| 18291 | CEFBS_None, // VSLEI_WU = 1394 |
| 18292 | CEFBS_None, // VSLE_B = 1395 |
| 18293 | CEFBS_None, // VSLE_BU = 1396 |
| 18294 | CEFBS_None, // VSLE_D = 1397 |
| 18295 | CEFBS_None, // VSLE_DU = 1398 |
| 18296 | CEFBS_None, // VSLE_H = 1399 |
| 18297 | CEFBS_None, // VSLE_HU = 1400 |
| 18298 | CEFBS_None, // VSLE_W = 1401 |
| 18299 | CEFBS_None, // VSLE_WU = 1402 |
| 18300 | CEFBS_None, // VSLLI_B = 1403 |
| 18301 | CEFBS_None, // VSLLI_D = 1404 |
| 18302 | CEFBS_None, // VSLLI_H = 1405 |
| 18303 | CEFBS_None, // VSLLI_W = 1406 |
| 18304 | CEFBS_None, // VSLLWIL_DU_WU = 1407 |
| 18305 | CEFBS_None, // VSLLWIL_D_W = 1408 |
| 18306 | CEFBS_None, // VSLLWIL_HU_BU = 1409 |
| 18307 | CEFBS_None, // VSLLWIL_H_B = 1410 |
| 18308 | CEFBS_None, // VSLLWIL_WU_HU = 1411 |
| 18309 | CEFBS_None, // VSLLWIL_W_H = 1412 |
| 18310 | CEFBS_None, // VSLL_B = 1413 |
| 18311 | CEFBS_None, // VSLL_D = 1414 |
| 18312 | CEFBS_None, // VSLL_H = 1415 |
| 18313 | CEFBS_None, // VSLL_W = 1416 |
| 18314 | CEFBS_None, // VSLTI_B = 1417 |
| 18315 | CEFBS_None, // VSLTI_BU = 1418 |
| 18316 | CEFBS_None, // VSLTI_D = 1419 |
| 18317 | CEFBS_None, // VSLTI_DU = 1420 |
| 18318 | CEFBS_None, // VSLTI_H = 1421 |
| 18319 | CEFBS_None, // VSLTI_HU = 1422 |
| 18320 | CEFBS_None, // VSLTI_W = 1423 |
| 18321 | CEFBS_None, // VSLTI_WU = 1424 |
| 18322 | CEFBS_None, // VSLT_B = 1425 |
| 18323 | CEFBS_None, // VSLT_BU = 1426 |
| 18324 | CEFBS_None, // VSLT_D = 1427 |
| 18325 | CEFBS_None, // VSLT_DU = 1428 |
| 18326 | CEFBS_None, // VSLT_H = 1429 |
| 18327 | CEFBS_None, // VSLT_HU = 1430 |
| 18328 | CEFBS_None, // VSLT_W = 1431 |
| 18329 | CEFBS_None, // VSLT_WU = 1432 |
| 18330 | CEFBS_None, // VSRAI_B = 1433 |
| 18331 | CEFBS_None, // VSRAI_D = 1434 |
| 18332 | CEFBS_None, // VSRAI_H = 1435 |
| 18333 | CEFBS_None, // VSRAI_W = 1436 |
| 18334 | CEFBS_None, // VSRANI_B_H = 1437 |
| 18335 | CEFBS_None, // VSRANI_D_Q = 1438 |
| 18336 | CEFBS_None, // VSRANI_H_W = 1439 |
| 18337 | CEFBS_None, // VSRANI_W_D = 1440 |
| 18338 | CEFBS_None, // VSRAN_B_H = 1441 |
| 18339 | CEFBS_None, // VSRAN_H_W = 1442 |
| 18340 | CEFBS_None, // VSRAN_W_D = 1443 |
| 18341 | CEFBS_None, // VSRARI_B = 1444 |
| 18342 | CEFBS_None, // VSRARI_D = 1445 |
| 18343 | CEFBS_None, // VSRARI_H = 1446 |
| 18344 | CEFBS_None, // VSRARI_W = 1447 |
| 18345 | CEFBS_None, // VSRARNI_B_H = 1448 |
| 18346 | CEFBS_None, // VSRARNI_D_Q = 1449 |
| 18347 | CEFBS_None, // VSRARNI_H_W = 1450 |
| 18348 | CEFBS_None, // VSRARNI_W_D = 1451 |
| 18349 | CEFBS_None, // VSRARN_B_H = 1452 |
| 18350 | CEFBS_None, // VSRARN_H_W = 1453 |
| 18351 | CEFBS_None, // VSRARN_W_D = 1454 |
| 18352 | CEFBS_None, // VSRAR_B = 1455 |
| 18353 | CEFBS_None, // VSRAR_D = 1456 |
| 18354 | CEFBS_None, // VSRAR_H = 1457 |
| 18355 | CEFBS_None, // VSRAR_W = 1458 |
| 18356 | CEFBS_None, // VSRA_B = 1459 |
| 18357 | CEFBS_None, // VSRA_D = 1460 |
| 18358 | CEFBS_None, // VSRA_H = 1461 |
| 18359 | CEFBS_None, // VSRA_W = 1462 |
| 18360 | CEFBS_None, // VSRLI_B = 1463 |
| 18361 | CEFBS_None, // VSRLI_D = 1464 |
| 18362 | CEFBS_None, // VSRLI_H = 1465 |
| 18363 | CEFBS_None, // VSRLI_W = 1466 |
| 18364 | CEFBS_None, // VSRLNI_B_H = 1467 |
| 18365 | CEFBS_None, // VSRLNI_D_Q = 1468 |
| 18366 | CEFBS_None, // VSRLNI_H_W = 1469 |
| 18367 | CEFBS_None, // VSRLNI_W_D = 1470 |
| 18368 | CEFBS_None, // VSRLN_B_H = 1471 |
| 18369 | CEFBS_None, // VSRLN_H_W = 1472 |
| 18370 | CEFBS_None, // VSRLN_W_D = 1473 |
| 18371 | CEFBS_None, // VSRLRI_B = 1474 |
| 18372 | CEFBS_None, // VSRLRI_D = 1475 |
| 18373 | CEFBS_None, // VSRLRI_H = 1476 |
| 18374 | CEFBS_None, // VSRLRI_W = 1477 |
| 18375 | CEFBS_None, // VSRLRNI_B_H = 1478 |
| 18376 | CEFBS_None, // VSRLRNI_D_Q = 1479 |
| 18377 | CEFBS_None, // VSRLRNI_H_W = 1480 |
| 18378 | CEFBS_None, // VSRLRNI_W_D = 1481 |
| 18379 | CEFBS_None, // VSRLRN_B_H = 1482 |
| 18380 | CEFBS_None, // VSRLRN_H_W = 1483 |
| 18381 | CEFBS_None, // VSRLRN_W_D = 1484 |
| 18382 | CEFBS_None, // VSRLR_B = 1485 |
| 18383 | CEFBS_None, // VSRLR_D = 1486 |
| 18384 | CEFBS_None, // VSRLR_H = 1487 |
| 18385 | CEFBS_None, // VSRLR_W = 1488 |
| 18386 | CEFBS_None, // VSRL_B = 1489 |
| 18387 | CEFBS_None, // VSRL_D = 1490 |
| 18388 | CEFBS_None, // VSRL_H = 1491 |
| 18389 | CEFBS_None, // VSRL_W = 1492 |
| 18390 | CEFBS_None, // VSSRANI_BU_H = 1493 |
| 18391 | CEFBS_None, // VSSRANI_B_H = 1494 |
| 18392 | CEFBS_None, // VSSRANI_DU_Q = 1495 |
| 18393 | CEFBS_None, // VSSRANI_D_Q = 1496 |
| 18394 | CEFBS_None, // VSSRANI_HU_W = 1497 |
| 18395 | CEFBS_None, // VSSRANI_H_W = 1498 |
| 18396 | CEFBS_None, // VSSRANI_WU_D = 1499 |
| 18397 | CEFBS_None, // VSSRANI_W_D = 1500 |
| 18398 | CEFBS_None, // VSSRAN_BU_H = 1501 |
| 18399 | CEFBS_None, // VSSRAN_B_H = 1502 |
| 18400 | CEFBS_None, // VSSRAN_HU_W = 1503 |
| 18401 | CEFBS_None, // VSSRAN_H_W = 1504 |
| 18402 | CEFBS_None, // VSSRAN_WU_D = 1505 |
| 18403 | CEFBS_None, // VSSRAN_W_D = 1506 |
| 18404 | CEFBS_None, // VSSRARNI_BU_H = 1507 |
| 18405 | CEFBS_None, // VSSRARNI_B_H = 1508 |
| 18406 | CEFBS_None, // VSSRARNI_DU_Q = 1509 |
| 18407 | CEFBS_None, // VSSRARNI_D_Q = 1510 |
| 18408 | CEFBS_None, // VSSRARNI_HU_W = 1511 |
| 18409 | CEFBS_None, // VSSRARNI_H_W = 1512 |
| 18410 | CEFBS_None, // VSSRARNI_WU_D = 1513 |
| 18411 | CEFBS_None, // VSSRARNI_W_D = 1514 |
| 18412 | CEFBS_None, // VSSRARN_BU_H = 1515 |
| 18413 | CEFBS_None, // VSSRARN_B_H = 1516 |
| 18414 | CEFBS_None, // VSSRARN_HU_W = 1517 |
| 18415 | CEFBS_None, // VSSRARN_H_W = 1518 |
| 18416 | CEFBS_None, // VSSRARN_WU_D = 1519 |
| 18417 | CEFBS_None, // VSSRARN_W_D = 1520 |
| 18418 | CEFBS_None, // VSSRLNI_BU_H = 1521 |
| 18419 | CEFBS_None, // VSSRLNI_B_H = 1522 |
| 18420 | CEFBS_None, // VSSRLNI_DU_Q = 1523 |
| 18421 | CEFBS_None, // VSSRLNI_D_Q = 1524 |
| 18422 | CEFBS_None, // VSSRLNI_HU_W = 1525 |
| 18423 | CEFBS_None, // VSSRLNI_H_W = 1526 |
| 18424 | CEFBS_None, // VSSRLNI_WU_D = 1527 |
| 18425 | CEFBS_None, // VSSRLNI_W_D = 1528 |
| 18426 | CEFBS_None, // VSSRLN_BU_H = 1529 |
| 18427 | CEFBS_None, // VSSRLN_B_H = 1530 |
| 18428 | CEFBS_None, // VSSRLN_HU_W = 1531 |
| 18429 | CEFBS_None, // VSSRLN_H_W = 1532 |
| 18430 | CEFBS_None, // VSSRLN_WU_D = 1533 |
| 18431 | CEFBS_None, // VSSRLN_W_D = 1534 |
| 18432 | CEFBS_None, // VSSRLRNI_BU_H = 1535 |
| 18433 | CEFBS_None, // VSSRLRNI_B_H = 1536 |
| 18434 | CEFBS_None, // VSSRLRNI_DU_Q = 1537 |
| 18435 | CEFBS_None, // VSSRLRNI_D_Q = 1538 |
| 18436 | CEFBS_None, // VSSRLRNI_HU_W = 1539 |
| 18437 | CEFBS_None, // VSSRLRNI_H_W = 1540 |
| 18438 | CEFBS_None, // VSSRLRNI_WU_D = 1541 |
| 18439 | CEFBS_None, // VSSRLRNI_W_D = 1542 |
| 18440 | CEFBS_None, // VSSRLRN_BU_H = 1543 |
| 18441 | CEFBS_None, // VSSRLRN_B_H = 1544 |
| 18442 | CEFBS_None, // VSSRLRN_HU_W = 1545 |
| 18443 | CEFBS_None, // VSSRLRN_H_W = 1546 |
| 18444 | CEFBS_None, // VSSRLRN_WU_D = 1547 |
| 18445 | CEFBS_None, // VSSRLRN_W_D = 1548 |
| 18446 | CEFBS_None, // VSSUB_B = 1549 |
| 18447 | CEFBS_None, // VSSUB_BU = 1550 |
| 18448 | CEFBS_None, // VSSUB_D = 1551 |
| 18449 | CEFBS_None, // VSSUB_DU = 1552 |
| 18450 | CEFBS_None, // VSSUB_H = 1553 |
| 18451 | CEFBS_None, // VSSUB_HU = 1554 |
| 18452 | CEFBS_None, // VSSUB_W = 1555 |
| 18453 | CEFBS_None, // VSSUB_WU = 1556 |
| 18454 | CEFBS_None, // VST = 1557 |
| 18455 | CEFBS_None, // VSTELM_B = 1558 |
| 18456 | CEFBS_None, // VSTELM_D = 1559 |
| 18457 | CEFBS_None, // VSTELM_H = 1560 |
| 18458 | CEFBS_None, // VSTELM_W = 1561 |
| 18459 | CEFBS_None, // VSTX = 1562 |
| 18460 | CEFBS_None, // VSUBI_BU = 1563 |
| 18461 | CEFBS_None, // VSUBI_DU = 1564 |
| 18462 | CEFBS_None, // VSUBI_HU = 1565 |
| 18463 | CEFBS_None, // VSUBI_WU = 1566 |
| 18464 | CEFBS_None, // VSUBWEV_D_W = 1567 |
| 18465 | CEFBS_None, // VSUBWEV_D_WU = 1568 |
| 18466 | CEFBS_None, // VSUBWEV_H_B = 1569 |
| 18467 | CEFBS_None, // VSUBWEV_H_BU = 1570 |
| 18468 | CEFBS_None, // VSUBWEV_Q_D = 1571 |
| 18469 | CEFBS_None, // VSUBWEV_Q_DU = 1572 |
| 18470 | CEFBS_None, // VSUBWEV_W_H = 1573 |
| 18471 | CEFBS_None, // VSUBWEV_W_HU = 1574 |
| 18472 | CEFBS_None, // VSUBWOD_D_W = 1575 |
| 18473 | CEFBS_None, // VSUBWOD_D_WU = 1576 |
| 18474 | CEFBS_None, // VSUBWOD_H_B = 1577 |
| 18475 | CEFBS_None, // VSUBWOD_H_BU = 1578 |
| 18476 | CEFBS_None, // VSUBWOD_Q_D = 1579 |
| 18477 | CEFBS_None, // VSUBWOD_Q_DU = 1580 |
| 18478 | CEFBS_None, // VSUBWOD_W_H = 1581 |
| 18479 | CEFBS_None, // VSUBWOD_W_HU = 1582 |
| 18480 | CEFBS_None, // VSUB_B = 1583 |
| 18481 | CEFBS_None, // VSUB_D = 1584 |
| 18482 | CEFBS_None, // VSUB_H = 1585 |
| 18483 | CEFBS_None, // VSUB_Q = 1586 |
| 18484 | CEFBS_None, // VSUB_W = 1587 |
| 18485 | CEFBS_None, // VXORI_B = 1588 |
| 18486 | CEFBS_None, // VXOR_V = 1589 |
| 18487 | CEFBS_None, // X86ADC_B = 1590 |
| 18488 | CEFBS_IsLA64, // X86ADC_D = 1591 |
| 18489 | CEFBS_None, // X86ADC_H = 1592 |
| 18490 | CEFBS_None, // X86ADC_W = 1593 |
| 18491 | CEFBS_None, // X86ADD_B = 1594 |
| 18492 | CEFBS_IsLA64, // X86ADD_D = 1595 |
| 18493 | CEFBS_IsLA64, // X86ADD_DU = 1596 |
| 18494 | CEFBS_None, // X86ADD_H = 1597 |
| 18495 | CEFBS_None, // X86ADD_W = 1598 |
| 18496 | CEFBS_IsLA64, // X86ADD_WU = 1599 |
| 18497 | CEFBS_None, // X86AND_B = 1600 |
| 18498 | CEFBS_IsLA64, // X86AND_D = 1601 |
| 18499 | CEFBS_None, // X86AND_H = 1602 |
| 18500 | CEFBS_None, // X86AND_W = 1603 |
| 18501 | CEFBS_None, // X86CLRTM = 1604 |
| 18502 | CEFBS_None, // X86DECTOP = 1605 |
| 18503 | CEFBS_None, // X86DEC_B = 1606 |
| 18504 | CEFBS_IsLA64, // X86DEC_D = 1607 |
| 18505 | CEFBS_None, // X86DEC_H = 1608 |
| 18506 | CEFBS_None, // X86DEC_W = 1609 |
| 18507 | CEFBS_None, // X86INCTOP = 1610 |
| 18508 | CEFBS_None, // X86INC_B = 1611 |
| 18509 | CEFBS_IsLA64, // X86INC_D = 1612 |
| 18510 | CEFBS_None, // X86INC_H = 1613 |
| 18511 | CEFBS_None, // X86INC_W = 1614 |
| 18512 | CEFBS_None, // X86MFFLAG = 1615 |
| 18513 | CEFBS_None, // X86MFTOP = 1616 |
| 18514 | CEFBS_None, // X86MTFLAG = 1617 |
| 18515 | CEFBS_None, // X86MTTOP = 1618 |
| 18516 | CEFBS_None, // X86MUL_B = 1619 |
| 18517 | CEFBS_None, // X86MUL_BU = 1620 |
| 18518 | CEFBS_IsLA64, // X86MUL_D = 1621 |
| 18519 | CEFBS_IsLA64, // X86MUL_DU = 1622 |
| 18520 | CEFBS_None, // X86MUL_H = 1623 |
| 18521 | CEFBS_None, // X86MUL_HU = 1624 |
| 18522 | CEFBS_None, // X86MUL_W = 1625 |
| 18523 | CEFBS_IsLA64, // X86MUL_WU = 1626 |
| 18524 | CEFBS_None, // X86OR_B = 1627 |
| 18525 | CEFBS_IsLA64, // X86OR_D = 1628 |
| 18526 | CEFBS_None, // X86OR_H = 1629 |
| 18527 | CEFBS_None, // X86OR_W = 1630 |
| 18528 | CEFBS_None, // X86RCLI_B = 1631 |
| 18529 | CEFBS_IsLA64, // X86RCLI_D = 1632 |
| 18530 | CEFBS_None, // X86RCLI_H = 1633 |
| 18531 | CEFBS_None, // X86RCLI_W = 1634 |
| 18532 | CEFBS_None, // X86RCL_B = 1635 |
| 18533 | CEFBS_IsLA64, // X86RCL_D = 1636 |
| 18534 | CEFBS_None, // X86RCL_H = 1637 |
| 18535 | CEFBS_None, // X86RCL_W = 1638 |
| 18536 | CEFBS_None, // X86RCRI_B = 1639 |
| 18537 | CEFBS_IsLA64, // X86RCRI_D = 1640 |
| 18538 | CEFBS_None, // X86RCRI_H = 1641 |
| 18539 | CEFBS_None, // X86RCRI_W = 1642 |
| 18540 | CEFBS_None, // X86RCR_B = 1643 |
| 18541 | CEFBS_IsLA64, // X86RCR_D = 1644 |
| 18542 | CEFBS_None, // X86RCR_H = 1645 |
| 18543 | CEFBS_None, // X86RCR_W = 1646 |
| 18544 | CEFBS_None, // X86ROTLI_B = 1647 |
| 18545 | CEFBS_IsLA64, // X86ROTLI_D = 1648 |
| 18546 | CEFBS_None, // X86ROTLI_H = 1649 |
| 18547 | CEFBS_None, // X86ROTLI_W = 1650 |
| 18548 | CEFBS_None, // X86ROTL_B = 1651 |
| 18549 | CEFBS_IsLA64, // X86ROTL_D = 1652 |
| 18550 | CEFBS_None, // X86ROTL_H = 1653 |
| 18551 | CEFBS_None, // X86ROTL_W = 1654 |
| 18552 | CEFBS_None, // X86ROTRI_B = 1655 |
| 18553 | CEFBS_IsLA64, // X86ROTRI_D = 1656 |
| 18554 | CEFBS_None, // X86ROTRI_H = 1657 |
| 18555 | CEFBS_None, // X86ROTRI_W = 1658 |
| 18556 | CEFBS_None, // X86ROTR_B = 1659 |
| 18557 | CEFBS_IsLA64, // X86ROTR_D = 1660 |
| 18558 | CEFBS_None, // X86ROTR_H = 1661 |
| 18559 | CEFBS_None, // X86ROTR_W = 1662 |
| 18560 | CEFBS_None, // X86SBC_B = 1663 |
| 18561 | CEFBS_IsLA64, // X86SBC_D = 1664 |
| 18562 | CEFBS_None, // X86SBC_H = 1665 |
| 18563 | CEFBS_None, // X86SBC_W = 1666 |
| 18564 | CEFBS_None, // X86SETTAG = 1667 |
| 18565 | CEFBS_None, // X86SETTM = 1668 |
| 18566 | CEFBS_None, // X86SLLI_B = 1669 |
| 18567 | CEFBS_IsLA64, // X86SLLI_D = 1670 |
| 18568 | CEFBS_None, // X86SLLI_H = 1671 |
| 18569 | CEFBS_None, // X86SLLI_W = 1672 |
| 18570 | CEFBS_None, // X86SLL_B = 1673 |
| 18571 | CEFBS_IsLA64, // X86SLL_D = 1674 |
| 18572 | CEFBS_None, // X86SLL_H = 1675 |
| 18573 | CEFBS_None, // X86SLL_W = 1676 |
| 18574 | CEFBS_None, // X86SRAI_B = 1677 |
| 18575 | CEFBS_IsLA64, // X86SRAI_D = 1678 |
| 18576 | CEFBS_None, // X86SRAI_H = 1679 |
| 18577 | CEFBS_None, // X86SRAI_W = 1680 |
| 18578 | CEFBS_None, // X86SRA_B = 1681 |
| 18579 | CEFBS_IsLA64, // X86SRA_D = 1682 |
| 18580 | CEFBS_None, // X86SRA_H = 1683 |
| 18581 | CEFBS_None, // X86SRA_W = 1684 |
| 18582 | CEFBS_None, // X86SRLI_B = 1685 |
| 18583 | CEFBS_IsLA64, // X86SRLI_D = 1686 |
| 18584 | CEFBS_None, // X86SRLI_H = 1687 |
| 18585 | CEFBS_None, // X86SRLI_W = 1688 |
| 18586 | CEFBS_None, // X86SRL_B = 1689 |
| 18587 | CEFBS_IsLA64, // X86SRL_D = 1690 |
| 18588 | CEFBS_None, // X86SRL_H = 1691 |
| 18589 | CEFBS_None, // X86SRL_W = 1692 |
| 18590 | CEFBS_None, // X86SUB_B = 1693 |
| 18591 | CEFBS_IsLA64, // X86SUB_D = 1694 |
| 18592 | CEFBS_IsLA64, // X86SUB_DU = 1695 |
| 18593 | CEFBS_None, // X86SUB_H = 1696 |
| 18594 | CEFBS_None, // X86SUB_W = 1697 |
| 18595 | CEFBS_IsLA64, // X86SUB_WU = 1698 |
| 18596 | CEFBS_None, // X86XOR_B = 1699 |
| 18597 | CEFBS_IsLA64, // X86XOR_D = 1700 |
| 18598 | CEFBS_None, // X86XOR_H = 1701 |
| 18599 | CEFBS_None, // X86XOR_W = 1702 |
| 18600 | CEFBS_None, // XOR = 1703 |
| 18601 | CEFBS_None, // XORI = 1704 |
| 18602 | CEFBS_None, // XVABSD_B = 1705 |
| 18603 | CEFBS_None, // XVABSD_BU = 1706 |
| 18604 | CEFBS_None, // XVABSD_D = 1707 |
| 18605 | CEFBS_None, // XVABSD_DU = 1708 |
| 18606 | CEFBS_None, // XVABSD_H = 1709 |
| 18607 | CEFBS_None, // XVABSD_HU = 1710 |
| 18608 | CEFBS_None, // XVABSD_W = 1711 |
| 18609 | CEFBS_None, // XVABSD_WU = 1712 |
| 18610 | CEFBS_None, // XVADDA_B = 1713 |
| 18611 | CEFBS_None, // XVADDA_D = 1714 |
| 18612 | CEFBS_None, // XVADDA_H = 1715 |
| 18613 | CEFBS_None, // XVADDA_W = 1716 |
| 18614 | CEFBS_None, // XVADDI_BU = 1717 |
| 18615 | CEFBS_None, // XVADDI_DU = 1718 |
| 18616 | CEFBS_None, // XVADDI_HU = 1719 |
| 18617 | CEFBS_None, // XVADDI_WU = 1720 |
| 18618 | CEFBS_None, // XVADDWEV_D_W = 1721 |
| 18619 | CEFBS_None, // XVADDWEV_D_WU = 1722 |
| 18620 | CEFBS_None, // XVADDWEV_D_WU_W = 1723 |
| 18621 | CEFBS_None, // XVADDWEV_H_B = 1724 |
| 18622 | CEFBS_None, // XVADDWEV_H_BU = 1725 |
| 18623 | CEFBS_None, // XVADDWEV_H_BU_B = 1726 |
| 18624 | CEFBS_None, // XVADDWEV_Q_D = 1727 |
| 18625 | CEFBS_None, // XVADDWEV_Q_DU = 1728 |
| 18626 | CEFBS_None, // XVADDWEV_Q_DU_D = 1729 |
| 18627 | CEFBS_None, // XVADDWEV_W_H = 1730 |
| 18628 | CEFBS_None, // XVADDWEV_W_HU = 1731 |
| 18629 | CEFBS_None, // XVADDWEV_W_HU_H = 1732 |
| 18630 | CEFBS_None, // XVADDWOD_D_W = 1733 |
| 18631 | CEFBS_None, // XVADDWOD_D_WU = 1734 |
| 18632 | CEFBS_None, // XVADDWOD_D_WU_W = 1735 |
| 18633 | CEFBS_None, // XVADDWOD_H_B = 1736 |
| 18634 | CEFBS_None, // XVADDWOD_H_BU = 1737 |
| 18635 | CEFBS_None, // XVADDWOD_H_BU_B = 1738 |
| 18636 | CEFBS_None, // XVADDWOD_Q_D = 1739 |
| 18637 | CEFBS_None, // XVADDWOD_Q_DU = 1740 |
| 18638 | CEFBS_None, // XVADDWOD_Q_DU_D = 1741 |
| 18639 | CEFBS_None, // XVADDWOD_W_H = 1742 |
| 18640 | CEFBS_None, // XVADDWOD_W_HU = 1743 |
| 18641 | CEFBS_None, // XVADDWOD_W_HU_H = 1744 |
| 18642 | CEFBS_None, // XVADD_B = 1745 |
| 18643 | CEFBS_None, // XVADD_D = 1746 |
| 18644 | CEFBS_None, // XVADD_H = 1747 |
| 18645 | CEFBS_None, // XVADD_Q = 1748 |
| 18646 | CEFBS_None, // XVADD_W = 1749 |
| 18647 | CEFBS_None, // XVANDI_B = 1750 |
| 18648 | CEFBS_None, // XVANDN_V = 1751 |
| 18649 | CEFBS_None, // XVAND_V = 1752 |
| 18650 | CEFBS_None, // XVAVGR_B = 1753 |
| 18651 | CEFBS_None, // XVAVGR_BU = 1754 |
| 18652 | CEFBS_None, // XVAVGR_D = 1755 |
| 18653 | CEFBS_None, // XVAVGR_DU = 1756 |
| 18654 | CEFBS_None, // XVAVGR_H = 1757 |
| 18655 | CEFBS_None, // XVAVGR_HU = 1758 |
| 18656 | CEFBS_None, // XVAVGR_W = 1759 |
| 18657 | CEFBS_None, // XVAVGR_WU = 1760 |
| 18658 | CEFBS_None, // XVAVG_B = 1761 |
| 18659 | CEFBS_None, // XVAVG_BU = 1762 |
| 18660 | CEFBS_None, // XVAVG_D = 1763 |
| 18661 | CEFBS_None, // XVAVG_DU = 1764 |
| 18662 | CEFBS_None, // XVAVG_H = 1765 |
| 18663 | CEFBS_None, // XVAVG_HU = 1766 |
| 18664 | CEFBS_None, // XVAVG_W = 1767 |
| 18665 | CEFBS_None, // XVAVG_WU = 1768 |
| 18666 | CEFBS_None, // XVBITCLRI_B = 1769 |
| 18667 | CEFBS_None, // XVBITCLRI_D = 1770 |
| 18668 | CEFBS_None, // XVBITCLRI_H = 1771 |
| 18669 | CEFBS_None, // XVBITCLRI_W = 1772 |
| 18670 | CEFBS_None, // XVBITCLR_B = 1773 |
| 18671 | CEFBS_None, // XVBITCLR_D = 1774 |
| 18672 | CEFBS_None, // XVBITCLR_H = 1775 |
| 18673 | CEFBS_None, // XVBITCLR_W = 1776 |
| 18674 | CEFBS_None, // XVBITREVI_B = 1777 |
| 18675 | CEFBS_None, // XVBITREVI_D = 1778 |
| 18676 | CEFBS_None, // XVBITREVI_H = 1779 |
| 18677 | CEFBS_None, // XVBITREVI_W = 1780 |
| 18678 | CEFBS_None, // XVBITREV_B = 1781 |
| 18679 | CEFBS_None, // XVBITREV_D = 1782 |
| 18680 | CEFBS_None, // XVBITREV_H = 1783 |
| 18681 | CEFBS_None, // XVBITREV_W = 1784 |
| 18682 | CEFBS_None, // XVBITSELI_B = 1785 |
| 18683 | CEFBS_None, // XVBITSEL_V = 1786 |
| 18684 | CEFBS_None, // XVBITSETI_B = 1787 |
| 18685 | CEFBS_None, // XVBITSETI_D = 1788 |
| 18686 | CEFBS_None, // XVBITSETI_H = 1789 |
| 18687 | CEFBS_None, // XVBITSETI_W = 1790 |
| 18688 | CEFBS_None, // XVBITSET_B = 1791 |
| 18689 | CEFBS_None, // XVBITSET_D = 1792 |
| 18690 | CEFBS_None, // XVBITSET_H = 1793 |
| 18691 | CEFBS_None, // XVBITSET_W = 1794 |
| 18692 | CEFBS_None, // XVBSLL_V = 1795 |
| 18693 | CEFBS_None, // XVBSRL_V = 1796 |
| 18694 | CEFBS_None, // XVCLO_B = 1797 |
| 18695 | CEFBS_None, // XVCLO_D = 1798 |
| 18696 | CEFBS_None, // XVCLO_H = 1799 |
| 18697 | CEFBS_None, // XVCLO_W = 1800 |
| 18698 | CEFBS_None, // XVCLZ_B = 1801 |
| 18699 | CEFBS_None, // XVCLZ_D = 1802 |
| 18700 | CEFBS_None, // XVCLZ_H = 1803 |
| 18701 | CEFBS_None, // XVCLZ_W = 1804 |
| 18702 | CEFBS_None, // XVDIV_B = 1805 |
| 18703 | CEFBS_None, // XVDIV_BU = 1806 |
| 18704 | CEFBS_None, // XVDIV_D = 1807 |
| 18705 | CEFBS_None, // XVDIV_DU = 1808 |
| 18706 | CEFBS_None, // XVDIV_H = 1809 |
| 18707 | CEFBS_None, // XVDIV_HU = 1810 |
| 18708 | CEFBS_None, // XVDIV_W = 1811 |
| 18709 | CEFBS_None, // XVDIV_WU = 1812 |
| 18710 | CEFBS_None, // XVEXTH_DU_WU = 1813 |
| 18711 | CEFBS_None, // XVEXTH_D_W = 1814 |
| 18712 | CEFBS_None, // XVEXTH_HU_BU = 1815 |
| 18713 | CEFBS_None, // XVEXTH_H_B = 1816 |
| 18714 | CEFBS_None, // XVEXTH_QU_DU = 1817 |
| 18715 | CEFBS_None, // XVEXTH_Q_D = 1818 |
| 18716 | CEFBS_None, // XVEXTH_WU_HU = 1819 |
| 18717 | CEFBS_None, // XVEXTH_W_H = 1820 |
| 18718 | CEFBS_None, // XVEXTL_QU_DU = 1821 |
| 18719 | CEFBS_None, // XVEXTL_Q_D = 1822 |
| 18720 | CEFBS_None, // XVEXTRINS_B = 1823 |
| 18721 | CEFBS_None, // XVEXTRINS_D = 1824 |
| 18722 | CEFBS_None, // XVEXTRINS_H = 1825 |
| 18723 | CEFBS_None, // XVEXTRINS_W = 1826 |
| 18724 | CEFBS_None, // XVFADD_D = 1827 |
| 18725 | CEFBS_None, // XVFADD_S = 1828 |
| 18726 | CEFBS_None, // XVFCLASS_D = 1829 |
| 18727 | CEFBS_None, // XVFCLASS_S = 1830 |
| 18728 | CEFBS_None, // XVFCMP_CAF_D = 1831 |
| 18729 | CEFBS_None, // XVFCMP_CAF_S = 1832 |
| 18730 | CEFBS_None, // XVFCMP_CEQ_D = 1833 |
| 18731 | CEFBS_None, // XVFCMP_CEQ_S = 1834 |
| 18732 | CEFBS_None, // XVFCMP_CLE_D = 1835 |
| 18733 | CEFBS_None, // XVFCMP_CLE_S = 1836 |
| 18734 | CEFBS_None, // XVFCMP_CLT_D = 1837 |
| 18735 | CEFBS_None, // XVFCMP_CLT_S = 1838 |
| 18736 | CEFBS_None, // XVFCMP_CNE_D = 1839 |
| 18737 | CEFBS_None, // XVFCMP_CNE_S = 1840 |
| 18738 | CEFBS_None, // XVFCMP_COR_D = 1841 |
| 18739 | CEFBS_None, // XVFCMP_COR_S = 1842 |
| 18740 | CEFBS_None, // XVFCMP_CUEQ_D = 1843 |
| 18741 | CEFBS_None, // XVFCMP_CUEQ_S = 1844 |
| 18742 | CEFBS_None, // XVFCMP_CULE_D = 1845 |
| 18743 | CEFBS_None, // XVFCMP_CULE_S = 1846 |
| 18744 | CEFBS_None, // XVFCMP_CULT_D = 1847 |
| 18745 | CEFBS_None, // XVFCMP_CULT_S = 1848 |
| 18746 | CEFBS_None, // XVFCMP_CUNE_D = 1849 |
| 18747 | CEFBS_None, // XVFCMP_CUNE_S = 1850 |
| 18748 | CEFBS_None, // XVFCMP_CUN_D = 1851 |
| 18749 | CEFBS_None, // XVFCMP_CUN_S = 1852 |
| 18750 | CEFBS_None, // XVFCMP_SAF_D = 1853 |
| 18751 | CEFBS_None, // XVFCMP_SAF_S = 1854 |
| 18752 | CEFBS_None, // XVFCMP_SEQ_D = 1855 |
| 18753 | CEFBS_None, // XVFCMP_SEQ_S = 1856 |
| 18754 | CEFBS_None, // XVFCMP_SLE_D = 1857 |
| 18755 | CEFBS_None, // XVFCMP_SLE_S = 1858 |
| 18756 | CEFBS_None, // XVFCMP_SLT_D = 1859 |
| 18757 | CEFBS_None, // XVFCMP_SLT_S = 1860 |
| 18758 | CEFBS_None, // XVFCMP_SNE_D = 1861 |
| 18759 | CEFBS_None, // XVFCMP_SNE_S = 1862 |
| 18760 | CEFBS_None, // XVFCMP_SOR_D = 1863 |
| 18761 | CEFBS_None, // XVFCMP_SOR_S = 1864 |
| 18762 | CEFBS_None, // XVFCMP_SUEQ_D = 1865 |
| 18763 | CEFBS_None, // XVFCMP_SUEQ_S = 1866 |
| 18764 | CEFBS_None, // XVFCMP_SULE_D = 1867 |
| 18765 | CEFBS_None, // XVFCMP_SULE_S = 1868 |
| 18766 | CEFBS_None, // XVFCMP_SULT_D = 1869 |
| 18767 | CEFBS_None, // XVFCMP_SULT_S = 1870 |
| 18768 | CEFBS_None, // XVFCMP_SUNE_D = 1871 |
| 18769 | CEFBS_None, // XVFCMP_SUNE_S = 1872 |
| 18770 | CEFBS_None, // XVFCMP_SUN_D = 1873 |
| 18771 | CEFBS_None, // XVFCMP_SUN_S = 1874 |
| 18772 | CEFBS_None, // XVFCVTH_D_S = 1875 |
| 18773 | CEFBS_None, // XVFCVTH_S_H = 1876 |
| 18774 | CEFBS_None, // XVFCVTL_D_S = 1877 |
| 18775 | CEFBS_None, // XVFCVTL_S_H = 1878 |
| 18776 | CEFBS_None, // XVFCVT_H_S = 1879 |
| 18777 | CEFBS_None, // XVFCVT_S_D = 1880 |
| 18778 | CEFBS_None, // XVFDIV_D = 1881 |
| 18779 | CEFBS_None, // XVFDIV_S = 1882 |
| 18780 | CEFBS_None, // XVFFINTH_D_W = 1883 |
| 18781 | CEFBS_None, // XVFFINTL_D_W = 1884 |
| 18782 | CEFBS_None, // XVFFINT_D_L = 1885 |
| 18783 | CEFBS_None, // XVFFINT_D_LU = 1886 |
| 18784 | CEFBS_None, // XVFFINT_S_L = 1887 |
| 18785 | CEFBS_None, // XVFFINT_S_W = 1888 |
| 18786 | CEFBS_None, // XVFFINT_S_WU = 1889 |
| 18787 | CEFBS_None, // XVFLOGB_D = 1890 |
| 18788 | CEFBS_None, // XVFLOGB_S = 1891 |
| 18789 | CEFBS_None, // XVFMADD_D = 1892 |
| 18790 | CEFBS_None, // XVFMADD_S = 1893 |
| 18791 | CEFBS_None, // XVFMAXA_D = 1894 |
| 18792 | CEFBS_None, // XVFMAXA_S = 1895 |
| 18793 | CEFBS_None, // XVFMAX_D = 1896 |
| 18794 | CEFBS_None, // XVFMAX_S = 1897 |
| 18795 | CEFBS_None, // XVFMINA_D = 1898 |
| 18796 | CEFBS_None, // XVFMINA_S = 1899 |
| 18797 | CEFBS_None, // XVFMIN_D = 1900 |
| 18798 | CEFBS_None, // XVFMIN_S = 1901 |
| 18799 | CEFBS_None, // XVFMSUB_D = 1902 |
| 18800 | CEFBS_None, // XVFMSUB_S = 1903 |
| 18801 | CEFBS_None, // XVFMUL_D = 1904 |
| 18802 | CEFBS_None, // XVFMUL_S = 1905 |
| 18803 | CEFBS_None, // XVFNMADD_D = 1906 |
| 18804 | CEFBS_None, // XVFNMADD_S = 1907 |
| 18805 | CEFBS_None, // XVFNMSUB_D = 1908 |
| 18806 | CEFBS_None, // XVFNMSUB_S = 1909 |
| 18807 | CEFBS_None, // XVFRECIPE_D = 1910 |
| 18808 | CEFBS_None, // XVFRECIPE_S = 1911 |
| 18809 | CEFBS_None, // XVFRECIP_D = 1912 |
| 18810 | CEFBS_None, // XVFRECIP_S = 1913 |
| 18811 | CEFBS_None, // XVFRINTRM_D = 1914 |
| 18812 | CEFBS_None, // XVFRINTRM_S = 1915 |
| 18813 | CEFBS_None, // XVFRINTRNE_D = 1916 |
| 18814 | CEFBS_None, // XVFRINTRNE_S = 1917 |
| 18815 | CEFBS_None, // XVFRINTRP_D = 1918 |
| 18816 | CEFBS_None, // XVFRINTRP_S = 1919 |
| 18817 | CEFBS_None, // XVFRINTRZ_D = 1920 |
| 18818 | CEFBS_None, // XVFRINTRZ_S = 1921 |
| 18819 | CEFBS_None, // XVFRINT_D = 1922 |
| 18820 | CEFBS_None, // XVFRINT_S = 1923 |
| 18821 | CEFBS_None, // XVFRSQRTE_D = 1924 |
| 18822 | CEFBS_None, // XVFRSQRTE_S = 1925 |
| 18823 | CEFBS_None, // XVFRSQRT_D = 1926 |
| 18824 | CEFBS_None, // XVFRSQRT_S = 1927 |
| 18825 | CEFBS_None, // XVFRSTPI_B = 1928 |
| 18826 | CEFBS_None, // XVFRSTPI_H = 1929 |
| 18827 | CEFBS_None, // XVFRSTP_B = 1930 |
| 18828 | CEFBS_None, // XVFRSTP_H = 1931 |
| 18829 | CEFBS_None, // XVFSQRT_D = 1932 |
| 18830 | CEFBS_None, // XVFSQRT_S = 1933 |
| 18831 | CEFBS_None, // XVFSUB_D = 1934 |
| 18832 | CEFBS_None, // XVFSUB_S = 1935 |
| 18833 | CEFBS_None, // XVFTINTH_L_S = 1936 |
| 18834 | CEFBS_None, // XVFTINTL_L_S = 1937 |
| 18835 | CEFBS_None, // XVFTINTRMH_L_S = 1938 |
| 18836 | CEFBS_None, // XVFTINTRML_L_S = 1939 |
| 18837 | CEFBS_None, // XVFTINTRM_L_D = 1940 |
| 18838 | CEFBS_None, // XVFTINTRM_W_D = 1941 |
| 18839 | CEFBS_None, // XVFTINTRM_W_S = 1942 |
| 18840 | CEFBS_None, // XVFTINTRNEH_L_S = 1943 |
| 18841 | CEFBS_None, // XVFTINTRNEL_L_S = 1944 |
| 18842 | CEFBS_None, // XVFTINTRNE_L_D = 1945 |
| 18843 | CEFBS_None, // XVFTINTRNE_W_D = 1946 |
| 18844 | CEFBS_None, // XVFTINTRNE_W_S = 1947 |
| 18845 | CEFBS_None, // XVFTINTRPH_L_S = 1948 |
| 18846 | CEFBS_None, // XVFTINTRPL_L_S = 1949 |
| 18847 | CEFBS_None, // XVFTINTRP_L_D = 1950 |
| 18848 | CEFBS_None, // XVFTINTRP_W_D = 1951 |
| 18849 | CEFBS_None, // XVFTINTRP_W_S = 1952 |
| 18850 | CEFBS_None, // XVFTINTRZH_L_S = 1953 |
| 18851 | CEFBS_None, // XVFTINTRZL_L_S = 1954 |
| 18852 | CEFBS_None, // XVFTINTRZ_LU_D = 1955 |
| 18853 | CEFBS_None, // XVFTINTRZ_L_D = 1956 |
| 18854 | CEFBS_None, // XVFTINTRZ_WU_S = 1957 |
| 18855 | CEFBS_None, // XVFTINTRZ_W_D = 1958 |
| 18856 | CEFBS_None, // XVFTINTRZ_W_S = 1959 |
| 18857 | CEFBS_None, // XVFTINT_LU_D = 1960 |
| 18858 | CEFBS_None, // XVFTINT_L_D = 1961 |
| 18859 | CEFBS_None, // XVFTINT_WU_S = 1962 |
| 18860 | CEFBS_None, // XVFTINT_W_D = 1963 |
| 18861 | CEFBS_None, // XVFTINT_W_S = 1964 |
| 18862 | CEFBS_None, // XVHADDW_DU_WU = 1965 |
| 18863 | CEFBS_None, // XVHADDW_D_W = 1966 |
| 18864 | CEFBS_None, // XVHADDW_HU_BU = 1967 |
| 18865 | CEFBS_None, // XVHADDW_H_B = 1968 |
| 18866 | CEFBS_None, // XVHADDW_QU_DU = 1969 |
| 18867 | CEFBS_None, // XVHADDW_Q_D = 1970 |
| 18868 | CEFBS_None, // XVHADDW_WU_HU = 1971 |
| 18869 | CEFBS_None, // XVHADDW_W_H = 1972 |
| 18870 | CEFBS_None, // XVHSELI_D = 1973 |
| 18871 | CEFBS_None, // XVHSUBW_DU_WU = 1974 |
| 18872 | CEFBS_None, // XVHSUBW_D_W = 1975 |
| 18873 | CEFBS_None, // XVHSUBW_HU_BU = 1976 |
| 18874 | CEFBS_None, // XVHSUBW_H_B = 1977 |
| 18875 | CEFBS_None, // XVHSUBW_QU_DU = 1978 |
| 18876 | CEFBS_None, // XVHSUBW_Q_D = 1979 |
| 18877 | CEFBS_None, // XVHSUBW_WU_HU = 1980 |
| 18878 | CEFBS_None, // XVHSUBW_W_H = 1981 |
| 18879 | CEFBS_None, // XVILVH_B = 1982 |
| 18880 | CEFBS_None, // XVILVH_D = 1983 |
| 18881 | CEFBS_None, // XVILVH_H = 1984 |
| 18882 | CEFBS_None, // XVILVH_W = 1985 |
| 18883 | CEFBS_None, // XVILVL_B = 1986 |
| 18884 | CEFBS_None, // XVILVL_D = 1987 |
| 18885 | CEFBS_None, // XVILVL_H = 1988 |
| 18886 | CEFBS_None, // XVILVL_W = 1989 |
| 18887 | CEFBS_None, // XVINSGR2VR_D = 1990 |
| 18888 | CEFBS_None, // XVINSGR2VR_W = 1991 |
| 18889 | CEFBS_None, // XVINSVE0_D = 1992 |
| 18890 | CEFBS_None, // XVINSVE0_W = 1993 |
| 18891 | CEFBS_None, // XVLD = 1994 |
| 18892 | CEFBS_None, // XVLDI = 1995 |
| 18893 | CEFBS_None, // XVLDREPL_B = 1996 |
| 18894 | CEFBS_None, // XVLDREPL_D = 1997 |
| 18895 | CEFBS_None, // XVLDREPL_H = 1998 |
| 18896 | CEFBS_None, // XVLDREPL_W = 1999 |
| 18897 | CEFBS_None, // XVLDX = 2000 |
| 18898 | CEFBS_None, // XVMADDWEV_D_W = 2001 |
| 18899 | CEFBS_None, // XVMADDWEV_D_WU = 2002 |
| 18900 | CEFBS_None, // XVMADDWEV_D_WU_W = 2003 |
| 18901 | CEFBS_None, // XVMADDWEV_H_B = 2004 |
| 18902 | CEFBS_None, // XVMADDWEV_H_BU = 2005 |
| 18903 | CEFBS_None, // XVMADDWEV_H_BU_B = 2006 |
| 18904 | CEFBS_None, // XVMADDWEV_Q_D = 2007 |
| 18905 | CEFBS_None, // XVMADDWEV_Q_DU = 2008 |
| 18906 | CEFBS_None, // XVMADDWEV_Q_DU_D = 2009 |
| 18907 | CEFBS_None, // XVMADDWEV_W_H = 2010 |
| 18908 | CEFBS_None, // XVMADDWEV_W_HU = 2011 |
| 18909 | CEFBS_None, // XVMADDWEV_W_HU_H = 2012 |
| 18910 | CEFBS_None, // XVMADDWOD_D_W = 2013 |
| 18911 | CEFBS_None, // XVMADDWOD_D_WU = 2014 |
| 18912 | CEFBS_None, // XVMADDWOD_D_WU_W = 2015 |
| 18913 | CEFBS_None, // XVMADDWOD_H_B = 2016 |
| 18914 | CEFBS_None, // XVMADDWOD_H_BU = 2017 |
| 18915 | CEFBS_None, // XVMADDWOD_H_BU_B = 2018 |
| 18916 | CEFBS_None, // XVMADDWOD_Q_D = 2019 |
| 18917 | CEFBS_None, // XVMADDWOD_Q_DU = 2020 |
| 18918 | CEFBS_None, // XVMADDWOD_Q_DU_D = 2021 |
| 18919 | CEFBS_None, // XVMADDWOD_W_H = 2022 |
| 18920 | CEFBS_None, // XVMADDWOD_W_HU = 2023 |
| 18921 | CEFBS_None, // XVMADDWOD_W_HU_H = 2024 |
| 18922 | CEFBS_None, // XVMADD_B = 2025 |
| 18923 | CEFBS_None, // XVMADD_D = 2026 |
| 18924 | CEFBS_None, // XVMADD_H = 2027 |
| 18925 | CEFBS_None, // XVMADD_W = 2028 |
| 18926 | CEFBS_None, // XVMAXI_B = 2029 |
| 18927 | CEFBS_None, // XVMAXI_BU = 2030 |
| 18928 | CEFBS_None, // XVMAXI_D = 2031 |
| 18929 | CEFBS_None, // XVMAXI_DU = 2032 |
| 18930 | CEFBS_None, // XVMAXI_H = 2033 |
| 18931 | CEFBS_None, // XVMAXI_HU = 2034 |
| 18932 | CEFBS_None, // XVMAXI_W = 2035 |
| 18933 | CEFBS_None, // XVMAXI_WU = 2036 |
| 18934 | CEFBS_None, // XVMAX_B = 2037 |
| 18935 | CEFBS_None, // XVMAX_BU = 2038 |
| 18936 | CEFBS_None, // XVMAX_D = 2039 |
| 18937 | CEFBS_None, // XVMAX_DU = 2040 |
| 18938 | CEFBS_None, // XVMAX_H = 2041 |
| 18939 | CEFBS_None, // XVMAX_HU = 2042 |
| 18940 | CEFBS_None, // XVMAX_W = 2043 |
| 18941 | CEFBS_None, // XVMAX_WU = 2044 |
| 18942 | CEFBS_None, // XVMINI_B = 2045 |
| 18943 | CEFBS_None, // XVMINI_BU = 2046 |
| 18944 | CEFBS_None, // XVMINI_D = 2047 |
| 18945 | CEFBS_None, // XVMINI_DU = 2048 |
| 18946 | CEFBS_None, // XVMINI_H = 2049 |
| 18947 | CEFBS_None, // XVMINI_HU = 2050 |
| 18948 | CEFBS_None, // XVMINI_W = 2051 |
| 18949 | CEFBS_None, // XVMINI_WU = 2052 |
| 18950 | CEFBS_None, // XVMIN_B = 2053 |
| 18951 | CEFBS_None, // XVMIN_BU = 2054 |
| 18952 | CEFBS_None, // XVMIN_D = 2055 |
| 18953 | CEFBS_None, // XVMIN_DU = 2056 |
| 18954 | CEFBS_None, // XVMIN_H = 2057 |
| 18955 | CEFBS_None, // XVMIN_HU = 2058 |
| 18956 | CEFBS_None, // XVMIN_W = 2059 |
| 18957 | CEFBS_None, // XVMIN_WU = 2060 |
| 18958 | CEFBS_None, // XVMOD_B = 2061 |
| 18959 | CEFBS_None, // XVMOD_BU = 2062 |
| 18960 | CEFBS_None, // XVMOD_D = 2063 |
| 18961 | CEFBS_None, // XVMOD_DU = 2064 |
| 18962 | CEFBS_None, // XVMOD_H = 2065 |
| 18963 | CEFBS_None, // XVMOD_HU = 2066 |
| 18964 | CEFBS_None, // XVMOD_W = 2067 |
| 18965 | CEFBS_None, // XVMOD_WU = 2068 |
| 18966 | CEFBS_None, // XVMSKGEZ_B = 2069 |
| 18967 | CEFBS_None, // XVMSKLTZ_B = 2070 |
| 18968 | CEFBS_None, // XVMSKLTZ_D = 2071 |
| 18969 | CEFBS_None, // XVMSKLTZ_H = 2072 |
| 18970 | CEFBS_None, // XVMSKLTZ_W = 2073 |
| 18971 | CEFBS_None, // XVMSKNZ_B = 2074 |
| 18972 | CEFBS_None, // XVMSUB_B = 2075 |
| 18973 | CEFBS_None, // XVMSUB_D = 2076 |
| 18974 | CEFBS_None, // XVMSUB_H = 2077 |
| 18975 | CEFBS_None, // XVMSUB_W = 2078 |
| 18976 | CEFBS_None, // XVMUH_B = 2079 |
| 18977 | CEFBS_None, // XVMUH_BU = 2080 |
| 18978 | CEFBS_None, // XVMUH_D = 2081 |
| 18979 | CEFBS_None, // XVMUH_DU = 2082 |
| 18980 | CEFBS_None, // XVMUH_H = 2083 |
| 18981 | CEFBS_None, // XVMUH_HU = 2084 |
| 18982 | CEFBS_None, // XVMUH_W = 2085 |
| 18983 | CEFBS_None, // XVMUH_WU = 2086 |
| 18984 | CEFBS_None, // XVMULWEV_D_W = 2087 |
| 18985 | CEFBS_None, // XVMULWEV_D_WU = 2088 |
| 18986 | CEFBS_None, // XVMULWEV_D_WU_W = 2089 |
| 18987 | CEFBS_None, // XVMULWEV_H_B = 2090 |
| 18988 | CEFBS_None, // XVMULWEV_H_BU = 2091 |
| 18989 | CEFBS_None, // XVMULWEV_H_BU_B = 2092 |
| 18990 | CEFBS_None, // XVMULWEV_Q_D = 2093 |
| 18991 | CEFBS_None, // XVMULWEV_Q_DU = 2094 |
| 18992 | CEFBS_None, // XVMULWEV_Q_DU_D = 2095 |
| 18993 | CEFBS_None, // XVMULWEV_W_H = 2096 |
| 18994 | CEFBS_None, // XVMULWEV_W_HU = 2097 |
| 18995 | CEFBS_None, // XVMULWEV_W_HU_H = 2098 |
| 18996 | CEFBS_None, // XVMULWOD_D_W = 2099 |
| 18997 | CEFBS_None, // XVMULWOD_D_WU = 2100 |
| 18998 | CEFBS_None, // XVMULWOD_D_WU_W = 2101 |
| 18999 | CEFBS_None, // XVMULWOD_H_B = 2102 |
| 19000 | CEFBS_None, // XVMULWOD_H_BU = 2103 |
| 19001 | CEFBS_None, // XVMULWOD_H_BU_B = 2104 |
| 19002 | CEFBS_None, // XVMULWOD_Q_D = 2105 |
| 19003 | CEFBS_None, // XVMULWOD_Q_DU = 2106 |
| 19004 | CEFBS_None, // XVMULWOD_Q_DU_D = 2107 |
| 19005 | CEFBS_None, // XVMULWOD_W_H = 2108 |
| 19006 | CEFBS_None, // XVMULWOD_W_HU = 2109 |
| 19007 | CEFBS_None, // XVMULWOD_W_HU_H = 2110 |
| 19008 | CEFBS_None, // XVMUL_B = 2111 |
| 19009 | CEFBS_None, // XVMUL_D = 2112 |
| 19010 | CEFBS_None, // XVMUL_H = 2113 |
| 19011 | CEFBS_None, // XVMUL_W = 2114 |
| 19012 | CEFBS_None, // XVNEG_B = 2115 |
| 19013 | CEFBS_None, // XVNEG_D = 2116 |
| 19014 | CEFBS_None, // XVNEG_H = 2117 |
| 19015 | CEFBS_None, // XVNEG_W = 2118 |
| 19016 | CEFBS_None, // XVNORI_B = 2119 |
| 19017 | CEFBS_None, // XVNOR_V = 2120 |
| 19018 | CEFBS_None, // XVORI_B = 2121 |
| 19019 | CEFBS_None, // XVORN_V = 2122 |
| 19020 | CEFBS_None, // XVOR_V = 2123 |
| 19021 | CEFBS_None, // XVPACKEV_B = 2124 |
| 19022 | CEFBS_None, // XVPACKEV_D = 2125 |
| 19023 | CEFBS_None, // XVPACKEV_H = 2126 |
| 19024 | CEFBS_None, // XVPACKEV_W = 2127 |
| 19025 | CEFBS_None, // XVPACKOD_B = 2128 |
| 19026 | CEFBS_None, // XVPACKOD_D = 2129 |
| 19027 | CEFBS_None, // XVPACKOD_H = 2130 |
| 19028 | CEFBS_None, // XVPACKOD_W = 2131 |
| 19029 | CEFBS_None, // XVPCNT_B = 2132 |
| 19030 | CEFBS_None, // XVPCNT_D = 2133 |
| 19031 | CEFBS_None, // XVPCNT_H = 2134 |
| 19032 | CEFBS_None, // XVPCNT_W = 2135 |
| 19033 | CEFBS_None, // XVPERMI_D = 2136 |
| 19034 | CEFBS_None, // XVPERMI_Q = 2137 |
| 19035 | CEFBS_None, // XVPERMI_W = 2138 |
| 19036 | CEFBS_None, // XVPERM_W = 2139 |
| 19037 | CEFBS_None, // XVPICKEV_B = 2140 |
| 19038 | CEFBS_None, // XVPICKEV_D = 2141 |
| 19039 | CEFBS_None, // XVPICKEV_H = 2142 |
| 19040 | CEFBS_None, // XVPICKEV_W = 2143 |
| 19041 | CEFBS_None, // XVPICKOD_B = 2144 |
| 19042 | CEFBS_None, // XVPICKOD_D = 2145 |
| 19043 | CEFBS_None, // XVPICKOD_H = 2146 |
| 19044 | CEFBS_None, // XVPICKOD_W = 2147 |
| 19045 | CEFBS_None, // XVPICKVE2GR_D = 2148 |
| 19046 | CEFBS_None, // XVPICKVE2GR_DU = 2149 |
| 19047 | CEFBS_None, // XVPICKVE2GR_W = 2150 |
| 19048 | CEFBS_None, // XVPICKVE2GR_WU = 2151 |
| 19049 | CEFBS_None, // XVPICKVE_D = 2152 |
| 19050 | CEFBS_None, // XVPICKVE_W = 2153 |
| 19051 | CEFBS_None, // XVREPL128VEI_B = 2154 |
| 19052 | CEFBS_None, // XVREPL128VEI_D = 2155 |
| 19053 | CEFBS_None, // XVREPL128VEI_H = 2156 |
| 19054 | CEFBS_None, // XVREPL128VEI_W = 2157 |
| 19055 | CEFBS_None, // XVREPLGR2VR_B = 2158 |
| 19056 | CEFBS_None, // XVREPLGR2VR_D = 2159 |
| 19057 | CEFBS_None, // XVREPLGR2VR_H = 2160 |
| 19058 | CEFBS_None, // XVREPLGR2VR_W = 2161 |
| 19059 | CEFBS_None, // XVREPLVE0_B = 2162 |
| 19060 | CEFBS_None, // XVREPLVE0_D = 2163 |
| 19061 | CEFBS_None, // XVREPLVE0_H = 2164 |
| 19062 | CEFBS_None, // XVREPLVE0_Q = 2165 |
| 19063 | CEFBS_None, // XVREPLVE0_W = 2166 |
| 19064 | CEFBS_None, // XVREPLVE_B = 2167 |
| 19065 | CEFBS_None, // XVREPLVE_D = 2168 |
| 19066 | CEFBS_None, // XVREPLVE_H = 2169 |
| 19067 | CEFBS_None, // XVREPLVE_W = 2170 |
| 19068 | CEFBS_None, // XVROTRI_B = 2171 |
| 19069 | CEFBS_None, // XVROTRI_D = 2172 |
| 19070 | CEFBS_None, // XVROTRI_H = 2173 |
| 19071 | CEFBS_None, // XVROTRI_W = 2174 |
| 19072 | CEFBS_None, // XVROTR_B = 2175 |
| 19073 | CEFBS_None, // XVROTR_D = 2176 |
| 19074 | CEFBS_None, // XVROTR_H = 2177 |
| 19075 | CEFBS_None, // XVROTR_W = 2178 |
| 19076 | CEFBS_None, // XVSADD_B = 2179 |
| 19077 | CEFBS_None, // XVSADD_BU = 2180 |
| 19078 | CEFBS_None, // XVSADD_D = 2181 |
| 19079 | CEFBS_None, // XVSADD_DU = 2182 |
| 19080 | CEFBS_None, // XVSADD_H = 2183 |
| 19081 | CEFBS_None, // XVSADD_HU = 2184 |
| 19082 | CEFBS_None, // XVSADD_W = 2185 |
| 19083 | CEFBS_None, // XVSADD_WU = 2186 |
| 19084 | CEFBS_None, // XVSAT_B = 2187 |
| 19085 | CEFBS_None, // XVSAT_BU = 2188 |
| 19086 | CEFBS_None, // XVSAT_D = 2189 |
| 19087 | CEFBS_None, // XVSAT_DU = 2190 |
| 19088 | CEFBS_None, // XVSAT_H = 2191 |
| 19089 | CEFBS_None, // XVSAT_HU = 2192 |
| 19090 | CEFBS_None, // XVSAT_W = 2193 |
| 19091 | CEFBS_None, // XVSAT_WU = 2194 |
| 19092 | CEFBS_None, // XVSEQI_B = 2195 |
| 19093 | CEFBS_None, // XVSEQI_D = 2196 |
| 19094 | CEFBS_None, // XVSEQI_H = 2197 |
| 19095 | CEFBS_None, // XVSEQI_W = 2198 |
| 19096 | CEFBS_None, // XVSEQ_B = 2199 |
| 19097 | CEFBS_None, // XVSEQ_D = 2200 |
| 19098 | CEFBS_None, // XVSEQ_H = 2201 |
| 19099 | CEFBS_None, // XVSEQ_W = 2202 |
| 19100 | CEFBS_None, // XVSETALLNEZ_B = 2203 |
| 19101 | CEFBS_None, // XVSETALLNEZ_D = 2204 |
| 19102 | CEFBS_None, // XVSETALLNEZ_H = 2205 |
| 19103 | CEFBS_None, // XVSETALLNEZ_W = 2206 |
| 19104 | CEFBS_None, // XVSETANYEQZ_B = 2207 |
| 19105 | CEFBS_None, // XVSETANYEQZ_D = 2208 |
| 19106 | CEFBS_None, // XVSETANYEQZ_H = 2209 |
| 19107 | CEFBS_None, // XVSETANYEQZ_W = 2210 |
| 19108 | CEFBS_None, // XVSETEQZ_V = 2211 |
| 19109 | CEFBS_None, // XVSETNEZ_V = 2212 |
| 19110 | CEFBS_None, // XVSHUF4I_B = 2213 |
| 19111 | CEFBS_None, // XVSHUF4I_D = 2214 |
| 19112 | CEFBS_None, // XVSHUF4I_H = 2215 |
| 19113 | CEFBS_None, // XVSHUF4I_W = 2216 |
| 19114 | CEFBS_None, // XVSHUF_B = 2217 |
| 19115 | CEFBS_None, // XVSHUF_D = 2218 |
| 19116 | CEFBS_None, // XVSHUF_H = 2219 |
| 19117 | CEFBS_None, // XVSHUF_W = 2220 |
| 19118 | CEFBS_None, // XVSIGNCOV_B = 2221 |
| 19119 | CEFBS_None, // XVSIGNCOV_D = 2222 |
| 19120 | CEFBS_None, // XVSIGNCOV_H = 2223 |
| 19121 | CEFBS_None, // XVSIGNCOV_W = 2224 |
| 19122 | CEFBS_None, // XVSLEI_B = 2225 |
| 19123 | CEFBS_None, // XVSLEI_BU = 2226 |
| 19124 | CEFBS_None, // XVSLEI_D = 2227 |
| 19125 | CEFBS_None, // XVSLEI_DU = 2228 |
| 19126 | CEFBS_None, // XVSLEI_H = 2229 |
| 19127 | CEFBS_None, // XVSLEI_HU = 2230 |
| 19128 | CEFBS_None, // XVSLEI_W = 2231 |
| 19129 | CEFBS_None, // XVSLEI_WU = 2232 |
| 19130 | CEFBS_None, // XVSLE_B = 2233 |
| 19131 | CEFBS_None, // XVSLE_BU = 2234 |
| 19132 | CEFBS_None, // XVSLE_D = 2235 |
| 19133 | CEFBS_None, // XVSLE_DU = 2236 |
| 19134 | CEFBS_None, // XVSLE_H = 2237 |
| 19135 | CEFBS_None, // XVSLE_HU = 2238 |
| 19136 | CEFBS_None, // XVSLE_W = 2239 |
| 19137 | CEFBS_None, // XVSLE_WU = 2240 |
| 19138 | CEFBS_None, // XVSLLI_B = 2241 |
| 19139 | CEFBS_None, // XVSLLI_D = 2242 |
| 19140 | CEFBS_None, // XVSLLI_H = 2243 |
| 19141 | CEFBS_None, // XVSLLI_W = 2244 |
| 19142 | CEFBS_None, // XVSLLWIL_DU_WU = 2245 |
| 19143 | CEFBS_None, // XVSLLWIL_D_W = 2246 |
| 19144 | CEFBS_None, // XVSLLWIL_HU_BU = 2247 |
| 19145 | CEFBS_None, // XVSLLWIL_H_B = 2248 |
| 19146 | CEFBS_None, // XVSLLWIL_WU_HU = 2249 |
| 19147 | CEFBS_None, // XVSLLWIL_W_H = 2250 |
| 19148 | CEFBS_None, // XVSLL_B = 2251 |
| 19149 | CEFBS_None, // XVSLL_D = 2252 |
| 19150 | CEFBS_None, // XVSLL_H = 2253 |
| 19151 | CEFBS_None, // XVSLL_W = 2254 |
| 19152 | CEFBS_None, // XVSLTI_B = 2255 |
| 19153 | CEFBS_None, // XVSLTI_BU = 2256 |
| 19154 | CEFBS_None, // XVSLTI_D = 2257 |
| 19155 | CEFBS_None, // XVSLTI_DU = 2258 |
| 19156 | CEFBS_None, // XVSLTI_H = 2259 |
| 19157 | CEFBS_None, // XVSLTI_HU = 2260 |
| 19158 | CEFBS_None, // XVSLTI_W = 2261 |
| 19159 | CEFBS_None, // XVSLTI_WU = 2262 |
| 19160 | CEFBS_None, // XVSLT_B = 2263 |
| 19161 | CEFBS_None, // XVSLT_BU = 2264 |
| 19162 | CEFBS_None, // XVSLT_D = 2265 |
| 19163 | CEFBS_None, // XVSLT_DU = 2266 |
| 19164 | CEFBS_None, // XVSLT_H = 2267 |
| 19165 | CEFBS_None, // XVSLT_HU = 2268 |
| 19166 | CEFBS_None, // XVSLT_W = 2269 |
| 19167 | CEFBS_None, // XVSLT_WU = 2270 |
| 19168 | CEFBS_None, // XVSRAI_B = 2271 |
| 19169 | CEFBS_None, // XVSRAI_D = 2272 |
| 19170 | CEFBS_None, // XVSRAI_H = 2273 |
| 19171 | CEFBS_None, // XVSRAI_W = 2274 |
| 19172 | CEFBS_None, // XVSRANI_B_H = 2275 |
| 19173 | CEFBS_None, // XVSRANI_D_Q = 2276 |
| 19174 | CEFBS_None, // XVSRANI_H_W = 2277 |
| 19175 | CEFBS_None, // XVSRANI_W_D = 2278 |
| 19176 | CEFBS_None, // XVSRAN_B_H = 2279 |
| 19177 | CEFBS_None, // XVSRAN_H_W = 2280 |
| 19178 | CEFBS_None, // XVSRAN_W_D = 2281 |
| 19179 | CEFBS_None, // XVSRARI_B = 2282 |
| 19180 | CEFBS_None, // XVSRARI_D = 2283 |
| 19181 | CEFBS_None, // XVSRARI_H = 2284 |
| 19182 | CEFBS_None, // XVSRARI_W = 2285 |
| 19183 | CEFBS_None, // XVSRARNI_B_H = 2286 |
| 19184 | CEFBS_None, // XVSRARNI_D_Q = 2287 |
| 19185 | CEFBS_None, // XVSRARNI_H_W = 2288 |
| 19186 | CEFBS_None, // XVSRARNI_W_D = 2289 |
| 19187 | CEFBS_None, // XVSRARN_B_H = 2290 |
| 19188 | CEFBS_None, // XVSRARN_H_W = 2291 |
| 19189 | CEFBS_None, // XVSRARN_W_D = 2292 |
| 19190 | CEFBS_None, // XVSRAR_B = 2293 |
| 19191 | CEFBS_None, // XVSRAR_D = 2294 |
| 19192 | CEFBS_None, // XVSRAR_H = 2295 |
| 19193 | CEFBS_None, // XVSRAR_W = 2296 |
| 19194 | CEFBS_None, // XVSRA_B = 2297 |
| 19195 | CEFBS_None, // XVSRA_D = 2298 |
| 19196 | CEFBS_None, // XVSRA_H = 2299 |
| 19197 | CEFBS_None, // XVSRA_W = 2300 |
| 19198 | CEFBS_None, // XVSRLI_B = 2301 |
| 19199 | CEFBS_None, // XVSRLI_D = 2302 |
| 19200 | CEFBS_None, // XVSRLI_H = 2303 |
| 19201 | CEFBS_None, // XVSRLI_W = 2304 |
| 19202 | CEFBS_None, // XVSRLNI_B_H = 2305 |
| 19203 | CEFBS_None, // XVSRLNI_D_Q = 2306 |
| 19204 | CEFBS_None, // XVSRLNI_H_W = 2307 |
| 19205 | CEFBS_None, // XVSRLNI_W_D = 2308 |
| 19206 | CEFBS_None, // XVSRLN_B_H = 2309 |
| 19207 | CEFBS_None, // XVSRLN_H_W = 2310 |
| 19208 | CEFBS_None, // XVSRLN_W_D = 2311 |
| 19209 | CEFBS_None, // XVSRLRI_B = 2312 |
| 19210 | CEFBS_None, // XVSRLRI_D = 2313 |
| 19211 | CEFBS_None, // XVSRLRI_H = 2314 |
| 19212 | CEFBS_None, // XVSRLRI_W = 2315 |
| 19213 | CEFBS_None, // XVSRLRNI_B_H = 2316 |
| 19214 | CEFBS_None, // XVSRLRNI_D_Q = 2317 |
| 19215 | CEFBS_None, // XVSRLRNI_H_W = 2318 |
| 19216 | CEFBS_None, // XVSRLRNI_W_D = 2319 |
| 19217 | CEFBS_None, // XVSRLRN_B_H = 2320 |
| 19218 | CEFBS_None, // XVSRLRN_H_W = 2321 |
| 19219 | CEFBS_None, // XVSRLRN_W_D = 2322 |
| 19220 | CEFBS_None, // XVSRLR_B = 2323 |
| 19221 | CEFBS_None, // XVSRLR_D = 2324 |
| 19222 | CEFBS_None, // XVSRLR_H = 2325 |
| 19223 | CEFBS_None, // XVSRLR_W = 2326 |
| 19224 | CEFBS_None, // XVSRL_B = 2327 |
| 19225 | CEFBS_None, // XVSRL_D = 2328 |
| 19226 | CEFBS_None, // XVSRL_H = 2329 |
| 19227 | CEFBS_None, // XVSRL_W = 2330 |
| 19228 | CEFBS_None, // XVSSRANI_BU_H = 2331 |
| 19229 | CEFBS_None, // XVSSRANI_B_H = 2332 |
| 19230 | CEFBS_None, // XVSSRANI_DU_Q = 2333 |
| 19231 | CEFBS_None, // XVSSRANI_D_Q = 2334 |
| 19232 | CEFBS_None, // XVSSRANI_HU_W = 2335 |
| 19233 | CEFBS_None, // XVSSRANI_H_W = 2336 |
| 19234 | CEFBS_None, // XVSSRANI_WU_D = 2337 |
| 19235 | CEFBS_None, // XVSSRANI_W_D = 2338 |
| 19236 | CEFBS_None, // XVSSRAN_BU_H = 2339 |
| 19237 | CEFBS_None, // XVSSRAN_B_H = 2340 |
| 19238 | CEFBS_None, // XVSSRAN_HU_W = 2341 |
| 19239 | CEFBS_None, // XVSSRAN_H_W = 2342 |
| 19240 | CEFBS_None, // XVSSRAN_WU_D = 2343 |
| 19241 | CEFBS_None, // XVSSRAN_W_D = 2344 |
| 19242 | CEFBS_None, // XVSSRARNI_BU_H = 2345 |
| 19243 | CEFBS_None, // XVSSRARNI_B_H = 2346 |
| 19244 | CEFBS_None, // XVSSRARNI_DU_Q = 2347 |
| 19245 | CEFBS_None, // XVSSRARNI_D_Q = 2348 |
| 19246 | CEFBS_None, // XVSSRARNI_HU_W = 2349 |
| 19247 | CEFBS_None, // XVSSRARNI_H_W = 2350 |
| 19248 | CEFBS_None, // XVSSRARNI_WU_D = 2351 |
| 19249 | CEFBS_None, // XVSSRARNI_W_D = 2352 |
| 19250 | CEFBS_None, // XVSSRARN_BU_H = 2353 |
| 19251 | CEFBS_None, // XVSSRARN_B_H = 2354 |
| 19252 | CEFBS_None, // XVSSRARN_HU_W = 2355 |
| 19253 | CEFBS_None, // XVSSRARN_H_W = 2356 |
| 19254 | CEFBS_None, // XVSSRARN_WU_D = 2357 |
| 19255 | CEFBS_None, // XVSSRARN_W_D = 2358 |
| 19256 | CEFBS_None, // XVSSRLNI_BU_H = 2359 |
| 19257 | CEFBS_None, // XVSSRLNI_B_H = 2360 |
| 19258 | CEFBS_None, // XVSSRLNI_DU_Q = 2361 |
| 19259 | CEFBS_None, // XVSSRLNI_D_Q = 2362 |
| 19260 | CEFBS_None, // XVSSRLNI_HU_W = 2363 |
| 19261 | CEFBS_None, // XVSSRLNI_H_W = 2364 |
| 19262 | CEFBS_None, // XVSSRLNI_WU_D = 2365 |
| 19263 | CEFBS_None, // XVSSRLNI_W_D = 2366 |
| 19264 | CEFBS_None, // XVSSRLN_BU_H = 2367 |
| 19265 | CEFBS_None, // XVSSRLN_B_H = 2368 |
| 19266 | CEFBS_None, // XVSSRLN_HU_W = 2369 |
| 19267 | CEFBS_None, // XVSSRLN_H_W = 2370 |
| 19268 | CEFBS_None, // XVSSRLN_WU_D = 2371 |
| 19269 | CEFBS_None, // XVSSRLN_W_D = 2372 |
| 19270 | CEFBS_None, // XVSSRLRNI_BU_H = 2373 |
| 19271 | CEFBS_None, // XVSSRLRNI_B_H = 2374 |
| 19272 | CEFBS_None, // XVSSRLRNI_DU_Q = 2375 |
| 19273 | CEFBS_None, // XVSSRLRNI_D_Q = 2376 |
| 19274 | CEFBS_None, // XVSSRLRNI_HU_W = 2377 |
| 19275 | CEFBS_None, // XVSSRLRNI_H_W = 2378 |
| 19276 | CEFBS_None, // XVSSRLRNI_WU_D = 2379 |
| 19277 | CEFBS_None, // XVSSRLRNI_W_D = 2380 |
| 19278 | CEFBS_None, // XVSSRLRN_BU_H = 2381 |
| 19279 | CEFBS_None, // XVSSRLRN_B_H = 2382 |
| 19280 | CEFBS_None, // XVSSRLRN_HU_W = 2383 |
| 19281 | CEFBS_None, // XVSSRLRN_H_W = 2384 |
| 19282 | CEFBS_None, // XVSSRLRN_WU_D = 2385 |
| 19283 | CEFBS_None, // XVSSRLRN_W_D = 2386 |
| 19284 | CEFBS_None, // XVSSUB_B = 2387 |
| 19285 | CEFBS_None, // XVSSUB_BU = 2388 |
| 19286 | CEFBS_None, // XVSSUB_D = 2389 |
| 19287 | CEFBS_None, // XVSSUB_DU = 2390 |
| 19288 | CEFBS_None, // XVSSUB_H = 2391 |
| 19289 | CEFBS_None, // XVSSUB_HU = 2392 |
| 19290 | CEFBS_None, // XVSSUB_W = 2393 |
| 19291 | CEFBS_None, // XVSSUB_WU = 2394 |
| 19292 | CEFBS_None, // XVST = 2395 |
| 19293 | CEFBS_None, // XVSTELM_B = 2396 |
| 19294 | CEFBS_None, // XVSTELM_D = 2397 |
| 19295 | CEFBS_None, // XVSTELM_H = 2398 |
| 19296 | CEFBS_None, // XVSTELM_W = 2399 |
| 19297 | CEFBS_None, // XVSTX = 2400 |
| 19298 | CEFBS_None, // XVSUBI_BU = 2401 |
| 19299 | CEFBS_None, // XVSUBI_DU = 2402 |
| 19300 | CEFBS_None, // XVSUBI_HU = 2403 |
| 19301 | CEFBS_None, // XVSUBI_WU = 2404 |
| 19302 | CEFBS_None, // XVSUBWEV_D_W = 2405 |
| 19303 | CEFBS_None, // XVSUBWEV_D_WU = 2406 |
| 19304 | CEFBS_None, // XVSUBWEV_H_B = 2407 |
| 19305 | CEFBS_None, // XVSUBWEV_H_BU = 2408 |
| 19306 | CEFBS_None, // XVSUBWEV_Q_D = 2409 |
| 19307 | CEFBS_None, // XVSUBWEV_Q_DU = 2410 |
| 19308 | CEFBS_None, // XVSUBWEV_W_H = 2411 |
| 19309 | CEFBS_None, // XVSUBWEV_W_HU = 2412 |
| 19310 | CEFBS_None, // XVSUBWOD_D_W = 2413 |
| 19311 | CEFBS_None, // XVSUBWOD_D_WU = 2414 |
| 19312 | CEFBS_None, // XVSUBWOD_H_B = 2415 |
| 19313 | CEFBS_None, // XVSUBWOD_H_BU = 2416 |
| 19314 | CEFBS_None, // XVSUBWOD_Q_D = 2417 |
| 19315 | CEFBS_None, // XVSUBWOD_Q_DU = 2418 |
| 19316 | CEFBS_None, // XVSUBWOD_W_H = 2419 |
| 19317 | CEFBS_None, // XVSUBWOD_W_HU = 2420 |
| 19318 | CEFBS_None, // XVSUB_B = 2421 |
| 19319 | CEFBS_None, // XVSUB_D = 2422 |
| 19320 | CEFBS_None, // XVSUB_H = 2423 |
| 19321 | CEFBS_None, // XVSUB_Q = 2424 |
| 19322 | CEFBS_None, // XVSUB_W = 2425 |
| 19323 | CEFBS_None, // XVXORI_B = 2426 |
| 19324 | CEFBS_None, // XVXOR_V = 2427 |
| 19325 | }; |
| 19326 | |
| 19327 | assert(Opcode < 2428); |
| 19328 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| 19329 | } |
| 19330 | |
| 19331 | } // end namespace LoongArch_MC |
| 19332 | } // end namespace llvm |
| 19333 | #endif // GET_COMPUTE_FEATURES |
| 19334 | |
| 19335 | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
| 19336 | #undef GET_AVAILABLE_OPCODE_CHECKER |
| 19337 | namespace llvm { |
| 19338 | namespace LoongArch_MC { |
| 19339 | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
| 19340 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 19341 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 19342 | FeatureBitset MissingFeatures = |
| 19343 | (AvailableFeatures & RequiredFeatures) ^ |
| 19344 | RequiredFeatures; |
| 19345 | return !MissingFeatures.any(); |
| 19346 | } |
| 19347 | } // end namespace LoongArch_MC |
| 19348 | } // end namespace llvm |
| 19349 | #endif // GET_AVAILABLE_OPCODE_CHECKER |
| 19350 | |
| 19351 | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| 19352 | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| 19353 | #include <sstream> |
| 19354 | |
| 19355 | namespace llvm { |
| 19356 | namespace LoongArch_MC { |
| 19357 | |
| 19358 | #ifndef NDEBUG |
| 19359 | static const char *SubtargetFeatureNames[] = { |
| 19360 | "Feature_HasLaGlobalWithAbs", |
| 19361 | "Feature_HasLaGlobalWithPcrel", |
| 19362 | "Feature_HasLaLocalWithAbs", |
| 19363 | "Feature_IsLA32", |
| 19364 | "Feature_IsLA64", |
| 19365 | nullptr |
| 19366 | }; |
| 19367 | |
| 19368 | #endif // NDEBUG |
| 19369 | |
| 19370 | void verifyInstructionPredicates( |
| 19371 | unsigned Opcode, const FeatureBitset &Features) { |
| 19372 | #ifndef NDEBUG |
| 19373 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| 19374 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
| 19375 | FeatureBitset MissingFeatures = |
| 19376 | (AvailableFeatures & RequiredFeatures) ^ |
| 19377 | RequiredFeatures; |
| 19378 | if (MissingFeatures.any()) { |
| 19379 | std::ostringstream Msg; |
| 19380 | Msg << "Attempting to emit "<< &LoongArchInstrNameData[LoongArchInstrNameIndices[Opcode]] |
| 19381 | << " instruction but the "; |
| 19382 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| 19383 | if (MissingFeatures.test(i)) |
| 19384 | Msg << SubtargetFeatureNames[i] << " "; |
| 19385 | Msg << "predicate(s) are not met"; |
| 19386 | report_fatal_error(Msg.str().c_str()); |
| 19387 | } |
| 19388 | #endif // NDEBUG |
| 19389 | } |
| 19390 | } // end namespace LoongArch_MC |
| 19391 | } // end namespace llvm |
| 19392 | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| 19393 | |
| 19394 |
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