1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass LoongArchMCRegisterClasses[];
17
18namespace LoongArch {
19enum {
20 NoRegister,
21 F0 = 1,
22 F1 = 2,
23 F2 = 3,
24 F3 = 4,
25 F4 = 5,
26 F5 = 6,
27 F6 = 7,
28 F7 = 8,
29 F8 = 9,
30 F9 = 10,
31 F10 = 11,
32 F11 = 12,
33 F12 = 13,
34 F13 = 14,
35 F14 = 15,
36 F15 = 16,
37 F16 = 17,
38 F17 = 18,
39 F18 = 19,
40 F19 = 20,
41 F20 = 21,
42 F21 = 22,
43 F22 = 23,
44 F23 = 24,
45 F24 = 25,
46 F25 = 26,
47 F26 = 27,
48 F27 = 28,
49 F28 = 29,
50 F29 = 30,
51 F30 = 31,
52 F31 = 32,
53 FCC0 = 33,
54 FCC1 = 34,
55 FCC2 = 35,
56 FCC3 = 36,
57 FCC4 = 37,
58 FCC5 = 38,
59 FCC6 = 39,
60 FCC7 = 40,
61 FCSR0 = 41,
62 FCSR1 = 42,
63 FCSR2 = 43,
64 FCSR3 = 44,
65 R0 = 45,
66 R1 = 46,
67 R2 = 47,
68 R3 = 48,
69 R4 = 49,
70 R5 = 50,
71 R6 = 51,
72 R7 = 52,
73 R8 = 53,
74 R9 = 54,
75 R10 = 55,
76 R11 = 56,
77 R12 = 57,
78 R13 = 58,
79 R14 = 59,
80 R15 = 60,
81 R16 = 61,
82 R17 = 62,
83 R18 = 63,
84 R19 = 64,
85 R20 = 65,
86 R21 = 66,
87 R22 = 67,
88 R23 = 68,
89 R24 = 69,
90 R25 = 70,
91 R26 = 71,
92 R27 = 72,
93 R28 = 73,
94 R29 = 74,
95 R30 = 75,
96 R31 = 76,
97 SCR0 = 77,
98 SCR1 = 78,
99 SCR2 = 79,
100 SCR3 = 80,
101 VR0 = 81,
102 VR1 = 82,
103 VR2 = 83,
104 VR3 = 84,
105 VR4 = 85,
106 VR5 = 86,
107 VR6 = 87,
108 VR7 = 88,
109 VR8 = 89,
110 VR9 = 90,
111 VR10 = 91,
112 VR11 = 92,
113 VR12 = 93,
114 VR13 = 94,
115 VR14 = 95,
116 VR15 = 96,
117 VR16 = 97,
118 VR17 = 98,
119 VR18 = 99,
120 VR19 = 100,
121 VR20 = 101,
122 VR21 = 102,
123 VR22 = 103,
124 VR23 = 104,
125 VR24 = 105,
126 VR25 = 106,
127 VR26 = 107,
128 VR27 = 108,
129 VR28 = 109,
130 VR29 = 110,
131 VR30 = 111,
132 VR31 = 112,
133 XR0 = 113,
134 XR1 = 114,
135 XR2 = 115,
136 XR3 = 116,
137 XR4 = 117,
138 XR5 = 118,
139 XR6 = 119,
140 XR7 = 120,
141 XR8 = 121,
142 XR9 = 122,
143 XR10 = 123,
144 XR11 = 124,
145 XR12 = 125,
146 XR13 = 126,
147 XR14 = 127,
148 XR15 = 128,
149 XR16 = 129,
150 XR17 = 130,
151 XR18 = 131,
152 XR19 = 132,
153 XR20 = 133,
154 XR21 = 134,
155 XR22 = 135,
156 XR23 = 136,
157 XR24 = 137,
158 XR25 = 138,
159 XR26 = 139,
160 XR27 = 140,
161 XR28 = 141,
162 XR29 = 142,
163 XR30 = 143,
164 XR31 = 144,
165 F0_64 = 145,
166 F1_64 = 146,
167 F2_64 = 147,
168 F3_64 = 148,
169 F4_64 = 149,
170 F5_64 = 150,
171 F6_64 = 151,
172 F7_64 = 152,
173 F8_64 = 153,
174 F9_64 = 154,
175 F10_64 = 155,
176 F11_64 = 156,
177 F12_64 = 157,
178 F13_64 = 158,
179 F14_64 = 159,
180 F15_64 = 160,
181 F16_64 = 161,
182 F17_64 = 162,
183 F18_64 = 163,
184 F19_64 = 164,
185 F20_64 = 165,
186 F21_64 = 166,
187 F22_64 = 167,
188 F23_64 = 168,
189 F24_64 = 169,
190 F25_64 = 170,
191 F26_64 = 171,
192 F27_64 = 172,
193 F28_64 = 173,
194 F29_64 = 174,
195 F30_64 = 175,
196 F31_64 = 176,
197 NUM_TARGET_REGS // 177
198};
199} // end namespace LoongArch
200
201// Register classes
202
203namespace LoongArch {
204enum {
205 FPR32RegClassID = 0,
206 GPRRegClassID = 1,
207 GPRTRegClassID = 2,
208 CFRRegClassID = 3,
209 FCSRRegClassID = 4,
210 SCRRegClassID = 5,
211 FPR64RegClassID = 6,
212 LSX128RegClassID = 7,
213 LASX256RegClassID = 8,
214
215};
216} // end namespace LoongArch
217
218
219// Register alternate name indices
220
221namespace LoongArch {
222enum {
223 NoRegAltName, // 0
224 RegAliasName, // 1
225 NUM_TARGET_REG_ALT_NAMES = 2
226};
227} // end namespace LoongArch
228
229
230// Subregister indices
231
232namespace LoongArch {
233enum : uint16_t {
234 NoSubRegister,
235 sub_32, // 1
236 sub_64, // 2
237 sub_128, // 3
238 NUM_TARGET_SUBREGS
239};
240} // end namespace LoongArch
241
242// Register pressure sets enum.
243namespace LoongArch {
244enum RegisterPressureSets {
245 CFR = 0,
246 GPRT = 1,
247 FPR32 = 2,
248 GPR = 3,
249};
250} // end namespace LoongArch
251
252} // end namespace llvm
253
254#endif // GET_REGINFO_ENUM
255
256/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
257|* *|
258|* MC Register Information *|
259|* *|
260|* Automatically generated file, do not edit! *|
261|* *|
262\*===----------------------------------------------------------------------===*/
263
264
265#ifdef GET_REGINFO_MC_DESC
266#undef GET_REGINFO_MC_DESC
267
268namespace llvm {
269
270extern const int16_t LoongArchRegDiffLists[] = {
271 /* 0 */ -32, 64, -144, 0,
272 /* 4 */ 144, -64, 32, 0,
273};
274
275extern const LaneBitmask LoongArchLaneMaskLists[] = {
276 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
277 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
278};
279
280extern const uint16_t LoongArchSubRegIdxLists[] = {
281 /* 0 */ 3, 2, 1, 0,
282};
283
284
285#ifdef __GNUC__
286#pragma GCC diagnostic push
287#pragma GCC diagnostic ignored "-Woverlength-strings"
288#endif
289extern const char LoongArchRegStrings[] = {
290 /* 0 */ "F10\0"
291 /* 4 */ "VR10\0"
292 /* 9 */ "XR10\0"
293 /* 14 */ "F20\0"
294 /* 18 */ "VR20\0"
295 /* 23 */ "XR20\0"
296 /* 28 */ "F30\0"
297 /* 32 */ "VR30\0"
298 /* 37 */ "XR30\0"
299 /* 42 */ "FCC0\0"
300 /* 47 */ "F0\0"
301 /* 50 */ "SCR0\0"
302 /* 55 */ "FCSR0\0"
303 /* 61 */ "VR0\0"
304 /* 65 */ "XR0\0"
305 /* 69 */ "F11\0"
306 /* 73 */ "VR11\0"
307 /* 78 */ "XR11\0"
308 /* 83 */ "F21\0"
309 /* 87 */ "VR21\0"
310 /* 92 */ "XR21\0"
311 /* 97 */ "F31\0"
312 /* 101 */ "VR31\0"
313 /* 106 */ "XR31\0"
314 /* 111 */ "FCC1\0"
315 /* 116 */ "F1\0"
316 /* 119 */ "SCR1\0"
317 /* 124 */ "FCSR1\0"
318 /* 130 */ "VR1\0"
319 /* 134 */ "XR1\0"
320 /* 138 */ "F12\0"
321 /* 142 */ "VR12\0"
322 /* 147 */ "XR12\0"
323 /* 152 */ "F22\0"
324 /* 156 */ "VR22\0"
325 /* 161 */ "XR22\0"
326 /* 166 */ "FCC2\0"
327 /* 171 */ "F2\0"
328 /* 174 */ "SCR2\0"
329 /* 179 */ "FCSR2\0"
330 /* 185 */ "VR2\0"
331 /* 189 */ "XR2\0"
332 /* 193 */ "F13\0"
333 /* 197 */ "VR13\0"
334 /* 202 */ "XR13\0"
335 /* 207 */ "F23\0"
336 /* 211 */ "VR23\0"
337 /* 216 */ "XR23\0"
338 /* 221 */ "FCC3\0"
339 /* 226 */ "F3\0"
340 /* 229 */ "SCR3\0"
341 /* 234 */ "FCSR3\0"
342 /* 240 */ "VR3\0"
343 /* 244 */ "XR3\0"
344 /* 248 */ "F14\0"
345 /* 252 */ "VR14\0"
346 /* 257 */ "XR14\0"
347 /* 262 */ "F24\0"
348 /* 266 */ "VR24\0"
349 /* 271 */ "XR24\0"
350 /* 276 */ "F10_64\0"
351 /* 283 */ "F20_64\0"
352 /* 290 */ "F30_64\0"
353 /* 297 */ "F0_64\0"
354 /* 303 */ "F11_64\0"
355 /* 310 */ "F21_64\0"
356 /* 317 */ "F31_64\0"
357 /* 324 */ "F1_64\0"
358 /* 330 */ "F12_64\0"
359 /* 337 */ "F22_64\0"
360 /* 344 */ "F2_64\0"
361 /* 350 */ "F13_64\0"
362 /* 357 */ "F23_64\0"
363 /* 364 */ "F3_64\0"
364 /* 370 */ "F14_64\0"
365 /* 377 */ "F24_64\0"
366 /* 384 */ "F4_64\0"
367 /* 390 */ "F15_64\0"
368 /* 397 */ "F25_64\0"
369 /* 404 */ "F5_64\0"
370 /* 410 */ "F16_64\0"
371 /* 417 */ "F26_64\0"
372 /* 424 */ "F6_64\0"
373 /* 430 */ "F17_64\0"
374 /* 437 */ "F27_64\0"
375 /* 444 */ "F7_64\0"
376 /* 450 */ "F18_64\0"
377 /* 457 */ "F28_64\0"
378 /* 464 */ "F8_64\0"
379 /* 470 */ "F19_64\0"
380 /* 477 */ "F29_64\0"
381 /* 484 */ "F9_64\0"
382 /* 490 */ "FCC4\0"
383 /* 495 */ "F4\0"
384 /* 498 */ "VR4\0"
385 /* 502 */ "XR4\0"
386 /* 506 */ "F15\0"
387 /* 510 */ "VR15\0"
388 /* 515 */ "XR15\0"
389 /* 520 */ "F25\0"
390 /* 524 */ "VR25\0"
391 /* 529 */ "XR25\0"
392 /* 534 */ "FCC5\0"
393 /* 539 */ "F5\0"
394 /* 542 */ "VR5\0"
395 /* 546 */ "XR5\0"
396 /* 550 */ "F16\0"
397 /* 554 */ "VR16\0"
398 /* 559 */ "XR16\0"
399 /* 564 */ "F26\0"
400 /* 568 */ "VR26\0"
401 /* 573 */ "XR26\0"
402 /* 578 */ "FCC6\0"
403 /* 583 */ "F6\0"
404 /* 586 */ "VR6\0"
405 /* 590 */ "XR6\0"
406 /* 594 */ "F17\0"
407 /* 598 */ "VR17\0"
408 /* 603 */ "XR17\0"
409 /* 608 */ "F27\0"
410 /* 612 */ "VR27\0"
411 /* 617 */ "XR27\0"
412 /* 622 */ "FCC7\0"
413 /* 627 */ "F7\0"
414 /* 630 */ "VR7\0"
415 /* 634 */ "XR7\0"
416 /* 638 */ "F18\0"
417 /* 642 */ "VR18\0"
418 /* 647 */ "XR18\0"
419 /* 652 */ "F28\0"
420 /* 656 */ "VR28\0"
421 /* 661 */ "XR28\0"
422 /* 666 */ "F8\0"
423 /* 669 */ "VR8\0"
424 /* 673 */ "XR8\0"
425 /* 677 */ "F19\0"
426 /* 681 */ "VR19\0"
427 /* 686 */ "XR19\0"
428 /* 691 */ "F29\0"
429 /* 695 */ "VR29\0"
430 /* 700 */ "XR29\0"
431 /* 705 */ "F9\0"
432 /* 708 */ "VR9\0"
433 /* 712 */ "XR9\0"
434};
435#ifdef __GNUC__
436#pragma GCC diagnostic pop
437#endif
438
439extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
440 { 3, 0, 0, 0, 0, 0, 0 },
441 { 47, 3, 4, 3, 12288, 2, 0 },
442 { 116, 3, 4, 3, 12289, 2, 0 },
443 { 171, 3, 4, 3, 12290, 2, 0 },
444 { 226, 3, 4, 3, 12291, 2, 0 },
445 { 495, 3, 4, 3, 12292, 2, 0 },
446 { 539, 3, 4, 3, 12293, 2, 0 },
447 { 583, 3, 4, 3, 12294, 2, 0 },
448 { 627, 3, 4, 3, 12295, 2, 0 },
449 { 666, 3, 4, 3, 12296, 2, 0 },
450 { 705, 3, 4, 3, 12297, 2, 0 },
451 { 0, 3, 4, 3, 12298, 2, 0 },
452 { 69, 3, 4, 3, 12299, 2, 0 },
453 { 138, 3, 4, 3, 12300, 2, 0 },
454 { 193, 3, 4, 3, 12301, 2, 0 },
455 { 248, 3, 4, 3, 12302, 2, 0 },
456 { 506, 3, 4, 3, 12303, 2, 0 },
457 { 550, 3, 4, 3, 12304, 2, 0 },
458 { 594, 3, 4, 3, 12305, 2, 0 },
459 { 638, 3, 4, 3, 12306, 2, 0 },
460 { 677, 3, 4, 3, 12307, 2, 0 },
461 { 14, 3, 4, 3, 12308, 2, 0 },
462 { 83, 3, 4, 3, 12309, 2, 0 },
463 { 152, 3, 4, 3, 12310, 2, 0 },
464 { 207, 3, 4, 3, 12311, 2, 0 },
465 { 262, 3, 4, 3, 12312, 2, 0 },
466 { 520, 3, 4, 3, 12313, 2, 0 },
467 { 564, 3, 4, 3, 12314, 2, 0 },
468 { 608, 3, 4, 3, 12315, 2, 0 },
469 { 652, 3, 4, 3, 12316, 2, 0 },
470 { 691, 3, 4, 3, 12317, 2, 0 },
471 { 28, 3, 4, 3, 12318, 2, 0 },
472 { 97, 3, 4, 3, 12319, 2, 0 },
473 { 42, 3, 3, 3, 12320, 2, 0 },
474 { 111, 3, 3, 3, 12321, 2, 0 },
475 { 166, 3, 3, 3, 12322, 2, 0 },
476 { 221, 3, 3, 3, 12323, 2, 0 },
477 { 490, 3, 3, 3, 12324, 2, 0 },
478 { 534, 3, 3, 3, 12325, 2, 0 },
479 { 578, 3, 3, 3, 12326, 2, 0 },
480 { 622, 3, 3, 3, 12327, 2, 0 },
481 { 55, 3, 3, 3, 12328, 2, 0 },
482 { 124, 3, 3, 3, 12329, 2, 0 },
483 { 179, 3, 3, 3, 12330, 2, 0 },
484 { 234, 3, 3, 3, 12331, 2, 0 },
485 { 52, 3, 3, 3, 12332, 2, 1 },
486 { 121, 3, 3, 3, 12333, 2, 0 },
487 { 176, 3, 3, 3, 12334, 2, 0 },
488 { 231, 3, 3, 3, 12335, 2, 0 },
489 { 499, 3, 3, 3, 12336, 2, 0 },
490 { 543, 3, 3, 3, 12337, 2, 0 },
491 { 587, 3, 3, 3, 12338, 2, 0 },
492 { 631, 3, 3, 3, 12339, 2, 0 },
493 { 670, 3, 3, 3, 12340, 2, 0 },
494 { 709, 3, 3, 3, 12341, 2, 0 },
495 { 5, 3, 3, 3, 12342, 2, 0 },
496 { 74, 3, 3, 3, 12343, 2, 0 },
497 { 143, 3, 3, 3, 12344, 2, 0 },
498 { 198, 3, 3, 3, 12345, 2, 0 },
499 { 253, 3, 3, 3, 12346, 2, 0 },
500 { 511, 3, 3, 3, 12347, 2, 0 },
501 { 555, 3, 3, 3, 12348, 2, 0 },
502 { 599, 3, 3, 3, 12349, 2, 0 },
503 { 643, 3, 3, 3, 12350, 2, 0 },
504 { 682, 3, 3, 3, 12351, 2, 0 },
505 { 19, 3, 3, 3, 12352, 2, 0 },
506 { 88, 3, 3, 3, 12353, 2, 0 },
507 { 157, 3, 3, 3, 12354, 2, 0 },
508 { 212, 3, 3, 3, 12355, 2, 0 },
509 { 267, 3, 3, 3, 12356, 2, 0 },
510 { 525, 3, 3, 3, 12357, 2, 0 },
511 { 569, 3, 3, 3, 12358, 2, 0 },
512 { 613, 3, 3, 3, 12359, 2, 0 },
513 { 657, 3, 3, 3, 12360, 2, 0 },
514 { 696, 3, 3, 3, 12361, 2, 0 },
515 { 33, 3, 3, 3, 12362, 2, 0 },
516 { 102, 3, 3, 3, 12363, 2, 0 },
517 { 50, 3, 3, 3, 12364, 2, 0 },
518 { 119, 3, 3, 3, 12365, 2, 0 },
519 { 174, 3, 3, 3, 12366, 2, 0 },
520 { 229, 3, 3, 3, 12367, 2, 0 },
521 { 61, 1, 6, 1, 12288, 0, 0 },
522 { 130, 1, 6, 1, 12289, 0, 0 },
523 { 185, 1, 6, 1, 12290, 0, 0 },
524 { 240, 1, 6, 1, 12291, 0, 0 },
525 { 498, 1, 6, 1, 12292, 0, 0 },
526 { 542, 1, 6, 1, 12293, 0, 0 },
527 { 586, 1, 6, 1, 12294, 0, 0 },
528 { 630, 1, 6, 1, 12295, 0, 0 },
529 { 669, 1, 6, 1, 12296, 0, 0 },
530 { 708, 1, 6, 1, 12297, 0, 0 },
531 { 4, 1, 6, 1, 12298, 0, 0 },
532 { 73, 1, 6, 1, 12299, 0, 0 },
533 { 142, 1, 6, 1, 12300, 0, 0 },
534 { 197, 1, 6, 1, 12301, 0, 0 },
535 { 252, 1, 6, 1, 12302, 0, 0 },
536 { 510, 1, 6, 1, 12303, 0, 0 },
537 { 554, 1, 6, 1, 12304, 0, 0 },
538 { 598, 1, 6, 1, 12305, 0, 0 },
539 { 642, 1, 6, 1, 12306, 0, 0 },
540 { 681, 1, 6, 1, 12307, 0, 0 },
541 { 18, 1, 6, 1, 12308, 0, 0 },
542 { 87, 1, 6, 1, 12309, 0, 0 },
543 { 156, 1, 6, 1, 12310, 0, 0 },
544 { 211, 1, 6, 1, 12311, 0, 0 },
545 { 266, 1, 6, 1, 12312, 0, 0 },
546 { 524, 1, 6, 1, 12313, 0, 0 },
547 { 568, 1, 6, 1, 12314, 0, 0 },
548 { 612, 1, 6, 1, 12315, 0, 0 },
549 { 656, 1, 6, 1, 12316, 0, 0 },
550 { 695, 1, 6, 1, 12317, 0, 0 },
551 { 32, 1, 6, 1, 12318, 0, 0 },
552 { 101, 1, 6, 1, 12319, 0, 0 },
553 { 65, 0, 3, 0, 12288, 0, 0 },
554 { 134, 0, 3, 0, 12289, 0, 0 },
555 { 189, 0, 3, 0, 12290, 0, 0 },
556 { 244, 0, 3, 0, 12291, 0, 0 },
557 { 502, 0, 3, 0, 12292, 0, 0 },
558 { 546, 0, 3, 0, 12293, 0, 0 },
559 { 590, 0, 3, 0, 12294, 0, 0 },
560 { 634, 0, 3, 0, 12295, 0, 0 },
561 { 673, 0, 3, 0, 12296, 0, 0 },
562 { 712, 0, 3, 0, 12297, 0, 0 },
563 { 9, 0, 3, 0, 12298, 0, 0 },
564 { 78, 0, 3, 0, 12299, 0, 0 },
565 { 147, 0, 3, 0, 12300, 0, 0 },
566 { 202, 0, 3, 0, 12301, 0, 0 },
567 { 257, 0, 3, 0, 12302, 0, 0 },
568 { 515, 0, 3, 0, 12303, 0, 0 },
569 { 559, 0, 3, 0, 12304, 0, 0 },
570 { 603, 0, 3, 0, 12305, 0, 0 },
571 { 647, 0, 3, 0, 12306, 0, 0 },
572 { 686, 0, 3, 0, 12307, 0, 0 },
573 { 23, 0, 3, 0, 12308, 0, 0 },
574 { 92, 0, 3, 0, 12309, 0, 0 },
575 { 161, 0, 3, 0, 12310, 0, 0 },
576 { 216, 0, 3, 0, 12311, 0, 0 },
577 { 271, 0, 3, 0, 12312, 0, 0 },
578 { 529, 0, 3, 0, 12313, 0, 0 },
579 { 573, 0, 3, 0, 12314, 0, 0 },
580 { 617, 0, 3, 0, 12315, 0, 0 },
581 { 661, 0, 3, 0, 12316, 0, 0 },
582 { 700, 0, 3, 0, 12317, 0, 0 },
583 { 37, 0, 3, 0, 12318, 0, 0 },
584 { 106, 0, 3, 0, 12319, 0, 0 },
585 { 297, 2, 5, 2, 12288, 0, 0 },
586 { 324, 2, 5, 2, 12289, 0, 0 },
587 { 344, 2, 5, 2, 12290, 0, 0 },
588 { 364, 2, 5, 2, 12291, 0, 0 },
589 { 384, 2, 5, 2, 12292, 0, 0 },
590 { 404, 2, 5, 2, 12293, 0, 0 },
591 { 424, 2, 5, 2, 12294, 0, 0 },
592 { 444, 2, 5, 2, 12295, 0, 0 },
593 { 464, 2, 5, 2, 12296, 0, 0 },
594 { 484, 2, 5, 2, 12297, 0, 0 },
595 { 276, 2, 5, 2, 12298, 0, 0 },
596 { 303, 2, 5, 2, 12299, 0, 0 },
597 { 330, 2, 5, 2, 12300, 0, 0 },
598 { 350, 2, 5, 2, 12301, 0, 0 },
599 { 370, 2, 5, 2, 12302, 0, 0 },
600 { 390, 2, 5, 2, 12303, 0, 0 },
601 { 410, 2, 5, 2, 12304, 0, 0 },
602 { 430, 2, 5, 2, 12305, 0, 0 },
603 { 450, 2, 5, 2, 12306, 0, 0 },
604 { 470, 2, 5, 2, 12307, 0, 0 },
605 { 283, 2, 5, 2, 12308, 0, 0 },
606 { 310, 2, 5, 2, 12309, 0, 0 },
607 { 337, 2, 5, 2, 12310, 0, 0 },
608 { 357, 2, 5, 2, 12311, 0, 0 },
609 { 377, 2, 5, 2, 12312, 0, 0 },
610 { 397, 2, 5, 2, 12313, 0, 0 },
611 { 417, 2, 5, 2, 12314, 0, 0 },
612 { 437, 2, 5, 2, 12315, 0, 0 },
613 { 457, 2, 5, 2, 12316, 0, 0 },
614 { 477, 2, 5, 2, 12317, 0, 0 },
615 { 290, 2, 5, 2, 12318, 0, 0 },
616 { 317, 2, 5, 2, 12319, 0, 0 },
617};
618
619extern const MCPhysReg LoongArchRegUnitRoots[][2] = {
620 { LoongArch::F0 },
621 { LoongArch::F1 },
622 { LoongArch::F2 },
623 { LoongArch::F3 },
624 { LoongArch::F4 },
625 { LoongArch::F5 },
626 { LoongArch::F6 },
627 { LoongArch::F7 },
628 { LoongArch::F8 },
629 { LoongArch::F9 },
630 { LoongArch::F10 },
631 { LoongArch::F11 },
632 { LoongArch::F12 },
633 { LoongArch::F13 },
634 { LoongArch::F14 },
635 { LoongArch::F15 },
636 { LoongArch::F16 },
637 { LoongArch::F17 },
638 { LoongArch::F18 },
639 { LoongArch::F19 },
640 { LoongArch::F20 },
641 { LoongArch::F21 },
642 { LoongArch::F22 },
643 { LoongArch::F23 },
644 { LoongArch::F24 },
645 { LoongArch::F25 },
646 { LoongArch::F26 },
647 { LoongArch::F27 },
648 { LoongArch::F28 },
649 { LoongArch::F29 },
650 { LoongArch::F30 },
651 { LoongArch::F31 },
652 { LoongArch::FCC0 },
653 { LoongArch::FCC1 },
654 { LoongArch::FCC2 },
655 { LoongArch::FCC3 },
656 { LoongArch::FCC4 },
657 { LoongArch::FCC5 },
658 { LoongArch::FCC6 },
659 { LoongArch::FCC7 },
660 { LoongArch::FCSR0 },
661 { LoongArch::FCSR1 },
662 { LoongArch::FCSR2 },
663 { LoongArch::FCSR3 },
664 { LoongArch::R0 },
665 { LoongArch::R1 },
666 { LoongArch::R2 },
667 { LoongArch::R3 },
668 { LoongArch::R4 },
669 { LoongArch::R5 },
670 { LoongArch::R6 },
671 { LoongArch::R7 },
672 { LoongArch::R8 },
673 { LoongArch::R9 },
674 { LoongArch::R10 },
675 { LoongArch::R11 },
676 { LoongArch::R12 },
677 { LoongArch::R13 },
678 { LoongArch::R14 },
679 { LoongArch::R15 },
680 { LoongArch::R16 },
681 { LoongArch::R17 },
682 { LoongArch::R18 },
683 { LoongArch::R19 },
684 { LoongArch::R20 },
685 { LoongArch::R21 },
686 { LoongArch::R22 },
687 { LoongArch::R23 },
688 { LoongArch::R24 },
689 { LoongArch::R25 },
690 { LoongArch::R26 },
691 { LoongArch::R27 },
692 { LoongArch::R28 },
693 { LoongArch::R29 },
694 { LoongArch::R30 },
695 { LoongArch::R31 },
696 { LoongArch::SCR0 },
697 { LoongArch::SCR1 },
698 { LoongArch::SCR2 },
699 { LoongArch::SCR3 },
700};
701
702namespace { // Register classes...
703 // FPR32 Register Class...
704 const MCPhysReg FPR32[] = {
705 LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31,
706 };
707
708 // FPR32 Bit set.
709 const uint8_t FPR32Bits[] = {
710 0xfe, 0xff, 0xff, 0xff, 0x01,
711 };
712
713 // GPR Register Class...
714 const MCPhysReg GPR[] = {
715 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21,
716 };
717
718 // GPR Bit set.
719 const uint8_t GPRBits[] = {
720 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
721 };
722
723 // GPRT Register Class...
724 const MCPhysReg GPRT[] = {
725 LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20,
726 };
727
728 // GPRT Bit set.
729 const uint8_t GPRTBits[] = {
730 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03,
731 };
732
733 // CFR Register Class...
734 const MCPhysReg CFR[] = {
735 LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7,
736 };
737
738 // CFR Bit set.
739 const uint8_t CFRBits[] = {
740 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
741 };
742
743 // FCSR Register Class...
744 const MCPhysReg FCSR[] = {
745 LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3,
746 };
747
748 // FCSR Bit set.
749 const uint8_t FCSRBits[] = {
750 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
751 };
752
753 // SCR Register Class...
754 const MCPhysReg SCR[] = {
755 LoongArch::SCR0, LoongArch::SCR1, LoongArch::SCR2, LoongArch::SCR3,
756 };
757
758 // SCR Bit set.
759 const uint8_t SCRBits[] = {
760 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
761 };
762
763 // FPR64 Register Class...
764 const MCPhysReg FPR64[] = {
765 LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64,
766 };
767
768 // FPR64 Bit set.
769 const uint8_t FPR64Bits[] = {
770 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
771 };
772
773 // LSX128 Register Class...
774 const MCPhysReg LSX128[] = {
775 LoongArch::VR0, LoongArch::VR1, LoongArch::VR2, LoongArch::VR3, LoongArch::VR4, LoongArch::VR5, LoongArch::VR6, LoongArch::VR7, LoongArch::VR8, LoongArch::VR9, LoongArch::VR10, LoongArch::VR11, LoongArch::VR12, LoongArch::VR13, LoongArch::VR14, LoongArch::VR15, LoongArch::VR16, LoongArch::VR17, LoongArch::VR18, LoongArch::VR19, LoongArch::VR20, LoongArch::VR21, LoongArch::VR22, LoongArch::VR23, LoongArch::VR24, LoongArch::VR25, LoongArch::VR26, LoongArch::VR27, LoongArch::VR28, LoongArch::VR29, LoongArch::VR30, LoongArch::VR31,
776 };
777
778 // LSX128 Bit set.
779 const uint8_t LSX128Bits[] = {
780 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
781 };
782
783 // LASX256 Register Class...
784 const MCPhysReg LASX256[] = {
785 LoongArch::XR0, LoongArch::XR1, LoongArch::XR2, LoongArch::XR3, LoongArch::XR4, LoongArch::XR5, LoongArch::XR6, LoongArch::XR7, LoongArch::XR8, LoongArch::XR9, LoongArch::XR10, LoongArch::XR11, LoongArch::XR12, LoongArch::XR13, LoongArch::XR14, LoongArch::XR15, LoongArch::XR16, LoongArch::XR17, LoongArch::XR18, LoongArch::XR19, LoongArch::XR20, LoongArch::XR21, LoongArch::XR22, LoongArch::XR23, LoongArch::XR24, LoongArch::XR25, LoongArch::XR26, LoongArch::XR27, LoongArch::XR28, LoongArch::XR29, LoongArch::XR30, LoongArch::XR31,
786 };
787
788 // LASX256 Bit set.
789 const uint8_t LASX256Bits[] = {
790 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
791 };
792
793} // end anonymous namespace
794
795
796#ifdef __GNUC__
797#pragma GCC diagnostic push
798#pragma GCC diagnostic ignored "-Woverlength-strings"
799#endif
800extern const char LoongArchRegClassStrings[] = {
801 /* 0 */ "FPR32\0"
802 /* 6 */ "FPR64\0"
803 /* 12 */ "LASX256\0"
804 /* 20 */ "LSX128\0"
805 /* 27 */ "SCR\0"
806 /* 31 */ "CFR\0"
807 /* 35 */ "GPR\0"
808 /* 39 */ "FCSR\0"
809 /* 44 */ "GPRT\0"
810};
811#ifdef __GNUC__
812#pragma GCC diagnostic pop
813#endif
814
815extern const MCRegisterClass LoongArchMCRegisterClasses[] = {
816 { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), LoongArch::FPR32RegClassID, 32, 1, true, false },
817 { GPR, GPRBits, 35, 32, sizeof(GPRBits), LoongArch::GPRRegClassID, 0, 1, true, false },
818 { GPRT, GPRTBits, 44, 17, sizeof(GPRTBits), LoongArch::GPRTRegClassID, 0, 1, true, false },
819 { CFR, CFRBits, 31, 8, sizeof(CFRBits), LoongArch::CFRRegClassID, 0, 1, true, false },
820 { FCSR, FCSRBits, 39, 4, sizeof(FCSRBits), LoongArch::FCSRRegClassID, 32, 1, false, false },
821 { SCR, SCRBits, 27, 4, sizeof(SCRBits), LoongArch::SCRRegClassID, 0, 1, false, false },
822 { FPR64, FPR64Bits, 6, 32, sizeof(FPR64Bits), LoongArch::FPR64RegClassID, 64, 1, true, false },
823 { LSX128, LSX128Bits, 20, 32, sizeof(LSX128Bits), LoongArch::LSX128RegClassID, 128, 1, true, false },
824 { LASX256, LASX256Bits, 12, 32, sizeof(LASX256Bits), LoongArch::LASX256RegClassID, 256, 1, true, false },
825};
826
827// LoongArch Dwarf<->LLVM register mappings.
828extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = {
829 { 0U, LoongArch::R0 },
830 { 1U, LoongArch::R1 },
831 { 2U, LoongArch::R2 },
832 { 3U, LoongArch::R3 },
833 { 4U, LoongArch::R4 },
834 { 5U, LoongArch::R5 },
835 { 6U, LoongArch::R6 },
836 { 7U, LoongArch::R7 },
837 { 8U, LoongArch::R8 },
838 { 9U, LoongArch::R9 },
839 { 10U, LoongArch::R10 },
840 { 11U, LoongArch::R11 },
841 { 12U, LoongArch::R12 },
842 { 13U, LoongArch::R13 },
843 { 14U, LoongArch::R14 },
844 { 15U, LoongArch::R15 },
845 { 16U, LoongArch::R16 },
846 { 17U, LoongArch::R17 },
847 { 18U, LoongArch::R18 },
848 { 19U, LoongArch::R19 },
849 { 20U, LoongArch::R20 },
850 { 21U, LoongArch::R21 },
851 { 22U, LoongArch::R22 },
852 { 23U, LoongArch::R23 },
853 { 24U, LoongArch::R24 },
854 { 25U, LoongArch::R25 },
855 { 26U, LoongArch::R26 },
856 { 27U, LoongArch::R27 },
857 { 28U, LoongArch::R28 },
858 { 29U, LoongArch::R29 },
859 { 30U, LoongArch::R30 },
860 { 31U, LoongArch::R31 },
861 { 32U, LoongArch::F0_64 },
862 { 33U, LoongArch::F1_64 },
863 { 34U, LoongArch::F2_64 },
864 { 35U, LoongArch::F3_64 },
865 { 36U, LoongArch::F4_64 },
866 { 37U, LoongArch::F5_64 },
867 { 38U, LoongArch::F6_64 },
868 { 39U, LoongArch::F7_64 },
869 { 40U, LoongArch::F8_64 },
870 { 41U, LoongArch::F9_64 },
871 { 42U, LoongArch::F10_64 },
872 { 43U, LoongArch::F11_64 },
873 { 44U, LoongArch::F12_64 },
874 { 45U, LoongArch::F13_64 },
875 { 46U, LoongArch::F14_64 },
876 { 47U, LoongArch::F15_64 },
877 { 48U, LoongArch::F16_64 },
878 { 49U, LoongArch::F17_64 },
879 { 50U, LoongArch::F18_64 },
880 { 51U, LoongArch::F19_64 },
881 { 52U, LoongArch::F20_64 },
882 { 53U, LoongArch::F21_64 },
883 { 54U, LoongArch::F22_64 },
884 { 55U, LoongArch::F23_64 },
885 { 56U, LoongArch::F24_64 },
886 { 57U, LoongArch::F25_64 },
887 { 58U, LoongArch::F26_64 },
888 { 59U, LoongArch::F27_64 },
889 { 60U, LoongArch::F28_64 },
890 { 61U, LoongArch::F29_64 },
891 { 62U, LoongArch::F30_64 },
892 { 63U, LoongArch::F31_64 },
893};
894extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L);
895
896extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = {
897 { 0U, LoongArch::R0 },
898 { 1U, LoongArch::R1 },
899 { 2U, LoongArch::R2 },
900 { 3U, LoongArch::R3 },
901 { 4U, LoongArch::R4 },
902 { 5U, LoongArch::R5 },
903 { 6U, LoongArch::R6 },
904 { 7U, LoongArch::R7 },
905 { 8U, LoongArch::R8 },
906 { 9U, LoongArch::R9 },
907 { 10U, LoongArch::R10 },
908 { 11U, LoongArch::R11 },
909 { 12U, LoongArch::R12 },
910 { 13U, LoongArch::R13 },
911 { 14U, LoongArch::R14 },
912 { 15U, LoongArch::R15 },
913 { 16U, LoongArch::R16 },
914 { 17U, LoongArch::R17 },
915 { 18U, LoongArch::R18 },
916 { 19U, LoongArch::R19 },
917 { 20U, LoongArch::R20 },
918 { 21U, LoongArch::R21 },
919 { 22U, LoongArch::R22 },
920 { 23U, LoongArch::R23 },
921 { 24U, LoongArch::R24 },
922 { 25U, LoongArch::R25 },
923 { 26U, LoongArch::R26 },
924 { 27U, LoongArch::R27 },
925 { 28U, LoongArch::R28 },
926 { 29U, LoongArch::R29 },
927 { 30U, LoongArch::R30 },
928 { 31U, LoongArch::R31 },
929 { 32U, LoongArch::F0_64 },
930 { 33U, LoongArch::F1_64 },
931 { 34U, LoongArch::F2_64 },
932 { 35U, LoongArch::F3_64 },
933 { 36U, LoongArch::F4_64 },
934 { 37U, LoongArch::F5_64 },
935 { 38U, LoongArch::F6_64 },
936 { 39U, LoongArch::F7_64 },
937 { 40U, LoongArch::F8_64 },
938 { 41U, LoongArch::F9_64 },
939 { 42U, LoongArch::F10_64 },
940 { 43U, LoongArch::F11_64 },
941 { 44U, LoongArch::F12_64 },
942 { 45U, LoongArch::F13_64 },
943 { 46U, LoongArch::F14_64 },
944 { 47U, LoongArch::F15_64 },
945 { 48U, LoongArch::F16_64 },
946 { 49U, LoongArch::F17_64 },
947 { 50U, LoongArch::F18_64 },
948 { 51U, LoongArch::F19_64 },
949 { 52U, LoongArch::F20_64 },
950 { 53U, LoongArch::F21_64 },
951 { 54U, LoongArch::F22_64 },
952 { 55U, LoongArch::F23_64 },
953 { 56U, LoongArch::F24_64 },
954 { 57U, LoongArch::F25_64 },
955 { 58U, LoongArch::F26_64 },
956 { 59U, LoongArch::F27_64 },
957 { 60U, LoongArch::F28_64 },
958 { 61U, LoongArch::F29_64 },
959 { 62U, LoongArch::F30_64 },
960 { 63U, LoongArch::F31_64 },
961};
962extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L);
963
964extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = {
965 { LoongArch::F0, 32U },
966 { LoongArch::F1, 33U },
967 { LoongArch::F2, 34U },
968 { LoongArch::F3, 35U },
969 { LoongArch::F4, 36U },
970 { LoongArch::F5, 37U },
971 { LoongArch::F6, 38U },
972 { LoongArch::F7, 39U },
973 { LoongArch::F8, 40U },
974 { LoongArch::F9, 41U },
975 { LoongArch::F10, 42U },
976 { LoongArch::F11, 43U },
977 { LoongArch::F12, 44U },
978 { LoongArch::F13, 45U },
979 { LoongArch::F14, 46U },
980 { LoongArch::F15, 47U },
981 { LoongArch::F16, 48U },
982 { LoongArch::F17, 49U },
983 { LoongArch::F18, 50U },
984 { LoongArch::F19, 51U },
985 { LoongArch::F20, 52U },
986 { LoongArch::F21, 53U },
987 { LoongArch::F22, 54U },
988 { LoongArch::F23, 55U },
989 { LoongArch::F24, 56U },
990 { LoongArch::F25, 57U },
991 { LoongArch::F26, 58U },
992 { LoongArch::F27, 59U },
993 { LoongArch::F28, 60U },
994 { LoongArch::F29, 61U },
995 { LoongArch::F30, 62U },
996 { LoongArch::F31, 63U },
997 { LoongArch::R0, 0U },
998 { LoongArch::R1, 1U },
999 { LoongArch::R2, 2U },
1000 { LoongArch::R3, 3U },
1001 { LoongArch::R4, 4U },
1002 { LoongArch::R5, 5U },
1003 { LoongArch::R6, 6U },
1004 { LoongArch::R7, 7U },
1005 { LoongArch::R8, 8U },
1006 { LoongArch::R9, 9U },
1007 { LoongArch::R10, 10U },
1008 { LoongArch::R11, 11U },
1009 { LoongArch::R12, 12U },
1010 { LoongArch::R13, 13U },
1011 { LoongArch::R14, 14U },
1012 { LoongArch::R15, 15U },
1013 { LoongArch::R16, 16U },
1014 { LoongArch::R17, 17U },
1015 { LoongArch::R18, 18U },
1016 { LoongArch::R19, 19U },
1017 { LoongArch::R20, 20U },
1018 { LoongArch::R21, 21U },
1019 { LoongArch::R22, 22U },
1020 { LoongArch::R23, 23U },
1021 { LoongArch::R24, 24U },
1022 { LoongArch::R25, 25U },
1023 { LoongArch::R26, 26U },
1024 { LoongArch::R27, 27U },
1025 { LoongArch::R28, 28U },
1026 { LoongArch::R29, 29U },
1027 { LoongArch::R30, 30U },
1028 { LoongArch::R31, 31U },
1029 { LoongArch::VR0, 32U },
1030 { LoongArch::VR1, 33U },
1031 { LoongArch::VR2, 34U },
1032 { LoongArch::VR3, 35U },
1033 { LoongArch::VR4, 36U },
1034 { LoongArch::VR5, 37U },
1035 { LoongArch::VR6, 38U },
1036 { LoongArch::VR7, 39U },
1037 { LoongArch::VR8, 40U },
1038 { LoongArch::VR9, 41U },
1039 { LoongArch::VR10, 42U },
1040 { LoongArch::VR11, 43U },
1041 { LoongArch::VR12, 44U },
1042 { LoongArch::VR13, 45U },
1043 { LoongArch::VR14, 46U },
1044 { LoongArch::VR15, 47U },
1045 { LoongArch::VR16, 48U },
1046 { LoongArch::VR17, 49U },
1047 { LoongArch::VR18, 50U },
1048 { LoongArch::VR19, 51U },
1049 { LoongArch::VR20, 52U },
1050 { LoongArch::VR21, 53U },
1051 { LoongArch::VR22, 54U },
1052 { LoongArch::VR23, 55U },
1053 { LoongArch::VR24, 56U },
1054 { LoongArch::VR25, 57U },
1055 { LoongArch::VR26, 58U },
1056 { LoongArch::VR27, 59U },
1057 { LoongArch::VR28, 60U },
1058 { LoongArch::VR29, 61U },
1059 { LoongArch::VR30, 62U },
1060 { LoongArch::VR31, 63U },
1061 { LoongArch::XR0, 32U },
1062 { LoongArch::XR1, 33U },
1063 { LoongArch::XR2, 34U },
1064 { LoongArch::XR3, 35U },
1065 { LoongArch::XR4, 36U },
1066 { LoongArch::XR5, 37U },
1067 { LoongArch::XR6, 38U },
1068 { LoongArch::XR7, 39U },
1069 { LoongArch::XR8, 40U },
1070 { LoongArch::XR9, 41U },
1071 { LoongArch::XR10, 42U },
1072 { LoongArch::XR11, 43U },
1073 { LoongArch::XR12, 44U },
1074 { LoongArch::XR13, 45U },
1075 { LoongArch::XR14, 46U },
1076 { LoongArch::XR15, 47U },
1077 { LoongArch::XR16, 48U },
1078 { LoongArch::XR17, 49U },
1079 { LoongArch::XR18, 50U },
1080 { LoongArch::XR19, 51U },
1081 { LoongArch::XR20, 52U },
1082 { LoongArch::XR21, 53U },
1083 { LoongArch::XR22, 54U },
1084 { LoongArch::XR23, 55U },
1085 { LoongArch::XR24, 56U },
1086 { LoongArch::XR25, 57U },
1087 { LoongArch::XR26, 58U },
1088 { LoongArch::XR27, 59U },
1089 { LoongArch::XR28, 60U },
1090 { LoongArch::XR29, 61U },
1091 { LoongArch::XR30, 62U },
1092 { LoongArch::XR31, 63U },
1093 { LoongArch::F0_64, 32U },
1094 { LoongArch::F1_64, 33U },
1095 { LoongArch::F2_64, 34U },
1096 { LoongArch::F3_64, 35U },
1097 { LoongArch::F4_64, 36U },
1098 { LoongArch::F5_64, 37U },
1099 { LoongArch::F6_64, 38U },
1100 { LoongArch::F7_64, 39U },
1101 { LoongArch::F8_64, 40U },
1102 { LoongArch::F9_64, 41U },
1103 { LoongArch::F10_64, 42U },
1104 { LoongArch::F11_64, 43U },
1105 { LoongArch::F12_64, 44U },
1106 { LoongArch::F13_64, 45U },
1107 { LoongArch::F14_64, 46U },
1108 { LoongArch::F15_64, 47U },
1109 { LoongArch::F16_64, 48U },
1110 { LoongArch::F17_64, 49U },
1111 { LoongArch::F18_64, 50U },
1112 { LoongArch::F19_64, 51U },
1113 { LoongArch::F20_64, 52U },
1114 { LoongArch::F21_64, 53U },
1115 { LoongArch::F22_64, 54U },
1116 { LoongArch::F23_64, 55U },
1117 { LoongArch::F24_64, 56U },
1118 { LoongArch::F25_64, 57U },
1119 { LoongArch::F26_64, 58U },
1120 { LoongArch::F27_64, 59U },
1121 { LoongArch::F28_64, 60U },
1122 { LoongArch::F29_64, 61U },
1123 { LoongArch::F30_64, 62U },
1124 { LoongArch::F31_64, 63U },
1125};
1126extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf);
1127
1128extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = {
1129 { LoongArch::F0, 32U },
1130 { LoongArch::F1, 33U },
1131 { LoongArch::F2, 34U },
1132 { LoongArch::F3, 35U },
1133 { LoongArch::F4, 36U },
1134 { LoongArch::F5, 37U },
1135 { LoongArch::F6, 38U },
1136 { LoongArch::F7, 39U },
1137 { LoongArch::F8, 40U },
1138 { LoongArch::F9, 41U },
1139 { LoongArch::F10, 42U },
1140 { LoongArch::F11, 43U },
1141 { LoongArch::F12, 44U },
1142 { LoongArch::F13, 45U },
1143 { LoongArch::F14, 46U },
1144 { LoongArch::F15, 47U },
1145 { LoongArch::F16, 48U },
1146 { LoongArch::F17, 49U },
1147 { LoongArch::F18, 50U },
1148 { LoongArch::F19, 51U },
1149 { LoongArch::F20, 52U },
1150 { LoongArch::F21, 53U },
1151 { LoongArch::F22, 54U },
1152 { LoongArch::F23, 55U },
1153 { LoongArch::F24, 56U },
1154 { LoongArch::F25, 57U },
1155 { LoongArch::F26, 58U },
1156 { LoongArch::F27, 59U },
1157 { LoongArch::F28, 60U },
1158 { LoongArch::F29, 61U },
1159 { LoongArch::F30, 62U },
1160 { LoongArch::F31, 63U },
1161 { LoongArch::R0, 0U },
1162 { LoongArch::R1, 1U },
1163 { LoongArch::R2, 2U },
1164 { LoongArch::R3, 3U },
1165 { LoongArch::R4, 4U },
1166 { LoongArch::R5, 5U },
1167 { LoongArch::R6, 6U },
1168 { LoongArch::R7, 7U },
1169 { LoongArch::R8, 8U },
1170 { LoongArch::R9, 9U },
1171 { LoongArch::R10, 10U },
1172 { LoongArch::R11, 11U },
1173 { LoongArch::R12, 12U },
1174 { LoongArch::R13, 13U },
1175 { LoongArch::R14, 14U },
1176 { LoongArch::R15, 15U },
1177 { LoongArch::R16, 16U },
1178 { LoongArch::R17, 17U },
1179 { LoongArch::R18, 18U },
1180 { LoongArch::R19, 19U },
1181 { LoongArch::R20, 20U },
1182 { LoongArch::R21, 21U },
1183 { LoongArch::R22, 22U },
1184 { LoongArch::R23, 23U },
1185 { LoongArch::R24, 24U },
1186 { LoongArch::R25, 25U },
1187 { LoongArch::R26, 26U },
1188 { LoongArch::R27, 27U },
1189 { LoongArch::R28, 28U },
1190 { LoongArch::R29, 29U },
1191 { LoongArch::R30, 30U },
1192 { LoongArch::R31, 31U },
1193 { LoongArch::VR0, 32U },
1194 { LoongArch::VR1, 33U },
1195 { LoongArch::VR2, 34U },
1196 { LoongArch::VR3, 35U },
1197 { LoongArch::VR4, 36U },
1198 { LoongArch::VR5, 37U },
1199 { LoongArch::VR6, 38U },
1200 { LoongArch::VR7, 39U },
1201 { LoongArch::VR8, 40U },
1202 { LoongArch::VR9, 41U },
1203 { LoongArch::VR10, 42U },
1204 { LoongArch::VR11, 43U },
1205 { LoongArch::VR12, 44U },
1206 { LoongArch::VR13, 45U },
1207 { LoongArch::VR14, 46U },
1208 { LoongArch::VR15, 47U },
1209 { LoongArch::VR16, 48U },
1210 { LoongArch::VR17, 49U },
1211 { LoongArch::VR18, 50U },
1212 { LoongArch::VR19, 51U },
1213 { LoongArch::VR20, 52U },
1214 { LoongArch::VR21, 53U },
1215 { LoongArch::VR22, 54U },
1216 { LoongArch::VR23, 55U },
1217 { LoongArch::VR24, 56U },
1218 { LoongArch::VR25, 57U },
1219 { LoongArch::VR26, 58U },
1220 { LoongArch::VR27, 59U },
1221 { LoongArch::VR28, 60U },
1222 { LoongArch::VR29, 61U },
1223 { LoongArch::VR30, 62U },
1224 { LoongArch::VR31, 63U },
1225 { LoongArch::XR0, 32U },
1226 { LoongArch::XR1, 33U },
1227 { LoongArch::XR2, 34U },
1228 { LoongArch::XR3, 35U },
1229 { LoongArch::XR4, 36U },
1230 { LoongArch::XR5, 37U },
1231 { LoongArch::XR6, 38U },
1232 { LoongArch::XR7, 39U },
1233 { LoongArch::XR8, 40U },
1234 { LoongArch::XR9, 41U },
1235 { LoongArch::XR10, 42U },
1236 { LoongArch::XR11, 43U },
1237 { LoongArch::XR12, 44U },
1238 { LoongArch::XR13, 45U },
1239 { LoongArch::XR14, 46U },
1240 { LoongArch::XR15, 47U },
1241 { LoongArch::XR16, 48U },
1242 { LoongArch::XR17, 49U },
1243 { LoongArch::XR18, 50U },
1244 { LoongArch::XR19, 51U },
1245 { LoongArch::XR20, 52U },
1246 { LoongArch::XR21, 53U },
1247 { LoongArch::XR22, 54U },
1248 { LoongArch::XR23, 55U },
1249 { LoongArch::XR24, 56U },
1250 { LoongArch::XR25, 57U },
1251 { LoongArch::XR26, 58U },
1252 { LoongArch::XR27, 59U },
1253 { LoongArch::XR28, 60U },
1254 { LoongArch::XR29, 61U },
1255 { LoongArch::XR30, 62U },
1256 { LoongArch::XR31, 63U },
1257 { LoongArch::F0_64, 32U },
1258 { LoongArch::F1_64, 33U },
1259 { LoongArch::F2_64, 34U },
1260 { LoongArch::F3_64, 35U },
1261 { LoongArch::F4_64, 36U },
1262 { LoongArch::F5_64, 37U },
1263 { LoongArch::F6_64, 38U },
1264 { LoongArch::F7_64, 39U },
1265 { LoongArch::F8_64, 40U },
1266 { LoongArch::F9_64, 41U },
1267 { LoongArch::F10_64, 42U },
1268 { LoongArch::F11_64, 43U },
1269 { LoongArch::F12_64, 44U },
1270 { LoongArch::F13_64, 45U },
1271 { LoongArch::F14_64, 46U },
1272 { LoongArch::F15_64, 47U },
1273 { LoongArch::F16_64, 48U },
1274 { LoongArch::F17_64, 49U },
1275 { LoongArch::F18_64, 50U },
1276 { LoongArch::F19_64, 51U },
1277 { LoongArch::F20_64, 52U },
1278 { LoongArch::F21_64, 53U },
1279 { LoongArch::F22_64, 54U },
1280 { LoongArch::F23_64, 55U },
1281 { LoongArch::F24_64, 56U },
1282 { LoongArch::F25_64, 57U },
1283 { LoongArch::F26_64, 58U },
1284 { LoongArch::F27_64, 59U },
1285 { LoongArch::F28_64, 60U },
1286 { LoongArch::F29_64, 61U },
1287 { LoongArch::F30_64, 62U },
1288 { LoongArch::F31_64, 63U },
1289};
1290extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf);
1291
1292extern const uint16_t LoongArchRegEncodingTable[] = {
1293 0,
1294 0,
1295 1,
1296 2,
1297 3,
1298 4,
1299 5,
1300 6,
1301 7,
1302 8,
1303 9,
1304 10,
1305 11,
1306 12,
1307 13,
1308 14,
1309 15,
1310 16,
1311 17,
1312 18,
1313 19,
1314 20,
1315 21,
1316 22,
1317 23,
1318 24,
1319 25,
1320 26,
1321 27,
1322 28,
1323 29,
1324 30,
1325 31,
1326 0,
1327 1,
1328 2,
1329 3,
1330 4,
1331 5,
1332 6,
1333 7,
1334 0,
1335 1,
1336 2,
1337 3,
1338 0,
1339 1,
1340 2,
1341 3,
1342 4,
1343 5,
1344 6,
1345 7,
1346 8,
1347 9,
1348 10,
1349 11,
1350 12,
1351 13,
1352 14,
1353 15,
1354 16,
1355 17,
1356 18,
1357 19,
1358 20,
1359 21,
1360 22,
1361 23,
1362 24,
1363 25,
1364 26,
1365 27,
1366 28,
1367 29,
1368 30,
1369 31,
1370 0,
1371 1,
1372 2,
1373 3,
1374 0,
1375 1,
1376 2,
1377 3,
1378 4,
1379 5,
1380 6,
1381 7,
1382 8,
1383 9,
1384 10,
1385 11,
1386 12,
1387 13,
1388 14,
1389 15,
1390 16,
1391 17,
1392 18,
1393 19,
1394 20,
1395 21,
1396 22,
1397 23,
1398 24,
1399 25,
1400 26,
1401 27,
1402 28,
1403 29,
1404 30,
1405 31,
1406 0,
1407 1,
1408 2,
1409 3,
1410 4,
1411 5,
1412 6,
1413 7,
1414 8,
1415 9,
1416 10,
1417 11,
1418 12,
1419 13,
1420 14,
1421 15,
1422 16,
1423 17,
1424 18,
1425 19,
1426 20,
1427 21,
1428 22,
1429 23,
1430 24,
1431 25,
1432 26,
1433 27,
1434 28,
1435 29,
1436 30,
1437 31,
1438 0,
1439 1,
1440 2,
1441 3,
1442 4,
1443 5,
1444 6,
1445 7,
1446 8,
1447 9,
1448 10,
1449 11,
1450 12,
1451 13,
1452 14,
1453 15,
1454 16,
1455 17,
1456 18,
1457 19,
1458 20,
1459 21,
1460 22,
1461 23,
1462 24,
1463 25,
1464 26,
1465 27,
1466 28,
1467 29,
1468 30,
1469 31,
1470};
1471static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1472 RI->InitMCRegisterInfo(LoongArchRegDesc, 177, RA, PC, LoongArchMCRegisterClasses, 9, LoongArchRegUnitRoots, 80, LoongArchRegDiffLists, LoongArchLaneMaskLists, LoongArchRegStrings, LoongArchRegClassStrings, LoongArchSubRegIdxLists, 4,
1473LoongArchRegEncodingTable);
1474
1475 switch (DwarfFlavour) {
1476 default:
1477 llvm_unreachable("Unknown DWARF flavour");
1478 case 0:
1479 RI->mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
1480 break;
1481 }
1482 switch (EHFlavour) {
1483 default:
1484 llvm_unreachable("Unknown DWARF flavour");
1485 case 0:
1486 RI->mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
1487 break;
1488 }
1489 switch (DwarfFlavour) {
1490 default:
1491 llvm_unreachable("Unknown DWARF flavour");
1492 case 0:
1493 RI->mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
1494 break;
1495 }
1496 switch (EHFlavour) {
1497 default:
1498 llvm_unreachable("Unknown DWARF flavour");
1499 case 0:
1500 RI->mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
1501 break;
1502 }
1503}
1504
1505} // end namespace llvm
1506
1507#endif // GET_REGINFO_MC_DESC
1508
1509/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1510|* *|
1511|* Register Information Header Fragment *|
1512|* *|
1513|* Automatically generated file, do not edit! *|
1514|* *|
1515\*===----------------------------------------------------------------------===*/
1516
1517
1518#ifdef GET_REGINFO_HEADER
1519#undef GET_REGINFO_HEADER
1520
1521#include "llvm/CodeGen/TargetRegisterInfo.h"
1522
1523namespace llvm {
1524
1525class LoongArchFrameLowering;
1526
1527struct LoongArchGenRegisterInfo : public TargetRegisterInfo {
1528 explicit LoongArchGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
1529 unsigned PC = 0, unsigned HwMode = 0);
1530 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
1531 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1532 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
1533 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
1534 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
1535 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1536 unsigned getRegUnitWeight(unsigned RegUnit) const override;
1537 unsigned getNumRegPressureSets() const override;
1538 const char *getRegPressureSetName(unsigned Idx) const override;
1539 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
1540 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1541 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
1542 ArrayRef<const char *> getRegMaskNames() const override;
1543 ArrayRef<const uint32_t *> getRegMasks() const override;
1544 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
1545 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
1546 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
1547 bool isConstantPhysReg(MCRegister PhysReg) const override final;
1548 /// Devirtualized TargetFrameLowering.
1549 static const LoongArchFrameLowering *getFrameLowering(
1550 const MachineFunction &MF);
1551};
1552
1553namespace LoongArch { // Register classes
1554 extern const TargetRegisterClass FPR32RegClass;
1555 extern const TargetRegisterClass GPRRegClass;
1556 extern const TargetRegisterClass GPRTRegClass;
1557 extern const TargetRegisterClass CFRRegClass;
1558 extern const TargetRegisterClass FCSRRegClass;
1559 extern const TargetRegisterClass SCRRegClass;
1560 extern const TargetRegisterClass FPR64RegClass;
1561 extern const TargetRegisterClass LSX128RegClass;
1562 extern const TargetRegisterClass LASX256RegClass;
1563} // end namespace LoongArch
1564
1565} // end namespace llvm
1566
1567#endif // GET_REGINFO_HEADER
1568
1569/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1570|* *|
1571|* Target Register and Register Classes Information *|
1572|* *|
1573|* Automatically generated file, do not edit! *|
1574|* *|
1575\*===----------------------------------------------------------------------===*/
1576
1577
1578#ifdef GET_REGINFO_TARGET_DESC
1579#undef GET_REGINFO_TARGET_DESC
1580
1581namespace llvm {
1582
1583extern const MCRegisterClass LoongArchMCRegisterClasses[];
1584
1585static const MVT::SimpleValueType VTLists[] = {
1586 /* 0 */ MVT::i32, MVT::Other,
1587 /* 2 */ MVT::i64, MVT::Other,
1588 /* 4 */ MVT::f32, MVT::Other,
1589 /* 6 */ MVT::f64, MVT::Other,
1590 /* 8 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::Other,
1591 /* 15 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
1592};
1593
1594static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_128", "" };
1595
1596static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
1597 { 65535, 65535 },
1598 { 0, 32 }, // sub_32
1599 { 0, 64 }, // sub_64
1600 { 0, 128 }, // sub_128
1601 { 65535, 65535 },
1602 { 0, 32 }, // sub_32
1603 { 0, 64 }, // sub_64
1604 { 0, 128 }, // sub_128
1605};
1606
1607
1608static const LaneBitmask SubRegIndexLaneMaskTable[] = {
1609 LaneBitmask::getAll(),
1610 LaneBitmask(0x0000000000000001), // sub_32
1611 LaneBitmask(0x0000000000000001), // sub_64
1612 LaneBitmask(0x0000000000000001), // sub_128
1613 };
1614
1615
1616
1617static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
1618 // Mode = 0 (Default)
1619 { 32, 32, 32, /*VTLists+*/4 }, // FPR32
1620 { 32, 32, 32, /*VTLists+*/0 }, // GPR
1621 { 32, 32, 32, /*VTLists+*/0 }, // GPRT
1622 { 32, 32, 32, /*VTLists+*/0 }, // CFR
1623 { 32, 32, 32, /*VTLists+*/0 }, // FCSR
1624 { 32, 32, 32, /*VTLists+*/0 }, // SCR
1625 { 64, 64, 64, /*VTLists+*/6 }, // FPR64
1626 { 128, 128, 128, /*VTLists+*/8 }, // LSX128
1627 { 256, 256, 256, /*VTLists+*/15 }, // LASX256
1628 // Mode = 1 (LA64)
1629 { 32, 32, 32, /*VTLists+*/4 }, // FPR32
1630 { 64, 64, 64, /*VTLists+*/2 }, // GPR
1631 { 64, 64, 64, /*VTLists+*/2 }, // GPRT
1632 { 64, 64, 64, /*VTLists+*/2 }, // CFR
1633 { 32, 32, 32, /*VTLists+*/0 }, // FCSR
1634 { 64, 64, 64, /*VTLists+*/2 }, // SCR
1635 { 64, 64, 64, /*VTLists+*/6 }, // FPR64
1636 { 128, 128, 128, /*VTLists+*/8 }, // LSX128
1637 { 256, 256, 256, /*VTLists+*/15 }, // LASX256
1638};
1639
1640static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1641
1642static const uint32_t FPR32SubClassMask[] = {
1643 0x00000001,
1644 0x000001c0, // sub_32
1645};
1646
1647static const uint32_t GPRSubClassMask[] = {
1648 0x00000006,
1649};
1650
1651static const uint32_t GPRTSubClassMask[] = {
1652 0x00000004,
1653};
1654
1655static const uint32_t CFRSubClassMask[] = {
1656 0x00000008,
1657};
1658
1659static const uint32_t FCSRSubClassMask[] = {
1660 0x00000010,
1661};
1662
1663static const uint32_t SCRSubClassMask[] = {
1664 0x00000020,
1665};
1666
1667static const uint32_t FPR64SubClassMask[] = {
1668 0x00000040,
1669 0x00000180, // sub_64
1670};
1671
1672static const uint32_t LSX128SubClassMask[] = {
1673 0x00000080,
1674 0x00000100, // sub_128
1675};
1676
1677static const uint32_t LASX256SubClassMask[] = {
1678 0x00000100,
1679};
1680
1681static const uint16_t SuperRegIdxSeqs[] = {
1682 /* 0 */ 1, 0,
1683 /* 2 */ 2, 0,
1684 /* 4 */ 3, 0,
1685};
1686
1687static const TargetRegisterClass *const GPRTSuperclasses[] = {
1688 &LoongArch::GPRRegClass,
1689 nullptr
1690};
1691
1692
1693namespace LoongArch { // Register class instances
1694 extern const TargetRegisterClass FPR32RegClass = {
1695 &LoongArchMCRegisterClasses[FPR32RegClassID],
1696 FPR32SubClassMask,
1697 SuperRegIdxSeqs + 0,
1698 LaneBitmask(0x0000000000000001),
1699 0,
1700 false,
1701 0x00, /* TSFlags */
1702 false, /* HasDisjunctSubRegs */
1703 false, /* CoveredBySubRegs */
1704 NullRegClasses,
1705 nullptr
1706 };
1707
1708 extern const TargetRegisterClass GPRRegClass = {
1709 &LoongArchMCRegisterClasses[GPRRegClassID],
1710 GPRSubClassMask,
1711 SuperRegIdxSeqs + 1,
1712 LaneBitmask(0x0000000000000001),
1713 0,
1714 false,
1715 0x00, /* TSFlags */
1716 false, /* HasDisjunctSubRegs */
1717 false, /* CoveredBySubRegs */
1718 NullRegClasses,
1719 nullptr
1720 };
1721
1722 extern const TargetRegisterClass GPRTRegClass = {
1723 &LoongArchMCRegisterClasses[GPRTRegClassID],
1724 GPRTSubClassMask,
1725 SuperRegIdxSeqs + 1,
1726 LaneBitmask(0x0000000000000001),
1727 0,
1728 false,
1729 0x00, /* TSFlags */
1730 false, /* HasDisjunctSubRegs */
1731 false, /* CoveredBySubRegs */
1732 GPRTSuperclasses,
1733 nullptr
1734 };
1735
1736 extern const TargetRegisterClass CFRRegClass = {
1737 &LoongArchMCRegisterClasses[CFRRegClassID],
1738 CFRSubClassMask,
1739 SuperRegIdxSeqs + 1,
1740 LaneBitmask(0x0000000000000001),
1741 0,
1742 false,
1743 0x00, /* TSFlags */
1744 false, /* HasDisjunctSubRegs */
1745 false, /* CoveredBySubRegs */
1746 NullRegClasses,
1747 nullptr
1748 };
1749
1750 extern const TargetRegisterClass FCSRRegClass = {
1751 &LoongArchMCRegisterClasses[FCSRRegClassID],
1752 FCSRSubClassMask,
1753 SuperRegIdxSeqs + 1,
1754 LaneBitmask(0x0000000000000001),
1755 0,
1756 false,
1757 0x00, /* TSFlags */
1758 false, /* HasDisjunctSubRegs */
1759 false, /* CoveredBySubRegs */
1760 NullRegClasses,
1761 nullptr
1762 };
1763
1764 extern const TargetRegisterClass SCRRegClass = {
1765 &LoongArchMCRegisterClasses[SCRRegClassID],
1766 SCRSubClassMask,
1767 SuperRegIdxSeqs + 1,
1768 LaneBitmask(0x0000000000000001),
1769 0,
1770 false,
1771 0x00, /* TSFlags */
1772 false, /* HasDisjunctSubRegs */
1773 false, /* CoveredBySubRegs */
1774 NullRegClasses,
1775 nullptr
1776 };
1777
1778 extern const TargetRegisterClass FPR64RegClass = {
1779 &LoongArchMCRegisterClasses[FPR64RegClassID],
1780 FPR64SubClassMask,
1781 SuperRegIdxSeqs + 2,
1782 LaneBitmask(0x0000000000000001),
1783 0,
1784 false,
1785 0x00, /* TSFlags */
1786 false, /* HasDisjunctSubRegs */
1787 false, /* CoveredBySubRegs */
1788 NullRegClasses,
1789 nullptr
1790 };
1791
1792 extern const TargetRegisterClass LSX128RegClass = {
1793 &LoongArchMCRegisterClasses[LSX128RegClassID],
1794 LSX128SubClassMask,
1795 SuperRegIdxSeqs + 4,
1796 LaneBitmask(0x0000000000000001),
1797 0,
1798 false,
1799 0x00, /* TSFlags */
1800 false, /* HasDisjunctSubRegs */
1801 false, /* CoveredBySubRegs */
1802 NullRegClasses,
1803 nullptr
1804 };
1805
1806 extern const TargetRegisterClass LASX256RegClass = {
1807 &LoongArchMCRegisterClasses[LASX256RegClassID],
1808 LASX256SubClassMask,
1809 SuperRegIdxSeqs + 1,
1810 LaneBitmask(0x0000000000000001),
1811 0,
1812 false,
1813 0x00, /* TSFlags */
1814 false, /* HasDisjunctSubRegs */
1815 false, /* CoveredBySubRegs */
1816 NullRegClasses,
1817 nullptr
1818 };
1819
1820} // end namespace LoongArch
1821
1822namespace {
1823 const TargetRegisterClass *const RegisterClasses[] = {
1824 &LoongArch::FPR32RegClass,
1825 &LoongArch::GPRRegClass,
1826 &LoongArch::GPRTRegClass,
1827 &LoongArch::CFRRegClass,
1828 &LoongArch::FCSRRegClass,
1829 &LoongArch::SCRRegClass,
1830 &LoongArch::FPR64RegClass,
1831 &LoongArch::LSX128RegClass,
1832 &LoongArch::LASX256RegClass,
1833 };
1834} // end anonymous namespace
1835
1836static const uint8_t CostPerUseTable[] = {
18370, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
1838
1839
1840static const bool InAllocatableClassTable[] = {
1841false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
1842
1843
1844static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors
1845CostPerUseTable, 1, InAllocatableClassTable};
1846
1847unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
1848 static const uint8_t Rows[1][3] = {
1849 { LoongArch::sub_32, LoongArch::sub_64, 0, },
1850 };
1851
1852 --IdxA; assert(IdxA < 3); (void) IdxA;
1853 --IdxB; assert(IdxB < 3);
1854 return Rows[0][IdxB];
1855}
1856
1857 struct MaskRolOp {
1858 LaneBitmask Mask;
1859 uint8_t RotateLeft;
1860 };
1861 static const MaskRolOp LaneMaskComposeSequences[] = {
1862 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
1863 };
1864 static const uint8_t CompositeSequences[] = {
1865 0, // to sub_32
1866 0, // to sub_64
1867 0 // to sub_128
1868 };
1869
1870LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1871 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
1872 LaneBitmask Result;
1873 for (const MaskRolOp *Ops =
1874 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1875 Ops->Mask.any(); ++Ops) {
1876 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
1877 if (unsigned S = Ops->RotateLeft)
1878 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
1879 else
1880 Result |= LaneBitmask(M);
1881 }
1882 return Result;
1883}
1884
1885LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
1886 LaneMask &= getSubRegIndexLaneMask(IdxA);
1887 --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
1888 LaneBitmask Result;
1889 for (const MaskRolOp *Ops =
1890 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
1891 Ops->Mask.any(); ++Ops) {
1892 LaneBitmask::Type M = LaneMask.getAsInteger();
1893 if (unsigned S = Ops->RotateLeft)
1894 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
1895 else
1896 Result |= LaneBitmask(M);
1897 }
1898 return Result;
1899}
1900
1901const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1902 static const uint8_t Table[9][3] = {
1903 { // FPR32
1904 0, // sub_32
1905 0, // sub_64
1906 0, // sub_128
1907 },
1908 { // GPR
1909 0, // sub_32
1910 0, // sub_64
1911 0, // sub_128
1912 },
1913 { // GPRT
1914 0, // sub_32
1915 0, // sub_64
1916 0, // sub_128
1917 },
1918 { // CFR
1919 0, // sub_32
1920 0, // sub_64
1921 0, // sub_128
1922 },
1923 { // FCSR
1924 0, // sub_32
1925 0, // sub_64
1926 0, // sub_128
1927 },
1928 { // SCR
1929 0, // sub_32
1930 0, // sub_64
1931 0, // sub_128
1932 },
1933 { // FPR64
1934 7, // sub_32 -> FPR64
1935 0, // sub_64
1936 0, // sub_128
1937 },
1938 { // LSX128
1939 8, // sub_32 -> LSX128
1940 8, // sub_64 -> LSX128
1941 0, // sub_128
1942 },
1943 { // LASX256
1944 9, // sub_32 -> LASX256
1945 9, // sub_64 -> LASX256
1946 9, // sub_128 -> LASX256
1947 },
1948 };
1949 assert(RC && "Missing regclass");
1950 if (!Idx) return RC;
1951 --Idx;
1952 assert(Idx < 3 && "Bad subreg");
1953 unsigned TV = Table[RC->getID()][Idx];
1954 return TV ? getRegClass(TV - 1) : nullptr;
1955}
1956
1957const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
1958 static const uint8_t Table[9][3] = {
1959 { // FPR32
1960 0, // FPR32:sub_32
1961 0, // FPR32:sub_64
1962 0, // FPR32:sub_128
1963 },
1964 { // GPR
1965 0, // GPR:sub_32
1966 0, // GPR:sub_64
1967 0, // GPR:sub_128
1968 },
1969 { // GPRT
1970 0, // GPRT:sub_32
1971 0, // GPRT:sub_64
1972 0, // GPRT:sub_128
1973 },
1974 { // CFR
1975 0, // CFR:sub_32
1976 0, // CFR:sub_64
1977 0, // CFR:sub_128
1978 },
1979 { // FCSR
1980 0, // FCSR:sub_32
1981 0, // FCSR:sub_64
1982 0, // FCSR:sub_128
1983 },
1984 { // SCR
1985 0, // SCR:sub_32
1986 0, // SCR:sub_64
1987 0, // SCR:sub_128
1988 },
1989 { // FPR64
1990 1, // FPR64:sub_32 -> FPR32
1991 0, // FPR64:sub_64
1992 0, // FPR64:sub_128
1993 },
1994 { // LSX128
1995 1, // LSX128:sub_32 -> FPR32
1996 7, // LSX128:sub_64 -> FPR64
1997 0, // LSX128:sub_128
1998 },
1999 { // LASX256
2000 1, // LASX256:sub_32 -> FPR32
2001 7, // LASX256:sub_64 -> FPR64
2002 8, // LASX256:sub_128 -> LSX128
2003 },
2004 };
2005 assert(RC && "Missing regclass");
2006 if (!Idx) return RC;
2007 --Idx;
2008 assert(Idx < 3 && "Bad subreg");
2009 unsigned TV = Table[RC->getID()][Idx];
2010 return TV ? getRegClass(TV - 1) : nullptr;
2011}
2012
2013/// Get the weight in units of pressure for this register class.
2014const RegClassWeight &LoongArchGenRegisterInfo::
2015getRegClassWeight(const TargetRegisterClass *RC) const {
2016 static const RegClassWeight RCWeightTable[] = {
2017 {1, 32}, // FPR32
2018 {1, 32}, // GPR
2019 {1, 17}, // GPRT
2020 {1, 8}, // CFR
2021 {0, 0}, // FCSR
2022 {0, 0}, // SCR
2023 {1, 32}, // FPR64
2024 {1, 32}, // LSX128
2025 {1, 32}, // LASX256
2026 };
2027 return RCWeightTable[RC->getID()];
2028}
2029
2030/// Get the weight in units of pressure for this register unit.
2031unsigned LoongArchGenRegisterInfo::
2032getRegUnitWeight(unsigned RegUnit) const {
2033 assert(RegUnit < 80 && "invalid register unit");
2034 // All register units have unit weight.
2035 return 1;
2036}
2037
2038
2039// Get the number of dimensions of register pressure.
2040unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const {
2041 return 4;
2042}
2043
2044// Get the name of this register unit pressure set.
2045const char *LoongArchGenRegisterInfo::
2046getRegPressureSetName(unsigned Idx) const {
2047 static const char *PressureNameTable[] = {
2048 "CFR",
2049 "GPRT",
2050 "FPR32",
2051 "GPR",
2052 };
2053 return PressureNameTable[Idx];
2054}
2055
2056// Get the register unit pressure limit for this dimension.
2057// This limit must be adjusted dynamically for reserved registers.
2058unsigned LoongArchGenRegisterInfo::
2059getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
2060 static const uint8_t PressureLimitTable[] = {
2061 8, // 0: CFR
2062 17, // 1: GPRT
2063 32, // 2: FPR32
2064 32, // 3: GPR
2065 };
2066 return PressureLimitTable[Idx];
2067}
2068
2069/// Table of pressure sets per register class or unit.
2070static const int RCSetsTable[] = {
2071 /* 0 */ 0, -1,
2072 /* 2 */ 2, -1,
2073 /* 4 */ 1, 3, -1,
2074};
2075
2076/// Get the dimensions of register pressure impacted by this register class.
2077/// Returns a -1 terminated array of pressure set IDs
2078const int *LoongArchGenRegisterInfo::
2079getRegClassPressureSets(const TargetRegisterClass *RC) const {
2080 static const uint8_t RCSetStartTable[] = {
2081 2,5,4,0,1,1,2,2,2,};
2082 return &RCSetsTable[RCSetStartTable[RC->getID()]];
2083}
2084
2085/// Get the dimensions of register pressure impacted by this register unit.
2086/// Returns a -1 terminated array of pressure set IDs
2087const int *LoongArchGenRegisterInfo::
2088getRegUnitPressureSets(unsigned RegUnit) const {
2089 assert(RegUnit < 80 && "invalid register unit");
2090 static const uint8_t RUSetStartTable[] = {
2091 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,};
2092 return &RCSetsTable[RUSetStartTable[RegUnit]];
2093}
2094
2095extern const MCRegisterDesc LoongArchRegDesc[];
2096extern const int16_t LoongArchRegDiffLists[];
2097extern const LaneBitmask LoongArchLaneMaskLists[];
2098extern const char LoongArchRegStrings[];
2099extern const char LoongArchRegClassStrings[];
2100extern const MCPhysReg LoongArchRegUnitRoots[][2];
2101extern const uint16_t LoongArchSubRegIdxLists[];
2102extern const uint16_t LoongArchRegEncodingTable[];
2103// LoongArch Dwarf<->LLVM register mappings.
2104extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[];
2105extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize;
2106
2107extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[];
2108extern const unsigned LoongArchEHFlavour0Dwarf2LSize;
2109
2110extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[];
2111extern const unsigned LoongArchDwarfFlavour0L2DwarfSize;
2112
2113extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[];
2114extern const unsigned LoongArchEHFlavour0L2DwarfSize;
2115
2116LoongArchGenRegisterInfo::
2117LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
2118 unsigned PC, unsigned HwMode)
2119 : TargetRegisterInfo(&LoongArchRegInfoDesc, RegisterClasses, RegisterClasses+9,
2120 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
2121 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
2122 InitMCRegisterInfo(LoongArchRegDesc, 177, RA, PC,
2123 LoongArchMCRegisterClasses, 9,
2124 LoongArchRegUnitRoots,
2125 80,
2126 LoongArchRegDiffLists,
2127 LoongArchLaneMaskLists,
2128 LoongArchRegStrings,
2129 LoongArchRegClassStrings,
2130 LoongArchSubRegIdxLists,
2131 4,
2132 LoongArchRegEncodingTable);
2133
2134 switch (DwarfFlavour) {
2135 default:
2136 llvm_unreachable("Unknown DWARF flavour");
2137 case 0:
2138 mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
2139 break;
2140 }
2141 switch (EHFlavour) {
2142 default:
2143 llvm_unreachable("Unknown DWARF flavour");
2144 case 0:
2145 mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
2146 break;
2147 }
2148 switch (DwarfFlavour) {
2149 default:
2150 llvm_unreachable("Unknown DWARF flavour");
2151 case 0:
2152 mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
2153 break;
2154 }
2155 switch (EHFlavour) {
2156 default:
2157 llvm_unreachable("Unknown DWARF flavour");
2158 case 0:
2159 mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
2160 break;
2161 }
2162}
2163
2164static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 };
2165static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x0001fe00, };
2166static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 };
2167static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
2168static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 };
2169static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
2170static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
2171static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
2172
2173
2174ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const {
2175 static const uint32_t *const Masks[] = {
2176 CSR_ILP32D_LP64D_RegMask,
2177 CSR_ILP32F_LP64F_RegMask,
2178 CSR_ILP32S_LP64S_RegMask,
2179 CSR_NoRegs_RegMask,
2180 };
2181 return ArrayRef(Masks);
2182}
2183
2184bool LoongArchGenRegisterInfo::
2185isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2186 return
2187 false;
2188}
2189
2190bool LoongArchGenRegisterInfo::
2191isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2192 return
2193 false;
2194}
2195
2196bool LoongArchGenRegisterInfo::
2197isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
2198 return
2199 false;
2200}
2201
2202bool LoongArchGenRegisterInfo::
2203isConstantPhysReg(MCRegister PhysReg) const {
2204 return
2205 PhysReg == LoongArch::R0 ||
2206 false;
2207}
2208
2209ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const {
2210 static const char *Names[] = {
2211 "CSR_ILP32D_LP64D",
2212 "CSR_ILP32F_LP64F",
2213 "CSR_ILP32S_LP64S",
2214 "CSR_NoRegs",
2215 };
2216 return ArrayRef(Names);
2217}
2218
2219const LoongArchFrameLowering *
2220LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
2221 return static_cast<const LoongArchFrameLowering *>(
2222 MF.getSubtarget().getFrameLowering());
2223}
2224
2225} // end namespace llvm
2226
2227#endif // GET_REGINFO_TARGET_DESC
2228
2229