1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace LoongArch {
15enum {
16 Feature32Bit = 0,
17 Feature64Bit = 1,
18 FeatureBasicD = 2,
19 FeatureBasicF = 3,
20 FeatureExtLASX = 4,
21 FeatureExtLBT = 5,
22 FeatureExtLSX = 6,
23 FeatureExtLVZ = 7,
24 FeatureFrecipe = 8,
25 FeatureRelax = 9,
26 FeatureUAL = 10,
27 LaGlobalWithAbs = 11,
28 LaGlobalWithPcrel = 12,
29 LaLocalWithAbs = 13,
30 TunePreferWInst = 14,
31 NumSubtargetFeatures = 15
32};
33} // end namespace LoongArch
34} // end namespace llvm
35
36#endif // GET_SUBTARGETINFO_ENUM
37
38
39#ifdef GET_SUBTARGETINFO_MACRO
40GET_SUBTARGETINFO_MACRO(HasBasicD, false, hasBasicD)
41GET_SUBTARGETINFO_MACRO(HasBasicF, false, hasBasicF)
42GET_SUBTARGETINFO_MACRO(HasExtLASX, false, hasExtLASX)
43GET_SUBTARGETINFO_MACRO(HasExtLBT, false, hasExtLBT)
44GET_SUBTARGETINFO_MACRO(HasExtLSX, false, hasExtLSX)
45GET_SUBTARGETINFO_MACRO(HasExtLVZ, false, hasExtLVZ)
46GET_SUBTARGETINFO_MACRO(HasFrecipe, false, hasFrecipe)
47GET_SUBTARGETINFO_MACRO(HasLA32, false, hasLA32)
48GET_SUBTARGETINFO_MACRO(HasLA64, false, hasLA64)
49GET_SUBTARGETINFO_MACRO(HasLaGlobalWithAbs, false, hasLaGlobalWithAbs)
50GET_SUBTARGETINFO_MACRO(HasLaGlobalWithPcrel, false, hasLaGlobalWithPcrel)
51GET_SUBTARGETINFO_MACRO(HasLaLocalWithAbs, false, hasLaLocalWithAbs)
52GET_SUBTARGETINFO_MACRO(HasLinkerRelax, false, hasLinkerRelax)
53GET_SUBTARGETINFO_MACRO(HasUAL, false, hasUAL)
54GET_SUBTARGETINFO_MACRO(PreferWInst, false, preferWInst)
55#undef GET_SUBTARGETINFO_MACRO
56#endif // GET_SUBTARGETINFO_MACRO
57
58
59#ifdef GET_SUBTARGETINFO_MC_DESC
60#undef GET_SUBTARGETINFO_MC_DESC
61
62namespace llvm {
63// Sorted (by key) array of values for CPU features.
64extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[] = {
65 { "32bit", "LA32 Basic Integer and Privilege Instruction Set", LoongArch::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
66 { "64bit", "LA64 Basic Integer and Privilege Instruction Set", LoongArch::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
67 { "d", "'D' (Double-Precision Floating-Point)", LoongArch::FeatureBasicD, { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
68 { "f", "'F' (Single-Precision Floating-Point)", LoongArch::FeatureBasicF, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
69 { "frecipe", "Support frecipe.{s/d} and frsqrte.{s/d} instructions.", LoongArch::FeatureFrecipe, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
70 { "la-global-with-abs", "Expand la.global as la.abs", LoongArch::LaGlobalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
71 { "la-global-with-pcrel", "Expand la.global as la.pcrel", LoongArch::LaGlobalWithPcrel, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
72 { "la-local-with-abs", "Expand la.local as la.abs", LoongArch::LaLocalWithAbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
73 { "lasx", "'LASX' (Loongson Advanced SIMD Extension)", LoongArch::FeatureExtLASX, { { { 0x40ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
74 { "lbt", "'LBT' (Loongson Binary Translation Extension)", LoongArch::FeatureExtLBT, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
75 { "lsx", "'LSX' (Loongson SIMD Extension)", LoongArch::FeatureExtLSX, { { { 0x4ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
76 { "lvz", "'LVZ' (Loongson Virtualization Extension)", LoongArch::FeatureExtLVZ, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
77 { "prefer-w-inst", "Prefer instructions with W suffix", LoongArch::TunePreferWInst, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
78 { "relax", "Enable Linker relaxation", LoongArch::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
79 { "ual", "Allow memory accesses to be unaligned", LoongArch::FeatureUAL, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
80};
81
82#ifdef DBGFIELD
83#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
84#endif
85#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
86#define DBGFIELD(x) x,
87#else
88#define DBGFIELD(x)
89#endif
90
91// ===============================================================
92// Data tables for the new per-operand machine model.
93
94// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
95extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[] = {
96 { 0, 0, 0 }, // Invalid
97}; // LoongArchWriteProcResTable
98
99// {Cycles, WriteResourceID}
100extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[] = {
101 { 0, 0}, // Invalid
102}; // LoongArchWriteLatencyTable
103
104// {UseIdx, WriteResourceID, Cycles}
105extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[] = {
106 {0, 0, 0}, // Invalid
107}; // LoongArchReadAdvanceTable
108
109#undef DBGFIELD
110
111static const llvm::MCSchedModel NoSchedModel = {
112 MCSchedModel::DefaultIssueWidth,
113 MCSchedModel::DefaultMicroOpBufferSize,
114 MCSchedModel::DefaultLoopMicroOpBufferSize,
115 MCSchedModel::DefaultLoadLatency,
116 MCSchedModel::DefaultHighLatency,
117 MCSchedModel::DefaultMispredictPenalty,
118 false, // PostRAScheduler
119 false, // CompleteModel
120 false, // EnableIntervals
121 0, // Processor ID
122 nullptr, nullptr, 0, 0, // No instruction-level machine model.
123 nullptr, // No Itinerary
124 nullptr // No extra processor descriptor
125};
126
127// Sorted (by key) array of values for CPU subtype.
128extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[] = {
129 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
130 { "generic-la32", { { { 0x1ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
131 { "generic-la64", { { { 0x402ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
132 { "la464", { { { 0x4b2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
133 { "la664", { { { 0x5b2ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
134 { "loongarch64", { { { 0x406ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
135};
136
137namespace LoongArch_MC {
138unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
139 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
140 // Don't know how to resolve this scheduling class.
141 return 0;
142}
143} // end namespace LoongArch_MC
144
145struct LoongArchGenMCSubtargetInfo : public MCSubtargetInfo {
146 LoongArchGenMCSubtargetInfo(const Triple &TT,
147 StringRef CPU, StringRef TuneCPU, StringRef FS,
148 ArrayRef<SubtargetFeatureKV> PF,
149 ArrayRef<SubtargetSubTypeKV> PD,
150 const MCWriteProcResEntry *WPR,
151 const MCWriteLatencyEntry *WL,
152 const MCReadAdvanceEntry *RA, const InstrStage *IS,
153 const unsigned *OC, const unsigned *FP) :
154 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
155 WPR, WL, RA, IS, OC, FP) { }
156
157 unsigned resolveVariantSchedClass(unsigned SchedClass,
158 const MCInst *MI, const MCInstrInfo *MCII,
159 unsigned CPUID) const override {
160 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
161 }
162 unsigned getHwModeSet() const override;
163 unsigned getHwMode(enum HwModeType type = HwMode_Default) const override;
164};
165unsigned LoongArchGenMCSubtargetInfo::getHwModeSet() const {
166 // Collect HwModes and store them as a bit set.
167 unsigned Modes = 0;
168 if (checkFeatures("+64bit")) Modes |= (1 << 0);
169 return Modes;
170}
171unsigned LoongArchGenMCSubtargetInfo::getHwMode(enum HwModeType type) const {
172 unsigned Modes = getHwModeSet();
173
174 if (!Modes)
175 return Modes;
176
177 switch (type) {
178 case HwMode_Default:
179 return llvm::countr_zero(Modes) + 1;
180 case HwMode_ValueType:
181 Modes &= 1;
182 if (!Modes)
183 return Modes;
184 if (!llvm::has_single_bit<unsigned>(Modes))
185 llvm_unreachable("Two or more HwModes for ValueType were found!");
186 return llvm::countr_zero(Modes) + 1;
187 case HwMode_RegInfo:
188 Modes &= 1;
189 if (!Modes)
190 return Modes;
191 if (!llvm::has_single_bit<unsigned>(Modes))
192 llvm_unreachable("Two or more HwModes for RegInfo were found!");
193 return llvm::countr_zero(Modes) + 1;
194 case HwMode_EncodingInfo:
195 Modes &= 0;
196 if (!Modes)
197 return Modes;
198 if (!llvm::has_single_bit<unsigned>(Modes))
199 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
200 return llvm::countr_zero(Modes) + 1;
201 }
202 llvm_unreachable("unexpected HwModeType");
203 return 0; // should not get here
204}
205
206static inline MCSubtargetInfo *createLoongArchMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
207 return new LoongArchGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, LoongArchFeatureKV, LoongArchSubTypeKV,
208 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
209 nullptr, nullptr, nullptr);
210}
211
212} // end namespace llvm
213
214#endif // GET_SUBTARGETINFO_MC_DESC
215
216
217#ifdef GET_SUBTARGETINFO_TARGET_DESC
218#undef GET_SUBTARGETINFO_TARGET_DESC
219
220#include "llvm/Support/Debug.h"
221#include "llvm/Support/raw_ostream.h"
222
223// ParseSubtargetFeatures - Parses features string setting specified
224// subtarget options.
225void llvm::LoongArchSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
226 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
227 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
228 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
229 InitMCProcessorInfo(CPU, TuneCPU, FS);
230 const FeatureBitset &Bits = getFeatureBits();
231 if (Bits[LoongArch::Feature32Bit]) HasLA32 = true;
232 if (Bits[LoongArch::Feature64Bit]) HasLA64 = true;
233 if (Bits[LoongArch::FeatureBasicD]) HasBasicD = true;
234 if (Bits[LoongArch::FeatureBasicF]) HasBasicF = true;
235 if (Bits[LoongArch::FeatureExtLASX]) HasExtLASX = true;
236 if (Bits[LoongArch::FeatureExtLBT]) HasExtLBT = true;
237 if (Bits[LoongArch::FeatureExtLSX]) HasExtLSX = true;
238 if (Bits[LoongArch::FeatureExtLVZ]) HasExtLVZ = true;
239 if (Bits[LoongArch::FeatureFrecipe]) HasFrecipe = true;
240 if (Bits[LoongArch::FeatureRelax]) HasLinkerRelax = true;
241 if (Bits[LoongArch::FeatureUAL]) HasUAL = true;
242 if (Bits[LoongArch::LaGlobalWithAbs]) HasLaGlobalWithAbs = true;
243 if (Bits[LoongArch::LaGlobalWithPcrel]) HasLaGlobalWithPcrel = true;
244 if (Bits[LoongArch::LaLocalWithAbs]) HasLaLocalWithAbs = true;
245 if (Bits[LoongArch::TunePreferWInst]) PreferWInst = true;
246}
247#endif // GET_SUBTARGETINFO_TARGET_DESC
248
249
250#ifdef GET_SUBTARGETINFO_HEADER
251#undef GET_SUBTARGETINFO_HEADER
252
253namespace llvm {
254class DFAPacketizer;
255namespace LoongArch_MC {
256unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
257} // end namespace LoongArch_MC
258
259struct LoongArchGenSubtargetInfo : public TargetSubtargetInfo {
260 explicit LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
261public:
262 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
263 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
264 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
265 unsigned getHwModeSet() const override;
266 unsigned getHwMode(enum HwModeType type = HwMode_Default) const override;
267};
268} // end namespace llvm
269
270#endif // GET_SUBTARGETINFO_HEADER
271
272
273#ifdef GET_SUBTARGETINFO_CTOR
274#undef GET_SUBTARGETINFO_CTOR
275
276#include "llvm/CodeGen/TargetSchedule.h"
277
278namespace llvm {
279extern const llvm::SubtargetFeatureKV LoongArchFeatureKV[];
280extern const llvm::SubtargetSubTypeKV LoongArchSubTypeKV[];
281extern const llvm::MCWriteProcResEntry LoongArchWriteProcResTable[];
282extern const llvm::MCWriteLatencyEntry LoongArchWriteLatencyTable[];
283extern const llvm::MCReadAdvanceEntry LoongArchReadAdvanceTable[];
284LoongArchGenSubtargetInfo::LoongArchGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
285 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(LoongArchFeatureKV, 15), ArrayRef(LoongArchSubTypeKV, 6),
286 LoongArchWriteProcResTable, LoongArchWriteLatencyTable, LoongArchReadAdvanceTable,
287 nullptr, nullptr, nullptr) {}
288
289unsigned LoongArchGenSubtargetInfo
290::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
291 report_fatal_error("Expected a variant SchedClass");
292} // LoongArchGenSubtargetInfo::resolveSchedClass
293
294unsigned LoongArchGenSubtargetInfo
295::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
296 return LoongArch_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
297} // LoongArchGenSubtargetInfo::resolveVariantSchedClass
298
299unsigned LoongArchGenSubtargetInfo::getHwModeSet() const {
300 // Collect HwModes and store them as a bit set.
301 unsigned Modes = 0;
302 if (checkFeatures("+64bit")) Modes |= (1 << 0);
303 return Modes;
304}
305unsigned LoongArchGenSubtargetInfo::getHwMode(enum HwModeType type) const {
306 unsigned Modes = getHwModeSet();
307
308 if (!Modes)
309 return Modes;
310
311 switch (type) {
312 case HwMode_Default:
313 return llvm::countr_zero(Modes) + 1;
314 case HwMode_ValueType:
315 Modes &= 1;
316 if (!Modes)
317 return Modes;
318 if (!llvm::has_single_bit<unsigned>(Modes))
319 llvm_unreachable("Two or more HwModes for ValueType were found!");
320 return llvm::countr_zero(Modes) + 1;
321 case HwMode_RegInfo:
322 Modes &= 1;
323 if (!Modes)
324 return Modes;
325 if (!llvm::has_single_bit<unsigned>(Modes))
326 llvm_unreachable("Two or more HwModes for RegInfo were found!");
327 return llvm::countr_zero(Modes) + 1;
328 case HwMode_EncodingInfo:
329 Modes &= 0;
330 if (!Modes)
331 return Modes;
332 if (!llvm::has_single_bit<unsigned>(Modes))
333 llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
334 return llvm::countr_zero(Modes) + 1;
335 }
336 llvm_unreachable("unexpected HwModeType");
337 return 0; // should not get here
338}
339} // end namespace llvm
340
341#endif // GET_SUBTARGETINFO_CTOR
342
343
344#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
345#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
346
347#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
348
349
350#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
351#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
352
353#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
354
355