1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Instruction Enum Values and Descriptors *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_INSTRINFO_ENUM
10#undef GET_INSTRINFO_ENUM
11namespace llvm {
12
13namespace MSP430 {
14 enum {
15 PHI = 0,
16 INLINEASM = 1,
17 INLINEASM_BR = 2,
18 CFI_INSTRUCTION = 3,
19 EH_LABEL = 4,
20 GC_LABEL = 5,
21 ANNOTATION_LABEL = 6,
22 KILL = 7,
23 EXTRACT_SUBREG = 8,
24 INSERT_SUBREG = 9,
25 IMPLICIT_DEF = 10,
26 SUBREG_TO_REG = 11,
27 COPY_TO_REGCLASS = 12,
28 DBG_VALUE = 13,
29 DBG_VALUE_LIST = 14,
30 DBG_INSTR_REF = 15,
31 DBG_PHI = 16,
32 DBG_LABEL = 17,
33 REG_SEQUENCE = 18,
34 COPY = 19,
35 BUNDLE = 20,
36 LIFETIME_START = 21,
37 LIFETIME_END = 22,
38 PSEUDO_PROBE = 23,
39 ARITH_FENCE = 24,
40 STACKMAP = 25,
41 FENTRY_CALL = 26,
42 PATCHPOINT = 27,
43 LOAD_STACK_GUARD = 28,
44 PREALLOCATED_SETUP = 29,
45 PREALLOCATED_ARG = 30,
46 STATEPOINT = 31,
47 LOCAL_ESCAPE = 32,
48 FAULTING_OP = 33,
49 PATCHABLE_OP = 34,
50 PATCHABLE_FUNCTION_ENTER = 35,
51 PATCHABLE_RET = 36,
52 PATCHABLE_FUNCTION_EXIT = 37,
53 PATCHABLE_TAIL_CALL = 38,
54 PATCHABLE_EVENT_CALL = 39,
55 PATCHABLE_TYPED_EVENT_CALL = 40,
56 ICALL_BRANCH_FUNNEL = 41,
57 MEMBARRIER = 42,
58 JUMP_TABLE_DEBUG_INFO = 43,
59 CONVERGENCECTRL_ENTRY = 44,
60 CONVERGENCECTRL_ANCHOR = 45,
61 CONVERGENCECTRL_LOOP = 46,
62 CONVERGENCECTRL_GLUE = 47,
63 G_ASSERT_SEXT = 48,
64 G_ASSERT_ZEXT = 49,
65 G_ASSERT_ALIGN = 50,
66 G_ADD = 51,
67 G_SUB = 52,
68 G_MUL = 53,
69 G_SDIV = 54,
70 G_UDIV = 55,
71 G_SREM = 56,
72 G_UREM = 57,
73 G_SDIVREM = 58,
74 G_UDIVREM = 59,
75 G_AND = 60,
76 G_OR = 61,
77 G_XOR = 62,
78 G_IMPLICIT_DEF = 63,
79 G_PHI = 64,
80 G_FRAME_INDEX = 65,
81 G_GLOBAL_VALUE = 66,
82 G_PTRAUTH_GLOBAL_VALUE = 67,
83 G_CONSTANT_POOL = 68,
84 G_EXTRACT = 69,
85 G_UNMERGE_VALUES = 70,
86 G_INSERT = 71,
87 G_MERGE_VALUES = 72,
88 G_BUILD_VECTOR = 73,
89 G_BUILD_VECTOR_TRUNC = 74,
90 G_CONCAT_VECTORS = 75,
91 G_PTRTOINT = 76,
92 G_INTTOPTR = 77,
93 G_BITCAST = 78,
94 G_FREEZE = 79,
95 G_CONSTANT_FOLD_BARRIER = 80,
96 G_INTRINSIC_FPTRUNC_ROUND = 81,
97 G_INTRINSIC_TRUNC = 82,
98 G_INTRINSIC_ROUND = 83,
99 G_INTRINSIC_LRINT = 84,
100 G_INTRINSIC_LLRINT = 85,
101 G_INTRINSIC_ROUNDEVEN = 86,
102 G_READCYCLECOUNTER = 87,
103 G_READSTEADYCOUNTER = 88,
104 G_LOAD = 89,
105 G_SEXTLOAD = 90,
106 G_ZEXTLOAD = 91,
107 G_INDEXED_LOAD = 92,
108 G_INDEXED_SEXTLOAD = 93,
109 G_INDEXED_ZEXTLOAD = 94,
110 G_STORE = 95,
111 G_INDEXED_STORE = 96,
112 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97,
113 G_ATOMIC_CMPXCHG = 98,
114 G_ATOMICRMW_XCHG = 99,
115 G_ATOMICRMW_ADD = 100,
116 G_ATOMICRMW_SUB = 101,
117 G_ATOMICRMW_AND = 102,
118 G_ATOMICRMW_NAND = 103,
119 G_ATOMICRMW_OR = 104,
120 G_ATOMICRMW_XOR = 105,
121 G_ATOMICRMW_MAX = 106,
122 G_ATOMICRMW_MIN = 107,
123 G_ATOMICRMW_UMAX = 108,
124 G_ATOMICRMW_UMIN = 109,
125 G_ATOMICRMW_FADD = 110,
126 G_ATOMICRMW_FSUB = 111,
127 G_ATOMICRMW_FMAX = 112,
128 G_ATOMICRMW_FMIN = 113,
129 G_ATOMICRMW_UINC_WRAP = 114,
130 G_ATOMICRMW_UDEC_WRAP = 115,
131 G_FENCE = 116,
132 G_PREFETCH = 117,
133 G_BRCOND = 118,
134 G_BRINDIRECT = 119,
135 G_INVOKE_REGION_START = 120,
136 G_INTRINSIC = 121,
137 G_INTRINSIC_W_SIDE_EFFECTS = 122,
138 G_INTRINSIC_CONVERGENT = 123,
139 G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124,
140 G_ANYEXT = 125,
141 G_TRUNC = 126,
142 G_CONSTANT = 127,
143 G_FCONSTANT = 128,
144 G_VASTART = 129,
145 G_VAARG = 130,
146 G_SEXT = 131,
147 G_SEXT_INREG = 132,
148 G_ZEXT = 133,
149 G_SHL = 134,
150 G_LSHR = 135,
151 G_ASHR = 136,
152 G_FSHL = 137,
153 G_FSHR = 138,
154 G_ROTR = 139,
155 G_ROTL = 140,
156 G_ICMP = 141,
157 G_FCMP = 142,
158 G_SCMP = 143,
159 G_UCMP = 144,
160 G_SELECT = 145,
161 G_UADDO = 146,
162 G_UADDE = 147,
163 G_USUBO = 148,
164 G_USUBE = 149,
165 G_SADDO = 150,
166 G_SADDE = 151,
167 G_SSUBO = 152,
168 G_SSUBE = 153,
169 G_UMULO = 154,
170 G_SMULO = 155,
171 G_UMULH = 156,
172 G_SMULH = 157,
173 G_UADDSAT = 158,
174 G_SADDSAT = 159,
175 G_USUBSAT = 160,
176 G_SSUBSAT = 161,
177 G_USHLSAT = 162,
178 G_SSHLSAT = 163,
179 G_SMULFIX = 164,
180 G_UMULFIX = 165,
181 G_SMULFIXSAT = 166,
182 G_UMULFIXSAT = 167,
183 G_SDIVFIX = 168,
184 G_UDIVFIX = 169,
185 G_SDIVFIXSAT = 170,
186 G_UDIVFIXSAT = 171,
187 G_FADD = 172,
188 G_FSUB = 173,
189 G_FMUL = 174,
190 G_FMA = 175,
191 G_FMAD = 176,
192 G_FDIV = 177,
193 G_FREM = 178,
194 G_FPOW = 179,
195 G_FPOWI = 180,
196 G_FEXP = 181,
197 G_FEXP2 = 182,
198 G_FEXP10 = 183,
199 G_FLOG = 184,
200 G_FLOG2 = 185,
201 G_FLOG10 = 186,
202 G_FLDEXP = 187,
203 G_FFREXP = 188,
204 G_FNEG = 189,
205 G_FPEXT = 190,
206 G_FPTRUNC = 191,
207 G_FPTOSI = 192,
208 G_FPTOUI = 193,
209 G_SITOFP = 194,
210 G_UITOFP = 195,
211 G_FABS = 196,
212 G_FCOPYSIGN = 197,
213 G_IS_FPCLASS = 198,
214 G_FCANONICALIZE = 199,
215 G_FMINNUM = 200,
216 G_FMAXNUM = 201,
217 G_FMINNUM_IEEE = 202,
218 G_FMAXNUM_IEEE = 203,
219 G_FMINIMUM = 204,
220 G_FMAXIMUM = 205,
221 G_GET_FPENV = 206,
222 G_SET_FPENV = 207,
223 G_RESET_FPENV = 208,
224 G_GET_FPMODE = 209,
225 G_SET_FPMODE = 210,
226 G_RESET_FPMODE = 211,
227 G_PTR_ADD = 212,
228 G_PTRMASK = 213,
229 G_SMIN = 214,
230 G_SMAX = 215,
231 G_UMIN = 216,
232 G_UMAX = 217,
233 G_ABS = 218,
234 G_LROUND = 219,
235 G_LLROUND = 220,
236 G_BR = 221,
237 G_BRJT = 222,
238 G_VSCALE = 223,
239 G_INSERT_SUBVECTOR = 224,
240 G_EXTRACT_SUBVECTOR = 225,
241 G_INSERT_VECTOR_ELT = 226,
242 G_EXTRACT_VECTOR_ELT = 227,
243 G_SHUFFLE_VECTOR = 228,
244 G_SPLAT_VECTOR = 229,
245 G_VECTOR_COMPRESS = 230,
246 G_CTTZ = 231,
247 G_CTTZ_ZERO_UNDEF = 232,
248 G_CTLZ = 233,
249 G_CTLZ_ZERO_UNDEF = 234,
250 G_CTPOP = 235,
251 G_BSWAP = 236,
252 G_BITREVERSE = 237,
253 G_FCEIL = 238,
254 G_FCOS = 239,
255 G_FSIN = 240,
256 G_FTAN = 241,
257 G_FACOS = 242,
258 G_FASIN = 243,
259 G_FATAN = 244,
260 G_FCOSH = 245,
261 G_FSINH = 246,
262 G_FTANH = 247,
263 G_FSQRT = 248,
264 G_FFLOOR = 249,
265 G_FRINT = 250,
266 G_FNEARBYINT = 251,
267 G_ADDRSPACE_CAST = 252,
268 G_BLOCK_ADDR = 253,
269 G_JUMP_TABLE = 254,
270 G_DYN_STACKALLOC = 255,
271 G_STACKSAVE = 256,
272 G_STACKRESTORE = 257,
273 G_STRICT_FADD = 258,
274 G_STRICT_FSUB = 259,
275 G_STRICT_FMUL = 260,
276 G_STRICT_FDIV = 261,
277 G_STRICT_FREM = 262,
278 G_STRICT_FMA = 263,
279 G_STRICT_FSQRT = 264,
280 G_STRICT_FLDEXP = 265,
281 G_READ_REGISTER = 266,
282 G_WRITE_REGISTER = 267,
283 G_MEMCPY = 268,
284 G_MEMCPY_INLINE = 269,
285 G_MEMMOVE = 270,
286 G_MEMSET = 271,
287 G_BZERO = 272,
288 G_TRAP = 273,
289 G_DEBUGTRAP = 274,
290 G_UBSANTRAP = 275,
291 G_VECREDUCE_SEQ_FADD = 276,
292 G_VECREDUCE_SEQ_FMUL = 277,
293 G_VECREDUCE_FADD = 278,
294 G_VECREDUCE_FMUL = 279,
295 G_VECREDUCE_FMAX = 280,
296 G_VECREDUCE_FMIN = 281,
297 G_VECREDUCE_FMAXIMUM = 282,
298 G_VECREDUCE_FMINIMUM = 283,
299 G_VECREDUCE_ADD = 284,
300 G_VECREDUCE_MUL = 285,
301 G_VECREDUCE_AND = 286,
302 G_VECREDUCE_OR = 287,
303 G_VECREDUCE_XOR = 288,
304 G_VECREDUCE_SMAX = 289,
305 G_VECREDUCE_SMIN = 290,
306 G_VECREDUCE_UMAX = 291,
307 G_VECREDUCE_UMIN = 292,
308 G_SBFX = 293,
309 G_UBFX = 294,
310 ADD16mc = 295,
311 ADD16mi = 296,
312 ADD16mm = 297,
313 ADD16mn = 298,
314 ADD16mp = 299,
315 ADD16mr = 300,
316 ADD16rc = 301,
317 ADD16ri = 302,
318 ADD16rm = 303,
319 ADD16rn = 304,
320 ADD16rp = 305,
321 ADD16rr = 306,
322 ADD8mc = 307,
323 ADD8mi = 308,
324 ADD8mm = 309,
325 ADD8mn = 310,
326 ADD8mp = 311,
327 ADD8mr = 312,
328 ADD8rc = 313,
329 ADD8ri = 314,
330 ADD8rm = 315,
331 ADD8rn = 316,
332 ADD8rp = 317,
333 ADD8rr = 318,
334 ADDC16mc = 319,
335 ADDC16mi = 320,
336 ADDC16mm = 321,
337 ADDC16mn = 322,
338 ADDC16mp = 323,
339 ADDC16mr = 324,
340 ADDC16rc = 325,
341 ADDC16ri = 326,
342 ADDC16rm = 327,
343 ADDC16rn = 328,
344 ADDC16rp = 329,
345 ADDC16rr = 330,
346 ADDC8mc = 331,
347 ADDC8mi = 332,
348 ADDC8mm = 333,
349 ADDC8mn = 334,
350 ADDC8mp = 335,
351 ADDC8mr = 336,
352 ADDC8rc = 337,
353 ADDC8ri = 338,
354 ADDC8rm = 339,
355 ADDC8rn = 340,
356 ADDC8rp = 341,
357 ADDC8rr = 342,
358 ADDframe = 343,
359 ADJCALLSTACKDOWN = 344,
360 ADJCALLSTACKUP = 345,
361 AND16mc = 346,
362 AND16mi = 347,
363 AND16mm = 348,
364 AND16mn = 349,
365 AND16mp = 350,
366 AND16mr = 351,
367 AND16rc = 352,
368 AND16ri = 353,
369 AND16rm = 354,
370 AND16rn = 355,
371 AND16rp = 356,
372 AND16rr = 357,
373 AND8mc = 358,
374 AND8mi = 359,
375 AND8mm = 360,
376 AND8mn = 361,
377 AND8mp = 362,
378 AND8mr = 363,
379 AND8rc = 364,
380 AND8ri = 365,
381 AND8rm = 366,
382 AND8rn = 367,
383 AND8rp = 368,
384 AND8rr = 369,
385 BIC16mc = 370,
386 BIC16mi = 371,
387 BIC16mm = 372,
388 BIC16mn = 373,
389 BIC16mp = 374,
390 BIC16mr = 375,
391 BIC16rc = 376,
392 BIC16ri = 377,
393 BIC16rm = 378,
394 BIC16rn = 379,
395 BIC16rp = 380,
396 BIC16rr = 381,
397 BIC8mc = 382,
398 BIC8mi = 383,
399 BIC8mm = 384,
400 BIC8mn = 385,
401 BIC8mp = 386,
402 BIC8mr = 387,
403 BIC8rc = 388,
404 BIC8ri = 389,
405 BIC8rm = 390,
406 BIC8rn = 391,
407 BIC8rp = 392,
408 BIC8rr = 393,
409 BIS16mc = 394,
410 BIS16mi = 395,
411 BIS16mm = 396,
412 BIS16mn = 397,
413 BIS16mp = 398,
414 BIS16mr = 399,
415 BIS16rc = 400,
416 BIS16ri = 401,
417 BIS16rm = 402,
418 BIS16rn = 403,
419 BIS16rp = 404,
420 BIS16rr = 405,
421 BIS8mc = 406,
422 BIS8mi = 407,
423 BIS8mm = 408,
424 BIS8mn = 409,
425 BIS8mp = 410,
426 BIS8mr = 411,
427 BIS8rc = 412,
428 BIS8ri = 413,
429 BIS8rm = 414,
430 BIS8rn = 415,
431 BIS8rp = 416,
432 BIS8rr = 417,
433 BIT16mc = 418,
434 BIT16mi = 419,
435 BIT16mm = 420,
436 BIT16mn = 421,
437 BIT16mp = 422,
438 BIT16mr = 423,
439 BIT16rc = 424,
440 BIT16ri = 425,
441 BIT16rm = 426,
442 BIT16rn = 427,
443 BIT16rp = 428,
444 BIT16rr = 429,
445 BIT8mc = 430,
446 BIT8mi = 431,
447 BIT8mm = 432,
448 BIT8mn = 433,
449 BIT8mp = 434,
450 BIT8mr = 435,
451 BIT8rc = 436,
452 BIT8ri = 437,
453 BIT8rm = 438,
454 BIT8rn = 439,
455 BIT8rp = 440,
456 BIT8rr = 441,
457 Bi = 442,
458 Bm = 443,
459 Br = 444,
460 CALLi = 445,
461 CALLm = 446,
462 CALLn = 447,
463 CALLp = 448,
464 CALLr = 449,
465 CMP16mc = 450,
466 CMP16mi = 451,
467 CMP16mm = 452,
468 CMP16mn = 453,
469 CMP16mp = 454,
470 CMP16mr = 455,
471 CMP16rc = 456,
472 CMP16ri = 457,
473 CMP16rm = 458,
474 CMP16rn = 459,
475 CMP16rp = 460,
476 CMP16rr = 461,
477 CMP8mc = 462,
478 CMP8mi = 463,
479 CMP8mm = 464,
480 CMP8mn = 465,
481 CMP8mp = 466,
482 CMP8mr = 467,
483 CMP8rc = 468,
484 CMP8ri = 469,
485 CMP8rm = 470,
486 CMP8rn = 471,
487 CMP8rp = 472,
488 CMP8rr = 473,
489 DADD16mc = 474,
490 DADD16mi = 475,
491 DADD16mm = 476,
492 DADD16mn = 477,
493 DADD16mp = 478,
494 DADD16mr = 479,
495 DADD16rc = 480,
496 DADD16ri = 481,
497 DADD16rm = 482,
498 DADD16rn = 483,
499 DADD16rp = 484,
500 DADD16rr = 485,
501 DADD8mc = 486,
502 DADD8mi = 487,
503 DADD8mm = 488,
504 DADD8mn = 489,
505 DADD8mp = 490,
506 DADD8mr = 491,
507 DADD8rc = 492,
508 DADD8ri = 493,
509 DADD8rm = 494,
510 DADD8rn = 495,
511 DADD8rp = 496,
512 DADD8rr = 497,
513 JCC = 498,
514 JMP = 499,
515 MOV16mc = 500,
516 MOV16mi = 501,
517 MOV16mm = 502,
518 MOV16mn = 503,
519 MOV16mr = 504,
520 MOV16rc = 505,
521 MOV16ri = 506,
522 MOV16rm = 507,
523 MOV16rn = 508,
524 MOV16rp = 509,
525 MOV16rr = 510,
526 MOV8mc = 511,
527 MOV8mi = 512,
528 MOV8mm = 513,
529 MOV8mn = 514,
530 MOV8mr = 515,
531 MOV8rc = 516,
532 MOV8ri = 517,
533 MOV8rm = 518,
534 MOV8rn = 519,
535 MOV8rp = 520,
536 MOV8rr = 521,
537 MOVZX16rm8 = 522,
538 MOVZX16rr8 = 523,
539 POP16r = 524,
540 PUSH16c = 525,
541 PUSH16i = 526,
542 PUSH16r = 527,
543 PUSH8r = 528,
544 RET = 529,
545 RETI = 530,
546 RRA16m = 531,
547 RRA16n = 532,
548 RRA16p = 533,
549 RRA16r = 534,
550 RRA8m = 535,
551 RRA8n = 536,
552 RRA8p = 537,
553 RRA8r = 538,
554 RRC16m = 539,
555 RRC16n = 540,
556 RRC16p = 541,
557 RRC16r = 542,
558 RRC8m = 543,
559 RRC8n = 544,
560 RRC8p = 545,
561 RRC8r = 546,
562 Rrcl16 = 547,
563 Rrcl8 = 548,
564 SEXT16m = 549,
565 SEXT16n = 550,
566 SEXT16p = 551,
567 SEXT16r = 552,
568 SUB16mc = 553,
569 SUB16mi = 554,
570 SUB16mm = 555,
571 SUB16mn = 556,
572 SUB16mp = 557,
573 SUB16mr = 558,
574 SUB16rc = 559,
575 SUB16ri = 560,
576 SUB16rm = 561,
577 SUB16rn = 562,
578 SUB16rp = 563,
579 SUB16rr = 564,
580 SUB8mc = 565,
581 SUB8mi = 566,
582 SUB8mm = 567,
583 SUB8mn = 568,
584 SUB8mp = 569,
585 SUB8mr = 570,
586 SUB8rc = 571,
587 SUB8ri = 572,
588 SUB8rm = 573,
589 SUB8rn = 574,
590 SUB8rp = 575,
591 SUB8rr = 576,
592 SUBC16mc = 577,
593 SUBC16mi = 578,
594 SUBC16mm = 579,
595 SUBC16mn = 580,
596 SUBC16mp = 581,
597 SUBC16mr = 582,
598 SUBC16rc = 583,
599 SUBC16ri = 584,
600 SUBC16rm = 585,
601 SUBC16rn = 586,
602 SUBC16rp = 587,
603 SUBC16rr = 588,
604 SUBC8mc = 589,
605 SUBC8mi = 590,
606 SUBC8mm = 591,
607 SUBC8mn = 592,
608 SUBC8mp = 593,
609 SUBC8mr = 594,
610 SUBC8rc = 595,
611 SUBC8ri = 596,
612 SUBC8rm = 597,
613 SUBC8rn = 598,
614 SUBC8rp = 599,
615 SUBC8rr = 600,
616 SWPB16m = 601,
617 SWPB16n = 602,
618 SWPB16p = 603,
619 SWPB16r = 604,
620 Select16 = 605,
621 Select8 = 606,
622 Shl16 = 607,
623 Shl8 = 608,
624 Sra16 = 609,
625 Sra8 = 610,
626 Srl16 = 611,
627 Srl8 = 612,
628 XOR16mc = 613,
629 XOR16mi = 614,
630 XOR16mm = 615,
631 XOR16mn = 616,
632 XOR16mp = 617,
633 XOR16mr = 618,
634 XOR16rc = 619,
635 XOR16ri = 620,
636 XOR16rm = 621,
637 XOR16rn = 622,
638 XOR16rp = 623,
639 XOR16rr = 624,
640 XOR8mc = 625,
641 XOR8mi = 626,
642 XOR8mm = 627,
643 XOR8mn = 628,
644 XOR8mp = 629,
645 XOR8mr = 630,
646 XOR8rc = 631,
647 XOR8ri = 632,
648 XOR8rm = 633,
649 XOR8rn = 634,
650 XOR8rp = 635,
651 XOR8rr = 636,
652 ZEXT16r = 637,
653 INSTRUCTION_LIST_END = 638
654 };
655
656} // end namespace MSP430
657} // end namespace llvm
658#endif // GET_INSTRINFO_ENUM
659
660#ifdef GET_INSTRINFO_SCHED_ENUM
661#undef GET_INSTRINFO_SCHED_ENUM
662namespace llvm {
663
664namespace MSP430 {
665namespace Sched {
666 enum {
667 NoInstrModel = 0,
668 SCHED_LIST_END = 1
669 };
670} // end namespace Sched
671} // end namespace MSP430
672} // end namespace llvm
673#endif // GET_INSTRINFO_SCHED_ENUM
674
675#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
676namespace llvm {
677
678struct MSP430InstrTable {
679 MCInstrDesc Insts[638];
680 static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
681 MCOperandInfo OperandInfo[267];
682 static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
683 MCPhysReg ImplicitOps[17];
684};
685
686} // end namespace llvm
687#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
688
689#ifdef GET_INSTRINFO_MC_DESC
690#undef GET_INSTRINFO_MC_DESC
691namespace llvm {
692
693static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
694static constexpr unsigned MSP430ImpOpBase = sizeof MSP430InstrTable::OperandInfo / (sizeof(MCPhysReg));
695
696extern const MSP430InstrTable MSP430Descs = {
697 {
698 { 637, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 249, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #637 = ZEXT16r
699 { 636, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 208, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #636 = XOR8rr
700 { 635, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #635 = XOR8rp
701 { 634, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #634 = XOR8rn
702 { 633, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #633 = XOR8rm
703 { 632, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #632 = XOR8ri
704 { 631, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #631 = XOR8rc
705 { 630, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #630 = XOR8mr
706 { 629, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #629 = XOR8mp
707 { 628, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #628 = XOR8mn
708 { 627, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #627 = XOR8mm
709 { 626, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #626 = XOR8mi
710 { 625, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #625 = XOR8mc
711 { 624, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 185, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #624 = XOR16rr
712 { 623, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #623 = XOR16rp
713 { 622, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #622 = XOR16rn
714 { 621, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #621 = XOR16rm
715 { 620, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #620 = XOR16ri
716 { 619, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #619 = XOR16rc
717 { 618, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #618 = XOR16mr
718 { 617, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #617 = XOR16mp
719 { 616, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #616 = XOR16mn
720 { 615, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #615 = XOR16mm
721 { 614, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #614 = XOR16mi
722 { 613, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #613 = XOR16mc
723 { 612, 3, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 264, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #612 = Srl8
724 { 611, 3, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 261, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #611 = Srl16
725 { 610, 3, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 264, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #610 = Sra8
726 { 609, 3, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 261, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #609 = Sra16
727 { 608, 3, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 264, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #608 = Shl8
728 { 607, 3, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 261, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #607 = Shl16
729 { 606, 4, 1, 0, 0, 1, 0, MSP430ImpOpBase + 0, 257, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #606 = Select8
730 { 605, 4, 1, 0, 0, 1, 0, MSP430ImpOpBase + 0, 253, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #605 = Select16
731 { 604, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 249, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #604 = SWPB16r
732 { 603, 1, 0, 2, 0, 0, 0, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #603 = SWPB16p
733 { 602, 1, 0, 2, 0, 0, 0, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #602 = SWPB16n
734 { 601, 2, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 236, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #601 = SWPB16m
735 { 600, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 208, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #600 = SUBC8rr
736 { 599, 4, 2, 2, 0, 1, 1, MSP430ImpOpBase + 1, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #599 = SUBC8rp
737 { 598, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #598 = SUBC8rn
738 { 597, 4, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #597 = SUBC8rm
739 { 596, 3, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #596 = SUBC8ri
740 { 595, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #595 = SUBC8rc
741 { 594, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #594 = SUBC8mr
742 { 593, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #593 = SUBC8mp
743 { 592, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #592 = SUBC8mn
744 { 591, 4, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #591 = SUBC8mm
745 { 590, 3, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #590 = SUBC8mi
746 { 589, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #589 = SUBC8mc
747 { 588, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 185, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #588 = SUBC16rr
748 { 587, 4, 2, 2, 0, 1, 1, MSP430ImpOpBase + 1, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #587 = SUBC16rp
749 { 586, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #586 = SUBC16rn
750 { 585, 4, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #585 = SUBC16rm
751 { 584, 3, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #584 = SUBC16ri
752 { 583, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #583 = SUBC16rc
753 { 582, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #582 = SUBC16mr
754 { 581, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #581 = SUBC16mp
755 { 580, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #580 = SUBC16mn
756 { 579, 4, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #579 = SUBC16mm
757 { 578, 3, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #578 = SUBC16mi
758 { 577, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #577 = SUBC16mc
759 { 576, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 208, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #576 = SUB8rr
760 { 575, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #575 = SUB8rp
761 { 574, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #574 = SUB8rn
762 { 573, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #573 = SUB8rm
763 { 572, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #572 = SUB8ri
764 { 571, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #571 = SUB8rc
765 { 570, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #570 = SUB8mr
766 { 569, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #569 = SUB8mp
767 { 568, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #568 = SUB8mn
768 { 567, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #567 = SUB8mm
769 { 566, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #566 = SUB8mi
770 { 565, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #565 = SUB8mc
771 { 564, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 185, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #564 = SUB16rr
772 { 563, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #563 = SUB16rp
773 { 562, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #562 = SUB16rn
774 { 561, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #561 = SUB16rm
775 { 560, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #560 = SUB16ri
776 { 559, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #559 = SUB16rc
777 { 558, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #558 = SUB16mr
778 { 557, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #557 = SUB16mp
779 { 556, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #556 = SUB16mn
780 { 555, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #555 = SUB16mm
781 { 554, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #554 = SUB16mi
782 { 553, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #553 = SUB16mc
783 { 552, 2, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 249, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #552 = SEXT16r
784 { 551, 1, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #551 = SEXT16p
785 { 550, 1, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #550 = SEXT16n
786 { 549, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 236, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #549 = SEXT16m
787 { 548, 2, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 234, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #548 = Rrcl8
788 { 547, 2, 1, 0, 0, 0, 1, MSP430ImpOpBase + 0, 223, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #547 = Rrcl16
789 { 546, 2, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 251, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #546 = RRC8r
790 { 545, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 1, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #545 = RRC8p
791 { 544, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 1, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #544 = RRC8n
792 { 543, 2, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 236, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #543 = RRC8m
793 { 542, 2, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 249, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #542 = RRC16r
794 { 541, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 1, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #541 = RRC16p
795 { 540, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 1, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #540 = RRC16n
796 { 539, 2, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 236, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #539 = RRC16m
797 { 538, 2, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 251, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #538 = RRA8r
798 { 537, 1, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #537 = RRA8p
799 { 536, 1, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #536 = RRA8n
800 { 535, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 236, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #535 = RRA8m
801 { 534, 2, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 249, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #534 = RRA16r
802 { 533, 1, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #533 = RRA16p
803 { 532, 1, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 239, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #532 = RRA16n
804 { 531, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 236, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #531 = RRA16m
805 { 530, 0, 0, 2, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #530 = RETI
806 { 529, 0, 0, 2, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #529 = RET
807 { 528, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 15, 248, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #528 = PUSH8r
808 { 527, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 15, 238, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #527 = PUSH16r
809 { 526, 1, 0, 4, 0, 1, 1, MSP430ImpOpBase + 15, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #526 = PUSH16i
810 { 525, 1, 0, 2, 0, 1, 1, MSP430ImpOpBase + 15, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #525 = PUSH16c
811 { 524, 1, 1, 2, 0, 1, 1, MSP430ImpOpBase + 15, 238, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #524 = POP16r
812 { 523, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 246, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #523 = MOVZX16rr8
813 { 522, 3, 1, 4, 0, 0, 0, MSP430ImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #522 = MOVZX16rm8
814 { 521, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 234, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #521 = MOV8rr
815 { 520, 3, 2, 2, 0, 0, 0, MSP430ImpOpBase + 0, 243, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #520 = MOV8rp
816 { 519, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 232, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #519 = MOV8rn
817 { 518, 3, 1, 4, 0, 0, 0, MSP430ImpOpBase + 0, 229, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #518 = MOV8rm
818 { 517, 2, 1, 4, 0, 0, 0, MSP430ImpOpBase + 0, 227, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #517 = MOV8ri
819 { 516, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 225, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #516 = MOV8rc
820 { 515, 3, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #515 = MOV8mr
821 { 514, 3, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #514 = MOV8mn
822 { 513, 4, 0, 6, 0, 0, 0, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #513 = MOV8mm
823 { 512, 3, 0, 6, 0, 0, 0, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #512 = MOV8mi
824 { 511, 3, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #511 = MOV8mc
825 { 510, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 223, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #510 = MOV16rr
826 { 509, 3, 2, 2, 0, 0, 0, MSP430ImpOpBase + 0, 240, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #509 = MOV16rp
827 { 508, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 221, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #508 = MOV16rn
828 { 507, 3, 1, 4, 0, 0, 0, MSP430ImpOpBase + 0, 218, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #507 = MOV16rm
829 { 506, 2, 1, 4, 0, 0, 0, MSP430ImpOpBase + 0, 216, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #506 = MOV16ri
830 { 505, 2, 1, 2, 0, 0, 0, MSP430ImpOpBase + 0, 214, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #505 = MOV16rc
831 { 504, 3, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #504 = MOV16mr
832 { 503, 3, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #503 = MOV16mn
833 { 502, 4, 0, 6, 0, 0, 0, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #502 = MOV16mm
834 { 501, 3, 0, 6, 0, 0, 0, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #501 = MOV16mi
835 { 500, 3, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #500 = MOV16mc
836 { 499, 1, 0, 2, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #499 = JMP
837 { 498, 2, 0, 2, 0, 1, 0, MSP430ImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #498 = JCC
838 { 497, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 208, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #497 = DADD8rr
839 { 496, 4, 2, 2, 0, 1, 1, MSP430ImpOpBase + 1, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #496 = DADD8rp
840 { 495, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #495 = DADD8rn
841 { 494, 4, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #494 = DADD8rm
842 { 493, 3, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #493 = DADD8ri
843 { 492, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #492 = DADD8rc
844 { 491, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #491 = DADD8mr
845 { 490, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #490 = DADD8mp
846 { 489, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #489 = DADD8mn
847 { 488, 4, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #488 = DADD8mm
848 { 487, 3, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #487 = DADD8mi
849 { 486, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #486 = DADD8mc
850 { 485, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 185, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #485 = DADD16rr
851 { 484, 4, 2, 2, 0, 1, 1, MSP430ImpOpBase + 1, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #484 = DADD16rp
852 { 483, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #483 = DADD16rn
853 { 482, 4, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #482 = DADD16rm
854 { 481, 3, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #481 = DADD16ri
855 { 480, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #480 = DADD16rc
856 { 479, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #479 = DADD16mr
857 { 478, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #478 = DADD16mp
858 { 477, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #477 = DADD16mn
859 { 476, 4, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #476 = DADD16mm
860 { 475, 3, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #475 = DADD16mi
861 { 474, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #474 = DADD16mc
862 { 473, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 234, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #473 = CMP8rr
863 { 472, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #472 = CMP8rp
864 { 471, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #471 = CMP8rn
865 { 470, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #470 = CMP8rm
866 { 469, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 227, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #469 = CMP8ri
867 { 468, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 225, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #468 = CMP8rc
868 { 467, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #467 = CMP8mr
869 { 466, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #466 = CMP8mp
870 { 465, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #465 = CMP8mn
871 { 464, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #464 = CMP8mm
872 { 463, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #463 = CMP8mi
873 { 462, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #462 = CMP8mc
874 { 461, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 223, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #461 = CMP16rr
875 { 460, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #460 = CMP16rp
876 { 459, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #459 = CMP16rn
877 { 458, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #458 = CMP16rm
878 { 457, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #457 = CMP16ri
879 { 456, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 214, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #456 = CMP16rc
880 { 455, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #455 = CMP16mr
881 { 454, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #454 = CMP16mp
882 { 453, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #453 = CMP16mn
883 { 452, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #452 = CMP16mm
884 { 451, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #451 = CMP16mi
885 { 450, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #450 = CMP16mc
886 { 449, 1, 0, 2, 0, 1, 6, MSP430ImpOpBase + 8, 238, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #449 = CALLr
887 { 448, 1, 0, 2, 0, 1, 6, MSP430ImpOpBase + 8, 239, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #448 = CALLp
888 { 447, 1, 0, 2, 0, 1, 6, MSP430ImpOpBase + 8, 239, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #447 = CALLn
889 { 446, 2, 0, 4, 0, 1, 6, MSP430ImpOpBase + 8, 236, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #446 = CALLm
890 { 445, 1, 0, 4, 0, 1, 6, MSP430ImpOpBase + 8, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #445 = CALLi
891 { 444, 1, 0, 2, 0, 0, 0, MSP430ImpOpBase + 0, 238, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #444 = Br
892 { 443, 2, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 236, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #443 = Bm
893 { 442, 1, 0, 4, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #442 = Bi
894 { 441, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 234, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #441 = BIT8rr
895 { 440, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #440 = BIT8rp
896 { 439, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 232, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #439 = BIT8rn
897 { 438, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #438 = BIT8rm
898 { 437, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 227, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #437 = BIT8ri
899 { 436, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 225, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #436 = BIT8rc
900 { 435, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #435 = BIT8mr
901 { 434, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #434 = BIT8mp
902 { 433, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #433 = BIT8mn
903 { 432, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #432 = BIT8mm
904 { 431, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #431 = BIT8mi
905 { 430, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #430 = BIT8mc
906 { 429, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #429 = BIT16rr
907 { 428, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #428 = BIT16rp
908 { 427, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 221, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #427 = BIT16rn
909 { 426, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 218, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #426 = BIT16rm
910 { 425, 2, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 216, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #425 = BIT16ri
911 { 424, 2, 0, 2, 0, 0, 1, MSP430ImpOpBase + 0, 214, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #424 = BIT16rc
912 { 423, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #423 = BIT16mr
913 { 422, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #422 = BIT16mp
914 { 421, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #421 = BIT16mn
915 { 420, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #420 = BIT16mm
916 { 419, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #419 = BIT16mi
917 { 418, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #418 = BIT16mc
918 { 417, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 208, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #417 = BIS8rr
919 { 416, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #416 = BIS8rp
920 { 415, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #415 = BIS8rn
921 { 414, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #414 = BIS8rm
922 { 413, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #413 = BIS8ri
923 { 412, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #412 = BIS8rc
924 { 411, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #411 = BIS8mr
925 { 410, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #410 = BIS8mp
926 { 409, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #409 = BIS8mn
927 { 408, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #408 = BIS8mm
928 { 407, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #407 = BIS8mi
929 { 406, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #406 = BIS8mc
930 { 405, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 185, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #405 = BIS16rr
931 { 404, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #404 = BIS16rp
932 { 403, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #403 = BIS16rn
933 { 402, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #402 = BIS16rm
934 { 401, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #401 = BIS16ri
935 { 400, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #400 = BIS16rc
936 { 399, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #399 = BIS16mr
937 { 398, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #398 = BIS16mp
938 { 397, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #397 = BIS16mn
939 { 396, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #396 = BIS16mm
940 { 395, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #395 = BIS16mi
941 { 394, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #394 = BIS16mc
942 { 393, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 208, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #393 = BIC8rr
943 { 392, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #392 = BIC8rp
944 { 391, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #391 = BIC8rn
945 { 390, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #390 = BIC8rm
946 { 389, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #389 = BIC8ri
947 { 388, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #388 = BIC8rc
948 { 387, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #387 = BIC8mr
949 { 386, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #386 = BIC8mp
950 { 385, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #385 = BIC8mn
951 { 384, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #384 = BIC8mm
952 { 383, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #383 = BIC8mi
953 { 382, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #382 = BIC8mc
954 { 381, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 185, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #381 = BIC16rr
955 { 380, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #380 = BIC16rp
956 { 379, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #379 = BIC16rn
957 { 378, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #378 = BIC16rm
958 { 377, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #377 = BIC16ri
959 { 376, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #376 = BIC16rc
960 { 375, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #375 = BIC16mr
961 { 374, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #374 = BIC16mp
962 { 373, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #373 = BIC16mn
963 { 372, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #372 = BIC16mm
964 { 371, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #371 = BIC16mi
965 { 370, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #370 = BIC16mc
966 { 369, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 208, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #369 = AND8rr
967 { 368, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #368 = AND8rp
968 { 367, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #367 = AND8rn
969 { 366, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #366 = AND8rm
970 { 365, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #365 = AND8ri
971 { 364, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #364 = AND8rc
972 { 363, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #363 = AND8mr
973 { 362, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #362 = AND8mp
974 { 361, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #361 = AND8mn
975 { 360, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #360 = AND8mm
976 { 359, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #359 = AND8mi
977 { 358, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #358 = AND8mc
978 { 357, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 185, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #357 = AND16rr
979 { 356, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #356 = AND16rp
980 { 355, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #355 = AND16rn
981 { 354, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #354 = AND16rm
982 { 353, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #353 = AND16ri
983 { 352, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #352 = AND16rc
984 { 351, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #351 = AND16mr
985 { 350, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #350 = AND16mp
986 { 349, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #349 = AND16mn
987 { 348, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #348 = AND16mm
988 { 347, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #347 = AND16mi
989 { 346, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #346 = AND16mc
990 { 345, 2, 0, 0, 0, 1, 2, MSP430ImpOpBase + 5, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #345 = ADJCALLSTACKUP
991 { 344, 2, 0, 0, 0, 1, 2, MSP430ImpOpBase + 5, 21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #344 = ADJCALLSTACKDOWN
992 { 343, 3, 1, 0, 0, 1, 1, MSP430ImpOpBase + 3, 211, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #343 = ADDframe
993 { 342, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 208, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #342 = ADDC8rr
994 { 341, 4, 2, 2, 0, 1, 1, MSP430ImpOpBase + 1, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #341 = ADDC8rp
995 { 340, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #340 = ADDC8rn
996 { 339, 4, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #339 = ADDC8rm
997 { 338, 3, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #338 = ADDC8ri
998 { 337, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #337 = ADDC8rc
999 { 336, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #336 = ADDC8mr
1000 { 335, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #335 = ADDC8mp
1001 { 334, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #334 = ADDC8mn
1002 { 333, 4, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #333 = ADDC8mm
1003 { 332, 3, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #332 = ADDC8mi
1004 { 331, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #331 = ADDC8mc
1005 { 330, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 185, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #330 = ADDC16rr
1006 { 329, 4, 2, 2, 0, 1, 1, MSP430ImpOpBase + 1, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #329 = ADDC16rp
1007 { 328, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #328 = ADDC16rn
1008 { 327, 4, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #327 = ADDC16rm
1009 { 326, 3, 1, 4, 0, 1, 1, MSP430ImpOpBase + 1, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #326 = ADDC16ri
1010 { 325, 3, 1, 2, 0, 1, 1, MSP430ImpOpBase + 1, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #325 = ADDC16rc
1011 { 324, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #324 = ADDC16mr
1012 { 323, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #323 = ADDC16mp
1013 { 322, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #322 = ADDC16mn
1014 { 321, 4, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #321 = ADDC16mm
1015 { 320, 3, 0, 6, 0, 1, 1, MSP430ImpOpBase + 1, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #320 = ADDC16mi
1016 { 319, 3, 0, 4, 0, 1, 1, MSP430ImpOpBase + 1, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #319 = ADDC16mc
1017 { 318, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 208, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #318 = ADD8rr
1018 { 317, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 204, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #317 = ADD8rp
1019 { 316, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 201, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #316 = ADD8rn
1020 { 315, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 197, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #315 = ADD8rm
1021 { 314, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 194, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #314 = ADD8ri
1022 { 313, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 191, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #313 = ADD8rc
1023 { 312, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #312 = ADD8mr
1024 { 311, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #311 = ADD8mp
1025 { 310, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #310 = ADD8mn
1026 { 309, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #309 = ADD8mm
1027 { 308, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #308 = ADD8mi
1028 { 307, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #307 = ADD8mc
1029 { 306, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 185, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #306 = ADD16rr
1030 { 305, 4, 2, 2, 0, 0, 1, MSP430ImpOpBase + 0, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #305 = ADD16rp
1031 { 304, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 178, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #304 = ADD16rn
1032 { 303, 4, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 174, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #303 = ADD16rm
1033 { 302, 3, 1, 4, 0, 0, 1, MSP430ImpOpBase + 0, 171, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #302 = ADD16ri
1034 { 301, 3, 1, 2, 0, 0, 1, MSP430ImpOpBase + 0, 168, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #301 = ADD16rc
1035 { 300, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 165, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #300 = ADD16mr
1036 { 299, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #299 = ADD16mp
1037 { 298, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 162, 0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #298 = ADD16mn
1038 { 297, 4, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #297 = ADD16mm
1039 { 296, 3, 0, 6, 0, 0, 1, MSP430ImpOpBase + 0, 155, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #296 = ADD16mi
1040 { 295, 3, 0, 4, 0, 0, 1, MSP430ImpOpBase + 0, 152, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #295 = ADD16mc
1041 { 294, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #294 = G_UBFX
1042 { 293, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 148, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #293 = G_SBFX
1043 { 292, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #292 = G_VECREDUCE_UMIN
1044 { 291, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #291 = G_VECREDUCE_UMAX
1045 { 290, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #290 = G_VECREDUCE_SMIN
1046 { 289, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #289 = G_VECREDUCE_SMAX
1047 { 288, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #288 = G_VECREDUCE_XOR
1048 { 287, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #287 = G_VECREDUCE_OR
1049 { 286, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #286 = G_VECREDUCE_AND
1050 { 285, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #285 = G_VECREDUCE_MUL
1051 { 284, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #284 = G_VECREDUCE_ADD
1052 { 283, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #283 = G_VECREDUCE_FMINIMUM
1053 { 282, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #282 = G_VECREDUCE_FMAXIMUM
1054 { 281, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #281 = G_VECREDUCE_FMIN
1055 { 280, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #280 = G_VECREDUCE_FMAX
1056 { 279, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #279 = G_VECREDUCE_FMUL
1057 { 278, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #278 = G_VECREDUCE_FADD
1058 { 277, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #277 = G_VECREDUCE_SEQ_FMUL
1059 { 276, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #276 = G_VECREDUCE_SEQ_FADD
1060 { 275, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #275 = G_UBSANTRAP
1061 { 274, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #274 = G_DEBUGTRAP
1062 { 273, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #273 = G_TRAP
1063 { 272, 3, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #272 = G_BZERO
1064 { 271, 4, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #271 = G_MEMSET
1065 { 270, 4, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #270 = G_MEMMOVE
1066 { 269, 3, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #269 = G_MEMCPY_INLINE
1067 { 268, 4, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 144, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #268 = G_MEMCPY
1068 { 267, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 142, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #267 = G_WRITE_REGISTER
1069 { 266, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #266 = G_READ_REGISTER
1070 { 265, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #265 = G_STRICT_FLDEXP
1071 { 264, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #264 = G_STRICT_FSQRT
1072 { 263, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #263 = G_STRICT_FMA
1073 { 262, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #262 = G_STRICT_FREM
1074 { 261, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #261 = G_STRICT_FDIV
1075 { 260, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #260 = G_STRICT_FMUL
1076 { 259, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #259 = G_STRICT_FSUB
1077 { 258, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #258 = G_STRICT_FADD
1078 { 257, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #257 = G_STACKRESTORE
1079 { 256, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #256 = G_STACKSAVE
1080 { 255, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #255 = G_DYN_STACKALLOC
1081 { 254, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #254 = G_JUMP_TABLE
1082 { 253, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #253 = G_BLOCK_ADDR
1083 { 252, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #252 = G_ADDRSPACE_CAST
1084 { 251, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #251 = G_FNEARBYINT
1085 { 250, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #250 = G_FRINT
1086 { 249, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #249 = G_FFLOOR
1087 { 248, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #248 = G_FSQRT
1088 { 247, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #247 = G_FTANH
1089 { 246, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #246 = G_FSINH
1090 { 245, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #245 = G_FCOSH
1091 { 244, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #244 = G_FATAN
1092 { 243, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #243 = G_FASIN
1093 { 242, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #242 = G_FACOS
1094 { 241, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #241 = G_FTAN
1095 { 240, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #240 = G_FSIN
1096 { 239, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #239 = G_FCOS
1097 { 238, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #238 = G_FCEIL
1098 { 237, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #237 = G_BITREVERSE
1099 { 236, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #236 = G_BSWAP
1100 { 235, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #235 = G_CTPOP
1101 { 234, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #234 = G_CTLZ_ZERO_UNDEF
1102 { 233, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #233 = G_CTLZ
1103 { 232, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #232 = G_CTTZ_ZERO_UNDEF
1104 { 231, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #231 = G_CTTZ
1105 { 230, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 138, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #230 = G_VECTOR_COMPRESS
1106 { 229, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #229 = G_SPLAT_VECTOR
1107 { 228, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 134, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #228 = G_SHUFFLE_VECTOR
1108 { 227, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 131, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #227 = G_EXTRACT_VECTOR_ELT
1109 { 226, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 127, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #226 = G_INSERT_VECTOR_ELT
1110 { 225, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #225 = G_EXTRACT_SUBVECTOR
1111 { 224, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #224 = G_INSERT_SUBVECTOR
1112 { 223, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #223 = G_VSCALE
1113 { 222, 3, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 124, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #222 = G_BRJT
1114 { 221, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #221 = G_BR
1115 { 220, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #220 = G_LLROUND
1116 { 219, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #219 = G_LROUND
1117 { 218, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #218 = G_ABS
1118 { 217, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #217 = G_UMAX
1119 { 216, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #216 = G_UMIN
1120 { 215, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #215 = G_SMAX
1121 { 214, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #214 = G_SMIN
1122 { 213, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #213 = G_PTRMASK
1123 { 212, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #212 = G_PTR_ADD
1124 { 211, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #211 = G_RESET_FPMODE
1125 { 210, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #210 = G_SET_FPMODE
1126 { 209, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #209 = G_GET_FPMODE
1127 { 208, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #208 = G_RESET_FPENV
1128 { 207, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #207 = G_SET_FPENV
1129 { 206, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #206 = G_GET_FPENV
1130 { 205, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #205 = G_FMAXIMUM
1131 { 204, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #204 = G_FMINIMUM
1132 { 203, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #203 = G_FMAXNUM_IEEE
1133 { 202, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #202 = G_FMINNUM_IEEE
1134 { 201, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #201 = G_FMAXNUM
1135 { 200, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #200 = G_FMINNUM
1136 { 199, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #199 = G_FCANONICALIZE
1137 { 198, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #198 = G_IS_FPCLASS
1138 { 197, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #197 = G_FCOPYSIGN
1139 { 196, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #196 = G_FABS
1140 { 195, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #195 = G_UITOFP
1141 { 194, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #194 = G_SITOFP
1142 { 193, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #193 = G_FPTOUI
1143 { 192, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #192 = G_FPTOSI
1144 { 191, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #191 = G_FPTRUNC
1145 { 190, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #190 = G_FPEXT
1146 { 189, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #189 = G_FNEG
1147 { 188, 3, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #188 = G_FFREXP
1148 { 187, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #187 = G_FLDEXP
1149 { 186, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #186 = G_FLOG10
1150 { 185, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #185 = G_FLOG2
1151 { 184, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #184 = G_FLOG
1152 { 183, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #183 = G_FEXP10
1153 { 182, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #182 = G_FEXP2
1154 { 181, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #181 = G_FEXP
1155 { 180, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #180 = G_FPOWI
1156 { 179, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #179 = G_FPOW
1157 { 178, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #178 = G_FREM
1158 { 177, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #177 = G_FDIV
1159 { 176, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #176 = G_FMAD
1160 { 175, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #175 = G_FMA
1161 { 174, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #174 = G_FMUL
1162 { 173, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #173 = G_FSUB
1163 { 172, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #172 = G_FADD
1164 { 171, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #171 = G_UDIVFIXSAT
1165 { 170, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #170 = G_SDIVFIXSAT
1166 { 169, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #169 = G_UDIVFIX
1167 { 168, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #168 = G_SDIVFIX
1168 { 167, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #167 = G_UMULFIXSAT
1169 { 166, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #166 = G_SMULFIXSAT
1170 { 165, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #165 = G_UMULFIX
1171 { 164, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 120, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #164 = G_SMULFIX
1172 { 163, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #163 = G_SSHLSAT
1173 { 162, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #162 = G_USHLSAT
1174 { 161, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #161 = G_SSUBSAT
1175 { 160, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #160 = G_USUBSAT
1176 { 159, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #159 = G_SADDSAT
1177 { 158, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #158 = G_UADDSAT
1178 { 157, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #157 = G_SMULH
1179 { 156, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #156 = G_UMULH
1180 { 155, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #155 = G_SMULO
1181 { 154, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #154 = G_UMULO
1182 { 153, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #153 = G_SSUBE
1183 { 152, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #152 = G_SSUBO
1184 { 151, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #151 = G_SADDE
1185 { 150, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #150 = G_SADDO
1186 { 149, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #149 = G_USUBE
1187 { 148, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #148 = G_USUBO
1188 { 147, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 115, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #147 = G_UADDE
1189 { 146, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #146 = G_UADDO
1190 { 145, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #145 = G_SELECT
1191 { 144, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #144 = G_UCMP
1192 { 143, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #143 = G_SCMP
1193 { 142, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #142 = G_FCMP
1194 { 141, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 108, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #141 = G_ICMP
1195 { 140, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #140 = G_ROTL
1196 { 139, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #139 = G_ROTR
1197 { 138, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #138 = G_FSHR
1198 { 137, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 104, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #137 = G_FSHL
1199 { 136, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #136 = G_ASHR
1200 { 135, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #135 = G_LSHR
1201 { 134, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 101, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #134 = G_SHL
1202 { 133, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #133 = G_ZEXT
1203 { 132, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #132 = G_SEXT_INREG
1204 { 131, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #131 = G_SEXT
1205 { 130, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 98, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #130 = G_VAARG
1206 { 129, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #129 = G_VASTART
1207 { 128, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #128 = G_FCONSTANT
1208 { 127, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #127 = G_CONSTANT
1209 { 126, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #126 = G_TRUNC
1210 { 125, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #125 = G_ANYEXT
1211 { 124, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #124 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1212 { 123, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #123 = G_INTRINSIC_CONVERGENT
1213 { 122, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #122 = G_INTRINSIC_W_SIDE_EFFECTS
1214 { 121, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #121 = G_INTRINSIC
1215 { 120, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #120 = G_INVOKE_REGION_START
1216 { 119, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #119 = G_BRINDIRECT
1217 { 118, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #118 = G_BRCOND
1218 { 117, 4, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 94, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #117 = G_PREFETCH
1219 { 116, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #116 = G_FENCE
1220 { 115, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #115 = G_ATOMICRMW_UDEC_WRAP
1221 { 114, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #114 = G_ATOMICRMW_UINC_WRAP
1222 { 113, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #113 = G_ATOMICRMW_FMIN
1223 { 112, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #112 = G_ATOMICRMW_FMAX
1224 { 111, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #111 = G_ATOMICRMW_FSUB
1225 { 110, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #110 = G_ATOMICRMW_FADD
1226 { 109, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #109 = G_ATOMICRMW_UMIN
1227 { 108, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UMAX
1228 { 107, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #107 = G_ATOMICRMW_MIN
1229 { 106, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #106 = G_ATOMICRMW_MAX
1230 { 105, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #105 = G_ATOMICRMW_XOR
1231 { 104, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #104 = G_ATOMICRMW_OR
1232 { 103, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #103 = G_ATOMICRMW_NAND
1233 { 102, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #102 = G_ATOMICRMW_AND
1234 { 101, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #101 = G_ATOMICRMW_SUB
1235 { 100, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #100 = G_ATOMICRMW_ADD
1236 { 99, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 91, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #99 = G_ATOMICRMW_XCHG
1237 { 98, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 87, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #98 = G_ATOMIC_CMPXCHG
1238 { 97, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #97 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1239 { 96, 5, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #96 = G_INDEXED_STORE
1240 { 95, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #95 = G_STORE
1241 { 94, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #94 = G_INDEXED_ZEXTLOAD
1242 { 93, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #93 = G_INDEXED_SEXTLOAD
1243 { 92, 5, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #92 = G_INDEXED_LOAD
1244 { 91, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #91 = G_ZEXTLOAD
1245 { 90, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #90 = G_SEXTLOAD
1246 { 89, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #89 = G_LOAD
1247 { 88, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #88 = G_READSTEADYCOUNTER
1248 { 87, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #87 = G_READCYCLECOUNTER
1249 { 86, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #86 = G_INTRINSIC_ROUNDEVEN
1250 { 85, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #85 = G_INTRINSIC_LLRINT
1251 { 84, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #84 = G_INTRINSIC_LRINT
1252 { 83, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #83 = G_INTRINSIC_ROUND
1253 { 82, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #82 = G_INTRINSIC_TRUNC
1254 { 81, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 69, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #81 = G_INTRINSIC_FPTRUNC_ROUND
1255 { 80, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #80 = G_CONSTANT_FOLD_BARRIER
1256 { 79, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #79 = G_FREEZE
1257 { 78, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #78 = G_BITCAST
1258 { 77, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #77 = G_INTTOPTR
1259 { 76, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #76 = G_PTRTOINT
1260 { 75, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #75 = G_CONCAT_VECTORS
1261 { 74, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #74 = G_BUILD_VECTOR_TRUNC
1262 { 73, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #73 = G_BUILD_VECTOR
1263 { 72, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #72 = G_MERGE_VALUES
1264 { 71, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 63, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #71 = G_INSERT
1265 { 70, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 61, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #70 = G_UNMERGE_VALUES
1266 { 69, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #69 = G_EXTRACT
1267 { 68, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #68 = G_CONSTANT_POOL
1268 { 67, 5, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #67 = G_PTRAUTH_GLOBAL_VALUE
1269 { 66, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #66 = G_GLOBAL_VALUE
1270 { 65, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #65 = G_FRAME_INDEX
1271 { 64, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #64 = G_PHI
1272 { 63, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #63 = G_IMPLICIT_DEF
1273 { 62, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #62 = G_XOR
1274 { 61, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #61 = G_OR
1275 { 60, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #60 = G_AND
1276 { 59, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #59 = G_UDIVREM
1277 { 58, 4, 2, 0, 0, 0, 0, MSP430ImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #58 = G_SDIVREM
1278 { 57, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #57 = G_UREM
1279 { 56, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #56 = G_SREM
1280 { 55, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #55 = G_UDIV
1281 { 54, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #54 = G_SDIV
1282 { 53, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #53 = G_MUL
1283 { 52, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #52 = G_SUB
1284 { 51, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #51 = G_ADD
1285 { 50, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #50 = G_ASSERT_ALIGN
1286 { 49, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #49 = G_ASSERT_ZEXT
1287 { 48, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #48 = G_ASSERT_SEXT
1288 { 47, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #47 = CONVERGENCECTRL_GLUE
1289 { 46, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #46 = CONVERGENCECTRL_LOOP
1290 { 45, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #45 = CONVERGENCECTRL_ANCHOR
1291 { 44, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #44 = CONVERGENCECTRL_ENTRY
1292 { 43, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO
1293 { 42, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #42 = MEMBARRIER
1294 { 41, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL
1295 { 40, 3, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1296 { 39, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL
1297 { 38, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL
1298 { 37, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT
1299 { 36, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #36 = PATCHABLE_RET
1300 { 35, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER
1301 { 34, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #34 = PATCHABLE_OP
1302 { 33, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #33 = FAULTING_OP
1303 { 32, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE
1304 { 31, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #31 = STATEPOINT
1305 { 30, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG
1306 { 29, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP
1307 { 28, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD
1308 { 27, 6, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #27 = PATCHPOINT
1309 { 26, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #26 = FENTRY_CALL
1310 { 25, 2, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #25 = STACKMAP
1311 { 24, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #24 = ARITH_FENCE
1312 { 23, 4, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #23 = PSEUDO_PROBE
1313 { 22, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #22 = LIFETIME_END
1314 { 21, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #21 = LIFETIME_START
1315 { 20, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #20 = BUNDLE
1316 { 19, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #19 = COPY
1317 { 18, 2, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #18 = REG_SEQUENCE
1318 { 17, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #17 = DBG_LABEL
1319 { 16, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #16 = DBG_PHI
1320 { 15, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #15 = DBG_INSTR_REF
1321 { 14, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST
1322 { 13, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #13 = DBG_VALUE
1323 { 12, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS
1324 { 11, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #11 = SUBREG_TO_REG
1325 { 10, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #10 = IMPLICIT_DEF
1326 { 9, 4, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #9 = INSERT_SUBREG
1327 { 8, 3, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG
1328 { 7, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #7 = KILL
1329 { 6, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL
1330 { 5, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #5 = GC_LABEL
1331 { 4, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #4 = EH_LABEL
1332 { 3, 1, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION
1333 { 2, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #2 = INLINEASM_BR
1334 { 1, 0, 0, 0, 0, 0, 0, MSP430ImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #1 = INLINEASM
1335 { 0, 1, 1, 0, 0, 0, 0, MSP430ImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL }, // Inst #0 = PHI
1336 }, {
1337 /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1338 /* 1 */
1339 /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1340 /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1341 /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1342 /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1343 /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1344 /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1345 /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1346 /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1347 /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1348 /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1349 /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1350 /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1351 /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1352 /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1353 /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1354 /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1355 /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1356 /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1357 /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1358 /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1359 /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1360 /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1361 /* 63 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1362 /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1363 /* 69 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1364 /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1365 /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1366 /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1367 /* 87 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1368 /* 91 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1369 /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1370 /* 98 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1371 /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1372 /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1373 /* 108 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1374 /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1375 /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1376 /* 120 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1377 /* 124 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1378 /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1379 /* 131 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1380 /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1381 /* 138 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1382 /* 142 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1383 /* 144 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1384 /* 148 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1385 /* 152 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1386 /* 155 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1387 /* 158 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1388 /* 162 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1389 /* 165 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1390 /* 168 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1391 /* 171 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1392 /* 174 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1393 /* 178 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1394 /* 181 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1395 /* 185 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1396 /* 188 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1397 /* 191 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1398 /* 194 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1399 /* 197 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1400 /* 201 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1401 /* 204 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1402 /* 208 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1403 /* 211 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1404 /* 214 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1405 /* 216 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1406 /* 218 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1407 /* 221 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1408 /* 223 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1409 /* 225 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1410 /* 227 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1411 /* 229 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1412 /* 232 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1413 /* 234 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1414 /* 236 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1415 /* 238 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1416 /* 239 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1417 /* 240 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1418 /* 243 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1419 /* 246 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1420 /* 248 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1421 /* 249 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1422 /* 251 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1423 /* 253 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1424 /* 257 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1425 /* 261 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1426 /* 264 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1427 }, {
1428 /* 0 */
1429 /* 0 */ MSP430::SR,
1430 /* 1 */ MSP430::SR, MSP430::SR,
1431 /* 3 */ MSP430::SP, MSP430::SR,
1432 /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1433 /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1434 /* 15 */ MSP430::SP, MSP430::SP,
1435 }
1436};
1437
1438
1439#ifdef __GNUC__
1440#pragma GCC diagnostic push
1441#pragma GCC diagnostic ignored "-Woverlength-strings"
1442#endif
1443extern const char MSP430InstrNameData[] = {
1444 /* 0 */ "G_FLOG10\0"
1445 /* 9 */ "G_FEXP10\0"
1446 /* 18 */ "G_FLOG2\0"
1447 /* 26 */ "G_FEXP2\0"
1448 /* 34 */ "Sra16\0"
1449 /* 40 */ "Rrcl16\0"
1450 /* 47 */ "Shl16\0"
1451 /* 53 */ "Srl16\0"
1452 /* 59 */ "Select16\0"
1453 /* 68 */ "Sra8\0"
1454 /* 73 */ "Rrcl8\0"
1455 /* 79 */ "Shl8\0"
1456 /* 84 */ "Srl8\0"
1457 /* 89 */ "MOVZX16rm8\0"
1458 /* 100 */ "MOVZX16rr8\0"
1459 /* 111 */ "Select8\0"
1460 /* 119 */ "G_FMA\0"
1461 /* 125 */ "G_STRICT_FMA\0"
1462 /* 138 */ "G_FSUB\0"
1463 /* 145 */ "G_STRICT_FSUB\0"
1464 /* 159 */ "G_ATOMICRMW_FSUB\0"
1465 /* 176 */ "G_SUB\0"
1466 /* 182 */ "G_ATOMICRMW_SUB\0"
1467 /* 198 */ "JCC\0"
1468 /* 202 */ "G_INTRINSIC\0"
1469 /* 214 */ "G_FPTRUNC\0"
1470 /* 224 */ "G_INTRINSIC_TRUNC\0"
1471 /* 242 */ "G_TRUNC\0"
1472 /* 250 */ "G_BUILD_VECTOR_TRUNC\0"
1473 /* 271 */ "G_DYN_STACKALLOC\0"
1474 /* 288 */ "G_FMAD\0"
1475 /* 295 */ "G_INDEXED_SEXTLOAD\0"
1476 /* 314 */ "G_SEXTLOAD\0"
1477 /* 325 */ "G_INDEXED_ZEXTLOAD\0"
1478 /* 344 */ "G_ZEXTLOAD\0"
1479 /* 355 */ "G_INDEXED_LOAD\0"
1480 /* 370 */ "G_LOAD\0"
1481 /* 377 */ "G_VECREDUCE_FADD\0"
1482 /* 394 */ "G_FADD\0"
1483 /* 401 */ "G_VECREDUCE_SEQ_FADD\0"
1484 /* 422 */ "G_STRICT_FADD\0"
1485 /* 436 */ "G_ATOMICRMW_FADD\0"
1486 /* 453 */ "G_VECREDUCE_ADD\0"
1487 /* 469 */ "G_ADD\0"
1488 /* 475 */ "G_PTR_ADD\0"
1489 /* 485 */ "G_ATOMICRMW_ADD\0"
1490 /* 501 */ "G_ATOMICRMW_NAND\0"
1491 /* 518 */ "G_VECREDUCE_AND\0"
1492 /* 534 */ "G_AND\0"
1493 /* 540 */ "G_ATOMICRMW_AND\0"
1494 /* 556 */ "LIFETIME_END\0"
1495 /* 569 */ "G_BRCOND\0"
1496 /* 578 */ "G_LLROUND\0"
1497 /* 588 */ "G_LROUND\0"
1498 /* 597 */ "G_INTRINSIC_ROUND\0"
1499 /* 615 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1500 /* 641 */ "LOAD_STACK_GUARD\0"
1501 /* 658 */ "PSEUDO_PROBE\0"
1502 /* 671 */ "G_SSUBE\0"
1503 /* 679 */ "G_USUBE\0"
1504 /* 687 */ "G_FENCE\0"
1505 /* 695 */ "ARITH_FENCE\0"
1506 /* 707 */ "REG_SEQUENCE\0"
1507 /* 720 */ "G_SADDE\0"
1508 /* 728 */ "G_UADDE\0"
1509 /* 736 */ "G_GET_FPMODE\0"
1510 /* 749 */ "G_RESET_FPMODE\0"
1511 /* 764 */ "G_SET_FPMODE\0"
1512 /* 777 */ "G_FMINNUM_IEEE\0"
1513 /* 792 */ "G_FMAXNUM_IEEE\0"
1514 /* 807 */ "G_VSCALE\0"
1515 /* 816 */ "G_JUMP_TABLE\0"
1516 /* 829 */ "BUNDLE\0"
1517 /* 836 */ "G_MEMCPY_INLINE\0"
1518 /* 852 */ "LOCAL_ESCAPE\0"
1519 /* 865 */ "G_STACKRESTORE\0"
1520 /* 880 */ "G_INDEXED_STORE\0"
1521 /* 896 */ "G_STORE\0"
1522 /* 904 */ "G_BITREVERSE\0"
1523 /* 917 */ "DBG_VALUE\0"
1524 /* 927 */ "G_GLOBAL_VALUE\0"
1525 /* 942 */ "G_PTRAUTH_GLOBAL_VALUE\0"
1526 /* 965 */ "CONVERGENCECTRL_GLUE\0"
1527 /* 986 */ "G_STACKSAVE\0"
1528 /* 998 */ "G_MEMMOVE\0"
1529 /* 1008 */ "G_FREEZE\0"
1530 /* 1017 */ "G_FCANONICALIZE\0"
1531 /* 1033 */ "G_CTLZ_ZERO_UNDEF\0"
1532 /* 1051 */ "G_CTTZ_ZERO_UNDEF\0"
1533 /* 1069 */ "G_IMPLICIT_DEF\0"
1534 /* 1084 */ "DBG_INSTR_REF\0"
1535 /* 1098 */ "G_FNEG\0"
1536 /* 1105 */ "EXTRACT_SUBREG\0"
1537 /* 1120 */ "INSERT_SUBREG\0"
1538 /* 1134 */ "G_SEXT_INREG\0"
1539 /* 1147 */ "SUBREG_TO_REG\0"
1540 /* 1161 */ "G_ATOMIC_CMPXCHG\0"
1541 /* 1178 */ "G_ATOMICRMW_XCHG\0"
1542 /* 1195 */ "G_FLOG\0"
1543 /* 1202 */ "G_VAARG\0"
1544 /* 1210 */ "PREALLOCATED_ARG\0"
1545 /* 1227 */ "G_PREFETCH\0"
1546 /* 1238 */ "G_SMULH\0"
1547 /* 1246 */ "G_UMULH\0"
1548 /* 1254 */ "G_FTANH\0"
1549 /* 1262 */ "G_FSINH\0"
1550 /* 1270 */ "G_FCOSH\0"
1551 /* 1278 */ "DBG_PHI\0"
1552 /* 1286 */ "G_FPTOSI\0"
1553 /* 1295 */ "RETI\0"
1554 /* 1300 */ "G_FPTOUI\0"
1555 /* 1309 */ "G_FPOWI\0"
1556 /* 1317 */ "G_PTRMASK\0"
1557 /* 1327 */ "GC_LABEL\0"
1558 /* 1336 */ "DBG_LABEL\0"
1559 /* 1346 */ "EH_LABEL\0"
1560 /* 1355 */ "ANNOTATION_LABEL\0"
1561 /* 1372 */ "ICALL_BRANCH_FUNNEL\0"
1562 /* 1392 */ "G_FSHL\0"
1563 /* 1399 */ "G_SHL\0"
1564 /* 1405 */ "G_FCEIL\0"
1565 /* 1413 */ "PATCHABLE_TAIL_CALL\0"
1566 /* 1433 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1567 /* 1460 */ "PATCHABLE_EVENT_CALL\0"
1568 /* 1481 */ "FENTRY_CALL\0"
1569 /* 1493 */ "KILL\0"
1570 /* 1498 */ "G_CONSTANT_POOL\0"
1571 /* 1514 */ "G_ROTL\0"
1572 /* 1521 */ "G_VECREDUCE_FMUL\0"
1573 /* 1538 */ "G_FMUL\0"
1574 /* 1545 */ "G_VECREDUCE_SEQ_FMUL\0"
1575 /* 1566 */ "G_STRICT_FMUL\0"
1576 /* 1580 */ "G_VECREDUCE_MUL\0"
1577 /* 1596 */ "G_MUL\0"
1578 /* 1602 */ "G_FREM\0"
1579 /* 1609 */ "G_STRICT_FREM\0"
1580 /* 1623 */ "G_SREM\0"
1581 /* 1630 */ "G_UREM\0"
1582 /* 1637 */ "G_SDIVREM\0"
1583 /* 1647 */ "G_UDIVREM\0"
1584 /* 1657 */ "INLINEASM\0"
1585 /* 1667 */ "G_VECREDUCE_FMINIMUM\0"
1586 /* 1688 */ "G_FMINIMUM\0"
1587 /* 1699 */ "G_VECREDUCE_FMAXIMUM\0"
1588 /* 1720 */ "G_FMAXIMUM\0"
1589 /* 1731 */ "G_FMINNUM\0"
1590 /* 1741 */ "G_FMAXNUM\0"
1591 /* 1751 */ "G_FATAN\0"
1592 /* 1759 */ "G_FTAN\0"
1593 /* 1766 */ "G_INTRINSIC_ROUNDEVEN\0"
1594 /* 1788 */ "G_ASSERT_ALIGN\0"
1595 /* 1803 */ "G_FCOPYSIGN\0"
1596 /* 1815 */ "G_VECREDUCE_FMIN\0"
1597 /* 1832 */ "G_ATOMICRMW_FMIN\0"
1598 /* 1849 */ "G_VECREDUCE_SMIN\0"
1599 /* 1866 */ "G_SMIN\0"
1600 /* 1873 */ "G_VECREDUCE_UMIN\0"
1601 /* 1890 */ "G_UMIN\0"
1602 /* 1897 */ "G_ATOMICRMW_UMIN\0"
1603 /* 1914 */ "G_ATOMICRMW_MIN\0"
1604 /* 1930 */ "G_FASIN\0"
1605 /* 1938 */ "G_FSIN\0"
1606 /* 1945 */ "CFI_INSTRUCTION\0"
1607 /* 1961 */ "ADJCALLSTACKDOWN\0"
1608 /* 1978 */ "G_SSUBO\0"
1609 /* 1986 */ "G_USUBO\0"
1610 /* 1994 */ "G_SADDO\0"
1611 /* 2002 */ "G_UADDO\0"
1612 /* 2010 */ "JUMP_TABLE_DEBUG_INFO\0"
1613 /* 2032 */ "G_SMULO\0"
1614 /* 2040 */ "G_UMULO\0"
1615 /* 2048 */ "G_BZERO\0"
1616 /* 2056 */ "STACKMAP\0"
1617 /* 2065 */ "G_DEBUGTRAP\0"
1618 /* 2077 */ "G_UBSANTRAP\0"
1619 /* 2089 */ "G_TRAP\0"
1620 /* 2096 */ "G_ATOMICRMW_UDEC_WRAP\0"
1621 /* 2118 */ "G_ATOMICRMW_UINC_WRAP\0"
1622 /* 2140 */ "G_BSWAP\0"
1623 /* 2148 */ "G_SITOFP\0"
1624 /* 2157 */ "G_UITOFP\0"
1625 /* 2166 */ "G_FCMP\0"
1626 /* 2173 */ "G_ICMP\0"
1627 /* 2180 */ "G_SCMP\0"
1628 /* 2187 */ "G_UCMP\0"
1629 /* 2194 */ "JMP\0"
1630 /* 2198 */ "CONVERGENCECTRL_LOOP\0"
1631 /* 2219 */ "G_CTPOP\0"
1632 /* 2227 */ "PATCHABLE_OP\0"
1633 /* 2240 */ "FAULTING_OP\0"
1634 /* 2252 */ "ADJCALLSTACKUP\0"
1635 /* 2267 */ "PREALLOCATED_SETUP\0"
1636 /* 2286 */ "G_FLDEXP\0"
1637 /* 2295 */ "G_STRICT_FLDEXP\0"
1638 /* 2311 */ "G_FEXP\0"
1639 /* 2318 */ "G_FFREXP\0"
1640 /* 2327 */ "G_BR\0"
1641 /* 2332 */ "INLINEASM_BR\0"
1642 /* 2345 */ "G_BLOCK_ADDR\0"
1643 /* 2358 */ "MEMBARRIER\0"
1644 /* 2369 */ "G_CONSTANT_FOLD_BARRIER\0"
1645 /* 2393 */ "PATCHABLE_FUNCTION_ENTER\0"
1646 /* 2418 */ "G_READCYCLECOUNTER\0"
1647 /* 2437 */ "G_READSTEADYCOUNTER\0"
1648 /* 2457 */ "G_READ_REGISTER\0"
1649 /* 2473 */ "G_WRITE_REGISTER\0"
1650 /* 2490 */ "G_ASHR\0"
1651 /* 2497 */ "G_FSHR\0"
1652 /* 2504 */ "G_LSHR\0"
1653 /* 2511 */ "CONVERGENCECTRL_ANCHOR\0"
1654 /* 2534 */ "G_FFLOOR\0"
1655 /* 2543 */ "G_EXTRACT_SUBVECTOR\0"
1656 /* 2563 */ "G_INSERT_SUBVECTOR\0"
1657 /* 2582 */ "G_BUILD_VECTOR\0"
1658 /* 2597 */ "G_SHUFFLE_VECTOR\0"
1659 /* 2614 */ "G_SPLAT_VECTOR\0"
1660 /* 2629 */ "G_VECREDUCE_XOR\0"
1661 /* 2645 */ "G_XOR\0"
1662 /* 2651 */ "G_ATOMICRMW_XOR\0"
1663 /* 2667 */ "G_VECREDUCE_OR\0"
1664 /* 2682 */ "G_OR\0"
1665 /* 2687 */ "G_ATOMICRMW_OR\0"
1666 /* 2702 */ "G_ROTR\0"
1667 /* 2709 */ "G_INTTOPTR\0"
1668 /* 2720 */ "G_FABS\0"
1669 /* 2727 */ "G_ABS\0"
1670 /* 2733 */ "G_UNMERGE_VALUES\0"
1671 /* 2750 */ "G_MERGE_VALUES\0"
1672 /* 2765 */ "G_FACOS\0"
1673 /* 2773 */ "G_FCOS\0"
1674 /* 2780 */ "G_CONCAT_VECTORS\0"
1675 /* 2797 */ "COPY_TO_REGCLASS\0"
1676 /* 2814 */ "G_IS_FPCLASS\0"
1677 /* 2827 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1678 /* 2857 */ "G_VECTOR_COMPRESS\0"
1679 /* 2875 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1680 /* 2902 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1681 /* 2940 */ "G_SSUBSAT\0"
1682 /* 2950 */ "G_USUBSAT\0"
1683 /* 2960 */ "G_SADDSAT\0"
1684 /* 2970 */ "G_UADDSAT\0"
1685 /* 2980 */ "G_SSHLSAT\0"
1686 /* 2990 */ "G_USHLSAT\0"
1687 /* 3000 */ "G_SMULFIXSAT\0"
1688 /* 3013 */ "G_UMULFIXSAT\0"
1689 /* 3026 */ "G_SDIVFIXSAT\0"
1690 /* 3039 */ "G_UDIVFIXSAT\0"
1691 /* 3052 */ "G_EXTRACT\0"
1692 /* 3062 */ "G_SELECT\0"
1693 /* 3071 */ "G_BRINDIRECT\0"
1694 /* 3084 */ "PATCHABLE_RET\0"
1695 /* 3098 */ "G_MEMSET\0"
1696 /* 3107 */ "PATCHABLE_FUNCTION_EXIT\0"
1697 /* 3131 */ "G_BRJT\0"
1698 /* 3138 */ "G_EXTRACT_VECTOR_ELT\0"
1699 /* 3159 */ "G_INSERT_VECTOR_ELT\0"
1700 /* 3179 */ "G_FCONSTANT\0"
1701 /* 3191 */ "G_CONSTANT\0"
1702 /* 3202 */ "G_INTRINSIC_CONVERGENT\0"
1703 /* 3225 */ "STATEPOINT\0"
1704 /* 3236 */ "PATCHPOINT\0"
1705 /* 3247 */ "G_PTRTOINT\0"
1706 /* 3258 */ "G_FRINT\0"
1707 /* 3266 */ "G_INTRINSIC_LLRINT\0"
1708 /* 3285 */ "G_INTRINSIC_LRINT\0"
1709 /* 3303 */ "G_FNEARBYINT\0"
1710 /* 3316 */ "G_VASTART\0"
1711 /* 3326 */ "LIFETIME_START\0"
1712 /* 3341 */ "G_INVOKE_REGION_START\0"
1713 /* 3363 */ "G_INSERT\0"
1714 /* 3372 */ "G_FSQRT\0"
1715 /* 3380 */ "G_STRICT_FSQRT\0"
1716 /* 3395 */ "G_BITCAST\0"
1717 /* 3405 */ "G_ADDRSPACE_CAST\0"
1718 /* 3422 */ "DBG_VALUE_LIST\0"
1719 /* 3437 */ "G_FPEXT\0"
1720 /* 3445 */ "G_SEXT\0"
1721 /* 3452 */ "G_ASSERT_SEXT\0"
1722 /* 3466 */ "G_ANYEXT\0"
1723 /* 3475 */ "G_ZEXT\0"
1724 /* 3482 */ "G_ASSERT_ZEXT\0"
1725 /* 3496 */ "G_FDIV\0"
1726 /* 3503 */ "G_STRICT_FDIV\0"
1727 /* 3517 */ "G_SDIV\0"
1728 /* 3524 */ "G_UDIV\0"
1729 /* 3531 */ "G_GET_FPENV\0"
1730 /* 3543 */ "G_RESET_FPENV\0"
1731 /* 3557 */ "G_SET_FPENV\0"
1732 /* 3569 */ "G_FPOW\0"
1733 /* 3576 */ "G_VECREDUCE_FMAX\0"
1734 /* 3593 */ "G_ATOMICRMW_FMAX\0"
1735 /* 3610 */ "G_VECREDUCE_SMAX\0"
1736 /* 3627 */ "G_SMAX\0"
1737 /* 3634 */ "G_VECREDUCE_UMAX\0"
1738 /* 3651 */ "G_UMAX\0"
1739 /* 3658 */ "G_ATOMICRMW_UMAX\0"
1740 /* 3675 */ "G_ATOMICRMW_MAX\0"
1741 /* 3691 */ "G_FRAME_INDEX\0"
1742 /* 3705 */ "G_SBFX\0"
1743 /* 3712 */ "G_UBFX\0"
1744 /* 3719 */ "G_SMULFIX\0"
1745 /* 3729 */ "G_UMULFIX\0"
1746 /* 3739 */ "G_SDIVFIX\0"
1747 /* 3749 */ "G_UDIVFIX\0"
1748 /* 3759 */ "G_MEMCPY\0"
1749 /* 3768 */ "COPY\0"
1750 /* 3773 */ "CONVERGENCECTRL_ENTRY\0"
1751 /* 3795 */ "G_CTLZ\0"
1752 /* 3802 */ "G_CTTZ\0"
1753 /* 3809 */ "PUSH16c\0"
1754 /* 3817 */ "SUB16mc\0"
1755 /* 3825 */ "SUBC16mc\0"
1756 /* 3834 */ "ADDC16mc\0"
1757 /* 3843 */ "BIC16mc\0"
1758 /* 3851 */ "DADD16mc\0"
1759 /* 3860 */ "AND16mc\0"
1760 /* 3868 */ "CMP16mc\0"
1761 /* 3876 */ "XOR16mc\0"
1762 /* 3884 */ "BIS16mc\0"
1763 /* 3892 */ "BIT16mc\0"
1764 /* 3900 */ "MOV16mc\0"
1765 /* 3908 */ "SUB8mc\0"
1766 /* 3915 */ "SUBC8mc\0"
1767 /* 3923 */ "ADDC8mc\0"
1768 /* 3931 */ "BIC8mc\0"
1769 /* 3938 */ "DADD8mc\0"
1770 /* 3946 */ "AND8mc\0"
1771 /* 3953 */ "CMP8mc\0"
1772 /* 3960 */ "XOR8mc\0"
1773 /* 3967 */ "BIS8mc\0"
1774 /* 3974 */ "BIT8mc\0"
1775 /* 3981 */ "MOV8mc\0"
1776 /* 3988 */ "SUB16rc\0"
1777 /* 3996 */ "SUBC16rc\0"
1778 /* 4005 */ "ADDC16rc\0"
1779 /* 4014 */ "BIC16rc\0"
1780 /* 4022 */ "DADD16rc\0"
1781 /* 4031 */ "AND16rc\0"
1782 /* 4039 */ "CMP16rc\0"
1783 /* 4047 */ "XOR16rc\0"
1784 /* 4055 */ "BIS16rc\0"
1785 /* 4063 */ "BIT16rc\0"
1786 /* 4071 */ "MOV16rc\0"
1787 /* 4079 */ "SUB8rc\0"
1788 /* 4086 */ "SUBC8rc\0"
1789 /* 4094 */ "ADDC8rc\0"
1790 /* 4102 */ "BIC8rc\0"
1791 /* 4109 */ "DADD8rc\0"
1792 /* 4117 */ "AND8rc\0"
1793 /* 4124 */ "CMP8rc\0"
1794 /* 4131 */ "XOR8rc\0"
1795 /* 4138 */ "BIS8rc\0"
1796 /* 4145 */ "BIT8rc\0"
1797 /* 4152 */ "MOV8rc\0"
1798 /* 4159 */ "ADDframe\0"
1799 /* 4168 */ "PUSH16i\0"
1800 /* 4176 */ "Bi\0"
1801 /* 4179 */ "CALLi\0"
1802 /* 4185 */ "SUB16mi\0"
1803 /* 4193 */ "SUBC16mi\0"
1804 /* 4202 */ "ADDC16mi\0"
1805 /* 4211 */ "BIC16mi\0"
1806 /* 4219 */ "DADD16mi\0"
1807 /* 4228 */ "AND16mi\0"
1808 /* 4236 */ "CMP16mi\0"
1809 /* 4244 */ "XOR16mi\0"
1810 /* 4252 */ "BIS16mi\0"
1811 /* 4260 */ "BIT16mi\0"
1812 /* 4268 */ "MOV16mi\0"
1813 /* 4276 */ "SUB8mi\0"
1814 /* 4283 */ "SUBC8mi\0"
1815 /* 4291 */ "ADDC8mi\0"
1816 /* 4299 */ "BIC8mi\0"
1817 /* 4306 */ "DADD8mi\0"
1818 /* 4314 */ "AND8mi\0"
1819 /* 4321 */ "CMP8mi\0"
1820 /* 4328 */ "XOR8mi\0"
1821 /* 4335 */ "BIS8mi\0"
1822 /* 4342 */ "BIT8mi\0"
1823 /* 4349 */ "MOV8mi\0"
1824 /* 4356 */ "SUB16ri\0"
1825 /* 4364 */ "SUBC16ri\0"
1826 /* 4373 */ "ADDC16ri\0"
1827 /* 4382 */ "BIC16ri\0"
1828 /* 4390 */ "DADD16ri\0"
1829 /* 4399 */ "AND16ri\0"
1830 /* 4407 */ "CMP16ri\0"
1831 /* 4415 */ "XOR16ri\0"
1832 /* 4423 */ "BIS16ri\0"
1833 /* 4431 */ "BIT16ri\0"
1834 /* 4439 */ "MOV16ri\0"
1835 /* 4447 */ "SUB8ri\0"
1836 /* 4454 */ "SUBC8ri\0"
1837 /* 4462 */ "ADDC8ri\0"
1838 /* 4470 */ "BIC8ri\0"
1839 /* 4477 */ "DADD8ri\0"
1840 /* 4485 */ "AND8ri\0"
1841 /* 4492 */ "CMP8ri\0"
1842 /* 4499 */ "XOR8ri\0"
1843 /* 4506 */ "BIS8ri\0"
1844 /* 4513 */ "BIT8ri\0"
1845 /* 4520 */ "MOV8ri\0"
1846 /* 4527 */ "RRA16m\0"
1847 /* 4534 */ "SWPB16m\0"
1848 /* 4542 */ "RRC16m\0"
1849 /* 4549 */ "SEXT16m\0"
1850 /* 4557 */ "RRA8m\0"
1851 /* 4563 */ "RRC8m\0"
1852 /* 4569 */ "Bm\0"
1853 /* 4572 */ "CALLm\0"
1854 /* 4578 */ "SUB16mm\0"
1855 /* 4586 */ "SUBC16mm\0"
1856 /* 4595 */ "ADDC16mm\0"
1857 /* 4604 */ "BIC16mm\0"
1858 /* 4612 */ "DADD16mm\0"
1859 /* 4621 */ "AND16mm\0"
1860 /* 4629 */ "CMP16mm\0"
1861 /* 4637 */ "XOR16mm\0"
1862 /* 4645 */ "BIS16mm\0"
1863 /* 4653 */ "BIT16mm\0"
1864 /* 4661 */ "MOV16mm\0"
1865 /* 4669 */ "SUB8mm\0"
1866 /* 4676 */ "SUBC8mm\0"
1867 /* 4684 */ "ADDC8mm\0"
1868 /* 4692 */ "BIC8mm\0"
1869 /* 4699 */ "DADD8mm\0"
1870 /* 4707 */ "AND8mm\0"
1871 /* 4714 */ "CMP8mm\0"
1872 /* 4721 */ "XOR8mm\0"
1873 /* 4728 */ "BIS8mm\0"
1874 /* 4735 */ "BIT8mm\0"
1875 /* 4742 */ "MOV8mm\0"
1876 /* 4749 */ "SUB16rm\0"
1877 /* 4757 */ "SUBC16rm\0"
1878 /* 4766 */ "ADDC16rm\0"
1879 /* 4775 */ "BIC16rm\0"
1880 /* 4783 */ "DADD16rm\0"
1881 /* 4792 */ "AND16rm\0"
1882 /* 4800 */ "CMP16rm\0"
1883 /* 4808 */ "XOR16rm\0"
1884 /* 4816 */ "BIS16rm\0"
1885 /* 4824 */ "BIT16rm\0"
1886 /* 4832 */ "MOV16rm\0"
1887 /* 4840 */ "SUB8rm\0"
1888 /* 4847 */ "SUBC8rm\0"
1889 /* 4855 */ "ADDC8rm\0"
1890 /* 4863 */ "BIC8rm\0"
1891 /* 4870 */ "DADD8rm\0"
1892 /* 4878 */ "AND8rm\0"
1893 /* 4885 */ "CMP8rm\0"
1894 /* 4892 */ "XOR8rm\0"
1895 /* 4899 */ "BIS8rm\0"
1896 /* 4906 */ "BIT8rm\0"
1897 /* 4913 */ "MOV8rm\0"
1898 /* 4920 */ "RRA16n\0"
1899 /* 4927 */ "SWPB16n\0"
1900 /* 4935 */ "RRC16n\0"
1901 /* 4942 */ "SEXT16n\0"
1902 /* 4950 */ "RRA8n\0"
1903 /* 4956 */ "RRC8n\0"
1904 /* 4962 */ "CALLn\0"
1905 /* 4968 */ "SUB16mn\0"
1906 /* 4976 */ "SUBC16mn\0"
1907 /* 4985 */ "ADDC16mn\0"
1908 /* 4994 */ "BIC16mn\0"
1909 /* 5002 */ "DADD16mn\0"
1910 /* 5011 */ "AND16mn\0"
1911 /* 5019 */ "CMP16mn\0"
1912 /* 5027 */ "XOR16mn\0"
1913 /* 5035 */ "BIS16mn\0"
1914 /* 5043 */ "BIT16mn\0"
1915 /* 5051 */ "MOV16mn\0"
1916 /* 5059 */ "SUB8mn\0"
1917 /* 5066 */ "SUBC8mn\0"
1918 /* 5074 */ "ADDC8mn\0"
1919 /* 5082 */ "BIC8mn\0"
1920 /* 5089 */ "DADD8mn\0"
1921 /* 5097 */ "AND8mn\0"
1922 /* 5104 */ "CMP8mn\0"
1923 /* 5111 */ "XOR8mn\0"
1924 /* 5118 */ "BIS8mn\0"
1925 /* 5125 */ "BIT8mn\0"
1926 /* 5132 */ "MOV8mn\0"
1927 /* 5139 */ "SUB16rn\0"
1928 /* 5147 */ "SUBC16rn\0"
1929 /* 5156 */ "ADDC16rn\0"
1930 /* 5165 */ "BIC16rn\0"
1931 /* 5173 */ "DADD16rn\0"
1932 /* 5182 */ "AND16rn\0"
1933 /* 5190 */ "CMP16rn\0"
1934 /* 5198 */ "XOR16rn\0"
1935 /* 5206 */ "BIS16rn\0"
1936 /* 5214 */ "BIT16rn\0"
1937 /* 5222 */ "MOV16rn\0"
1938 /* 5230 */ "SUB8rn\0"
1939 /* 5237 */ "SUBC8rn\0"
1940 /* 5245 */ "ADDC8rn\0"
1941 /* 5253 */ "BIC8rn\0"
1942 /* 5260 */ "DADD8rn\0"
1943 /* 5268 */ "AND8rn\0"
1944 /* 5275 */ "CMP8rn\0"
1945 /* 5282 */ "XOR8rn\0"
1946 /* 5289 */ "BIS8rn\0"
1947 /* 5296 */ "BIT8rn\0"
1948 /* 5303 */ "MOV8rn\0"
1949 /* 5310 */ "RRA16p\0"
1950 /* 5317 */ "SWPB16p\0"
1951 /* 5325 */ "RRC16p\0"
1952 /* 5332 */ "SEXT16p\0"
1953 /* 5340 */ "RRA8p\0"
1954 /* 5346 */ "RRC8p\0"
1955 /* 5352 */ "CALLp\0"
1956 /* 5358 */ "SUB16mp\0"
1957 /* 5366 */ "SUBC16mp\0"
1958 /* 5375 */ "ADDC16mp\0"
1959 /* 5384 */ "BIC16mp\0"
1960 /* 5392 */ "DADD16mp\0"
1961 /* 5401 */ "AND16mp\0"
1962 /* 5409 */ "CMP16mp\0"
1963 /* 5417 */ "XOR16mp\0"
1964 /* 5425 */ "BIS16mp\0"
1965 /* 5433 */ "BIT16mp\0"
1966 /* 5441 */ "SUB8mp\0"
1967 /* 5448 */ "SUBC8mp\0"
1968 /* 5456 */ "ADDC8mp\0"
1969 /* 5464 */ "BIC8mp\0"
1970 /* 5471 */ "DADD8mp\0"
1971 /* 5479 */ "AND8mp\0"
1972 /* 5486 */ "CMP8mp\0"
1973 /* 5493 */ "XOR8mp\0"
1974 /* 5500 */ "BIS8mp\0"
1975 /* 5507 */ "BIT8mp\0"
1976 /* 5514 */ "SUB16rp\0"
1977 /* 5522 */ "SUBC16rp\0"
1978 /* 5531 */ "ADDC16rp\0"
1979 /* 5540 */ "BIC16rp\0"
1980 /* 5548 */ "DADD16rp\0"
1981 /* 5557 */ "AND16rp\0"
1982 /* 5565 */ "CMP16rp\0"
1983 /* 5573 */ "XOR16rp\0"
1984 /* 5581 */ "BIS16rp\0"
1985 /* 5589 */ "BIT16rp\0"
1986 /* 5597 */ "MOV16rp\0"
1987 /* 5605 */ "SUB8rp\0"
1988 /* 5612 */ "SUBC8rp\0"
1989 /* 5620 */ "ADDC8rp\0"
1990 /* 5628 */ "BIC8rp\0"
1991 /* 5635 */ "DADD8rp\0"
1992 /* 5643 */ "AND8rp\0"
1993 /* 5650 */ "CMP8rp\0"
1994 /* 5657 */ "XOR8rp\0"
1995 /* 5664 */ "BIS8rp\0"
1996 /* 5671 */ "BIT8rp\0"
1997 /* 5678 */ "MOV8rp\0"
1998 /* 5685 */ "RRA16r\0"
1999 /* 5692 */ "SWPB16r\0"
2000 /* 5700 */ "RRC16r\0"
2001 /* 5707 */ "PUSH16r\0"
2002 /* 5715 */ "POP16r\0"
2003 /* 5722 */ "SEXT16r\0"
2004 /* 5730 */ "ZEXT16r\0"
2005 /* 5738 */ "RRA8r\0"
2006 /* 5744 */ "RRC8r\0"
2007 /* 5750 */ "PUSH8r\0"
2008 /* 5757 */ "Br\0"
2009 /* 5760 */ "CALLr\0"
2010 /* 5766 */ "SUB16mr\0"
2011 /* 5774 */ "SUBC16mr\0"
2012 /* 5783 */ "ADDC16mr\0"
2013 /* 5792 */ "BIC16mr\0"
2014 /* 5800 */ "DADD16mr\0"
2015 /* 5809 */ "AND16mr\0"
2016 /* 5817 */ "CMP16mr\0"
2017 /* 5825 */ "XOR16mr\0"
2018 /* 5833 */ "BIS16mr\0"
2019 /* 5841 */ "BIT16mr\0"
2020 /* 5849 */ "MOV16mr\0"
2021 /* 5857 */ "SUB8mr\0"
2022 /* 5864 */ "SUBC8mr\0"
2023 /* 5872 */ "ADDC8mr\0"
2024 /* 5880 */ "BIC8mr\0"
2025 /* 5887 */ "DADD8mr\0"
2026 /* 5895 */ "AND8mr\0"
2027 /* 5902 */ "CMP8mr\0"
2028 /* 5909 */ "XOR8mr\0"
2029 /* 5916 */ "BIS8mr\0"
2030 /* 5923 */ "BIT8mr\0"
2031 /* 5930 */ "MOV8mr\0"
2032 /* 5937 */ "SUB16rr\0"
2033 /* 5945 */ "SUBC16rr\0"
2034 /* 5954 */ "ADDC16rr\0"
2035 /* 5963 */ "BIC16rr\0"
2036 /* 5971 */ "DADD16rr\0"
2037 /* 5980 */ "AND16rr\0"
2038 /* 5988 */ "CMP16rr\0"
2039 /* 5996 */ "XOR16rr\0"
2040 /* 6004 */ "BIS16rr\0"
2041 /* 6012 */ "BIT16rr\0"
2042 /* 6020 */ "MOV16rr\0"
2043 /* 6028 */ "SUB8rr\0"
2044 /* 6035 */ "SUBC8rr\0"
2045 /* 6043 */ "ADDC8rr\0"
2046 /* 6051 */ "BIC8rr\0"
2047 /* 6058 */ "DADD8rr\0"
2048 /* 6066 */ "AND8rr\0"
2049 /* 6073 */ "CMP8rr\0"
2050 /* 6080 */ "XOR8rr\0"
2051 /* 6087 */ "BIS8rr\0"
2052 /* 6094 */ "BIT8rr\0"
2053 /* 6101 */ "MOV8rr\0"
2054};
2055#ifdef __GNUC__
2056#pragma GCC diagnostic pop
2057#endif
2058
2059extern const unsigned MSP430InstrNameIndices[] = {
2060 1282U, 1657U, 2332U, 1945U, 1346U, 1327U, 1355U, 1493U,
2061 1105U, 1120U, 1071U, 1147U, 2797U, 917U, 3422U, 1084U,
2062 1278U, 1336U, 707U, 3768U, 829U, 3326U, 556U, 658U,
2063 695U, 2056U, 1481U, 3236U, 641U, 2267U, 1210U, 3225U,
2064 852U, 2240U, 2227U, 2393U, 3084U, 3107U, 1413U, 1460U,
2065 1433U, 1372U, 2358U, 2010U, 3773U, 2511U, 2198U, 965U,
2066 3452U, 3482U, 1788U, 469U, 176U, 1596U, 3517U, 3524U,
2067 1623U, 1630U, 1637U, 1647U, 534U, 2682U, 2645U, 1069U,
2068 1280U, 3691U, 927U, 942U, 1498U, 3052U, 2733U, 3363U,
2069 2750U, 2582U, 250U, 2780U, 3247U, 2709U, 3395U, 1008U,
2070 2369U, 615U, 224U, 597U, 3285U, 3266U, 1766U, 2418U,
2071 2437U, 370U, 314U, 344U, 355U, 295U, 325U, 896U,
2072 880U, 2827U, 1161U, 1178U, 485U, 182U, 540U, 501U,
2073 2687U, 2651U, 3675U, 1914U, 3658U, 1897U, 436U, 159U,
2074 3593U, 1832U, 2118U, 2096U, 687U, 1227U, 569U, 3071U,
2075 3341U, 202U, 2875U, 3202U, 2902U, 3466U, 242U, 3191U,
2076 3179U, 3316U, 1202U, 3445U, 1134U, 3475U, 1399U, 2504U,
2077 2490U, 1392U, 2497U, 2702U, 1514U, 2173U, 2166U, 2180U,
2078 2187U, 3062U, 2002U, 728U, 1986U, 679U, 1994U, 720U,
2079 1978U, 671U, 2040U, 2032U, 1246U, 1238U, 2970U, 2960U,
2080 2950U, 2940U, 2990U, 2980U, 3719U, 3729U, 3000U, 3013U,
2081 3739U, 3749U, 3026U, 3039U, 394U, 138U, 1538U, 119U,
2082 288U, 3496U, 1602U, 3569U, 1309U, 2311U, 26U, 9U,
2083 1195U, 18U, 0U, 2286U, 2318U, 1098U, 3437U, 214U,
2084 1286U, 1300U, 2148U, 2157U, 2720U, 1803U, 2814U, 1017U,
2085 1731U, 1741U, 777U, 792U, 1688U, 1720U, 3531U, 3557U,
2086 3543U, 736U, 764U, 749U, 475U, 1317U, 1866U, 3627U,
2087 1890U, 3651U, 2727U, 588U, 578U, 2327U, 3131U, 807U,
2088 2563U, 2543U, 3159U, 3138U, 2597U, 2614U, 2857U, 3802U,
2089 1051U, 3795U, 1033U, 2219U, 2140U, 904U, 1405U, 2773U,
2090 1938U, 1759U, 2765U, 1930U, 1751U, 1270U, 1262U, 1254U,
2091 3372U, 2534U, 3258U, 3303U, 3405U, 2345U, 816U, 271U,
2092 986U, 865U, 422U, 145U, 1566U, 3503U, 1609U, 125U,
2093 3380U, 2295U, 2457U, 2473U, 3759U, 836U, 998U, 3098U,
2094 2048U, 2089U, 2065U, 2077U, 401U, 1545U, 377U, 1521U,
2095 3576U, 1815U, 1699U, 1667U, 453U, 1580U, 518U, 2667U,
2096 2629U, 3610U, 1849U, 3634U, 1873U, 3705U, 3712U, 3852U,
2097 4220U, 4613U, 5003U, 5393U, 5801U, 4023U, 4391U, 4784U,
2098 5174U, 5549U, 5972U, 3939U, 4307U, 4700U, 5090U, 5472U,
2099 5888U, 4110U, 4478U, 4871U, 5261U, 5636U, 6059U, 3834U,
2100 4202U, 4595U, 4985U, 5375U, 5783U, 4005U, 4373U, 4766U,
2101 5156U, 5531U, 5954U, 3923U, 4291U, 4684U, 5074U, 5456U,
2102 5872U, 4094U, 4462U, 4855U, 5245U, 5620U, 6043U, 4159U,
2103 1961U, 2252U, 3860U, 4228U, 4621U, 5011U, 5401U, 5809U,
2104 4031U, 4399U, 4792U, 5182U, 5557U, 5980U, 3946U, 4314U,
2105 4707U, 5097U, 5479U, 5895U, 4117U, 4485U, 4878U, 5268U,
2106 5643U, 6066U, 3843U, 4211U, 4604U, 4994U, 5384U, 5792U,
2107 4014U, 4382U, 4775U, 5165U, 5540U, 5963U, 3931U, 4299U,
2108 4692U, 5082U, 5464U, 5880U, 4102U, 4470U, 4863U, 5253U,
2109 5628U, 6051U, 3884U, 4252U, 4645U, 5035U, 5425U, 5833U,
2110 4055U, 4423U, 4816U, 5206U, 5581U, 6004U, 3967U, 4335U,
2111 4728U, 5118U, 5500U, 5916U, 4138U, 4506U, 4899U, 5289U,
2112 5664U, 6087U, 3892U, 4260U, 4653U, 5043U, 5433U, 5841U,
2113 4063U, 4431U, 4824U, 5214U, 5589U, 6012U, 3974U, 4342U,
2114 4735U, 5125U, 5507U, 5923U, 4145U, 4513U, 4906U, 5296U,
2115 5671U, 6094U, 4176U, 4569U, 5757U, 4179U, 4572U, 4962U,
2116 5352U, 5760U, 3868U, 4236U, 4629U, 5019U, 5409U, 5817U,
2117 4039U, 4407U, 4800U, 5190U, 5565U, 5988U, 3953U, 4321U,
2118 4714U, 5104U, 5486U, 5902U, 4124U, 4492U, 4885U, 5275U,
2119 5650U, 6073U, 3851U, 4219U, 4612U, 5002U, 5392U, 5800U,
2120 4022U, 4390U, 4783U, 5173U, 5548U, 5971U, 3938U, 4306U,
2121 4699U, 5089U, 5471U, 5887U, 4109U, 4477U, 4870U, 5260U,
2122 5635U, 6058U, 198U, 2194U, 3900U, 4268U, 4661U, 5051U,
2123 5849U, 4071U, 4439U, 4832U, 5222U, 5597U, 6020U, 3981U,
2124 4349U, 4742U, 5132U, 5930U, 4152U, 4520U, 4913U, 5303U,
2125 5678U, 6101U, 89U, 100U, 5715U, 3809U, 4168U, 5707U,
2126 5750U, 3094U, 1295U, 4527U, 4920U, 5310U, 5685U, 4557U,
2127 4950U, 5340U, 5738U, 4542U, 4935U, 5325U, 5700U, 4563U,
2128 4956U, 5346U, 5744U, 40U, 73U, 4549U, 4942U, 5332U,
2129 5722U, 3817U, 4185U, 4578U, 4968U, 5358U, 5766U, 3988U,
2130 4356U, 4749U, 5139U, 5514U, 5937U, 3908U, 4276U, 4669U,
2131 5059U, 5441U, 5857U, 4079U, 4447U, 4840U, 5230U, 5605U,
2132 6028U, 3825U, 4193U, 4586U, 4976U, 5366U, 5774U, 3996U,
2133 4364U, 4757U, 5147U, 5522U, 5945U, 3915U, 4283U, 4676U,
2134 5066U, 5448U, 5864U, 4086U, 4454U, 4847U, 5237U, 5612U,
2135 6035U, 4534U, 4927U, 5317U, 5692U, 59U, 111U, 47U,
2136 79U, 34U, 68U, 53U, 84U, 3876U, 4244U, 4637U,
2137 5027U, 5417U, 5825U, 4047U, 4415U, 4808U, 5198U, 5573U,
2138 5996U, 3960U, 4328U, 4721U, 5111U, 5493U, 5909U, 4131U,
2139 4499U, 4892U, 5282U, 5657U, 6080U, 5730U,
2140};
2141
2142static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2143 II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 638);
2144}
2145
2146} // end namespace llvm
2147#endif // GET_INSTRINFO_MC_DESC
2148
2149#ifdef GET_INSTRINFO_HEADER
2150#undef GET_INSTRINFO_HEADER
2151namespace llvm {
2152struct MSP430GenInstrInfo : public TargetInstrInfo {
2153 explicit MSP430GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2154 ~MSP430GenInstrInfo() override = default;
2155
2156};
2157} // end namespace llvm
2158#endif // GET_INSTRINFO_HEADER
2159
2160#ifdef GET_INSTRINFO_HELPER_DECLS
2161#undef GET_INSTRINFO_HELPER_DECLS
2162
2163
2164#endif // GET_INSTRINFO_HELPER_DECLS
2165
2166#ifdef GET_INSTRINFO_HELPERS
2167#undef GET_INSTRINFO_HELPERS
2168
2169#endif // GET_INSTRINFO_HELPERS
2170
2171#ifdef GET_INSTRINFO_CTOR_DTOR
2172#undef GET_INSTRINFO_CTOR_DTOR
2173namespace llvm {
2174extern const MSP430InstrTable MSP430Descs;
2175extern const unsigned MSP430InstrNameIndices[];
2176extern const char MSP430InstrNameData[];
2177MSP430GenInstrInfo::MSP430GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2178 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2179 InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 638);
2180}
2181} // end namespace llvm
2182#endif // GET_INSTRINFO_CTOR_DTOR
2183
2184#ifdef GET_INSTRINFO_OPERAND_ENUM
2185#undef GET_INSTRINFO_OPERAND_ENUM
2186namespace llvm {
2187namespace MSP430 {
2188namespace OpName {
2189enum {
2190 OPERAND_LAST
2191};
2192} // end namespace OpName
2193} // end namespace MSP430
2194} // end namespace llvm
2195#endif //GET_INSTRINFO_OPERAND_ENUM
2196
2197#ifdef GET_INSTRINFO_NAMED_OPS
2198#undef GET_INSTRINFO_NAMED_OPS
2199namespace llvm {
2200namespace MSP430 {
2201LLVM_READONLY
2202int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
2203 return -1;
2204}
2205} // end namespace MSP430
2206} // end namespace llvm
2207#endif //GET_INSTRINFO_NAMED_OPS
2208
2209#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
2210#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
2211namespace llvm {
2212namespace MSP430 {
2213namespace OpTypes {
2214enum OperandType {
2215 cc = 0,
2216 cg8imm = 1,
2217 cg16imm = 2,
2218 f32imm = 3,
2219 f64imm = 4,
2220 i1imm = 5,
2221 i8imm = 6,
2222 i16imm = 7,
2223 i32imm = 8,
2224 i64imm = 9,
2225 indreg = 10,
2226 jmptarget = 11,
2227 memdst = 12,
2228 memsrc = 13,
2229 postreg = 14,
2230 ptype0 = 15,
2231 ptype1 = 16,
2232 ptype2 = 17,
2233 ptype3 = 18,
2234 ptype4 = 19,
2235 ptype5 = 20,
2236 type0 = 21,
2237 type1 = 22,
2238 type2 = 23,
2239 type3 = 24,
2240 type4 = 25,
2241 type5 = 26,
2242 untyped_imm_0 = 27,
2243 GR8 = 28,
2244 GR16 = 29,
2245 OPERAND_TYPE_LIST_END
2246};
2247} // end namespace OpTypes
2248} // end namespace MSP430
2249} // end namespace llvm
2250#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2251
2252#ifdef GET_INSTRINFO_OPERAND_TYPE
2253#undef GET_INSTRINFO_OPERAND_TYPE
2254namespace llvm {
2255namespace MSP430 {
2256LLVM_READONLY
2257static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
2258 static const uint16_t Offsets[] = {
2259 /* PHI */
2260 0,
2261 /* INLINEASM */
2262 1,
2263 /* INLINEASM_BR */
2264 1,
2265 /* CFI_INSTRUCTION */
2266 1,
2267 /* EH_LABEL */
2268 2,
2269 /* GC_LABEL */
2270 3,
2271 /* ANNOTATION_LABEL */
2272 4,
2273 /* KILL */
2274 5,
2275 /* EXTRACT_SUBREG */
2276 5,
2277 /* INSERT_SUBREG */
2278 8,
2279 /* IMPLICIT_DEF */
2280 12,
2281 /* SUBREG_TO_REG */
2282 13,
2283 /* COPY_TO_REGCLASS */
2284 17,
2285 /* DBG_VALUE */
2286 20,
2287 /* DBG_VALUE_LIST */
2288 20,
2289 /* DBG_INSTR_REF */
2290 20,
2291 /* DBG_PHI */
2292 20,
2293 /* DBG_LABEL */
2294 20,
2295 /* REG_SEQUENCE */
2296 21,
2297 /* COPY */
2298 23,
2299 /* BUNDLE */
2300 25,
2301 /* LIFETIME_START */
2302 25,
2303 /* LIFETIME_END */
2304 26,
2305 /* PSEUDO_PROBE */
2306 27,
2307 /* ARITH_FENCE */
2308 31,
2309 /* STACKMAP */
2310 33,
2311 /* FENTRY_CALL */
2312 35,
2313 /* PATCHPOINT */
2314 35,
2315 /* LOAD_STACK_GUARD */
2316 41,
2317 /* PREALLOCATED_SETUP */
2318 42,
2319 /* PREALLOCATED_ARG */
2320 43,
2321 /* STATEPOINT */
2322 46,
2323 /* LOCAL_ESCAPE */
2324 46,
2325 /* FAULTING_OP */
2326 48,
2327 /* PATCHABLE_OP */
2328 49,
2329 /* PATCHABLE_FUNCTION_ENTER */
2330 49,
2331 /* PATCHABLE_RET */
2332 49,
2333 /* PATCHABLE_FUNCTION_EXIT */
2334 49,
2335 /* PATCHABLE_TAIL_CALL */
2336 49,
2337 /* PATCHABLE_EVENT_CALL */
2338 49,
2339 /* PATCHABLE_TYPED_EVENT_CALL */
2340 51,
2341 /* ICALL_BRANCH_FUNNEL */
2342 54,
2343 /* MEMBARRIER */
2344 54,
2345 /* JUMP_TABLE_DEBUG_INFO */
2346 54,
2347 /* CONVERGENCECTRL_ENTRY */
2348 55,
2349 /* CONVERGENCECTRL_ANCHOR */
2350 56,
2351 /* CONVERGENCECTRL_LOOP */
2352 57,
2353 /* CONVERGENCECTRL_GLUE */
2354 59,
2355 /* G_ASSERT_SEXT */
2356 60,
2357 /* G_ASSERT_ZEXT */
2358 63,
2359 /* G_ASSERT_ALIGN */
2360 66,
2361 /* G_ADD */
2362 69,
2363 /* G_SUB */
2364 72,
2365 /* G_MUL */
2366 75,
2367 /* G_SDIV */
2368 78,
2369 /* G_UDIV */
2370 81,
2371 /* G_SREM */
2372 84,
2373 /* G_UREM */
2374 87,
2375 /* G_SDIVREM */
2376 90,
2377 /* G_UDIVREM */
2378 94,
2379 /* G_AND */
2380 98,
2381 /* G_OR */
2382 101,
2383 /* G_XOR */
2384 104,
2385 /* G_IMPLICIT_DEF */
2386 107,
2387 /* G_PHI */
2388 108,
2389 /* G_FRAME_INDEX */
2390 109,
2391 /* G_GLOBAL_VALUE */
2392 111,
2393 /* G_PTRAUTH_GLOBAL_VALUE */
2394 113,
2395 /* G_CONSTANT_POOL */
2396 118,
2397 /* G_EXTRACT */
2398 120,
2399 /* G_UNMERGE_VALUES */
2400 123,
2401 /* G_INSERT */
2402 125,
2403 /* G_MERGE_VALUES */
2404 129,
2405 /* G_BUILD_VECTOR */
2406 131,
2407 /* G_BUILD_VECTOR_TRUNC */
2408 133,
2409 /* G_CONCAT_VECTORS */
2410 135,
2411 /* G_PTRTOINT */
2412 137,
2413 /* G_INTTOPTR */
2414 139,
2415 /* G_BITCAST */
2416 141,
2417 /* G_FREEZE */
2418 143,
2419 /* G_CONSTANT_FOLD_BARRIER */
2420 145,
2421 /* G_INTRINSIC_FPTRUNC_ROUND */
2422 147,
2423 /* G_INTRINSIC_TRUNC */
2424 150,
2425 /* G_INTRINSIC_ROUND */
2426 152,
2427 /* G_INTRINSIC_LRINT */
2428 154,
2429 /* G_INTRINSIC_LLRINT */
2430 156,
2431 /* G_INTRINSIC_ROUNDEVEN */
2432 158,
2433 /* G_READCYCLECOUNTER */
2434 160,
2435 /* G_READSTEADYCOUNTER */
2436 161,
2437 /* G_LOAD */
2438 162,
2439 /* G_SEXTLOAD */
2440 164,
2441 /* G_ZEXTLOAD */
2442 166,
2443 /* G_INDEXED_LOAD */
2444 168,
2445 /* G_INDEXED_SEXTLOAD */
2446 173,
2447 /* G_INDEXED_ZEXTLOAD */
2448 178,
2449 /* G_STORE */
2450 183,
2451 /* G_INDEXED_STORE */
2452 185,
2453 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2454 190,
2455 /* G_ATOMIC_CMPXCHG */
2456 195,
2457 /* G_ATOMICRMW_XCHG */
2458 199,
2459 /* G_ATOMICRMW_ADD */
2460 202,
2461 /* G_ATOMICRMW_SUB */
2462 205,
2463 /* G_ATOMICRMW_AND */
2464 208,
2465 /* G_ATOMICRMW_NAND */
2466 211,
2467 /* G_ATOMICRMW_OR */
2468 214,
2469 /* G_ATOMICRMW_XOR */
2470 217,
2471 /* G_ATOMICRMW_MAX */
2472 220,
2473 /* G_ATOMICRMW_MIN */
2474 223,
2475 /* G_ATOMICRMW_UMAX */
2476 226,
2477 /* G_ATOMICRMW_UMIN */
2478 229,
2479 /* G_ATOMICRMW_FADD */
2480 232,
2481 /* G_ATOMICRMW_FSUB */
2482 235,
2483 /* G_ATOMICRMW_FMAX */
2484 238,
2485 /* G_ATOMICRMW_FMIN */
2486 241,
2487 /* G_ATOMICRMW_UINC_WRAP */
2488 244,
2489 /* G_ATOMICRMW_UDEC_WRAP */
2490 247,
2491 /* G_FENCE */
2492 250,
2493 /* G_PREFETCH */
2494 252,
2495 /* G_BRCOND */
2496 256,
2497 /* G_BRINDIRECT */
2498 258,
2499 /* G_INVOKE_REGION_START */
2500 259,
2501 /* G_INTRINSIC */
2502 259,
2503 /* G_INTRINSIC_W_SIDE_EFFECTS */
2504 260,
2505 /* G_INTRINSIC_CONVERGENT */
2506 261,
2507 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2508 262,
2509 /* G_ANYEXT */
2510 263,
2511 /* G_TRUNC */
2512 265,
2513 /* G_CONSTANT */
2514 267,
2515 /* G_FCONSTANT */
2516 269,
2517 /* G_VASTART */
2518 271,
2519 /* G_VAARG */
2520 272,
2521 /* G_SEXT */
2522 275,
2523 /* G_SEXT_INREG */
2524 277,
2525 /* G_ZEXT */
2526 280,
2527 /* G_SHL */
2528 282,
2529 /* G_LSHR */
2530 285,
2531 /* G_ASHR */
2532 288,
2533 /* G_FSHL */
2534 291,
2535 /* G_FSHR */
2536 295,
2537 /* G_ROTR */
2538 299,
2539 /* G_ROTL */
2540 302,
2541 /* G_ICMP */
2542 305,
2543 /* G_FCMP */
2544 309,
2545 /* G_SCMP */
2546 313,
2547 /* G_UCMP */
2548 316,
2549 /* G_SELECT */
2550 319,
2551 /* G_UADDO */
2552 323,
2553 /* G_UADDE */
2554 327,
2555 /* G_USUBO */
2556 332,
2557 /* G_USUBE */
2558 336,
2559 /* G_SADDO */
2560 341,
2561 /* G_SADDE */
2562 345,
2563 /* G_SSUBO */
2564 350,
2565 /* G_SSUBE */
2566 354,
2567 /* G_UMULO */
2568 359,
2569 /* G_SMULO */
2570 363,
2571 /* G_UMULH */
2572 367,
2573 /* G_SMULH */
2574 370,
2575 /* G_UADDSAT */
2576 373,
2577 /* G_SADDSAT */
2578 376,
2579 /* G_USUBSAT */
2580 379,
2581 /* G_SSUBSAT */
2582 382,
2583 /* G_USHLSAT */
2584 385,
2585 /* G_SSHLSAT */
2586 388,
2587 /* G_SMULFIX */
2588 391,
2589 /* G_UMULFIX */
2590 395,
2591 /* G_SMULFIXSAT */
2592 399,
2593 /* G_UMULFIXSAT */
2594 403,
2595 /* G_SDIVFIX */
2596 407,
2597 /* G_UDIVFIX */
2598 411,
2599 /* G_SDIVFIXSAT */
2600 415,
2601 /* G_UDIVFIXSAT */
2602 419,
2603 /* G_FADD */
2604 423,
2605 /* G_FSUB */
2606 426,
2607 /* G_FMUL */
2608 429,
2609 /* G_FMA */
2610 432,
2611 /* G_FMAD */
2612 436,
2613 /* G_FDIV */
2614 440,
2615 /* G_FREM */
2616 443,
2617 /* G_FPOW */
2618 446,
2619 /* G_FPOWI */
2620 449,
2621 /* G_FEXP */
2622 452,
2623 /* G_FEXP2 */
2624 454,
2625 /* G_FEXP10 */
2626 456,
2627 /* G_FLOG */
2628 458,
2629 /* G_FLOG2 */
2630 460,
2631 /* G_FLOG10 */
2632 462,
2633 /* G_FLDEXP */
2634 464,
2635 /* G_FFREXP */
2636 467,
2637 /* G_FNEG */
2638 470,
2639 /* G_FPEXT */
2640 472,
2641 /* G_FPTRUNC */
2642 474,
2643 /* G_FPTOSI */
2644 476,
2645 /* G_FPTOUI */
2646 478,
2647 /* G_SITOFP */
2648 480,
2649 /* G_UITOFP */
2650 482,
2651 /* G_FABS */
2652 484,
2653 /* G_FCOPYSIGN */
2654 486,
2655 /* G_IS_FPCLASS */
2656 489,
2657 /* G_FCANONICALIZE */
2658 492,
2659 /* G_FMINNUM */
2660 494,
2661 /* G_FMAXNUM */
2662 497,
2663 /* G_FMINNUM_IEEE */
2664 500,
2665 /* G_FMAXNUM_IEEE */
2666 503,
2667 /* G_FMINIMUM */
2668 506,
2669 /* G_FMAXIMUM */
2670 509,
2671 /* G_GET_FPENV */
2672 512,
2673 /* G_SET_FPENV */
2674 513,
2675 /* G_RESET_FPENV */
2676 514,
2677 /* G_GET_FPMODE */
2678 514,
2679 /* G_SET_FPMODE */
2680 515,
2681 /* G_RESET_FPMODE */
2682 516,
2683 /* G_PTR_ADD */
2684 516,
2685 /* G_PTRMASK */
2686 519,
2687 /* G_SMIN */
2688 522,
2689 /* G_SMAX */
2690 525,
2691 /* G_UMIN */
2692 528,
2693 /* G_UMAX */
2694 531,
2695 /* G_ABS */
2696 534,
2697 /* G_LROUND */
2698 536,
2699 /* G_LLROUND */
2700 538,
2701 /* G_BR */
2702 540,
2703 /* G_BRJT */
2704 541,
2705 /* G_VSCALE */
2706 544,
2707 /* G_INSERT_SUBVECTOR */
2708 546,
2709 /* G_EXTRACT_SUBVECTOR */
2710 550,
2711 /* G_INSERT_VECTOR_ELT */
2712 553,
2713 /* G_EXTRACT_VECTOR_ELT */
2714 557,
2715 /* G_SHUFFLE_VECTOR */
2716 560,
2717 /* G_SPLAT_VECTOR */
2718 564,
2719 /* G_VECTOR_COMPRESS */
2720 566,
2721 /* G_CTTZ */
2722 570,
2723 /* G_CTTZ_ZERO_UNDEF */
2724 572,
2725 /* G_CTLZ */
2726 574,
2727 /* G_CTLZ_ZERO_UNDEF */
2728 576,
2729 /* G_CTPOP */
2730 578,
2731 /* G_BSWAP */
2732 580,
2733 /* G_BITREVERSE */
2734 582,
2735 /* G_FCEIL */
2736 584,
2737 /* G_FCOS */
2738 586,
2739 /* G_FSIN */
2740 588,
2741 /* G_FTAN */
2742 590,
2743 /* G_FACOS */
2744 592,
2745 /* G_FASIN */
2746 594,
2747 /* G_FATAN */
2748 596,
2749 /* G_FCOSH */
2750 598,
2751 /* G_FSINH */
2752 600,
2753 /* G_FTANH */
2754 602,
2755 /* G_FSQRT */
2756 604,
2757 /* G_FFLOOR */
2758 606,
2759 /* G_FRINT */
2760 608,
2761 /* G_FNEARBYINT */
2762 610,
2763 /* G_ADDRSPACE_CAST */
2764 612,
2765 /* G_BLOCK_ADDR */
2766 614,
2767 /* G_JUMP_TABLE */
2768 616,
2769 /* G_DYN_STACKALLOC */
2770 618,
2771 /* G_STACKSAVE */
2772 621,
2773 /* G_STACKRESTORE */
2774 622,
2775 /* G_STRICT_FADD */
2776 623,
2777 /* G_STRICT_FSUB */
2778 626,
2779 /* G_STRICT_FMUL */
2780 629,
2781 /* G_STRICT_FDIV */
2782 632,
2783 /* G_STRICT_FREM */
2784 635,
2785 /* G_STRICT_FMA */
2786 638,
2787 /* G_STRICT_FSQRT */
2788 642,
2789 /* G_STRICT_FLDEXP */
2790 644,
2791 /* G_READ_REGISTER */
2792 647,
2793 /* G_WRITE_REGISTER */
2794 649,
2795 /* G_MEMCPY */
2796 651,
2797 /* G_MEMCPY_INLINE */
2798 655,
2799 /* G_MEMMOVE */
2800 658,
2801 /* G_MEMSET */
2802 662,
2803 /* G_BZERO */
2804 666,
2805 /* G_TRAP */
2806 669,
2807 /* G_DEBUGTRAP */
2808 669,
2809 /* G_UBSANTRAP */
2810 669,
2811 /* G_VECREDUCE_SEQ_FADD */
2812 670,
2813 /* G_VECREDUCE_SEQ_FMUL */
2814 673,
2815 /* G_VECREDUCE_FADD */
2816 676,
2817 /* G_VECREDUCE_FMUL */
2818 678,
2819 /* G_VECREDUCE_FMAX */
2820 680,
2821 /* G_VECREDUCE_FMIN */
2822 682,
2823 /* G_VECREDUCE_FMAXIMUM */
2824 684,
2825 /* G_VECREDUCE_FMINIMUM */
2826 686,
2827 /* G_VECREDUCE_ADD */
2828 688,
2829 /* G_VECREDUCE_MUL */
2830 690,
2831 /* G_VECREDUCE_AND */
2832 692,
2833 /* G_VECREDUCE_OR */
2834 694,
2835 /* G_VECREDUCE_XOR */
2836 696,
2837 /* G_VECREDUCE_SMAX */
2838 698,
2839 /* G_VECREDUCE_SMIN */
2840 700,
2841 /* G_VECREDUCE_UMAX */
2842 702,
2843 /* G_VECREDUCE_UMIN */
2844 704,
2845 /* G_SBFX */
2846 706,
2847 /* G_UBFX */
2848 710,
2849 /* ADD16mc */
2850 714,
2851 /* ADD16mi */
2852 717,
2853 /* ADD16mm */
2854 720,
2855 /* ADD16mn */
2856 724,
2857 /* ADD16mp */
2858 727,
2859 /* ADD16mr */
2860 730,
2861 /* ADD16rc */
2862 733,
2863 /* ADD16ri */
2864 736,
2865 /* ADD16rm */
2866 739,
2867 /* ADD16rn */
2868 743,
2869 /* ADD16rp */
2870 746,
2871 /* ADD16rr */
2872 750,
2873 /* ADD8mc */
2874 753,
2875 /* ADD8mi */
2876 756,
2877 /* ADD8mm */
2878 759,
2879 /* ADD8mn */
2880 763,
2881 /* ADD8mp */
2882 766,
2883 /* ADD8mr */
2884 769,
2885 /* ADD8rc */
2886 772,
2887 /* ADD8ri */
2888 775,
2889 /* ADD8rm */
2890 778,
2891 /* ADD8rn */
2892 782,
2893 /* ADD8rp */
2894 785,
2895 /* ADD8rr */
2896 789,
2897 /* ADDC16mc */
2898 792,
2899 /* ADDC16mi */
2900 795,
2901 /* ADDC16mm */
2902 798,
2903 /* ADDC16mn */
2904 802,
2905 /* ADDC16mp */
2906 805,
2907 /* ADDC16mr */
2908 808,
2909 /* ADDC16rc */
2910 811,
2911 /* ADDC16ri */
2912 814,
2913 /* ADDC16rm */
2914 817,
2915 /* ADDC16rn */
2916 821,
2917 /* ADDC16rp */
2918 824,
2919 /* ADDC16rr */
2920 828,
2921 /* ADDC8mc */
2922 831,
2923 /* ADDC8mi */
2924 834,
2925 /* ADDC8mm */
2926 837,
2927 /* ADDC8mn */
2928 841,
2929 /* ADDC8mp */
2930 844,
2931 /* ADDC8mr */
2932 847,
2933 /* ADDC8rc */
2934 850,
2935 /* ADDC8ri */
2936 853,
2937 /* ADDC8rm */
2938 856,
2939 /* ADDC8rn */
2940 860,
2941 /* ADDC8rp */
2942 863,
2943 /* ADDC8rr */
2944 867,
2945 /* ADDframe */
2946 870,
2947 /* ADJCALLSTACKDOWN */
2948 873,
2949 /* ADJCALLSTACKUP */
2950 875,
2951 /* AND16mc */
2952 877,
2953 /* AND16mi */
2954 880,
2955 /* AND16mm */
2956 883,
2957 /* AND16mn */
2958 887,
2959 /* AND16mp */
2960 890,
2961 /* AND16mr */
2962 893,
2963 /* AND16rc */
2964 896,
2965 /* AND16ri */
2966 899,
2967 /* AND16rm */
2968 902,
2969 /* AND16rn */
2970 906,
2971 /* AND16rp */
2972 909,
2973 /* AND16rr */
2974 913,
2975 /* AND8mc */
2976 916,
2977 /* AND8mi */
2978 919,
2979 /* AND8mm */
2980 922,
2981 /* AND8mn */
2982 926,
2983 /* AND8mp */
2984 929,
2985 /* AND8mr */
2986 932,
2987 /* AND8rc */
2988 935,
2989 /* AND8ri */
2990 938,
2991 /* AND8rm */
2992 941,
2993 /* AND8rn */
2994 945,
2995 /* AND8rp */
2996 948,
2997 /* AND8rr */
2998 952,
2999 /* BIC16mc */
3000 955,
3001 /* BIC16mi */
3002 958,
3003 /* BIC16mm */
3004 961,
3005 /* BIC16mn */
3006 965,
3007 /* BIC16mp */
3008 968,
3009 /* BIC16mr */
3010 971,
3011 /* BIC16rc */
3012 974,
3013 /* BIC16ri */
3014 977,
3015 /* BIC16rm */
3016 980,
3017 /* BIC16rn */
3018 984,
3019 /* BIC16rp */
3020 987,
3021 /* BIC16rr */
3022 991,
3023 /* BIC8mc */
3024 994,
3025 /* BIC8mi */
3026 997,
3027 /* BIC8mm */
3028 1000,
3029 /* BIC8mn */
3030 1004,
3031 /* BIC8mp */
3032 1007,
3033 /* BIC8mr */
3034 1010,
3035 /* BIC8rc */
3036 1013,
3037 /* BIC8ri */
3038 1016,
3039 /* BIC8rm */
3040 1019,
3041 /* BIC8rn */
3042 1023,
3043 /* BIC8rp */
3044 1026,
3045 /* BIC8rr */
3046 1030,
3047 /* BIS16mc */
3048 1033,
3049 /* BIS16mi */
3050 1036,
3051 /* BIS16mm */
3052 1039,
3053 /* BIS16mn */
3054 1043,
3055 /* BIS16mp */
3056 1046,
3057 /* BIS16mr */
3058 1049,
3059 /* BIS16rc */
3060 1052,
3061 /* BIS16ri */
3062 1055,
3063 /* BIS16rm */
3064 1058,
3065 /* BIS16rn */
3066 1062,
3067 /* BIS16rp */
3068 1065,
3069 /* BIS16rr */
3070 1069,
3071 /* BIS8mc */
3072 1072,
3073 /* BIS8mi */
3074 1075,
3075 /* BIS8mm */
3076 1078,
3077 /* BIS8mn */
3078 1082,
3079 /* BIS8mp */
3080 1085,
3081 /* BIS8mr */
3082 1088,
3083 /* BIS8rc */
3084 1091,
3085 /* BIS8ri */
3086 1094,
3087 /* BIS8rm */
3088 1097,
3089 /* BIS8rn */
3090 1101,
3091 /* BIS8rp */
3092 1104,
3093 /* BIS8rr */
3094 1108,
3095 /* BIT16mc */
3096 1111,
3097 /* BIT16mi */
3098 1114,
3099 /* BIT16mm */
3100 1117,
3101 /* BIT16mn */
3102 1121,
3103 /* BIT16mp */
3104 1124,
3105 /* BIT16mr */
3106 1127,
3107 /* BIT16rc */
3108 1130,
3109 /* BIT16ri */
3110 1132,
3111 /* BIT16rm */
3112 1134,
3113 /* BIT16rn */
3114 1137,
3115 /* BIT16rp */
3116 1139,
3117 /* BIT16rr */
3118 1141,
3119 /* BIT8mc */
3120 1143,
3121 /* BIT8mi */
3122 1146,
3123 /* BIT8mm */
3124 1149,
3125 /* BIT8mn */
3126 1153,
3127 /* BIT8mp */
3128 1156,
3129 /* BIT8mr */
3130 1159,
3131 /* BIT8rc */
3132 1162,
3133 /* BIT8ri */
3134 1164,
3135 /* BIT8rm */
3136 1166,
3137 /* BIT8rn */
3138 1169,
3139 /* BIT8rp */
3140 1171,
3141 /* BIT8rr */
3142 1173,
3143 /* Bi */
3144 1175,
3145 /* Bm */
3146 1176,
3147 /* Br */
3148 1178,
3149 /* CALLi */
3150 1179,
3151 /* CALLm */
3152 1180,
3153 /* CALLn */
3154 1182,
3155 /* CALLp */
3156 1183,
3157 /* CALLr */
3158 1184,
3159 /* CMP16mc */
3160 1185,
3161 /* CMP16mi */
3162 1188,
3163 /* CMP16mm */
3164 1191,
3165 /* CMP16mn */
3166 1195,
3167 /* CMP16mp */
3168 1198,
3169 /* CMP16mr */
3170 1201,
3171 /* CMP16rc */
3172 1204,
3173 /* CMP16ri */
3174 1206,
3175 /* CMP16rm */
3176 1208,
3177 /* CMP16rn */
3178 1211,
3179 /* CMP16rp */
3180 1213,
3181 /* CMP16rr */
3182 1215,
3183 /* CMP8mc */
3184 1217,
3185 /* CMP8mi */
3186 1220,
3187 /* CMP8mm */
3188 1223,
3189 /* CMP8mn */
3190 1227,
3191 /* CMP8mp */
3192 1230,
3193 /* CMP8mr */
3194 1233,
3195 /* CMP8rc */
3196 1236,
3197 /* CMP8ri */
3198 1238,
3199 /* CMP8rm */
3200 1240,
3201 /* CMP8rn */
3202 1243,
3203 /* CMP8rp */
3204 1245,
3205 /* CMP8rr */
3206 1247,
3207 /* DADD16mc */
3208 1249,
3209 /* DADD16mi */
3210 1252,
3211 /* DADD16mm */
3212 1255,
3213 /* DADD16mn */
3214 1259,
3215 /* DADD16mp */
3216 1262,
3217 /* DADD16mr */
3218 1265,
3219 /* DADD16rc */
3220 1268,
3221 /* DADD16ri */
3222 1271,
3223 /* DADD16rm */
3224 1274,
3225 /* DADD16rn */
3226 1278,
3227 /* DADD16rp */
3228 1281,
3229 /* DADD16rr */
3230 1285,
3231 /* DADD8mc */
3232 1288,
3233 /* DADD8mi */
3234 1291,
3235 /* DADD8mm */
3236 1294,
3237 /* DADD8mn */
3238 1298,
3239 /* DADD8mp */
3240 1301,
3241 /* DADD8mr */
3242 1304,
3243 /* DADD8rc */
3244 1307,
3245 /* DADD8ri */
3246 1310,
3247 /* DADD8rm */
3248 1313,
3249 /* DADD8rn */
3250 1317,
3251 /* DADD8rp */
3252 1320,
3253 /* DADD8rr */
3254 1324,
3255 /* JCC */
3256 1327,
3257 /* JMP */
3258 1329,
3259 /* MOV16mc */
3260 1330,
3261 /* MOV16mi */
3262 1333,
3263 /* MOV16mm */
3264 1336,
3265 /* MOV16mn */
3266 1340,
3267 /* MOV16mr */
3268 1343,
3269 /* MOV16rc */
3270 1346,
3271 /* MOV16ri */
3272 1348,
3273 /* MOV16rm */
3274 1350,
3275 /* MOV16rn */
3276 1353,
3277 /* MOV16rp */
3278 1355,
3279 /* MOV16rr */
3280 1358,
3281 /* MOV8mc */
3282 1360,
3283 /* MOV8mi */
3284 1363,
3285 /* MOV8mm */
3286 1366,
3287 /* MOV8mn */
3288 1370,
3289 /* MOV8mr */
3290 1373,
3291 /* MOV8rc */
3292 1376,
3293 /* MOV8ri */
3294 1378,
3295 /* MOV8rm */
3296 1380,
3297 /* MOV8rn */
3298 1383,
3299 /* MOV8rp */
3300 1385,
3301 /* MOV8rr */
3302 1388,
3303 /* MOVZX16rm8 */
3304 1390,
3305 /* MOVZX16rr8 */
3306 1393,
3307 /* POP16r */
3308 1395,
3309 /* PUSH16c */
3310 1396,
3311 /* PUSH16i */
3312 1397,
3313 /* PUSH16r */
3314 1398,
3315 /* PUSH8r */
3316 1399,
3317 /* RET */
3318 1400,
3319 /* RETI */
3320 1400,
3321 /* RRA16m */
3322 1400,
3323 /* RRA16n */
3324 1402,
3325 /* RRA16p */
3326 1403,
3327 /* RRA16r */
3328 1404,
3329 /* RRA8m */
3330 1406,
3331 /* RRA8n */
3332 1408,
3333 /* RRA8p */
3334 1409,
3335 /* RRA8r */
3336 1410,
3337 /* RRC16m */
3338 1412,
3339 /* RRC16n */
3340 1414,
3341 /* RRC16p */
3342 1415,
3343 /* RRC16r */
3344 1416,
3345 /* RRC8m */
3346 1418,
3347 /* RRC8n */
3348 1420,
3349 /* RRC8p */
3350 1421,
3351 /* RRC8r */
3352 1422,
3353 /* Rrcl16 */
3354 1424,
3355 /* Rrcl8 */
3356 1426,
3357 /* SEXT16m */
3358 1428,
3359 /* SEXT16n */
3360 1430,
3361 /* SEXT16p */
3362 1431,
3363 /* SEXT16r */
3364 1432,
3365 /* SUB16mc */
3366 1434,
3367 /* SUB16mi */
3368 1437,
3369 /* SUB16mm */
3370 1440,
3371 /* SUB16mn */
3372 1444,
3373 /* SUB16mp */
3374 1447,
3375 /* SUB16mr */
3376 1450,
3377 /* SUB16rc */
3378 1453,
3379 /* SUB16ri */
3380 1456,
3381 /* SUB16rm */
3382 1459,
3383 /* SUB16rn */
3384 1463,
3385 /* SUB16rp */
3386 1466,
3387 /* SUB16rr */
3388 1470,
3389 /* SUB8mc */
3390 1473,
3391 /* SUB8mi */
3392 1476,
3393 /* SUB8mm */
3394 1479,
3395 /* SUB8mn */
3396 1483,
3397 /* SUB8mp */
3398 1486,
3399 /* SUB8mr */
3400 1489,
3401 /* SUB8rc */
3402 1492,
3403 /* SUB8ri */
3404 1495,
3405 /* SUB8rm */
3406 1498,
3407 /* SUB8rn */
3408 1502,
3409 /* SUB8rp */
3410 1505,
3411 /* SUB8rr */
3412 1509,
3413 /* SUBC16mc */
3414 1512,
3415 /* SUBC16mi */
3416 1515,
3417 /* SUBC16mm */
3418 1518,
3419 /* SUBC16mn */
3420 1522,
3421 /* SUBC16mp */
3422 1525,
3423 /* SUBC16mr */
3424 1528,
3425 /* SUBC16rc */
3426 1531,
3427 /* SUBC16ri */
3428 1534,
3429 /* SUBC16rm */
3430 1537,
3431 /* SUBC16rn */
3432 1541,
3433 /* SUBC16rp */
3434 1544,
3435 /* SUBC16rr */
3436 1548,
3437 /* SUBC8mc */
3438 1551,
3439 /* SUBC8mi */
3440 1554,
3441 /* SUBC8mm */
3442 1557,
3443 /* SUBC8mn */
3444 1561,
3445 /* SUBC8mp */
3446 1564,
3447 /* SUBC8mr */
3448 1567,
3449 /* SUBC8rc */
3450 1570,
3451 /* SUBC8ri */
3452 1573,
3453 /* SUBC8rm */
3454 1576,
3455 /* SUBC8rn */
3456 1580,
3457 /* SUBC8rp */
3458 1583,
3459 /* SUBC8rr */
3460 1587,
3461 /* SWPB16m */
3462 1590,
3463 /* SWPB16n */
3464 1592,
3465 /* SWPB16p */
3466 1593,
3467 /* SWPB16r */
3468 1594,
3469 /* Select16 */
3470 1596,
3471 /* Select8 */
3472 1600,
3473 /* Shl16 */
3474 1604,
3475 /* Shl8 */
3476 1607,
3477 /* Sra16 */
3478 1610,
3479 /* Sra8 */
3480 1613,
3481 /* Srl16 */
3482 1616,
3483 /* Srl8 */
3484 1619,
3485 /* XOR16mc */
3486 1622,
3487 /* XOR16mi */
3488 1625,
3489 /* XOR16mm */
3490 1628,
3491 /* XOR16mn */
3492 1632,
3493 /* XOR16mp */
3494 1635,
3495 /* XOR16mr */
3496 1638,
3497 /* XOR16rc */
3498 1641,
3499 /* XOR16ri */
3500 1644,
3501 /* XOR16rm */
3502 1647,
3503 /* XOR16rn */
3504 1651,
3505 /* XOR16rp */
3506 1654,
3507 /* XOR16rr */
3508 1658,
3509 /* XOR8mc */
3510 1661,
3511 /* XOR8mi */
3512 1664,
3513 /* XOR8mm */
3514 1667,
3515 /* XOR8mn */
3516 1671,
3517 /* XOR8mp */
3518 1674,
3519 /* XOR8mr */
3520 1677,
3521 /* XOR8rc */
3522 1680,
3523 /* XOR8ri */
3524 1683,
3525 /* XOR8rm */
3526 1686,
3527 /* XOR8rn */
3528 1690,
3529 /* XOR8rp */
3530 1693,
3531 /* XOR8rr */
3532 1697,
3533 /* ZEXT16r */
3534 1700,
3535 };
3536
3537 using namespace OpTypes;
3538 static const int8_t OpcodeOperandTypes[] = {
3539
3540 /* PHI */
3541 -1,
3542 /* INLINEASM */
3543 /* INLINEASM_BR */
3544 /* CFI_INSTRUCTION */
3545 i32imm,
3546 /* EH_LABEL */
3547 i32imm,
3548 /* GC_LABEL */
3549 i32imm,
3550 /* ANNOTATION_LABEL */
3551 i32imm,
3552 /* KILL */
3553 /* EXTRACT_SUBREG */
3554 -1, -1, i32imm,
3555 /* INSERT_SUBREG */
3556 -1, -1, -1, i32imm,
3557 /* IMPLICIT_DEF */
3558 -1,
3559 /* SUBREG_TO_REG */
3560 -1, -1, -1, i32imm,
3561 /* COPY_TO_REGCLASS */
3562 -1, -1, i32imm,
3563 /* DBG_VALUE */
3564 /* DBG_VALUE_LIST */
3565 /* DBG_INSTR_REF */
3566 /* DBG_PHI */
3567 /* DBG_LABEL */
3568 -1,
3569 /* REG_SEQUENCE */
3570 -1, -1,
3571 /* COPY */
3572 -1, -1,
3573 /* BUNDLE */
3574 /* LIFETIME_START */
3575 i32imm,
3576 /* LIFETIME_END */
3577 i32imm,
3578 /* PSEUDO_PROBE */
3579 i64imm, i64imm, i8imm, i32imm,
3580 /* ARITH_FENCE */
3581 -1, -1,
3582 /* STACKMAP */
3583 i64imm, i32imm,
3584 /* FENTRY_CALL */
3585 /* PATCHPOINT */
3586 -1, i64imm, i32imm, -1, i32imm, i32imm,
3587 /* LOAD_STACK_GUARD */
3588 -1,
3589 /* PREALLOCATED_SETUP */
3590 i32imm,
3591 /* PREALLOCATED_ARG */
3592 -1, i32imm, i32imm,
3593 /* STATEPOINT */
3594 /* LOCAL_ESCAPE */
3595 -1, i32imm,
3596 /* FAULTING_OP */
3597 -1,
3598 /* PATCHABLE_OP */
3599 /* PATCHABLE_FUNCTION_ENTER */
3600 /* PATCHABLE_RET */
3601 /* PATCHABLE_FUNCTION_EXIT */
3602 /* PATCHABLE_TAIL_CALL */
3603 /* PATCHABLE_EVENT_CALL */
3604 -1, -1,
3605 /* PATCHABLE_TYPED_EVENT_CALL */
3606 -1, -1, -1,
3607 /* ICALL_BRANCH_FUNNEL */
3608 /* MEMBARRIER */
3609 /* JUMP_TABLE_DEBUG_INFO */
3610 i64imm,
3611 /* CONVERGENCECTRL_ENTRY */
3612 -1,
3613 /* CONVERGENCECTRL_ANCHOR */
3614 -1,
3615 /* CONVERGENCECTRL_LOOP */
3616 -1, -1,
3617 /* CONVERGENCECTRL_GLUE */
3618 -1,
3619 /* G_ASSERT_SEXT */
3620 type0, type0, untyped_imm_0,
3621 /* G_ASSERT_ZEXT */
3622 type0, type0, untyped_imm_0,
3623 /* G_ASSERT_ALIGN */
3624 type0, type0, untyped_imm_0,
3625 /* G_ADD */
3626 type0, type0, type0,
3627 /* G_SUB */
3628 type0, type0, type0,
3629 /* G_MUL */
3630 type0, type0, type0,
3631 /* G_SDIV */
3632 type0, type0, type0,
3633 /* G_UDIV */
3634 type0, type0, type0,
3635 /* G_SREM */
3636 type0, type0, type0,
3637 /* G_UREM */
3638 type0, type0, type0,
3639 /* G_SDIVREM */
3640 type0, type0, type0, type0,
3641 /* G_UDIVREM */
3642 type0, type0, type0, type0,
3643 /* G_AND */
3644 type0, type0, type0,
3645 /* G_OR */
3646 type0, type0, type0,
3647 /* G_XOR */
3648 type0, type0, type0,
3649 /* G_IMPLICIT_DEF */
3650 type0,
3651 /* G_PHI */
3652 type0,
3653 /* G_FRAME_INDEX */
3654 type0, -1,
3655 /* G_GLOBAL_VALUE */
3656 type0, -1,
3657 /* G_PTRAUTH_GLOBAL_VALUE */
3658 type0, -1, i32imm, type1, i64imm,
3659 /* G_CONSTANT_POOL */
3660 type0, -1,
3661 /* G_EXTRACT */
3662 type0, type1, untyped_imm_0,
3663 /* G_UNMERGE_VALUES */
3664 type0, type1,
3665 /* G_INSERT */
3666 type0, type0, type1, untyped_imm_0,
3667 /* G_MERGE_VALUES */
3668 type0, type1,
3669 /* G_BUILD_VECTOR */
3670 type0, type1,
3671 /* G_BUILD_VECTOR_TRUNC */
3672 type0, type1,
3673 /* G_CONCAT_VECTORS */
3674 type0, type1,
3675 /* G_PTRTOINT */
3676 type0, type1,
3677 /* G_INTTOPTR */
3678 type0, type1,
3679 /* G_BITCAST */
3680 type0, type1,
3681 /* G_FREEZE */
3682 type0, type0,
3683 /* G_CONSTANT_FOLD_BARRIER */
3684 type0, type0,
3685 /* G_INTRINSIC_FPTRUNC_ROUND */
3686 type0, type1, i32imm,
3687 /* G_INTRINSIC_TRUNC */
3688 type0, type0,
3689 /* G_INTRINSIC_ROUND */
3690 type0, type0,
3691 /* G_INTRINSIC_LRINT */
3692 type0, type1,
3693 /* G_INTRINSIC_LLRINT */
3694 type0, type1,
3695 /* G_INTRINSIC_ROUNDEVEN */
3696 type0, type0,
3697 /* G_READCYCLECOUNTER */
3698 type0,
3699 /* G_READSTEADYCOUNTER */
3700 type0,
3701 /* G_LOAD */
3702 type0, ptype1,
3703 /* G_SEXTLOAD */
3704 type0, ptype1,
3705 /* G_ZEXTLOAD */
3706 type0, ptype1,
3707 /* G_INDEXED_LOAD */
3708 type0, ptype1, ptype1, type2, -1,
3709 /* G_INDEXED_SEXTLOAD */
3710 type0, ptype1, ptype1, type2, -1,
3711 /* G_INDEXED_ZEXTLOAD */
3712 type0, ptype1, ptype1, type2, -1,
3713 /* G_STORE */
3714 type0, ptype1,
3715 /* G_INDEXED_STORE */
3716 ptype0, type1, ptype0, ptype2, -1,
3717 /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
3718 type0, type1, type2, type0, type0,
3719 /* G_ATOMIC_CMPXCHG */
3720 type0, ptype1, type0, type0,
3721 /* G_ATOMICRMW_XCHG */
3722 type0, ptype1, type0,
3723 /* G_ATOMICRMW_ADD */
3724 type0, ptype1, type0,
3725 /* G_ATOMICRMW_SUB */
3726 type0, ptype1, type0,
3727 /* G_ATOMICRMW_AND */
3728 type0, ptype1, type0,
3729 /* G_ATOMICRMW_NAND */
3730 type0, ptype1, type0,
3731 /* G_ATOMICRMW_OR */
3732 type0, ptype1, type0,
3733 /* G_ATOMICRMW_XOR */
3734 type0, ptype1, type0,
3735 /* G_ATOMICRMW_MAX */
3736 type0, ptype1, type0,
3737 /* G_ATOMICRMW_MIN */
3738 type0, ptype1, type0,
3739 /* G_ATOMICRMW_UMAX */
3740 type0, ptype1, type0,
3741 /* G_ATOMICRMW_UMIN */
3742 type0, ptype1, type0,
3743 /* G_ATOMICRMW_FADD */
3744 type0, ptype1, type0,
3745 /* G_ATOMICRMW_FSUB */
3746 type0, ptype1, type0,
3747 /* G_ATOMICRMW_FMAX */
3748 type0, ptype1, type0,
3749 /* G_ATOMICRMW_FMIN */
3750 type0, ptype1, type0,
3751 /* G_ATOMICRMW_UINC_WRAP */
3752 type0, ptype1, type0,
3753 /* G_ATOMICRMW_UDEC_WRAP */
3754 type0, ptype1, type0,
3755 /* G_FENCE */
3756 i32imm, i32imm,
3757 /* G_PREFETCH */
3758 ptype0, i32imm, i32imm, i32imm,
3759 /* G_BRCOND */
3760 type0, -1,
3761 /* G_BRINDIRECT */
3762 type0,
3763 /* G_INVOKE_REGION_START */
3764 /* G_INTRINSIC */
3765 -1,
3766 /* G_INTRINSIC_W_SIDE_EFFECTS */
3767 -1,
3768 /* G_INTRINSIC_CONVERGENT */
3769 -1,
3770 /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
3771 -1,
3772 /* G_ANYEXT */
3773 type0, type1,
3774 /* G_TRUNC */
3775 type0, type1,
3776 /* G_CONSTANT */
3777 type0, -1,
3778 /* G_FCONSTANT */
3779 type0, -1,
3780 /* G_VASTART */
3781 type0,
3782 /* G_VAARG */
3783 type0, type1, -1,
3784 /* G_SEXT */
3785 type0, type1,
3786 /* G_SEXT_INREG */
3787 type0, type0, untyped_imm_0,
3788 /* G_ZEXT */
3789 type0, type1,
3790 /* G_SHL */
3791 type0, type0, type1,
3792 /* G_LSHR */
3793 type0, type0, type1,
3794 /* G_ASHR */
3795 type0, type0, type1,
3796 /* G_FSHL */
3797 type0, type0, type0, type1,
3798 /* G_FSHR */
3799 type0, type0, type0, type1,
3800 /* G_ROTR */
3801 type0, type0, type1,
3802 /* G_ROTL */
3803 type0, type0, type1,
3804 /* G_ICMP */
3805 type0, -1, type1, type1,
3806 /* G_FCMP */
3807 type0, -1, type1, type1,
3808 /* G_SCMP */
3809 type0, type1, type1,
3810 /* G_UCMP */
3811 type0, type1, type1,
3812 /* G_SELECT */
3813 type0, type1, type0, type0,
3814 /* G_UADDO */
3815 type0, type1, type0, type0,
3816 /* G_UADDE */
3817 type0, type1, type0, type0, type1,
3818 /* G_USUBO */
3819 type0, type1, type0, type0,
3820 /* G_USUBE */
3821 type0, type1, type0, type0, type1,
3822 /* G_SADDO */
3823 type0, type1, type0, type0,
3824 /* G_SADDE */
3825 type0, type1, type0, type0, type1,
3826 /* G_SSUBO */
3827 type0, type1, type0, type0,
3828 /* G_SSUBE */
3829 type0, type1, type0, type0, type1,
3830 /* G_UMULO */
3831 type0, type1, type0, type0,
3832 /* G_SMULO */
3833 type0, type1, type0, type0,
3834 /* G_UMULH */
3835 type0, type0, type0,
3836 /* G_SMULH */
3837 type0, type0, type0,
3838 /* G_UADDSAT */
3839 type0, type0, type0,
3840 /* G_SADDSAT */
3841 type0, type0, type0,
3842 /* G_USUBSAT */
3843 type0, type0, type0,
3844 /* G_SSUBSAT */
3845 type0, type0, type0,
3846 /* G_USHLSAT */
3847 type0, type0, type1,
3848 /* G_SSHLSAT */
3849 type0, type0, type1,
3850 /* G_SMULFIX */
3851 type0, type0, type0, untyped_imm_0,
3852 /* G_UMULFIX */
3853 type0, type0, type0, untyped_imm_0,
3854 /* G_SMULFIXSAT */
3855 type0, type0, type0, untyped_imm_0,
3856 /* G_UMULFIXSAT */
3857 type0, type0, type0, untyped_imm_0,
3858 /* G_SDIVFIX */
3859 type0, type0, type0, untyped_imm_0,
3860 /* G_UDIVFIX */
3861 type0, type0, type0, untyped_imm_0,
3862 /* G_SDIVFIXSAT */
3863 type0, type0, type0, untyped_imm_0,
3864 /* G_UDIVFIXSAT */
3865 type0, type0, type0, untyped_imm_0,
3866 /* G_FADD */
3867 type0, type0, type0,
3868 /* G_FSUB */
3869 type0, type0, type0,
3870 /* G_FMUL */
3871 type0, type0, type0,
3872 /* G_FMA */
3873 type0, type0, type0, type0,
3874 /* G_FMAD */
3875 type0, type0, type0, type0,
3876 /* G_FDIV */
3877 type0, type0, type0,
3878 /* G_FREM */
3879 type0, type0, type0,
3880 /* G_FPOW */
3881 type0, type0, type0,
3882 /* G_FPOWI */
3883 type0, type0, type1,
3884 /* G_FEXP */
3885 type0, type0,
3886 /* G_FEXP2 */
3887 type0, type0,
3888 /* G_FEXP10 */
3889 type0, type0,
3890 /* G_FLOG */
3891 type0, type0,
3892 /* G_FLOG2 */
3893 type0, type0,
3894 /* G_FLOG10 */
3895 type0, type0,
3896 /* G_FLDEXP */
3897 type0, type0, type1,
3898 /* G_FFREXP */
3899 type0, type1, type0,
3900 /* G_FNEG */
3901 type0, type0,
3902 /* G_FPEXT */
3903 type0, type1,
3904 /* G_FPTRUNC */
3905 type0, type1,
3906 /* G_FPTOSI */
3907 type0, type1,
3908 /* G_FPTOUI */
3909 type0, type1,
3910 /* G_SITOFP */
3911 type0, type1,
3912 /* G_UITOFP */
3913 type0, type1,
3914 /* G_FABS */
3915 type0, type0,
3916 /* G_FCOPYSIGN */
3917 type0, type0, type1,
3918 /* G_IS_FPCLASS */
3919 type0, type1, -1,
3920 /* G_FCANONICALIZE */
3921 type0, type0,
3922 /* G_FMINNUM */
3923 type0, type0, type0,
3924 /* G_FMAXNUM */
3925 type0, type0, type0,
3926 /* G_FMINNUM_IEEE */
3927 type0, type0, type0,
3928 /* G_FMAXNUM_IEEE */
3929 type0, type0, type0,
3930 /* G_FMINIMUM */
3931 type0, type0, type0,
3932 /* G_FMAXIMUM */
3933 type0, type0, type0,
3934 /* G_GET_FPENV */
3935 type0,
3936 /* G_SET_FPENV */
3937 type0,
3938 /* G_RESET_FPENV */
3939 /* G_GET_FPMODE */
3940 type0,
3941 /* G_SET_FPMODE */
3942 type0,
3943 /* G_RESET_FPMODE */
3944 /* G_PTR_ADD */
3945 ptype0, ptype0, type1,
3946 /* G_PTRMASK */
3947 ptype0, ptype0, type1,
3948 /* G_SMIN */
3949 type0, type0, type0,
3950 /* G_SMAX */
3951 type0, type0, type0,
3952 /* G_UMIN */
3953 type0, type0, type0,
3954 /* G_UMAX */
3955 type0, type0, type0,
3956 /* G_ABS */
3957 type0, type0,
3958 /* G_LROUND */
3959 type0, type1,
3960 /* G_LLROUND */
3961 type0, type1,
3962 /* G_BR */
3963 -1,
3964 /* G_BRJT */
3965 ptype0, -1, type1,
3966 /* G_VSCALE */
3967 type0, -1,
3968 /* G_INSERT_SUBVECTOR */
3969 type0, type0, type1, untyped_imm_0,
3970 /* G_EXTRACT_SUBVECTOR */
3971 type0, type0, untyped_imm_0,
3972 /* G_INSERT_VECTOR_ELT */
3973 type0, type0, type1, type2,
3974 /* G_EXTRACT_VECTOR_ELT */
3975 type0, type1, type2,
3976 /* G_SHUFFLE_VECTOR */
3977 type0, type1, type1, -1,
3978 /* G_SPLAT_VECTOR */
3979 type0, type1,
3980 /* G_VECTOR_COMPRESS */
3981 type0, type0, type1, type0,
3982 /* G_CTTZ */
3983 type0, type1,
3984 /* G_CTTZ_ZERO_UNDEF */
3985 type0, type1,
3986 /* G_CTLZ */
3987 type0, type1,
3988 /* G_CTLZ_ZERO_UNDEF */
3989 type0, type1,
3990 /* G_CTPOP */
3991 type0, type1,
3992 /* G_BSWAP */
3993 type0, type0,
3994 /* G_BITREVERSE */
3995 type0, type0,
3996 /* G_FCEIL */
3997 type0, type0,
3998 /* G_FCOS */
3999 type0, type0,
4000 /* G_FSIN */
4001 type0, type0,
4002 /* G_FTAN */
4003 type0, type0,
4004 /* G_FACOS */
4005 type0, type0,
4006 /* G_FASIN */
4007 type0, type0,
4008 /* G_FATAN */
4009 type0, type0,
4010 /* G_FCOSH */
4011 type0, type0,
4012 /* G_FSINH */
4013 type0, type0,
4014 /* G_FTANH */
4015 type0, type0,
4016 /* G_FSQRT */
4017 type0, type0,
4018 /* G_FFLOOR */
4019 type0, type0,
4020 /* G_FRINT */
4021 type0, type0,
4022 /* G_FNEARBYINT */
4023 type0, type0,
4024 /* G_ADDRSPACE_CAST */
4025 type0, type1,
4026 /* G_BLOCK_ADDR */
4027 type0, -1,
4028 /* G_JUMP_TABLE */
4029 type0, -1,
4030 /* G_DYN_STACKALLOC */
4031 ptype0, type1, i32imm,
4032 /* G_STACKSAVE */
4033 ptype0,
4034 /* G_STACKRESTORE */
4035 ptype0,
4036 /* G_STRICT_FADD */
4037 type0, type0, type0,
4038 /* G_STRICT_FSUB */
4039 type0, type0, type0,
4040 /* G_STRICT_FMUL */
4041 type0, type0, type0,
4042 /* G_STRICT_FDIV */
4043 type0, type0, type0,
4044 /* G_STRICT_FREM */
4045 type0, type0, type0,
4046 /* G_STRICT_FMA */
4047 type0, type0, type0, type0,
4048 /* G_STRICT_FSQRT */
4049 type0, type0,
4050 /* G_STRICT_FLDEXP */
4051 type0, type0, type1,
4052 /* G_READ_REGISTER */
4053 type0, -1,
4054 /* G_WRITE_REGISTER */
4055 -1, type0,
4056 /* G_MEMCPY */
4057 ptype0, ptype1, type2, untyped_imm_0,
4058 /* G_MEMCPY_INLINE */
4059 ptype0, ptype1, type2,
4060 /* G_MEMMOVE */
4061 ptype0, ptype1, type2, untyped_imm_0,
4062 /* G_MEMSET */
4063 ptype0, type1, type2, untyped_imm_0,
4064 /* G_BZERO */
4065 ptype0, type1, untyped_imm_0,
4066 /* G_TRAP */
4067 /* G_DEBUGTRAP */
4068 /* G_UBSANTRAP */
4069 i8imm,
4070 /* G_VECREDUCE_SEQ_FADD */
4071 type0, type1, type2,
4072 /* G_VECREDUCE_SEQ_FMUL */
4073 type0, type1, type2,
4074 /* G_VECREDUCE_FADD */
4075 type0, type1,
4076 /* G_VECREDUCE_FMUL */
4077 type0, type1,
4078 /* G_VECREDUCE_FMAX */
4079 type0, type1,
4080 /* G_VECREDUCE_FMIN */
4081 type0, type1,
4082 /* G_VECREDUCE_FMAXIMUM */
4083 type0, type1,
4084 /* G_VECREDUCE_FMINIMUM */
4085 type0, type1,
4086 /* G_VECREDUCE_ADD */
4087 type0, type1,
4088 /* G_VECREDUCE_MUL */
4089 type0, type1,
4090 /* G_VECREDUCE_AND */
4091 type0, type1,
4092 /* G_VECREDUCE_OR */
4093 type0, type1,
4094 /* G_VECREDUCE_XOR */
4095 type0, type1,
4096 /* G_VECREDUCE_SMAX */
4097 type0, type1,
4098 /* G_VECREDUCE_SMIN */
4099 type0, type1,
4100 /* G_VECREDUCE_UMAX */
4101 type0, type1,
4102 /* G_VECREDUCE_UMIN */
4103 type0, type1,
4104 /* G_SBFX */
4105 type0, type0, type1, type1,
4106 /* G_UBFX */
4107 type0, type0, type1, type1,
4108 /* ADD16mc */
4109 GR16, i16imm, cg16imm,
4110 /* ADD16mi */
4111 GR16, i16imm, i16imm,
4112 /* ADD16mm */
4113 GR16, i16imm, GR16, i16imm,
4114 /* ADD16mn */
4115 GR16, i16imm, GR16,
4116 /* ADD16mp */
4117 GR16, i16imm, GR16,
4118 /* ADD16mr */
4119 GR16, i16imm, GR16,
4120 /* ADD16rc */
4121 GR16, GR16, cg16imm,
4122 /* ADD16ri */
4123 GR16, GR16, i16imm,
4124 /* ADD16rm */
4125 GR16, GR16, GR16, i16imm,
4126 /* ADD16rn */
4127 GR16, GR16, GR16,
4128 /* ADD16rp */
4129 GR16, GR16, GR16, GR16,
4130 /* ADD16rr */
4131 GR16, GR16, GR16,
4132 /* ADD8mc */
4133 GR16, i16imm, cg8imm,
4134 /* ADD8mi */
4135 GR16, i16imm, i8imm,
4136 /* ADD8mm */
4137 GR16, i16imm, GR16, i16imm,
4138 /* ADD8mn */
4139 GR16, i16imm, GR16,
4140 /* ADD8mp */
4141 GR16, i16imm, GR16,
4142 /* ADD8mr */
4143 GR16, i16imm, GR8,
4144 /* ADD8rc */
4145 GR8, GR8, cg8imm,
4146 /* ADD8ri */
4147 GR8, GR8, i8imm,
4148 /* ADD8rm */
4149 GR8, GR8, GR16, i16imm,
4150 /* ADD8rn */
4151 GR8, GR8, GR16,
4152 /* ADD8rp */
4153 GR8, GR16, GR8, GR16,
4154 /* ADD8rr */
4155 GR8, GR8, GR8,
4156 /* ADDC16mc */
4157 GR16, i16imm, cg16imm,
4158 /* ADDC16mi */
4159 GR16, i16imm, i16imm,
4160 /* ADDC16mm */
4161 GR16, i16imm, GR16, i16imm,
4162 /* ADDC16mn */
4163 GR16, i16imm, GR16,
4164 /* ADDC16mp */
4165 GR16, i16imm, GR16,
4166 /* ADDC16mr */
4167 GR16, i16imm, GR16,
4168 /* ADDC16rc */
4169 GR16, GR16, cg16imm,
4170 /* ADDC16ri */
4171 GR16, GR16, i16imm,
4172 /* ADDC16rm */
4173 GR16, GR16, GR16, i16imm,
4174 /* ADDC16rn */
4175 GR16, GR16, GR16,
4176 /* ADDC16rp */
4177 GR16, GR16, GR16, GR16,
4178 /* ADDC16rr */
4179 GR16, GR16, GR16,
4180 /* ADDC8mc */
4181 GR16, i16imm, cg8imm,
4182 /* ADDC8mi */
4183 GR16, i16imm, i8imm,
4184 /* ADDC8mm */
4185 GR16, i16imm, GR16, i16imm,
4186 /* ADDC8mn */
4187 GR16, i16imm, GR16,
4188 /* ADDC8mp */
4189 GR16, i16imm, GR16,
4190 /* ADDC8mr */
4191 GR16, i16imm, GR8,
4192 /* ADDC8rc */
4193 GR8, GR8, cg8imm,
4194 /* ADDC8ri */
4195 GR8, GR8, i8imm,
4196 /* ADDC8rm */
4197 GR8, GR8, GR16, i16imm,
4198 /* ADDC8rn */
4199 GR8, GR8, GR16,
4200 /* ADDC8rp */
4201 GR8, GR16, GR8, GR16,
4202 /* ADDC8rr */
4203 GR8, GR8, GR8,
4204 /* ADDframe */
4205 GR16, i16imm, i16imm,
4206 /* ADJCALLSTACKDOWN */
4207 i16imm, i16imm,
4208 /* ADJCALLSTACKUP */
4209 i16imm, i16imm,
4210 /* AND16mc */
4211 GR16, i16imm, cg16imm,
4212 /* AND16mi */
4213 GR16, i16imm, i16imm,
4214 /* AND16mm */
4215 GR16, i16imm, GR16, i16imm,
4216 /* AND16mn */
4217 GR16, i16imm, GR16,
4218 /* AND16mp */
4219 GR16, i16imm, GR16,
4220 /* AND16mr */
4221 GR16, i16imm, GR16,
4222 /* AND16rc */
4223 GR16, GR16, cg16imm,
4224 /* AND16ri */
4225 GR16, GR16, i16imm,
4226 /* AND16rm */
4227 GR16, GR16, GR16, i16imm,
4228 /* AND16rn */
4229 GR16, GR16, GR16,
4230 /* AND16rp */
4231 GR16, GR16, GR16, GR16,
4232 /* AND16rr */
4233 GR16, GR16, GR16,
4234 /* AND8mc */
4235 GR16, i16imm, cg8imm,
4236 /* AND8mi */
4237 GR16, i16imm, i8imm,
4238 /* AND8mm */
4239 GR16, i16imm, GR16, i16imm,
4240 /* AND8mn */
4241 GR16, i16imm, GR16,
4242 /* AND8mp */
4243 GR16, i16imm, GR16,
4244 /* AND8mr */
4245 GR16, i16imm, GR8,
4246 /* AND8rc */
4247 GR8, GR8, cg8imm,
4248 /* AND8ri */
4249 GR8, GR8, i8imm,
4250 /* AND8rm */
4251 GR8, GR8, GR16, i16imm,
4252 /* AND8rn */
4253 GR8, GR8, GR16,
4254 /* AND8rp */
4255 GR8, GR16, GR8, GR16,
4256 /* AND8rr */
4257 GR8, GR8, GR8,
4258 /* BIC16mc */
4259 GR16, i16imm, cg16imm,
4260 /* BIC16mi */
4261 GR16, i16imm, i16imm,
4262 /* BIC16mm */
4263 GR16, i16imm, GR16, i16imm,
4264 /* BIC16mn */
4265 GR16, i16imm, GR16,
4266 /* BIC16mp */
4267 GR16, i16imm, GR16,
4268 /* BIC16mr */
4269 GR16, i16imm, GR16,
4270 /* BIC16rc */
4271 GR16, GR16, cg16imm,
4272 /* BIC16ri */
4273 GR16, GR16, i16imm,
4274 /* BIC16rm */
4275 GR16, GR16, GR16, i16imm,
4276 /* BIC16rn */
4277 GR16, GR16, GR16,
4278 /* BIC16rp */
4279 GR16, GR16, GR16, GR16,
4280 /* BIC16rr */
4281 GR16, GR16, GR16,
4282 /* BIC8mc */
4283 GR16, i16imm, cg8imm,
4284 /* BIC8mi */
4285 GR16, i16imm, i8imm,
4286 /* BIC8mm */
4287 GR16, i16imm, GR16, i16imm,
4288 /* BIC8mn */
4289 GR16, i16imm, GR16,
4290 /* BIC8mp */
4291 GR16, i16imm, GR16,
4292 /* BIC8mr */
4293 GR16, i16imm, GR8,
4294 /* BIC8rc */
4295 GR8, GR8, cg8imm,
4296 /* BIC8ri */
4297 GR8, GR8, i8imm,
4298 /* BIC8rm */
4299 GR8, GR8, GR16, i16imm,
4300 /* BIC8rn */
4301 GR8, GR8, GR16,
4302 /* BIC8rp */
4303 GR8, GR16, GR8, GR16,
4304 /* BIC8rr */
4305 GR8, GR8, GR8,
4306 /* BIS16mc */
4307 GR16, i16imm, cg16imm,
4308 /* BIS16mi */
4309 GR16, i16imm, i16imm,
4310 /* BIS16mm */
4311 GR16, i16imm, GR16, i16imm,
4312 /* BIS16mn */
4313 GR16, i16imm, GR16,
4314 /* BIS16mp */
4315 GR16, i16imm, GR16,
4316 /* BIS16mr */
4317 GR16, i16imm, GR16,
4318 /* BIS16rc */
4319 GR16, GR16, cg16imm,
4320 /* BIS16ri */
4321 GR16, GR16, i16imm,
4322 /* BIS16rm */
4323 GR16, GR16, GR16, i16imm,
4324 /* BIS16rn */
4325 GR16, GR16, GR16,
4326 /* BIS16rp */
4327 GR16, GR16, GR16, GR16,
4328 /* BIS16rr */
4329 GR16, GR16, GR16,
4330 /* BIS8mc */
4331 GR16, i16imm, cg8imm,
4332 /* BIS8mi */
4333 GR16, i16imm, i8imm,
4334 /* BIS8mm */
4335 GR16, i16imm, GR16, i16imm,
4336 /* BIS8mn */
4337 GR16, i16imm, GR16,
4338 /* BIS8mp */
4339 GR16, i16imm, GR16,
4340 /* BIS8mr */
4341 GR16, i16imm, GR8,
4342 /* BIS8rc */
4343 GR8, GR8, cg8imm,
4344 /* BIS8ri */
4345 GR8, GR8, i8imm,
4346 /* BIS8rm */
4347 GR8, GR8, GR16, i16imm,
4348 /* BIS8rn */
4349 GR8, GR8, GR16,
4350 /* BIS8rp */
4351 GR8, GR16, GR8, GR16,
4352 /* BIS8rr */
4353 GR8, GR8, GR8,
4354 /* BIT16mc */
4355 GR16, i16imm, cg16imm,
4356 /* BIT16mi */
4357 GR16, i16imm, i16imm,
4358 /* BIT16mm */
4359 GR16, i16imm, GR16, i16imm,
4360 /* BIT16mn */
4361 GR16, i16imm, GR16,
4362 /* BIT16mp */
4363 GR16, i16imm, GR16,
4364 /* BIT16mr */
4365 GR16, i16imm, GR16,
4366 /* BIT16rc */
4367 GR16, cg16imm,
4368 /* BIT16ri */
4369 GR16, i16imm,
4370 /* BIT16rm */
4371 GR16, GR16, i16imm,
4372 /* BIT16rn */
4373 GR16, GR16,
4374 /* BIT16rp */
4375 GR16, GR16,
4376 /* BIT16rr */
4377 GR16, GR16,
4378 /* BIT8mc */
4379 GR16, i16imm, cg8imm,
4380 /* BIT8mi */
4381 GR16, i16imm, i8imm,
4382 /* BIT8mm */
4383 GR16, i16imm, GR16, i16imm,
4384 /* BIT8mn */
4385 GR16, i16imm, GR16,
4386 /* BIT8mp */
4387 GR16, i16imm, GR16,
4388 /* BIT8mr */
4389 GR16, i16imm, GR8,
4390 /* BIT8rc */
4391 GR8, cg8imm,
4392 /* BIT8ri */
4393 GR8, i8imm,
4394 /* BIT8rm */
4395 GR8, GR16, i16imm,
4396 /* BIT8rn */
4397 GR8, GR16,
4398 /* BIT8rp */
4399 GR8, GR16,
4400 /* BIT8rr */
4401 GR8, GR8,
4402 /* Bi */
4403 i16imm,
4404 /* Bm */
4405 GR16, i16imm,
4406 /* Br */
4407 GR16,
4408 /* CALLi */
4409 i16imm,
4410 /* CALLm */
4411 GR16, i16imm,
4412 /* CALLn */
4413 GR16,
4414 /* CALLp */
4415 GR16,
4416 /* CALLr */
4417 GR16,
4418 /* CMP16mc */
4419 GR16, i16imm, cg16imm,
4420 /* CMP16mi */
4421 GR16, i16imm, i16imm,
4422 /* CMP16mm */
4423 GR16, i16imm, GR16, i16imm,
4424 /* CMP16mn */
4425 GR16, i16imm, GR16,
4426 /* CMP16mp */
4427 GR16, i16imm, GR16,
4428 /* CMP16mr */
4429 GR16, i16imm, GR16,
4430 /* CMP16rc */
4431 GR16, cg16imm,
4432 /* CMP16ri */
4433 GR16, i16imm,
4434 /* CMP16rm */
4435 GR16, GR16, i16imm,
4436 /* CMP16rn */
4437 GR16, GR16,
4438 /* CMP16rp */
4439 GR16, GR16,
4440 /* CMP16rr */
4441 GR16, GR16,
4442 /* CMP8mc */
4443 GR16, i16imm, cg8imm,
4444 /* CMP8mi */
4445 GR16, i16imm, i8imm,
4446 /* CMP8mm */
4447 GR16, i16imm, GR16, i16imm,
4448 /* CMP8mn */
4449 GR16, i16imm, GR16,
4450 /* CMP8mp */
4451 GR16, i16imm, GR16,
4452 /* CMP8mr */
4453 GR16, i16imm, GR8,
4454 /* CMP8rc */
4455 GR8, cg8imm,
4456 /* CMP8ri */
4457 GR8, i8imm,
4458 /* CMP8rm */
4459 GR8, GR16, i16imm,
4460 /* CMP8rn */
4461 GR8, GR16,
4462 /* CMP8rp */
4463 GR8, GR16,
4464 /* CMP8rr */
4465 GR8, GR8,
4466 /* DADD16mc */
4467 GR16, i16imm, cg16imm,
4468 /* DADD16mi */
4469 GR16, i16imm, i16imm,
4470 /* DADD16mm */
4471 GR16, i16imm, GR16, i16imm,
4472 /* DADD16mn */
4473 GR16, i16imm, GR16,
4474 /* DADD16mp */
4475 GR16, i16imm, GR16,
4476 /* DADD16mr */
4477 GR16, i16imm, GR16,
4478 /* DADD16rc */
4479 GR16, GR16, cg16imm,
4480 /* DADD16ri */
4481 GR16, GR16, i16imm,
4482 /* DADD16rm */
4483 GR16, GR16, GR16, i16imm,
4484 /* DADD16rn */
4485 GR16, GR16, GR16,
4486 /* DADD16rp */
4487 GR16, GR16, GR16, GR16,
4488 /* DADD16rr */
4489 GR16, GR16, GR16,
4490 /* DADD8mc */
4491 GR16, i16imm, cg8imm,
4492 /* DADD8mi */
4493 GR16, i16imm, i8imm,
4494 /* DADD8mm */
4495 GR16, i16imm, GR16, i16imm,
4496 /* DADD8mn */
4497 GR16, i16imm, GR16,
4498 /* DADD8mp */
4499 GR16, i16imm, GR16,
4500 /* DADD8mr */
4501 GR16, i16imm, GR8,
4502 /* DADD8rc */
4503 GR8, GR8, cg8imm,
4504 /* DADD8ri */
4505 GR8, GR8, i8imm,
4506 /* DADD8rm */
4507 GR8, GR8, GR16, i16imm,
4508 /* DADD8rn */
4509 GR8, GR8, GR16,
4510 /* DADD8rp */
4511 GR8, GR16, GR8, GR16,
4512 /* DADD8rr */
4513 GR8, GR8, GR8,
4514 /* JCC */
4515 jmptarget, cc,
4516 /* JMP */
4517 jmptarget,
4518 /* MOV16mc */
4519 GR16, i16imm, cg16imm,
4520 /* MOV16mi */
4521 GR16, i16imm, i16imm,
4522 /* MOV16mm */
4523 GR16, i16imm, GR16, i16imm,
4524 /* MOV16mn */
4525 GR16, i16imm, GR16,
4526 /* MOV16mr */
4527 GR16, i16imm, GR16,
4528 /* MOV16rc */
4529 GR16, cg16imm,
4530 /* MOV16ri */
4531 GR16, i16imm,
4532 /* MOV16rm */
4533 GR16, GR16, i16imm,
4534 /* MOV16rn */
4535 GR16, GR16,
4536 /* MOV16rp */
4537 GR16, GR16, GR16,
4538 /* MOV16rr */
4539 GR16, GR16,
4540 /* MOV8mc */
4541 GR16, i16imm, cg8imm,
4542 /* MOV8mi */
4543 GR16, i16imm, i8imm,
4544 /* MOV8mm */
4545 GR16, i16imm, GR16, i16imm,
4546 /* MOV8mn */
4547 GR16, i16imm, GR16,
4548 /* MOV8mr */
4549 GR16, i16imm, GR8,
4550 /* MOV8rc */
4551 GR8, cg8imm,
4552 /* MOV8ri */
4553 GR8, i8imm,
4554 /* MOV8rm */
4555 GR8, GR16, i16imm,
4556 /* MOV8rn */
4557 GR8, GR16,
4558 /* MOV8rp */
4559 GR8, GR16, GR16,
4560 /* MOV8rr */
4561 GR8, GR8,
4562 /* MOVZX16rm8 */
4563 GR16, GR16, i16imm,
4564 /* MOVZX16rr8 */
4565 GR16, GR8,
4566 /* POP16r */
4567 GR16,
4568 /* PUSH16c */
4569 cg16imm,
4570 /* PUSH16i */
4571 i16imm,
4572 /* PUSH16r */
4573 GR16,
4574 /* PUSH8r */
4575 GR8,
4576 /* RET */
4577 /* RETI */
4578 /* RRA16m */
4579 GR16, i16imm,
4580 /* RRA16n */
4581 GR16,
4582 /* RRA16p */
4583 GR16,
4584 /* RRA16r */
4585 GR16, GR16,
4586 /* RRA8m */
4587 GR16, i16imm,
4588 /* RRA8n */
4589 GR16,
4590 /* RRA8p */
4591 GR16,
4592 /* RRA8r */
4593 GR8, GR8,
4594 /* RRC16m */
4595 GR16, i16imm,
4596 /* RRC16n */
4597 GR16,
4598 /* RRC16p */
4599 GR16,
4600 /* RRC16r */
4601 GR16, GR16,
4602 /* RRC8m */
4603 GR16, i16imm,
4604 /* RRC8n */
4605 GR16,
4606 /* RRC8p */
4607 GR16,
4608 /* RRC8r */
4609 GR8, GR8,
4610 /* Rrcl16 */
4611 GR16, GR16,
4612 /* Rrcl8 */
4613 GR8, GR8,
4614 /* SEXT16m */
4615 GR16, i16imm,
4616 /* SEXT16n */
4617 GR16,
4618 /* SEXT16p */
4619 GR16,
4620 /* SEXT16r */
4621 GR16, GR16,
4622 /* SUB16mc */
4623 GR16, i16imm, cg16imm,
4624 /* SUB16mi */
4625 GR16, i16imm, i16imm,
4626 /* SUB16mm */
4627 GR16, i16imm, GR16, i16imm,
4628 /* SUB16mn */
4629 GR16, i16imm, GR16,
4630 /* SUB16mp */
4631 GR16, i16imm, GR16,
4632 /* SUB16mr */
4633 GR16, i16imm, GR16,
4634 /* SUB16rc */
4635 GR16, GR16, cg16imm,
4636 /* SUB16ri */
4637 GR16, GR16, i16imm,
4638 /* SUB16rm */
4639 GR16, GR16, GR16, i16imm,
4640 /* SUB16rn */
4641 GR16, GR16, GR16,
4642 /* SUB16rp */
4643 GR16, GR16, GR16, GR16,
4644 /* SUB16rr */
4645 GR16, GR16, GR16,
4646 /* SUB8mc */
4647 GR16, i16imm, cg8imm,
4648 /* SUB8mi */
4649 GR16, i16imm, i8imm,
4650 /* SUB8mm */
4651 GR16, i16imm, GR16, i16imm,
4652 /* SUB8mn */
4653 GR16, i16imm, GR16,
4654 /* SUB8mp */
4655 GR16, i16imm, GR16,
4656 /* SUB8mr */
4657 GR16, i16imm, GR8,
4658 /* SUB8rc */
4659 GR8, GR8, cg8imm,
4660 /* SUB8ri */
4661 GR8, GR8, i8imm,
4662 /* SUB8rm */
4663 GR8, GR8, GR16, i16imm,
4664 /* SUB8rn */
4665 GR8, GR8, GR16,
4666 /* SUB8rp */
4667 GR8, GR16, GR8, GR16,
4668 /* SUB8rr */
4669 GR8, GR8, GR8,
4670 /* SUBC16mc */
4671 GR16, i16imm, cg16imm,
4672 /* SUBC16mi */
4673 GR16, i16imm, i16imm,
4674 /* SUBC16mm */
4675 GR16, i16imm, GR16, i16imm,
4676 /* SUBC16mn */
4677 GR16, i16imm, GR16,
4678 /* SUBC16mp */
4679 GR16, i16imm, GR16,
4680 /* SUBC16mr */
4681 GR16, i16imm, GR16,
4682 /* SUBC16rc */
4683 GR16, GR16, cg16imm,
4684 /* SUBC16ri */
4685 GR16, GR16, i16imm,
4686 /* SUBC16rm */
4687 GR16, GR16, GR16, i16imm,
4688 /* SUBC16rn */
4689 GR16, GR16, GR16,
4690 /* SUBC16rp */
4691 GR16, GR16, GR16, GR16,
4692 /* SUBC16rr */
4693 GR16, GR16, GR16,
4694 /* SUBC8mc */
4695 GR16, i16imm, cg8imm,
4696 /* SUBC8mi */
4697 GR16, i16imm, i8imm,
4698 /* SUBC8mm */
4699 GR16, i16imm, GR16, i16imm,
4700 /* SUBC8mn */
4701 GR16, i16imm, GR16,
4702 /* SUBC8mp */
4703 GR16, i16imm, GR16,
4704 /* SUBC8mr */
4705 GR16, i16imm, GR8,
4706 /* SUBC8rc */
4707 GR8, GR8, cg8imm,
4708 /* SUBC8ri */
4709 GR8, GR8, i8imm,
4710 /* SUBC8rm */
4711 GR8, GR8, GR16, i16imm,
4712 /* SUBC8rn */
4713 GR8, GR8, GR16,
4714 /* SUBC8rp */
4715 GR8, GR16, GR8, GR16,
4716 /* SUBC8rr */
4717 GR8, GR8, GR8,
4718 /* SWPB16m */
4719 GR16, i16imm,
4720 /* SWPB16n */
4721 GR16,
4722 /* SWPB16p */
4723 GR16,
4724 /* SWPB16r */
4725 GR16, GR16,
4726 /* Select16 */
4727 GR16, GR16, GR16, i8imm,
4728 /* Select8 */
4729 GR8, GR8, GR8, i8imm,
4730 /* Shl16 */
4731 GR16, GR16, GR8,
4732 /* Shl8 */
4733 GR8, GR8, GR8,
4734 /* Sra16 */
4735 GR16, GR16, GR8,
4736 /* Sra8 */
4737 GR8, GR8, GR8,
4738 /* Srl16 */
4739 GR16, GR16, GR8,
4740 /* Srl8 */
4741 GR8, GR8, GR8,
4742 /* XOR16mc */
4743 GR16, i16imm, cg16imm,
4744 /* XOR16mi */
4745 GR16, i16imm, i16imm,
4746 /* XOR16mm */
4747 GR16, i16imm, GR16, i16imm,
4748 /* XOR16mn */
4749 GR16, i16imm, GR16,
4750 /* XOR16mp */
4751 GR16, i16imm, GR16,
4752 /* XOR16mr */
4753 GR16, i16imm, GR16,
4754 /* XOR16rc */
4755 GR16, GR16, cg16imm,
4756 /* XOR16ri */
4757 GR16, GR16, i16imm,
4758 /* XOR16rm */
4759 GR16, GR16, GR16, i16imm,
4760 /* XOR16rn */
4761 GR16, GR16, GR16,
4762 /* XOR16rp */
4763 GR16, GR16, GR16, GR16,
4764 /* XOR16rr */
4765 GR16, GR16, GR16,
4766 /* XOR8mc */
4767 GR16, i16imm, cg8imm,
4768 /* XOR8mi */
4769 GR16, i16imm, i8imm,
4770 /* XOR8mm */
4771 GR16, i16imm, GR16, i16imm,
4772 /* XOR8mn */
4773 GR16, i16imm, GR16,
4774 /* XOR8mp */
4775 GR16, i16imm, GR16,
4776 /* XOR8mr */
4777 GR16, i16imm, GR8,
4778 /* XOR8rc */
4779 GR8, GR8, cg8imm,
4780 /* XOR8ri */
4781 GR8, GR8, i8imm,
4782 /* XOR8rm */
4783 GR8, GR8, GR16, i16imm,
4784 /* XOR8rn */
4785 GR8, GR8, GR16,
4786 /* XOR8rp */
4787 GR8, GR16, GR8, GR16,
4788 /* XOR8rr */
4789 GR8, GR8, GR8,
4790 /* ZEXT16r */
4791 GR16, GR16,
4792 };
4793 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
4794}
4795} // end namespace MSP430
4796} // end namespace llvm
4797#endif // GET_INSTRINFO_OPERAND_TYPE
4798
4799#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
4800#undef GET_INSTRINFO_MEM_OPERAND_SIZE
4801namespace llvm {
4802namespace MSP430 {
4803LLVM_READONLY
4804static int getMemOperandSize(int OpType) {
4805 switch (OpType) {
4806 default: return 0;
4807 }
4808}
4809} // end namespace MSP430
4810} // end namespace llvm
4811#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
4812
4813#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
4814#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
4815namespace llvm {
4816namespace MSP430 {
4817LLVM_READONLY static unsigned
4818getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
4819 return LogicalOpIdx;
4820}
4821LLVM_READONLY static inline unsigned
4822getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
4823 auto S = 0U;
4824 for (auto i = 0U; i < LogicalOpIdx; ++i)
4825 S += getLogicalOperandSize(Opcode, i);
4826 return S;
4827}
4828} // end namespace MSP430
4829} // end namespace llvm
4830#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
4831
4832#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
4833#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
4834namespace llvm {
4835namespace MSP430 {
4836LLVM_READONLY static int
4837getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
4838 return -1;
4839}
4840} // end namespace MSP430
4841} // end namespace llvm
4842#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
4843
4844#ifdef GET_INSTRINFO_MC_HELPER_DECLS
4845#undef GET_INSTRINFO_MC_HELPER_DECLS
4846
4847namespace llvm {
4848class MCInst;
4849class FeatureBitset;
4850
4851namespace MSP430_MC {
4852
4853void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
4854
4855} // end namespace MSP430_MC
4856} // end namespace llvm
4857
4858#endif // GET_INSTRINFO_MC_HELPER_DECLS
4859
4860#ifdef GET_INSTRINFO_MC_HELPERS
4861#undef GET_INSTRINFO_MC_HELPERS
4862
4863namespace llvm {
4864namespace MSP430_MC {
4865
4866} // end namespace MSP430_MC
4867} // end namespace llvm
4868
4869#endif // GET_GENISTRINFO_MC_HELPERS
4870
4871#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
4872 defined(GET_AVAILABLE_OPCODE_CHECKER)
4873#define GET_COMPUTE_FEATURES
4874#endif
4875#ifdef GET_COMPUTE_FEATURES
4876#undef GET_COMPUTE_FEATURES
4877namespace llvm {
4878namespace MSP430_MC {
4879
4880// Bits for subtarget features that participate in instruction matching.
4881enum SubtargetFeatureBits : uint8_t {
4882};
4883
4884inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
4885 FeatureBitset Features;
4886 return Features;
4887}
4888
4889inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
4890 enum : uint8_t {
4891 CEFBS_None,
4892 };
4893
4894 static constexpr FeatureBitset FeatureBitsets[] = {
4895 {}, // CEFBS_None
4896 };
4897 static constexpr uint8_t RequiredFeaturesRefs[] = {
4898 CEFBS_None, // PHI = 0
4899 CEFBS_None, // INLINEASM = 1
4900 CEFBS_None, // INLINEASM_BR = 2
4901 CEFBS_None, // CFI_INSTRUCTION = 3
4902 CEFBS_None, // EH_LABEL = 4
4903 CEFBS_None, // GC_LABEL = 5
4904 CEFBS_None, // ANNOTATION_LABEL = 6
4905 CEFBS_None, // KILL = 7
4906 CEFBS_None, // EXTRACT_SUBREG = 8
4907 CEFBS_None, // INSERT_SUBREG = 9
4908 CEFBS_None, // IMPLICIT_DEF = 10
4909 CEFBS_None, // SUBREG_TO_REG = 11
4910 CEFBS_None, // COPY_TO_REGCLASS = 12
4911 CEFBS_None, // DBG_VALUE = 13
4912 CEFBS_None, // DBG_VALUE_LIST = 14
4913 CEFBS_None, // DBG_INSTR_REF = 15
4914 CEFBS_None, // DBG_PHI = 16
4915 CEFBS_None, // DBG_LABEL = 17
4916 CEFBS_None, // REG_SEQUENCE = 18
4917 CEFBS_None, // COPY = 19
4918 CEFBS_None, // BUNDLE = 20
4919 CEFBS_None, // LIFETIME_START = 21
4920 CEFBS_None, // LIFETIME_END = 22
4921 CEFBS_None, // PSEUDO_PROBE = 23
4922 CEFBS_None, // ARITH_FENCE = 24
4923 CEFBS_None, // STACKMAP = 25
4924 CEFBS_None, // FENTRY_CALL = 26
4925 CEFBS_None, // PATCHPOINT = 27
4926 CEFBS_None, // LOAD_STACK_GUARD = 28
4927 CEFBS_None, // PREALLOCATED_SETUP = 29
4928 CEFBS_None, // PREALLOCATED_ARG = 30
4929 CEFBS_None, // STATEPOINT = 31
4930 CEFBS_None, // LOCAL_ESCAPE = 32
4931 CEFBS_None, // FAULTING_OP = 33
4932 CEFBS_None, // PATCHABLE_OP = 34
4933 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
4934 CEFBS_None, // PATCHABLE_RET = 36
4935 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
4936 CEFBS_None, // PATCHABLE_TAIL_CALL = 38
4937 CEFBS_None, // PATCHABLE_EVENT_CALL = 39
4938 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
4939 CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
4940 CEFBS_None, // MEMBARRIER = 42
4941 CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
4942 CEFBS_None, // CONVERGENCECTRL_ENTRY = 44
4943 CEFBS_None, // CONVERGENCECTRL_ANCHOR = 45
4944 CEFBS_None, // CONVERGENCECTRL_LOOP = 46
4945 CEFBS_None, // CONVERGENCECTRL_GLUE = 47
4946 CEFBS_None, // G_ASSERT_SEXT = 48
4947 CEFBS_None, // G_ASSERT_ZEXT = 49
4948 CEFBS_None, // G_ASSERT_ALIGN = 50
4949 CEFBS_None, // G_ADD = 51
4950 CEFBS_None, // G_SUB = 52
4951 CEFBS_None, // G_MUL = 53
4952 CEFBS_None, // G_SDIV = 54
4953 CEFBS_None, // G_UDIV = 55
4954 CEFBS_None, // G_SREM = 56
4955 CEFBS_None, // G_UREM = 57
4956 CEFBS_None, // G_SDIVREM = 58
4957 CEFBS_None, // G_UDIVREM = 59
4958 CEFBS_None, // G_AND = 60
4959 CEFBS_None, // G_OR = 61
4960 CEFBS_None, // G_XOR = 62
4961 CEFBS_None, // G_IMPLICIT_DEF = 63
4962 CEFBS_None, // G_PHI = 64
4963 CEFBS_None, // G_FRAME_INDEX = 65
4964 CEFBS_None, // G_GLOBAL_VALUE = 66
4965 CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE = 67
4966 CEFBS_None, // G_CONSTANT_POOL = 68
4967 CEFBS_None, // G_EXTRACT = 69
4968 CEFBS_None, // G_UNMERGE_VALUES = 70
4969 CEFBS_None, // G_INSERT = 71
4970 CEFBS_None, // G_MERGE_VALUES = 72
4971 CEFBS_None, // G_BUILD_VECTOR = 73
4972 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 74
4973 CEFBS_None, // G_CONCAT_VECTORS = 75
4974 CEFBS_None, // G_PTRTOINT = 76
4975 CEFBS_None, // G_INTTOPTR = 77
4976 CEFBS_None, // G_BITCAST = 78
4977 CEFBS_None, // G_FREEZE = 79
4978 CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 80
4979 CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 81
4980 CEFBS_None, // G_INTRINSIC_TRUNC = 82
4981 CEFBS_None, // G_INTRINSIC_ROUND = 83
4982 CEFBS_None, // G_INTRINSIC_LRINT = 84
4983 CEFBS_None, // G_INTRINSIC_LLRINT = 85
4984 CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 86
4985 CEFBS_None, // G_READCYCLECOUNTER = 87
4986 CEFBS_None, // G_READSTEADYCOUNTER = 88
4987 CEFBS_None, // G_LOAD = 89
4988 CEFBS_None, // G_SEXTLOAD = 90
4989 CEFBS_None, // G_ZEXTLOAD = 91
4990 CEFBS_None, // G_INDEXED_LOAD = 92
4991 CEFBS_None, // G_INDEXED_SEXTLOAD = 93
4992 CEFBS_None, // G_INDEXED_ZEXTLOAD = 94
4993 CEFBS_None, // G_STORE = 95
4994 CEFBS_None, // G_INDEXED_STORE = 96
4995 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 97
4996 CEFBS_None, // G_ATOMIC_CMPXCHG = 98
4997 CEFBS_None, // G_ATOMICRMW_XCHG = 99
4998 CEFBS_None, // G_ATOMICRMW_ADD = 100
4999 CEFBS_None, // G_ATOMICRMW_SUB = 101
5000 CEFBS_None, // G_ATOMICRMW_AND = 102
5001 CEFBS_None, // G_ATOMICRMW_NAND = 103
5002 CEFBS_None, // G_ATOMICRMW_OR = 104
5003 CEFBS_None, // G_ATOMICRMW_XOR = 105
5004 CEFBS_None, // G_ATOMICRMW_MAX = 106
5005 CEFBS_None, // G_ATOMICRMW_MIN = 107
5006 CEFBS_None, // G_ATOMICRMW_UMAX = 108
5007 CEFBS_None, // G_ATOMICRMW_UMIN = 109
5008 CEFBS_None, // G_ATOMICRMW_FADD = 110
5009 CEFBS_None, // G_ATOMICRMW_FSUB = 111
5010 CEFBS_None, // G_ATOMICRMW_FMAX = 112
5011 CEFBS_None, // G_ATOMICRMW_FMIN = 113
5012 CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 114
5013 CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 115
5014 CEFBS_None, // G_FENCE = 116
5015 CEFBS_None, // G_PREFETCH = 117
5016 CEFBS_None, // G_BRCOND = 118
5017 CEFBS_None, // G_BRINDIRECT = 119
5018 CEFBS_None, // G_INVOKE_REGION_START = 120
5019 CEFBS_None, // G_INTRINSIC = 121
5020 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 122
5021 CEFBS_None, // G_INTRINSIC_CONVERGENT = 123
5022 CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 124
5023 CEFBS_None, // G_ANYEXT = 125
5024 CEFBS_None, // G_TRUNC = 126
5025 CEFBS_None, // G_CONSTANT = 127
5026 CEFBS_None, // G_FCONSTANT = 128
5027 CEFBS_None, // G_VASTART = 129
5028 CEFBS_None, // G_VAARG = 130
5029 CEFBS_None, // G_SEXT = 131
5030 CEFBS_None, // G_SEXT_INREG = 132
5031 CEFBS_None, // G_ZEXT = 133
5032 CEFBS_None, // G_SHL = 134
5033 CEFBS_None, // G_LSHR = 135
5034 CEFBS_None, // G_ASHR = 136
5035 CEFBS_None, // G_FSHL = 137
5036 CEFBS_None, // G_FSHR = 138
5037 CEFBS_None, // G_ROTR = 139
5038 CEFBS_None, // G_ROTL = 140
5039 CEFBS_None, // G_ICMP = 141
5040 CEFBS_None, // G_FCMP = 142
5041 CEFBS_None, // G_SCMP = 143
5042 CEFBS_None, // G_UCMP = 144
5043 CEFBS_None, // G_SELECT = 145
5044 CEFBS_None, // G_UADDO = 146
5045 CEFBS_None, // G_UADDE = 147
5046 CEFBS_None, // G_USUBO = 148
5047 CEFBS_None, // G_USUBE = 149
5048 CEFBS_None, // G_SADDO = 150
5049 CEFBS_None, // G_SADDE = 151
5050 CEFBS_None, // G_SSUBO = 152
5051 CEFBS_None, // G_SSUBE = 153
5052 CEFBS_None, // G_UMULO = 154
5053 CEFBS_None, // G_SMULO = 155
5054 CEFBS_None, // G_UMULH = 156
5055 CEFBS_None, // G_SMULH = 157
5056 CEFBS_None, // G_UADDSAT = 158
5057 CEFBS_None, // G_SADDSAT = 159
5058 CEFBS_None, // G_USUBSAT = 160
5059 CEFBS_None, // G_SSUBSAT = 161
5060 CEFBS_None, // G_USHLSAT = 162
5061 CEFBS_None, // G_SSHLSAT = 163
5062 CEFBS_None, // G_SMULFIX = 164
5063 CEFBS_None, // G_UMULFIX = 165
5064 CEFBS_None, // G_SMULFIXSAT = 166
5065 CEFBS_None, // G_UMULFIXSAT = 167
5066 CEFBS_None, // G_SDIVFIX = 168
5067 CEFBS_None, // G_UDIVFIX = 169
5068 CEFBS_None, // G_SDIVFIXSAT = 170
5069 CEFBS_None, // G_UDIVFIXSAT = 171
5070 CEFBS_None, // G_FADD = 172
5071 CEFBS_None, // G_FSUB = 173
5072 CEFBS_None, // G_FMUL = 174
5073 CEFBS_None, // G_FMA = 175
5074 CEFBS_None, // G_FMAD = 176
5075 CEFBS_None, // G_FDIV = 177
5076 CEFBS_None, // G_FREM = 178
5077 CEFBS_None, // G_FPOW = 179
5078 CEFBS_None, // G_FPOWI = 180
5079 CEFBS_None, // G_FEXP = 181
5080 CEFBS_None, // G_FEXP2 = 182
5081 CEFBS_None, // G_FEXP10 = 183
5082 CEFBS_None, // G_FLOG = 184
5083 CEFBS_None, // G_FLOG2 = 185
5084 CEFBS_None, // G_FLOG10 = 186
5085 CEFBS_None, // G_FLDEXP = 187
5086 CEFBS_None, // G_FFREXP = 188
5087 CEFBS_None, // G_FNEG = 189
5088 CEFBS_None, // G_FPEXT = 190
5089 CEFBS_None, // G_FPTRUNC = 191
5090 CEFBS_None, // G_FPTOSI = 192
5091 CEFBS_None, // G_FPTOUI = 193
5092 CEFBS_None, // G_SITOFP = 194
5093 CEFBS_None, // G_UITOFP = 195
5094 CEFBS_None, // G_FABS = 196
5095 CEFBS_None, // G_FCOPYSIGN = 197
5096 CEFBS_None, // G_IS_FPCLASS = 198
5097 CEFBS_None, // G_FCANONICALIZE = 199
5098 CEFBS_None, // G_FMINNUM = 200
5099 CEFBS_None, // G_FMAXNUM = 201
5100 CEFBS_None, // G_FMINNUM_IEEE = 202
5101 CEFBS_None, // G_FMAXNUM_IEEE = 203
5102 CEFBS_None, // G_FMINIMUM = 204
5103 CEFBS_None, // G_FMAXIMUM = 205
5104 CEFBS_None, // G_GET_FPENV = 206
5105 CEFBS_None, // G_SET_FPENV = 207
5106 CEFBS_None, // G_RESET_FPENV = 208
5107 CEFBS_None, // G_GET_FPMODE = 209
5108 CEFBS_None, // G_SET_FPMODE = 210
5109 CEFBS_None, // G_RESET_FPMODE = 211
5110 CEFBS_None, // G_PTR_ADD = 212
5111 CEFBS_None, // G_PTRMASK = 213
5112 CEFBS_None, // G_SMIN = 214
5113 CEFBS_None, // G_SMAX = 215
5114 CEFBS_None, // G_UMIN = 216
5115 CEFBS_None, // G_UMAX = 217
5116 CEFBS_None, // G_ABS = 218
5117 CEFBS_None, // G_LROUND = 219
5118 CEFBS_None, // G_LLROUND = 220
5119 CEFBS_None, // G_BR = 221
5120 CEFBS_None, // G_BRJT = 222
5121 CEFBS_None, // G_VSCALE = 223
5122 CEFBS_None, // G_INSERT_SUBVECTOR = 224
5123 CEFBS_None, // G_EXTRACT_SUBVECTOR = 225
5124 CEFBS_None, // G_INSERT_VECTOR_ELT = 226
5125 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 227
5126 CEFBS_None, // G_SHUFFLE_VECTOR = 228
5127 CEFBS_None, // G_SPLAT_VECTOR = 229
5128 CEFBS_None, // G_VECTOR_COMPRESS = 230
5129 CEFBS_None, // G_CTTZ = 231
5130 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 232
5131 CEFBS_None, // G_CTLZ = 233
5132 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 234
5133 CEFBS_None, // G_CTPOP = 235
5134 CEFBS_None, // G_BSWAP = 236
5135 CEFBS_None, // G_BITREVERSE = 237
5136 CEFBS_None, // G_FCEIL = 238
5137 CEFBS_None, // G_FCOS = 239
5138 CEFBS_None, // G_FSIN = 240
5139 CEFBS_None, // G_FTAN = 241
5140 CEFBS_None, // G_FACOS = 242
5141 CEFBS_None, // G_FASIN = 243
5142 CEFBS_None, // G_FATAN = 244
5143 CEFBS_None, // G_FCOSH = 245
5144 CEFBS_None, // G_FSINH = 246
5145 CEFBS_None, // G_FTANH = 247
5146 CEFBS_None, // G_FSQRT = 248
5147 CEFBS_None, // G_FFLOOR = 249
5148 CEFBS_None, // G_FRINT = 250
5149 CEFBS_None, // G_FNEARBYINT = 251
5150 CEFBS_None, // G_ADDRSPACE_CAST = 252
5151 CEFBS_None, // G_BLOCK_ADDR = 253
5152 CEFBS_None, // G_JUMP_TABLE = 254
5153 CEFBS_None, // G_DYN_STACKALLOC = 255
5154 CEFBS_None, // G_STACKSAVE = 256
5155 CEFBS_None, // G_STACKRESTORE = 257
5156 CEFBS_None, // G_STRICT_FADD = 258
5157 CEFBS_None, // G_STRICT_FSUB = 259
5158 CEFBS_None, // G_STRICT_FMUL = 260
5159 CEFBS_None, // G_STRICT_FDIV = 261
5160 CEFBS_None, // G_STRICT_FREM = 262
5161 CEFBS_None, // G_STRICT_FMA = 263
5162 CEFBS_None, // G_STRICT_FSQRT = 264
5163 CEFBS_None, // G_STRICT_FLDEXP = 265
5164 CEFBS_None, // G_READ_REGISTER = 266
5165 CEFBS_None, // G_WRITE_REGISTER = 267
5166 CEFBS_None, // G_MEMCPY = 268
5167 CEFBS_None, // G_MEMCPY_INLINE = 269
5168 CEFBS_None, // G_MEMMOVE = 270
5169 CEFBS_None, // G_MEMSET = 271
5170 CEFBS_None, // G_BZERO = 272
5171 CEFBS_None, // G_TRAP = 273
5172 CEFBS_None, // G_DEBUGTRAP = 274
5173 CEFBS_None, // G_UBSANTRAP = 275
5174 CEFBS_None, // G_VECREDUCE_SEQ_FADD = 276
5175 CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 277
5176 CEFBS_None, // G_VECREDUCE_FADD = 278
5177 CEFBS_None, // G_VECREDUCE_FMUL = 279
5178 CEFBS_None, // G_VECREDUCE_FMAX = 280
5179 CEFBS_None, // G_VECREDUCE_FMIN = 281
5180 CEFBS_None, // G_VECREDUCE_FMAXIMUM = 282
5181 CEFBS_None, // G_VECREDUCE_FMINIMUM = 283
5182 CEFBS_None, // G_VECREDUCE_ADD = 284
5183 CEFBS_None, // G_VECREDUCE_MUL = 285
5184 CEFBS_None, // G_VECREDUCE_AND = 286
5185 CEFBS_None, // G_VECREDUCE_OR = 287
5186 CEFBS_None, // G_VECREDUCE_XOR = 288
5187 CEFBS_None, // G_VECREDUCE_SMAX = 289
5188 CEFBS_None, // G_VECREDUCE_SMIN = 290
5189 CEFBS_None, // G_VECREDUCE_UMAX = 291
5190 CEFBS_None, // G_VECREDUCE_UMIN = 292
5191 CEFBS_None, // G_SBFX = 293
5192 CEFBS_None, // G_UBFX = 294
5193 CEFBS_None, // ADD16mc = 295
5194 CEFBS_None, // ADD16mi = 296
5195 CEFBS_None, // ADD16mm = 297
5196 CEFBS_None, // ADD16mn = 298
5197 CEFBS_None, // ADD16mp = 299
5198 CEFBS_None, // ADD16mr = 300
5199 CEFBS_None, // ADD16rc = 301
5200 CEFBS_None, // ADD16ri = 302
5201 CEFBS_None, // ADD16rm = 303
5202 CEFBS_None, // ADD16rn = 304
5203 CEFBS_None, // ADD16rp = 305
5204 CEFBS_None, // ADD16rr = 306
5205 CEFBS_None, // ADD8mc = 307
5206 CEFBS_None, // ADD8mi = 308
5207 CEFBS_None, // ADD8mm = 309
5208 CEFBS_None, // ADD8mn = 310
5209 CEFBS_None, // ADD8mp = 311
5210 CEFBS_None, // ADD8mr = 312
5211 CEFBS_None, // ADD8rc = 313
5212 CEFBS_None, // ADD8ri = 314
5213 CEFBS_None, // ADD8rm = 315
5214 CEFBS_None, // ADD8rn = 316
5215 CEFBS_None, // ADD8rp = 317
5216 CEFBS_None, // ADD8rr = 318
5217 CEFBS_None, // ADDC16mc = 319
5218 CEFBS_None, // ADDC16mi = 320
5219 CEFBS_None, // ADDC16mm = 321
5220 CEFBS_None, // ADDC16mn = 322
5221 CEFBS_None, // ADDC16mp = 323
5222 CEFBS_None, // ADDC16mr = 324
5223 CEFBS_None, // ADDC16rc = 325
5224 CEFBS_None, // ADDC16ri = 326
5225 CEFBS_None, // ADDC16rm = 327
5226 CEFBS_None, // ADDC16rn = 328
5227 CEFBS_None, // ADDC16rp = 329
5228 CEFBS_None, // ADDC16rr = 330
5229 CEFBS_None, // ADDC8mc = 331
5230 CEFBS_None, // ADDC8mi = 332
5231 CEFBS_None, // ADDC8mm = 333
5232 CEFBS_None, // ADDC8mn = 334
5233 CEFBS_None, // ADDC8mp = 335
5234 CEFBS_None, // ADDC8mr = 336
5235 CEFBS_None, // ADDC8rc = 337
5236 CEFBS_None, // ADDC8ri = 338
5237 CEFBS_None, // ADDC8rm = 339
5238 CEFBS_None, // ADDC8rn = 340
5239 CEFBS_None, // ADDC8rp = 341
5240 CEFBS_None, // ADDC8rr = 342
5241 CEFBS_None, // ADDframe = 343
5242 CEFBS_None, // ADJCALLSTACKDOWN = 344
5243 CEFBS_None, // ADJCALLSTACKUP = 345
5244 CEFBS_None, // AND16mc = 346
5245 CEFBS_None, // AND16mi = 347
5246 CEFBS_None, // AND16mm = 348
5247 CEFBS_None, // AND16mn = 349
5248 CEFBS_None, // AND16mp = 350
5249 CEFBS_None, // AND16mr = 351
5250 CEFBS_None, // AND16rc = 352
5251 CEFBS_None, // AND16ri = 353
5252 CEFBS_None, // AND16rm = 354
5253 CEFBS_None, // AND16rn = 355
5254 CEFBS_None, // AND16rp = 356
5255 CEFBS_None, // AND16rr = 357
5256 CEFBS_None, // AND8mc = 358
5257 CEFBS_None, // AND8mi = 359
5258 CEFBS_None, // AND8mm = 360
5259 CEFBS_None, // AND8mn = 361
5260 CEFBS_None, // AND8mp = 362
5261 CEFBS_None, // AND8mr = 363
5262 CEFBS_None, // AND8rc = 364
5263 CEFBS_None, // AND8ri = 365
5264 CEFBS_None, // AND8rm = 366
5265 CEFBS_None, // AND8rn = 367
5266 CEFBS_None, // AND8rp = 368
5267 CEFBS_None, // AND8rr = 369
5268 CEFBS_None, // BIC16mc = 370
5269 CEFBS_None, // BIC16mi = 371
5270 CEFBS_None, // BIC16mm = 372
5271 CEFBS_None, // BIC16mn = 373
5272 CEFBS_None, // BIC16mp = 374
5273 CEFBS_None, // BIC16mr = 375
5274 CEFBS_None, // BIC16rc = 376
5275 CEFBS_None, // BIC16ri = 377
5276 CEFBS_None, // BIC16rm = 378
5277 CEFBS_None, // BIC16rn = 379
5278 CEFBS_None, // BIC16rp = 380
5279 CEFBS_None, // BIC16rr = 381
5280 CEFBS_None, // BIC8mc = 382
5281 CEFBS_None, // BIC8mi = 383
5282 CEFBS_None, // BIC8mm = 384
5283 CEFBS_None, // BIC8mn = 385
5284 CEFBS_None, // BIC8mp = 386
5285 CEFBS_None, // BIC8mr = 387
5286 CEFBS_None, // BIC8rc = 388
5287 CEFBS_None, // BIC8ri = 389
5288 CEFBS_None, // BIC8rm = 390
5289 CEFBS_None, // BIC8rn = 391
5290 CEFBS_None, // BIC8rp = 392
5291 CEFBS_None, // BIC8rr = 393
5292 CEFBS_None, // BIS16mc = 394
5293 CEFBS_None, // BIS16mi = 395
5294 CEFBS_None, // BIS16mm = 396
5295 CEFBS_None, // BIS16mn = 397
5296 CEFBS_None, // BIS16mp = 398
5297 CEFBS_None, // BIS16mr = 399
5298 CEFBS_None, // BIS16rc = 400
5299 CEFBS_None, // BIS16ri = 401
5300 CEFBS_None, // BIS16rm = 402
5301 CEFBS_None, // BIS16rn = 403
5302 CEFBS_None, // BIS16rp = 404
5303 CEFBS_None, // BIS16rr = 405
5304 CEFBS_None, // BIS8mc = 406
5305 CEFBS_None, // BIS8mi = 407
5306 CEFBS_None, // BIS8mm = 408
5307 CEFBS_None, // BIS8mn = 409
5308 CEFBS_None, // BIS8mp = 410
5309 CEFBS_None, // BIS8mr = 411
5310 CEFBS_None, // BIS8rc = 412
5311 CEFBS_None, // BIS8ri = 413
5312 CEFBS_None, // BIS8rm = 414
5313 CEFBS_None, // BIS8rn = 415
5314 CEFBS_None, // BIS8rp = 416
5315 CEFBS_None, // BIS8rr = 417
5316 CEFBS_None, // BIT16mc = 418
5317 CEFBS_None, // BIT16mi = 419
5318 CEFBS_None, // BIT16mm = 420
5319 CEFBS_None, // BIT16mn = 421
5320 CEFBS_None, // BIT16mp = 422
5321 CEFBS_None, // BIT16mr = 423
5322 CEFBS_None, // BIT16rc = 424
5323 CEFBS_None, // BIT16ri = 425
5324 CEFBS_None, // BIT16rm = 426
5325 CEFBS_None, // BIT16rn = 427
5326 CEFBS_None, // BIT16rp = 428
5327 CEFBS_None, // BIT16rr = 429
5328 CEFBS_None, // BIT8mc = 430
5329 CEFBS_None, // BIT8mi = 431
5330 CEFBS_None, // BIT8mm = 432
5331 CEFBS_None, // BIT8mn = 433
5332 CEFBS_None, // BIT8mp = 434
5333 CEFBS_None, // BIT8mr = 435
5334 CEFBS_None, // BIT8rc = 436
5335 CEFBS_None, // BIT8ri = 437
5336 CEFBS_None, // BIT8rm = 438
5337 CEFBS_None, // BIT8rn = 439
5338 CEFBS_None, // BIT8rp = 440
5339 CEFBS_None, // BIT8rr = 441
5340 CEFBS_None, // Bi = 442
5341 CEFBS_None, // Bm = 443
5342 CEFBS_None, // Br = 444
5343 CEFBS_None, // CALLi = 445
5344 CEFBS_None, // CALLm = 446
5345 CEFBS_None, // CALLn = 447
5346 CEFBS_None, // CALLp = 448
5347 CEFBS_None, // CALLr = 449
5348 CEFBS_None, // CMP16mc = 450
5349 CEFBS_None, // CMP16mi = 451
5350 CEFBS_None, // CMP16mm = 452
5351 CEFBS_None, // CMP16mn = 453
5352 CEFBS_None, // CMP16mp = 454
5353 CEFBS_None, // CMP16mr = 455
5354 CEFBS_None, // CMP16rc = 456
5355 CEFBS_None, // CMP16ri = 457
5356 CEFBS_None, // CMP16rm = 458
5357 CEFBS_None, // CMP16rn = 459
5358 CEFBS_None, // CMP16rp = 460
5359 CEFBS_None, // CMP16rr = 461
5360 CEFBS_None, // CMP8mc = 462
5361 CEFBS_None, // CMP8mi = 463
5362 CEFBS_None, // CMP8mm = 464
5363 CEFBS_None, // CMP8mn = 465
5364 CEFBS_None, // CMP8mp = 466
5365 CEFBS_None, // CMP8mr = 467
5366 CEFBS_None, // CMP8rc = 468
5367 CEFBS_None, // CMP8ri = 469
5368 CEFBS_None, // CMP8rm = 470
5369 CEFBS_None, // CMP8rn = 471
5370 CEFBS_None, // CMP8rp = 472
5371 CEFBS_None, // CMP8rr = 473
5372 CEFBS_None, // DADD16mc = 474
5373 CEFBS_None, // DADD16mi = 475
5374 CEFBS_None, // DADD16mm = 476
5375 CEFBS_None, // DADD16mn = 477
5376 CEFBS_None, // DADD16mp = 478
5377 CEFBS_None, // DADD16mr = 479
5378 CEFBS_None, // DADD16rc = 480
5379 CEFBS_None, // DADD16ri = 481
5380 CEFBS_None, // DADD16rm = 482
5381 CEFBS_None, // DADD16rn = 483
5382 CEFBS_None, // DADD16rp = 484
5383 CEFBS_None, // DADD16rr = 485
5384 CEFBS_None, // DADD8mc = 486
5385 CEFBS_None, // DADD8mi = 487
5386 CEFBS_None, // DADD8mm = 488
5387 CEFBS_None, // DADD8mn = 489
5388 CEFBS_None, // DADD8mp = 490
5389 CEFBS_None, // DADD8mr = 491
5390 CEFBS_None, // DADD8rc = 492
5391 CEFBS_None, // DADD8ri = 493
5392 CEFBS_None, // DADD8rm = 494
5393 CEFBS_None, // DADD8rn = 495
5394 CEFBS_None, // DADD8rp = 496
5395 CEFBS_None, // DADD8rr = 497
5396 CEFBS_None, // JCC = 498
5397 CEFBS_None, // JMP = 499
5398 CEFBS_None, // MOV16mc = 500
5399 CEFBS_None, // MOV16mi = 501
5400 CEFBS_None, // MOV16mm = 502
5401 CEFBS_None, // MOV16mn = 503
5402 CEFBS_None, // MOV16mr = 504
5403 CEFBS_None, // MOV16rc = 505
5404 CEFBS_None, // MOV16ri = 506
5405 CEFBS_None, // MOV16rm = 507
5406 CEFBS_None, // MOV16rn = 508
5407 CEFBS_None, // MOV16rp = 509
5408 CEFBS_None, // MOV16rr = 510
5409 CEFBS_None, // MOV8mc = 511
5410 CEFBS_None, // MOV8mi = 512
5411 CEFBS_None, // MOV8mm = 513
5412 CEFBS_None, // MOV8mn = 514
5413 CEFBS_None, // MOV8mr = 515
5414 CEFBS_None, // MOV8rc = 516
5415 CEFBS_None, // MOV8ri = 517
5416 CEFBS_None, // MOV8rm = 518
5417 CEFBS_None, // MOV8rn = 519
5418 CEFBS_None, // MOV8rp = 520
5419 CEFBS_None, // MOV8rr = 521
5420 CEFBS_None, // MOVZX16rm8 = 522
5421 CEFBS_None, // MOVZX16rr8 = 523
5422 CEFBS_None, // POP16r = 524
5423 CEFBS_None, // PUSH16c = 525
5424 CEFBS_None, // PUSH16i = 526
5425 CEFBS_None, // PUSH16r = 527
5426 CEFBS_None, // PUSH8r = 528
5427 CEFBS_None, // RET = 529
5428 CEFBS_None, // RETI = 530
5429 CEFBS_None, // RRA16m = 531
5430 CEFBS_None, // RRA16n = 532
5431 CEFBS_None, // RRA16p = 533
5432 CEFBS_None, // RRA16r = 534
5433 CEFBS_None, // RRA8m = 535
5434 CEFBS_None, // RRA8n = 536
5435 CEFBS_None, // RRA8p = 537
5436 CEFBS_None, // RRA8r = 538
5437 CEFBS_None, // RRC16m = 539
5438 CEFBS_None, // RRC16n = 540
5439 CEFBS_None, // RRC16p = 541
5440 CEFBS_None, // RRC16r = 542
5441 CEFBS_None, // RRC8m = 543
5442 CEFBS_None, // RRC8n = 544
5443 CEFBS_None, // RRC8p = 545
5444 CEFBS_None, // RRC8r = 546
5445 CEFBS_None, // Rrcl16 = 547
5446 CEFBS_None, // Rrcl8 = 548
5447 CEFBS_None, // SEXT16m = 549
5448 CEFBS_None, // SEXT16n = 550
5449 CEFBS_None, // SEXT16p = 551
5450 CEFBS_None, // SEXT16r = 552
5451 CEFBS_None, // SUB16mc = 553
5452 CEFBS_None, // SUB16mi = 554
5453 CEFBS_None, // SUB16mm = 555
5454 CEFBS_None, // SUB16mn = 556
5455 CEFBS_None, // SUB16mp = 557
5456 CEFBS_None, // SUB16mr = 558
5457 CEFBS_None, // SUB16rc = 559
5458 CEFBS_None, // SUB16ri = 560
5459 CEFBS_None, // SUB16rm = 561
5460 CEFBS_None, // SUB16rn = 562
5461 CEFBS_None, // SUB16rp = 563
5462 CEFBS_None, // SUB16rr = 564
5463 CEFBS_None, // SUB8mc = 565
5464 CEFBS_None, // SUB8mi = 566
5465 CEFBS_None, // SUB8mm = 567
5466 CEFBS_None, // SUB8mn = 568
5467 CEFBS_None, // SUB8mp = 569
5468 CEFBS_None, // SUB8mr = 570
5469 CEFBS_None, // SUB8rc = 571
5470 CEFBS_None, // SUB8ri = 572
5471 CEFBS_None, // SUB8rm = 573
5472 CEFBS_None, // SUB8rn = 574
5473 CEFBS_None, // SUB8rp = 575
5474 CEFBS_None, // SUB8rr = 576
5475 CEFBS_None, // SUBC16mc = 577
5476 CEFBS_None, // SUBC16mi = 578
5477 CEFBS_None, // SUBC16mm = 579
5478 CEFBS_None, // SUBC16mn = 580
5479 CEFBS_None, // SUBC16mp = 581
5480 CEFBS_None, // SUBC16mr = 582
5481 CEFBS_None, // SUBC16rc = 583
5482 CEFBS_None, // SUBC16ri = 584
5483 CEFBS_None, // SUBC16rm = 585
5484 CEFBS_None, // SUBC16rn = 586
5485 CEFBS_None, // SUBC16rp = 587
5486 CEFBS_None, // SUBC16rr = 588
5487 CEFBS_None, // SUBC8mc = 589
5488 CEFBS_None, // SUBC8mi = 590
5489 CEFBS_None, // SUBC8mm = 591
5490 CEFBS_None, // SUBC8mn = 592
5491 CEFBS_None, // SUBC8mp = 593
5492 CEFBS_None, // SUBC8mr = 594
5493 CEFBS_None, // SUBC8rc = 595
5494 CEFBS_None, // SUBC8ri = 596
5495 CEFBS_None, // SUBC8rm = 597
5496 CEFBS_None, // SUBC8rn = 598
5497 CEFBS_None, // SUBC8rp = 599
5498 CEFBS_None, // SUBC8rr = 600
5499 CEFBS_None, // SWPB16m = 601
5500 CEFBS_None, // SWPB16n = 602
5501 CEFBS_None, // SWPB16p = 603
5502 CEFBS_None, // SWPB16r = 604
5503 CEFBS_None, // Select16 = 605
5504 CEFBS_None, // Select8 = 606
5505 CEFBS_None, // Shl16 = 607
5506 CEFBS_None, // Shl8 = 608
5507 CEFBS_None, // Sra16 = 609
5508 CEFBS_None, // Sra8 = 610
5509 CEFBS_None, // Srl16 = 611
5510 CEFBS_None, // Srl8 = 612
5511 CEFBS_None, // XOR16mc = 613
5512 CEFBS_None, // XOR16mi = 614
5513 CEFBS_None, // XOR16mm = 615
5514 CEFBS_None, // XOR16mn = 616
5515 CEFBS_None, // XOR16mp = 617
5516 CEFBS_None, // XOR16mr = 618
5517 CEFBS_None, // XOR16rc = 619
5518 CEFBS_None, // XOR16ri = 620
5519 CEFBS_None, // XOR16rm = 621
5520 CEFBS_None, // XOR16rn = 622
5521 CEFBS_None, // XOR16rp = 623
5522 CEFBS_None, // XOR16rr = 624
5523 CEFBS_None, // XOR8mc = 625
5524 CEFBS_None, // XOR8mi = 626
5525 CEFBS_None, // XOR8mm = 627
5526 CEFBS_None, // XOR8mn = 628
5527 CEFBS_None, // XOR8mp = 629
5528 CEFBS_None, // XOR8mr = 630
5529 CEFBS_None, // XOR8rc = 631
5530 CEFBS_None, // XOR8ri = 632
5531 CEFBS_None, // XOR8rm = 633
5532 CEFBS_None, // XOR8rn = 634
5533 CEFBS_None, // XOR8rp = 635
5534 CEFBS_None, // XOR8rr = 636
5535 CEFBS_None, // ZEXT16r = 637
5536 };
5537
5538 assert(Opcode < 638);
5539 return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
5540}
5541
5542} // end namespace MSP430_MC
5543} // end namespace llvm
5544#endif // GET_COMPUTE_FEATURES
5545
5546#ifdef GET_AVAILABLE_OPCODE_CHECKER
5547#undef GET_AVAILABLE_OPCODE_CHECKER
5548namespace llvm {
5549namespace MSP430_MC {
5550bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
5551 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
5552 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
5553 FeatureBitset MissingFeatures =
5554 (AvailableFeatures & RequiredFeatures) ^
5555 RequiredFeatures;
5556 return !MissingFeatures.any();
5557}
5558} // end namespace MSP430_MC
5559} // end namespace llvm
5560#endif // GET_AVAILABLE_OPCODE_CHECKER
5561
5562#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
5563#undef ENABLE_INSTR_PREDICATE_VERIFIER
5564#include <sstream>
5565
5566namespace llvm {
5567namespace MSP430_MC {
5568
5569#ifndef NDEBUG
5570static const char *SubtargetFeatureNames[] = {
5571 nullptr
5572};
5573
5574#endif // NDEBUG
5575
5576void verifyInstructionPredicates(
5577 unsigned Opcode, const FeatureBitset &Features) {
5578#ifndef NDEBUG
5579 FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
5580 FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
5581 FeatureBitset MissingFeatures =
5582 (AvailableFeatures & RequiredFeatures) ^
5583 RequiredFeatures;
5584 if (MissingFeatures.any()) {
5585 std::ostringstream Msg;
5586 Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
5587 << " instruction but the ";
5588 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
5589 if (MissingFeatures.test(i))
5590 Msg << SubtargetFeatureNames[i] << " ";
5591 Msg << "predicate(s) are not met";
5592 report_fatal_error(Msg.str().c_str());
5593 }
5594#endif // NDEBUG
5595}
5596} // end namespace MSP430_MC
5597} // end namespace llvm
5598#endif // ENABLE_INSTR_PREDICATE_VERIFIER
5599
5600