1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Target Register Enum Values *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_REGINFO_ENUM
11#undef GET_REGINFO_ENUM
12
13namespace llvm {
14
15class MCRegisterClass;
16extern const MCRegisterClass MSP430MCRegisterClasses[];
17
18namespace MSP430 {
19enum {
20 NoRegister,
21 CG = 1,
22 CGB = 2,
23 PC = 3,
24 PCB = 4,
25 SP = 5,
26 SPB = 6,
27 SR = 7,
28 SRB = 8,
29 R4 = 9,
30 R5 = 10,
31 R6 = 11,
32 R7 = 12,
33 R8 = 13,
34 R9 = 14,
35 R10 = 15,
36 R11 = 16,
37 R12 = 17,
38 R13 = 18,
39 R14 = 19,
40 R15 = 20,
41 R4B = 21,
42 R5B = 22,
43 R6B = 23,
44 R7B = 24,
45 R8B = 25,
46 R9B = 26,
47 R10B = 27,
48 R11B = 28,
49 R12B = 29,
50 R13B = 30,
51 R14B = 31,
52 R15B = 32,
53 NUM_TARGET_REGS // 33
54};
55} // end namespace MSP430
56
57// Register classes
58
59namespace MSP430 {
60enum {
61 GR8RegClassID = 0,
62 GR16RegClassID = 1,
63
64};
65} // end namespace MSP430
66
67
68// Subregister indices
69
70namespace MSP430 {
71enum : uint16_t {
72 NoSubRegister,
73 subreg_8bit, // 1
74 NUM_TARGET_SUBREGS
75};
76} // end namespace MSP430
77
78// Register pressure sets enum.
79namespace MSP430 {
80enum RegisterPressureSets {
81 GR8 = 0,
82};
83} // end namespace MSP430
84
85} // end namespace llvm
86
87#endif // GET_REGINFO_ENUM
88
89/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
90|* *|
91|* MC Register Information *|
92|* *|
93|* Automatically generated file, do not edit! *|
94|* *|
95\*===----------------------------------------------------------------------===*/
96
97
98#ifdef GET_REGINFO_MC_DESC
99#undef GET_REGINFO_MC_DESC
100
101namespace llvm {
102
103extern const int16_t MSP430RegDiffLists[] = {
104 /* 0 */ -12, 0,
105 /* 2 */ -1, 0,
106 /* 4 */ 1, 0,
107 /* 6 */ 12, 0,
108};
109
110extern const LaneBitmask MSP430LaneMaskLists[] = {
111 /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
112 /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
113};
114
115extern const uint16_t MSP430SubRegIdxLists[] = {
116 /* 0 */ 1, 0,
117};
118
119
120#ifdef __GNUC__
121#pragma GCC diagnostic push
122#pragma GCC diagnostic ignored "-Woverlength-strings"
123#endif
124extern const char MSP430RegStrings[] = {
125 /* 0 */ "R10\0"
126 /* 4 */ "R11\0"
127 /* 8 */ "R12\0"
128 /* 12 */ "R13\0"
129 /* 16 */ "R14\0"
130 /* 20 */ "R4\0"
131 /* 23 */ "R15\0"
132 /* 27 */ "R5\0"
133 /* 30 */ "R6\0"
134 /* 33 */ "R7\0"
135 /* 36 */ "R8\0"
136 /* 39 */ "R9\0"
137 /* 42 */ "R10B\0"
138 /* 47 */ "R11B\0"
139 /* 52 */ "R12B\0"
140 /* 57 */ "R13B\0"
141 /* 62 */ "R14B\0"
142 /* 67 */ "R4B\0"
143 /* 71 */ "R15B\0"
144 /* 76 */ "R5B\0"
145 /* 80 */ "R6B\0"
146 /* 84 */ "R7B\0"
147 /* 88 */ "R8B\0"
148 /* 92 */ "R9B\0"
149 /* 96 */ "PCB\0"
150 /* 100 */ "CGB\0"
151 /* 104 */ "SPB\0"
152 /* 108 */ "SRB\0"
153 /* 112 */ "PC\0"
154 /* 115 */ "CG\0"
155 /* 118 */ "SP\0"
156 /* 121 */ "SR\0"
157};
158#ifdef __GNUC__
159#pragma GCC diagnostic pop
160#endif
161
162extern const MCRegisterDesc MSP430RegDesc[] = { // Descriptors
163 { 3, 0, 0, 0, 0, 0, 0 },
164 { 115, 4, 1, 0, 4096, 0, 0 },
165 { 100, 1, 2, 1, 4096, 2, 0 },
166 { 112, 4, 1, 0, 4097, 0, 0 },
167 { 96, 1, 2, 1, 4097, 2, 0 },
168 { 118, 4, 1, 0, 4098, 0, 0 },
169 { 104, 1, 2, 1, 4098, 2, 0 },
170 { 121, 4, 1, 0, 4099, 0, 0 },
171 { 108, 1, 2, 1, 4099, 2, 0 },
172 { 20, 6, 1, 0, 4100, 0, 0 },
173 { 27, 6, 1, 0, 4101, 0, 0 },
174 { 30, 6, 1, 0, 4102, 0, 0 },
175 { 33, 6, 1, 0, 4103, 0, 0 },
176 { 36, 6, 1, 0, 4104, 0, 0 },
177 { 39, 6, 1, 0, 4105, 0, 0 },
178 { 0, 6, 1, 0, 4106, 0, 0 },
179 { 4, 6, 1, 0, 4107, 0, 0 },
180 { 8, 6, 1, 0, 4108, 0, 0 },
181 { 12, 6, 1, 0, 4109, 0, 0 },
182 { 16, 6, 1, 0, 4110, 0, 0 },
183 { 23, 6, 1, 0, 4111, 0, 0 },
184 { 67, 1, 0, 1, 4100, 2, 0 },
185 { 76, 1, 0, 1, 4101, 2, 0 },
186 { 80, 1, 0, 1, 4102, 2, 0 },
187 { 84, 1, 0, 1, 4103, 2, 0 },
188 { 88, 1, 0, 1, 4104, 2, 0 },
189 { 92, 1, 0, 1, 4105, 2, 0 },
190 { 42, 1, 0, 1, 4106, 2, 0 },
191 { 47, 1, 0, 1, 4107, 2, 0 },
192 { 52, 1, 0, 1, 4108, 2, 0 },
193 { 57, 1, 0, 1, 4109, 2, 0 },
194 { 62, 1, 0, 1, 4110, 2, 0 },
195 { 71, 1, 0, 1, 4111, 2, 0 },
196};
197
198extern const MCPhysReg MSP430RegUnitRoots[][2] = {
199 { MSP430::CGB },
200 { MSP430::PCB },
201 { MSP430::SPB },
202 { MSP430::SRB },
203 { MSP430::R4B },
204 { MSP430::R5B },
205 { MSP430::R6B },
206 { MSP430::R7B },
207 { MSP430::R8B },
208 { MSP430::R9B },
209 { MSP430::R10B },
210 { MSP430::R11B },
211 { MSP430::R12B },
212 { MSP430::R13B },
213 { MSP430::R14B },
214 { MSP430::R15B },
215};
216
217namespace { // Register classes...
218 // GR8 Register Class...
219 const MCPhysReg GR8[] = {
220 MSP430::R12B, MSP430::R13B, MSP430::R14B, MSP430::R15B, MSP430::R11B, MSP430::R10B, MSP430::R9B, MSP430::R8B, MSP430::R7B, MSP430::R6B, MSP430::R5B, MSP430::R4B, MSP430::PCB, MSP430::SPB, MSP430::SRB, MSP430::CGB,
221 };
222
223 // GR8 Bit set.
224 const uint8_t GR8Bits[] = {
225 0x54, 0x01, 0xe0, 0xff, 0x01,
226 };
227
228 // GR16 Register Class...
229 const MCPhysReg GR16[] = {
230 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::R11, MSP430::R10, MSP430::R9, MSP430::R8, MSP430::R7, MSP430::R6, MSP430::R5, MSP430::R4, MSP430::PC, MSP430::SP, MSP430::SR, MSP430::CG,
231 };
232
233 // GR16 Bit set.
234 const uint8_t GR16Bits[] = {
235 0xaa, 0xfe, 0x1f,
236 };
237
238} // end anonymous namespace
239
240
241#ifdef __GNUC__
242#pragma GCC diagnostic push
243#pragma GCC diagnostic ignored "-Woverlength-strings"
244#endif
245extern const char MSP430RegClassStrings[] = {
246 /* 0 */ "GR16\0"
247 /* 5 */ "GR8\0"
248};
249#ifdef __GNUC__
250#pragma GCC diagnostic pop
251#endif
252
253extern const MCRegisterClass MSP430MCRegisterClasses[] = {
254 { GR8, GR8Bits, 5, 16, sizeof(GR8Bits), MSP430::GR8RegClassID, 8, 1, true, false },
255 { GR16, GR16Bits, 0, 16, sizeof(GR16Bits), MSP430::GR16RegClassID, 16, 1, true, false },
256};
257
258// MSP430 Dwarf<->LLVM register mappings.
259extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[] = {
260 { 0U, MSP430::PC },
261 { 1U, MSP430::SP },
262 { 2U, MSP430::SR },
263 { 3U, MSP430::CG },
264 { 4U, MSP430::R4 },
265 { 5U, MSP430::R5 },
266 { 6U, MSP430::R6 },
267 { 7U, MSP430::R7 },
268 { 8U, MSP430::R8 },
269 { 9U, MSP430::R9 },
270 { 10U, MSP430::R10 },
271 { 11U, MSP430::R11 },
272 { 12U, MSP430::R12 },
273 { 13U, MSP430::R13 },
274 { 14U, MSP430::R14 },
275 { 15U, MSP430::R15 },
276 { 16U, MSP430::PCB },
277 { 17U, MSP430::SPB },
278 { 18U, MSP430::SRB },
279 { 19U, MSP430::CGB },
280 { 20U, MSP430::R4B },
281 { 21U, MSP430::R5B },
282 { 22U, MSP430::R6B },
283 { 23U, MSP430::R7B },
284 { 24U, MSP430::R8B },
285 { 25U, MSP430::R9B },
286 { 26U, MSP430::R10B },
287 { 27U, MSP430::R11B },
288 { 28U, MSP430::R12B },
289 { 29U, MSP430::R13B },
290 { 30U, MSP430::R14B },
291 { 31U, MSP430::R15B },
292};
293extern const unsigned MSP430DwarfFlavour0Dwarf2LSize = std::size(MSP430DwarfFlavour0Dwarf2L);
294
295extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[] = {
296 { 0U, MSP430::PC },
297 { 1U, MSP430::SP },
298 { 2U, MSP430::SR },
299 { 3U, MSP430::CG },
300 { 4U, MSP430::R4 },
301 { 5U, MSP430::R5 },
302 { 6U, MSP430::R6 },
303 { 7U, MSP430::R7 },
304 { 8U, MSP430::R8 },
305 { 9U, MSP430::R9 },
306 { 10U, MSP430::R10 },
307 { 11U, MSP430::R11 },
308 { 12U, MSP430::R12 },
309 { 13U, MSP430::R13 },
310 { 14U, MSP430::R14 },
311 { 15U, MSP430::R15 },
312 { 16U, MSP430::PCB },
313 { 17U, MSP430::SPB },
314 { 18U, MSP430::SRB },
315 { 19U, MSP430::CGB },
316 { 20U, MSP430::R4B },
317 { 21U, MSP430::R5B },
318 { 22U, MSP430::R6B },
319 { 23U, MSP430::R7B },
320 { 24U, MSP430::R8B },
321 { 25U, MSP430::R9B },
322 { 26U, MSP430::R10B },
323 { 27U, MSP430::R11B },
324 { 28U, MSP430::R12B },
325 { 29U, MSP430::R13B },
326 { 30U, MSP430::R14B },
327 { 31U, MSP430::R15B },
328};
329extern const unsigned MSP430EHFlavour0Dwarf2LSize = std::size(MSP430EHFlavour0Dwarf2L);
330
331extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[] = {
332 { MSP430::CG, 3U },
333 { MSP430::CGB, 19U },
334 { MSP430::PC, 0U },
335 { MSP430::PCB, 16U },
336 { MSP430::SP, 1U },
337 { MSP430::SPB, 17U },
338 { MSP430::SR, 2U },
339 { MSP430::SRB, 18U },
340 { MSP430::R4, 4U },
341 { MSP430::R5, 5U },
342 { MSP430::R6, 6U },
343 { MSP430::R7, 7U },
344 { MSP430::R8, 8U },
345 { MSP430::R9, 9U },
346 { MSP430::R10, 10U },
347 { MSP430::R11, 11U },
348 { MSP430::R12, 12U },
349 { MSP430::R13, 13U },
350 { MSP430::R14, 14U },
351 { MSP430::R15, 15U },
352 { MSP430::R4B, 20U },
353 { MSP430::R5B, 21U },
354 { MSP430::R6B, 22U },
355 { MSP430::R7B, 23U },
356 { MSP430::R8B, 24U },
357 { MSP430::R9B, 25U },
358 { MSP430::R10B, 26U },
359 { MSP430::R11B, 27U },
360 { MSP430::R12B, 28U },
361 { MSP430::R13B, 29U },
362 { MSP430::R14B, 30U },
363 { MSP430::R15B, 31U },
364};
365extern const unsigned MSP430DwarfFlavour0L2DwarfSize = std::size(MSP430DwarfFlavour0L2Dwarf);
366
367extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[] = {
368 { MSP430::CG, 3U },
369 { MSP430::CGB, 19U },
370 { MSP430::PC, 0U },
371 { MSP430::PCB, 16U },
372 { MSP430::SP, 1U },
373 { MSP430::SPB, 17U },
374 { MSP430::SR, 2U },
375 { MSP430::SRB, 18U },
376 { MSP430::R4, 4U },
377 { MSP430::R5, 5U },
378 { MSP430::R6, 6U },
379 { MSP430::R7, 7U },
380 { MSP430::R8, 8U },
381 { MSP430::R9, 9U },
382 { MSP430::R10, 10U },
383 { MSP430::R11, 11U },
384 { MSP430::R12, 12U },
385 { MSP430::R13, 13U },
386 { MSP430::R14, 14U },
387 { MSP430::R15, 15U },
388 { MSP430::R4B, 20U },
389 { MSP430::R5B, 21U },
390 { MSP430::R6B, 22U },
391 { MSP430::R7B, 23U },
392 { MSP430::R8B, 24U },
393 { MSP430::R9B, 25U },
394 { MSP430::R10B, 26U },
395 { MSP430::R11B, 27U },
396 { MSP430::R12B, 28U },
397 { MSP430::R13B, 29U },
398 { MSP430::R14B, 30U },
399 { MSP430::R15B, 31U },
400};
401extern const unsigned MSP430EHFlavour0L2DwarfSize = std::size(MSP430EHFlavour0L2Dwarf);
402
403extern const uint16_t MSP430RegEncodingTable[] = {
404 0,
405 3,
406 3,
407 0,
408 0,
409 1,
410 1,
411 2,
412 2,
413 4,
414 5,
415 6,
416 7,
417 8,
418 9,
419 10,
420 11,
421 12,
422 13,
423 14,
424 15,
425 4,
426 5,
427 6,
428 7,
429 8,
430 9,
431 10,
432 11,
433 12,
434 13,
435 14,
436 15,
437};
438static inline void InitMSP430MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
439 RI->InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC, MSP430MCRegisterClasses, 2, MSP430RegUnitRoots, 16, MSP430RegDiffLists, MSP430LaneMaskLists, MSP430RegStrings, MSP430RegClassStrings, MSP430SubRegIdxLists, 2,
440MSP430RegEncodingTable);
441
442 switch (DwarfFlavour) {
443 default:
444 llvm_unreachable("Unknown DWARF flavour");
445 case 0:
446 RI->mapDwarfRegsToLLVMRegs(MSP430DwarfFlavour0Dwarf2L, MSP430DwarfFlavour0Dwarf2LSize, false);
447 break;
448 }
449 switch (EHFlavour) {
450 default:
451 llvm_unreachable("Unknown DWARF flavour");
452 case 0:
453 RI->mapDwarfRegsToLLVMRegs(MSP430EHFlavour0Dwarf2L, MSP430EHFlavour0Dwarf2LSize, true);
454 break;
455 }
456 switch (DwarfFlavour) {
457 default:
458 llvm_unreachable("Unknown DWARF flavour");
459 case 0:
460 RI->mapLLVMRegsToDwarfRegs(MSP430DwarfFlavour0L2Dwarf, MSP430DwarfFlavour0L2DwarfSize, false);
461 break;
462 }
463 switch (EHFlavour) {
464 default:
465 llvm_unreachable("Unknown DWARF flavour");
466 case 0:
467 RI->mapLLVMRegsToDwarfRegs(MSP430EHFlavour0L2Dwarf, MSP430EHFlavour0L2DwarfSize, true);
468 break;
469 }
470}
471
472} // end namespace llvm
473
474#endif // GET_REGINFO_MC_DESC
475
476/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
477|* *|
478|* Register Information Header Fragment *|
479|* *|
480|* Automatically generated file, do not edit! *|
481|* *|
482\*===----------------------------------------------------------------------===*/
483
484
485#ifdef GET_REGINFO_HEADER
486#undef GET_REGINFO_HEADER
487
488#include "llvm/CodeGen/TargetRegisterInfo.h"
489
490namespace llvm {
491
492class MSP430FrameLowering;
493
494struct MSP430GenRegisterInfo : public TargetRegisterInfo {
495 explicit MSP430GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
496 unsigned PC = 0, unsigned HwMode = 0);
497 unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
498 LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
499 LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
500 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
501 const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
502 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
503 unsigned getRegUnitWeight(unsigned RegUnit) const override;
504 unsigned getNumRegPressureSets() const override;
505 const char *getRegPressureSetName(unsigned Idx) const override;
506 unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
507 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
508 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
509 ArrayRef<const char *> getRegMaskNames() const override;
510 ArrayRef<const uint32_t *> getRegMasks() const override;
511 bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
512 bool isFixedRegister(const MachineFunction &, MCRegister) const override;
513 bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
514 bool isConstantPhysReg(MCRegister PhysReg) const override final;
515 /// Devirtualized TargetFrameLowering.
516 static const MSP430FrameLowering *getFrameLowering(
517 const MachineFunction &MF);
518};
519
520namespace MSP430 { // Register classes
521 extern const TargetRegisterClass GR8RegClass;
522 extern const TargetRegisterClass GR16RegClass;
523} // end namespace MSP430
524
525} // end namespace llvm
526
527#endif // GET_REGINFO_HEADER
528
529/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
530|* *|
531|* Target Register and Register Classes Information *|
532|* *|
533|* Automatically generated file, do not edit! *|
534|* *|
535\*===----------------------------------------------------------------------===*/
536
537
538#ifdef GET_REGINFO_TARGET_DESC
539#undef GET_REGINFO_TARGET_DESC
540
541namespace llvm {
542
543extern const MCRegisterClass MSP430MCRegisterClasses[];
544
545static const MVT::SimpleValueType VTLists[] = {
546 /* 0 */ MVT::i8, MVT::Other,
547 /* 2 */ MVT::i16, MVT::Other,
548};
549
550static const char *SubRegIndexNameTable[] = { "subreg_8bit", "" };
551
552static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
553 { 65535, 65535 },
554 { 0, 8 }, // subreg_8bit
555};
556
557
558static const LaneBitmask SubRegIndexLaneMaskTable[] = {
559 LaneBitmask::getAll(),
560 LaneBitmask(0x0000000000000001), // subreg_8bit
561 };
562
563
564
565static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
566 // Mode = 0 (Default)
567 { 8, 8, 8, /*VTLists+*/0 }, // GR8
568 { 16, 16, 16, /*VTLists+*/2 }, // GR16
569};
570
571static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
572
573static const uint32_t GR8SubClassMask[] = {
574 0x00000001,
575 0x00000002, // subreg_8bit
576};
577
578static const uint32_t GR16SubClassMask[] = {
579 0x00000002,
580};
581
582static const uint16_t SuperRegIdxSeqs[] = {
583 /* 0 */ 1, 0,
584};
585
586
587namespace MSP430 { // Register class instances
588 extern const TargetRegisterClass GR8RegClass = {
589 &MSP430MCRegisterClasses[GR8RegClassID],
590 GR8SubClassMask,
591 SuperRegIdxSeqs + 0,
592 LaneBitmask(0x0000000000000001),
593 0,
594 false,
595 0x00, /* TSFlags */
596 false, /* HasDisjunctSubRegs */
597 false, /* CoveredBySubRegs */
598 NullRegClasses,
599 nullptr
600 };
601
602 extern const TargetRegisterClass GR16RegClass = {
603 &MSP430MCRegisterClasses[GR16RegClassID],
604 GR16SubClassMask,
605 SuperRegIdxSeqs + 1,
606 LaneBitmask(0x0000000000000001),
607 0,
608 false,
609 0x00, /* TSFlags */
610 false, /* HasDisjunctSubRegs */
611 false, /* CoveredBySubRegs */
612 NullRegClasses,
613 nullptr
614 };
615
616} // end namespace MSP430
617
618namespace {
619 const TargetRegisterClass *const RegisterClasses[] = {
620 &MSP430::GR8RegClass,
621 &MSP430::GR16RegClass,
622 };
623} // end anonymous namespace
624
625static const uint8_t CostPerUseTable[] = {
6260, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
627
628
629static const bool InAllocatableClassTable[] = {
630false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
631
632
633static const TargetRegisterInfoDesc MSP430RegInfoDesc = { // Extra Descriptors
634CostPerUseTable, 1, InAllocatableClassTable};
635
636unsigned MSP430GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
637 static const uint8_t Rows[1][1] = {
638 { 0, },
639 };
640
641 --IdxA; assert(IdxA < 1); (void) IdxA;
642 --IdxB; assert(IdxB < 1);
643 return Rows[0][IdxB];
644}
645
646 struct MaskRolOp {
647 LaneBitmask Mask;
648 uint8_t RotateLeft;
649 };
650 static const MaskRolOp LaneMaskComposeSequences[] = {
651 { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
652 };
653 static const uint8_t CompositeSequences[] = {
654 0 // to subreg_8bit
655 };
656
657LaneBitmask MSP430GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
658 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
659 LaneBitmask Result;
660 for (const MaskRolOp *Ops =
661 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
662 Ops->Mask.any(); ++Ops) {
663 LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
664 if (unsigned S = Ops->RotateLeft)
665 Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
666 else
667 Result |= LaneBitmask(M);
668 }
669 return Result;
670}
671
672LaneBitmask MSP430GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
673 LaneMask &= getSubRegIndexLaneMask(IdxA);
674 --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
675 LaneBitmask Result;
676 for (const MaskRolOp *Ops =
677 &LaneMaskComposeSequences[CompositeSequences[IdxA]];
678 Ops->Mask.any(); ++Ops) {
679 LaneBitmask::Type M = LaneMask.getAsInteger();
680 if (unsigned S = Ops->RotateLeft)
681 Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
682 else
683 Result |= LaneBitmask(M);
684 }
685 return Result;
686}
687
688const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
689 static const uint8_t Table[2][1] = {
690 { // GR8
691 0, // subreg_8bit
692 },
693 { // GR16
694 2, // subreg_8bit -> GR16
695 },
696 };
697 assert(RC && "Missing regclass");
698 if (!Idx) return RC;
699 --Idx;
700 assert(Idx < 1 && "Bad subreg");
701 unsigned TV = Table[RC->getID()][Idx];
702 return TV ? getRegClass(TV - 1) : nullptr;
703}
704
705const TargetRegisterClass *MSP430GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
706 static const uint8_t Table[2][1] = {
707 { // GR8
708 0, // GR8:subreg_8bit
709 },
710 { // GR16
711 1, // GR16:subreg_8bit -> GR8
712 },
713 };
714 assert(RC && "Missing regclass");
715 if (!Idx) return RC;
716 --Idx;
717 assert(Idx < 1 && "Bad subreg");
718 unsigned TV = Table[RC->getID()][Idx];
719 return TV ? getRegClass(TV - 1) : nullptr;
720}
721
722/// Get the weight in units of pressure for this register class.
723const RegClassWeight &MSP430GenRegisterInfo::
724getRegClassWeight(const TargetRegisterClass *RC) const {
725 static const RegClassWeight RCWeightTable[] = {
726 {1, 16}, // GR8
727 {1, 16}, // GR16
728 };
729 return RCWeightTable[RC->getID()];
730}
731
732/// Get the weight in units of pressure for this register unit.
733unsigned MSP430GenRegisterInfo::
734getRegUnitWeight(unsigned RegUnit) const {
735 assert(RegUnit < 16 && "invalid register unit");
736 // All register units have unit weight.
737 return 1;
738}
739
740
741// Get the number of dimensions of register pressure.
742unsigned MSP430GenRegisterInfo::getNumRegPressureSets() const {
743 return 1;
744}
745
746// Get the name of this register unit pressure set.
747const char *MSP430GenRegisterInfo::
748getRegPressureSetName(unsigned Idx) const {
749 static const char *PressureNameTable[] = {
750 "GR8",
751 };
752 return PressureNameTable[Idx];
753}
754
755// Get the register unit pressure limit for this dimension.
756// This limit must be adjusted dynamically for reserved registers.
757unsigned MSP430GenRegisterInfo::
758getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
759 static const uint8_t PressureLimitTable[] = {
760 16, // 0: GR8
761 };
762 return PressureLimitTable[Idx];
763}
764
765/// Table of pressure sets per register class or unit.
766static const int RCSetsTable[] = {
767 /* 0 */ 0, -1,
768};
769
770/// Get the dimensions of register pressure impacted by this register class.
771/// Returns a -1 terminated array of pressure set IDs
772const int *MSP430GenRegisterInfo::
773getRegClassPressureSets(const TargetRegisterClass *RC) const {
774 static const uint8_t RCSetStartTable[] = {
775 0,0,};
776 return &RCSetsTable[RCSetStartTable[RC->getID()]];
777}
778
779/// Get the dimensions of register pressure impacted by this register unit.
780/// Returns a -1 terminated array of pressure set IDs
781const int *MSP430GenRegisterInfo::
782getRegUnitPressureSets(unsigned RegUnit) const {
783 assert(RegUnit < 16 && "invalid register unit");
784 static const uint8_t RUSetStartTable[] = {
785 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,};
786 return &RCSetsTable[RUSetStartTable[RegUnit]];
787}
788
789extern const MCRegisterDesc MSP430RegDesc[];
790extern const int16_t MSP430RegDiffLists[];
791extern const LaneBitmask MSP430LaneMaskLists[];
792extern const char MSP430RegStrings[];
793extern const char MSP430RegClassStrings[];
794extern const MCPhysReg MSP430RegUnitRoots[][2];
795extern const uint16_t MSP430SubRegIdxLists[];
796extern const uint16_t MSP430RegEncodingTable[];
797// MSP430 Dwarf<->LLVM register mappings.
798extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0Dwarf2L[];
799extern const unsigned MSP430DwarfFlavour0Dwarf2LSize;
800
801extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0Dwarf2L[];
802extern const unsigned MSP430EHFlavour0Dwarf2LSize;
803
804extern const MCRegisterInfo::DwarfLLVMRegPair MSP430DwarfFlavour0L2Dwarf[];
805extern const unsigned MSP430DwarfFlavour0L2DwarfSize;
806
807extern const MCRegisterInfo::DwarfLLVMRegPair MSP430EHFlavour0L2Dwarf[];
808extern const unsigned MSP430EHFlavour0L2DwarfSize;
809
810MSP430GenRegisterInfo::
811MSP430GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
812 unsigned PC, unsigned HwMode)
813 : TargetRegisterInfo(&MSP430RegInfoDesc, RegisterClasses, RegisterClasses+2,
814 SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
815 LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
816 InitMCRegisterInfo(MSP430RegDesc, 33, RA, PC,
817 MSP430MCRegisterClasses, 2,
818 MSP430RegUnitRoots,
819 16,
820 MSP430RegDiffLists,
821 MSP430LaneMaskLists,
822 MSP430RegStrings,
823 MSP430RegClassStrings,
824 MSP430SubRegIdxLists,
825 2,
826 MSP430RegEncodingTable);
827
828 switch (DwarfFlavour) {
829 default:
830 llvm_unreachable("Unknown DWARF flavour");
831 case 0:
832 mapDwarfRegsToLLVMRegs(MSP430DwarfFlavour0Dwarf2L, MSP430DwarfFlavour0Dwarf2LSize, false);
833 break;
834 }
835 switch (EHFlavour) {
836 default:
837 llvm_unreachable("Unknown DWARF flavour");
838 case 0:
839 mapDwarfRegsToLLVMRegs(MSP430EHFlavour0Dwarf2L, MSP430EHFlavour0Dwarf2LSize, true);
840 break;
841 }
842 switch (DwarfFlavour) {
843 default:
844 llvm_unreachable("Unknown DWARF flavour");
845 case 0:
846 mapLLVMRegsToDwarfRegs(MSP430DwarfFlavour0L2Dwarf, MSP430DwarfFlavour0L2DwarfSize, false);
847 break;
848 }
849 switch (EHFlavour) {
850 default:
851 llvm_unreachable("Unknown DWARF flavour");
852 case 0:
853 mapLLVMRegsToDwarfRegs(MSP430EHFlavour0L2Dwarf, MSP430EHFlavour0L2DwarfSize, true);
854 break;
855 }
856}
857
858
859
860ArrayRef<const uint32_t *> MSP430GenRegisterInfo::getRegMasks() const {
861 return std::nullopt;
862}
863
864bool MSP430GenRegisterInfo::
865isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
866 return
867 false;
868}
869
870bool MSP430GenRegisterInfo::
871isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
872 return
873 false;
874}
875
876bool MSP430GenRegisterInfo::
877isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
878 return
879 false;
880}
881
882bool MSP430GenRegisterInfo::
883isConstantPhysReg(MCRegister PhysReg) const {
884 return
885 false;
886}
887
888ArrayRef<const char *> MSP430GenRegisterInfo::getRegMaskNames() const {
889 return std::nullopt;
890}
891
892const MSP430FrameLowering *
893MSP430GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
894 return static_cast<const MSP430FrameLowering *>(
895 MF.getSubtarget().getFrameLowering());
896}
897
898} // end namespace llvm
899
900#endif // GET_REGINFO_TARGET_DESC
901
902