1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace MSP430 {
15enum {
16 FeatureHWMult16 = 0,
17 FeatureHWMult32 = 1,
18 FeatureHWMultF5 = 2,
19 FeatureX = 3,
20 NumSubtargetFeatures = 4
21};
22} // end namespace MSP430
23} // end namespace llvm
24
25#endif // GET_SUBTARGETINFO_ENUM
26
27
28#ifdef GET_SUBTARGETINFO_MACRO
29GET_SUBTARGETINFO_MACRO(ExtendedInsts, false, extendedInsts)
30#undef GET_SUBTARGETINFO_MACRO
31#endif // GET_SUBTARGETINFO_MACRO
32
33
34#ifdef GET_SUBTARGETINFO_MC_DESC
35#undef GET_SUBTARGETINFO_MC_DESC
36
37namespace llvm {
38// Sorted (by key) array of values for CPU features.
39extern const llvm::SubtargetFeatureKV MSP430FeatureKV[] = {
40 { "ext", "Enable MSP430-X extensions", MSP430::FeatureX, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
41 { "hwmult16", "Enable 16-bit hardware multiplier", MSP430::FeatureHWMult16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
42 { "hwmult32", "Enable 32-bit hardware multiplier", MSP430::FeatureHWMult32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
43 { "hwmultf5", "Enable F5 series hardware multiplier", MSP430::FeatureHWMultF5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
44};
45
46#ifdef DBGFIELD
47#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
48#endif
49#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
50#define DBGFIELD(x) x,
51#else
52#define DBGFIELD(x)
53#endif
54
55// ===============================================================
56// Data tables for the new per-operand machine model.
57
58// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
59extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[] = {
60 { 0, 0, 0 }, // Invalid
61}; // MSP430WriteProcResTable
62
63// {Cycles, WriteResourceID}
64extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[] = {
65 { 0, 0}, // Invalid
66}; // MSP430WriteLatencyTable
67
68// {UseIdx, WriteResourceID, Cycles}
69extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[] = {
70 {0, 0, 0}, // Invalid
71}; // MSP430ReadAdvanceTable
72
73#undef DBGFIELD
74
75static const llvm::MCSchedModel NoSchedModel = {
76 MCSchedModel::DefaultIssueWidth,
77 MCSchedModel::DefaultMicroOpBufferSize,
78 MCSchedModel::DefaultLoopMicroOpBufferSize,
79 MCSchedModel::DefaultLoadLatency,
80 MCSchedModel::DefaultHighLatency,
81 MCSchedModel::DefaultMispredictPenalty,
82 false, // PostRAScheduler
83 false, // CompleteModel
84 false, // EnableIntervals
85 0, // Processor ID
86 nullptr, nullptr, 0, 0, // No instruction-level machine model.
87 nullptr, // No Itinerary
88 nullptr // No extra processor descriptor
89};
90
91// Sorted (by key) array of values for CPU subtype.
92extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[] = {
93 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
94 { "msp430", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
95 { "msp430x", { { { 0x8ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
96};
97
98namespace MSP430_MC {
99unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
100 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
101 // Don't know how to resolve this scheduling class.
102 return 0;
103}
104} // end namespace MSP430_MC
105
106struct MSP430GenMCSubtargetInfo : public MCSubtargetInfo {
107 MSP430GenMCSubtargetInfo(const Triple &TT,
108 StringRef CPU, StringRef TuneCPU, StringRef FS,
109 ArrayRef<SubtargetFeatureKV> PF,
110 ArrayRef<SubtargetSubTypeKV> PD,
111 const MCWriteProcResEntry *WPR,
112 const MCWriteLatencyEntry *WL,
113 const MCReadAdvanceEntry *RA, const InstrStage *IS,
114 const unsigned *OC, const unsigned *FP) :
115 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
116 WPR, WL, RA, IS, OC, FP) { }
117
118 unsigned resolveVariantSchedClass(unsigned SchedClass,
119 const MCInst *MI, const MCInstrInfo *MCII,
120 unsigned CPUID) const override {
121 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
122 }
123};
124
125static inline MCSubtargetInfo *createMSP430MCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
126 return new MSP430GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, MSP430FeatureKV, MSP430SubTypeKV,
127 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
128 nullptr, nullptr, nullptr);
129}
130
131} // end namespace llvm
132
133#endif // GET_SUBTARGETINFO_MC_DESC
134
135
136#ifdef GET_SUBTARGETINFO_TARGET_DESC
137#undef GET_SUBTARGETINFO_TARGET_DESC
138
139#include "llvm/Support/Debug.h"
140#include "llvm/Support/raw_ostream.h"
141
142// ParseSubtargetFeatures - Parses features string setting specified
143// subtarget options.
144void llvm::MSP430Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
145 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
146 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
147 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
148 InitMCProcessorInfo(CPU, TuneCPU, FS);
149 const FeatureBitset &Bits = getFeatureBits();
150 if (Bits[MSP430::FeatureHWMult16] && HWMultMode < HWMult16) HWMultMode = HWMult16;
151 if (Bits[MSP430::FeatureHWMult32] && HWMultMode < HWMult32) HWMultMode = HWMult32;
152 if (Bits[MSP430::FeatureHWMultF5] && HWMultMode < HWMultF5) HWMultMode = HWMultF5;
153 if (Bits[MSP430::FeatureX]) ExtendedInsts = true;
154}
155#endif // GET_SUBTARGETINFO_TARGET_DESC
156
157
158#ifdef GET_SUBTARGETINFO_HEADER
159#undef GET_SUBTARGETINFO_HEADER
160
161namespace llvm {
162class DFAPacketizer;
163namespace MSP430_MC {
164unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
165} // end namespace MSP430_MC
166
167struct MSP430GenSubtargetInfo : public TargetSubtargetInfo {
168 explicit MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
169public:
170 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
171 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
172 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
173};
174} // end namespace llvm
175
176#endif // GET_SUBTARGETINFO_HEADER
177
178
179#ifdef GET_SUBTARGETINFO_CTOR
180#undef GET_SUBTARGETINFO_CTOR
181
182#include "llvm/CodeGen/TargetSchedule.h"
183
184namespace llvm {
185extern const llvm::SubtargetFeatureKV MSP430FeatureKV[];
186extern const llvm::SubtargetSubTypeKV MSP430SubTypeKV[];
187extern const llvm::MCWriteProcResEntry MSP430WriteProcResTable[];
188extern const llvm::MCWriteLatencyEntry MSP430WriteLatencyTable[];
189extern const llvm::MCReadAdvanceEntry MSP430ReadAdvanceTable[];
190MSP430GenSubtargetInfo::MSP430GenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
191 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(MSP430FeatureKV, 4), ArrayRef(MSP430SubTypeKV, 3),
192 MSP430WriteProcResTable, MSP430WriteLatencyTable, MSP430ReadAdvanceTable,
193 nullptr, nullptr, nullptr) {}
194
195unsigned MSP430GenSubtargetInfo
196::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
197 report_fatal_error("Expected a variant SchedClass");
198} // MSP430GenSubtargetInfo::resolveSchedClass
199
200unsigned MSP430GenSubtargetInfo
201::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
202 return MSP430_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
203} // MSP430GenSubtargetInfo::resolveVariantSchedClass
204
205} // end namespace llvm
206
207#endif // GET_SUBTARGETINFO_CTOR
208
209
210#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
211#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
212
213#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
214
215
216#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
217#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
218
219#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
220
221