| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Assembly Matcher Source Fragment *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* From: Mips.td *| |
| 7 | |* *| |
| 8 | \*===----------------------------------------------------------------------===*/ |
| 9 | |
| 10 | |
| 11 | #ifdef GET_ASSEMBLER_HEADER |
| 12 | #undef GET_ASSEMBLER_HEADER |
| 13 | // This should be included into the middle of the declaration of |
| 14 | // your subclasses implementation of MCTargetAsmParser. |
| 15 | FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const; |
| 16 | void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
| 17 | const OperandVector &Operands); |
| 18 | void convertToMapAndConstraints(unsigned Kind, |
| 19 | const OperandVector &Operands) override; |
| 20 | unsigned MatchInstructionImpl(const OperandVector &Operands, |
| 21 | MCInst &Inst, |
| 22 | uint64_t &ErrorInfo, |
| 23 | FeatureBitset &MissingFeatures, |
| 24 | bool matchingInlineAsm, |
| 25 | unsigned VariantID = 0); |
| 26 | unsigned MatchInstructionImpl(const OperandVector &Operands, |
| 27 | MCInst &Inst, |
| 28 | uint64_t &ErrorInfo, |
| 29 | bool matchingInlineAsm, |
| 30 | unsigned VariantID = 0) { |
| 31 | FeatureBitset MissingFeatures; |
| 32 | return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, |
| 33 | matchingInlineAsm, VariantID); |
| 34 | } |
| 35 | |
| 36 | ParseStatus MatchOperandParserImpl( |
| 37 | OperandVector &Operands, |
| 38 | StringRef Mnemonic, |
| 39 | bool ParseForAllFeatures = false); |
| 40 | ParseStatus tryCustomParseOperand( |
| 41 | OperandVector &Operands, |
| 42 | unsigned MCK); |
| 43 | |
| 44 | #endif // GET_ASSEMBLER_HEADER |
| 45 | |
| 46 | |
| 47 | #ifdef GET_OPERAND_DIAGNOSTIC_TYPES |
| 48 | #undef GET_OPERAND_DIAGNOSTIC_TYPES |
| 49 | |
| 50 | Match_Immz, |
| 51 | Match_MemSImm10, |
| 52 | Match_MemSImm10Lsl1, |
| 53 | Match_MemSImm10Lsl2, |
| 54 | Match_MemSImm10Lsl3, |
| 55 | Match_MemSImm11, |
| 56 | Match_MemSImm12, |
| 57 | Match_MemSImm16, |
| 58 | Match_MemSImm9, |
| 59 | Match_MemSImmPtr, |
| 60 | Match_SImm10_0, |
| 61 | Match_SImm10_Lsl1, |
| 62 | Match_SImm10_Lsl2, |
| 63 | Match_SImm10_Lsl3, |
| 64 | Match_SImm11_0, |
| 65 | Match_SImm16, |
| 66 | Match_SImm16_Relaxed, |
| 67 | Match_SImm19_Lsl2, |
| 68 | Match_SImm32, |
| 69 | Match_SImm32_Relaxed, |
| 70 | Match_SImm4_0, |
| 71 | Match_SImm5_0, |
| 72 | Match_SImm6_0, |
| 73 | Match_SImm7_Lsl2, |
| 74 | Match_SImm9_0, |
| 75 | Match_UImm10_0, |
| 76 | Match_UImm16, |
| 77 | Match_UImm16_AltRelaxed, |
| 78 | Match_UImm16_Relaxed, |
| 79 | Match_UImm1_0, |
| 80 | Match_UImm20_0, |
| 81 | Match_UImm26_0, |
| 82 | Match_UImm2_0, |
| 83 | Match_UImm2_1, |
| 84 | Match_UImm32_Coerced, |
| 85 | Match_UImm3_0, |
| 86 | Match_UImm4_0, |
| 87 | Match_UImm5_0, |
| 88 | Match_UImm5_0_Report_UImm6, |
| 89 | Match_UImm5_1, |
| 90 | Match_UImm5_32, |
| 91 | Match_UImm5_33, |
| 92 | Match_UImm5_Lsl2, |
| 93 | Match_UImm6_0, |
| 94 | Match_UImm6_Lsl2, |
| 95 | Match_UImm7_0, |
| 96 | Match_UImm7_N1, |
| 97 | Match_UImm8_0, |
| 98 | Match_UImmRange2_64, |
| 99 | END_OPERAND_DIAGNOSTIC_TYPES |
| 100 | #endif // GET_OPERAND_DIAGNOSTIC_TYPES |
| 101 | |
| 102 | |
| 103 | #ifdef GET_REGISTER_MATCHER |
| 104 | #undef GET_REGISTER_MATCHER |
| 105 | |
| 106 | // Bits for subtarget features that participate in instruction matching. |
| 107 | enum SubtargetFeatureBits : uint8_t { |
| 108 | Feature_HasMips2Bit = 11, |
| 109 | Feature_HasMips3_32Bit = 14, |
| 110 | Feature_HasMips3_32r2Bit = 15, |
| 111 | Feature_HasMips3Bit = 12, |
| 112 | Feature_NotMips3Bit = 47, |
| 113 | Feature_HasMips4_32Bit = 16, |
| 114 | Feature_NotMips4_32Bit = 48, |
| 115 | Feature_HasMips4_32r2Bit = 17, |
| 116 | Feature_HasMips5_32r2Bit = 18, |
| 117 | Feature_HasMips32Bit = 19, |
| 118 | Feature_HasMips32r2Bit = 20, |
| 119 | Feature_HasMips32r5Bit = 21, |
| 120 | Feature_HasMips32r6Bit = 22, |
| 121 | Feature_NotMips32r6Bit = 49, |
| 122 | Feature_IsGP64bitBit = 33, |
| 123 | Feature_IsGP32bitBit = 32, |
| 124 | Feature_IsPTR64bitBit = 37, |
| 125 | Feature_IsPTR32bitBit = 36, |
| 126 | Feature_HasMips64Bit = 23, |
| 127 | Feature_NotMips64Bit = 50, |
| 128 | Feature_HasMips64r2Bit = 24, |
| 129 | Feature_HasMips64r5Bit = 25, |
| 130 | Feature_HasMips64r6Bit = 26, |
| 131 | Feature_NotMips64r6Bit = 51, |
| 132 | Feature_InMips16ModeBit = 30, |
| 133 | Feature_NotInMips16ModeBit = 46, |
| 134 | Feature_HasCnMipsBit = 1, |
| 135 | Feature_NotCnMipsBit = 42, |
| 136 | Feature_HasCnMipsPBit = 2, |
| 137 | Feature_NotCnMipsPBit = 43, |
| 138 | Feature_IsSym32Bit = 39, |
| 139 | Feature_IsSym64Bit = 40, |
| 140 | Feature_HasStdEncBit = 27, |
| 141 | Feature_InMicroMipsBit = 29, |
| 142 | Feature_NotInMicroMipsBit = 45, |
| 143 | Feature_HasEVABit = 6, |
| 144 | Feature_HasMSABit = 8, |
| 145 | Feature_HasMadd4Bit = 10, |
| 146 | Feature_HasMTBit = 9, |
| 147 | Feature_UseIndirectJumpsHazardBit = 52, |
| 148 | Feature_NoIndirectJumpGuardsBit = 41, |
| 149 | Feature_HasCRCBit = 0, |
| 150 | Feature_HasVirtBit = 28, |
| 151 | Feature_HasGINVBit = 7, |
| 152 | Feature_IsFP64bitBit = 31, |
| 153 | Feature_NotFP64bitBit = 44, |
| 154 | Feature_IsSingleFloatBit = 38, |
| 155 | Feature_IsNotSingleFloatBit = 34, |
| 156 | Feature_IsNotSoftFloatBit = 35, |
| 157 | Feature_HasMips3DBit = 13, |
| 158 | Feature_HasDSPBit = 3, |
| 159 | Feature_HasDSPR2Bit = 4, |
| 160 | Feature_HasDSPR3Bit = 5, |
| 161 | }; |
| 162 | |
| 163 | #endif // GET_REGISTER_MATCHER |
| 164 | |
| 165 | |
| 166 | #ifdef GET_SUBTARGET_FEATURE_NAME |
| 167 | #undef GET_SUBTARGET_FEATURE_NAME |
| 168 | |
| 169 | // User-level names for subtarget features that participate in |
| 170 | // instruction matching. |
| 171 | static const char *getSubtargetFeatureName(uint64_t Val) { |
| 172 | switch(Val) { |
| 173 | case Feature_HasMips2Bit: return ""; |
| 174 | case Feature_HasMips3_32Bit: return ""; |
| 175 | case Feature_HasMips3_32r2Bit: return ""; |
| 176 | case Feature_HasMips3Bit: return ""; |
| 177 | case Feature_NotMips3Bit: return ""; |
| 178 | case Feature_HasMips4_32Bit: return ""; |
| 179 | case Feature_NotMips4_32Bit: return ""; |
| 180 | case Feature_HasMips4_32r2Bit: return ""; |
| 181 | case Feature_HasMips5_32r2Bit: return ""; |
| 182 | case Feature_HasMips32Bit: return ""; |
| 183 | case Feature_HasMips32r2Bit: return ""; |
| 184 | case Feature_HasMips32r5Bit: return ""; |
| 185 | case Feature_HasMips32r6Bit: return ""; |
| 186 | case Feature_NotMips32r6Bit: return ""; |
| 187 | case Feature_IsGP64bitBit: return ""; |
| 188 | case Feature_IsGP32bitBit: return ""; |
| 189 | case Feature_IsPTR64bitBit: return ""; |
| 190 | case Feature_IsPTR32bitBit: return ""; |
| 191 | case Feature_HasMips64Bit: return ""; |
| 192 | case Feature_NotMips64Bit: return ""; |
| 193 | case Feature_HasMips64r2Bit: return ""; |
| 194 | case Feature_HasMips64r5Bit: return ""; |
| 195 | case Feature_HasMips64r6Bit: return ""; |
| 196 | case Feature_NotMips64r6Bit: return ""; |
| 197 | case Feature_InMips16ModeBit: return ""; |
| 198 | case Feature_NotInMips16ModeBit: return ""; |
| 199 | case Feature_HasCnMipsBit: return ""; |
| 200 | case Feature_NotCnMipsBit: return ""; |
| 201 | case Feature_HasCnMipsPBit: return ""; |
| 202 | case Feature_NotCnMipsPBit: return ""; |
| 203 | case Feature_IsSym32Bit: return ""; |
| 204 | case Feature_IsSym64Bit: return ""; |
| 205 | case Feature_HasStdEncBit: return ""; |
| 206 | case Feature_InMicroMipsBit: return ""; |
| 207 | case Feature_NotInMicroMipsBit: return ""; |
| 208 | case Feature_HasEVABit: return ""; |
| 209 | case Feature_HasMSABit: return ""; |
| 210 | case Feature_HasMadd4Bit: return ""; |
| 211 | case Feature_HasMTBit: return ""; |
| 212 | case Feature_UseIndirectJumpsHazardBit: return ""; |
| 213 | case Feature_NoIndirectJumpGuardsBit: return ""; |
| 214 | case Feature_HasCRCBit: return ""; |
| 215 | case Feature_HasVirtBit: return ""; |
| 216 | case Feature_HasGINVBit: return ""; |
| 217 | case Feature_IsFP64bitBit: return ""; |
| 218 | case Feature_NotFP64bitBit: return ""; |
| 219 | case Feature_IsSingleFloatBit: return ""; |
| 220 | case Feature_IsNotSingleFloatBit: return ""; |
| 221 | case Feature_IsNotSoftFloatBit: return ""; |
| 222 | case Feature_HasMips3DBit: return ""; |
| 223 | case Feature_HasDSPBit: return ""; |
| 224 | case Feature_HasDSPR2Bit: return ""; |
| 225 | case Feature_HasDSPR3Bit: return ""; |
| 226 | default: return "(unknown)"; |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | #endif // GET_SUBTARGET_FEATURE_NAME |
| 231 | |
| 232 | |
| 233 | #ifdef GET_MATCHER_IMPLEMENTATION |
| 234 | #undef GET_MATCHER_IMPLEMENTATION |
| 235 | |
| 236 | enum { |
| 237 | Tie0_1_1, |
| 238 | Tie0_1_2, |
| 239 | }; |
| 240 | |
| 241 | static const uint8_t TiedAsmOperandTable[][3] = { |
| 242 | /* Tie0_1_1 */ { 0, 1, 1 }, |
| 243 | /* Tie0_1_2 */ { 0, 1, 2 }, |
| 244 | }; |
| 245 | |
| 246 | namespace { |
| 247 | enum OperatorConversionKind { |
| 248 | CVT_Done, |
| 249 | CVT_Reg, |
| 250 | CVT_Tied, |
| 251 | CVT_95_addGPR32AsmRegOperands, |
| 252 | CVT_95_addAFGR64AsmRegOperands, |
| 253 | CVT_95_addFGR64AsmRegOperands, |
| 254 | CVT_95_addFGR32AsmRegOperands, |
| 255 | CVT_95_addSImmOperands_LT_32_GT_, |
| 256 | CVT_95_addMSA128AsmRegOperands, |
| 257 | CVT_95_addSImmOperands_LT_16_GT_, |
| 258 | CVT_95_Reg, |
| 259 | CVT_95_addImmOperands, |
| 260 | CVT_95_addGPRMM16AsmRegOperands, |
| 261 | CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, |
| 262 | CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, |
| 263 | CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, |
| 264 | CVT_95_addUImmOperands_LT_16_GT_, |
| 265 | CVT_95_addGPR64AsmRegOperands, |
| 266 | CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, |
| 267 | CVT_regZERO, |
| 268 | CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, |
| 269 | CVT_regFCC0, |
| 270 | CVT_95_addFCCAsmRegOperands, |
| 271 | CVT_95_addCOP2AsmRegOperands, |
| 272 | CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, |
| 273 | CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, |
| 274 | CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, |
| 275 | CVT_imm_95_0, |
| 276 | CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, |
| 277 | CVT_95_addMemOperands, |
| 278 | CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, |
| 279 | CVT_95_addCCRAsmRegOperands, |
| 280 | CVT_95_addMSACtrlAsmRegOperands, |
| 281 | CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, |
| 282 | CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, |
| 283 | CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, |
| 284 | CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, |
| 285 | CVT_95_addGPR32NonZeroAsmRegOperands, |
| 286 | CVT_95_addGPR32ZeroAsmRegOperands, |
| 287 | CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, |
| 288 | CVT_95_addCOP0AsmRegOperands, |
| 289 | CVT_regZERO_64, |
| 290 | CVT_95_addACC64DSPAsmRegOperands, |
| 291 | CVT_95_addConstantUImmOperands_LT_1_GT_, |
| 292 | CVT_regRA, |
| 293 | CVT_regRA_64, |
| 294 | CVT_95_addMicroMipsMemOperands, |
| 295 | CVT_95_addCOP3AsmRegOperands, |
| 296 | CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, |
| 297 | CVT_95_addConstantUImmOperands_LT_32_GT_, |
| 298 | CVT_95_addStrictlyAFGR64AsmRegOperands, |
| 299 | CVT_95_addStrictlyFGR64AsmRegOperands, |
| 300 | CVT_95_addStrictlyFGR32AsmRegOperands, |
| 301 | CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, |
| 302 | CVT_95_addRegListOperands, |
| 303 | CVT_ConvertXWPOperands, |
| 304 | CVT_regAC0, |
| 305 | CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, |
| 306 | CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, |
| 307 | CVT_95_addGPRMM16AsmRegMovePOperands, |
| 308 | CVT_95_addHI32DSPAsmRegOperands, |
| 309 | CVT_95_addLO32DSPAsmRegOperands, |
| 310 | CVT_regS0, |
| 311 | CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, |
| 312 | CVT_95_addHWRegsAsmRegOperands, |
| 313 | CVT_95_addGPRMM16AsmRegZeroOperands, |
| 314 | CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, |
| 315 | CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, |
| 316 | CVT_imm_95_2, |
| 317 | CVT_imm_95_6, |
| 318 | CVT_imm_95_4, |
| 319 | CVT_imm_95_5, |
| 320 | CVT_imm_95_31, |
| 321 | CVT_NUM_CONVERTERS |
| 322 | }; |
| 323 | |
| 324 | enum InstructionConversionKind { |
| 325 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, |
| 326 | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, |
| 327 | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, |
| 328 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, |
| 329 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, |
| 330 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, |
| 331 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| 332 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, |
| 333 | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, |
| 334 | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| 335 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| 336 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, |
| 337 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, |
| 338 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, |
| 339 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, |
| 340 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, |
| 341 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, |
| 342 | Convert__SImm161_1, |
| 343 | Convert__Reg1_0__SImm161_1, |
| 344 | Convert__Reg1_0__SImm161_2, |
| 345 | Convert__Reg1_0__Reg1_1__SImm161_2, |
| 346 | Convert__Reg1_0__Tie0_1_1__SImm161_1, |
| 347 | Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, |
| 348 | Convert__GPRMM16AsmReg1_0__Imm1_1, |
| 349 | Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, |
| 350 | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, |
| 351 | Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, |
| 352 | Convert__Imm1_0, |
| 353 | Convert__Reg1_0__Reg1_1__Reg1_2, |
| 354 | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, |
| 355 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, |
| 356 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, |
| 357 | Convert__GPR32AsmReg1_0__SImm161_1, |
| 358 | Convert__Reg1_0__Tie0_1_1__Reg1_1, |
| 359 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, |
| 360 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, |
| 361 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, |
| 362 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, |
| 363 | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, |
| 364 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, |
| 365 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, |
| 366 | Convert__regZERO__regZERO__JumpTarget1_0, |
| 367 | Convert__JumpTarget1_0, |
| 368 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, |
| 369 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, |
| 370 | Convert__regZERO__JumpTarget1_0, |
| 371 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, |
| 372 | Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, |
| 373 | Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, |
| 374 | Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, |
| 375 | Convert__FGR64AsmReg1_0__JumpTarget1_1, |
| 376 | Convert__regFCC0__JumpTarget1_0, |
| 377 | Convert__FCCAsmReg1_0__JumpTarget1_1, |
| 378 | Convert__COP2AsmReg1_0__JumpTarget1_1, |
| 379 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, |
| 380 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, |
| 381 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, |
| 382 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, |
| 383 | Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, |
| 384 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, |
| 385 | Convert__Reg1_0__JumpTarget1_1, |
| 386 | Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, |
| 387 | Convert__GPRMM16AsmReg1_0__JumpTarget1_1, |
| 388 | Convert__GPR32AsmReg1_0__JumpTarget1_1, |
| 389 | Convert__GPR64AsmReg1_0__JumpTarget1_1, |
| 390 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, |
| 391 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, |
| 392 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, |
| 393 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, |
| 394 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, |
| 395 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, |
| 396 | Convert__MSA128AsmReg1_0__JumpTarget1_1, |
| 397 | Convert__imm_95_0__imm_95_0, |
| 398 | Convert_NoOperands, |
| 399 | Convert__ConstantUImm10_01_0__imm_95_0, |
| 400 | Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, |
| 401 | Convert__ConstantUImm4_01_0, |
| 402 | Convert__SImm161_0, |
| 403 | Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, |
| 404 | Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, |
| 405 | Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, |
| 406 | Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| 407 | Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, |
| 408 | Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| 409 | Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, |
| 410 | Convert__Mem2_1__ConstantUImm5_01_0, |
| 411 | Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, |
| 412 | Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, |
| 413 | Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, |
| 414 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, |
| 415 | Convert__GPR32AsmReg1_0__CCRAsmReg1_1, |
| 416 | Convert__GPR32AsmReg1_0__COP2AsmReg1_1, |
| 417 | Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, |
| 418 | Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, |
| 419 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, |
| 420 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, |
| 421 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, |
| 422 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, |
| 423 | Convert__Reg1_0__Reg1_1, |
| 424 | Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| 425 | Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, |
| 426 | Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, |
| 427 | Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, |
| 428 | Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, |
| 429 | Convert__CCRAsmReg1_1__GPR32AsmReg1_0, |
| 430 | Convert__COP2AsmReg1_1__GPR32AsmReg1_0, |
| 431 | Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, |
| 432 | Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, |
| 433 | Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, |
| 434 | Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| 435 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, |
| 436 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, |
| 437 | Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, |
| 438 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, |
| 439 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, |
| 440 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, |
| 441 | Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, |
| 442 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, |
| 443 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, |
| 444 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, |
| 445 | Convert__regZERO, |
| 446 | Convert__GPR32AsmReg1_0, |
| 447 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, |
| 448 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, |
| 449 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, |
| 450 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, |
| 451 | Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, |
| 452 | Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, |
| 453 | Convert__Reg1_1__Reg1_2, |
| 454 | Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| 455 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, |
| 456 | Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| 457 | Convert__GPR64AsmReg1_0__Imm1_1, |
| 458 | Convert__GPR64AsmReg1_0__Mem2_1, |
| 459 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, |
| 460 | Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, |
| 461 | Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, |
| 462 | Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, |
| 463 | Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, |
| 464 | Convert__GPR64AsmReg1_0__UImm161_1, |
| 465 | Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, |
| 466 | Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, |
| 467 | Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, |
| 468 | Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, |
| 469 | Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, |
| 470 | Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, |
| 471 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, |
| 472 | Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, |
| 473 | Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, |
| 474 | Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| 475 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, |
| 476 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, |
| 477 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, |
| 478 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, |
| 479 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, |
| 480 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, |
| 481 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, |
| 482 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, |
| 483 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, |
| 484 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, |
| 485 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, |
| 486 | Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, |
| 487 | Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, |
| 488 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, |
| 489 | Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, |
| 490 | Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, |
| 491 | Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, |
| 492 | Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, |
| 493 | Convert__imm_95_0, |
| 494 | Convert__ConstantUImm10_01_0, |
| 495 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, |
| 496 | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, |
| 497 | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, |
| 498 | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, |
| 499 | Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, |
| 500 | Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, |
| 501 | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| 502 | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| 503 | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| 504 | Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| 505 | Convert__regRA__GPR32AsmReg1_0, |
| 506 | Convert__regRA_64__GPR64AsmReg1_0, |
| 507 | Convert__Reg1_0, |
| 508 | Convert__GPR32AsmReg1_0__imm_95_0, |
| 509 | Convert__GPR64AsmReg1_0__imm_95_0, |
| 510 | Convert__regZERO__GPR32AsmReg1_0, |
| 511 | Convert__GPR64AsmReg1_0, |
| 512 | Convert__regZERO_64__GPR64AsmReg1_0, |
| 513 | Convert__UImm5Lsl21_0, |
| 514 | Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, |
| 515 | Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, |
| 516 | Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, |
| 517 | Convert__GPR32AsmReg1_0__Imm1_1, |
| 518 | Convert__GPR32AsmReg1_0__Mem2_1, |
| 519 | Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, |
| 520 | Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, |
| 521 | Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, |
| 522 | Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, |
| 523 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| 524 | Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, |
| 525 | Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, |
| 526 | Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, |
| 527 | Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, |
| 528 | Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, |
| 529 | Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, |
| 530 | Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, |
| 531 | Convert__COP3AsmReg1_0__Mem2_1, |
| 532 | Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, |
| 533 | Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, |
| 534 | Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| 535 | Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| 536 | Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, |
| 537 | Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, |
| 538 | Convert__StrictlyFGR64AsmReg1_0__Imm1_1, |
| 539 | Convert__StrictlyFGR32AsmReg1_0__Imm1_1, |
| 540 | Convert__GPRMM16AsmReg1_0__UImm7_N11_1, |
| 541 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, |
| 542 | Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, |
| 543 | Convert__GPR32AsmReg1_0__UImm161_1, |
| 544 | Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, |
| 545 | Convert__Reg1_0__Imm1_1__imm_95_0, |
| 546 | Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, |
| 547 | Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, |
| 548 | Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, |
| 549 | Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, |
| 550 | Convert__RegList1_0__Mem2_1, |
| 551 | Convert__RegList161_0__MemOffsetUimm42_1, |
| 552 | ConvertCustom_ConvertXWPOperands, |
| 553 | Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, |
| 554 | Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| 555 | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, |
| 556 | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, |
| 557 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, |
| 558 | Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| 559 | Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| 560 | Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, |
| 561 | Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, |
| 562 | Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, |
| 563 | Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, |
| 564 | Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, |
| 565 | Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, |
| 566 | Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, |
| 567 | Convert__GPR32AsmReg1_0__regAC0, |
| 568 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, |
| 569 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, |
| 570 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, |
| 571 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, |
| 572 | Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, |
| 573 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| 574 | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| 575 | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| 576 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| 577 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| 578 | Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| 579 | Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| 580 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| 581 | Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, |
| 582 | Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, |
| 583 | Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, |
| 584 | Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, |
| 585 | Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, |
| 586 | Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, |
| 587 | Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, |
| 588 | Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, |
| 589 | Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, |
| 590 | Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, |
| 591 | Convert__regAC0__GPR32AsmReg1_0, |
| 592 | Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, |
| 593 | Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, |
| 594 | Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, |
| 595 | Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| 596 | Convert__regZERO__imm_95_0, |
| 597 | Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, |
| 598 | Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, |
| 599 | Convert__regZERO__regZERO__imm_95_0, |
| 600 | Convert__regZERO__regS0, |
| 601 | Convert__regZERO__regZERO, |
| 602 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, |
| 603 | Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, |
| 604 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, |
| 605 | Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, |
| 606 | Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, |
| 607 | Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, |
| 608 | Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, |
| 609 | Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, |
| 610 | Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, |
| 611 | Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, |
| 612 | Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, |
| 613 | Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, |
| 614 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, |
| 615 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, |
| 616 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, |
| 617 | Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, |
| 618 | Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, |
| 619 | Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, |
| 620 | Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, |
| 621 | Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, |
| 622 | Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, |
| 623 | Convert__ConstantUImm20_01_0, |
| 624 | Convert__Reg1_0__Tie0_1_1, |
| 625 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, |
| 626 | Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, |
| 627 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, |
| 628 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, |
| 629 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, |
| 630 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, |
| 631 | Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, |
| 632 | Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, |
| 633 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, |
| 634 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, |
| 635 | Convert__UImm161_0, |
| 636 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, |
| 637 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, |
| 638 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, |
| 639 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, |
| 640 | Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, |
| 641 | Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, |
| 642 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, |
| 643 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, |
| 644 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, |
| 645 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, |
| 646 | Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, |
| 647 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, |
| 648 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, |
| 649 | Convert__ConstantUImm5_01_0, |
| 650 | Convert__MemOffsetSimm16_02_0, |
| 651 | Convert__imm_95_2, |
| 652 | Convert__imm_95_6, |
| 653 | Convert__imm_95_4, |
| 654 | Convert__imm_95_5, |
| 655 | Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, |
| 656 | Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, |
| 657 | Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, |
| 658 | Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, |
| 659 | Convert__GPR32AsmReg1_0__imm_95_31, |
| 660 | CVT_NUM_SIGNATURES |
| 661 | }; |
| 662 | |
| 663 | } // end anonymous namespace |
| 664 | |
| 665 | static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { |
| 666 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1 |
| 667 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 668 | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1 |
| 669 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| 670 | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1 |
| 671 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| 672 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1 |
| 673 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| 674 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1 |
| 675 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 676 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1 |
| 677 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
| 678 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| 679 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 680 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2 |
| 681 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
| 682 | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 |
| 683 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, |
| 684 | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| 685 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| 686 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| 687 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| 688 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1 |
| 689 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| 690 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2 |
| 691 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, |
| 692 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1 |
| 693 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 694 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1 |
| 695 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 696 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2 |
| 697 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 698 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2 |
| 699 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 700 | // Convert__SImm161_1 |
| 701 | { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 702 | // Convert__Reg1_0__SImm161_1 |
| 703 | { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 704 | // Convert__Reg1_0__SImm161_2 |
| 705 | { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 706 | // Convert__Reg1_0__Reg1_1__SImm161_2 |
| 707 | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 708 | // Convert__Reg1_0__Tie0_1_1__SImm161_1 |
| 709 | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 710 | // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1 |
| 711 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 712 | // Convert__GPRMM16AsmReg1_0__Imm1_1 |
| 713 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 714 | // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1 |
| 715 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 716 | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2 |
| 717 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 718 | // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1 |
| 719 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done }, |
| 720 | // Convert__Imm1_0 |
| 721 | { CVT_95_addImmOperands, 1, CVT_Done }, |
| 722 | // Convert__Reg1_0__Reg1_1__Reg1_2 |
| 723 | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
| 724 | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2 |
| 725 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done }, |
| 726 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2 |
| 727 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 728 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3 |
| 729 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| 730 | // Convert__GPR32AsmReg1_0__SImm161_1 |
| 731 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 732 | // Convert__Reg1_0__Tie0_1_1__Reg1_1 |
| 733 | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, |
| 734 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1 |
| 735 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 736 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1 |
| 737 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 738 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2 |
| 739 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 740 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2 |
| 741 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 742 | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1 |
| 743 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 744 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2 |
| 745 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
| 746 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1 |
| 747 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 748 | // Convert__regZERO__regZERO__JumpTarget1_0 |
| 749 | { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
| 750 | // Convert__JumpTarget1_0 |
| 751 | { CVT_95_addImmOperands, 1, CVT_Done }, |
| 752 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1 |
| 753 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| 754 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2 |
| 755 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
| 756 | // Convert__regZERO__JumpTarget1_0 |
| 757 | { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
| 758 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1 |
| 759 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 760 | // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2 |
| 761 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 762 | // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2 |
| 763 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 764 | // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2 |
| 765 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 766 | // Convert__FGR64AsmReg1_0__JumpTarget1_1 |
| 767 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 768 | // Convert__regFCC0__JumpTarget1_0 |
| 769 | { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
| 770 | // Convert__FCCAsmReg1_0__JumpTarget1_1 |
| 771 | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 772 | // Convert__COP2AsmReg1_0__JumpTarget1_1 |
| 773 | { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 774 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2 |
| 775 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 776 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2 |
| 777 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
| 778 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2 |
| 779 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| 780 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2 |
| 781 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 782 | // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2 |
| 783 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 784 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2 |
| 785 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 786 | // Convert__Reg1_0__JumpTarget1_1 |
| 787 | { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 788 | // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1 |
| 789 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done }, |
| 790 | // Convert__GPRMM16AsmReg1_0__JumpTarget1_1 |
| 791 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 792 | // Convert__GPR32AsmReg1_0__JumpTarget1_1 |
| 793 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 794 | // Convert__GPR64AsmReg1_0__JumpTarget1_1 |
| 795 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 796 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2 |
| 797 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, |
| 798 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2 |
| 799 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 800 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2 |
| 801 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
| 802 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2 |
| 803 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| 804 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2 |
| 805 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 806 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2 |
| 807 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
| 808 | // Convert__MSA128AsmReg1_0__JumpTarget1_1 |
| 809 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 810 | // Convert__imm_95_0__imm_95_0 |
| 811 | { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, |
| 812 | // Convert_NoOperands |
| 813 | { CVT_Done }, |
| 814 | // Convert__ConstantUImm10_01_0__imm_95_0 |
| 815 | { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 816 | // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1 |
| 817 | { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| 818 | // Convert__ConstantUImm4_01_0 |
| 819 | { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done }, |
| 820 | // Convert__SImm161_0 |
| 821 | { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done }, |
| 822 | // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1 |
| 823 | { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| 824 | // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1 |
| 825 | { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| 826 | // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 |
| 827 | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, |
| 828 | // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| 829 | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| 830 | // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1 |
| 831 | { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| 832 | // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| 833 | { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| 834 | // Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0 |
| 835 | { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| 836 | // Convert__Mem2_1__ConstantUImm5_01_0 |
| 837 | { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| 838 | // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1 |
| 839 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| 840 | // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1 |
| 841 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| 842 | // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1 |
| 843 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| 844 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2 |
| 845 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 846 | // Convert__GPR32AsmReg1_0__CCRAsmReg1_1 |
| 847 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done }, |
| 848 | // Convert__GPR32AsmReg1_0__COP2AsmReg1_1 |
| 849 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done }, |
| 850 | // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1 |
| 851 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done }, |
| 852 | // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1 |
| 853 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| 854 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2 |
| 855 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 856 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2 |
| 857 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 858 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3 |
| 859 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, |
| 860 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3 |
| 861 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, |
| 862 | // Convert__Reg1_0__Reg1_1 |
| 863 | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, |
| 864 | // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| 865 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| 866 | // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 |
| 867 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
| 868 | // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 |
| 869 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
| 870 | // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 |
| 871 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| 872 | // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 |
| 873 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| 874 | // Convert__CCRAsmReg1_1__GPR32AsmReg1_0 |
| 875 | { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 876 | // Convert__COP2AsmReg1_1__GPR32AsmReg1_0 |
| 877 | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 878 | // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1 |
| 879 | { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 880 | // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0 |
| 881 | { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 882 | // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1 |
| 883 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| 884 | // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| 885 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| 886 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1 |
| 887 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 888 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2 |
| 889 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 890 | // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2 |
| 891 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 892 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3 |
| 893 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| 894 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2 |
| 895 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, |
| 896 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1 |
| 897 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| 898 | // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2 |
| 899 | { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
| 900 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3 |
| 901 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done }, |
| 902 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3 |
| 903 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
| 904 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3 |
| 905 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
| 906 | // Convert__regZERO |
| 907 | { CVT_regZERO, 0, CVT_Done }, |
| 908 | // Convert__GPR32AsmReg1_0 |
| 909 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 910 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1 |
| 911 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 912 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1 |
| 913 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 914 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1 |
| 915 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 916 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1 |
| 917 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
| 918 | // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1 |
| 919 | { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 920 | // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1 |
| 921 | { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 922 | // Convert__Reg1_1__Reg1_2 |
| 923 | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
| 924 | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| 925 | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 926 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2 |
| 927 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
| 928 | // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| 929 | { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 930 | // Convert__GPR64AsmReg1_0__Imm1_1 |
| 931 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 932 | // Convert__GPR64AsmReg1_0__Mem2_1 |
| 933 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 934 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3 |
| 935 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
| 936 | // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0 |
| 937 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 938 | // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 |
| 939 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 940 | // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1 |
| 941 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| 942 | // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0 |
| 943 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 944 | // Convert__GPR64AsmReg1_0__UImm161_1 |
| 945 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 946 | // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 |
| 947 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 948 | // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0 |
| 949 | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 950 | // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 |
| 951 | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 952 | // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0 |
| 953 | { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| 954 | // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0 |
| 955 | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 956 | // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 |
| 957 | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 958 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2 |
| 959 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
| 960 | // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0 |
| 961 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| 962 | // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1 |
| 963 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| 964 | // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| 965 | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 966 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0 |
| 967 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| 968 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1 |
| 969 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
| 970 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1 |
| 971 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done }, |
| 972 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2 |
| 973 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
| 974 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1 |
| 975 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, |
| 976 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2 |
| 977 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 978 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2 |
| 979 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 980 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1 |
| 981 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 982 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1 |
| 983 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 984 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2 |
| 985 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 986 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3 |
| 987 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
| 988 | // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2 |
| 989 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 990 | // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2 |
| 991 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 992 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1 |
| 993 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done }, |
| 994 | // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1 |
| 995 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 996 | // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1 |
| 997 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| 998 | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2 |
| 999 | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 1000 | // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1 |
| 1001 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done }, |
| 1002 | // Convert__imm_95_0 |
| 1003 | { CVT_imm_95_0, 0, CVT_Done }, |
| 1004 | // Convert__ConstantUImm10_01_0 |
| 1005 | { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done }, |
| 1006 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1 |
| 1007 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1008 | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2 |
| 1009 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| 1010 | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2 |
| 1011 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done }, |
| 1012 | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2 |
| 1013 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1014 | // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2 |
| 1015 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done }, |
| 1016 | // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1 |
| 1017 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1018 | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| 1019 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| 1020 | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| 1021 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| 1022 | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| 1023 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| 1024 | // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| 1025 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| 1026 | // Convert__regRA__GPR32AsmReg1_0 |
| 1027 | { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1028 | // Convert__regRA_64__GPR64AsmReg1_0 |
| 1029 | { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| 1030 | // Convert__Reg1_0 |
| 1031 | { CVT_95_Reg, 1, CVT_Done }, |
| 1032 | // Convert__GPR32AsmReg1_0__imm_95_0 |
| 1033 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 1034 | // Convert__GPR64AsmReg1_0__imm_95_0 |
| 1035 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 1036 | // Convert__regZERO__GPR32AsmReg1_0 |
| 1037 | { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1038 | // Convert__GPR64AsmReg1_0 |
| 1039 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| 1040 | // Convert__regZERO_64__GPR64AsmReg1_0 |
| 1041 | { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| 1042 | // Convert__UImm5Lsl21_0 |
| 1043 | { CVT_95_addImmOperands, 1, CVT_Done }, |
| 1044 | // Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1 |
| 1045 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1046 | // Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1 |
| 1047 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1048 | // Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1 |
| 1049 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1050 | // Convert__GPR32AsmReg1_0__Imm1_1 |
| 1051 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 1052 | // Convert__GPR32AsmReg1_0__Mem2_1 |
| 1053 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1054 | // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1 |
| 1055 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1056 | // Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1 |
| 1057 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1058 | // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1 |
| 1059 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1060 | // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1 |
| 1061 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, |
| 1062 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| 1063 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1064 | // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1 |
| 1065 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1066 | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1 |
| 1067 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1068 | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1 |
| 1069 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1070 | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1 |
| 1071 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1072 | // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1 |
| 1073 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1074 | // Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1 |
| 1075 | { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1076 | // Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1 |
| 1077 | { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1078 | // Convert__COP3AsmReg1_0__Mem2_1 |
| 1079 | { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1080 | // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1 |
| 1081 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| 1082 | // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1 |
| 1083 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1084 | // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| 1085 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1086 | // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| 1087 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1088 | // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1 |
| 1089 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, |
| 1090 | // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1 |
| 1091 | { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 1092 | // Convert__StrictlyFGR64AsmReg1_0__Imm1_1 |
| 1093 | { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 1094 | // Convert__StrictlyFGR32AsmReg1_0__Imm1_1 |
| 1095 | { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 1096 | // Convert__GPRMM16AsmReg1_0__UImm7_N11_1 |
| 1097 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done }, |
| 1098 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3 |
| 1099 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
| 1100 | // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3 |
| 1101 | { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
| 1102 | // Convert__GPR32AsmReg1_0__UImm161_1 |
| 1103 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 1104 | // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1 |
| 1105 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| 1106 | // Convert__Reg1_0__Imm1_1__imm_95_0 |
| 1107 | { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 1108 | // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1 |
| 1109 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1110 | // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1 |
| 1111 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1112 | // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1 |
| 1113 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1114 | // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1 |
| 1115 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1116 | // Convert__RegList1_0__Mem2_1 |
| 1117 | { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1118 | // Convert__RegList161_0__MemOffsetUimm42_1 |
| 1119 | { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1120 | // ConvertCustom_ConvertXWPOperands |
| 1121 | { CVT_ConvertXWPOperands, 0, CVT_Done }, |
| 1122 | // Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1 |
| 1123 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1124 | // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| 1125 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1126 | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3 |
| 1127 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done }, |
| 1128 | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3 |
| 1129 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done }, |
| 1130 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3 |
| 1131 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done }, |
| 1132 | // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| 1133 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| 1134 | // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| 1135 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| 1136 | // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0 |
| 1137 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 1138 | // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 |
| 1139 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1140 | // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1 |
| 1141 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| 1142 | // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0 |
| 1143 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 1144 | // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 |
| 1145 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1146 | // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1 |
| 1147 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| 1148 | // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1 |
| 1149 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done }, |
| 1150 | // Convert__GPR32AsmReg1_0__regAC0 |
| 1151 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done }, |
| 1152 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0 |
| 1153 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 1154 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 |
| 1155 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, |
| 1156 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO |
| 1157 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done }, |
| 1158 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64 |
| 1159 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done }, |
| 1160 | // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3 |
| 1161 | { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done }, |
| 1162 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| 1163 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1164 | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| 1165 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1166 | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| 1167 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1168 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| 1169 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1170 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| 1171 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1172 | // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| 1173 | { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1174 | // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| 1175 | { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1176 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| 1177 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1178 | // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0 |
| 1179 | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 1180 | // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 |
| 1181 | { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1182 | // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0 |
| 1183 | { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1184 | // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0 |
| 1185 | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| 1186 | // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 |
| 1187 | { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1188 | // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 |
| 1189 | { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1190 | // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 |
| 1191 | { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1192 | // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0 |
| 1193 | { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1194 | // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1 |
| 1195 | { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1196 | // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0 |
| 1197 | { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1198 | // Convert__regAC0__GPR32AsmReg1_0 |
| 1199 | { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1200 | // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0 |
| 1201 | { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1202 | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0 |
| 1203 | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1204 | // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 |
| 1205 | { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, |
| 1206 | // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| 1207 | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 1208 | // Convert__regZERO__imm_95_0 |
| 1209 | { CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done }, |
| 1210 | // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0 |
| 1211 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1212 | // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1 |
| 1213 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1214 | // Convert__regZERO__regZERO__imm_95_0 |
| 1215 | { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done }, |
| 1216 | // Convert__regZERO__regS0 |
| 1217 | { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done }, |
| 1218 | // Convert__regZERO__regZERO |
| 1219 | { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done }, |
| 1220 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO |
| 1221 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done }, |
| 1222 | // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1 |
| 1223 | { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done }, |
| 1224 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0 |
| 1225 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1226 | // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0 |
| 1227 | { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| 1228 | // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1 |
| 1229 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done }, |
| 1230 | // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1 |
| 1231 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| 1232 | // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 |
| 1233 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 1234 | // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 |
| 1235 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| 1236 | // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2 |
| 1237 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1238 | // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2 |
| 1239 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
| 1240 | // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1 |
| 1241 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| 1242 | // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1 |
| 1243 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done }, |
| 1244 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1 |
| 1245 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, |
| 1246 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2 |
| 1247 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 1248 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_2 |
| 1249 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
| 1250 | // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1 |
| 1251 | { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, |
| 1252 | // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1 |
| 1253 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1254 | // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1 |
| 1255 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1256 | // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1 |
| 1257 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1258 | // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1 |
| 1259 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1260 | // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1 |
| 1261 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| 1262 | // Convert__ConstantUImm20_01_0 |
| 1263 | { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done }, |
| 1264 | // Convert__Reg1_0__Tie0_1_1 |
| 1265 | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1266 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1 |
| 1267 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| 1268 | // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2 |
| 1269 | { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, |
| 1270 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1 |
| 1271 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, |
| 1272 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2 |
| 1273 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done }, |
| 1274 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0 |
| 1275 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| 1276 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1 |
| 1277 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| 1278 | // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1 |
| 1279 | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1280 | // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1 |
| 1281 | { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| 1282 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2 |
| 1283 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| 1284 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2 |
| 1285 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| 1286 | // Convert__UImm161_0 |
| 1287 | { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done }, |
| 1288 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3 |
| 1289 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, |
| 1290 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3 |
| 1291 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
| 1292 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3 |
| 1293 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
| 1294 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3 |
| 1295 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| 1296 | // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3 |
| 1297 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| 1298 | // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2 |
| 1299 | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| 1300 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3 |
| 1301 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, |
| 1302 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 |
| 1303 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
| 1304 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 |
| 1305 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
| 1306 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 |
| 1307 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| 1308 | // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 |
| 1309 | { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| 1310 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1 |
| 1311 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| 1312 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2 |
| 1313 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| 1314 | // Convert__ConstantUImm5_01_0 |
| 1315 | { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| 1316 | // Convert__MemOffsetSimm16_02_0 |
| 1317 | { CVT_95_addMemOperands, 1, CVT_Done }, |
| 1318 | // Convert__imm_95_2 |
| 1319 | { CVT_imm_95_2, 0, CVT_Done }, |
| 1320 | // Convert__imm_95_6 |
| 1321 | { CVT_imm_95_6, 0, CVT_Done }, |
| 1322 | // Convert__imm_95_4 |
| 1323 | { CVT_imm_95_4, 0, CVT_Done }, |
| 1324 | // Convert__imm_95_5 |
| 1325 | { CVT_imm_95_5, 0, CVT_Done }, |
| 1326 | // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2 |
| 1327 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, |
| 1328 | // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2 |
| 1329 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 1330 | // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2 |
| 1331 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 1332 | // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2 |
| 1333 | { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| 1334 | // Convert__GPR32AsmReg1_0__imm_95_31 |
| 1335 | { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done }, |
| 1336 | }; |
| 1337 | |
| 1338 | void MipsAsmParser:: |
| 1339 | convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
| 1340 | const OperandVector &Operands) { |
| 1341 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
| 1342 | const uint8_t *Converter = ConversionTable[Kind]; |
| 1343 | Inst.setOpcode(Opcode); |
| 1344 | for (const uint8_t *p = Converter; *p; p += 2) { |
| 1345 | unsigned OpIdx = *(p + 1); |
| 1346 | switch (*p) { |
| 1347 | default: llvm_unreachable("invalid conversion entry!"); |
| 1348 | case CVT_Reg: |
| 1349 | static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
| 1350 | break; |
| 1351 | case CVT_Tied: { |
| 1352 | assert(*(p + 1) < (size_t)(std::end(TiedAsmOperandTable) - |
| 1353 | std::begin(TiedAsmOperandTable)) && |
| 1354 | "Tied operand not found"); |
| 1355 | unsigned TiedResOpnd = TiedAsmOperandTable[*(p + 1)][0]; |
| 1356 | if (TiedResOpnd != (uint8_t)-1) |
| 1357 | Inst.addOperand(Inst.getOperand(TiedResOpnd)); |
| 1358 | break; |
| 1359 | } |
| 1360 | case CVT_95_addGPR32AsmRegOperands: |
| 1361 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1); |
| 1362 | break; |
| 1363 | case CVT_95_addAFGR64AsmRegOperands: |
| 1364 | static_cast<MipsOperand &>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1); |
| 1365 | break; |
| 1366 | case CVT_95_addFGR64AsmRegOperands: |
| 1367 | static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1); |
| 1368 | break; |
| 1369 | case CVT_95_addFGR32AsmRegOperands: |
| 1370 | static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1); |
| 1371 | break; |
| 1372 | case CVT_95_addSImmOperands_LT_32_GT_: |
| 1373 | static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1); |
| 1374 | break; |
| 1375 | case CVT_95_addMSA128AsmRegOperands: |
| 1376 | static_cast<MipsOperand &>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1); |
| 1377 | break; |
| 1378 | case CVT_95_addSImmOperands_LT_16_GT_: |
| 1379 | static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1); |
| 1380 | break; |
| 1381 | case CVT_95_Reg: |
| 1382 | static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
| 1383 | break; |
| 1384 | case CVT_95_addImmOperands: |
| 1385 | static_cast<MipsOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1); |
| 1386 | break; |
| 1387 | case CVT_95_addGPRMM16AsmRegOperands: |
| 1388 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1); |
| 1389 | break; |
| 1390 | case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: |
| 1391 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1); |
| 1392 | break; |
| 1393 | case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: |
| 1394 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1); |
| 1395 | break; |
| 1396 | case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: |
| 1397 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1); |
| 1398 | break; |
| 1399 | case CVT_95_addUImmOperands_LT_16_GT_: |
| 1400 | static_cast<MipsOperand &>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1); |
| 1401 | break; |
| 1402 | case CVT_95_addGPR64AsmRegOperands: |
| 1403 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1); |
| 1404 | break; |
| 1405 | case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: |
| 1406 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1); |
| 1407 | break; |
| 1408 | case CVT_regZERO: |
| 1409 | Inst.addOperand(MCOperand::createReg(Mips::ZERO)); |
| 1410 | break; |
| 1411 | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: |
| 1412 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1); |
| 1413 | break; |
| 1414 | case CVT_regFCC0: |
| 1415 | Inst.addOperand(MCOperand::createReg(Mips::FCC0)); |
| 1416 | break; |
| 1417 | case CVT_95_addFCCAsmRegOperands: |
| 1418 | static_cast<MipsOperand &>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1); |
| 1419 | break; |
| 1420 | case CVT_95_addCOP2AsmRegOperands: |
| 1421 | static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1); |
| 1422 | break; |
| 1423 | case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: |
| 1424 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1); |
| 1425 | break; |
| 1426 | case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: |
| 1427 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1); |
| 1428 | break; |
| 1429 | case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: |
| 1430 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1); |
| 1431 | break; |
| 1432 | case CVT_imm_95_0: |
| 1433 | Inst.addOperand(MCOperand::createImm(0)); |
| 1434 | break; |
| 1435 | case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: |
| 1436 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1); |
| 1437 | break; |
| 1438 | case CVT_95_addMemOperands: |
| 1439 | static_cast<MipsOperand &>(*Operands[OpIdx]).addMemOperands(Inst, 2); |
| 1440 | break; |
| 1441 | case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: |
| 1442 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1); |
| 1443 | break; |
| 1444 | case CVT_95_addCCRAsmRegOperands: |
| 1445 | static_cast<MipsOperand &>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1); |
| 1446 | break; |
| 1447 | case CVT_95_addMSACtrlAsmRegOperands: |
| 1448 | static_cast<MipsOperand &>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1); |
| 1449 | break; |
| 1450 | case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: |
| 1451 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1); |
| 1452 | break; |
| 1453 | case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: |
| 1454 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1); |
| 1455 | break; |
| 1456 | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: |
| 1457 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1); |
| 1458 | break; |
| 1459 | case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: |
| 1460 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1); |
| 1461 | break; |
| 1462 | case CVT_95_addGPR32NonZeroAsmRegOperands: |
| 1463 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1); |
| 1464 | break; |
| 1465 | case CVT_95_addGPR32ZeroAsmRegOperands: |
| 1466 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1); |
| 1467 | break; |
| 1468 | case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: |
| 1469 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1); |
| 1470 | break; |
| 1471 | case CVT_95_addCOP0AsmRegOperands: |
| 1472 | static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1); |
| 1473 | break; |
| 1474 | case CVT_regZERO_64: |
| 1475 | Inst.addOperand(MCOperand::createReg(Mips::ZERO_64)); |
| 1476 | break; |
| 1477 | case CVT_95_addACC64DSPAsmRegOperands: |
| 1478 | static_cast<MipsOperand &>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1); |
| 1479 | break; |
| 1480 | case CVT_95_addConstantUImmOperands_LT_1_GT_: |
| 1481 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1); |
| 1482 | break; |
| 1483 | case CVT_regRA: |
| 1484 | Inst.addOperand(MCOperand::createReg(Mips::RA)); |
| 1485 | break; |
| 1486 | case CVT_regRA_64: |
| 1487 | Inst.addOperand(MCOperand::createReg(Mips::RA_64)); |
| 1488 | break; |
| 1489 | case CVT_95_addMicroMipsMemOperands: |
| 1490 | static_cast<MipsOperand &>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2); |
| 1491 | break; |
| 1492 | case CVT_95_addCOP3AsmRegOperands: |
| 1493 | static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1); |
| 1494 | break; |
| 1495 | case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: |
| 1496 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1); |
| 1497 | break; |
| 1498 | case CVT_95_addConstantUImmOperands_LT_32_GT_: |
| 1499 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1); |
| 1500 | break; |
| 1501 | case CVT_95_addStrictlyAFGR64AsmRegOperands: |
| 1502 | static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1); |
| 1503 | break; |
| 1504 | case CVT_95_addStrictlyFGR64AsmRegOperands: |
| 1505 | static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1); |
| 1506 | break; |
| 1507 | case CVT_95_addStrictlyFGR32AsmRegOperands: |
| 1508 | static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1); |
| 1509 | break; |
| 1510 | case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: |
| 1511 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1); |
| 1512 | break; |
| 1513 | case CVT_95_addRegListOperands: |
| 1514 | static_cast<MipsOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1); |
| 1515 | break; |
| 1516 | case CVT_ConvertXWPOperands: |
| 1517 | ConvertXWPOperands(Inst, Operands); |
| 1518 | break; |
| 1519 | case CVT_regAC0: |
| 1520 | Inst.addOperand(MCOperand::createReg(Mips::AC0)); |
| 1521 | break; |
| 1522 | case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: |
| 1523 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1); |
| 1524 | break; |
| 1525 | case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: |
| 1526 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1); |
| 1527 | break; |
| 1528 | case CVT_95_addGPRMM16AsmRegMovePOperands: |
| 1529 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1); |
| 1530 | break; |
| 1531 | case CVT_95_addHI32DSPAsmRegOperands: |
| 1532 | static_cast<MipsOperand &>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1); |
| 1533 | break; |
| 1534 | case CVT_95_addLO32DSPAsmRegOperands: |
| 1535 | static_cast<MipsOperand &>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1); |
| 1536 | break; |
| 1537 | case CVT_regS0: |
| 1538 | Inst.addOperand(MCOperand::createReg(Mips::S0)); |
| 1539 | break; |
| 1540 | case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: |
| 1541 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1); |
| 1542 | break; |
| 1543 | case CVT_95_addHWRegsAsmRegOperands: |
| 1544 | static_cast<MipsOperand &>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1); |
| 1545 | break; |
| 1546 | case CVT_95_addGPRMM16AsmRegZeroOperands: |
| 1547 | static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1); |
| 1548 | break; |
| 1549 | case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: |
| 1550 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1); |
| 1551 | break; |
| 1552 | case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: |
| 1553 | static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1); |
| 1554 | break; |
| 1555 | case CVT_imm_95_2: |
| 1556 | Inst.addOperand(MCOperand::createImm(2)); |
| 1557 | break; |
| 1558 | case CVT_imm_95_6: |
| 1559 | Inst.addOperand(MCOperand::createImm(6)); |
| 1560 | break; |
| 1561 | case CVT_imm_95_4: |
| 1562 | Inst.addOperand(MCOperand::createImm(4)); |
| 1563 | break; |
| 1564 | case CVT_imm_95_5: |
| 1565 | Inst.addOperand(MCOperand::createImm(5)); |
| 1566 | break; |
| 1567 | case CVT_imm_95_31: |
| 1568 | Inst.addOperand(MCOperand::createImm(31)); |
| 1569 | break; |
| 1570 | } |
| 1571 | } |
| 1572 | } |
| 1573 | |
| 1574 | void MipsAsmParser:: |
| 1575 | convertToMapAndConstraints(unsigned Kind, |
| 1576 | const OperandVector &Operands) { |
| 1577 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
| 1578 | unsigned NumMCOperands = 0; |
| 1579 | const uint8_t *Converter = ConversionTable[Kind]; |
| 1580 | for (const uint8_t *p = Converter; *p; p += 2) { |
| 1581 | switch (*p) { |
| 1582 | default: llvm_unreachable("invalid conversion entry!"); |
| 1583 | case CVT_Reg: |
| 1584 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1585 | Operands[*(p + 1)]->setConstraint("r"); |
| 1586 | ++NumMCOperands; |
| 1587 | break; |
| 1588 | case CVT_Tied: |
| 1589 | ++NumMCOperands; |
| 1590 | break; |
| 1591 | case CVT_95_addGPR32AsmRegOperands: |
| 1592 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1593 | Operands[*(p + 1)]->setConstraint("m"); |
| 1594 | NumMCOperands += 1; |
| 1595 | break; |
| 1596 | case CVT_95_addAFGR64AsmRegOperands: |
| 1597 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1598 | Operands[*(p + 1)]->setConstraint("m"); |
| 1599 | NumMCOperands += 1; |
| 1600 | break; |
| 1601 | case CVT_95_addFGR64AsmRegOperands: |
| 1602 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1603 | Operands[*(p + 1)]->setConstraint("m"); |
| 1604 | NumMCOperands += 1; |
| 1605 | break; |
| 1606 | case CVT_95_addFGR32AsmRegOperands: |
| 1607 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1608 | Operands[*(p + 1)]->setConstraint("m"); |
| 1609 | NumMCOperands += 1; |
| 1610 | break; |
| 1611 | case CVT_95_addSImmOperands_LT_32_GT_: |
| 1612 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1613 | Operands[*(p + 1)]->setConstraint("m"); |
| 1614 | NumMCOperands += 1; |
| 1615 | break; |
| 1616 | case CVT_95_addMSA128AsmRegOperands: |
| 1617 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1618 | Operands[*(p + 1)]->setConstraint("m"); |
| 1619 | NumMCOperands += 1; |
| 1620 | break; |
| 1621 | case CVT_95_addSImmOperands_LT_16_GT_: |
| 1622 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1623 | Operands[*(p + 1)]->setConstraint("m"); |
| 1624 | NumMCOperands += 1; |
| 1625 | break; |
| 1626 | case CVT_95_Reg: |
| 1627 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1628 | Operands[*(p + 1)]->setConstraint("r"); |
| 1629 | NumMCOperands += 1; |
| 1630 | break; |
| 1631 | case CVT_95_addImmOperands: |
| 1632 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1633 | Operands[*(p + 1)]->setConstraint("m"); |
| 1634 | NumMCOperands += 1; |
| 1635 | break; |
| 1636 | case CVT_95_addGPRMM16AsmRegOperands: |
| 1637 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1638 | Operands[*(p + 1)]->setConstraint("m"); |
| 1639 | NumMCOperands += 1; |
| 1640 | break; |
| 1641 | case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: |
| 1642 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1643 | Operands[*(p + 1)]->setConstraint("m"); |
| 1644 | NumMCOperands += 1; |
| 1645 | break; |
| 1646 | case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: |
| 1647 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1648 | Operands[*(p + 1)]->setConstraint("m"); |
| 1649 | NumMCOperands += 1; |
| 1650 | break; |
| 1651 | case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: |
| 1652 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1653 | Operands[*(p + 1)]->setConstraint("m"); |
| 1654 | NumMCOperands += 1; |
| 1655 | break; |
| 1656 | case CVT_95_addUImmOperands_LT_16_GT_: |
| 1657 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1658 | Operands[*(p + 1)]->setConstraint("m"); |
| 1659 | NumMCOperands += 1; |
| 1660 | break; |
| 1661 | case CVT_95_addGPR64AsmRegOperands: |
| 1662 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1663 | Operands[*(p + 1)]->setConstraint("m"); |
| 1664 | NumMCOperands += 1; |
| 1665 | break; |
| 1666 | case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: |
| 1667 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1668 | Operands[*(p + 1)]->setConstraint("m"); |
| 1669 | NumMCOperands += 1; |
| 1670 | break; |
| 1671 | case CVT_regZERO: |
| 1672 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1673 | Operands[*(p + 1)]->setConstraint("m"); |
| 1674 | ++NumMCOperands; |
| 1675 | break; |
| 1676 | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: |
| 1677 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1678 | Operands[*(p + 1)]->setConstraint("m"); |
| 1679 | NumMCOperands += 1; |
| 1680 | break; |
| 1681 | case CVT_regFCC0: |
| 1682 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1683 | Operands[*(p + 1)]->setConstraint("m"); |
| 1684 | ++NumMCOperands; |
| 1685 | break; |
| 1686 | case CVT_95_addFCCAsmRegOperands: |
| 1687 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1688 | Operands[*(p + 1)]->setConstraint("m"); |
| 1689 | NumMCOperands += 1; |
| 1690 | break; |
| 1691 | case CVT_95_addCOP2AsmRegOperands: |
| 1692 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1693 | Operands[*(p + 1)]->setConstraint("m"); |
| 1694 | NumMCOperands += 1; |
| 1695 | break; |
| 1696 | case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: |
| 1697 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1698 | Operands[*(p + 1)]->setConstraint("m"); |
| 1699 | NumMCOperands += 1; |
| 1700 | break; |
| 1701 | case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: |
| 1702 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1703 | Operands[*(p + 1)]->setConstraint("m"); |
| 1704 | NumMCOperands += 1; |
| 1705 | break; |
| 1706 | case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: |
| 1707 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1708 | Operands[*(p + 1)]->setConstraint("m"); |
| 1709 | NumMCOperands += 1; |
| 1710 | break; |
| 1711 | case CVT_imm_95_0: |
| 1712 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1713 | Operands[*(p + 1)]->setConstraint(""); |
| 1714 | ++NumMCOperands; |
| 1715 | break; |
| 1716 | case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: |
| 1717 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1718 | Operands[*(p + 1)]->setConstraint("m"); |
| 1719 | NumMCOperands += 1; |
| 1720 | break; |
| 1721 | case CVT_95_addMemOperands: |
| 1722 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1723 | Operands[*(p + 1)]->setConstraint("m"); |
| 1724 | NumMCOperands += 2; |
| 1725 | break; |
| 1726 | case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: |
| 1727 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1728 | Operands[*(p + 1)]->setConstraint("m"); |
| 1729 | NumMCOperands += 1; |
| 1730 | break; |
| 1731 | case CVT_95_addCCRAsmRegOperands: |
| 1732 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1733 | Operands[*(p + 1)]->setConstraint("m"); |
| 1734 | NumMCOperands += 1; |
| 1735 | break; |
| 1736 | case CVT_95_addMSACtrlAsmRegOperands: |
| 1737 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1738 | Operands[*(p + 1)]->setConstraint("m"); |
| 1739 | NumMCOperands += 1; |
| 1740 | break; |
| 1741 | case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: |
| 1742 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1743 | Operands[*(p + 1)]->setConstraint("m"); |
| 1744 | NumMCOperands += 1; |
| 1745 | break; |
| 1746 | case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: |
| 1747 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1748 | Operands[*(p + 1)]->setConstraint("m"); |
| 1749 | NumMCOperands += 1; |
| 1750 | break; |
| 1751 | case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: |
| 1752 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1753 | Operands[*(p + 1)]->setConstraint("m"); |
| 1754 | NumMCOperands += 1; |
| 1755 | break; |
| 1756 | case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: |
| 1757 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1758 | Operands[*(p + 1)]->setConstraint("m"); |
| 1759 | NumMCOperands += 1; |
| 1760 | break; |
| 1761 | case CVT_95_addGPR32NonZeroAsmRegOperands: |
| 1762 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1763 | Operands[*(p + 1)]->setConstraint("m"); |
| 1764 | NumMCOperands += 1; |
| 1765 | break; |
| 1766 | case CVT_95_addGPR32ZeroAsmRegOperands: |
| 1767 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1768 | Operands[*(p + 1)]->setConstraint("m"); |
| 1769 | NumMCOperands += 1; |
| 1770 | break; |
| 1771 | case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: |
| 1772 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1773 | Operands[*(p + 1)]->setConstraint("m"); |
| 1774 | NumMCOperands += 1; |
| 1775 | break; |
| 1776 | case CVT_95_addCOP0AsmRegOperands: |
| 1777 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1778 | Operands[*(p + 1)]->setConstraint("m"); |
| 1779 | NumMCOperands += 1; |
| 1780 | break; |
| 1781 | case CVT_regZERO_64: |
| 1782 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1783 | Operands[*(p + 1)]->setConstraint("m"); |
| 1784 | ++NumMCOperands; |
| 1785 | break; |
| 1786 | case CVT_95_addACC64DSPAsmRegOperands: |
| 1787 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1788 | Operands[*(p + 1)]->setConstraint("m"); |
| 1789 | NumMCOperands += 1; |
| 1790 | break; |
| 1791 | case CVT_95_addConstantUImmOperands_LT_1_GT_: |
| 1792 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1793 | Operands[*(p + 1)]->setConstraint("m"); |
| 1794 | NumMCOperands += 1; |
| 1795 | break; |
| 1796 | case CVT_regRA: |
| 1797 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1798 | Operands[*(p + 1)]->setConstraint("m"); |
| 1799 | ++NumMCOperands; |
| 1800 | break; |
| 1801 | case CVT_regRA_64: |
| 1802 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1803 | Operands[*(p + 1)]->setConstraint("m"); |
| 1804 | ++NumMCOperands; |
| 1805 | break; |
| 1806 | case CVT_95_addMicroMipsMemOperands: |
| 1807 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1808 | Operands[*(p + 1)]->setConstraint("m"); |
| 1809 | NumMCOperands += 2; |
| 1810 | break; |
| 1811 | case CVT_95_addCOP3AsmRegOperands: |
| 1812 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1813 | Operands[*(p + 1)]->setConstraint("m"); |
| 1814 | NumMCOperands += 1; |
| 1815 | break; |
| 1816 | case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: |
| 1817 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1818 | Operands[*(p + 1)]->setConstraint("m"); |
| 1819 | NumMCOperands += 1; |
| 1820 | break; |
| 1821 | case CVT_95_addConstantUImmOperands_LT_32_GT_: |
| 1822 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1823 | Operands[*(p + 1)]->setConstraint("m"); |
| 1824 | NumMCOperands += 1; |
| 1825 | break; |
| 1826 | case CVT_95_addStrictlyAFGR64AsmRegOperands: |
| 1827 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1828 | Operands[*(p + 1)]->setConstraint("m"); |
| 1829 | NumMCOperands += 1; |
| 1830 | break; |
| 1831 | case CVT_95_addStrictlyFGR64AsmRegOperands: |
| 1832 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1833 | Operands[*(p + 1)]->setConstraint("m"); |
| 1834 | NumMCOperands += 1; |
| 1835 | break; |
| 1836 | case CVT_95_addStrictlyFGR32AsmRegOperands: |
| 1837 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1838 | Operands[*(p + 1)]->setConstraint("m"); |
| 1839 | NumMCOperands += 1; |
| 1840 | break; |
| 1841 | case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: |
| 1842 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1843 | Operands[*(p + 1)]->setConstraint("m"); |
| 1844 | NumMCOperands += 1; |
| 1845 | break; |
| 1846 | case CVT_95_addRegListOperands: |
| 1847 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1848 | Operands[*(p + 1)]->setConstraint("m"); |
| 1849 | NumMCOperands += 1; |
| 1850 | break; |
| 1851 | case CVT_regAC0: |
| 1852 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1853 | Operands[*(p + 1)]->setConstraint("m"); |
| 1854 | ++NumMCOperands; |
| 1855 | break; |
| 1856 | case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: |
| 1857 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1858 | Operands[*(p + 1)]->setConstraint("m"); |
| 1859 | NumMCOperands += 1; |
| 1860 | break; |
| 1861 | case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: |
| 1862 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1863 | Operands[*(p + 1)]->setConstraint("m"); |
| 1864 | NumMCOperands += 1; |
| 1865 | break; |
| 1866 | case CVT_95_addGPRMM16AsmRegMovePOperands: |
| 1867 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1868 | Operands[*(p + 1)]->setConstraint("m"); |
| 1869 | NumMCOperands += 1; |
| 1870 | break; |
| 1871 | case CVT_95_addHI32DSPAsmRegOperands: |
| 1872 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1873 | Operands[*(p + 1)]->setConstraint("m"); |
| 1874 | NumMCOperands += 1; |
| 1875 | break; |
| 1876 | case CVT_95_addLO32DSPAsmRegOperands: |
| 1877 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1878 | Operands[*(p + 1)]->setConstraint("m"); |
| 1879 | NumMCOperands += 1; |
| 1880 | break; |
| 1881 | case CVT_regS0: |
| 1882 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1883 | Operands[*(p + 1)]->setConstraint("m"); |
| 1884 | ++NumMCOperands; |
| 1885 | break; |
| 1886 | case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: |
| 1887 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1888 | Operands[*(p + 1)]->setConstraint("m"); |
| 1889 | NumMCOperands += 1; |
| 1890 | break; |
| 1891 | case CVT_95_addHWRegsAsmRegOperands: |
| 1892 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1893 | Operands[*(p + 1)]->setConstraint("m"); |
| 1894 | NumMCOperands += 1; |
| 1895 | break; |
| 1896 | case CVT_95_addGPRMM16AsmRegZeroOperands: |
| 1897 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1898 | Operands[*(p + 1)]->setConstraint("m"); |
| 1899 | NumMCOperands += 1; |
| 1900 | break; |
| 1901 | case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: |
| 1902 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1903 | Operands[*(p + 1)]->setConstraint("m"); |
| 1904 | NumMCOperands += 1; |
| 1905 | break; |
| 1906 | case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: |
| 1907 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1908 | Operands[*(p + 1)]->setConstraint("m"); |
| 1909 | NumMCOperands += 1; |
| 1910 | break; |
| 1911 | case CVT_imm_95_2: |
| 1912 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1913 | Operands[*(p + 1)]->setConstraint(""); |
| 1914 | ++NumMCOperands; |
| 1915 | break; |
| 1916 | case CVT_imm_95_6: |
| 1917 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1918 | Operands[*(p + 1)]->setConstraint(""); |
| 1919 | ++NumMCOperands; |
| 1920 | break; |
| 1921 | case CVT_imm_95_4: |
| 1922 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1923 | Operands[*(p + 1)]->setConstraint(""); |
| 1924 | ++NumMCOperands; |
| 1925 | break; |
| 1926 | case CVT_imm_95_5: |
| 1927 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1928 | Operands[*(p + 1)]->setConstraint(""); |
| 1929 | ++NumMCOperands; |
| 1930 | break; |
| 1931 | case CVT_imm_95_31: |
| 1932 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| 1933 | Operands[*(p + 1)]->setConstraint(""); |
| 1934 | ++NumMCOperands; |
| 1935 | break; |
| 1936 | } |
| 1937 | } |
| 1938 | } |
| 1939 | |
| 1940 | namespace { |
| 1941 | |
| 1942 | /// MatchClassKind - The kinds of classes which participate in |
| 1943 | /// instruction matching. |
| 1944 | enum MatchClassKind { |
| 1945 | InvalidMatchClass = 0, |
| 1946 | OptionalMatchClass = 1, |
| 1947 | MCK__HASH_, // '#' |
| 1948 | MCK__40_, // '(' |
| 1949 | MCK__41_, // ')' |
| 1950 | MCK_0, // '0' |
| 1951 | MCK_16, // '16' |
| 1952 | MCK__91_, // '[' |
| 1953 | MCK__93_, // ']' |
| 1954 | MCK_bit, // 'bit' |
| 1955 | MCK_inst, // 'inst' |
| 1956 | MCK_LAST_TOKEN = MCK_inst, |
| 1957 | MCK_Reg37, // derived register class |
| 1958 | MCK_Reg19, // derived register class |
| 1959 | MCK_ACC128, // register class 'ACC128' |
| 1960 | MCK_ACC64, // register class 'ACC64' |
| 1961 | MCK_CPURAReg, // register class 'CPURAReg,RA' |
| 1962 | MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP' |
| 1963 | MCK_DSPCC, // register class 'DSPCC' |
| 1964 | MCK_GP32, // register class 'GP32' |
| 1965 | MCK_GP64, // register class 'GP64' |
| 1966 | MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO' |
| 1967 | MCK_HI32, // register class 'HI32' |
| 1968 | MCK_HI64, // register class 'HI64' |
| 1969 | MCK_LO32, // register class 'LO32' |
| 1970 | MCK_LO64, // register class 'LO64' |
| 1971 | MCK_PC, // register class 'PC' |
| 1972 | MCK_SP64, // register class 'SP64' |
| 1973 | MCK_Reg32, // derived register class |
| 1974 | MCK_Reg13, // derived register class |
| 1975 | MCK_Reg33, // derived register class |
| 1976 | MCK_Reg31, // derived register class |
| 1977 | MCK_Reg30, // derived register class |
| 1978 | MCK_Reg14, // derived register class |
| 1979 | MCK_Reg11, // derived register class |
| 1980 | MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst' |
| 1981 | MCK_OCTEON_MPL, // register class 'OCTEON_MPL' |
| 1982 | MCK_OCTEON_P, // register class 'OCTEON_P' |
| 1983 | MCK_Reg28, // derived register class |
| 1984 | MCK_Reg23, // derived register class |
| 1985 | MCK_Reg9, // derived register class |
| 1986 | MCK_Reg4, // derived register class |
| 1987 | MCK_ACC64DSP, // register class 'ACC64DSP' |
| 1988 | MCK_HI32DSP, // register class 'HI32DSP' |
| 1989 | MCK_LO32DSP, // register class 'LO32DSP' |
| 1990 | MCK_Reg34, // derived register class |
| 1991 | MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond' |
| 1992 | MCK_Reg29, // derived register class |
| 1993 | MCK_Reg27, // derived register class |
| 1994 | MCK_Reg10, // derived register class |
| 1995 | MCK_Reg8, // derived register class |
| 1996 | MCK_Reg25, // derived register class |
| 1997 | MCK_Reg22, // derived register class |
| 1998 | MCK_Reg21, // derived register class |
| 1999 | MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16' |
| 2000 | MCK_FCC, // register class 'FCC' |
| 2001 | MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP' |
| 2002 | MCK_GPRMM16Zero, // register class 'GPRMM16Zero' |
| 2003 | MCK_Reg26, // derived register class |
| 2004 | MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP' |
| 2005 | MCK_AFGR64, // register class 'AFGR64' |
| 2006 | MCK_MSA128WEvens, // register class 'MSA128WEvens' |
| 2007 | MCK_Reg24, // derived register class |
| 2008 | MCK_GPR32NONZERO, // register class 'GPR32NONZERO' |
| 2009 | MCK_CCR, // register class 'CCR' |
| 2010 | MCK_COP0, // register class 'COP0' |
| 2011 | MCK_COP2, // register class 'COP2' |
| 2012 | MCK_COP3, // register class 'COP3' |
| 2013 | MCK_DSPR, // register class 'DSPR,GPR32' |
| 2014 | MCK_FGR32, // register class 'FGR32,FGRCC' |
| 2015 | MCK_FGR64, // register class 'FGR64' |
| 2016 | MCK_GPR64, // register class 'GPR64' |
| 2017 | MCK_HWRegs, // register class 'HWRegs' |
| 2018 | MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W' |
| 2019 | MCK_MSACtrl, // register class 'MSACtrl' |
| 2020 | MCK_LAST_REGISTER = MCK_MSACtrl, |
| 2021 | MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand' |
| 2022 | MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand' |
| 2023 | MCK_CCRAsmReg, // user defined class 'CCRAsmOperand' |
| 2024 | MCK_COP0AsmReg, // user defined class 'COP0AsmOperand' |
| 2025 | MCK_COP2AsmReg, // user defined class 'COP2AsmOperand' |
| 2026 | MCK_COP3AsmReg, // user defined class 'COP3AsmOperand' |
| 2027 | MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand' |
| 2028 | MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand' |
| 2029 | MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand' |
| 2030 | MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand' |
| 2031 | MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand' |
| 2032 | MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand' |
| 2033 | MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand' |
| 2034 | MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand' |
| 2035 | MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP' |
| 2036 | MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst' |
| 2037 | MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond' |
| 2038 | MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero' |
| 2039 | MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand' |
| 2040 | MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand' |
| 2041 | MCK_Imm, // user defined class 'ImmAsmOperand' |
| 2042 | MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand' |
| 2043 | MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand' |
| 2044 | MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand' |
| 2045 | MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand' |
| 2046 | MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand' |
| 2047 | MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand' |
| 2048 | MCK_InvNum, // user defined class 'MipsInvertedImmoperand' |
| 2049 | MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand' |
| 2050 | MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand' |
| 2051 | MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand' |
| 2052 | MCK_MemOffsetSimm9_0, // user defined class 'anonymous_8391' |
| 2053 | MCK_MemOffsetSimm10_0, // user defined class 'anonymous_8392' |
| 2054 | MCK_MemOffsetSimm11_0, // user defined class 'anonymous_8393' |
| 2055 | MCK_MemOffsetSimm12_0, // user defined class 'anonymous_8394' |
| 2056 | MCK_MemOffsetSimm16_0, // user defined class 'anonymous_8395' |
| 2057 | MCK_MemOffsetSimm10_1, // user defined class 'anonymous_8396' |
| 2058 | MCK_MemOffsetSimm10_2, // user defined class 'anonymous_8397' |
| 2059 | MCK_MemOffsetSimm10_3, // user defined class 'anonymous_8398' |
| 2060 | MCK_Mem, // user defined class 'MipsMemAsmOperand' |
| 2061 | MCK_RegList16, // user defined class 'RegList16AsmOperand' |
| 2062 | MCK_RegList, // user defined class 'RegListAsmOperand' |
| 2063 | MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand' |
| 2064 | MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand' |
| 2065 | MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand' |
| 2066 | MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand' |
| 2067 | MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass' |
| 2068 | MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass' |
| 2069 | MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass' |
| 2070 | MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass' |
| 2071 | MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass' |
| 2072 | MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass' |
| 2073 | MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass' |
| 2074 | MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass' |
| 2075 | MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass' |
| 2076 | MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass' |
| 2077 | MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass' |
| 2078 | MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass' |
| 2079 | MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass' |
| 2080 | MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass' |
| 2081 | MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass' |
| 2082 | MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass' |
| 2083 | MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass' |
| 2084 | MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass' |
| 2085 | MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass' |
| 2086 | MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass' |
| 2087 | MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass' |
| 2088 | MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass' |
| 2089 | MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass' |
| 2090 | MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass' |
| 2091 | MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass' |
| 2092 | MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass' |
| 2093 | MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass' |
| 2094 | MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass' |
| 2095 | MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass' |
| 2096 | MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass' |
| 2097 | MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass' |
| 2098 | MCK_SImm16, // user defined class 'SImm16AsmOperandClass' |
| 2099 | MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass' |
| 2100 | MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass' |
| 2101 | MCK_UImm16, // user defined class 'UImm16AsmOperandClass' |
| 2102 | MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass' |
| 2103 | MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass' |
| 2104 | MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass' |
| 2105 | MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass' |
| 2106 | MCK_SImm32, // user defined class 'SImm32AsmOperandClass' |
| 2107 | MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass' |
| 2108 | MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass' |
| 2109 | NumMatchClassKinds |
| 2110 | }; |
| 2111 | |
| 2112 | } // end anonymous namespace |
| 2113 | |
| 2114 | static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { |
| 2115 | return MCTargetAsmParser::Match_InvalidOperand; |
| 2116 | } |
| 2117 | |
| 2118 | static MatchClassKind matchTokenString(StringRef Name) { |
| 2119 | switch (Name.size()) { |
| 2120 | default: break; |
| 2121 | case 1: // 6 strings to match. |
| 2122 | switch (Name[0]) { |
| 2123 | default: break; |
| 2124 | case '#': // 1 string to match. |
| 2125 | return MCK__HASH_; // "#" |
| 2126 | case '(': // 1 string to match. |
| 2127 | return MCK__40_; // "(" |
| 2128 | case ')': // 1 string to match. |
| 2129 | return MCK__41_; // ")" |
| 2130 | case '0': // 1 string to match. |
| 2131 | return MCK_0; // "0" |
| 2132 | case '[': // 1 string to match. |
| 2133 | return MCK__91_; // "[" |
| 2134 | case ']': // 1 string to match. |
| 2135 | return MCK__93_; // "]" |
| 2136 | } |
| 2137 | break; |
| 2138 | case 2: // 1 string to match. |
| 2139 | if (memcmp(Name.data()+0, "16", 2) != 0) |
| 2140 | break; |
| 2141 | return MCK_16; // "16" |
| 2142 | case 3: // 1 string to match. |
| 2143 | if (memcmp(Name.data()+0, "bit", 3) != 0) |
| 2144 | break; |
| 2145 | return MCK_bit; // "bit" |
| 2146 | case 4: // 1 string to match. |
| 2147 | if (memcmp(Name.data()+0, "inst", 4) != 0) |
| 2148 | break; |
| 2149 | return MCK_inst; // "inst" |
| 2150 | } |
| 2151 | return InvalidMatchClass; |
| 2152 | } |
| 2153 | |
| 2154 | /// isSubclass - Compute whether \p A is a subclass of \p B. |
| 2155 | static bool isSubclass(MatchClassKind A, MatchClassKind B) { |
| 2156 | if (A == B) |
| 2157 | return true; |
| 2158 | |
| 2159 | switch (A) { |
| 2160 | default: |
| 2161 | return false; |
| 2162 | |
| 2163 | case MCK_Reg37: |
| 2164 | switch (B) { |
| 2165 | default: return false; |
| 2166 | case MCK_Reg24: return true; |
| 2167 | case MCK_GPR64: return true; |
| 2168 | } |
| 2169 | |
| 2170 | case MCK_Reg19: |
| 2171 | switch (B) { |
| 2172 | default: return false; |
| 2173 | case MCK_Reg23: return true; |
| 2174 | case MCK_Reg22: return true; |
| 2175 | case MCK_Reg21: return true; |
| 2176 | case MCK_GPR64: return true; |
| 2177 | } |
| 2178 | |
| 2179 | case MCK_ACC64: |
| 2180 | return B == MCK_ACC64DSP; |
| 2181 | |
| 2182 | case MCK_CPURAReg: |
| 2183 | switch (B) { |
| 2184 | default: return false; |
| 2185 | case MCK_GPR32NONZERO: return true; |
| 2186 | case MCK_DSPR: return true; |
| 2187 | } |
| 2188 | |
| 2189 | case MCK_CPUSPReg: |
| 2190 | switch (B) { |
| 2191 | default: return false; |
| 2192 | case MCK_CPU16RegsPlusSP: return true; |
| 2193 | case MCK_GPR32NONZERO: return true; |
| 2194 | case MCK_DSPR: return true; |
| 2195 | } |
| 2196 | |
| 2197 | case MCK_GP32: |
| 2198 | switch (B) { |
| 2199 | default: return false; |
| 2200 | case MCK_GPR32NONZERO: return true; |
| 2201 | case MCK_DSPR: return true; |
| 2202 | } |
| 2203 | |
| 2204 | case MCK_GP64: |
| 2205 | switch (B) { |
| 2206 | default: return false; |
| 2207 | case MCK_Reg24: return true; |
| 2208 | case MCK_GPR64: return true; |
| 2209 | } |
| 2210 | |
| 2211 | case MCK_GPR32ZERO: |
| 2212 | switch (B) { |
| 2213 | default: return false; |
| 2214 | case MCK_Reg4: return true; |
| 2215 | case MCK_GPRMM16MoveP: return true; |
| 2216 | case MCK_GPRMM16Zero: return true; |
| 2217 | case MCK_DSPR: return true; |
| 2218 | } |
| 2219 | |
| 2220 | case MCK_HI32: |
| 2221 | return B == MCK_HI32DSP; |
| 2222 | |
| 2223 | case MCK_LO32: |
| 2224 | return B == MCK_LO32DSP; |
| 2225 | |
| 2226 | case MCK_SP64: |
| 2227 | switch (B) { |
| 2228 | default: return false; |
| 2229 | case MCK_Reg26: return true; |
| 2230 | case MCK_Reg24: return true; |
| 2231 | case MCK_GPR64: return true; |
| 2232 | } |
| 2233 | |
| 2234 | case MCK_Reg32: |
| 2235 | switch (B) { |
| 2236 | default: return false; |
| 2237 | case MCK_Reg33: return true; |
| 2238 | case MCK_Reg31: return true; |
| 2239 | case MCK_Reg34: return true; |
| 2240 | case MCK_Reg27: return true; |
| 2241 | case MCK_Reg25: return true; |
| 2242 | case MCK_Reg21: return true; |
| 2243 | case MCK_Reg26: return true; |
| 2244 | case MCK_Reg24: return true; |
| 2245 | case MCK_GPR64: return true; |
| 2246 | } |
| 2247 | |
| 2248 | case MCK_Reg13: |
| 2249 | switch (B) { |
| 2250 | default: return false; |
| 2251 | case MCK_Reg14: return true; |
| 2252 | case MCK_GPRMM16MovePPairFirst: return true; |
| 2253 | case MCK_GPRMM16MovePPairSecond: return true; |
| 2254 | case MCK_Reg8: return true; |
| 2255 | case MCK_CPU16Regs: return true; |
| 2256 | case MCK_GPRMM16Zero: return true; |
| 2257 | case MCK_CPU16RegsPlusSP: return true; |
| 2258 | case MCK_GPR32NONZERO: return true; |
| 2259 | case MCK_DSPR: return true; |
| 2260 | } |
| 2261 | |
| 2262 | case MCK_Reg33: |
| 2263 | switch (B) { |
| 2264 | default: return false; |
| 2265 | case MCK_Reg34: return true; |
| 2266 | case MCK_Reg27: return true; |
| 2267 | case MCK_Reg25: return true; |
| 2268 | case MCK_Reg21: return true; |
| 2269 | case MCK_Reg26: return true; |
| 2270 | case MCK_Reg24: return true; |
| 2271 | case MCK_GPR64: return true; |
| 2272 | } |
| 2273 | |
| 2274 | case MCK_Reg31: |
| 2275 | switch (B) { |
| 2276 | default: return false; |
| 2277 | case MCK_Reg27: return true; |
| 2278 | case MCK_Reg25: return true; |
| 2279 | case MCK_Reg21: return true; |
| 2280 | case MCK_Reg26: return true; |
| 2281 | case MCK_Reg24: return true; |
| 2282 | case MCK_GPR64: return true; |
| 2283 | } |
| 2284 | |
| 2285 | case MCK_Reg30: |
| 2286 | switch (B) { |
| 2287 | default: return false; |
| 2288 | case MCK_Reg28: return true; |
| 2289 | case MCK_Reg23: return true; |
| 2290 | case MCK_Reg29: return true; |
| 2291 | case MCK_Reg27: return true; |
| 2292 | case MCK_Reg25: return true; |
| 2293 | case MCK_Reg22: return true; |
| 2294 | case MCK_Reg21: return true; |
| 2295 | case MCK_Reg26: return true; |
| 2296 | case MCK_Reg24: return true; |
| 2297 | case MCK_GPR64: return true; |
| 2298 | } |
| 2299 | |
| 2300 | case MCK_Reg14: |
| 2301 | switch (B) { |
| 2302 | default: return false; |
| 2303 | case MCK_GPRMM16MovePPairSecond: return true; |
| 2304 | case MCK_Reg8: return true; |
| 2305 | case MCK_CPU16Regs: return true; |
| 2306 | case MCK_GPRMM16Zero: return true; |
| 2307 | case MCK_CPU16RegsPlusSP: return true; |
| 2308 | case MCK_GPR32NONZERO: return true; |
| 2309 | case MCK_DSPR: return true; |
| 2310 | } |
| 2311 | |
| 2312 | case MCK_Reg11: |
| 2313 | switch (B) { |
| 2314 | default: return false; |
| 2315 | case MCK_Reg9: return true; |
| 2316 | case MCK_Reg4: return true; |
| 2317 | case MCK_Reg10: return true; |
| 2318 | case MCK_Reg8: return true; |
| 2319 | case MCK_CPU16Regs: return true; |
| 2320 | case MCK_GPRMM16MoveP: return true; |
| 2321 | case MCK_GPRMM16Zero: return true; |
| 2322 | case MCK_CPU16RegsPlusSP: return true; |
| 2323 | case MCK_GPR32NONZERO: return true; |
| 2324 | case MCK_DSPR: return true; |
| 2325 | } |
| 2326 | |
| 2327 | case MCK_GPRMM16MovePPairFirst: |
| 2328 | switch (B) { |
| 2329 | default: return false; |
| 2330 | case MCK_Reg8: return true; |
| 2331 | case MCK_CPU16Regs: return true; |
| 2332 | case MCK_GPRMM16Zero: return true; |
| 2333 | case MCK_CPU16RegsPlusSP: return true; |
| 2334 | case MCK_GPR32NONZERO: return true; |
| 2335 | case MCK_DSPR: return true; |
| 2336 | } |
| 2337 | |
| 2338 | case MCK_Reg28: |
| 2339 | switch (B) { |
| 2340 | default: return false; |
| 2341 | case MCK_Reg29: return true; |
| 2342 | case MCK_Reg25: return true; |
| 2343 | case MCK_Reg22: return true; |
| 2344 | case MCK_Reg26: return true; |
| 2345 | case MCK_Reg24: return true; |
| 2346 | case MCK_GPR64: return true; |
| 2347 | } |
| 2348 | |
| 2349 | case MCK_Reg23: |
| 2350 | switch (B) { |
| 2351 | default: return false; |
| 2352 | case MCK_Reg22: return true; |
| 2353 | case MCK_Reg21: return true; |
| 2354 | case MCK_GPR64: return true; |
| 2355 | } |
| 2356 | |
| 2357 | case MCK_Reg9: |
| 2358 | switch (B) { |
| 2359 | default: return false; |
| 2360 | case MCK_Reg10: return true; |
| 2361 | case MCK_CPU16Regs: return true; |
| 2362 | case MCK_GPRMM16MoveP: return true; |
| 2363 | case MCK_CPU16RegsPlusSP: return true; |
| 2364 | case MCK_GPR32NONZERO: return true; |
| 2365 | case MCK_DSPR: return true; |
| 2366 | } |
| 2367 | |
| 2368 | case MCK_Reg4: |
| 2369 | switch (B) { |
| 2370 | default: return false; |
| 2371 | case MCK_GPRMM16MoveP: return true; |
| 2372 | case MCK_GPRMM16Zero: return true; |
| 2373 | case MCK_DSPR: return true; |
| 2374 | } |
| 2375 | |
| 2376 | case MCK_Reg34: |
| 2377 | switch (B) { |
| 2378 | default: return false; |
| 2379 | case MCK_Reg24: return true; |
| 2380 | case MCK_GPR64: return true; |
| 2381 | } |
| 2382 | |
| 2383 | case MCK_GPRMM16MovePPairSecond: |
| 2384 | switch (B) { |
| 2385 | default: return false; |
| 2386 | case MCK_GPR32NONZERO: return true; |
| 2387 | case MCK_DSPR: return true; |
| 2388 | } |
| 2389 | |
| 2390 | case MCK_Reg29: |
| 2391 | switch (B) { |
| 2392 | default: return false; |
| 2393 | case MCK_Reg22: return true; |
| 2394 | case MCK_Reg24: return true; |
| 2395 | case MCK_GPR64: return true; |
| 2396 | } |
| 2397 | |
| 2398 | case MCK_Reg27: |
| 2399 | switch (B) { |
| 2400 | default: return false; |
| 2401 | case MCK_Reg25: return true; |
| 2402 | case MCK_Reg21: return true; |
| 2403 | case MCK_Reg26: return true; |
| 2404 | case MCK_Reg24: return true; |
| 2405 | case MCK_GPR64: return true; |
| 2406 | } |
| 2407 | |
| 2408 | case MCK_Reg10: |
| 2409 | switch (B) { |
| 2410 | default: return false; |
| 2411 | case MCK_GPRMM16MoveP: return true; |
| 2412 | case MCK_GPR32NONZERO: return true; |
| 2413 | case MCK_DSPR: return true; |
| 2414 | } |
| 2415 | |
| 2416 | case MCK_Reg8: |
| 2417 | switch (B) { |
| 2418 | default: return false; |
| 2419 | case MCK_CPU16Regs: return true; |
| 2420 | case MCK_GPRMM16Zero: return true; |
| 2421 | case MCK_CPU16RegsPlusSP: return true; |
| 2422 | case MCK_GPR32NONZERO: return true; |
| 2423 | case MCK_DSPR: return true; |
| 2424 | } |
| 2425 | |
| 2426 | case MCK_Reg25: |
| 2427 | switch (B) { |
| 2428 | default: return false; |
| 2429 | case MCK_Reg26: return true; |
| 2430 | case MCK_Reg24: return true; |
| 2431 | case MCK_GPR64: return true; |
| 2432 | } |
| 2433 | |
| 2434 | case MCK_Reg22: |
| 2435 | return B == MCK_GPR64; |
| 2436 | |
| 2437 | case MCK_Reg21: |
| 2438 | return B == MCK_GPR64; |
| 2439 | |
| 2440 | case MCK_CPU16Regs: |
| 2441 | switch (B) { |
| 2442 | default: return false; |
| 2443 | case MCK_CPU16RegsPlusSP: return true; |
| 2444 | case MCK_GPR32NONZERO: return true; |
| 2445 | case MCK_DSPR: return true; |
| 2446 | } |
| 2447 | |
| 2448 | case MCK_GPRMM16MoveP: |
| 2449 | return B == MCK_DSPR; |
| 2450 | |
| 2451 | case MCK_GPRMM16Zero: |
| 2452 | return B == MCK_DSPR; |
| 2453 | |
| 2454 | case MCK_Reg26: |
| 2455 | switch (B) { |
| 2456 | default: return false; |
| 2457 | case MCK_Reg24: return true; |
| 2458 | case MCK_GPR64: return true; |
| 2459 | } |
| 2460 | |
| 2461 | case MCK_CPU16RegsPlusSP: |
| 2462 | switch (B) { |
| 2463 | default: return false; |
| 2464 | case MCK_GPR32NONZERO: return true; |
| 2465 | case MCK_DSPR: return true; |
| 2466 | } |
| 2467 | |
| 2468 | case MCK_MSA128WEvens: |
| 2469 | return B == MCK_MSA128F16; |
| 2470 | |
| 2471 | case MCK_Reg24: |
| 2472 | return B == MCK_GPR64; |
| 2473 | |
| 2474 | case MCK_GPR32NONZERO: |
| 2475 | return B == MCK_DSPR; |
| 2476 | |
| 2477 | case MCK_MemOffsetSimmPtr: |
| 2478 | return B == MCK_Mem; |
| 2479 | |
| 2480 | case MCK_MemOffsetUimm4: |
| 2481 | return B == MCK_Mem; |
| 2482 | |
| 2483 | case MCK_MemOffsetSimm9_0: |
| 2484 | return B == MCK_Mem; |
| 2485 | |
| 2486 | case MCK_MemOffsetSimm10_0: |
| 2487 | return B == MCK_Mem; |
| 2488 | |
| 2489 | case MCK_MemOffsetSimm11_0: |
| 2490 | return B == MCK_Mem; |
| 2491 | |
| 2492 | case MCK_MemOffsetSimm12_0: |
| 2493 | return B == MCK_Mem; |
| 2494 | |
| 2495 | case MCK_MemOffsetSimm16_0: |
| 2496 | return B == MCK_Mem; |
| 2497 | |
| 2498 | case MCK_MemOffsetSimm10_1: |
| 2499 | return B == MCK_Mem; |
| 2500 | |
| 2501 | case MCK_MemOffsetSimm10_2: |
| 2502 | return B == MCK_Mem; |
| 2503 | |
| 2504 | case MCK_MemOffsetSimm10_3: |
| 2505 | return B == MCK_Mem; |
| 2506 | |
| 2507 | case MCK_ConstantImmz: |
| 2508 | switch (B) { |
| 2509 | default: return false; |
| 2510 | case MCK_ConstantUImm1_0: return true; |
| 2511 | case MCK_ConstantUImm2_0: return true; |
| 2512 | case MCK_ConstantUImm3_0: return true; |
| 2513 | case MCK_ConstantSImm4_0: return true; |
| 2514 | case MCK_ConstantUImm4_0: return true; |
| 2515 | case MCK_ConstantSImm5_0: return true; |
| 2516 | case MCK_ConstantUImm5_0: return true; |
| 2517 | case MCK_ConstantUImm5_1: return true; |
| 2518 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2519 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2520 | case MCK_ConstantUImm5_32: return true; |
| 2521 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2522 | case MCK_ConstantUImm5_33: return true; |
| 2523 | case MCK_ConstantUImmRange2_64: return true; |
| 2524 | case MCK_UImm5Lsl2: return true; |
| 2525 | case MCK_ConstantSImm6_0: return true; |
| 2526 | case MCK_ConstantUImm6_0: return true; |
| 2527 | case MCK_UImm6Lsl2: return true; |
| 2528 | case MCK_ConstantUImm7_0: return true; |
| 2529 | case MCK_UImm7_N1: return true; |
| 2530 | case MCK_ConstantUImm8_0: return true; |
| 2531 | case MCK_SImm7Lsl2: return true; |
| 2532 | case MCK_ConstantSImm9_0: return true; |
| 2533 | case MCK_ConstantSImm10_0: return true; |
| 2534 | case MCK_ConstantUImm10_0: return true; |
| 2535 | case MCK_SImm10Lsl1: return true; |
| 2536 | case MCK_ConstantSImm11_0: return true; |
| 2537 | case MCK_SImm10Lsl2: return true; |
| 2538 | case MCK_SImm10Lsl3: return true; |
| 2539 | case MCK_SImm16: return true; |
| 2540 | case MCK_SImm16_Relaxed: return true; |
| 2541 | case MCK_UImm16_Relaxed: return true; |
| 2542 | case MCK_ConstantUImm20_0: return true; |
| 2543 | case MCK_ConstantUImm26_0: return true; |
| 2544 | case MCK_SImm32: return true; |
| 2545 | case MCK_SImm32_Relaxed: return true; |
| 2546 | case MCK_UImm32_Coerced: return true; |
| 2547 | } |
| 2548 | |
| 2549 | case MCK_ConstantUImm1_0: |
| 2550 | switch (B) { |
| 2551 | default: return false; |
| 2552 | case MCK_ConstantUImm2_0: return true; |
| 2553 | case MCK_ConstantUImm3_0: return true; |
| 2554 | case MCK_ConstantSImm4_0: return true; |
| 2555 | case MCK_ConstantUImm4_0: return true; |
| 2556 | case MCK_ConstantSImm5_0: return true; |
| 2557 | case MCK_ConstantUImm5_0: return true; |
| 2558 | case MCK_ConstantUImm5_1: return true; |
| 2559 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2560 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2561 | case MCK_ConstantUImm5_32: return true; |
| 2562 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2563 | case MCK_ConstantUImm5_33: return true; |
| 2564 | case MCK_ConstantUImmRange2_64: return true; |
| 2565 | case MCK_UImm5Lsl2: return true; |
| 2566 | case MCK_ConstantSImm6_0: return true; |
| 2567 | case MCK_ConstantUImm6_0: return true; |
| 2568 | case MCK_UImm6Lsl2: return true; |
| 2569 | case MCK_ConstantUImm7_0: return true; |
| 2570 | case MCK_UImm7_N1: return true; |
| 2571 | case MCK_ConstantUImm8_0: return true; |
| 2572 | case MCK_SImm7Lsl2: return true; |
| 2573 | case MCK_ConstantSImm9_0: return true; |
| 2574 | case MCK_ConstantSImm10_0: return true; |
| 2575 | case MCK_ConstantUImm10_0: return true; |
| 2576 | case MCK_SImm10Lsl1: return true; |
| 2577 | case MCK_ConstantSImm11_0: return true; |
| 2578 | case MCK_SImm10Lsl2: return true; |
| 2579 | case MCK_SImm10Lsl3: return true; |
| 2580 | case MCK_SImm16: return true; |
| 2581 | case MCK_SImm16_Relaxed: return true; |
| 2582 | case MCK_UImm16_Relaxed: return true; |
| 2583 | case MCK_ConstantUImm20_0: return true; |
| 2584 | case MCK_ConstantUImm26_0: return true; |
| 2585 | case MCK_SImm32: return true; |
| 2586 | case MCK_SImm32_Relaxed: return true; |
| 2587 | case MCK_UImm32_Coerced: return true; |
| 2588 | } |
| 2589 | |
| 2590 | case MCK_ConstantUImm2_0: |
| 2591 | switch (B) { |
| 2592 | default: return false; |
| 2593 | case MCK_ConstantUImm3_0: return true; |
| 2594 | case MCK_ConstantSImm4_0: return true; |
| 2595 | case MCK_ConstantUImm4_0: return true; |
| 2596 | case MCK_ConstantSImm5_0: return true; |
| 2597 | case MCK_ConstantUImm5_0: return true; |
| 2598 | case MCK_ConstantUImm5_1: return true; |
| 2599 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2600 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2601 | case MCK_ConstantUImm5_32: return true; |
| 2602 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2603 | case MCK_ConstantUImm5_33: return true; |
| 2604 | case MCK_ConstantUImmRange2_64: return true; |
| 2605 | case MCK_UImm5Lsl2: return true; |
| 2606 | case MCK_ConstantSImm6_0: return true; |
| 2607 | case MCK_ConstantUImm6_0: return true; |
| 2608 | case MCK_UImm6Lsl2: return true; |
| 2609 | case MCK_ConstantUImm7_0: return true; |
| 2610 | case MCK_UImm7_N1: return true; |
| 2611 | case MCK_ConstantUImm8_0: return true; |
| 2612 | case MCK_SImm7Lsl2: return true; |
| 2613 | case MCK_ConstantSImm9_0: return true; |
| 2614 | case MCK_ConstantSImm10_0: return true; |
| 2615 | case MCK_ConstantUImm10_0: return true; |
| 2616 | case MCK_SImm10Lsl1: return true; |
| 2617 | case MCK_ConstantSImm11_0: return true; |
| 2618 | case MCK_SImm10Lsl2: return true; |
| 2619 | case MCK_SImm10Lsl3: return true; |
| 2620 | case MCK_SImm16: return true; |
| 2621 | case MCK_SImm16_Relaxed: return true; |
| 2622 | case MCK_UImm16_Relaxed: return true; |
| 2623 | case MCK_ConstantUImm20_0: return true; |
| 2624 | case MCK_ConstantUImm26_0: return true; |
| 2625 | case MCK_SImm32: return true; |
| 2626 | case MCK_SImm32_Relaxed: return true; |
| 2627 | case MCK_UImm32_Coerced: return true; |
| 2628 | } |
| 2629 | |
| 2630 | case MCK_ConstantUImm2_1: |
| 2631 | switch (B) { |
| 2632 | default: return false; |
| 2633 | case MCK_ConstantUImm3_0: return true; |
| 2634 | case MCK_ConstantSImm4_0: return true; |
| 2635 | case MCK_ConstantUImm4_0: return true; |
| 2636 | case MCK_ConstantSImm5_0: return true; |
| 2637 | case MCK_ConstantUImm5_0: return true; |
| 2638 | case MCK_ConstantUImm5_1: return true; |
| 2639 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2640 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2641 | case MCK_ConstantUImm5_32: return true; |
| 2642 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2643 | case MCK_ConstantUImm5_33: return true; |
| 2644 | case MCK_ConstantUImmRange2_64: return true; |
| 2645 | case MCK_UImm5Lsl2: return true; |
| 2646 | case MCK_ConstantSImm6_0: return true; |
| 2647 | case MCK_ConstantUImm6_0: return true; |
| 2648 | case MCK_UImm6Lsl2: return true; |
| 2649 | case MCK_ConstantUImm7_0: return true; |
| 2650 | case MCK_UImm7_N1: return true; |
| 2651 | case MCK_ConstantUImm8_0: return true; |
| 2652 | case MCK_SImm7Lsl2: return true; |
| 2653 | case MCK_ConstantSImm9_0: return true; |
| 2654 | case MCK_ConstantSImm10_0: return true; |
| 2655 | case MCK_ConstantUImm10_0: return true; |
| 2656 | case MCK_SImm10Lsl1: return true; |
| 2657 | case MCK_ConstantSImm11_0: return true; |
| 2658 | case MCK_SImm10Lsl2: return true; |
| 2659 | case MCK_SImm10Lsl3: return true; |
| 2660 | case MCK_SImm16: return true; |
| 2661 | case MCK_SImm16_Relaxed: return true; |
| 2662 | case MCK_UImm16_Relaxed: return true; |
| 2663 | case MCK_ConstantUImm20_0: return true; |
| 2664 | case MCK_ConstantUImm26_0: return true; |
| 2665 | case MCK_SImm32: return true; |
| 2666 | case MCK_SImm32_Relaxed: return true; |
| 2667 | case MCK_UImm32_Coerced: return true; |
| 2668 | } |
| 2669 | |
| 2670 | case MCK_ConstantUImm3_0: |
| 2671 | switch (B) { |
| 2672 | default: return false; |
| 2673 | case MCK_ConstantSImm4_0: return true; |
| 2674 | case MCK_ConstantUImm4_0: return true; |
| 2675 | case MCK_ConstantSImm5_0: return true; |
| 2676 | case MCK_ConstantUImm5_0: return true; |
| 2677 | case MCK_ConstantUImm5_1: return true; |
| 2678 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2679 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2680 | case MCK_ConstantUImm5_32: return true; |
| 2681 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2682 | case MCK_ConstantUImm5_33: return true; |
| 2683 | case MCK_ConstantUImmRange2_64: return true; |
| 2684 | case MCK_UImm5Lsl2: return true; |
| 2685 | case MCK_ConstantSImm6_0: return true; |
| 2686 | case MCK_ConstantUImm6_0: return true; |
| 2687 | case MCK_UImm6Lsl2: return true; |
| 2688 | case MCK_ConstantUImm7_0: return true; |
| 2689 | case MCK_UImm7_N1: return true; |
| 2690 | case MCK_ConstantUImm8_0: return true; |
| 2691 | case MCK_SImm7Lsl2: return true; |
| 2692 | case MCK_ConstantSImm9_0: return true; |
| 2693 | case MCK_ConstantSImm10_0: return true; |
| 2694 | case MCK_ConstantUImm10_0: return true; |
| 2695 | case MCK_SImm10Lsl1: return true; |
| 2696 | case MCK_ConstantSImm11_0: return true; |
| 2697 | case MCK_SImm10Lsl2: return true; |
| 2698 | case MCK_SImm10Lsl3: return true; |
| 2699 | case MCK_SImm16: return true; |
| 2700 | case MCK_SImm16_Relaxed: return true; |
| 2701 | case MCK_UImm16_Relaxed: return true; |
| 2702 | case MCK_ConstantUImm20_0: return true; |
| 2703 | case MCK_ConstantUImm26_0: return true; |
| 2704 | case MCK_SImm32: return true; |
| 2705 | case MCK_SImm32_Relaxed: return true; |
| 2706 | case MCK_UImm32_Coerced: return true; |
| 2707 | } |
| 2708 | |
| 2709 | case MCK_ConstantSImm4_0: |
| 2710 | switch (B) { |
| 2711 | default: return false; |
| 2712 | case MCK_ConstantUImm4_0: return true; |
| 2713 | case MCK_ConstantSImm5_0: return true; |
| 2714 | case MCK_ConstantUImm5_0: return true; |
| 2715 | case MCK_ConstantUImm5_1: return true; |
| 2716 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2717 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2718 | case MCK_ConstantUImm5_32: return true; |
| 2719 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2720 | case MCK_ConstantUImm5_33: return true; |
| 2721 | case MCK_ConstantUImmRange2_64: return true; |
| 2722 | case MCK_UImm5Lsl2: return true; |
| 2723 | case MCK_ConstantSImm6_0: return true; |
| 2724 | case MCK_ConstantUImm6_0: return true; |
| 2725 | case MCK_UImm6Lsl2: return true; |
| 2726 | case MCK_ConstantUImm7_0: return true; |
| 2727 | case MCK_UImm7_N1: return true; |
| 2728 | case MCK_ConstantUImm8_0: return true; |
| 2729 | case MCK_SImm7Lsl2: return true; |
| 2730 | case MCK_ConstantSImm9_0: return true; |
| 2731 | case MCK_ConstantSImm10_0: return true; |
| 2732 | case MCK_ConstantUImm10_0: return true; |
| 2733 | case MCK_SImm10Lsl1: return true; |
| 2734 | case MCK_ConstantSImm11_0: return true; |
| 2735 | case MCK_SImm10Lsl2: return true; |
| 2736 | case MCK_SImm10Lsl3: return true; |
| 2737 | case MCK_SImm16: return true; |
| 2738 | case MCK_SImm16_Relaxed: return true; |
| 2739 | case MCK_UImm16_Relaxed: return true; |
| 2740 | case MCK_ConstantUImm20_0: return true; |
| 2741 | case MCK_ConstantUImm26_0: return true; |
| 2742 | case MCK_SImm32: return true; |
| 2743 | case MCK_SImm32_Relaxed: return true; |
| 2744 | case MCK_UImm32_Coerced: return true; |
| 2745 | } |
| 2746 | |
| 2747 | case MCK_ConstantUImm4_0: |
| 2748 | switch (B) { |
| 2749 | default: return false; |
| 2750 | case MCK_ConstantSImm5_0: return true; |
| 2751 | case MCK_ConstantUImm5_0: return true; |
| 2752 | case MCK_ConstantUImm5_1: return true; |
| 2753 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2754 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2755 | case MCK_ConstantUImm5_32: return true; |
| 2756 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2757 | case MCK_ConstantUImm5_33: return true; |
| 2758 | case MCK_ConstantUImmRange2_64: return true; |
| 2759 | case MCK_UImm5Lsl2: return true; |
| 2760 | case MCK_ConstantSImm6_0: return true; |
| 2761 | case MCK_ConstantUImm6_0: return true; |
| 2762 | case MCK_UImm6Lsl2: return true; |
| 2763 | case MCK_ConstantUImm7_0: return true; |
| 2764 | case MCK_UImm7_N1: return true; |
| 2765 | case MCK_ConstantUImm8_0: return true; |
| 2766 | case MCK_SImm7Lsl2: return true; |
| 2767 | case MCK_ConstantSImm9_0: return true; |
| 2768 | case MCK_ConstantSImm10_0: return true; |
| 2769 | case MCK_ConstantUImm10_0: return true; |
| 2770 | case MCK_SImm10Lsl1: return true; |
| 2771 | case MCK_ConstantSImm11_0: return true; |
| 2772 | case MCK_SImm10Lsl2: return true; |
| 2773 | case MCK_SImm10Lsl3: return true; |
| 2774 | case MCK_SImm16: return true; |
| 2775 | case MCK_SImm16_Relaxed: return true; |
| 2776 | case MCK_UImm16_Relaxed: return true; |
| 2777 | case MCK_ConstantUImm20_0: return true; |
| 2778 | case MCK_ConstantUImm26_0: return true; |
| 2779 | case MCK_SImm32: return true; |
| 2780 | case MCK_SImm32_Relaxed: return true; |
| 2781 | case MCK_UImm32_Coerced: return true; |
| 2782 | } |
| 2783 | |
| 2784 | case MCK_ConstantSImm5_0: |
| 2785 | switch (B) { |
| 2786 | default: return false; |
| 2787 | case MCK_ConstantUImm5_0: return true; |
| 2788 | case MCK_ConstantUImm5_1: return true; |
| 2789 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2790 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2791 | case MCK_ConstantUImm5_32: return true; |
| 2792 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2793 | case MCK_ConstantUImm5_33: return true; |
| 2794 | case MCK_ConstantUImmRange2_64: return true; |
| 2795 | case MCK_UImm5Lsl2: return true; |
| 2796 | case MCK_ConstantSImm6_0: return true; |
| 2797 | case MCK_ConstantUImm6_0: return true; |
| 2798 | case MCK_UImm6Lsl2: return true; |
| 2799 | case MCK_ConstantUImm7_0: return true; |
| 2800 | case MCK_UImm7_N1: return true; |
| 2801 | case MCK_ConstantUImm8_0: return true; |
| 2802 | case MCK_SImm7Lsl2: return true; |
| 2803 | case MCK_ConstantSImm9_0: return true; |
| 2804 | case MCK_ConstantSImm10_0: return true; |
| 2805 | case MCK_ConstantUImm10_0: return true; |
| 2806 | case MCK_SImm10Lsl1: return true; |
| 2807 | case MCK_ConstantSImm11_0: return true; |
| 2808 | case MCK_SImm10Lsl2: return true; |
| 2809 | case MCK_SImm10Lsl3: return true; |
| 2810 | case MCK_SImm16: return true; |
| 2811 | case MCK_SImm16_Relaxed: return true; |
| 2812 | case MCK_UImm16_Relaxed: return true; |
| 2813 | case MCK_ConstantUImm20_0: return true; |
| 2814 | case MCK_ConstantUImm26_0: return true; |
| 2815 | case MCK_SImm32: return true; |
| 2816 | case MCK_SImm32_Relaxed: return true; |
| 2817 | case MCK_UImm32_Coerced: return true; |
| 2818 | } |
| 2819 | |
| 2820 | case MCK_ConstantUImm5_0: |
| 2821 | switch (B) { |
| 2822 | default: return false; |
| 2823 | case MCK_ConstantUImm5_1: return true; |
| 2824 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2825 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2826 | case MCK_ConstantUImm5_32: return true; |
| 2827 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2828 | case MCK_ConstantUImm5_33: return true; |
| 2829 | case MCK_ConstantUImmRange2_64: return true; |
| 2830 | case MCK_UImm5Lsl2: return true; |
| 2831 | case MCK_ConstantSImm6_0: return true; |
| 2832 | case MCK_ConstantUImm6_0: return true; |
| 2833 | case MCK_UImm6Lsl2: return true; |
| 2834 | case MCK_ConstantUImm7_0: return true; |
| 2835 | case MCK_UImm7_N1: return true; |
| 2836 | case MCK_ConstantUImm8_0: return true; |
| 2837 | case MCK_SImm7Lsl2: return true; |
| 2838 | case MCK_ConstantSImm9_0: return true; |
| 2839 | case MCK_ConstantSImm10_0: return true; |
| 2840 | case MCK_ConstantUImm10_0: return true; |
| 2841 | case MCK_SImm10Lsl1: return true; |
| 2842 | case MCK_ConstantSImm11_0: return true; |
| 2843 | case MCK_SImm10Lsl2: return true; |
| 2844 | case MCK_SImm10Lsl3: return true; |
| 2845 | case MCK_SImm16: return true; |
| 2846 | case MCK_SImm16_Relaxed: return true; |
| 2847 | case MCK_UImm16_Relaxed: return true; |
| 2848 | case MCK_ConstantUImm20_0: return true; |
| 2849 | case MCK_ConstantUImm26_0: return true; |
| 2850 | case MCK_SImm32: return true; |
| 2851 | case MCK_SImm32_Relaxed: return true; |
| 2852 | case MCK_UImm32_Coerced: return true; |
| 2853 | } |
| 2854 | |
| 2855 | case MCK_ConstantUImm5_1: |
| 2856 | switch (B) { |
| 2857 | default: return false; |
| 2858 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| 2859 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2860 | case MCK_ConstantUImm5_32: return true; |
| 2861 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2862 | case MCK_ConstantUImm5_33: return true; |
| 2863 | case MCK_ConstantUImmRange2_64: return true; |
| 2864 | case MCK_UImm5Lsl2: return true; |
| 2865 | case MCK_ConstantSImm6_0: return true; |
| 2866 | case MCK_ConstantUImm6_0: return true; |
| 2867 | case MCK_UImm6Lsl2: return true; |
| 2868 | case MCK_ConstantUImm7_0: return true; |
| 2869 | case MCK_UImm7_N1: return true; |
| 2870 | case MCK_ConstantUImm8_0: return true; |
| 2871 | case MCK_SImm7Lsl2: return true; |
| 2872 | case MCK_ConstantSImm9_0: return true; |
| 2873 | case MCK_ConstantSImm10_0: return true; |
| 2874 | case MCK_ConstantUImm10_0: return true; |
| 2875 | case MCK_SImm10Lsl1: return true; |
| 2876 | case MCK_ConstantSImm11_0: return true; |
| 2877 | case MCK_SImm10Lsl2: return true; |
| 2878 | case MCK_SImm10Lsl3: return true; |
| 2879 | case MCK_SImm16: return true; |
| 2880 | case MCK_SImm16_Relaxed: return true; |
| 2881 | case MCK_UImm16_Relaxed: return true; |
| 2882 | case MCK_ConstantUImm20_0: return true; |
| 2883 | case MCK_ConstantUImm26_0: return true; |
| 2884 | case MCK_SImm32: return true; |
| 2885 | case MCK_SImm32_Relaxed: return true; |
| 2886 | case MCK_UImm32_Coerced: return true; |
| 2887 | } |
| 2888 | |
| 2889 | case MCK_ConstantUImm5_Plus1_Report_UImm6: |
| 2890 | switch (B) { |
| 2891 | default: return false; |
| 2892 | case MCK_ConstantUImm5_32_Norm: return true; |
| 2893 | case MCK_ConstantUImm5_32: return true; |
| 2894 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2895 | case MCK_ConstantUImm5_33: return true; |
| 2896 | case MCK_ConstantUImmRange2_64: return true; |
| 2897 | case MCK_UImm5Lsl2: return true; |
| 2898 | case MCK_ConstantSImm6_0: return true; |
| 2899 | case MCK_ConstantUImm6_0: return true; |
| 2900 | case MCK_UImm6Lsl2: return true; |
| 2901 | case MCK_ConstantUImm7_0: return true; |
| 2902 | case MCK_UImm7_N1: return true; |
| 2903 | case MCK_ConstantUImm8_0: return true; |
| 2904 | case MCK_SImm7Lsl2: return true; |
| 2905 | case MCK_ConstantSImm9_0: return true; |
| 2906 | case MCK_ConstantSImm10_0: return true; |
| 2907 | case MCK_ConstantUImm10_0: return true; |
| 2908 | case MCK_SImm10Lsl1: return true; |
| 2909 | case MCK_ConstantSImm11_0: return true; |
| 2910 | case MCK_SImm10Lsl2: return true; |
| 2911 | case MCK_SImm10Lsl3: return true; |
| 2912 | case MCK_SImm16: return true; |
| 2913 | case MCK_SImm16_Relaxed: return true; |
| 2914 | case MCK_UImm16_Relaxed: return true; |
| 2915 | case MCK_ConstantUImm20_0: return true; |
| 2916 | case MCK_ConstantUImm26_0: return true; |
| 2917 | case MCK_SImm32: return true; |
| 2918 | case MCK_SImm32_Relaxed: return true; |
| 2919 | case MCK_UImm32_Coerced: return true; |
| 2920 | } |
| 2921 | |
| 2922 | case MCK_ConstantUImm5_32_Norm: |
| 2923 | switch (B) { |
| 2924 | default: return false; |
| 2925 | case MCK_ConstantUImm5_32: return true; |
| 2926 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2927 | case MCK_ConstantUImm5_33: return true; |
| 2928 | case MCK_ConstantUImmRange2_64: return true; |
| 2929 | case MCK_UImm5Lsl2: return true; |
| 2930 | case MCK_ConstantSImm6_0: return true; |
| 2931 | case MCK_ConstantUImm6_0: return true; |
| 2932 | case MCK_UImm6Lsl2: return true; |
| 2933 | case MCK_ConstantUImm7_0: return true; |
| 2934 | case MCK_UImm7_N1: return true; |
| 2935 | case MCK_ConstantUImm8_0: return true; |
| 2936 | case MCK_SImm7Lsl2: return true; |
| 2937 | case MCK_ConstantSImm9_0: return true; |
| 2938 | case MCK_ConstantSImm10_0: return true; |
| 2939 | case MCK_ConstantUImm10_0: return true; |
| 2940 | case MCK_SImm10Lsl1: return true; |
| 2941 | case MCK_ConstantSImm11_0: return true; |
| 2942 | case MCK_SImm10Lsl2: return true; |
| 2943 | case MCK_SImm10Lsl3: return true; |
| 2944 | case MCK_SImm16: return true; |
| 2945 | case MCK_SImm16_Relaxed: return true; |
| 2946 | case MCK_UImm16_Relaxed: return true; |
| 2947 | case MCK_ConstantUImm20_0: return true; |
| 2948 | case MCK_ConstantUImm26_0: return true; |
| 2949 | case MCK_SImm32: return true; |
| 2950 | case MCK_SImm32_Relaxed: return true; |
| 2951 | case MCK_UImm32_Coerced: return true; |
| 2952 | } |
| 2953 | |
| 2954 | case MCK_ConstantUImm5_32: |
| 2955 | switch (B) { |
| 2956 | default: return false; |
| 2957 | case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| 2958 | case MCK_ConstantUImm5_33: return true; |
| 2959 | case MCK_ConstantUImmRange2_64: return true; |
| 2960 | case MCK_UImm5Lsl2: return true; |
| 2961 | case MCK_ConstantSImm6_0: return true; |
| 2962 | case MCK_ConstantUImm6_0: return true; |
| 2963 | case MCK_UImm6Lsl2: return true; |
| 2964 | case MCK_ConstantUImm7_0: return true; |
| 2965 | case MCK_UImm7_N1: return true; |
| 2966 | case MCK_ConstantUImm8_0: return true; |
| 2967 | case MCK_SImm7Lsl2: return true; |
| 2968 | case MCK_ConstantSImm9_0: return true; |
| 2969 | case MCK_ConstantSImm10_0: return true; |
| 2970 | case MCK_ConstantUImm10_0: return true; |
| 2971 | case MCK_SImm10Lsl1: return true; |
| 2972 | case MCK_ConstantSImm11_0: return true; |
| 2973 | case MCK_SImm10Lsl2: return true; |
| 2974 | case MCK_SImm10Lsl3: return true; |
| 2975 | case MCK_SImm16: return true; |
| 2976 | case MCK_SImm16_Relaxed: return true; |
| 2977 | case MCK_UImm16_Relaxed: return true; |
| 2978 | case MCK_ConstantUImm20_0: return true; |
| 2979 | case MCK_ConstantUImm26_0: return true; |
| 2980 | case MCK_SImm32: return true; |
| 2981 | case MCK_SImm32_Relaxed: return true; |
| 2982 | case MCK_UImm32_Coerced: return true; |
| 2983 | } |
| 2984 | |
| 2985 | case MCK_ConstantUImm5_0_Report_UImm6: |
| 2986 | switch (B) { |
| 2987 | default: return false; |
| 2988 | case MCK_ConstantUImm5_33: return true; |
| 2989 | case MCK_ConstantUImmRange2_64: return true; |
| 2990 | case MCK_UImm5Lsl2: return true; |
| 2991 | case MCK_ConstantSImm6_0: return true; |
| 2992 | case MCK_ConstantUImm6_0: return true; |
| 2993 | case MCK_UImm6Lsl2: return true; |
| 2994 | case MCK_ConstantUImm7_0: return true; |
| 2995 | case MCK_UImm7_N1: return true; |
| 2996 | case MCK_ConstantUImm8_0: return true; |
| 2997 | case MCK_SImm7Lsl2: return true; |
| 2998 | case MCK_ConstantSImm9_0: return true; |
| 2999 | case MCK_ConstantSImm10_0: return true; |
| 3000 | case MCK_ConstantUImm10_0: return true; |
| 3001 | case MCK_SImm10Lsl1: return true; |
| 3002 | case MCK_ConstantSImm11_0: return true; |
| 3003 | case MCK_SImm10Lsl2: return true; |
| 3004 | case MCK_SImm10Lsl3: return true; |
| 3005 | case MCK_SImm16: return true; |
| 3006 | case MCK_SImm16_Relaxed: return true; |
| 3007 | case MCK_UImm16_Relaxed: return true; |
| 3008 | case MCK_ConstantUImm20_0: return true; |
| 3009 | case MCK_ConstantUImm26_0: return true; |
| 3010 | case MCK_SImm32: return true; |
| 3011 | case MCK_SImm32_Relaxed: return true; |
| 3012 | case MCK_UImm32_Coerced: return true; |
| 3013 | } |
| 3014 | |
| 3015 | case MCK_ConstantUImm5_33: |
| 3016 | switch (B) { |
| 3017 | default: return false; |
| 3018 | case MCK_ConstantUImmRange2_64: return true; |
| 3019 | case MCK_UImm5Lsl2: return true; |
| 3020 | case MCK_ConstantSImm6_0: return true; |
| 3021 | case MCK_ConstantUImm6_0: return true; |
| 3022 | case MCK_UImm6Lsl2: return true; |
| 3023 | case MCK_ConstantUImm7_0: return true; |
| 3024 | case MCK_UImm7_N1: return true; |
| 3025 | case MCK_ConstantUImm8_0: return true; |
| 3026 | case MCK_SImm7Lsl2: return true; |
| 3027 | case MCK_ConstantSImm9_0: return true; |
| 3028 | case MCK_ConstantSImm10_0: return true; |
| 3029 | case MCK_ConstantUImm10_0: return true; |
| 3030 | case MCK_SImm10Lsl1: return true; |
| 3031 | case MCK_ConstantSImm11_0: return true; |
| 3032 | case MCK_SImm10Lsl2: return true; |
| 3033 | case MCK_SImm10Lsl3: return true; |
| 3034 | case MCK_SImm16: return true; |
| 3035 | case MCK_SImm16_Relaxed: return true; |
| 3036 | case MCK_UImm16_Relaxed: return true; |
| 3037 | case MCK_ConstantUImm20_0: return true; |
| 3038 | case MCK_ConstantUImm26_0: return true; |
| 3039 | case MCK_SImm32: return true; |
| 3040 | case MCK_SImm32_Relaxed: return true; |
| 3041 | case MCK_UImm32_Coerced: return true; |
| 3042 | } |
| 3043 | |
| 3044 | case MCK_ConstantUImmRange2_64: |
| 3045 | switch (B) { |
| 3046 | default: return false; |
| 3047 | case MCK_UImm5Lsl2: return true; |
| 3048 | case MCK_ConstantSImm6_0: return true; |
| 3049 | case MCK_ConstantUImm6_0: return true; |
| 3050 | case MCK_UImm6Lsl2: return true; |
| 3051 | case MCK_ConstantUImm7_0: return true; |
| 3052 | case MCK_UImm7_N1: return true; |
| 3053 | case MCK_ConstantUImm8_0: return true; |
| 3054 | case MCK_SImm7Lsl2: return true; |
| 3055 | case MCK_ConstantSImm9_0: return true; |
| 3056 | case MCK_ConstantSImm10_0: return true; |
| 3057 | case MCK_ConstantUImm10_0: return true; |
| 3058 | case MCK_SImm10Lsl1: return true; |
| 3059 | case MCK_ConstantSImm11_0: return true; |
| 3060 | case MCK_SImm10Lsl2: return true; |
| 3061 | case MCK_SImm10Lsl3: return true; |
| 3062 | case MCK_SImm16: return true; |
| 3063 | case MCK_SImm16_Relaxed: return true; |
| 3064 | case MCK_UImm16_Relaxed: return true; |
| 3065 | case MCK_ConstantUImm20_0: return true; |
| 3066 | case MCK_ConstantUImm26_0: return true; |
| 3067 | case MCK_SImm32: return true; |
| 3068 | case MCK_SImm32_Relaxed: return true; |
| 3069 | case MCK_UImm32_Coerced: return true; |
| 3070 | } |
| 3071 | |
| 3072 | case MCK_UImm5Lsl2: |
| 3073 | switch (B) { |
| 3074 | default: return false; |
| 3075 | case MCK_ConstantSImm6_0: return true; |
| 3076 | case MCK_ConstantUImm6_0: return true; |
| 3077 | case MCK_UImm6Lsl2: return true; |
| 3078 | case MCK_ConstantUImm7_0: return true; |
| 3079 | case MCK_UImm7_N1: return true; |
| 3080 | case MCK_ConstantUImm8_0: return true; |
| 3081 | case MCK_SImm7Lsl2: return true; |
| 3082 | case MCK_ConstantSImm9_0: return true; |
| 3083 | case MCK_ConstantSImm10_0: return true; |
| 3084 | case MCK_ConstantUImm10_0: return true; |
| 3085 | case MCK_SImm10Lsl1: return true; |
| 3086 | case MCK_ConstantSImm11_0: return true; |
| 3087 | case MCK_SImm10Lsl2: return true; |
| 3088 | case MCK_SImm10Lsl3: return true; |
| 3089 | case MCK_SImm16: return true; |
| 3090 | case MCK_SImm16_Relaxed: return true; |
| 3091 | case MCK_UImm16_Relaxed: return true; |
| 3092 | case MCK_ConstantUImm20_0: return true; |
| 3093 | case MCK_ConstantUImm26_0: return true; |
| 3094 | case MCK_SImm32: return true; |
| 3095 | case MCK_SImm32_Relaxed: return true; |
| 3096 | case MCK_UImm32_Coerced: return true; |
| 3097 | } |
| 3098 | |
| 3099 | case MCK_ConstantSImm6_0: |
| 3100 | switch (B) { |
| 3101 | default: return false; |
| 3102 | case MCK_ConstantUImm6_0: return true; |
| 3103 | case MCK_UImm6Lsl2: return true; |
| 3104 | case MCK_ConstantUImm7_0: return true; |
| 3105 | case MCK_UImm7_N1: return true; |
| 3106 | case MCK_ConstantUImm8_0: return true; |
| 3107 | case MCK_SImm7Lsl2: return true; |
| 3108 | case MCK_ConstantSImm9_0: return true; |
| 3109 | case MCK_ConstantSImm10_0: return true; |
| 3110 | case MCK_ConstantUImm10_0: return true; |
| 3111 | case MCK_SImm10Lsl1: return true; |
| 3112 | case MCK_ConstantSImm11_0: return true; |
| 3113 | case MCK_SImm10Lsl2: return true; |
| 3114 | case MCK_SImm10Lsl3: return true; |
| 3115 | case MCK_SImm16: return true; |
| 3116 | case MCK_SImm16_Relaxed: return true; |
| 3117 | case MCK_UImm16_Relaxed: return true; |
| 3118 | case MCK_ConstantUImm20_0: return true; |
| 3119 | case MCK_ConstantUImm26_0: return true; |
| 3120 | case MCK_SImm32: return true; |
| 3121 | case MCK_SImm32_Relaxed: return true; |
| 3122 | case MCK_UImm32_Coerced: return true; |
| 3123 | } |
| 3124 | |
| 3125 | case MCK_ConstantUImm6_0: |
| 3126 | switch (B) { |
| 3127 | default: return false; |
| 3128 | case MCK_UImm6Lsl2: return true; |
| 3129 | case MCK_ConstantUImm7_0: return true; |
| 3130 | case MCK_UImm7_N1: return true; |
| 3131 | case MCK_ConstantUImm8_0: return true; |
| 3132 | case MCK_SImm7Lsl2: return true; |
| 3133 | case MCK_ConstantSImm9_0: return true; |
| 3134 | case MCK_ConstantSImm10_0: return true; |
| 3135 | case MCK_ConstantUImm10_0: return true; |
| 3136 | case MCK_SImm10Lsl1: return true; |
| 3137 | case MCK_ConstantSImm11_0: return true; |
| 3138 | case MCK_SImm10Lsl2: return true; |
| 3139 | case MCK_SImm10Lsl3: return true; |
| 3140 | case MCK_SImm16: return true; |
| 3141 | case MCK_SImm16_Relaxed: return true; |
| 3142 | case MCK_UImm16_Relaxed: return true; |
| 3143 | case MCK_ConstantUImm20_0: return true; |
| 3144 | case MCK_ConstantUImm26_0: return true; |
| 3145 | case MCK_SImm32: return true; |
| 3146 | case MCK_SImm32_Relaxed: return true; |
| 3147 | case MCK_UImm32_Coerced: return true; |
| 3148 | } |
| 3149 | |
| 3150 | case MCK_UImm6Lsl2: |
| 3151 | switch (B) { |
| 3152 | default: return false; |
| 3153 | case MCK_ConstantUImm7_0: return true; |
| 3154 | case MCK_UImm7_N1: return true; |
| 3155 | case MCK_ConstantUImm8_0: return true; |
| 3156 | case MCK_SImm7Lsl2: return true; |
| 3157 | case MCK_ConstantSImm9_0: return true; |
| 3158 | case MCK_ConstantSImm10_0: return true; |
| 3159 | case MCK_ConstantUImm10_0: return true; |
| 3160 | case MCK_SImm10Lsl1: return true; |
| 3161 | case MCK_ConstantSImm11_0: return true; |
| 3162 | case MCK_SImm10Lsl2: return true; |
| 3163 | case MCK_SImm10Lsl3: return true; |
| 3164 | case MCK_SImm16: return true; |
| 3165 | case MCK_SImm16_Relaxed: return true; |
| 3166 | case MCK_UImm16_Relaxed: return true; |
| 3167 | case MCK_ConstantUImm20_0: return true; |
| 3168 | case MCK_ConstantUImm26_0: return true; |
| 3169 | case MCK_SImm32: return true; |
| 3170 | case MCK_SImm32_Relaxed: return true; |
| 3171 | case MCK_UImm32_Coerced: return true; |
| 3172 | } |
| 3173 | |
| 3174 | case MCK_ConstantUImm7_0: |
| 3175 | switch (B) { |
| 3176 | default: return false; |
| 3177 | case MCK_UImm7_N1: return true; |
| 3178 | case MCK_ConstantUImm8_0: return true; |
| 3179 | case MCK_SImm7Lsl2: return true; |
| 3180 | case MCK_ConstantSImm9_0: return true; |
| 3181 | case MCK_ConstantSImm10_0: return true; |
| 3182 | case MCK_ConstantUImm10_0: return true; |
| 3183 | case MCK_SImm10Lsl1: return true; |
| 3184 | case MCK_ConstantSImm11_0: return true; |
| 3185 | case MCK_SImm10Lsl2: return true; |
| 3186 | case MCK_SImm10Lsl3: return true; |
| 3187 | case MCK_SImm16: return true; |
| 3188 | case MCK_SImm16_Relaxed: return true; |
| 3189 | case MCK_UImm16_Relaxed: return true; |
| 3190 | case MCK_ConstantUImm20_0: return true; |
| 3191 | case MCK_ConstantUImm26_0: return true; |
| 3192 | case MCK_SImm32: return true; |
| 3193 | case MCK_SImm32_Relaxed: return true; |
| 3194 | case MCK_UImm32_Coerced: return true; |
| 3195 | } |
| 3196 | |
| 3197 | case MCK_UImm7_N1: |
| 3198 | switch (B) { |
| 3199 | default: return false; |
| 3200 | case MCK_ConstantUImm8_0: return true; |
| 3201 | case MCK_SImm7Lsl2: return true; |
| 3202 | case MCK_ConstantSImm9_0: return true; |
| 3203 | case MCK_ConstantSImm10_0: return true; |
| 3204 | case MCK_ConstantUImm10_0: return true; |
| 3205 | case MCK_SImm10Lsl1: return true; |
| 3206 | case MCK_ConstantSImm11_0: return true; |
| 3207 | case MCK_SImm10Lsl2: return true; |
| 3208 | case MCK_SImm10Lsl3: return true; |
| 3209 | case MCK_SImm16: return true; |
| 3210 | case MCK_SImm16_Relaxed: return true; |
| 3211 | case MCK_UImm16_Relaxed: return true; |
| 3212 | case MCK_ConstantUImm20_0: return true; |
| 3213 | case MCK_ConstantUImm26_0: return true; |
| 3214 | case MCK_SImm32: return true; |
| 3215 | case MCK_SImm32_Relaxed: return true; |
| 3216 | case MCK_UImm32_Coerced: return true; |
| 3217 | } |
| 3218 | |
| 3219 | case MCK_ConstantUImm8_0: |
| 3220 | switch (B) { |
| 3221 | default: return false; |
| 3222 | case MCK_SImm7Lsl2: return true; |
| 3223 | case MCK_ConstantSImm9_0: return true; |
| 3224 | case MCK_ConstantSImm10_0: return true; |
| 3225 | case MCK_ConstantUImm10_0: return true; |
| 3226 | case MCK_SImm10Lsl1: return true; |
| 3227 | case MCK_ConstantSImm11_0: return true; |
| 3228 | case MCK_SImm10Lsl2: return true; |
| 3229 | case MCK_SImm10Lsl3: return true; |
| 3230 | case MCK_SImm16: return true; |
| 3231 | case MCK_SImm16_Relaxed: return true; |
| 3232 | case MCK_UImm16_Relaxed: return true; |
| 3233 | case MCK_ConstantUImm20_0: return true; |
| 3234 | case MCK_ConstantUImm26_0: return true; |
| 3235 | case MCK_SImm32: return true; |
| 3236 | case MCK_SImm32_Relaxed: return true; |
| 3237 | case MCK_UImm32_Coerced: return true; |
| 3238 | } |
| 3239 | |
| 3240 | case MCK_SImm7Lsl2: |
| 3241 | switch (B) { |
| 3242 | default: return false; |
| 3243 | case MCK_ConstantSImm9_0: return true; |
| 3244 | case MCK_ConstantSImm10_0: return true; |
| 3245 | case MCK_ConstantUImm10_0: return true; |
| 3246 | case MCK_SImm10Lsl1: return true; |
| 3247 | case MCK_ConstantSImm11_0: return true; |
| 3248 | case MCK_SImm10Lsl2: return true; |
| 3249 | case MCK_SImm10Lsl3: return true; |
| 3250 | case MCK_SImm16: return true; |
| 3251 | case MCK_SImm16_Relaxed: return true; |
| 3252 | case MCK_UImm16_Relaxed: return true; |
| 3253 | case MCK_ConstantUImm20_0: return true; |
| 3254 | case MCK_ConstantUImm26_0: return true; |
| 3255 | case MCK_SImm32: return true; |
| 3256 | case MCK_SImm32_Relaxed: return true; |
| 3257 | case MCK_UImm32_Coerced: return true; |
| 3258 | } |
| 3259 | |
| 3260 | case MCK_ConstantSImm9_0: |
| 3261 | switch (B) { |
| 3262 | default: return false; |
| 3263 | case MCK_ConstantSImm10_0: return true; |
| 3264 | case MCK_ConstantUImm10_0: return true; |
| 3265 | case MCK_SImm10Lsl1: return true; |
| 3266 | case MCK_ConstantSImm11_0: return true; |
| 3267 | case MCK_SImm10Lsl2: return true; |
| 3268 | case MCK_SImm10Lsl3: return true; |
| 3269 | case MCK_SImm16: return true; |
| 3270 | case MCK_SImm16_Relaxed: return true; |
| 3271 | case MCK_UImm16_Relaxed: return true; |
| 3272 | case MCK_ConstantUImm20_0: return true; |
| 3273 | case MCK_ConstantUImm26_0: return true; |
| 3274 | case MCK_SImm32: return true; |
| 3275 | case MCK_SImm32_Relaxed: return true; |
| 3276 | case MCK_UImm32_Coerced: return true; |
| 3277 | } |
| 3278 | |
| 3279 | case MCK_ConstantSImm10_0: |
| 3280 | switch (B) { |
| 3281 | default: return false; |
| 3282 | case MCK_ConstantUImm10_0: return true; |
| 3283 | case MCK_SImm10Lsl1: return true; |
| 3284 | case MCK_ConstantSImm11_0: return true; |
| 3285 | case MCK_SImm10Lsl2: return true; |
| 3286 | case MCK_SImm10Lsl3: return true; |
| 3287 | case MCK_SImm16: return true; |
| 3288 | case MCK_SImm16_Relaxed: return true; |
| 3289 | case MCK_UImm16_Relaxed: return true; |
| 3290 | case MCK_ConstantUImm20_0: return true; |
| 3291 | case MCK_ConstantUImm26_0: return true; |
| 3292 | case MCK_SImm32: return true; |
| 3293 | case MCK_SImm32_Relaxed: return true; |
| 3294 | case MCK_UImm32_Coerced: return true; |
| 3295 | } |
| 3296 | |
| 3297 | case MCK_ConstantUImm10_0: |
| 3298 | switch (B) { |
| 3299 | default: return false; |
| 3300 | case MCK_SImm10Lsl1: return true; |
| 3301 | case MCK_ConstantSImm11_0: return true; |
| 3302 | case MCK_SImm10Lsl2: return true; |
| 3303 | case MCK_SImm10Lsl3: return true; |
| 3304 | case MCK_SImm16: return true; |
| 3305 | case MCK_SImm16_Relaxed: return true; |
| 3306 | case MCK_UImm16_Relaxed: return true; |
| 3307 | case MCK_ConstantUImm20_0: return true; |
| 3308 | case MCK_ConstantUImm26_0: return true; |
| 3309 | case MCK_SImm32: return true; |
| 3310 | case MCK_SImm32_Relaxed: return true; |
| 3311 | case MCK_UImm32_Coerced: return true; |
| 3312 | } |
| 3313 | |
| 3314 | case MCK_SImm10Lsl1: |
| 3315 | switch (B) { |
| 3316 | default: return false; |
| 3317 | case MCK_ConstantSImm11_0: return true; |
| 3318 | case MCK_SImm10Lsl2: return true; |
| 3319 | case MCK_SImm10Lsl3: return true; |
| 3320 | case MCK_SImm16: return true; |
| 3321 | case MCK_SImm16_Relaxed: return true; |
| 3322 | case MCK_UImm16_Relaxed: return true; |
| 3323 | case MCK_ConstantUImm20_0: return true; |
| 3324 | case MCK_ConstantUImm26_0: return true; |
| 3325 | case MCK_SImm32: return true; |
| 3326 | case MCK_SImm32_Relaxed: return true; |
| 3327 | case MCK_UImm32_Coerced: return true; |
| 3328 | } |
| 3329 | |
| 3330 | case MCK_ConstantSImm11_0: |
| 3331 | switch (B) { |
| 3332 | default: return false; |
| 3333 | case MCK_SImm10Lsl2: return true; |
| 3334 | case MCK_SImm10Lsl3: return true; |
| 3335 | case MCK_SImm16: return true; |
| 3336 | case MCK_SImm16_Relaxed: return true; |
| 3337 | case MCK_UImm16_Relaxed: return true; |
| 3338 | case MCK_ConstantUImm20_0: return true; |
| 3339 | case MCK_ConstantUImm26_0: return true; |
| 3340 | case MCK_SImm32: return true; |
| 3341 | case MCK_SImm32_Relaxed: return true; |
| 3342 | case MCK_UImm32_Coerced: return true; |
| 3343 | } |
| 3344 | |
| 3345 | case MCK_SImm10Lsl2: |
| 3346 | switch (B) { |
| 3347 | default: return false; |
| 3348 | case MCK_SImm10Lsl3: return true; |
| 3349 | case MCK_SImm16: return true; |
| 3350 | case MCK_SImm16_Relaxed: return true; |
| 3351 | case MCK_UImm16_Relaxed: return true; |
| 3352 | case MCK_ConstantUImm20_0: return true; |
| 3353 | case MCK_ConstantUImm26_0: return true; |
| 3354 | case MCK_SImm32: return true; |
| 3355 | case MCK_SImm32_Relaxed: return true; |
| 3356 | case MCK_UImm32_Coerced: return true; |
| 3357 | } |
| 3358 | |
| 3359 | case MCK_SImm10Lsl3: |
| 3360 | switch (B) { |
| 3361 | default: return false; |
| 3362 | case MCK_SImm16: return true; |
| 3363 | case MCK_SImm16_Relaxed: return true; |
| 3364 | case MCK_UImm16_Relaxed: return true; |
| 3365 | case MCK_ConstantUImm20_0: return true; |
| 3366 | case MCK_ConstantUImm26_0: return true; |
| 3367 | case MCK_SImm32: return true; |
| 3368 | case MCK_SImm32_Relaxed: return true; |
| 3369 | case MCK_UImm32_Coerced: return true; |
| 3370 | } |
| 3371 | |
| 3372 | case MCK_SImm16: |
| 3373 | switch (B) { |
| 3374 | default: return false; |
| 3375 | case MCK_SImm16_Relaxed: return true; |
| 3376 | case MCK_UImm16_Relaxed: return true; |
| 3377 | case MCK_ConstantUImm20_0: return true; |
| 3378 | case MCK_ConstantUImm26_0: return true; |
| 3379 | case MCK_SImm32: return true; |
| 3380 | case MCK_SImm32_Relaxed: return true; |
| 3381 | case MCK_UImm32_Coerced: return true; |
| 3382 | } |
| 3383 | |
| 3384 | case MCK_SImm16_Relaxed: |
| 3385 | switch (B) { |
| 3386 | default: return false; |
| 3387 | case MCK_UImm16_Relaxed: return true; |
| 3388 | case MCK_ConstantUImm20_0: return true; |
| 3389 | case MCK_ConstantUImm26_0: return true; |
| 3390 | case MCK_SImm32: return true; |
| 3391 | case MCK_SImm32_Relaxed: return true; |
| 3392 | case MCK_UImm32_Coerced: return true; |
| 3393 | } |
| 3394 | |
| 3395 | case MCK_UImm16_AltRelaxed: |
| 3396 | switch (B) { |
| 3397 | default: return false; |
| 3398 | case MCK_UImm16_Relaxed: return true; |
| 3399 | case MCK_ConstantUImm20_0: return true; |
| 3400 | case MCK_ConstantUImm26_0: return true; |
| 3401 | case MCK_SImm32: return true; |
| 3402 | case MCK_SImm32_Relaxed: return true; |
| 3403 | case MCK_UImm32_Coerced: return true; |
| 3404 | } |
| 3405 | |
| 3406 | case MCK_UImm16: |
| 3407 | switch (B) { |
| 3408 | default: return false; |
| 3409 | case MCK_UImm16_Relaxed: return true; |
| 3410 | case MCK_ConstantUImm20_0: return true; |
| 3411 | case MCK_ConstantUImm26_0: return true; |
| 3412 | case MCK_SImm32: return true; |
| 3413 | case MCK_SImm32_Relaxed: return true; |
| 3414 | case MCK_UImm32_Coerced: return true; |
| 3415 | } |
| 3416 | |
| 3417 | case MCK_SImm19Lsl2: |
| 3418 | switch (B) { |
| 3419 | default: return false; |
| 3420 | case MCK_ConstantUImm20_0: return true; |
| 3421 | case MCK_ConstantUImm26_0: return true; |
| 3422 | case MCK_SImm32: return true; |
| 3423 | case MCK_SImm32_Relaxed: return true; |
| 3424 | case MCK_UImm32_Coerced: return true; |
| 3425 | } |
| 3426 | |
| 3427 | case MCK_UImm16_Relaxed: |
| 3428 | switch (B) { |
| 3429 | default: return false; |
| 3430 | case MCK_ConstantUImm20_0: return true; |
| 3431 | case MCK_ConstantUImm26_0: return true; |
| 3432 | case MCK_SImm32: return true; |
| 3433 | case MCK_SImm32_Relaxed: return true; |
| 3434 | case MCK_UImm32_Coerced: return true; |
| 3435 | } |
| 3436 | |
| 3437 | case MCK_ConstantUImm20_0: |
| 3438 | switch (B) { |
| 3439 | default: return false; |
| 3440 | case MCK_ConstantUImm26_0: return true; |
| 3441 | case MCK_SImm32: return true; |
| 3442 | case MCK_SImm32_Relaxed: return true; |
| 3443 | case MCK_UImm32_Coerced: return true; |
| 3444 | } |
| 3445 | |
| 3446 | case MCK_ConstantUImm26_0: |
| 3447 | switch (B) { |
| 3448 | default: return false; |
| 3449 | case MCK_SImm32: return true; |
| 3450 | case MCK_SImm32_Relaxed: return true; |
| 3451 | case MCK_UImm32_Coerced: return true; |
| 3452 | } |
| 3453 | |
| 3454 | case MCK_SImm32: |
| 3455 | switch (B) { |
| 3456 | default: return false; |
| 3457 | case MCK_SImm32_Relaxed: return true; |
| 3458 | case MCK_UImm32_Coerced: return true; |
| 3459 | } |
| 3460 | |
| 3461 | case MCK_SImm32_Relaxed: |
| 3462 | return B == MCK_UImm32_Coerced; |
| 3463 | } |
| 3464 | } |
| 3465 | |
| 3466 | static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { |
| 3467 | MipsOperand &Operand = (MipsOperand &)GOp; |
| 3468 | if (Kind == InvalidMatchClass) |
| 3469 | return MCTargetAsmParser::Match_InvalidOperand; |
| 3470 | |
| 3471 | if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) |
| 3472 | return isSubclass(matchTokenString(Operand.getToken()), Kind) ? |
| 3473 | MCTargetAsmParser::Match_Success : |
| 3474 | MCTargetAsmParser::Match_InvalidOperand; |
| 3475 | |
| 3476 | switch (Kind) { |
| 3477 | default: break; |
| 3478 | // 'ACC64DSPAsmReg' class |
| 3479 | case MCK_ACC64DSPAsmReg: { |
| 3480 | DiagnosticPredicate DP(Operand.isACCAsmReg()); |
| 3481 | if (DP.isMatch()) |
| 3482 | return MCTargetAsmParser::Match_Success; |
| 3483 | break; |
| 3484 | } |
| 3485 | // 'AFGR64AsmReg' class |
| 3486 | case MCK_AFGR64AsmReg: { |
| 3487 | DiagnosticPredicate DP(Operand.isFGRAsmReg()); |
| 3488 | if (DP.isMatch()) |
| 3489 | return MCTargetAsmParser::Match_Success; |
| 3490 | break; |
| 3491 | } |
| 3492 | // 'CCRAsmReg' class |
| 3493 | case MCK_CCRAsmReg: { |
| 3494 | DiagnosticPredicate DP(Operand.isCCRAsmReg()); |
| 3495 | if (DP.isMatch()) |
| 3496 | return MCTargetAsmParser::Match_Success; |
| 3497 | break; |
| 3498 | } |
| 3499 | // 'COP0AsmReg' class |
| 3500 | case MCK_COP0AsmReg: { |
| 3501 | DiagnosticPredicate DP(Operand.isCOP0AsmReg()); |
| 3502 | if (DP.isMatch()) |
| 3503 | return MCTargetAsmParser::Match_Success; |
| 3504 | break; |
| 3505 | } |
| 3506 | // 'COP2AsmReg' class |
| 3507 | case MCK_COP2AsmReg: { |
| 3508 | DiagnosticPredicate DP(Operand.isCOP2AsmReg()); |
| 3509 | if (DP.isMatch()) |
| 3510 | return MCTargetAsmParser::Match_Success; |
| 3511 | break; |
| 3512 | } |
| 3513 | // 'COP3AsmReg' class |
| 3514 | case MCK_COP3AsmReg: { |
| 3515 | DiagnosticPredicate DP(Operand.isCOP3AsmReg()); |
| 3516 | if (DP.isMatch()) |
| 3517 | return MCTargetAsmParser::Match_Success; |
| 3518 | break; |
| 3519 | } |
| 3520 | // 'FCCAsmReg' class |
| 3521 | case MCK_FCCAsmReg: { |
| 3522 | DiagnosticPredicate DP(Operand.isFCCAsmReg()); |
| 3523 | if (DP.isMatch()) |
| 3524 | return MCTargetAsmParser::Match_Success; |
| 3525 | break; |
| 3526 | } |
| 3527 | // 'FGR32AsmReg' class |
| 3528 | case MCK_FGR32AsmReg: { |
| 3529 | DiagnosticPredicate DP(Operand.isFGRAsmReg()); |
| 3530 | if (DP.isMatch()) |
| 3531 | return MCTargetAsmParser::Match_Success; |
| 3532 | break; |
| 3533 | } |
| 3534 | // 'FGR64AsmReg' class |
| 3535 | case MCK_FGR64AsmReg: { |
| 3536 | DiagnosticPredicate DP(Operand.isFGRAsmReg()); |
| 3537 | if (DP.isMatch()) |
| 3538 | return MCTargetAsmParser::Match_Success; |
| 3539 | break; |
| 3540 | } |
| 3541 | // 'GPR32AsmReg' class |
| 3542 | case MCK_GPR32AsmReg: { |
| 3543 | DiagnosticPredicate DP(Operand.isGPRAsmReg()); |
| 3544 | if (DP.isMatch()) |
| 3545 | return MCTargetAsmParser::Match_Success; |
| 3546 | break; |
| 3547 | } |
| 3548 | // 'GPR32NonZeroAsmReg' class |
| 3549 | case MCK_GPR32NonZeroAsmReg: { |
| 3550 | DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg()); |
| 3551 | if (DP.isMatch()) |
| 3552 | return MCTargetAsmParser::Match_Success; |
| 3553 | break; |
| 3554 | } |
| 3555 | // 'GPR32ZeroAsmReg' class |
| 3556 | case MCK_GPR32ZeroAsmReg: { |
| 3557 | DiagnosticPredicate DP(Operand.isGPRZeroAsmReg()); |
| 3558 | if (DP.isMatch()) |
| 3559 | return MCTargetAsmParser::Match_Success; |
| 3560 | break; |
| 3561 | } |
| 3562 | // 'GPR64AsmReg' class |
| 3563 | case MCK_GPR64AsmReg: { |
| 3564 | DiagnosticPredicate DP(Operand.isGPRAsmReg()); |
| 3565 | if (DP.isMatch()) |
| 3566 | return MCTargetAsmParser::Match_Success; |
| 3567 | break; |
| 3568 | } |
| 3569 | // 'GPRMM16AsmReg' class |
| 3570 | case MCK_GPRMM16AsmReg: { |
| 3571 | DiagnosticPredicate DP(Operand.isMM16AsmReg()); |
| 3572 | if (DP.isMatch()) |
| 3573 | return MCTargetAsmParser::Match_Success; |
| 3574 | break; |
| 3575 | } |
| 3576 | // 'GPRMM16AsmRegMoveP' class |
| 3577 | case MCK_GPRMM16AsmRegMoveP: { |
| 3578 | DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP()); |
| 3579 | if (DP.isMatch()) |
| 3580 | return MCTargetAsmParser::Match_Success; |
| 3581 | break; |
| 3582 | } |
| 3583 | // 'GPRMM16AsmRegMovePPairFirst' class |
| 3584 | case MCK_GPRMM16AsmRegMovePPairFirst: { |
| 3585 | DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst()); |
| 3586 | if (DP.isMatch()) |
| 3587 | return MCTargetAsmParser::Match_Success; |
| 3588 | break; |
| 3589 | } |
| 3590 | // 'GPRMM16AsmRegMovePPairSecond' class |
| 3591 | case MCK_GPRMM16AsmRegMovePPairSecond: { |
| 3592 | DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond()); |
| 3593 | if (DP.isMatch()) |
| 3594 | return MCTargetAsmParser::Match_Success; |
| 3595 | break; |
| 3596 | } |
| 3597 | // 'GPRMM16AsmRegZero' class |
| 3598 | case MCK_GPRMM16AsmRegZero: { |
| 3599 | DiagnosticPredicate DP(Operand.isMM16AsmRegZero()); |
| 3600 | if (DP.isMatch()) |
| 3601 | return MCTargetAsmParser::Match_Success; |
| 3602 | break; |
| 3603 | } |
| 3604 | // 'HI32DSPAsmReg' class |
| 3605 | case MCK_HI32DSPAsmReg: { |
| 3606 | DiagnosticPredicate DP(Operand.isACCAsmReg()); |
| 3607 | if (DP.isMatch()) |
| 3608 | return MCTargetAsmParser::Match_Success; |
| 3609 | break; |
| 3610 | } |
| 3611 | // 'HWRegsAsmReg' class |
| 3612 | case MCK_HWRegsAsmReg: { |
| 3613 | DiagnosticPredicate DP(Operand.isHWRegsAsmReg()); |
| 3614 | if (DP.isMatch()) |
| 3615 | return MCTargetAsmParser::Match_Success; |
| 3616 | break; |
| 3617 | } |
| 3618 | // 'Imm' class |
| 3619 | case MCK_Imm: { |
| 3620 | DiagnosticPredicate DP(Operand.isImm()); |
| 3621 | if (DP.isMatch()) |
| 3622 | return MCTargetAsmParser::Match_Success; |
| 3623 | break; |
| 3624 | } |
| 3625 | // 'LO32DSPAsmReg' class |
| 3626 | case MCK_LO32DSPAsmReg: { |
| 3627 | DiagnosticPredicate DP(Operand.isACCAsmReg()); |
| 3628 | if (DP.isMatch()) |
| 3629 | return MCTargetAsmParser::Match_Success; |
| 3630 | break; |
| 3631 | } |
| 3632 | // 'MSA128AsmReg' class |
| 3633 | case MCK_MSA128AsmReg: { |
| 3634 | DiagnosticPredicate DP(Operand.isMSA128AsmReg()); |
| 3635 | if (DP.isMatch()) |
| 3636 | return MCTargetAsmParser::Match_Success; |
| 3637 | break; |
| 3638 | } |
| 3639 | // 'MSACtrlAsmReg' class |
| 3640 | case MCK_MSACtrlAsmReg: { |
| 3641 | DiagnosticPredicate DP(Operand.isMSACtrlAsmReg()); |
| 3642 | if (DP.isMatch()) |
| 3643 | return MCTargetAsmParser::Match_Success; |
| 3644 | break; |
| 3645 | } |
| 3646 | // 'MicroMipsMemGP' class |
| 3647 | case MCK_MicroMipsMemGP: { |
| 3648 | DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>()); |
| 3649 | if (DP.isMatch()) |
| 3650 | return MCTargetAsmParser::Match_Success; |
| 3651 | break; |
| 3652 | } |
| 3653 | // 'MicroMipsMem' class |
| 3654 | case MCK_MicroMipsMem: { |
| 3655 | DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base()); |
| 3656 | if (DP.isMatch()) |
| 3657 | return MCTargetAsmParser::Match_Success; |
| 3658 | break; |
| 3659 | } |
| 3660 | // 'MicroMipsMemSP' class |
| 3661 | case MCK_MicroMipsMemSP: { |
| 3662 | DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>()); |
| 3663 | if (DP.isMatch()) |
| 3664 | return MCTargetAsmParser::Match_Success; |
| 3665 | break; |
| 3666 | } |
| 3667 | // 'InvNum' class |
| 3668 | case MCK_InvNum: { |
| 3669 | DiagnosticPredicate DP(Operand.isInvNum()); |
| 3670 | if (DP.isMatch()) |
| 3671 | return MCTargetAsmParser::Match_Success; |
| 3672 | break; |
| 3673 | } |
| 3674 | // 'JumpTarget' class |
| 3675 | case MCK_JumpTarget: { |
| 3676 | DiagnosticPredicate DP(Operand.isImm()); |
| 3677 | if (DP.isMatch()) |
| 3678 | return MCTargetAsmParser::Match_Success; |
| 3679 | break; |
| 3680 | } |
| 3681 | // 'MemOffsetSimmPtr' class |
| 3682 | case MCK_MemOffsetSimmPtr: { |
| 3683 | DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset()); |
| 3684 | if (DP.isMatch()) |
| 3685 | return MCTargetAsmParser::Match_Success; |
| 3686 | if (DP.isNearMatch()) |
| 3687 | return MipsAsmParser::Match_MemSImmPtr; |
| 3688 | break; |
| 3689 | } |
| 3690 | // 'MemOffsetUimm4' class |
| 3691 | case MCK_MemOffsetUimm4: { |
| 3692 | DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>()); |
| 3693 | if (DP.isMatch()) |
| 3694 | return MCTargetAsmParser::Match_Success; |
| 3695 | break; |
| 3696 | } |
| 3697 | // 'MemOffsetSimm9_0' class |
| 3698 | case MCK_MemOffsetSimm9_0: { |
| 3699 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9, 0>()); |
| 3700 | if (DP.isMatch()) |
| 3701 | return MCTargetAsmParser::Match_Success; |
| 3702 | if (DP.isNearMatch()) |
| 3703 | return MipsAsmParser::Match_MemSImm9; |
| 3704 | break; |
| 3705 | } |
| 3706 | // 'MemOffsetSimm10_0' class |
| 3707 | case MCK_MemOffsetSimm10_0: { |
| 3708 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 0>()); |
| 3709 | if (DP.isMatch()) |
| 3710 | return MCTargetAsmParser::Match_Success; |
| 3711 | if (DP.isNearMatch()) |
| 3712 | return MipsAsmParser::Match_MemSImm10; |
| 3713 | break; |
| 3714 | } |
| 3715 | // 'MemOffsetSimm11_0' class |
| 3716 | case MCK_MemOffsetSimm11_0: { |
| 3717 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11, 0>()); |
| 3718 | if (DP.isMatch()) |
| 3719 | return MCTargetAsmParser::Match_Success; |
| 3720 | if (DP.isNearMatch()) |
| 3721 | return MipsAsmParser::Match_MemSImm11; |
| 3722 | break; |
| 3723 | } |
| 3724 | // 'MemOffsetSimm12_0' class |
| 3725 | case MCK_MemOffsetSimm12_0: { |
| 3726 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12, 0>()); |
| 3727 | if (DP.isMatch()) |
| 3728 | return MCTargetAsmParser::Match_Success; |
| 3729 | if (DP.isNearMatch()) |
| 3730 | return MipsAsmParser::Match_MemSImm12; |
| 3731 | break; |
| 3732 | } |
| 3733 | // 'MemOffsetSimm16_0' class |
| 3734 | case MCK_MemOffsetSimm16_0: { |
| 3735 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16, 0>()); |
| 3736 | if (DP.isMatch()) |
| 3737 | return MCTargetAsmParser::Match_Success; |
| 3738 | if (DP.isNearMatch()) |
| 3739 | return MipsAsmParser::Match_MemSImm16; |
| 3740 | break; |
| 3741 | } |
| 3742 | // 'MemOffsetSimm10_1' class |
| 3743 | case MCK_MemOffsetSimm10_1: { |
| 3744 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>()); |
| 3745 | if (DP.isMatch()) |
| 3746 | return MCTargetAsmParser::Match_Success; |
| 3747 | if (DP.isNearMatch()) |
| 3748 | return MipsAsmParser::Match_MemSImm10Lsl1; |
| 3749 | break; |
| 3750 | } |
| 3751 | // 'MemOffsetSimm10_2' class |
| 3752 | case MCK_MemOffsetSimm10_2: { |
| 3753 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>()); |
| 3754 | if (DP.isMatch()) |
| 3755 | return MCTargetAsmParser::Match_Success; |
| 3756 | if (DP.isNearMatch()) |
| 3757 | return MipsAsmParser::Match_MemSImm10Lsl2; |
| 3758 | break; |
| 3759 | } |
| 3760 | // 'MemOffsetSimm10_3' class |
| 3761 | case MCK_MemOffsetSimm10_3: { |
| 3762 | DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>()); |
| 3763 | if (DP.isMatch()) |
| 3764 | return MCTargetAsmParser::Match_Success; |
| 3765 | if (DP.isNearMatch()) |
| 3766 | return MipsAsmParser::Match_MemSImm10Lsl3; |
| 3767 | break; |
| 3768 | } |
| 3769 | // 'Mem' class |
| 3770 | case MCK_Mem: { |
| 3771 | DiagnosticPredicate DP(Operand.isMem()); |
| 3772 | if (DP.isMatch()) |
| 3773 | return MCTargetAsmParser::Match_Success; |
| 3774 | break; |
| 3775 | } |
| 3776 | // 'RegList16' class |
| 3777 | case MCK_RegList16: { |
| 3778 | DiagnosticPredicate DP(Operand.isRegList16()); |
| 3779 | if (DP.isMatch()) |
| 3780 | return MCTargetAsmParser::Match_Success; |
| 3781 | break; |
| 3782 | } |
| 3783 | // 'RegList' class |
| 3784 | case MCK_RegList: { |
| 3785 | DiagnosticPredicate DP(Operand.isRegList()); |
| 3786 | if (DP.isMatch()) |
| 3787 | return MCTargetAsmParser::Match_Success; |
| 3788 | break; |
| 3789 | } |
| 3790 | // 'Simm19_Lsl2' class |
| 3791 | case MCK_Simm19_Lsl2: { |
| 3792 | DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); |
| 3793 | if (DP.isMatch()) |
| 3794 | return MCTargetAsmParser::Match_Success; |
| 3795 | if (DP.isNearMatch()) |
| 3796 | return MipsAsmParser::Match_SImm19_Lsl2; |
| 3797 | break; |
| 3798 | } |
| 3799 | // 'StrictlyAFGR64AsmReg' class |
| 3800 | case MCK_StrictlyAFGR64AsmReg: { |
| 3801 | DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); |
| 3802 | if (DP.isMatch()) |
| 3803 | return MCTargetAsmParser::Match_Success; |
| 3804 | break; |
| 3805 | } |
| 3806 | // 'StrictlyFGR32AsmReg' class |
| 3807 | case MCK_StrictlyFGR32AsmReg: { |
| 3808 | DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); |
| 3809 | if (DP.isMatch()) |
| 3810 | return MCTargetAsmParser::Match_Success; |
| 3811 | break; |
| 3812 | } |
| 3813 | // 'StrictlyFGR64AsmReg' class |
| 3814 | case MCK_StrictlyFGR64AsmReg: { |
| 3815 | DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); |
| 3816 | if (DP.isMatch()) |
| 3817 | return MCTargetAsmParser::Match_Success; |
| 3818 | break; |
| 3819 | } |
| 3820 | // 'ConstantImmz' class |
| 3821 | case MCK_ConstantImmz: { |
| 3822 | DiagnosticPredicate DP(Operand.isConstantImmz()); |
| 3823 | if (DP.isMatch()) |
| 3824 | return MCTargetAsmParser::Match_Success; |
| 3825 | if (DP.isNearMatch()) |
| 3826 | return MipsAsmParser::Match_Immz; |
| 3827 | break; |
| 3828 | } |
| 3829 | // 'ConstantUImm1_0' class |
| 3830 | case MCK_ConstantUImm1_0: { |
| 3831 | DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>()); |
| 3832 | if (DP.isMatch()) |
| 3833 | return MCTargetAsmParser::Match_Success; |
| 3834 | if (DP.isNearMatch()) |
| 3835 | return MipsAsmParser::Match_UImm1_0; |
| 3836 | break; |
| 3837 | } |
| 3838 | // 'ConstantUImm2_0' class |
| 3839 | case MCK_ConstantUImm2_0: { |
| 3840 | DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>()); |
| 3841 | if (DP.isMatch()) |
| 3842 | return MCTargetAsmParser::Match_Success; |
| 3843 | if (DP.isNearMatch()) |
| 3844 | return MipsAsmParser::Match_UImm2_0; |
| 3845 | break; |
| 3846 | } |
| 3847 | // 'ConstantUImm2_1' class |
| 3848 | case MCK_ConstantUImm2_1: { |
| 3849 | DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>()); |
| 3850 | if (DP.isMatch()) |
| 3851 | return MCTargetAsmParser::Match_Success; |
| 3852 | if (DP.isNearMatch()) |
| 3853 | return MipsAsmParser::Match_UImm2_1; |
| 3854 | break; |
| 3855 | } |
| 3856 | // 'ConstantUImm3_0' class |
| 3857 | case MCK_ConstantUImm3_0: { |
| 3858 | DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>()); |
| 3859 | if (DP.isMatch()) |
| 3860 | return MCTargetAsmParser::Match_Success; |
| 3861 | if (DP.isNearMatch()) |
| 3862 | return MipsAsmParser::Match_UImm3_0; |
| 3863 | break; |
| 3864 | } |
| 3865 | // 'ConstantSImm4_0' class |
| 3866 | case MCK_ConstantSImm4_0: { |
| 3867 | DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>()); |
| 3868 | if (DP.isMatch()) |
| 3869 | return MCTargetAsmParser::Match_Success; |
| 3870 | if (DP.isNearMatch()) |
| 3871 | return MipsAsmParser::Match_SImm4_0; |
| 3872 | break; |
| 3873 | } |
| 3874 | // 'ConstantUImm4_0' class |
| 3875 | case MCK_ConstantUImm4_0: { |
| 3876 | DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>()); |
| 3877 | if (DP.isMatch()) |
| 3878 | return MCTargetAsmParser::Match_Success; |
| 3879 | if (DP.isNearMatch()) |
| 3880 | return MipsAsmParser::Match_UImm4_0; |
| 3881 | break; |
| 3882 | } |
| 3883 | // 'ConstantSImm5_0' class |
| 3884 | case MCK_ConstantSImm5_0: { |
| 3885 | DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>()); |
| 3886 | if (DP.isMatch()) |
| 3887 | return MCTargetAsmParser::Match_Success; |
| 3888 | if (DP.isNearMatch()) |
| 3889 | return MipsAsmParser::Match_SImm5_0; |
| 3890 | break; |
| 3891 | } |
| 3892 | // 'ConstantUImm5_0' class |
| 3893 | case MCK_ConstantUImm5_0: { |
| 3894 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); |
| 3895 | if (DP.isMatch()) |
| 3896 | return MCTargetAsmParser::Match_Success; |
| 3897 | if (DP.isNearMatch()) |
| 3898 | return MipsAsmParser::Match_UImm5_0; |
| 3899 | break; |
| 3900 | } |
| 3901 | // 'ConstantUImm5_1' class |
| 3902 | case MCK_ConstantUImm5_1: { |
| 3903 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); |
| 3904 | if (DP.isMatch()) |
| 3905 | return MCTargetAsmParser::Match_Success; |
| 3906 | if (DP.isNearMatch()) |
| 3907 | return MipsAsmParser::Match_UImm5_1; |
| 3908 | break; |
| 3909 | } |
| 3910 | // 'ConstantUImm5_Plus1_Report_UImm6' class |
| 3911 | case MCK_ConstantUImm5_Plus1_Report_UImm6: { |
| 3912 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); |
| 3913 | if (DP.isMatch()) |
| 3914 | return MCTargetAsmParser::Match_Success; |
| 3915 | if (DP.isNearMatch()) |
| 3916 | return MipsAsmParser::Match_UImm5_1; |
| 3917 | break; |
| 3918 | } |
| 3919 | // 'ConstantUImm5_32_Norm' class |
| 3920 | case MCK_ConstantUImm5_32_Norm: { |
| 3921 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); |
| 3922 | if (DP.isMatch()) |
| 3923 | return MCTargetAsmParser::Match_Success; |
| 3924 | if (DP.isNearMatch()) |
| 3925 | return MipsAsmParser::Match_UImm5_32; |
| 3926 | break; |
| 3927 | } |
| 3928 | // 'ConstantUImm5_32' class |
| 3929 | case MCK_ConstantUImm5_32: { |
| 3930 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); |
| 3931 | if (DP.isMatch()) |
| 3932 | return MCTargetAsmParser::Match_Success; |
| 3933 | if (DP.isNearMatch()) |
| 3934 | return MipsAsmParser::Match_UImm5_32; |
| 3935 | break; |
| 3936 | } |
| 3937 | // 'ConstantUImm5_0_Report_UImm6' class |
| 3938 | case MCK_ConstantUImm5_0_Report_UImm6: { |
| 3939 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); |
| 3940 | if (DP.isMatch()) |
| 3941 | return MCTargetAsmParser::Match_Success; |
| 3942 | if (DP.isNearMatch()) |
| 3943 | return MipsAsmParser::Match_UImm5_0_Report_UImm6; |
| 3944 | break; |
| 3945 | } |
| 3946 | // 'ConstantUImm5_33' class |
| 3947 | case MCK_ConstantUImm5_33: { |
| 3948 | DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>()); |
| 3949 | if (DP.isMatch()) |
| 3950 | return MCTargetAsmParser::Match_Success; |
| 3951 | if (DP.isNearMatch()) |
| 3952 | return MipsAsmParser::Match_UImm5_33; |
| 3953 | break; |
| 3954 | } |
| 3955 | // 'ConstantUImmRange2_64' class |
| 3956 | case MCK_ConstantUImmRange2_64: { |
| 3957 | DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>()); |
| 3958 | if (DP.isMatch()) |
| 3959 | return MCTargetAsmParser::Match_Success; |
| 3960 | if (DP.isNearMatch()) |
| 3961 | return MipsAsmParser::Match_UImmRange2_64; |
| 3962 | break; |
| 3963 | } |
| 3964 | // 'UImm5Lsl2' class |
| 3965 | case MCK_UImm5Lsl2: { |
| 3966 | DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>()); |
| 3967 | if (DP.isMatch()) |
| 3968 | return MCTargetAsmParser::Match_Success; |
| 3969 | if (DP.isNearMatch()) |
| 3970 | return MipsAsmParser::Match_UImm5_Lsl2; |
| 3971 | break; |
| 3972 | } |
| 3973 | // 'ConstantSImm6_0' class |
| 3974 | case MCK_ConstantSImm6_0: { |
| 3975 | DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>()); |
| 3976 | if (DP.isMatch()) |
| 3977 | return MCTargetAsmParser::Match_Success; |
| 3978 | if (DP.isNearMatch()) |
| 3979 | return MipsAsmParser::Match_SImm6_0; |
| 3980 | break; |
| 3981 | } |
| 3982 | // 'ConstantUImm6_0' class |
| 3983 | case MCK_ConstantUImm6_0: { |
| 3984 | DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>()); |
| 3985 | if (DP.isMatch()) |
| 3986 | return MCTargetAsmParser::Match_Success; |
| 3987 | if (DP.isNearMatch()) |
| 3988 | return MipsAsmParser::Match_UImm6_0; |
| 3989 | break; |
| 3990 | } |
| 3991 | // 'UImm6Lsl2' class |
| 3992 | case MCK_UImm6Lsl2: { |
| 3993 | DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>()); |
| 3994 | if (DP.isMatch()) |
| 3995 | return MCTargetAsmParser::Match_Success; |
| 3996 | if (DP.isNearMatch()) |
| 3997 | return MipsAsmParser::Match_UImm6_Lsl2; |
| 3998 | break; |
| 3999 | } |
| 4000 | // 'ConstantUImm7_0' class |
| 4001 | case MCK_ConstantUImm7_0: { |
| 4002 | DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>()); |
| 4003 | if (DP.isMatch()) |
| 4004 | return MCTargetAsmParser::Match_Success; |
| 4005 | if (DP.isNearMatch()) |
| 4006 | return MipsAsmParser::Match_UImm7_0; |
| 4007 | break; |
| 4008 | } |
| 4009 | // 'UImm7_N1' class |
| 4010 | case MCK_UImm7_N1: { |
| 4011 | DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>()); |
| 4012 | if (DP.isMatch()) |
| 4013 | return MCTargetAsmParser::Match_Success; |
| 4014 | if (DP.isNearMatch()) |
| 4015 | return MipsAsmParser::Match_UImm7_N1; |
| 4016 | break; |
| 4017 | } |
| 4018 | // 'ConstantUImm8_0' class |
| 4019 | case MCK_ConstantUImm8_0: { |
| 4020 | DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>()); |
| 4021 | if (DP.isMatch()) |
| 4022 | return MCTargetAsmParser::Match_Success; |
| 4023 | if (DP.isNearMatch()) |
| 4024 | return MipsAsmParser::Match_UImm8_0; |
| 4025 | break; |
| 4026 | } |
| 4027 | // 'SImm7Lsl2' class |
| 4028 | case MCK_SImm7Lsl2: { |
| 4029 | DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>()); |
| 4030 | if (DP.isMatch()) |
| 4031 | return MCTargetAsmParser::Match_Success; |
| 4032 | if (DP.isNearMatch()) |
| 4033 | return MipsAsmParser::Match_SImm7_Lsl2; |
| 4034 | break; |
| 4035 | } |
| 4036 | // 'ConstantSImm9_0' class |
| 4037 | case MCK_ConstantSImm9_0: { |
| 4038 | DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>()); |
| 4039 | if (DP.isMatch()) |
| 4040 | return MCTargetAsmParser::Match_Success; |
| 4041 | if (DP.isNearMatch()) |
| 4042 | return MipsAsmParser::Match_SImm9_0; |
| 4043 | break; |
| 4044 | } |
| 4045 | // 'ConstantSImm10_0' class |
| 4046 | case MCK_ConstantSImm10_0: { |
| 4047 | DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>()); |
| 4048 | if (DP.isMatch()) |
| 4049 | return MCTargetAsmParser::Match_Success; |
| 4050 | if (DP.isNearMatch()) |
| 4051 | return MipsAsmParser::Match_SImm10_0; |
| 4052 | break; |
| 4053 | } |
| 4054 | // 'ConstantUImm10_0' class |
| 4055 | case MCK_ConstantUImm10_0: { |
| 4056 | DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>()); |
| 4057 | if (DP.isMatch()) |
| 4058 | return MCTargetAsmParser::Match_Success; |
| 4059 | if (DP.isNearMatch()) |
| 4060 | return MipsAsmParser::Match_UImm10_0; |
| 4061 | break; |
| 4062 | } |
| 4063 | // 'SImm10Lsl1' class |
| 4064 | case MCK_SImm10Lsl1: { |
| 4065 | DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>()); |
| 4066 | if (DP.isMatch()) |
| 4067 | return MCTargetAsmParser::Match_Success; |
| 4068 | if (DP.isNearMatch()) |
| 4069 | return MipsAsmParser::Match_SImm10_Lsl1; |
| 4070 | break; |
| 4071 | } |
| 4072 | // 'ConstantSImm11_0' class |
| 4073 | case MCK_ConstantSImm11_0: { |
| 4074 | DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>()); |
| 4075 | if (DP.isMatch()) |
| 4076 | return MCTargetAsmParser::Match_Success; |
| 4077 | if (DP.isNearMatch()) |
| 4078 | return MipsAsmParser::Match_SImm11_0; |
| 4079 | break; |
| 4080 | } |
| 4081 | // 'SImm10Lsl2' class |
| 4082 | case MCK_SImm10Lsl2: { |
| 4083 | DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>()); |
| 4084 | if (DP.isMatch()) |
| 4085 | return MCTargetAsmParser::Match_Success; |
| 4086 | if (DP.isNearMatch()) |
| 4087 | return MipsAsmParser::Match_SImm10_Lsl2; |
| 4088 | break; |
| 4089 | } |
| 4090 | // 'SImm10Lsl3' class |
| 4091 | case MCK_SImm10Lsl3: { |
| 4092 | DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>()); |
| 4093 | if (DP.isMatch()) |
| 4094 | return MCTargetAsmParser::Match_Success; |
| 4095 | if (DP.isNearMatch()) |
| 4096 | return MipsAsmParser::Match_SImm10_Lsl3; |
| 4097 | break; |
| 4098 | } |
| 4099 | // 'SImm16' class |
| 4100 | case MCK_SImm16: { |
| 4101 | DiagnosticPredicate DP(Operand.isSImm<16>()); |
| 4102 | if (DP.isMatch()) |
| 4103 | return MCTargetAsmParser::Match_Success; |
| 4104 | if (DP.isNearMatch()) |
| 4105 | return MipsAsmParser::Match_SImm16; |
| 4106 | break; |
| 4107 | } |
| 4108 | // 'SImm16_Relaxed' class |
| 4109 | case MCK_SImm16_Relaxed: { |
| 4110 | DiagnosticPredicate DP(Operand.isAnyImm<16>()); |
| 4111 | if (DP.isMatch()) |
| 4112 | return MCTargetAsmParser::Match_Success; |
| 4113 | if (DP.isNearMatch()) |
| 4114 | return MipsAsmParser::Match_SImm16_Relaxed; |
| 4115 | break; |
| 4116 | } |
| 4117 | // 'UImm16_AltRelaxed' class |
| 4118 | case MCK_UImm16_AltRelaxed: { |
| 4119 | DiagnosticPredicate DP(Operand.isUImm<16>()); |
| 4120 | if (DP.isMatch()) |
| 4121 | return MCTargetAsmParser::Match_Success; |
| 4122 | if (DP.isNearMatch()) |
| 4123 | return MipsAsmParser::Match_UImm16_AltRelaxed; |
| 4124 | break; |
| 4125 | } |
| 4126 | // 'UImm16' class |
| 4127 | case MCK_UImm16: { |
| 4128 | DiagnosticPredicate DP(Operand.isUImm<16>()); |
| 4129 | if (DP.isMatch()) |
| 4130 | return MCTargetAsmParser::Match_Success; |
| 4131 | if (DP.isNearMatch()) |
| 4132 | return MipsAsmParser::Match_UImm16; |
| 4133 | break; |
| 4134 | } |
| 4135 | // 'SImm19Lsl2' class |
| 4136 | case MCK_SImm19Lsl2: { |
| 4137 | DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); |
| 4138 | if (DP.isMatch()) |
| 4139 | return MCTargetAsmParser::Match_Success; |
| 4140 | if (DP.isNearMatch()) |
| 4141 | return MipsAsmParser::Match_SImm19_Lsl2; |
| 4142 | break; |
| 4143 | } |
| 4144 | // 'UImm16_Relaxed' class |
| 4145 | case MCK_UImm16_Relaxed: { |
| 4146 | DiagnosticPredicate DP(Operand.isAnyImm<16>()); |
| 4147 | if (DP.isMatch()) |
| 4148 | return MCTargetAsmParser::Match_Success; |
| 4149 | if (DP.isNearMatch()) |
| 4150 | return MipsAsmParser::Match_UImm16_Relaxed; |
| 4151 | break; |
| 4152 | } |
| 4153 | // 'ConstantUImm20_0' class |
| 4154 | case MCK_ConstantUImm20_0: { |
| 4155 | DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>()); |
| 4156 | if (DP.isMatch()) |
| 4157 | return MCTargetAsmParser::Match_Success; |
| 4158 | if (DP.isNearMatch()) |
| 4159 | return MipsAsmParser::Match_UImm20_0; |
| 4160 | break; |
| 4161 | } |
| 4162 | // 'ConstantUImm26_0' class |
| 4163 | case MCK_ConstantUImm26_0: { |
| 4164 | DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>()); |
| 4165 | if (DP.isMatch()) |
| 4166 | return MCTargetAsmParser::Match_Success; |
| 4167 | if (DP.isNearMatch()) |
| 4168 | return MipsAsmParser::Match_UImm26_0; |
| 4169 | break; |
| 4170 | } |
| 4171 | // 'SImm32' class |
| 4172 | case MCK_SImm32: { |
| 4173 | DiagnosticPredicate DP(Operand.isSImm<32>()); |
| 4174 | if (DP.isMatch()) |
| 4175 | return MCTargetAsmParser::Match_Success; |
| 4176 | if (DP.isNearMatch()) |
| 4177 | return MipsAsmParser::Match_SImm32; |
| 4178 | break; |
| 4179 | } |
| 4180 | // 'SImm32_Relaxed' class |
| 4181 | case MCK_SImm32_Relaxed: { |
| 4182 | DiagnosticPredicate DP(Operand.isAnyImm<33>()); |
| 4183 | if (DP.isMatch()) |
| 4184 | return MCTargetAsmParser::Match_Success; |
| 4185 | if (DP.isNearMatch()) |
| 4186 | return MipsAsmParser::Match_SImm32_Relaxed; |
| 4187 | break; |
| 4188 | } |
| 4189 | // 'UImm32_Coerced' class |
| 4190 | case MCK_UImm32_Coerced: { |
| 4191 | DiagnosticPredicate DP(Operand.isSImm<33>()); |
| 4192 | if (DP.isMatch()) |
| 4193 | return MCTargetAsmParser::Match_Success; |
| 4194 | if (DP.isNearMatch()) |
| 4195 | return MipsAsmParser::Match_UImm32_Coerced; |
| 4196 | break; |
| 4197 | } |
| 4198 | } // end switch (Kind) |
| 4199 | |
| 4200 | if (Operand.isReg()) { |
| 4201 | MatchClassKind OpKind; |
| 4202 | switch (Operand.getReg().id()) { |
| 4203 | default: OpKind = InvalidMatchClass; break; |
| 4204 | case Mips::ZERO: OpKind = MCK_GPR32ZERO; break; |
| 4205 | case Mips::AT: OpKind = MCK_GPR32NONZERO; break; |
| 4206 | case Mips::V0: OpKind = MCK_Reg11; break; |
| 4207 | case Mips::V1: OpKind = MCK_Reg11; break; |
| 4208 | case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break; |
| 4209 | case Mips::A1: OpKind = MCK_Reg13; break; |
| 4210 | case Mips::A2: OpKind = MCK_Reg13; break; |
| 4211 | case Mips::A3: OpKind = MCK_Reg14; break; |
| 4212 | case Mips::T0: OpKind = MCK_GPR32NONZERO; break; |
| 4213 | case Mips::T1: OpKind = MCK_GPR32NONZERO; break; |
| 4214 | case Mips::T2: OpKind = MCK_GPR32NONZERO; break; |
| 4215 | case Mips::T3: OpKind = MCK_GPR32NONZERO; break; |
| 4216 | case Mips::T4: OpKind = MCK_GPR32NONZERO; break; |
| 4217 | case Mips::T5: OpKind = MCK_GPR32NONZERO; break; |
| 4218 | case Mips::T6: OpKind = MCK_GPR32NONZERO; break; |
| 4219 | case Mips::T7: OpKind = MCK_GPR32NONZERO; break; |
| 4220 | case Mips::S0: OpKind = MCK_Reg9; break; |
| 4221 | case Mips::S1: OpKind = MCK_Reg11; break; |
| 4222 | case Mips::S2: OpKind = MCK_Reg10; break; |
| 4223 | case Mips::S3: OpKind = MCK_Reg10; break; |
| 4224 | case Mips::S4: OpKind = MCK_Reg10; break; |
| 4225 | case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break; |
| 4226 | case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break; |
| 4227 | case Mips::S7: OpKind = MCK_GPR32NONZERO; break; |
| 4228 | case Mips::T8: OpKind = MCK_GPR32NONZERO; break; |
| 4229 | case Mips::T9: OpKind = MCK_GPR32NONZERO; break; |
| 4230 | case Mips::K0: OpKind = MCK_GPR32NONZERO; break; |
| 4231 | case Mips::K1: OpKind = MCK_GPR32NONZERO; break; |
| 4232 | case Mips::GP: OpKind = MCK_GP32; break; |
| 4233 | case Mips::SP: OpKind = MCK_CPUSPReg; break; |
| 4234 | case Mips::FP: OpKind = MCK_GPR32NONZERO; break; |
| 4235 | case Mips::RA: OpKind = MCK_CPURAReg; break; |
| 4236 | case Mips::ZERO_64: OpKind = MCK_Reg19; break; |
| 4237 | case Mips::AT_64: OpKind = MCK_Reg24; break; |
| 4238 | case Mips::V0_64: OpKind = MCK_Reg30; break; |
| 4239 | case Mips::V1_64: OpKind = MCK_Reg30; break; |
| 4240 | case Mips::A0_64: OpKind = MCK_Reg31; break; |
| 4241 | case Mips::A1_64: OpKind = MCK_Reg32; break; |
| 4242 | case Mips::A2_64: OpKind = MCK_Reg32; break; |
| 4243 | case Mips::A3_64: OpKind = MCK_Reg33; break; |
| 4244 | case Mips::T0_64: OpKind = MCK_Reg24; break; |
| 4245 | case Mips::T1_64: OpKind = MCK_Reg24; break; |
| 4246 | case Mips::T2_64: OpKind = MCK_Reg24; break; |
| 4247 | case Mips::T3_64: OpKind = MCK_Reg24; break; |
| 4248 | case Mips::T4_64: OpKind = MCK_Reg24; break; |
| 4249 | case Mips::T5_64: OpKind = MCK_Reg24; break; |
| 4250 | case Mips::T6_64: OpKind = MCK_Reg24; break; |
| 4251 | case Mips::T7_64: OpKind = MCK_Reg24; break; |
| 4252 | case Mips::S0_64: OpKind = MCK_Reg28; break; |
| 4253 | case Mips::S1_64: OpKind = MCK_Reg30; break; |
| 4254 | case Mips::S2_64: OpKind = MCK_Reg29; break; |
| 4255 | case Mips::S3_64: OpKind = MCK_Reg29; break; |
| 4256 | case Mips::S4_64: OpKind = MCK_Reg29; break; |
| 4257 | case Mips::S5_64: OpKind = MCK_Reg34; break; |
| 4258 | case Mips::S6_64: OpKind = MCK_Reg34; break; |
| 4259 | case Mips::S7_64: OpKind = MCK_Reg24; break; |
| 4260 | case Mips::T8_64: OpKind = MCK_Reg24; break; |
| 4261 | case Mips::T9_64: OpKind = MCK_Reg24; break; |
| 4262 | case Mips::K0_64: OpKind = MCK_Reg24; break; |
| 4263 | case Mips::K1_64: OpKind = MCK_Reg24; break; |
| 4264 | case Mips::GP_64: OpKind = MCK_GP64; break; |
| 4265 | case Mips::SP_64: OpKind = MCK_SP64; break; |
| 4266 | case Mips::FP_64: OpKind = MCK_Reg24; break; |
| 4267 | case Mips::RA_64: OpKind = MCK_Reg37; break; |
| 4268 | case Mips::F0: OpKind = MCK_FGR32; break; |
| 4269 | case Mips::F1: OpKind = MCK_FGR32; break; |
| 4270 | case Mips::F2: OpKind = MCK_FGR32; break; |
| 4271 | case Mips::F3: OpKind = MCK_FGR32; break; |
| 4272 | case Mips::F4: OpKind = MCK_FGR32; break; |
| 4273 | case Mips::F5: OpKind = MCK_FGR32; break; |
| 4274 | case Mips::F6: OpKind = MCK_FGR32; break; |
| 4275 | case Mips::F7: OpKind = MCK_FGR32; break; |
| 4276 | case Mips::F8: OpKind = MCK_FGR32; break; |
| 4277 | case Mips::F9: OpKind = MCK_FGR32; break; |
| 4278 | case Mips::F10: OpKind = MCK_FGR32; break; |
| 4279 | case Mips::F11: OpKind = MCK_FGR32; break; |
| 4280 | case Mips::F12: OpKind = MCK_FGR32; break; |
| 4281 | case Mips::F13: OpKind = MCK_FGR32; break; |
| 4282 | case Mips::F14: OpKind = MCK_FGR32; break; |
| 4283 | case Mips::F15: OpKind = MCK_FGR32; break; |
| 4284 | case Mips::F16: OpKind = MCK_FGR32; break; |
| 4285 | case Mips::F17: OpKind = MCK_FGR32; break; |
| 4286 | case Mips::F18: OpKind = MCK_FGR32; break; |
| 4287 | case Mips::F19: OpKind = MCK_FGR32; break; |
| 4288 | case Mips::F20: OpKind = MCK_FGR32; break; |
| 4289 | case Mips::F21: OpKind = MCK_FGR32; break; |
| 4290 | case Mips::F22: OpKind = MCK_FGR32; break; |
| 4291 | case Mips::F23: OpKind = MCK_FGR32; break; |
| 4292 | case Mips::F24: OpKind = MCK_FGR32; break; |
| 4293 | case Mips::F25: OpKind = MCK_FGR32; break; |
| 4294 | case Mips::F26: OpKind = MCK_FGR32; break; |
| 4295 | case Mips::F27: OpKind = MCK_FGR32; break; |
| 4296 | case Mips::F28: OpKind = MCK_FGR32; break; |
| 4297 | case Mips::F29: OpKind = MCK_FGR32; break; |
| 4298 | case Mips::F30: OpKind = MCK_FGR32; break; |
| 4299 | case Mips::F31: OpKind = MCK_FGR32; break; |
| 4300 | case Mips::D0: OpKind = MCK_AFGR64; break; |
| 4301 | case Mips::D1: OpKind = MCK_AFGR64; break; |
| 4302 | case Mips::D2: OpKind = MCK_AFGR64; break; |
| 4303 | case Mips::D3: OpKind = MCK_AFGR64; break; |
| 4304 | case Mips::D4: OpKind = MCK_AFGR64; break; |
| 4305 | case Mips::D5: OpKind = MCK_AFGR64; break; |
| 4306 | case Mips::D6: OpKind = MCK_AFGR64; break; |
| 4307 | case Mips::D7: OpKind = MCK_AFGR64; break; |
| 4308 | case Mips::D8: OpKind = MCK_AFGR64; break; |
| 4309 | case Mips::D9: OpKind = MCK_AFGR64; break; |
| 4310 | case Mips::D10: OpKind = MCK_AFGR64; break; |
| 4311 | case Mips::D11: OpKind = MCK_AFGR64; break; |
| 4312 | case Mips::D12: OpKind = MCK_AFGR64; break; |
| 4313 | case Mips::D13: OpKind = MCK_AFGR64; break; |
| 4314 | case Mips::D14: OpKind = MCK_AFGR64; break; |
| 4315 | case Mips::D15: OpKind = MCK_AFGR64; break; |
| 4316 | case Mips::D0_64: OpKind = MCK_FGR64; break; |
| 4317 | case Mips::D1_64: OpKind = MCK_FGR64; break; |
| 4318 | case Mips::D2_64: OpKind = MCK_FGR64; break; |
| 4319 | case Mips::D3_64: OpKind = MCK_FGR64; break; |
| 4320 | case Mips::D4_64: OpKind = MCK_FGR64; break; |
| 4321 | case Mips::D5_64: OpKind = MCK_FGR64; break; |
| 4322 | case Mips::D6_64: OpKind = MCK_FGR64; break; |
| 4323 | case Mips::D7_64: OpKind = MCK_FGR64; break; |
| 4324 | case Mips::D8_64: OpKind = MCK_FGR64; break; |
| 4325 | case Mips::D9_64: OpKind = MCK_FGR64; break; |
| 4326 | case Mips::D10_64: OpKind = MCK_FGR64; break; |
| 4327 | case Mips::D11_64: OpKind = MCK_FGR64; break; |
| 4328 | case Mips::D12_64: OpKind = MCK_FGR64; break; |
| 4329 | case Mips::D13_64: OpKind = MCK_FGR64; break; |
| 4330 | case Mips::D14_64: OpKind = MCK_FGR64; break; |
| 4331 | case Mips::D15_64: OpKind = MCK_FGR64; break; |
| 4332 | case Mips::D16_64: OpKind = MCK_FGR64; break; |
| 4333 | case Mips::D17_64: OpKind = MCK_FGR64; break; |
| 4334 | case Mips::D18_64: OpKind = MCK_FGR64; break; |
| 4335 | case Mips::D19_64: OpKind = MCK_FGR64; break; |
| 4336 | case Mips::D20_64: OpKind = MCK_FGR64; break; |
| 4337 | case Mips::D21_64: OpKind = MCK_FGR64; break; |
| 4338 | case Mips::D22_64: OpKind = MCK_FGR64; break; |
| 4339 | case Mips::D23_64: OpKind = MCK_FGR64; break; |
| 4340 | case Mips::D24_64: OpKind = MCK_FGR64; break; |
| 4341 | case Mips::D25_64: OpKind = MCK_FGR64; break; |
| 4342 | case Mips::D26_64: OpKind = MCK_FGR64; break; |
| 4343 | case Mips::D27_64: OpKind = MCK_FGR64; break; |
| 4344 | case Mips::D28_64: OpKind = MCK_FGR64; break; |
| 4345 | case Mips::D29_64: OpKind = MCK_FGR64; break; |
| 4346 | case Mips::D30_64: OpKind = MCK_FGR64; break; |
| 4347 | case Mips::D31_64: OpKind = MCK_FGR64; break; |
| 4348 | case Mips::W0: OpKind = MCK_MSA128WEvens; break; |
| 4349 | case Mips::W1: OpKind = MCK_MSA128F16; break; |
| 4350 | case Mips::W2: OpKind = MCK_MSA128WEvens; break; |
| 4351 | case Mips::W3: OpKind = MCK_MSA128F16; break; |
| 4352 | case Mips::W4: OpKind = MCK_MSA128WEvens; break; |
| 4353 | case Mips::W5: OpKind = MCK_MSA128F16; break; |
| 4354 | case Mips::W6: OpKind = MCK_MSA128WEvens; break; |
| 4355 | case Mips::W7: OpKind = MCK_MSA128F16; break; |
| 4356 | case Mips::W8: OpKind = MCK_MSA128WEvens; break; |
| 4357 | case Mips::W9: OpKind = MCK_MSA128F16; break; |
| 4358 | case Mips::W10: OpKind = MCK_MSA128WEvens; break; |
| 4359 | case Mips::W11: OpKind = MCK_MSA128F16; break; |
| 4360 | case Mips::W12: OpKind = MCK_MSA128WEvens; break; |
| 4361 | case Mips::W13: OpKind = MCK_MSA128F16; break; |
| 4362 | case Mips::W14: OpKind = MCK_MSA128WEvens; break; |
| 4363 | case Mips::W15: OpKind = MCK_MSA128F16; break; |
| 4364 | case Mips::W16: OpKind = MCK_MSA128WEvens; break; |
| 4365 | case Mips::W17: OpKind = MCK_MSA128F16; break; |
| 4366 | case Mips::W18: OpKind = MCK_MSA128WEvens; break; |
| 4367 | case Mips::W19: OpKind = MCK_MSA128F16; break; |
| 4368 | case Mips::W20: OpKind = MCK_MSA128WEvens; break; |
| 4369 | case Mips::W21: OpKind = MCK_MSA128F16; break; |
| 4370 | case Mips::W22: OpKind = MCK_MSA128WEvens; break; |
| 4371 | case Mips::W23: OpKind = MCK_MSA128F16; break; |
| 4372 | case Mips::W24: OpKind = MCK_MSA128WEvens; break; |
| 4373 | case Mips::W25: OpKind = MCK_MSA128F16; break; |
| 4374 | case Mips::W26: OpKind = MCK_MSA128WEvens; break; |
| 4375 | case Mips::W27: OpKind = MCK_MSA128F16; break; |
| 4376 | case Mips::W28: OpKind = MCK_MSA128WEvens; break; |
| 4377 | case Mips::W29: OpKind = MCK_MSA128F16; break; |
| 4378 | case Mips::W30: OpKind = MCK_MSA128WEvens; break; |
| 4379 | case Mips::W31: OpKind = MCK_MSA128F16; break; |
| 4380 | case Mips::HI0: OpKind = MCK_HI32; break; |
| 4381 | case Mips::HI1: OpKind = MCK_HI32DSP; break; |
| 4382 | case Mips::HI2: OpKind = MCK_HI32DSP; break; |
| 4383 | case Mips::HI3: OpKind = MCK_HI32DSP; break; |
| 4384 | case Mips::LO0: OpKind = MCK_LO32; break; |
| 4385 | case Mips::LO1: OpKind = MCK_LO32DSP; break; |
| 4386 | case Mips::LO2: OpKind = MCK_LO32DSP; break; |
| 4387 | case Mips::LO3: OpKind = MCK_LO32DSP; break; |
| 4388 | case Mips::HI0_64: OpKind = MCK_HI64; break; |
| 4389 | case Mips::LO0_64: OpKind = MCK_LO64; break; |
| 4390 | case Mips::FCR0: OpKind = MCK_CCR; break; |
| 4391 | case Mips::FCR1: OpKind = MCK_CCR; break; |
| 4392 | case Mips::FCR2: OpKind = MCK_CCR; break; |
| 4393 | case Mips::FCR3: OpKind = MCK_CCR; break; |
| 4394 | case Mips::FCR4: OpKind = MCK_CCR; break; |
| 4395 | case Mips::FCR5: OpKind = MCK_CCR; break; |
| 4396 | case Mips::FCR6: OpKind = MCK_CCR; break; |
| 4397 | case Mips::FCR7: OpKind = MCK_CCR; break; |
| 4398 | case Mips::FCR8: OpKind = MCK_CCR; break; |
| 4399 | case Mips::FCR9: OpKind = MCK_CCR; break; |
| 4400 | case Mips::FCR10: OpKind = MCK_CCR; break; |
| 4401 | case Mips::FCR11: OpKind = MCK_CCR; break; |
| 4402 | case Mips::FCR12: OpKind = MCK_CCR; break; |
| 4403 | case Mips::FCR13: OpKind = MCK_CCR; break; |
| 4404 | case Mips::FCR14: OpKind = MCK_CCR; break; |
| 4405 | case Mips::FCR15: OpKind = MCK_CCR; break; |
| 4406 | case Mips::FCR16: OpKind = MCK_CCR; break; |
| 4407 | case Mips::FCR17: OpKind = MCK_CCR; break; |
| 4408 | case Mips::FCR18: OpKind = MCK_CCR; break; |
| 4409 | case Mips::FCR19: OpKind = MCK_CCR; break; |
| 4410 | case Mips::FCR20: OpKind = MCK_CCR; break; |
| 4411 | case Mips::FCR21: OpKind = MCK_CCR; break; |
| 4412 | case Mips::FCR22: OpKind = MCK_CCR; break; |
| 4413 | case Mips::FCR23: OpKind = MCK_CCR; break; |
| 4414 | case Mips::FCR24: OpKind = MCK_CCR; break; |
| 4415 | case Mips::FCR25: OpKind = MCK_CCR; break; |
| 4416 | case Mips::FCR26: OpKind = MCK_CCR; break; |
| 4417 | case Mips::FCR27: OpKind = MCK_CCR; break; |
| 4418 | case Mips::FCR28: OpKind = MCK_CCR; break; |
| 4419 | case Mips::FCR29: OpKind = MCK_CCR; break; |
| 4420 | case Mips::FCR30: OpKind = MCK_CCR; break; |
| 4421 | case Mips::FCR31: OpKind = MCK_CCR; break; |
| 4422 | case Mips::FCC0: OpKind = MCK_FCC; break; |
| 4423 | case Mips::FCC1: OpKind = MCK_FCC; break; |
| 4424 | case Mips::FCC2: OpKind = MCK_FCC; break; |
| 4425 | case Mips::FCC3: OpKind = MCK_FCC; break; |
| 4426 | case Mips::FCC4: OpKind = MCK_FCC; break; |
| 4427 | case Mips::FCC5: OpKind = MCK_FCC; break; |
| 4428 | case Mips::FCC6: OpKind = MCK_FCC; break; |
| 4429 | case Mips::FCC7: OpKind = MCK_FCC; break; |
| 4430 | case Mips::COP00: OpKind = MCK_COP0; break; |
| 4431 | case Mips::COP01: OpKind = MCK_COP0; break; |
| 4432 | case Mips::COP02: OpKind = MCK_COP0; break; |
| 4433 | case Mips::COP03: OpKind = MCK_COP0; break; |
| 4434 | case Mips::COP04: OpKind = MCK_COP0; break; |
| 4435 | case Mips::COP05: OpKind = MCK_COP0; break; |
| 4436 | case Mips::COP06: OpKind = MCK_COP0; break; |
| 4437 | case Mips::COP07: OpKind = MCK_COP0; break; |
| 4438 | case Mips::COP08: OpKind = MCK_COP0; break; |
| 4439 | case Mips::COP09: OpKind = MCK_COP0; break; |
| 4440 | case Mips::COP010: OpKind = MCK_COP0; break; |
| 4441 | case Mips::COP011: OpKind = MCK_COP0; break; |
| 4442 | case Mips::COP012: OpKind = MCK_COP0; break; |
| 4443 | case Mips::COP013: OpKind = MCK_COP0; break; |
| 4444 | case Mips::COP014: OpKind = MCK_COP0; break; |
| 4445 | case Mips::COP015: OpKind = MCK_COP0; break; |
| 4446 | case Mips::COP016: OpKind = MCK_COP0; break; |
| 4447 | case Mips::COP017: OpKind = MCK_COP0; break; |
| 4448 | case Mips::COP018: OpKind = MCK_COP0; break; |
| 4449 | case Mips::COP019: OpKind = MCK_COP0; break; |
| 4450 | case Mips::COP020: OpKind = MCK_COP0; break; |
| 4451 | case Mips::COP021: OpKind = MCK_COP0; break; |
| 4452 | case Mips::COP022: OpKind = MCK_COP0; break; |
| 4453 | case Mips::COP023: OpKind = MCK_COP0; break; |
| 4454 | case Mips::COP024: OpKind = MCK_COP0; break; |
| 4455 | case Mips::COP025: OpKind = MCK_COP0; break; |
| 4456 | case Mips::COP026: OpKind = MCK_COP0; break; |
| 4457 | case Mips::COP027: OpKind = MCK_COP0; break; |
| 4458 | case Mips::COP028: OpKind = MCK_COP0; break; |
| 4459 | case Mips::COP029: OpKind = MCK_COP0; break; |
| 4460 | case Mips::COP030: OpKind = MCK_COP0; break; |
| 4461 | case Mips::COP031: OpKind = MCK_COP0; break; |
| 4462 | case Mips::COP20: OpKind = MCK_COP2; break; |
| 4463 | case Mips::COP21: OpKind = MCK_COP2; break; |
| 4464 | case Mips::COP22: OpKind = MCK_COP2; break; |
| 4465 | case Mips::COP23: OpKind = MCK_COP2; break; |
| 4466 | case Mips::COP24: OpKind = MCK_COP2; break; |
| 4467 | case Mips::COP25: OpKind = MCK_COP2; break; |
| 4468 | case Mips::COP26: OpKind = MCK_COP2; break; |
| 4469 | case Mips::COP27: OpKind = MCK_COP2; break; |
| 4470 | case Mips::COP28: OpKind = MCK_COP2; break; |
| 4471 | case Mips::COP29: OpKind = MCK_COP2; break; |
| 4472 | case Mips::COP210: OpKind = MCK_COP2; break; |
| 4473 | case Mips::COP211: OpKind = MCK_COP2; break; |
| 4474 | case Mips::COP212: OpKind = MCK_COP2; break; |
| 4475 | case Mips::COP213: OpKind = MCK_COP2; break; |
| 4476 | case Mips::COP214: OpKind = MCK_COP2; break; |
| 4477 | case Mips::COP215: OpKind = MCK_COP2; break; |
| 4478 | case Mips::COP216: OpKind = MCK_COP2; break; |
| 4479 | case Mips::COP217: OpKind = MCK_COP2; break; |
| 4480 | case Mips::COP218: OpKind = MCK_COP2; break; |
| 4481 | case Mips::COP219: OpKind = MCK_COP2; break; |
| 4482 | case Mips::COP220: OpKind = MCK_COP2; break; |
| 4483 | case Mips::COP221: OpKind = MCK_COP2; break; |
| 4484 | case Mips::COP222: OpKind = MCK_COP2; break; |
| 4485 | case Mips::COP223: OpKind = MCK_COP2; break; |
| 4486 | case Mips::COP224: OpKind = MCK_COP2; break; |
| 4487 | case Mips::COP225: OpKind = MCK_COP2; break; |
| 4488 | case Mips::COP226: OpKind = MCK_COP2; break; |
| 4489 | case Mips::COP227: OpKind = MCK_COP2; break; |
| 4490 | case Mips::COP228: OpKind = MCK_COP2; break; |
| 4491 | case Mips::COP229: OpKind = MCK_COP2; break; |
| 4492 | case Mips::COP230: OpKind = MCK_COP2; break; |
| 4493 | case Mips::COP231: OpKind = MCK_COP2; break; |
| 4494 | case Mips::COP30: OpKind = MCK_COP3; break; |
| 4495 | case Mips::COP31: OpKind = MCK_COP3; break; |
| 4496 | case Mips::COP32: OpKind = MCK_COP3; break; |
| 4497 | case Mips::COP33: OpKind = MCK_COP3; break; |
| 4498 | case Mips::COP34: OpKind = MCK_COP3; break; |
| 4499 | case Mips::COP35: OpKind = MCK_COP3; break; |
| 4500 | case Mips::COP36: OpKind = MCK_COP3; break; |
| 4501 | case Mips::COP37: OpKind = MCK_COP3; break; |
| 4502 | case Mips::COP38: OpKind = MCK_COP3; break; |
| 4503 | case Mips::COP39: OpKind = MCK_COP3; break; |
| 4504 | case Mips::COP310: OpKind = MCK_COP3; break; |
| 4505 | case Mips::COP311: OpKind = MCK_COP3; break; |
| 4506 | case Mips::COP312: OpKind = MCK_COP3; break; |
| 4507 | case Mips::COP313: OpKind = MCK_COP3; break; |
| 4508 | case Mips::COP314: OpKind = MCK_COP3; break; |
| 4509 | case Mips::COP315: OpKind = MCK_COP3; break; |
| 4510 | case Mips::COP316: OpKind = MCK_COP3; break; |
| 4511 | case Mips::COP317: OpKind = MCK_COP3; break; |
| 4512 | case Mips::COP318: OpKind = MCK_COP3; break; |
| 4513 | case Mips::COP319: OpKind = MCK_COP3; break; |
| 4514 | case Mips::COP320: OpKind = MCK_COP3; break; |
| 4515 | case Mips::COP321: OpKind = MCK_COP3; break; |
| 4516 | case Mips::COP322: OpKind = MCK_COP3; break; |
| 4517 | case Mips::COP323: OpKind = MCK_COP3; break; |
| 4518 | case Mips::COP324: OpKind = MCK_COP3; break; |
| 4519 | case Mips::COP325: OpKind = MCK_COP3; break; |
| 4520 | case Mips::COP326: OpKind = MCK_COP3; break; |
| 4521 | case Mips::COP327: OpKind = MCK_COP3; break; |
| 4522 | case Mips::COP328: OpKind = MCK_COP3; break; |
| 4523 | case Mips::COP329: OpKind = MCK_COP3; break; |
| 4524 | case Mips::COP330: OpKind = MCK_COP3; break; |
| 4525 | case Mips::COP331: OpKind = MCK_COP3; break; |
| 4526 | case Mips::PC: OpKind = MCK_PC; break; |
| 4527 | case Mips::HWR0: OpKind = MCK_HWRegs; break; |
| 4528 | case Mips::HWR1: OpKind = MCK_HWRegs; break; |
| 4529 | case Mips::HWR2: OpKind = MCK_HWRegs; break; |
| 4530 | case Mips::HWR3: OpKind = MCK_HWRegs; break; |
| 4531 | case Mips::HWR4: OpKind = MCK_HWRegs; break; |
| 4532 | case Mips::HWR5: OpKind = MCK_HWRegs; break; |
| 4533 | case Mips::HWR6: OpKind = MCK_HWRegs; break; |
| 4534 | case Mips::HWR7: OpKind = MCK_HWRegs; break; |
| 4535 | case Mips::HWR8: OpKind = MCK_HWRegs; break; |
| 4536 | case Mips::HWR9: OpKind = MCK_HWRegs; break; |
| 4537 | case Mips::HWR10: OpKind = MCK_HWRegs; break; |
| 4538 | case Mips::HWR11: OpKind = MCK_HWRegs; break; |
| 4539 | case Mips::HWR12: OpKind = MCK_HWRegs; break; |
| 4540 | case Mips::HWR13: OpKind = MCK_HWRegs; break; |
| 4541 | case Mips::HWR14: OpKind = MCK_HWRegs; break; |
| 4542 | case Mips::HWR15: OpKind = MCK_HWRegs; break; |
| 4543 | case Mips::HWR16: OpKind = MCK_HWRegs; break; |
| 4544 | case Mips::HWR17: OpKind = MCK_HWRegs; break; |
| 4545 | case Mips::HWR18: OpKind = MCK_HWRegs; break; |
| 4546 | case Mips::HWR19: OpKind = MCK_HWRegs; break; |
| 4547 | case Mips::HWR20: OpKind = MCK_HWRegs; break; |
| 4548 | case Mips::HWR21: OpKind = MCK_HWRegs; break; |
| 4549 | case Mips::HWR22: OpKind = MCK_HWRegs; break; |
| 4550 | case Mips::HWR23: OpKind = MCK_HWRegs; break; |
| 4551 | case Mips::HWR24: OpKind = MCK_HWRegs; break; |
| 4552 | case Mips::HWR25: OpKind = MCK_HWRegs; break; |
| 4553 | case Mips::HWR26: OpKind = MCK_HWRegs; break; |
| 4554 | case Mips::HWR27: OpKind = MCK_HWRegs; break; |
| 4555 | case Mips::HWR28: OpKind = MCK_HWRegs; break; |
| 4556 | case Mips::HWR29: OpKind = MCK_HWRegs; break; |
| 4557 | case Mips::HWR30: OpKind = MCK_HWRegs; break; |
| 4558 | case Mips::HWR31: OpKind = MCK_HWRegs; break; |
| 4559 | case Mips::AC0: OpKind = MCK_ACC64; break; |
| 4560 | case Mips::AC1: OpKind = MCK_ACC64DSP; break; |
| 4561 | case Mips::AC2: OpKind = MCK_ACC64DSP; break; |
| 4562 | case Mips::AC3: OpKind = MCK_ACC64DSP; break; |
| 4563 | case Mips::AC0_64: OpKind = MCK_ACC128; break; |
| 4564 | case Mips::DSPCCond: OpKind = MCK_DSPCC; break; |
| 4565 | case Mips::MSAIR: OpKind = MCK_MSACtrl; break; |
| 4566 | case Mips::MSACSR: OpKind = MCK_MSACtrl; break; |
| 4567 | case Mips::MSAAccess: OpKind = MCK_MSACtrl; break; |
| 4568 | case Mips::MSASave: OpKind = MCK_MSACtrl; break; |
| 4569 | case Mips::MSAModify: OpKind = MCK_MSACtrl; break; |
| 4570 | case Mips::MSARequest: OpKind = MCK_MSACtrl; break; |
| 4571 | case Mips::MSAMap: OpKind = MCK_MSACtrl; break; |
| 4572 | case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break; |
| 4573 | case Mips::MSA8: OpKind = MCK_MSACtrl; break; |
| 4574 | case Mips::MSA9: OpKind = MCK_MSACtrl; break; |
| 4575 | case Mips::MSA10: OpKind = MCK_MSACtrl; break; |
| 4576 | case Mips::MSA11: OpKind = MCK_MSACtrl; break; |
| 4577 | case Mips::MSA12: OpKind = MCK_MSACtrl; break; |
| 4578 | case Mips::MSA13: OpKind = MCK_MSACtrl; break; |
| 4579 | case Mips::MSA14: OpKind = MCK_MSACtrl; break; |
| 4580 | case Mips::MSA15: OpKind = MCK_MSACtrl; break; |
| 4581 | case Mips::MSA16: OpKind = MCK_MSACtrl; break; |
| 4582 | case Mips::MSA17: OpKind = MCK_MSACtrl; break; |
| 4583 | case Mips::MSA18: OpKind = MCK_MSACtrl; break; |
| 4584 | case Mips::MSA19: OpKind = MCK_MSACtrl; break; |
| 4585 | case Mips::MSA20: OpKind = MCK_MSACtrl; break; |
| 4586 | case Mips::MSA21: OpKind = MCK_MSACtrl; break; |
| 4587 | case Mips::MSA22: OpKind = MCK_MSACtrl; break; |
| 4588 | case Mips::MSA23: OpKind = MCK_MSACtrl; break; |
| 4589 | case Mips::MSA24: OpKind = MCK_MSACtrl; break; |
| 4590 | case Mips::MSA25: OpKind = MCK_MSACtrl; break; |
| 4591 | case Mips::MSA26: OpKind = MCK_MSACtrl; break; |
| 4592 | case Mips::MSA27: OpKind = MCK_MSACtrl; break; |
| 4593 | case Mips::MSA28: OpKind = MCK_MSACtrl; break; |
| 4594 | case Mips::MSA29: OpKind = MCK_MSACtrl; break; |
| 4595 | case Mips::MSA30: OpKind = MCK_MSACtrl; break; |
| 4596 | case Mips::MSA31: OpKind = MCK_MSACtrl; break; |
| 4597 | case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break; |
| 4598 | case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break; |
| 4599 | case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break; |
| 4600 | case Mips::P0: OpKind = MCK_OCTEON_P; break; |
| 4601 | case Mips::P1: OpKind = MCK_OCTEON_P; break; |
| 4602 | case Mips::P2: OpKind = MCK_OCTEON_P; break; |
| 4603 | } |
| 4604 | return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : |
| 4605 | getDiagKindFromRegisterClass(Kind); |
| 4606 | } |
| 4607 | |
| 4608 | if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) |
| 4609 | return getDiagKindFromRegisterClass(Kind); |
| 4610 | |
| 4611 | return MCTargetAsmParser::Match_InvalidOperand; |
| 4612 | } |
| 4613 | |
| 4614 | #ifndef NDEBUG |
| 4615 | const char *getMatchClassName(MatchClassKind Kind) { |
| 4616 | switch (Kind) { |
| 4617 | case InvalidMatchClass: return "InvalidMatchClass"; |
| 4618 | case OptionalMatchClass: return "OptionalMatchClass"; |
| 4619 | case MCK__HASH_: return "MCK__HASH_"; |
| 4620 | case MCK__40_: return "MCK__40_"; |
| 4621 | case MCK__41_: return "MCK__41_"; |
| 4622 | case MCK_0: return "MCK_0"; |
| 4623 | case MCK_16: return "MCK_16"; |
| 4624 | case MCK__91_: return "MCK__91_"; |
| 4625 | case MCK__93_: return "MCK__93_"; |
| 4626 | case MCK_bit: return "MCK_bit"; |
| 4627 | case MCK_inst: return "MCK_inst"; |
| 4628 | case MCK_Reg37: return "MCK_Reg37"; |
| 4629 | case MCK_Reg19: return "MCK_Reg19"; |
| 4630 | case MCK_ACC128: return "MCK_ACC128"; |
| 4631 | case MCK_ACC64: return "MCK_ACC64"; |
| 4632 | case MCK_CPURAReg: return "MCK_CPURAReg"; |
| 4633 | case MCK_CPUSPReg: return "MCK_CPUSPReg"; |
| 4634 | case MCK_DSPCC: return "MCK_DSPCC"; |
| 4635 | case MCK_GP32: return "MCK_GP32"; |
| 4636 | case MCK_GP64: return "MCK_GP64"; |
| 4637 | case MCK_GPR32ZERO: return "MCK_GPR32ZERO"; |
| 4638 | case MCK_HI32: return "MCK_HI32"; |
| 4639 | case MCK_HI64: return "MCK_HI64"; |
| 4640 | case MCK_LO32: return "MCK_LO32"; |
| 4641 | case MCK_LO64: return "MCK_LO64"; |
| 4642 | case MCK_PC: return "MCK_PC"; |
| 4643 | case MCK_SP64: return "MCK_SP64"; |
| 4644 | case MCK_Reg32: return "MCK_Reg32"; |
| 4645 | case MCK_Reg13: return "MCK_Reg13"; |
| 4646 | case MCK_Reg33: return "MCK_Reg33"; |
| 4647 | case MCK_Reg31: return "MCK_Reg31"; |
| 4648 | case MCK_Reg30: return "MCK_Reg30"; |
| 4649 | case MCK_Reg14: return "MCK_Reg14"; |
| 4650 | case MCK_Reg11: return "MCK_Reg11"; |
| 4651 | case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst"; |
| 4652 | case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL"; |
| 4653 | case MCK_OCTEON_P: return "MCK_OCTEON_P"; |
| 4654 | case MCK_Reg28: return "MCK_Reg28"; |
| 4655 | case MCK_Reg23: return "MCK_Reg23"; |
| 4656 | case MCK_Reg9: return "MCK_Reg9"; |
| 4657 | case MCK_Reg4: return "MCK_Reg4"; |
| 4658 | case MCK_ACC64DSP: return "MCK_ACC64DSP"; |
| 4659 | case MCK_HI32DSP: return "MCK_HI32DSP"; |
| 4660 | case MCK_LO32DSP: return "MCK_LO32DSP"; |
| 4661 | case MCK_Reg34: return "MCK_Reg34"; |
| 4662 | case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond"; |
| 4663 | case MCK_Reg29: return "MCK_Reg29"; |
| 4664 | case MCK_Reg27: return "MCK_Reg27"; |
| 4665 | case MCK_Reg10: return "MCK_Reg10"; |
| 4666 | case MCK_Reg8: return "MCK_Reg8"; |
| 4667 | case MCK_Reg25: return "MCK_Reg25"; |
| 4668 | case MCK_Reg22: return "MCK_Reg22"; |
| 4669 | case MCK_Reg21: return "MCK_Reg21"; |
| 4670 | case MCK_CPU16Regs: return "MCK_CPU16Regs"; |
| 4671 | case MCK_FCC: return "MCK_FCC"; |
| 4672 | case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP"; |
| 4673 | case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero"; |
| 4674 | case MCK_Reg26: return "MCK_Reg26"; |
| 4675 | case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP"; |
| 4676 | case MCK_AFGR64: return "MCK_AFGR64"; |
| 4677 | case MCK_MSA128WEvens: return "MCK_MSA128WEvens"; |
| 4678 | case MCK_Reg24: return "MCK_Reg24"; |
| 4679 | case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO"; |
| 4680 | case MCK_CCR: return "MCK_CCR"; |
| 4681 | case MCK_COP0: return "MCK_COP0"; |
| 4682 | case MCK_COP2: return "MCK_COP2"; |
| 4683 | case MCK_COP3: return "MCK_COP3"; |
| 4684 | case MCK_DSPR: return "MCK_DSPR"; |
| 4685 | case MCK_FGR32: return "MCK_FGR32"; |
| 4686 | case MCK_FGR64: return "MCK_FGR64"; |
| 4687 | case MCK_GPR64: return "MCK_GPR64"; |
| 4688 | case MCK_HWRegs: return "MCK_HWRegs"; |
| 4689 | case MCK_MSA128F16: return "MCK_MSA128F16"; |
| 4690 | case MCK_MSACtrl: return "MCK_MSACtrl"; |
| 4691 | case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg"; |
| 4692 | case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg"; |
| 4693 | case MCK_CCRAsmReg: return "MCK_CCRAsmReg"; |
| 4694 | case MCK_COP0AsmReg: return "MCK_COP0AsmReg"; |
| 4695 | case MCK_COP2AsmReg: return "MCK_COP2AsmReg"; |
| 4696 | case MCK_COP3AsmReg: return "MCK_COP3AsmReg"; |
| 4697 | case MCK_FCCAsmReg: return "MCK_FCCAsmReg"; |
| 4698 | case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg"; |
| 4699 | case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg"; |
| 4700 | case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg"; |
| 4701 | case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg"; |
| 4702 | case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg"; |
| 4703 | case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg"; |
| 4704 | case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg"; |
| 4705 | case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP"; |
| 4706 | case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst"; |
| 4707 | case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond"; |
| 4708 | case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero"; |
| 4709 | case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg"; |
| 4710 | case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg"; |
| 4711 | case MCK_Imm: return "MCK_Imm"; |
| 4712 | case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg"; |
| 4713 | case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg"; |
| 4714 | case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg"; |
| 4715 | case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP"; |
| 4716 | case MCK_MicroMipsMem: return "MCK_MicroMipsMem"; |
| 4717 | case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP"; |
| 4718 | case MCK_InvNum: return "MCK_InvNum"; |
| 4719 | case MCK_JumpTarget: return "MCK_JumpTarget"; |
| 4720 | case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr"; |
| 4721 | case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4"; |
| 4722 | case MCK_MemOffsetSimm9_0: return "MCK_MemOffsetSimm9_0"; |
| 4723 | case MCK_MemOffsetSimm10_0: return "MCK_MemOffsetSimm10_0"; |
| 4724 | case MCK_MemOffsetSimm11_0: return "MCK_MemOffsetSimm11_0"; |
| 4725 | case MCK_MemOffsetSimm12_0: return "MCK_MemOffsetSimm12_0"; |
| 4726 | case MCK_MemOffsetSimm16_0: return "MCK_MemOffsetSimm16_0"; |
| 4727 | case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1"; |
| 4728 | case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2"; |
| 4729 | case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3"; |
| 4730 | case MCK_Mem: return "MCK_Mem"; |
| 4731 | case MCK_RegList16: return "MCK_RegList16"; |
| 4732 | case MCK_RegList: return "MCK_RegList"; |
| 4733 | case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2"; |
| 4734 | case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg"; |
| 4735 | case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg"; |
| 4736 | case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg"; |
| 4737 | case MCK_ConstantImmz: return "MCK_ConstantImmz"; |
| 4738 | case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0"; |
| 4739 | case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0"; |
| 4740 | case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1"; |
| 4741 | case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0"; |
| 4742 | case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0"; |
| 4743 | case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0"; |
| 4744 | case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0"; |
| 4745 | case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0"; |
| 4746 | case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1"; |
| 4747 | case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6"; |
| 4748 | case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm"; |
| 4749 | case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32"; |
| 4750 | case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6"; |
| 4751 | case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33"; |
| 4752 | case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64"; |
| 4753 | case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2"; |
| 4754 | case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0"; |
| 4755 | case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0"; |
| 4756 | case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2"; |
| 4757 | case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0"; |
| 4758 | case MCK_UImm7_N1: return "MCK_UImm7_N1"; |
| 4759 | case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0"; |
| 4760 | case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2"; |
| 4761 | case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0"; |
| 4762 | case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0"; |
| 4763 | case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0"; |
| 4764 | case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1"; |
| 4765 | case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0"; |
| 4766 | case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2"; |
| 4767 | case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3"; |
| 4768 | case MCK_SImm16: return "MCK_SImm16"; |
| 4769 | case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed"; |
| 4770 | case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed"; |
| 4771 | case MCK_UImm16: return "MCK_UImm16"; |
| 4772 | case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2"; |
| 4773 | case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed"; |
| 4774 | case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0"; |
| 4775 | case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0"; |
| 4776 | case MCK_SImm32: return "MCK_SImm32"; |
| 4777 | case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed"; |
| 4778 | case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced"; |
| 4779 | case NumMatchClassKinds: return "NumMatchClassKinds"; |
| 4780 | } |
| 4781 | llvm_unreachable("unhandled MatchClassKind!"); |
| 4782 | } |
| 4783 | |
| 4784 | #endif // NDEBUG |
| 4785 | FeatureBitset MipsAsmParser:: |
| 4786 | ComputeAvailableFeatures(const FeatureBitset &FB) const { |
| 4787 | FeatureBitset Features; |
| 4788 | if (FB[Mips::FeatureMips2]) |
| 4789 | Features.set(Feature_HasMips2Bit); |
| 4790 | if (FB[Mips::FeatureMips3_32]) |
| 4791 | Features.set(Feature_HasMips3_32Bit); |
| 4792 | if (FB[Mips::FeatureMips3_32r2]) |
| 4793 | Features.set(Feature_HasMips3_32r2Bit); |
| 4794 | if (FB[Mips::FeatureMips3]) |
| 4795 | Features.set(Feature_HasMips3Bit); |
| 4796 | if (!FB[Mips::FeatureMips3]) |
| 4797 | Features.set(Feature_NotMips3Bit); |
| 4798 | if (FB[Mips::FeatureMips4_32]) |
| 4799 | Features.set(Feature_HasMips4_32Bit); |
| 4800 | if (!FB[Mips::FeatureMips4_32]) |
| 4801 | Features.set(Feature_NotMips4_32Bit); |
| 4802 | if (FB[Mips::FeatureMips4_32r2]) |
| 4803 | Features.set(Feature_HasMips4_32r2Bit); |
| 4804 | if (FB[Mips::FeatureMips5_32r2]) |
| 4805 | Features.set(Feature_HasMips5_32r2Bit); |
| 4806 | if (FB[Mips::FeatureMips32]) |
| 4807 | Features.set(Feature_HasMips32Bit); |
| 4808 | if (FB[Mips::FeatureMips32r2]) |
| 4809 | Features.set(Feature_HasMips32r2Bit); |
| 4810 | if (FB[Mips::FeatureMips32r5]) |
| 4811 | Features.set(Feature_HasMips32r5Bit); |
| 4812 | if (FB[Mips::FeatureMips32r6]) |
| 4813 | Features.set(Feature_HasMips32r6Bit); |
| 4814 | if (!FB[Mips::FeatureMips32r6]) |
| 4815 | Features.set(Feature_NotMips32r6Bit); |
| 4816 | if (FB[Mips::FeatureGP64Bit]) |
| 4817 | Features.set(Feature_IsGP64bitBit); |
| 4818 | if (!FB[Mips::FeatureGP64Bit]) |
| 4819 | Features.set(Feature_IsGP32bitBit); |
| 4820 | if (FB[Mips::FeaturePTR64Bit]) |
| 4821 | Features.set(Feature_IsPTR64bitBit); |
| 4822 | if (!FB[Mips::FeaturePTR64Bit]) |
| 4823 | Features.set(Feature_IsPTR32bitBit); |
| 4824 | if (FB[Mips::FeatureMips64]) |
| 4825 | Features.set(Feature_HasMips64Bit); |
| 4826 | if (!FB[Mips::FeatureMips64]) |
| 4827 | Features.set(Feature_NotMips64Bit); |
| 4828 | if (FB[Mips::FeatureMips64r2]) |
| 4829 | Features.set(Feature_HasMips64r2Bit); |
| 4830 | if (FB[Mips::FeatureMips64r5]) |
| 4831 | Features.set(Feature_HasMips64r5Bit); |
| 4832 | if (FB[Mips::FeatureMips64r6]) |
| 4833 | Features.set(Feature_HasMips64r6Bit); |
| 4834 | if (!FB[Mips::FeatureMips64r6]) |
| 4835 | Features.set(Feature_NotMips64r6Bit); |
| 4836 | if (FB[Mips::FeatureMips16]) |
| 4837 | Features.set(Feature_InMips16ModeBit); |
| 4838 | if (!FB[Mips::FeatureMips16]) |
| 4839 | Features.set(Feature_NotInMips16ModeBit); |
| 4840 | if (FB[Mips::FeatureCnMips]) |
| 4841 | Features.set(Feature_HasCnMipsBit); |
| 4842 | if (!FB[Mips::FeatureCnMips]) |
| 4843 | Features.set(Feature_NotCnMipsBit); |
| 4844 | if (FB[Mips::FeatureCnMipsP]) |
| 4845 | Features.set(Feature_HasCnMipsPBit); |
| 4846 | if (!FB[Mips::FeatureCnMipsP]) |
| 4847 | Features.set(Feature_NotCnMipsPBit); |
| 4848 | if (FB[Mips::FeatureSym32]) |
| 4849 | Features.set(Feature_IsSym32Bit); |
| 4850 | if (!FB[Mips::FeatureSym32]) |
| 4851 | Features.set(Feature_IsSym64Bit); |
| 4852 | if (!FB[Mips::FeatureMips16]) |
| 4853 | Features.set(Feature_HasStdEncBit); |
| 4854 | if (FB[Mips::FeatureMicroMips]) |
| 4855 | Features.set(Feature_InMicroMipsBit); |
| 4856 | if (!FB[Mips::FeatureMicroMips]) |
| 4857 | Features.set(Feature_NotInMicroMipsBit); |
| 4858 | if (FB[Mips::FeatureEVA]) |
| 4859 | Features.set(Feature_HasEVABit); |
| 4860 | if (FB[Mips::FeatureMSA]) |
| 4861 | Features.set(Feature_HasMSABit); |
| 4862 | if (!FB[Mips::FeatureNoMadd4]) |
| 4863 | Features.set(Feature_HasMadd4Bit); |
| 4864 | if (FB[Mips::FeatureMT]) |
| 4865 | Features.set(Feature_HasMTBit); |
| 4866 | if (FB[Mips::FeatureUseIndirectJumpsHazard]) |
| 4867 | Features.set(Feature_UseIndirectJumpsHazardBit); |
| 4868 | if (!FB[Mips::FeatureUseIndirectJumpsHazard]) |
| 4869 | Features.set(Feature_NoIndirectJumpGuardsBit); |
| 4870 | if (FB[Mips::FeatureCRC]) |
| 4871 | Features.set(Feature_HasCRCBit); |
| 4872 | if (FB[Mips::FeatureVirt]) |
| 4873 | Features.set(Feature_HasVirtBit); |
| 4874 | if (FB[Mips::FeatureGINV]) |
| 4875 | Features.set(Feature_HasGINVBit); |
| 4876 | if (FB[Mips::FeatureFP64Bit]) |
| 4877 | Features.set(Feature_IsFP64bitBit); |
| 4878 | if (!FB[Mips::FeatureFP64Bit]) |
| 4879 | Features.set(Feature_NotFP64bitBit); |
| 4880 | if (FB[Mips::FeatureSingleFloat]) |
| 4881 | Features.set(Feature_IsSingleFloatBit); |
| 4882 | if (!FB[Mips::FeatureSingleFloat]) |
| 4883 | Features.set(Feature_IsNotSingleFloatBit); |
| 4884 | if (!FB[Mips::FeatureSoftFloat]) |
| 4885 | Features.set(Feature_IsNotSoftFloatBit); |
| 4886 | if (FB[Mips::FeatureMips3D]) |
| 4887 | Features.set(Feature_HasMips3DBit); |
| 4888 | if (FB[Mips::FeatureDSP]) |
| 4889 | Features.set(Feature_HasDSPBit); |
| 4890 | if (FB[Mips::FeatureDSPR2]) |
| 4891 | Features.set(Feature_HasDSPR2Bit); |
| 4892 | if (FB[Mips::FeatureDSPR3]) |
| 4893 | Features.set(Feature_HasDSPR3Bit); |
| 4894 | return Features; |
| 4895 | } |
| 4896 | |
| 4897 | static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser, |
| 4898 | unsigned Kind, const OperandVector &Operands, |
| 4899 | uint64_t &ErrorInfo) { |
| 4900 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
| 4901 | const uint8_t *Converter = ConversionTable[Kind]; |
| 4902 | for (const uint8_t *p = Converter; *p; p += 2) { |
| 4903 | switch (*p) { |
| 4904 | case CVT_Tied: { |
| 4905 | unsigned OpIdx = *(p + 1); |
| 4906 | assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - |
| 4907 | std::begin(TiedAsmOperandTable)) && |
| 4908 | "Tied operand not found"); |
| 4909 | unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; |
| 4910 | unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; |
| 4911 | if (OpndNum1 != OpndNum2) { |
| 4912 | auto &SrcOp1 = Operands[OpndNum1]; |
| 4913 | auto &SrcOp2 = Operands[OpndNum2]; |
| 4914 | if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) { |
| 4915 | ErrorInfo = OpndNum2; |
| 4916 | return false; |
| 4917 | } |
| 4918 | } |
| 4919 | break; |
| 4920 | } |
| 4921 | default: |
| 4922 | break; |
| 4923 | } |
| 4924 | } |
| 4925 | return true; |
| 4926 | } |
| 4927 | |
| 4928 | static const char MnemonicTable[] = |
| 4929 | "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a" |
| 4930 | "dd.d\006add.ps\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004" |
| 4931 | "addi\005addiu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007" |
| 4932 | "addq.ph\taddq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddq" |
| 4933 | "h_r.w\007addr.ps\010adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010add" |
| 4934 | "s_s.b\010adds_s.d\010adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010ad" |
| 4935 | "ds_u.h\010adds_u.w\005addsc\004addu\007addu.ph\007addu.qb\006addu16\tad" |
| 4936 | "du_s.ph\taddu_s.qb\010adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv." |
| 4937 | "h\006addv.w\007addvi.b\007addvi.d\007addvi.h\007addvi.w\005addwc\005ali" |
| 4938 | "gn\006aluipc\003and\005and.v\005and16\004andi\006andi.b\006andi16\006ap" |
| 4939 | "pend\010asub_s.b\010asub_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asu" |
| 4940 | "b_u.d\010asub_u.h\010asub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007" |
| 4941 | "ave_s.h\007ave_s.w\007ave_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_" |
| 4942 | "s.b\010aver_s.d\010aver_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver" |
| 4943 | "_u.h\010aver_u.w\001b\003b16\005baddu\003bal\004balc\006balign\005bbit0" |
| 4944 | "\007bbit032\005bbit1\007bbit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004b" |
| 4945 | "c1f\005bc1fl\006bc1nez\007bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc" |
| 4946 | "\006bc2nez\007bc2nezc\006bclr.b\006bclr.d\006bclr.h\006bclr.w\007bclri." |
| 4947 | "b\007bclri.d\007bclri.h\007bclri.w\003beq\004beqc\004beql\004beqz\006be" |
| 4948 | "qz16\007beqzalc\005beqzc\007beqzc16\005beqzl\003bge\004bgec\004bgel\004" |
| 4949 | "bgeu\005bgeuc\005bgeul\004bgez\006bgezal\007bgezalc\007bgezall\007bgeza" |
| 4950 | "ls\005bgezc\005bgezl\003bgt\004bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc" |
| 4951 | "\005bgtzc\005bgtzl\007binsl.b\007binsl.d\007binsl.h\007binsl.w\010binsl" |
| 4952 | "i.b\010binsli.d\010binsli.h\010binsli.w\007binsr.b\007binsr.d\007binsr." |
| 4953 | "h\007binsr.w\010binsri.b\010binsri.d\010binsri.h\010binsri.w\006bitrev\007" |
| 4954 | "bitswap\003ble\004blel\004bleu\005bleul\004blez\007blezalc\005blezc\005" |
| 4955 | "blezl\003blt\004bltc\004bltl\004bltu\005bltuc\005bltul\004bltz\006bltza" |
| 4956 | "l\007bltzalc\007bltzall\007bltzals\005bltzc\005bltzl\006bmnz.v\007bmnzi" |
| 4957 | ".b\005bmz.v\006bmzi.b\003bne\004bnec\006bneg.b\006bneg.d\006bneg.h\006b" |
| 4958 | "neg.w\007bnegi.b\007bnegi.d\007bnegi.h\007bnegi.w\004bnel\004bnez\006bn" |
| 4959 | "ez16\007bnezalc\005bnezc\007bnezc16\005bnezl\004bnvc\005bnz.b\005bnz.d\005" |
| 4960 | "bnz.h\005bnz.v\005bnz.w\004bovc\010bposge32\tbposge32c\005break\007brea" |
| 4961 | "k16\006bsel.v\007bseli.b\006bset.b\006bset.d\006bset.h\006bset.w\007bse" |
| 4962 | "ti.b\007bseti.d\007bseti.h\007bseti.w\005bteqz\005btnez\004bz.b\004bz.d" |
| 4963 | "\004bz.h\004bz.v\004bz.w\006c.eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le." |
| 4964 | "d\006c.le.s\006c.lt.d\006c.lt.s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.n" |
| 4965 | "gl.s\010c.ngle.d\010c.ngle.s\007c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole." |
| 4966 | "s\007c.olt.d\007c.olt.s\007c.seq.d\007c.seq.s\006c.sf.d\006c.sf.s\007c." |
| 4967 | "ueq.d\007c.ueq.s\007c.ule.d\007c.ule.s\007c.ult.d\007c.ult.s\006c.un.d\006" |
| 4968 | "c.un.s\005cache\006cachee\010ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w" |
| 4969 | ".s\005ceq.b\005ceq.d\005ceq.h\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006" |
| 4970 | "ceqi.w\004cfc1\004cfc2\006cfcmsa\005cftc1\004cins\006cins32\007class.d\007" |
| 4971 | "class.s\007cle_s.b\007cle_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u" |
| 4972 | ".d\007cle_u.h\007cle_u.w\010clei_s.b\010clei_s.d\010clei_s.h\010clei_s." |
| 4973 | "w\010clei_u.b\010clei_u.d\010clei_u.h\010clei_u.w\003clo\007clt_s.b\007" |
| 4974 | "clt_s.d\007clt_s.h\007clt_s.w\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u" |
| 4975 | ".w\010clti_s.b\010clti_s.d\010clti_s.h\010clti_s.w\010clti_u.b\010clti_" |
| 4976 | "u.d\010clti_u.h\010clti_u.w\003clz\003cmp\010cmp.af.d\010cmp.af.s\010cm" |
| 4977 | "p.eq.d\tcmp.eq.ph\010cmp.eq.s\010cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp" |
| 4978 | ".lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp.saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq." |
| 4979 | "s\tcmp.sle.d\tcmp.sle.s\tcmp.slt.d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\n" |
| 4980 | "cmp.sule.d\ncmp.sule.s\ncmp.sult.d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tc" |
| 4981 | "mp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tcmp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp." |
| 4982 | "un.d\010cmp.un.s\014cmpgdu.eq.qb\014cmpgdu.le.qb\014cmpgdu.lt.qb\013cmp" |
| 4983 | "gu.eq.qb\013cmpgu.le.qb\013cmpgu.lt.qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\n" |
| 4984 | "cmpu.lt.qb\010copy_s.b\010copy_s.d\010copy_s.h\010copy_s.w\010copy_u.b\010" |
| 4985 | "copy_u.h\010copy_u.w\006crc32b\007crc32cb\007crc32cd\007crc32ch\007crc3" |
| 4986 | "2cw\006crc32d\006crc32h\006crc32w\004ctc1\004ctc2\006ctcmsa\005cttc1\007" |
| 4987 | "cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.l.s\tcvt.ps.pw\010cvt.p" |
| 4988 | "s.s\tcvt.pw.ps\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s.pu\007cvt.s.w" |
| 4989 | "\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu\004dahi\006d" |
| 4990 | "align\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005ddivu\005d" |
| 4991 | "eret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dinsu\003div\005" |
| 4992 | "div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007" |
| 4993 | "div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005" |
| 4994 | "dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005d" |
| 4995 | "mtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006" |
| 4996 | "dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010" |
| 4997 | "dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpa" |
| 4998 | "dd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014" |
| 4999 | "dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpo" |
| 5000 | "p\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa" |
| 5001 | ".w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u" |
| 5002 | ".d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005" |
| 5003 | "drotr\007drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004" |
| 5004 | "dsra\006dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005" |
| 5005 | "dsubu\003dvp\004dvpe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004ev" |
| 5006 | "pe\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\t" |
| 5007 | "extr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004e" |
| 5008 | "xts\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq" |
| 5009 | ".w\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006f" |
| 5010 | "cne.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007" |
| 5011 | "fcule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w" |
| 5012 | "\006fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fex" |
| 5013 | "upl.d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_" |
| 5014 | "u.d\tffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fil" |
| 5015 | "l.d\006fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfl" |
| 5016 | "oor.w.d\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a." |
| 5017 | "d\010fmax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007" |
| 5018 | "fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007frint.d\007f" |
| 5019 | "rint.w\010frsqrt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006" |
| 5020 | "fsle.d\006fsle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006f" |
| 5021 | "sor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007" |
| 5022 | "fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d" |
| 5023 | "\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq" |
| 5024 | ".w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005ginvt\010" |
| 5025 | "hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010" |
| 5026 | "hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007" |
| 5027 | "hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl.b\006ilvl.d" |
| 5028 | "\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilvod.w\006ilv" |
| 5029 | "r.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010insert.d\010ins" |
| 5030 | "ert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007insve.w\001" |
| 5031 | "j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007jalrs16\004" |
| 5032 | "jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiusp\003jrc\005" |
| 5033 | "jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe\003lbu\005lb" |
| 5034 | "u16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ld" |
| 5035 | "c2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005" |
| 5036 | "ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004li.d\004li.s" |
| 5037 | "\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004lw16\004lw" |
| 5038 | "c1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lw" |
| 5039 | "p\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004lwxs\004mad" |
| 5040 | "d\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007maddf.s\tma" |
| 5041 | "ddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007maddv.w" |
| 5042 | "\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005max.d" |
| 5043 | "\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007max" |
| 5044 | "_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u.w\006" |
| 5045 | "maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010max" |
| 5046 | "i_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005mf" |
| 5047 | "gc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006m" |
| 5048 | "flo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mfth" |
| 5049 | "i\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007" |
| 5050 | "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u" |
| 5051 | ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010" |
| 5052 | "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003" |
| 5053 | "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007" |
| 5054 | "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move." |
| 5055 | "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m" |
| 5056 | "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006" |
| 5057 | "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q" |
| 5058 | ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m" |
| 5059 | "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt" |
| 5060 | "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006" |
| 5061 | "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl" |
| 5062 | "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\006mul.ps\005mul.s\007" |
| 5063 | "mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016mul" |
| 5064 | "eu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\t" |
| 5065 | "mulq_s.ph\010mulq_s.w\007mulr.ps\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015" |
| 5066 | "mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006" |
| 5067 | "mulv.w\003nal\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc.d\006n" |
| 5068 | "loc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd.d\007n" |
| 5069 | "madd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003not\005" |
| 5070 | "not16\002or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007pcke" |
| 5071 | "v.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod.h\007" |
| 5072 | "pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006" |
| 5073 | "pll.ps\006plu.ps\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.q" |
| 5074 | "bl\017precequ.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph" |
| 5075 | ".qbl\016preceu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.p" |
| 5076 | "h\016precr_sra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016" |
| 5077 | "precrq_rs.ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\006" |
| 5078 | "pul.ps\006puu.ps\nraddu.w.qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007" |
| 5079 | "recip.s\003rem\004remu\007repl.ph\007repl.qb\010replv.ph\010replv.qb\006" |
| 5080 | "rint.d\006rint.s\003rol\003ror\004rotr\005rotrv\tround.l.d\tround.l.s\t" |
| 5081 | "round.w.d\tround.w.s\007rsqrt.d\007rsqrt.s\003s.d\003s.s\003saa\004saad" |
| 5082 | "\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007sat_u.d\007s" |
| 5083 | "at_u.h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002sd\005sdb" |
| 5084 | "bp\007sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003seb\003" |
| 5085 | "seh\005sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selnez\010se" |
| 5086 | "lnez.d\010selnez.s\003seq\004seqi\003sge\004sgeu\003sgt\004sgtu\002sh\004" |
| 5087 | "sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov\007shll.ph\007" |
| 5088 | "shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\nshllv_s.ph\tshl" |
| 5089 | "lv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010shrav" |
| 5090 | ".ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007shrl.q" |
| 5091 | "b\010shrlv.ph\010shrlv.qb\006sigrie\005sld.b\005sld.d\005sld.h\005sld.w" |
| 5092 | "\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sle\004sleu\003sll\005sll.b" |
| 5093 | "\005sll.d\005sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006s" |
| 5094 | "lli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b" |
| 5095 | "\007splat.d\007splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010" |
| 5096 | "splati.w\006sqrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w" |
| 5097 | "\006srai.b\006srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006" |
| 5098 | "srar.w\007srari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005sr" |
| 5099 | "l.b\005srl.d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006" |
| 5100 | "srli.w\006srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007" |
| 5101 | "srlri.h\007srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003" |
| 5102 | "sub\005sub.d\006sub.ps\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010su" |
| 5103 | "bqh.ph\007subqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010sub" |
| 5104 | "s_s.h\010subs_s.w\010subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubs" |
| 5105 | "us_u.b\nsubsus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsub" |
| 5106 | "suu_s.h\nsubsuu_s.w\004subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\t" |
| 5107 | "subu_s.qb\010subuh.qb\nsubuh_r.qb\006subv.b\006subv.d\006subv.h\006subv" |
| 5108 | ".w\007subvi.b\007subvi.d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004" |
| 5109 | "swc1\004swc2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm32\003" |
| 5110 | "swp\003swr\004swre\004swsp\005swxc1\004sync\005synci\nsynciobdma\005syn" |
| 5111 | "cs\005syncw\006syncws\007syscall\003teq\004teqi\003tge\004tgei\005tgeiu" |
| 5112 | "\004tgeu\007tlbginv\010tlbginvf\005tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006" |
| 5113 | "tlbinv\007tlbinvf\004tlbp\004tlbr\005tlbwi\005tlbwr\003tlt\004tlti\005t" |
| 5114 | "ltiu\004tltu\003tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s" |
| 5115 | "\003ulh\004ulhu\003ulw\003ush\003usw\006v3mulu\004vmm0\005vmulu\006vshf" |
| 5116 | ".b\006vshf.d\006vshf.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004wsbh\003" |
| 5117 | "xor\005xor.v\005xor16\004xori\006xori.b\005yield"; |
| 5118 | |
| 5119 | // Feature bitsets. |
| 5120 | enum : uint8_t { |
| 5121 | AMFBS_None, |
| 5122 | AMFBS_HasCnMips, |
| 5123 | AMFBS_HasCnMipsP, |
| 5124 | AMFBS_HasDSP, |
| 5125 | AMFBS_HasDSPR2, |
| 5126 | AMFBS_HasMT, |
| 5127 | AMFBS_InMicroMips, |
| 5128 | AMFBS_InMips16Mode, |
| 5129 | AMFBS_IsGP32bit, |
| 5130 | AMFBS_IsGP64bit, |
| 5131 | AMFBS_IsNotSoftFloat, |
| 5132 | AMFBS_NotCnMips, |
| 5133 | AMFBS_NotInMicroMips, |
| 5134 | AMFBS_HasDSP_InMicroMips, |
| 5135 | AMFBS_HasDSP_NotInMicroMips, |
| 5136 | AMFBS_HasMT_NotInMicroMips, |
| 5137 | AMFBS_HasMips64_HasCnMips, |
| 5138 | AMFBS_HasStdEnc_HasMSA, |
| 5139 | AMFBS_HasStdEnc_HasMips3, |
| 5140 | AMFBS_HasStdEnc_HasMips32, |
| 5141 | AMFBS_HasStdEnc_HasMips32r6, |
| 5142 | AMFBS_HasStdEnc_HasMips64, |
| 5143 | AMFBS_HasStdEnc_HasMips64r6, |
| 5144 | AMFBS_HasStdEnc_IsNotSoftFloat, |
| 5145 | AMFBS_HasStdEnc_NotInMicroMips, |
| 5146 | AMFBS_HasStdEnc_NotMips3, |
| 5147 | AMFBS_InMicroMips_HasDSP, |
| 5148 | AMFBS_InMicroMips_HasDSPR2, |
| 5149 | AMFBS_InMicroMips_HasDSPR3, |
| 5150 | AMFBS_InMicroMips_HasEVA, |
| 5151 | AMFBS_InMicroMips_HasMips32r6, |
| 5152 | AMFBS_InMicroMips_IsNotSoftFloat, |
| 5153 | AMFBS_InMicroMips_NotMips32r6, |
| 5154 | AMFBS_IsFP64bit_IsNotSoftFloat, |
| 5155 | AMFBS_IsGP32bit_NotInMicroMips, |
| 5156 | AMFBS_IsGP64bit_NotInMicroMips, |
| 5157 | AMFBS_NotFP64bit_IsNotSoftFloat, |
| 5158 | AMFBS_NotInMips16Mode_HasDSP, |
| 5159 | AMFBS_NotInMips16Mode_IsPTR64bit, |
| 5160 | AMFBS_HasMips3_NotMips64r6_NotCnMips, |
| 5161 | AMFBS_HasMips64_HasCnMips_NotInMicroMips, |
| 5162 | AMFBS_HasStdEnc_HasMSA_HasMips64, |
| 5163 | AMFBS_HasStdEnc_HasMT_NotInMicroMips, |
| 5164 | AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, |
| 5165 | AMFBS_HasStdEnc_HasMips2_NotInMicroMips, |
| 5166 | AMFBS_HasStdEnc_HasMips3_NotInMicroMips, |
| 5167 | AMFBS_HasStdEnc_HasMips32_NotInMicroMips, |
| 5168 | AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, |
| 5169 | AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, |
| 5170 | AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, |
| 5171 | AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, |
| 5172 | AMFBS_HasStdEnc_HasMips64_NotInMicroMips, |
| 5173 | AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, |
| 5174 | AMFBS_HasStdEnc_HasMips64r5_HasVirt, |
| 5175 | AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, |
| 5176 | AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, |
| 5177 | AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, |
| 5178 | AMFBS_HasStdEnc_IsGP64bit_HasMips3, |
| 5179 | AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, |
| 5180 | AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, |
| 5181 | AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 5182 | AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, |
| 5183 | AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, |
| 5184 | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, |
| 5185 | AMFBS_InMicroMips_HasMips32r5_HasVirt, |
| 5186 | AMFBS_InMicroMips_HasMips32r6_HasGINV, |
| 5187 | AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, |
| 5188 | AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 5189 | AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, |
| 5190 | AMFBS_InMicroMips_NotMips32r6_HasDSP, |
| 5191 | AMFBS_InMicroMips_NotMips32r6_HasEVA, |
| 5192 | AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, |
| 5193 | AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, |
| 5194 | AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 5195 | AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, |
| 5196 | AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, |
| 5197 | AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, |
| 5198 | AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, |
| 5199 | AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, |
| 5200 | AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, |
| 5201 | AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, |
| 5202 | AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, |
| 5203 | AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, |
| 5204 | AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, |
| 5205 | AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, |
| 5206 | AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| 5207 | AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 5208 | AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, |
| 5209 | AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, |
| 5210 | AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, |
| 5211 | AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, |
| 5212 | AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 5213 | AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, |
| 5214 | AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, |
| 5215 | AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, |
| 5216 | AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, |
| 5217 | AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, |
| 5218 | AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 5219 | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5220 | AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, |
| 5221 | AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, |
| 5222 | AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, |
| 5223 | AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| 5224 | AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5225 | AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5226 | AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5227 | AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5228 | AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5229 | AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 5230 | AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 5231 | AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| 5232 | AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, |
| 5233 | AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| 5234 | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 5235 | AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, |
| 5236 | AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| 5237 | AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| 5238 | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| 5239 | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5240 | AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, |
| 5241 | AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| 5242 | AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5243 | AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, |
| 5244 | AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5245 | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| 5246 | AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5247 | AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5248 | AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| 5249 | AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5250 | AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 5251 | AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 5252 | AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, |
| 5253 | AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5254 | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5255 | AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5256 | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5257 | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5258 | AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| 5259 | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 5260 | AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 5261 | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| 5262 | AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| 5263 | }; |
| 5264 | |
| 5265 | static constexpr FeatureBitset FeatureBitsets[] = { |
| 5266 | {}, // AMFBS_None |
| 5267 | {Feature_HasCnMipsBit, }, |
| 5268 | {Feature_HasCnMipsPBit, }, |
| 5269 | {Feature_HasDSPBit, }, |
| 5270 | {Feature_HasDSPR2Bit, }, |
| 5271 | {Feature_HasMTBit, }, |
| 5272 | {Feature_InMicroMipsBit, }, |
| 5273 | {Feature_InMips16ModeBit, }, |
| 5274 | {Feature_IsGP32bitBit, }, |
| 5275 | {Feature_IsGP64bitBit, }, |
| 5276 | {Feature_IsNotSoftFloatBit, }, |
| 5277 | {Feature_NotCnMipsBit, }, |
| 5278 | {Feature_NotInMicroMipsBit, }, |
| 5279 | {Feature_HasDSPBit, Feature_InMicroMipsBit, }, |
| 5280 | {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
| 5281 | {Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
| 5282 | {Feature_HasMips64Bit, Feature_HasCnMipsBit, }, |
| 5283 | {Feature_HasStdEncBit, Feature_HasMSABit, }, |
| 5284 | {Feature_HasStdEncBit, Feature_HasMips3Bit, }, |
| 5285 | {Feature_HasStdEncBit, Feature_HasMips32Bit, }, |
| 5286 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, |
| 5287 | {Feature_HasStdEncBit, Feature_HasMips64Bit, }, |
| 5288 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, |
| 5289 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
| 5290 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 5291 | {Feature_HasStdEncBit, Feature_NotMips3Bit, }, |
| 5292 | {Feature_InMicroMipsBit, Feature_HasDSPBit, }, |
| 5293 | {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, |
| 5294 | {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, |
| 5295 | {Feature_InMicroMipsBit, Feature_HasEVABit, }, |
| 5296 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, |
| 5297 | {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
| 5298 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
| 5299 | {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 5300 | {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
| 5301 | {Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
| 5302 | {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 5303 | {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, |
| 5304 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, |
| 5305 | {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, |
| 5306 | {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 5307 | {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, |
| 5308 | {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
| 5309 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, |
| 5310 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, |
| 5311 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
| 5312 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, |
| 5313 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, |
| 5314 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, |
| 5315 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 5316 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, |
| 5317 | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotInMicroMipsBit, }, |
| 5318 | {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, |
| 5319 | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, |
| 5320 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5321 | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, }, |
| 5322 | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
| 5323 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, |
| 5324 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, |
| 5325 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, |
| 5326 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5327 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 5328 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| 5329 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 5330 | {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, |
| 5331 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, |
| 5332 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5333 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 5334 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 5335 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, |
| 5336 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, |
| 5337 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5338 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, |
| 5339 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5340 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 5341 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 5342 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5343 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 5344 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 5345 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| 5346 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 5347 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
| 5348 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| 5349 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, |
| 5350 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5351 | {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5352 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5353 | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5354 | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
| 5355 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| 5356 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, |
| 5357 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5358 | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 5359 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
| 5360 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| 5361 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5362 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, }, |
| 5363 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5364 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5365 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5366 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5367 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5368 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| 5369 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5370 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5371 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5372 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5373 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5374 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5375 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5376 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5377 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5378 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5379 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5380 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5381 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5382 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5383 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5384 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5385 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| 5386 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| 5387 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5388 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| 5389 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5390 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| 5391 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5392 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5393 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| 5394 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5395 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 5396 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 5397 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, |
| 5398 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5399 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5400 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5401 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5402 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5403 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 5404 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 5405 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 5406 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| 5407 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| 5408 | }; |
| 5409 | |
| 5410 | namespace { |
| 5411 | struct MatchEntry { |
| 5412 | uint16_t Mnemonic; |
| 5413 | uint16_t Opcode; |
| 5414 | uint16_t ConvertFn; |
| 5415 | uint8_t RequiredFeaturesIdx; |
| 5416 | uint8_t Classes[8]; |
| 5417 | StringRef getMnemonic() const { |
| 5418 | return StringRef(MnemonicTable + Mnemonic + 1, |
| 5419 | MnemonicTable[Mnemonic]); |
| 5420 | } |
| 5421 | }; |
| 5422 | |
| 5423 | // Predicate for searching for an opcode. |
| 5424 | struct LessOpcode { |
| 5425 | bool operator()(const MatchEntry &LHS, StringRef RHS) { |
| 5426 | return LHS.getMnemonic() < RHS; |
| 5427 | } |
| 5428 | bool operator()(StringRef LHS, const MatchEntry &RHS) { |
| 5429 | return LHS < RHS.getMnemonic(); |
| 5430 | } |
| 5431 | bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { |
| 5432 | return LHS.getMnemonic() < RHS.getMnemonic(); |
| 5433 | } |
| 5434 | }; |
| 5435 | } // end anonymous namespace |
| 5436 | |
| 5437 | static const MatchEntry MatchTable0[] = { |
| 5438 | { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5439 | { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5440 | { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5441 | { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5442 | { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5443 | { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5444 | { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5445 | { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5446 | { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5447 | { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5448 | { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5449 | { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5450 | { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5451 | { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5452 | { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5453 | { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5454 | { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5455 | { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5456 | { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5457 | { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5458 | { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5459 | { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5460 | { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5461 | { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5462 | { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5463 | { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5464 | { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5465 | { 55 /* add.ps */, Mips::FADD_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5466 | { 62 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5467 | { 62 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5468 | { 62 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5469 | { 68 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5470 | { 76 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5471 | { 84 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5472 | { 92 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5473 | { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5474 | { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
| 5475 | { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5476 | { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
| 5477 | { 105 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, }, |
| 5478 | { 105 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
| 5479 | { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5480 | { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5481 | { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
| 5482 | { 105 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, }, |
| 5483 | { 105 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, |
| 5484 | { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5485 | { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5486 | { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, |
| 5487 | { 105 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5488 | { 105 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5489 | { 111 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 5490 | { 111 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 5491 | { 111 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 5492 | { 119 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, }, |
| 5493 | { 129 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 5494 | { 137 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, }, |
| 5495 | { 145 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, }, |
| 5496 | { 153 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5497 | { 153 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5498 | { 161 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5499 | { 161 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5500 | { 171 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5501 | { 171 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5502 | { 180 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5503 | { 180 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5504 | { 189 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5505 | { 189 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5506 | { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5507 | { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5508 | { 208 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5509 | { 208 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5510 | { 218 /* addr.ps */, Mips::ADDR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5511 | { 226 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5512 | { 235 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5513 | { 244 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5514 | { 253 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5515 | { 262 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5516 | { 271 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5517 | { 280 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5518 | { 289 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5519 | { 298 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5520 | { 307 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5521 | { 316 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5522 | { 325 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5523 | { 334 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5524 | { 334 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5525 | { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5526 | { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5527 | { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5528 | { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5529 | { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5530 | { 340 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 5531 | { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5532 | { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5533 | { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5534 | { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5535 | { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5536 | { 345 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5537 | { 345 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5538 | { 353 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5539 | { 353 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5540 | { 361 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 5541 | { 361 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 5542 | { 368 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5543 | { 368 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5544 | { 378 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5545 | { 378 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5546 | { 388 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5547 | { 388 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5548 | { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5549 | { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5550 | { 408 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5551 | { 415 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5552 | { 422 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5553 | { 429 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5554 | { 436 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5555 | { 444 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5556 | { 452 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5557 | { 460 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5558 | { 468 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5559 | { 468 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5560 | { 474 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
| 5561 | { 474 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
| 5562 | { 480 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5563 | { 480 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5564 | { 487 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 5565 | { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5566 | { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5567 | { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5568 | { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5569 | { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5570 | { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5571 | { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 5572 | { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5573 | { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5574 | { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5575 | { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5576 | { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5577 | { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 5578 | { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 5579 | { 491 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5580 | { 497 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 5581 | { 497 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 5582 | { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5583 | { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5584 | { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5585 | { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5586 | { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5587 | { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5588 | { 508 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 5589 | { 515 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 5590 | { 515 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 5591 | { 522 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5592 | { 522 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5593 | { 529 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5594 | { 538 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5595 | { 547 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5596 | { 556 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5597 | { 565 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5598 | { 574 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5599 | { 583 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5600 | { 592 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5601 | { 601 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5602 | { 601 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 5603 | { 605 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5604 | { 605 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 5605 | { 611 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5606 | { 619 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5607 | { 627 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5608 | { 635 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5609 | { 643 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5610 | { 651 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5611 | { 659 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5612 | { 667 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5613 | { 675 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5614 | { 684 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5615 | { 693 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5616 | { 702 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5617 | { 711 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5618 | { 720 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5619 | { 729 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5620 | { 738 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5621 | { 747 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5622 | { 747 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, }, |
| 5623 | { 747 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget }, }, |
| 5624 | { 747 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, }, |
| 5625 | { 747 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5626 | { 749 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
| 5627 | { 749 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, }, |
| 5628 | { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 5629 | { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 5630 | { 759 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5631 | { 759 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, }, |
| 5632 | { 759 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, }, |
| 5633 | { 763 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, }, |
| 5634 | { 763 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
| 5635 | { 768 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
| 5636 | { 768 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
| 5637 | { 775 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, |
| 5638 | { 775 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, |
| 5639 | { 781 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, |
| 5640 | { 789 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, |
| 5641 | { 789 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, |
| 5642 | { 795 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, |
| 5643 | { 803 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5644 | { 803 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
| 5645 | { 806 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
| 5646 | { 811 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
| 5647 | { 818 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
| 5648 | { 826 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5649 | { 826 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, }, |
| 5650 | { 826 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
| 5651 | { 826 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
| 5652 | { 831 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5653 | { 831 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
| 5654 | { 837 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
| 5655 | { 844 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, |
| 5656 | { 852 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5657 | { 852 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, }, |
| 5658 | { 852 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
| 5659 | { 852 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
| 5660 | { 857 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5661 | { 857 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, |
| 5662 | { 863 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
| 5663 | { 870 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
| 5664 | { 878 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
| 5665 | { 885 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, |
| 5666 | { 893 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5667 | { 900 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5668 | { 907 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5669 | { 914 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5670 | { 921 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 5671 | { 929 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 5672 | { 937 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 5673 | { 945 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5674 | { 953 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5675 | { 953 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5676 | { 953 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5677 | { 957 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5678 | { 957 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5679 | { 957 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5680 | { 962 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5681 | { 962 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5682 | { 967 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, |
| 5683 | { 967 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5684 | { 967 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5685 | { 967 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5686 | { 972 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
| 5687 | { 972 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
| 5688 | { 979 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5689 | { 979 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5690 | { 987 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5691 | { 987 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5692 | { 987 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5693 | { 987 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5694 | { 993 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
| 5695 | { 1001 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5696 | { 1007 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5697 | { 1007 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5698 | { 1011 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5699 | { 1011 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5700 | { 1011 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5701 | { 1016 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5702 | { 1016 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5703 | { 1021 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5704 | { 1021 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5705 | { 1026 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5706 | { 1026 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5707 | { 1026 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5708 | { 1032 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5709 | { 1032 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5710 | { 1038 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5711 | { 1038 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5712 | { 1043 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5713 | { 1043 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5714 | { 1050 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5715 | { 1050 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5716 | { 1058 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5717 | { 1066 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5718 | { 1074 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5719 | { 1074 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5720 | { 1074 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5721 | { 1080 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5722 | { 1086 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5723 | { 1086 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5724 | { 1090 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5725 | { 1090 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5726 | { 1095 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5727 | { 1095 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5728 | { 1100 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5729 | { 1100 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5730 | { 1106 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5731 | { 1106 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5732 | { 1111 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5733 | { 1111 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5734 | { 1119 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5735 | { 1119 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5736 | { 1119 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5737 | { 1125 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5738 | { 1131 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5739 | { 1139 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5740 | { 1147 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5741 | { 1155 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5742 | { 1163 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 5743 | { 1172 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 5744 | { 1181 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 5745 | { 1190 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5746 | { 1199 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5747 | { 1207 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5748 | { 1215 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5749 | { 1223 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5750 | { 1231 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 5751 | { 1240 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 5752 | { 1249 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 5753 | { 1258 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5754 | { 1267 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5755 | { 1267 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5756 | { 1274 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5757 | { 1274 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 5758 | { 1282 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5759 | { 1282 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5760 | { 1286 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5761 | { 1286 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5762 | { 1291 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5763 | { 1291 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5764 | { 1296 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5765 | { 1296 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5766 | { 1302 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5767 | { 1302 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5768 | { 1307 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5769 | { 1307 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5770 | { 1315 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5771 | { 1315 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5772 | { 1315 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5773 | { 1321 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5774 | { 1327 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5775 | { 1327 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5776 | { 1331 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5777 | { 1331 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5778 | { 1331 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5779 | { 1336 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5780 | { 1336 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5781 | { 1341 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5782 | { 1341 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5783 | { 1346 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5784 | { 1346 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5785 | { 1346 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5786 | { 1352 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5787 | { 1352 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5788 | { 1358 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5789 | { 1358 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5790 | { 1363 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5791 | { 1363 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5792 | { 1370 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5793 | { 1370 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5794 | { 1378 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5795 | { 1386 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5796 | { 1394 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5797 | { 1394 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5798 | { 1394 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5799 | { 1400 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5800 | { 1406 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5801 | { 1413 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 5802 | { 1421 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5803 | { 1427 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 5804 | { 1434 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5805 | { 1434 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5806 | { 1434 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5807 | { 1438 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5808 | { 1438 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5809 | { 1438 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5810 | { 1443 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5811 | { 1450 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5812 | { 1457 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5813 | { 1464 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5814 | { 1471 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 5815 | { 1479 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 5816 | { 1487 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 5817 | { 1495 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5818 | { 1503 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5819 | { 1503 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, |
| 5820 | { 1508 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, |
| 5821 | { 1508 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5822 | { 1508 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5823 | { 1508 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5824 | { 1513 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
| 5825 | { 1513 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
| 5826 | { 1520 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5827 | { 1520 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5828 | { 1528 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5829 | { 1528 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5830 | { 1528 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5831 | { 1528 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 5832 | { 1534 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, |
| 5833 | { 1542 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5834 | { 1548 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5835 | { 1548 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5836 | { 1553 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5837 | { 1559 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5838 | { 1565 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5839 | { 1571 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5840 | { 1577 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5841 | { 1583 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5842 | { 1583 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 5843 | { 1588 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_HasDSP, { MCK_JumpTarget }, }, |
| 5844 | { 1588 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, AMFBS_HasDSP_NotInMicroMips, { MCK_JumpTarget }, }, |
| 5845 | { 1597 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasDSPR3, { MCK_JumpTarget }, }, |
| 5846 | { 1607 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 5847 | { 1607 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, { }, }, |
| 5848 | { 1607 /* break */, Mips::Break16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_0 }, }, |
| 5849 | { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, |
| 5850 | { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
| 5851 | { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, |
| 5852 | { 1607 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, |
| 5853 | { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, |
| 5854 | { 1613 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, }, |
| 5855 | { 1613 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, }, |
| 5856 | { 1621 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5857 | { 1628 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 5858 | { 1636 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5859 | { 1643 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5860 | { 1650 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5861 | { 1657 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 5862 | { 1664 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 5863 | { 1672 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 5864 | { 1680 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 5865 | { 1688 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 5866 | { 1696 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, }, |
| 5867 | { 1696 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5868 | { 1702 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, }, |
| 5869 | { 1702 /* btnez */, Mips::Btnez16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 5870 | { 1708 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5871 | { 1713 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5872 | { 1718 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5873 | { 1723 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5874 | { 1728 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, |
| 5875 | { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5876 | { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5877 | { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5878 | { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5879 | { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5880 | { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5881 | { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5882 | { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5883 | { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5884 | { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5885 | { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5886 | { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5887 | { 1747 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5888 | { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5889 | { 1747 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5890 | { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5891 | { 1747 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5892 | { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5893 | { 1747 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5894 | { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5895 | { 1753 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5896 | { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5897 | { 1753 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5898 | { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5899 | { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5900 | { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5901 | { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5902 | { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5903 | { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5904 | { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5905 | { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5906 | { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5907 | { 1766 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5908 | { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5909 | { 1766 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5910 | { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5911 | { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5912 | { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5913 | { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5914 | { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5915 | { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5916 | { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5917 | { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5918 | { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5919 | { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5920 | { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5921 | { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5922 | { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5923 | { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5924 | { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5925 | { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5926 | { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5927 | { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5928 | { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5929 | { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5930 | { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5931 | { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5932 | { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5933 | { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5934 | { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5935 | { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5936 | { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5937 | { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5938 | { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5939 | { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5940 | { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5941 | { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5942 | { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5943 | { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5944 | { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5945 | { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5946 | { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5947 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5948 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5949 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5950 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5951 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5952 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5953 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5954 | { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5955 | { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5956 | { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5957 | { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5958 | { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5959 | { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5960 | { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5961 | { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5962 | { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5963 | { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5964 | { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5965 | { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5966 | { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5967 | { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5968 | { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5969 | { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5970 | { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5971 | { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5972 | { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5973 | { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5974 | { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5975 | { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5976 | { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5977 | { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5978 | { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5979 | { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5980 | { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5981 | { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5982 | { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5983 | { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5984 | { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5985 | { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5986 | { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5987 | { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5988 | { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5989 | { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5990 | { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5991 | { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5992 | { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5993 | { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5994 | { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 5995 | { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5996 | { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 5997 | { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5998 | { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 5999 | { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6000 | { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6001 | { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6002 | { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6003 | { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6004 | { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6005 | { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6006 | { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6007 | { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6008 | { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6009 | { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6010 | { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6011 | { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6012 | { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6013 | { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6014 | { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6015 | { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6016 | { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6017 | { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6018 | { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6019 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6020 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6021 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6022 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6023 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6024 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6025 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6026 | { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6027 | { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6028 | { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6029 | { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6030 | { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6031 | { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6032 | { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6033 | { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6034 | { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6035 | { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6036 | { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6037 | { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6038 | { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6039 | { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6040 | { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6041 | { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6042 | { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6043 | { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6044 | { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6045 | { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6046 | { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6047 | { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6048 | { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6049 | { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6050 | { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6051 | { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6052 | { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6053 | { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6054 | { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6055 | { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6056 | { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6057 | { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6058 | { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6059 | { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6060 | { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6061 | { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6062 | { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6063 | { 1970 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6064 | { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6065 | { 1970 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6066 | { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6067 | { 1977 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, |
| 6068 | { 1977 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
| 6069 | { 1977 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
| 6070 | { 1977 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
| 6071 | { 1983 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, |
| 6072 | { 1983 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, |
| 6073 | { 1990 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6074 | { 1990 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6075 | { 1999 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6076 | { 1999 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6077 | { 2008 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6078 | { 2008 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6079 | { 2008 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6080 | { 2008 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6081 | { 2017 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6082 | { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6083 | { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6084 | { 2026 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6085 | { 2032 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6086 | { 2038 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6087 | { 2044 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6088 | { 2050 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6089 | { 2057 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6090 | { 2064 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6091 | { 2071 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6092 | { 2078 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
| 6093 | { 2078 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
| 6094 | { 2083 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 6095 | { 2088 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, }, |
| 6096 | { 2095 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6097 | { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6098 | { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
| 6099 | { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6100 | { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
| 6101 | { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6102 | { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6103 | { 2113 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6104 | { 2113 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6105 | { 2121 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6106 | { 2121 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6107 | { 2129 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6108 | { 2137 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6109 | { 2145 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6110 | { 2153 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6111 | { 2161 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6112 | { 2169 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6113 | { 2177 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6114 | { 2185 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6115 | { 2193 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6116 | { 2202 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6117 | { 2211 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6118 | { 2220 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6119 | { 2229 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6120 | { 2238 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6121 | { 2247 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6122 | { 2256 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6123 | { 2265 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6124 | { 2265 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6125 | { 2265 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6126 | { 2265 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6127 | { 2269 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6128 | { 2277 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6129 | { 2285 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6130 | { 2293 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6131 | { 2301 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6132 | { 2309 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6133 | { 2317 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6134 | { 2325 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6135 | { 2333 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6136 | { 2342 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6137 | { 2351 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6138 | { 2360 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6139 | { 2369 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6140 | { 2378 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6141 | { 2387 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6142 | { 2396 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6143 | { 2405 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6144 | { 2405 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6145 | { 2405 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6146 | { 2405 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6147 | { 2409 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 6148 | { 2413 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6149 | { 2413 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6150 | { 2422 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6151 | { 2422 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6152 | { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6153 | { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6154 | { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6155 | { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6156 | { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6157 | { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6158 | { 2459 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6159 | { 2459 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6160 | { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6161 | { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6162 | { 2478 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6163 | { 2478 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6164 | { 2487 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6165 | { 2487 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6166 | { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6167 | { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6168 | { 2506 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6169 | { 2506 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6170 | { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6171 | { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6172 | { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6173 | { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6174 | { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6175 | { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6176 | { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6177 | { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6178 | { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6179 | { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6180 | { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6181 | { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6182 | { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6183 | { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6184 | { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6185 | { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6186 | { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6187 | { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6188 | { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6189 | { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6190 | { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6191 | { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6192 | { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6193 | { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6194 | { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6195 | { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6196 | { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6197 | { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6198 | { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6199 | { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6200 | { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6201 | { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6202 | { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6203 | { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6204 | { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6205 | { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6206 | { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6207 | { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6208 | { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6209 | { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6210 | { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6211 | { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6212 | { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6213 | { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6214 | { 2741 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6215 | { 2741 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6216 | { 2750 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6217 | { 2750 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6218 | { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6219 | { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6220 | { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6221 | { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6222 | { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6223 | { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6224 | { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6225 | { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6226 | { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6227 | { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6228 | { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6229 | { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6230 | { 2834 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
| 6231 | { 2834 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 6232 | { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6233 | { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6234 | { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6235 | { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6236 | { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6237 | { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6238 | { 2872 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
| 6239 | { 2881 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, |
| 6240 | { 2890 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
| 6241 | { 2899 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
| 6242 | { 2908 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
| 6243 | { 2917 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
| 6244 | { 2926 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
| 6245 | { 2935 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6246 | { 2942 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6247 | { 2950 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6248 | { 2958 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6249 | { 2966 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6250 | { 2974 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6251 | { 2981 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6252 | { 2988 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6253 | { 2995 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
| 6254 | { 2995 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, |
| 6255 | { 3000 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 6256 | { 3005 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, }, |
| 6257 | { 3012 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6258 | { 3018 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6259 | { 3018 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6260 | { 3026 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6261 | { 3026 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6262 | { 3026 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6263 | { 3026 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6264 | { 3034 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6265 | { 3034 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6266 | { 3034 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6267 | { 3034 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6268 | { 3042 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6269 | { 3042 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6270 | { 3042 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6271 | { 3050 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6272 | { 3050 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6273 | { 3050 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6274 | { 3058 /* cvt.ps.pw */, Mips::CVT_PS_PW64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6275 | { 3068 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6276 | { 3077 /* cvt.pw.ps */, Mips::CVT_PW_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6277 | { 3087 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6278 | { 3087 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6279 | { 3087 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6280 | { 3087 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6281 | { 3095 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6282 | { 3095 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6283 | { 3103 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6284 | { 3112 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6285 | { 3121 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6286 | { 3121 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6287 | { 3121 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6288 | { 3129 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6289 | { 3129 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6290 | { 3129 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6291 | { 3129 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6292 | { 3137 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6293 | { 3137 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6294 | { 3137 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6295 | { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6296 | { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6297 | { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6298 | { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6299 | { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6300 | { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6301 | { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6302 | { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6303 | { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6304 | { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6305 | { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6306 | { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, |
| 6307 | { 3169 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, |
| 6308 | { 3174 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6309 | { 3181 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, |
| 6310 | { 3186 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, }, |
| 6311 | { 3191 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6312 | { 3200 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6313 | { 3200 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6314 | { 3205 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6315 | { 3205 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6316 | { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6317 | { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 6318 | { 3210 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6319 | { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6320 | { 3210 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6321 | { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 6322 | { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6323 | { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 6324 | { 3215 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6325 | { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6326 | { 3215 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6327 | { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 6328 | { 3221 /* deret */, Mips::DERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { }, }, |
| 6329 | { 3221 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6330 | { 3221 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 6331 | { 3227 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, |
| 6332 | { 3227 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
| 6333 | { 3227 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, }, |
| 6334 | { 3232 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, |
| 6335 | { 3238 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
| 6336 | { 3244 /* di */, Mips::DI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, |
| 6337 | { 3244 /* di */, Mips::DI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6338 | { 3244 /* di */, Mips::DI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, }, |
| 6339 | { 3244 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6340 | { 3244 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6341 | { 3244 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
| 6342 | { 3247 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, |
| 6343 | { 3247 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
| 6344 | { 3247 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, }, |
| 6345 | { 3252 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, |
| 6346 | { 3258 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, |
| 6347 | { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6348 | { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 6349 | { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, |
| 6350 | { 3264 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, |
| 6351 | { 3264 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 6352 | { 3264 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6353 | { 3264 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6354 | { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6355 | { 3264 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6356 | { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 6357 | { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6358 | { 3268 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6359 | { 3268 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6360 | { 3268 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6361 | { 3268 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6362 | { 3274 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6363 | { 3274 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6364 | { 3274 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6365 | { 3280 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6366 | { 3288 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6367 | { 3296 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6368 | { 3304 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6369 | { 3312 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6370 | { 3320 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6371 | { 3328 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6372 | { 3336 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6373 | { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6374 | { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 6375 | { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, |
| 6376 | { 3344 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, |
| 6377 | { 3344 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 6378 | { 3344 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6379 | { 3344 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6380 | { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6381 | { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6382 | { 3344 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6383 | { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 6384 | { 3349 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 6385 | { 3349 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 6386 | { 3353 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 6387 | { 3357 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, |
| 6388 | { 3357 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, |
| 6389 | { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
| 6390 | { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6391 | { 3368 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6392 | { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, |
| 6393 | { 3374 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, |
| 6394 | { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6395 | { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
| 6396 | { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6397 | { 3387 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6398 | { 3392 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6399 | { 3398 /* dmt */, Mips::DMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
| 6400 | { 3398 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6401 | { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
| 6402 | { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6403 | { 3408 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6404 | { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, |
| 6405 | { 3414 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, |
| 6406 | { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6407 | { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, |
| 6408 | { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 6409 | { 3427 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6410 | { 3432 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6411 | { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6412 | { 3438 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasMips3_NotMips64r6_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6413 | { 3438 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6414 | { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6415 | { 3438 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
| 6416 | { 3443 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6417 | { 3449 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6418 | { 3456 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6419 | { 3462 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6420 | { 3469 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6421 | { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
| 6422 | { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6423 | { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
| 6424 | { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6425 | { 3486 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6426 | { 3495 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6427 | { 3504 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6428 | { 3513 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6429 | { 3522 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6430 | { 3531 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6431 | { 3540 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6432 | { 3540 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6433 | { 3549 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6434 | { 3559 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6435 | { 3569 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6436 | { 3579 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6437 | { 3589 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6438 | { 3599 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6439 | { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6440 | { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6441 | { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6442 | { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6443 | { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6444 | { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6445 | { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6446 | { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6447 | { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6448 | { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6449 | { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6450 | { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6451 | { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6452 | { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6453 | { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 6454 | { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6455 | { 3697 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6456 | { 3697 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6457 | { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6458 | { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6459 | { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6460 | { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6461 | { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6462 | { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6463 | { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6464 | { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6465 | { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6466 | { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6467 | { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6468 | { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6469 | { 3779 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6470 | { 3789 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6471 | { 3799 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6472 | { 3809 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6473 | { 3819 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6474 | { 3829 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6475 | { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6476 | { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6477 | { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6478 | { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
| 6479 | { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6480 | { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
| 6481 | { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6482 | { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
| 6483 | { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6484 | { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, |
| 6485 | { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6486 | { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 6487 | { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6488 | { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 6489 | { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6490 | { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 6491 | { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6492 | { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 6493 | { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6494 | { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6495 | { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6496 | { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6497 | { 3884 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6498 | { 3891 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6499 | { 3896 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6500 | { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6501 | { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6502 | { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6503 | { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6504 | { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6505 | { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6506 | { 3913 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6507 | { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6508 | { 3919 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6509 | { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6510 | { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6511 | { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6512 | { 3931 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6513 | { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6514 | { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6515 | { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6516 | { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, |
| 6517 | { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6518 | { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6519 | { 3949 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, |
| 6520 | { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6521 | { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, |
| 6522 | { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6523 | { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, |
| 6524 | { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, |
| 6525 | { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, |
| 6526 | { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6527 | { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, }, |
| 6528 | { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6529 | { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, |
| 6530 | { 3972 /* dvp */, Mips::DVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, }, |
| 6531 | { 3972 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6532 | { 3972 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6533 | { 3972 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6534 | { 3976 /* dvpe */, Mips::DVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
| 6535 | { 3976 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6536 | { 3981 /* ehb */, Mips::EHB, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 6537 | { 3981 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6538 | { 3981 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 6539 | { 3985 /* ei */, Mips::EI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, |
| 6540 | { 3985 /* ei */, Mips::EI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6541 | { 3985 /* ei */, Mips::EI_MM, Convert__regZERO, AMFBS_InMicroMips, { }, }, |
| 6542 | { 3985 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6543 | { 3985 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6544 | { 3985 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
| 6545 | { 3988 /* emt */, Mips::EMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
| 6546 | { 3988 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6547 | { 3992 /* eret */, Mips::ERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, }, |
| 6548 | { 3992 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6549 | { 3992 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 6550 | { 3997 /* eretnc */, Mips::ERETNC, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, { }, }, |
| 6551 | { 3997 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6552 | { 4004 /* evp */, Mips::EVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, { }, }, |
| 6553 | { 4004 /* evp */, Mips::EVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 6554 | { 4004 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6555 | { 4004 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6556 | { 4008 /* evpe */, Mips::EVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, { }, }, |
| 6557 | { 4008 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6558 | { 4013 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
| 6559 | { 4013 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
| 6560 | { 4013 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
| 6561 | { 4017 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6562 | { 4017 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6563 | { 4022 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6564 | { 4022 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6565 | { 4029 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6566 | { 4029 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6567 | { 4037 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6568 | { 4037 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6569 | { 4043 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6570 | { 4043 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6571 | { 4050 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6572 | { 4050 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6573 | { 4059 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6574 | { 4059 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6575 | { 4069 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6576 | { 4069 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, |
| 6577 | { 4078 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6578 | { 4078 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6579 | { 4086 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6580 | { 4086 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6581 | { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6582 | { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6583 | { 4107 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6584 | { 4107 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 6585 | { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6586 | { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
| 6587 | { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6588 | { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, |
| 6589 | { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6590 | { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, |
| 6591 | { 4129 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6592 | { 4136 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6593 | { 4143 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6594 | { 4150 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6595 | { 4157 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6596 | { 4164 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6597 | { 4171 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6598 | { 4180 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6599 | { 4189 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6600 | { 4196 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6601 | { 4203 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6602 | { 4210 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6603 | { 4217 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6604 | { 4224 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6605 | { 4231 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6606 | { 4238 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6607 | { 4245 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6608 | { 4253 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6609 | { 4261 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6610 | { 4269 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6611 | { 4277 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6612 | { 4285 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6613 | { 4293 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6614 | { 4300 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6615 | { 4307 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6616 | { 4315 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6617 | { 4323 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6618 | { 4330 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6619 | { 4337 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6620 | { 4345 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6621 | { 4353 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6622 | { 4361 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6623 | { 4369 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6624 | { 4378 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6625 | { 4387 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6626 | { 4396 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6627 | { 4405 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6628 | { 4415 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6629 | { 4425 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6630 | { 4435 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6631 | { 4445 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6632 | { 4452 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6633 | { 4459 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6634 | { 4466 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6635 | { 4473 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, |
| 6636 | { 4480 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, }, |
| 6637 | { 4487 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, |
| 6638 | { 4494 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, |
| 6639 | { 4501 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6640 | { 4509 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6641 | { 4517 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6642 | { 4517 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6643 | { 4527 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6644 | { 4527 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 6645 | { 4537 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6646 | { 4537 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6647 | { 4537 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 6648 | { 4537 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 6649 | { 4547 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6650 | { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6651 | { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6652 | { 4557 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6653 | { 4565 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6654 | { 4573 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6655 | { 4580 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6656 | { 4587 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6657 | { 4596 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6658 | { 4605 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6659 | { 4612 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6660 | { 4619 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6661 | { 4628 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6662 | { 4637 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6663 | { 4645 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6664 | { 4653 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6665 | { 4660 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6666 | { 4667 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6667 | { 4672 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6668 | { 4679 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6669 | { 4686 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6670 | { 4694 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6671 | { 4702 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6672 | { 4711 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6673 | { 4720 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6674 | { 4727 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6675 | { 4734 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6676 | { 4741 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6677 | { 4748 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6678 | { 4755 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6679 | { 4762 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6680 | { 4769 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6681 | { 4776 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6682 | { 4783 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6683 | { 4790 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6684 | { 4797 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6685 | { 4804 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6686 | { 4812 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6687 | { 4820 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6688 | { 4827 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6689 | { 4834 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6690 | { 4842 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6691 | { 4850 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6692 | { 4858 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6693 | { 4866 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6694 | { 4874 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6695 | { 4882 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6696 | { 4889 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6697 | { 4896 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6698 | { 4904 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6699 | { 4912 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6700 | { 4922 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6701 | { 4932 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6702 | { 4942 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6703 | { 4952 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6704 | { 4958 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6705 | { 4964 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6706 | { 4975 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6707 | { 4986 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6708 | { 4997 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6709 | { 5008 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6710 | { 5008 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg }, }, |
| 6711 | { 5014 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
| 6712 | { 5014 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, |
| 6713 | { 5020 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6714 | { 5029 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6715 | { 5038 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6716 | { 5047 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6717 | { 5056 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6718 | { 5065 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6719 | { 5074 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6720 | { 5083 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6721 | { 5092 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6722 | { 5101 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6723 | { 5110 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6724 | { 5119 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6725 | { 5128 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 6726 | { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 6727 | { 5128 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, |
| 6728 | { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_ConstantUImm10_0 }, }, |
| 6729 | { 5136 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6730 | { 5144 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6731 | { 5152 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6732 | { 5160 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6733 | { 5168 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6734 | { 5175 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6735 | { 5182 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6736 | { 5189 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6737 | { 5196 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6738 | { 5204 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6739 | { 5212 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6740 | { 5220 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6741 | { 5228 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6742 | { 5235 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6743 | { 5242 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6744 | { 5249 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6745 | { 5256 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
| 6746 | { 5256 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
| 6747 | { 5256 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, |
| 6748 | { 5260 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, }, |
| 6749 | { 5269 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, }, |
| 6750 | { 5278 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, }, |
| 6751 | { 5287 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, }, |
| 6752 | { 5296 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6753 | { 5296 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6754 | { 5301 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
| 6755 | { 5309 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
| 6756 | { 5317 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
| 6757 | { 5325 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, |
| 6758 | { 5333 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6759 | { 5333 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 6760 | { 5333 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, |
| 6761 | { 5333 /* j */, Mips::J, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, |
| 6762 | { 5335 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, }, |
| 6763 | { 5335 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, |
| 6764 | { 5335 /* jal */, Mips::JAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, }, |
| 6765 | { 5335 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, }, |
| 6766 | { 5335 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6767 | { 5339 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 6768 | { 5339 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6769 | { 5339 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6770 | { 5339 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6771 | { 5339 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6772 | { 5339 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_IsPTR64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6773 | { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6774 | { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
| 6775 | { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6776 | { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 6777 | { 5352 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
| 6778 | { 5352 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6779 | { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6780 | { 5352 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, |
| 6781 | { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6782 | { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6783 | { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6784 | { 5367 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6785 | { 5373 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 6786 | { 5381 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, }, |
| 6787 | { 5386 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, }, |
| 6788 | { 5386 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, }, |
| 6789 | { 5391 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 6790 | { 5391 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 6791 | { 5391 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 6792 | { 5397 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 6793 | { 5397 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, |
| 6794 | { 5397 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 6795 | { 5401 /* jr */, Mips::JrRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, }, |
| 6796 | { 5401 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6797 | { 5401 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 6798 | { 5401 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 6799 | { 5401 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
| 6800 | { 5401 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, |
| 6801 | { 5404 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg }, }, |
| 6802 | { 5404 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6803 | { 5404 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg }, }, |
| 6804 | { 5404 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, }, |
| 6805 | { 5410 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 6806 | { 5415 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_NotMips32r6, { MCK_UImm5Lsl2 }, }, |
| 6807 | { 5425 /* jrc */, Mips::JrcRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, }, |
| 6808 | { 5425 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
| 6809 | { 5425 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6810 | { 5425 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 6811 | { 5425 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, }, |
| 6812 | { 5429 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 6813 | { 5435 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, }, |
| 6814 | { 5446 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6815 | { 5446 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6816 | { 5450 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6817 | { 5454 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, |
| 6818 | { 5454 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6819 | { 5457 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 6820 | { 5457 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 6821 | { 5462 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6822 | { 5462 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6823 | { 5462 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6824 | { 5465 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6825 | { 5465 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6826 | { 5469 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6827 | { 5469 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6828 | { 5469 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6829 | { 5473 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, |
| 6830 | { 5479 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6831 | { 5479 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6832 | { 5484 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6833 | { 5484 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6834 | { 5489 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6835 | { 5489 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6836 | { 5492 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, }, |
| 6837 | { 5497 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, |
| 6838 | { 5502 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, |
| 6839 | { 5507 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, |
| 6840 | { 5512 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6841 | { 5512 /* ldc1 */, Mips::LDC1_MM_D32, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6842 | { 5512 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6843 | { 5512 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6844 | { 5512 /* ldc1 */, Mips::LDC1_MM_D64, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6845 | { 5517 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 6846 | { 5517 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 6847 | { 5517 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6848 | { 5522 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
| 6849 | { 5527 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
| 6850 | { 5533 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
| 6851 | { 5539 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
| 6852 | { 5545 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, |
| 6853 | { 5551 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 6854 | { 5555 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, |
| 6855 | { 5560 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 6856 | { 5564 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6857 | { 5564 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6858 | { 5570 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6859 | { 5570 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6860 | { 5573 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6861 | { 5573 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6862 | { 5577 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6863 | { 5577 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6864 | { 5581 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, |
| 6865 | { 5587 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6866 | { 5587 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6867 | { 5592 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6868 | { 5592 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6869 | { 5596 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
| 6870 | { 5596 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 6871 | { 5596 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 6872 | { 5599 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, |
| 6873 | { 5599 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, }, |
| 6874 | { 5599 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, }, |
| 6875 | { 5604 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, }, |
| 6876 | { 5604 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, }, |
| 6877 | { 5609 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, |
| 6878 | { 5609 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, |
| 6879 | { 5614 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6880 | { 5614 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6881 | { 5614 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6882 | { 5614 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6883 | { 5614 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6884 | { 5614 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6885 | { 5617 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6886 | { 5617 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 6887 | { 5621 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6888 | { 5621 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6889 | { 5625 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, |
| 6890 | { 5625 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, |
| 6891 | { 5625 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, |
| 6892 | { 5629 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 6893 | { 5629 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, |
| 6894 | { 5629 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, |
| 6895 | { 5633 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6896 | { 5633 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6897 | { 5633 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6898 | { 5639 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, }, |
| 6899 | { 5639 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
| 6900 | { 5639 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6901 | { 5639 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6902 | { 5639 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6903 | { 5639 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6904 | { 5639 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6905 | { 5639 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, }, |
| 6906 | { 5639 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, |
| 6907 | { 5639 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 6908 | { 5642 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, |
| 6909 | { 5647 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6910 | { 5647 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6911 | { 5652 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 6912 | { 5652 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 6913 | { 5652 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 6914 | { 5657 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
| 6915 | { 5662 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6916 | { 5662 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6917 | { 5666 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6918 | { 5666 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6919 | { 5670 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6920 | { 5670 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6921 | { 5675 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
| 6922 | { 5679 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
| 6923 | { 5679 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
| 6924 | { 5685 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
| 6925 | { 5691 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, }, |
| 6926 | { 5695 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 6927 | { 5695 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 6928 | { 5700 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6929 | { 5700 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 6930 | { 5704 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6931 | { 5704 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 6932 | { 5709 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, }, |
| 6933 | { 5709 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 6934 | { 5713 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, |
| 6935 | { 5719 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6936 | { 5719 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6937 | { 5723 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6938 | { 5723 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6939 | { 5729 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 6940 | { 5734 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6941 | { 5734 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6942 | { 5734 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6943 | { 5734 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6944 | { 5739 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6945 | { 5739 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 6946 | { 5739 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6947 | { 5746 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6948 | { 5746 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6949 | { 5753 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6950 | { 5762 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6951 | { 5771 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6952 | { 5771 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6953 | { 5779 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6954 | { 5779 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6955 | { 5787 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6956 | { 5797 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6957 | { 5807 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6958 | { 5807 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6959 | { 5807 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6960 | { 5807 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6961 | { 5813 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6962 | { 5821 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6963 | { 5829 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6964 | { 5837 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6965 | { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6966 | { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6967 | { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6968 | { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6969 | { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6970 | { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6971 | { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6972 | { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 6973 | { 5895 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6974 | { 5895 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6975 | { 5901 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6976 | { 5901 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6977 | { 5907 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6978 | { 5915 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6979 | { 5923 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6980 | { 5931 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6981 | { 5939 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6982 | { 5947 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6983 | { 5955 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6984 | { 5963 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6985 | { 5971 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6986 | { 5979 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6987 | { 5987 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6988 | { 5995 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 6989 | { 6003 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6990 | { 6003 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 6991 | { 6010 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6992 | { 6010 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 6993 | { 6017 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6994 | { 6026 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6995 | { 6035 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6996 | { 6044 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 6997 | { 6053 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6998 | { 6062 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 6999 | { 6071 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7000 | { 6080 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7001 | { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7002 | { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7003 | { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7004 | { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7005 | { 6094 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7006 | { 6094 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7007 | { 6094 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7008 | { 6094 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7009 | { 6099 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 7010 | { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 7011 | { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7012 | { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7013 | { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7014 | { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7015 | { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7016 | { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7017 | { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7018 | { 6116 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 7019 | { 6116 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 7020 | { 6116 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7021 | { 6116 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7022 | { 6122 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 7023 | { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7024 | { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7025 | { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7026 | { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7027 | { 6135 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
| 7028 | { 6135 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7029 | { 6135 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7030 | { 6135 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7031 | { 6135 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7032 | { 6140 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7033 | { 6147 /* mflo */, Mips::Mflo16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
| 7034 | { 6147 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7035 | { 6147 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7036 | { 6147 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7037 | { 6147 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7038 | { 6152 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7039 | { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7040 | { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7041 | { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7042 | { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7043 | { 6172 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7044 | { 6178 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, }, |
| 7045 | { 6185 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7046 | { 6192 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7047 | { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7048 | { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7049 | { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7050 | { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7051 | { 6211 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, |
| 7052 | { 6216 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7053 | { 6216 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7054 | { 6222 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7055 | { 6222 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7056 | { 6228 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7057 | { 6236 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7058 | { 6244 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7059 | { 6252 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7060 | { 6260 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7061 | { 6268 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7062 | { 6276 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7063 | { 6284 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7064 | { 6292 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7065 | { 6300 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7066 | { 6308 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7067 | { 6316 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7068 | { 6324 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7069 | { 6324 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7070 | { 6331 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7071 | { 6331 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7072 | { 6338 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 7073 | { 6347 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 7074 | { 6356 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 7075 | { 6365 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, |
| 7076 | { 6374 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7077 | { 6383 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7078 | { 6392 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7079 | { 6401 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7080 | { 6410 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7081 | { 6410 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7082 | { 6414 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7083 | { 6422 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7084 | { 6430 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7085 | { 6438 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7086 | { 6446 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7087 | { 6454 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7088 | { 6462 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7089 | { 6470 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7090 | { 6478 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7091 | { 6478 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7092 | { 6485 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7093 | { 6485 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7094 | { 6490 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7095 | { 6490 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7096 | { 6490 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7097 | { 6490 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7098 | { 6490 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7099 | { 6496 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7100 | { 6496 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7101 | { 6496 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7102 | { 6502 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, }, |
| 7103 | { 6502 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, }, |
| 7104 | { 6502 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7105 | { 6502 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7106 | { 6502 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7107 | { 6502 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7108 | { 6502 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7109 | { 6507 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7110 | { 6514 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7111 | { 6521 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, |
| 7112 | { 6521 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, |
| 7113 | { 6527 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
| 7114 | { 6527 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
| 7115 | { 6532 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
| 7116 | { 6532 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
| 7117 | { 6532 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, |
| 7118 | { 6539 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
| 7119 | { 6539 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
| 7120 | { 6546 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7121 | { 6546 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7122 | { 6551 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 7123 | { 6551 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 7124 | { 6551 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 7125 | { 6558 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7126 | { 6558 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7127 | { 6565 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
| 7128 | { 6565 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, |
| 7129 | { 6570 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
| 7130 | { 6570 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, |
| 7131 | { 6570 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, |
| 7132 | { 6577 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
| 7133 | { 6577 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, |
| 7134 | { 6584 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7135 | { 6584 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7136 | { 6589 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 7137 | { 6589 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 7138 | { 6589 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 7139 | { 6596 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7140 | { 6596 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7141 | { 6603 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7142 | { 6603 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7143 | { 6603 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7144 | { 6603 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7145 | { 6608 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7146 | { 6608 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7147 | { 6608 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7148 | { 6615 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7149 | { 6615 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7150 | { 6622 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7151 | { 6631 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7152 | { 6640 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7153 | { 6640 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7154 | { 6648 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7155 | { 6648 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7156 | { 6656 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7157 | { 6666 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7158 | { 6676 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7159 | { 6676 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7160 | { 6676 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7161 | { 6676 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7162 | { 6682 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7163 | { 6690 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7164 | { 6698 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7165 | { 6706 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7166 | { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7167 | { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7168 | { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7169 | { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7170 | { 6719 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7171 | { 6719 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7172 | { 6719 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7173 | { 6719 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7174 | { 6719 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7175 | { 6724 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 7176 | { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 7177 | { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7178 | { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7179 | { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7180 | { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7181 | { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7182 | { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7183 | { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7184 | { 6741 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 7185 | { 6741 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 7186 | { 6741 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7187 | { 6741 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7188 | { 6747 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, |
| 7189 | { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7190 | { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7191 | { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7192 | { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7193 | { 6760 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7194 | { 6760 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7195 | { 6760 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, |
| 7196 | { 6760 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, |
| 7197 | { 6765 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7198 | { 6765 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7199 | { 6772 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7200 | { 6772 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7201 | { 6772 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, |
| 7202 | { 6772 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, |
| 7203 | { 6777 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 7204 | { 6782 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 7205 | { 6787 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 7206 | { 6792 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 7207 | { 6797 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 7208 | { 6802 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, }, |
| 7209 | { 6807 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7210 | { 6807 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7211 | { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, |
| 7212 | { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7213 | { 6820 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7214 | { 6826 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, }, |
| 7215 | { 6833 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7216 | { 6840 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7217 | { 6847 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7218 | { 6847 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7219 | { 6853 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7220 | { 6853 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, |
| 7221 | { 6859 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, |
| 7222 | { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7223 | { 6864 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7224 | { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7225 | { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7226 | { 6868 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7227 | { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7228 | { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7229 | { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7230 | { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7231 | { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7232 | { 6873 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7233 | { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7234 | { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7235 | { 6873 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7236 | { 6877 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7237 | { 6877 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7238 | { 6877 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7239 | { 6877 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7240 | { 6883 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7241 | { 6883 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7242 | { 6890 /* mul.ps */, Mips::FMUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7243 | { 6897 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7244 | { 6897 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7245 | { 6897 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7246 | { 6903 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7247 | { 6911 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7248 | { 6919 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7249 | { 6919 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7250 | { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7251 | { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7252 | { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7253 | { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7254 | { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7255 | { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7256 | { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7257 | { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7258 | { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7259 | { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7260 | { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7261 | { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7262 | { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7263 | { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7264 | { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7265 | { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7266 | { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7267 | { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7268 | { 7028 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7269 | { 7028 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7270 | { 7037 /* mulr.ps */, Mips::MULR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7271 | { 7045 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7272 | { 7054 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7273 | { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7274 | { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7275 | { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7276 | { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7277 | { 7088 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7278 | { 7088 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7279 | { 7088 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7280 | { 7088 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7281 | { 7093 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7282 | { 7093 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7283 | { 7093 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7284 | { 7093 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7285 | { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7286 | { 7099 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7287 | { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7288 | { 7104 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7289 | { 7111 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7290 | { 7118 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7291 | { 7125 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7292 | { 7132 /* nal */, Mips::BLTZAL, Convert__regZERO__imm_95_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { }, }, |
| 7293 | { 7132 /* nal */, Mips::NAL, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r6, { }, }, |
| 7294 | { 7136 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7295 | { 7136 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7296 | { 7136 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 7297 | { 7136 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7298 | { 7136 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7299 | { 7136 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7300 | { 7136 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7301 | { 7140 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7302 | { 7140 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7303 | { 7140 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7304 | { 7140 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7305 | { 7146 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7306 | { 7146 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7307 | { 7146 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7308 | { 7152 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7309 | { 7152 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7310 | { 7152 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 7311 | { 7152 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7312 | { 7152 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7313 | { 7152 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7314 | { 7157 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7315 | { 7164 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7316 | { 7171 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7317 | { 7178 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7318 | { 7185 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7319 | { 7192 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7320 | { 7199 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7321 | { 7206 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7322 | { 7213 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7323 | { 7213 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7324 | { 7213 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7325 | { 7221 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7326 | { 7221 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7327 | { 7229 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7328 | { 7229 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7329 | { 7229 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7330 | { 7237 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7331 | { 7237 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7332 | { 7245 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 7333 | { 7245 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 7334 | { 7245 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, AMFBS_InMips16Mode, { }, }, |
| 7335 | { 7245 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips, { }, }, |
| 7336 | { 7245 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, AMFBS_InMicroMips, { }, }, |
| 7337 | { 7249 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7338 | { 7249 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7339 | { 7249 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7340 | { 7249 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7341 | { 7249 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7342 | { 7249 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7343 | { 7249 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7344 | { 7253 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7345 | { 7259 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7346 | { 7266 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7347 | { 7266 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, }, |
| 7348 | { 7266 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, }, |
| 7349 | { 7266 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7350 | { 7266 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7351 | { 7266 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7352 | { 7266 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7353 | { 7270 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 7354 | { 7270 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 7355 | { 7276 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7356 | { 7276 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7357 | { 7276 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7358 | { 7276 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7359 | { 7276 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7360 | { 7276 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7361 | { 7276 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7362 | { 7276 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7363 | { 7276 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7364 | { 7276 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7365 | { 7276 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7366 | { 7276 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7367 | { 7276 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7368 | { 7276 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7369 | { 7276 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7370 | { 7279 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7371 | { 7284 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 7372 | { 7284 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 7373 | { 7289 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7374 | { 7289 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7375 | { 7289 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7376 | { 7289 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7377 | { 7289 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7378 | { 7289 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 7379 | { 7293 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7380 | { 7299 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7381 | { 7299 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7382 | { 7309 /* pause */, Mips::PAUSE, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { }, }, |
| 7383 | { 7309 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 7384 | { 7309 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 7385 | { 7315 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7386 | { 7323 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7387 | { 7331 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7388 | { 7339 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7389 | { 7347 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7390 | { 7355 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7391 | { 7363 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7392 | { 7371 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7393 | { 7379 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7394 | { 7386 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7395 | { 7393 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7396 | { 7400 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7397 | { 7407 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7398 | { 7407 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7399 | { 7415 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7400 | { 7415 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7401 | { 7423 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7402 | { 7430 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7403 | { 7437 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR32AsmReg }, }, |
| 7404 | { 7437 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7405 | { 7441 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7406 | { 7441 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7407 | { 7454 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7408 | { 7454 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7409 | { 7467 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7410 | { 7467 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7411 | { 7482 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7412 | { 7482 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7413 | { 7498 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7414 | { 7498 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7415 | { 7513 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7416 | { 7513 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7417 | { 7529 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7418 | { 7529 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7419 | { 7543 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7420 | { 7543 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7421 | { 7558 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7422 | { 7558 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7423 | { 7572 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7424 | { 7572 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7425 | { 7587 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7426 | { 7587 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7427 | { 7599 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7428 | { 7599 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7429 | { 7614 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7430 | { 7614 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7431 | { 7631 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7432 | { 7631 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7433 | { 7643 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7434 | { 7643 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7435 | { 7656 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7436 | { 7656 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7437 | { 7671 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7438 | { 7671 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7439 | { 7687 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, |
| 7440 | { 7687 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
| 7441 | { 7687 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
| 7442 | { 7687 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, |
| 7443 | { 7692 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, |
| 7444 | { 7692 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, }, |
| 7445 | { 7698 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7446 | { 7704 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7447 | { 7704 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7448 | { 7712 /* pul.ps */, Mips::PUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7449 | { 7719 /* puu.ps */, Mips::PUU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7450 | { 7726 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7451 | { 7726 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7452 | { 7737 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, |
| 7453 | { 7737 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 7454 | { 7743 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, |
| 7455 | { 7743 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, |
| 7456 | { 7743 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, |
| 7457 | { 7743 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, }, |
| 7458 | { 7743 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, }, |
| 7459 | { 7743 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, |
| 7460 | { 7743 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, |
| 7461 | { 7749 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7462 | { 7756 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7463 | { 7756 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7464 | { 7756 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7465 | { 7756 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7466 | { 7764 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7467 | { 7764 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7468 | { 7772 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7469 | { 7772 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7470 | { 7772 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7471 | { 7772 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7472 | { 7776 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7473 | { 7776 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7474 | { 7776 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7475 | { 7776 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7476 | { 7781 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, |
| 7477 | { 7781 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, |
| 7478 | { 7789 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7479 | { 7789 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7480 | { 7797 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7481 | { 7797 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7482 | { 7806 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7483 | { 7806 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7484 | { 7815 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7485 | { 7815 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7486 | { 7822 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7487 | { 7822 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7488 | { 7829 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7489 | { 7829 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7490 | { 7829 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7491 | { 7829 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7492 | { 7833 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7493 | { 7833 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7494 | { 7833 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7495 | { 7833 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7496 | { 7837 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7497 | { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7498 | { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7499 | { 7837 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7500 | { 7837 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7501 | { 7842 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7502 | { 7842 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7503 | { 7848 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7504 | { 7848 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7505 | { 7858 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 7506 | { 7858 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 7507 | { 7868 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 7508 | { 7868 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 7509 | { 7868 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 7510 | { 7868 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7511 | { 7878 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7512 | { 7878 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7513 | { 7878 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7514 | { 7888 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7515 | { 7888 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7516 | { 7888 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7517 | { 7888 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7518 | { 7896 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7519 | { 7896 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7520 | { 7904 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7521 | { 7904 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7522 | { 7904 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7523 | { 7904 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7524 | { 7908 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7525 | { 7912 /* saa */, Mips::SaaAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 7526 | { 7912 /* saa */, Mips::SAA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, }, |
| 7527 | { 7916 /* saad */, Mips::SaadAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 7528 | { 7916 /* saad */, Mips::SAAD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, }, |
| 7529 | { 7921 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7530 | { 7929 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7531 | { 7937 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7532 | { 7945 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7533 | { 7953 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7534 | { 7961 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7535 | { 7969 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7536 | { 7977 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7537 | { 7985 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7538 | { 7985 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7539 | { 7985 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7540 | { 7985 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, |
| 7541 | { 7988 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
| 7542 | { 7988 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
| 7543 | { 7993 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7544 | { 7993 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7545 | { 7997 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 7546 | { 7997 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 7547 | { 7997 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7548 | { 7997 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7549 | { 7997 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7550 | { 7997 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7551 | { 8000 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 7552 | { 8000 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 7553 | { 8004 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7554 | { 8004 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7555 | { 8008 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7556 | { 8008 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, |
| 7557 | { 8011 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, { }, }, |
| 7558 | { 8011 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, }, |
| 7559 | { 8011 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 7560 | { 8011 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
| 7561 | { 8011 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, |
| 7562 | { 8011 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, |
| 7563 | { 8011 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, }, |
| 7564 | { 8017 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, }, |
| 7565 | { 8017 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, }, |
| 7566 | { 8025 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7567 | { 8025 /* sdc1 */, Mips::SDC1_MM_D32, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7568 | { 8025 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7569 | { 8025 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7570 | { 8025 /* sdc1 */, Mips::SDC1_MM_D64, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7571 | { 8030 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 7572 | { 8030 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 7573 | { 8030 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7574 | { 8035 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
| 7575 | { 8040 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 7576 | { 8044 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, |
| 7577 | { 8048 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7578 | { 8048 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7579 | { 8054 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
| 7580 | { 8054 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7581 | { 8054 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
| 7582 | { 8054 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7583 | { 8054 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7584 | { 8058 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, }, |
| 7585 | { 8058 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 7586 | { 8058 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, }, |
| 7587 | { 8058 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7588 | { 8058 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7589 | { 8062 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7590 | { 8062 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7591 | { 8068 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7592 | { 8068 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7593 | { 8074 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7594 | { 8074 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7595 | { 8074 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7596 | { 8081 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7597 | { 8081 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7598 | { 8090 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7599 | { 8090 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7600 | { 8099 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7601 | { 8099 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7602 | { 8099 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7603 | { 8106 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7604 | { 8106 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7605 | { 8115 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7606 | { 8115 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7607 | { 8124 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7608 | { 8124 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7609 | { 8124 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7610 | { 8124 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7611 | { 8124 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7612 | { 8124 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7613 | { 8128 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
| 7614 | { 8128 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
| 7615 | { 8133 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7616 | { 8133 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7617 | { 8133 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7618 | { 8133 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7619 | { 8133 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7620 | { 8133 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7621 | { 8137 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7622 | { 8137 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 7623 | { 8137 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7624 | { 8137 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7625 | { 8137 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 7626 | { 8137 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7627 | { 8142 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7628 | { 8142 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7629 | { 8142 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7630 | { 8142 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7631 | { 8142 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7632 | { 8142 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7633 | { 8142 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7634 | { 8142 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7635 | { 8146 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7636 | { 8146 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7637 | { 8146 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 7638 | { 8146 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7639 | { 8146 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7640 | { 8146 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7641 | { 8146 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 7642 | { 8146 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7643 | { 8151 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7644 | { 8151 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7645 | { 8151 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7646 | { 8151 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, |
| 7647 | { 8154 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
| 7648 | { 8154 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
| 7649 | { 8159 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7650 | { 8159 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7651 | { 8163 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7652 | { 8169 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7653 | { 8175 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 7654 | { 8181 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, |
| 7655 | { 8181 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, |
| 7656 | { 8187 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 7657 | { 8187 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, |
| 7658 | { 8194 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7659 | { 8194 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7660 | { 8202 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7661 | { 8202 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7662 | { 8210 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7663 | { 8210 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7664 | { 8220 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7665 | { 8220 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7666 | { 8229 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7667 | { 8229 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7668 | { 8238 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7669 | { 8238 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7670 | { 8247 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7671 | { 8247 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7672 | { 8258 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7673 | { 8258 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7674 | { 8268 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7675 | { 8268 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7676 | { 8276 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7677 | { 8276 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7678 | { 8284 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7679 | { 8284 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7680 | { 8294 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7681 | { 8294 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7682 | { 8304 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7683 | { 8304 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7684 | { 8313 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7685 | { 8313 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7686 | { 8322 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7687 | { 8322 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7688 | { 8331 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7689 | { 8331 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7690 | { 8342 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7691 | { 8342 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7692 | { 8353 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7693 | { 8353 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7694 | { 8363 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7695 | { 8363 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7696 | { 8371 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7697 | { 8371 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7698 | { 8379 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7699 | { 8379 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7700 | { 8388 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7701 | { 8388 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7702 | { 8397 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { }, }, |
| 7703 | { 8397 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 7704 | { 8397 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, }, |
| 7705 | { 8397 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, }, |
| 7706 | { 8404 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7707 | { 8410 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7708 | { 8416 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7709 | { 8422 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7710 | { 8428 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
| 7711 | { 8435 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, |
| 7712 | { 8442 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
| 7713 | { 8449 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
| 7714 | { 8456 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7715 | { 8456 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7716 | { 8456 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7717 | { 8456 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7718 | { 8456 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7719 | { 8456 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7720 | { 8460 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7721 | { 8460 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 7722 | { 8460 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7723 | { 8460 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7724 | { 8460 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, |
| 7725 | { 8460 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7726 | { 8465 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7727 | { 8465 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7728 | { 8465 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7729 | { 8465 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7730 | { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7731 | { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7732 | { 8465 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, |
| 7733 | { 8465 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7734 | { 8465 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7735 | { 8465 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7736 | { 8465 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7737 | { 8465 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7738 | { 8469 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7739 | { 8475 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7740 | { 8481 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7741 | { 8487 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7742 | { 8493 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 7743 | { 8493 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 7744 | { 8499 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7745 | { 8506 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7746 | { 8513 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7747 | { 8520 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7748 | { 8527 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7749 | { 8527 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7750 | { 8527 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7751 | { 8532 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7752 | { 8532 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7753 | { 8532 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7754 | { 8532 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7755 | { 8532 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7756 | { 8532 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7757 | { 8532 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7758 | { 8532 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7759 | { 8532 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7760 | { 8536 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
| 7761 | { 8536 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7762 | { 8536 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7763 | { 8536 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 7764 | { 8541 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, |
| 7765 | { 8541 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7766 | { 8541 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 7767 | { 8541 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, }, |
| 7768 | { 8547 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7769 | { 8547 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7770 | { 8547 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7771 | { 8547 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7772 | { 8547 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7773 | { 8547 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7774 | { 8547 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7775 | { 8547 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7776 | { 8547 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 7777 | { 8552 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7778 | { 8552 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, |
| 7779 | { 8552 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7780 | { 8552 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7781 | { 8552 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 7782 | { 8552 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 7783 | { 8556 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
| 7784 | { 8556 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, |
| 7785 | { 8561 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7786 | { 8569 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7787 | { 8577 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7788 | { 8585 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, |
| 7789 | { 8593 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, |
| 7790 | { 8602 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, |
| 7791 | { 8611 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, |
| 7792 | { 8620 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, |
| 7793 | { 8629 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7794 | { 8629 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7795 | { 8629 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7796 | { 8629 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7797 | { 8636 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7798 | { 8636 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7799 | { 8643 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7800 | { 8643 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7801 | { 8643 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7802 | { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7803 | { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7804 | { 8643 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, |
| 7805 | { 8643 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7806 | { 8643 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7807 | { 8643 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7808 | { 8643 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7809 | { 8647 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7810 | { 8653 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7811 | { 8659 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7812 | { 8665 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7813 | { 8671 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7814 | { 8678 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7815 | { 8685 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7816 | { 8692 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7817 | { 8699 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7818 | { 8706 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7819 | { 8713 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7820 | { 8720 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7821 | { 8727 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7822 | { 8735 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7823 | { 8743 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7824 | { 8751 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7825 | { 8759 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7826 | { 8759 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7827 | { 8759 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7828 | { 8764 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7829 | { 8764 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7830 | { 8764 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7831 | { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7832 | { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7833 | { 8764 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, |
| 7834 | { 8764 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7835 | { 8764 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7836 | { 8764 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7837 | { 8764 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7838 | { 8768 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7839 | { 8774 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7840 | { 8780 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7841 | { 8786 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7842 | { 8792 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 7843 | { 8792 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, |
| 7844 | { 8798 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7845 | { 8805 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7846 | { 8812 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7847 | { 8819 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7848 | { 8826 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7849 | { 8833 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7850 | { 8840 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7851 | { 8847 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7852 | { 8854 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, |
| 7853 | { 8862 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, |
| 7854 | { 8870 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, |
| 7855 | { 8878 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7856 | { 8886 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7857 | { 8886 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7858 | { 8886 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7859 | { 8891 /* ssnop */, Mips::SSNOP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 7860 | { 8891 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 7861 | { 8891 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 7862 | { 8897 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, }, |
| 7863 | { 8902 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, |
| 7864 | { 8907 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, |
| 7865 | { 8912 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, |
| 7866 | { 8917 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7867 | { 8917 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7868 | { 8917 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7869 | { 8917 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, }, |
| 7870 | { 8917 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7871 | { 8917 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7872 | { 8917 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7873 | { 8917 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, |
| 7874 | { 8921 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7875 | { 8921 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, |
| 7876 | { 8921 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7877 | { 8921 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7878 | { 8927 /* sub.ps */, Mips::FSUB_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 7879 | { 8934 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7880 | { 8934 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7881 | { 8934 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 7882 | { 8940 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7883 | { 8940 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7884 | { 8948 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7885 | { 8948 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7886 | { 8958 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7887 | { 8958 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7888 | { 8967 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7889 | { 8967 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7890 | { 8976 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7891 | { 8976 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7892 | { 8984 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7893 | { 8984 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7894 | { 8995 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7895 | { 8995 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7896 | { 9005 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7897 | { 9014 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7898 | { 9023 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7899 | { 9032 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7900 | { 9041 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7901 | { 9050 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7902 | { 9059 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7903 | { 9068 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7904 | { 9077 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7905 | { 9088 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7906 | { 9099 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7907 | { 9110 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7908 | { 9121 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7909 | { 9132 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7910 | { 9143 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7911 | { 9154 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7912 | { 9165 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7913 | { 9165 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7914 | { 9165 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7915 | { 9165 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, }, |
| 7916 | { 9165 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 7917 | { 9165 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7918 | { 9165 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7919 | { 9165 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7920 | { 9165 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, |
| 7921 | { 9170 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7922 | { 9170 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7923 | { 9178 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7924 | { 9178 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7925 | { 9186 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 7926 | { 9186 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 7927 | { 9193 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7928 | { 9193 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7929 | { 9203 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7930 | { 9203 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7931 | { 9213 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7932 | { 9213 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7933 | { 9222 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7934 | { 9222 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7935 | { 9233 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7936 | { 9240 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7937 | { 9247 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7938 | { 9254 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 7939 | { 9261 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7940 | { 9269 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7941 | { 9277 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7942 | { 9285 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, |
| 7943 | { 9293 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7944 | { 9293 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7945 | { 9293 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7946 | { 9299 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
| 7947 | { 9299 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
| 7948 | { 9299 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7949 | { 9299 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7950 | { 9299 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7951 | { 9299 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7952 | { 9299 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7953 | { 9299 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, |
| 7954 | { 9299 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, |
| 7955 | { 9302 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
| 7956 | { 9302 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, |
| 7957 | { 9307 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7958 | { 9307 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7959 | { 9312 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 7960 | { 9312 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, }, |
| 7961 | { 9312 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, }, |
| 7962 | { 9317 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, |
| 7963 | { 9322 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7964 | { 9322 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7965 | { 9326 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7966 | { 9326 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7967 | { 9330 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7968 | { 9330 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7969 | { 9335 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
| 7970 | { 9339 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
| 7971 | { 9339 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, |
| 7972 | { 9345 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, }, |
| 7973 | { 9351 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, }, |
| 7974 | { 9355 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7975 | { 9355 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 7976 | { 9359 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7977 | { 9359 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, }, |
| 7978 | { 9364 /* swsp */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, |
| 7979 | { 9369 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7980 | { 9369 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, |
| 7981 | { 9375 /* sync */, Mips::SYNC, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { }, }, |
| 7982 | { 9375 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 7983 | { 9375 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, |
| 7984 | { 9375 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_ConstantUImm5_0 }, }, |
| 7985 | { 9375 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, }, |
| 7986 | { 9375 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, }, |
| 7987 | { 9380 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm16_02_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_MemOffsetSimm16_0 }, }, |
| 7988 | { 9380 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_NotMips32r6, { MCK_MemOffsetSimm16_0 }, }, |
| 7989 | { 9380 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16_0 }, }, |
| 7990 | { 9386 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, AMFBS_HasMips64_HasCnMips, { }, }, |
| 7991 | { 9397 /* syncs */, Mips::SYNC, Convert__imm_95_6, AMFBS_HasMips64_HasCnMips, { }, }, |
| 7992 | { 9403 /* syncw */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasMips64_HasCnMips, { }, }, |
| 7993 | { 9409 /* syncws */, Mips::SYNC, Convert__imm_95_5, AMFBS_HasMips64_HasCnMips, { }, }, |
| 7994 | { 9416 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 7995 | { 9416 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, |
| 7996 | { 9416 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
| 7997 | { 9416 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, |
| 7998 | { 9424 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 7999 | { 9424 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8000 | { 9424 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 8001 | { 9424 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8002 | { 9428 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8003 | { 9428 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8004 | { 9433 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8005 | { 9433 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8006 | { 9433 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 8007 | { 9433 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8008 | { 9437 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8009 | { 9437 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8010 | { 9442 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8011 | { 9442 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8012 | { 9448 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8013 | { 9448 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8014 | { 9448 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 8015 | { 9448 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8016 | { 9453 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 8017 | { 9453 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 8018 | { 9461 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 8019 | { 9461 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 8020 | { 9470 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 8021 | { 9470 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 8022 | { 9476 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 8023 | { 9476 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 8024 | { 9482 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 8025 | { 9482 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 8026 | { 9489 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { }, }, |
| 8027 | { 9489 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, { }, }, |
| 8028 | { 9496 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, |
| 8029 | { 9496 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 8030 | { 9503 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { }, }, |
| 8031 | { 9503 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, { }, }, |
| 8032 | { 9511 /* tlbp */, Mips::TLBP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 8033 | { 9511 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 8034 | { 9516 /* tlbr */, Mips::TLBR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 8035 | { 9516 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 8036 | { 9521 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 8037 | { 9521 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 8038 | { 9527 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, { }, }, |
| 8039 | { 9527 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, { }, }, |
| 8040 | { 9533 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8041 | { 9533 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8042 | { 9533 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 8043 | { 9533 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8044 | { 9537 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8045 | { 9537 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8046 | { 9542 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8047 | { 9542 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8048 | { 9548 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8049 | { 9548 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8050 | { 9548 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 8051 | { 9548 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8052 | { 9553 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8053 | { 9553 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8054 | { 9553 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, |
| 8055 | { 9553 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8056 | { 9557 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8057 | { 9557 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, |
| 8058 | { 9562 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 8059 | { 9562 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, |
| 8060 | { 9572 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 8061 | { 9572 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, |
| 8062 | { 9582 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 8063 | { 9582 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, |
| 8064 | { 9582 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 8065 | { 9582 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, |
| 8066 | { 9582 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 8067 | { 9582 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, |
| 8068 | { 9592 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 8069 | { 9592 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 8070 | { 9592 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, |
| 8071 | { 9592 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8072 | { 9602 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 8073 | { 9606 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 8074 | { 9611 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 8075 | { 9615 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 8076 | { 9619 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, }, |
| 8077 | { 9623 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 8078 | { 9623 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 8079 | { 9630 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 8080 | { 9630 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 8081 | { 9635 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 8082 | { 9635 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, |
| 8083 | { 9641 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 8084 | { 9648 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 8085 | { 9655 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 8086 | { 9662 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 8087 | { 9669 /* wait */, Mips::WAIT, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, { }, }, |
| 8088 | { 9669 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, { }, }, |
| 8089 | { 9669 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, }, |
| 8090 | { 9669 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, }, |
| 8091 | { 9674 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 8092 | { 9674 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_InMicroMips, { MCK_GPR32AsmReg }, }, |
| 8093 | { 9674 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, |
| 8094 | { 9674 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, |
| 8095 | { 9680 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8096 | { 9687 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8097 | { 9687 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8098 | { 9687 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8099 | { 9692 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, |
| 8100 | { 9692 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8101 | { 9692 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8102 | { 9692 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8103 | { 9692 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8104 | { 9692 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 8105 | { 9692 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 8106 | { 9692 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, |
| 8107 | { 9692 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8108 | { 9692 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8109 | { 9692 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8110 | { 9692 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8111 | { 9692 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 8112 | { 9692 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, |
| 8113 | { 9692 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, |
| 8114 | { 9696 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, |
| 8115 | { 9702 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 8116 | { 9702 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, |
| 8117 | { 9708 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8118 | { 9708 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8119 | { 9708 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8120 | { 9708 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8121 | { 9708 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8122 | { 9708 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, |
| 8123 | { 9713 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, |
| 8124 | { 9720 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, }, |
| 8125 | { 9720 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, |
| 8126 | }; |
| 8127 | |
| 8128 | #include "llvm/Support/Debug.h" |
| 8129 | #include "llvm/Support/Format.h" |
| 8130 | |
| 8131 | unsigned MipsAsmParser:: |
| 8132 | MatchInstructionImpl(const OperandVector &Operands, |
| 8133 | MCInst &Inst, |
| 8134 | uint64_t &ErrorInfo, |
| 8135 | FeatureBitset &MissingFeatures, |
| 8136 | bool matchingInlineAsm, unsigned VariantID) { |
| 8137 | // Eliminate obvious mismatches. |
| 8138 | if (Operands.size() > 9) { |
| 8139 | ErrorInfo = 9; |
| 8140 | return Match_InvalidOperand; |
| 8141 | } |
| 8142 | |
| 8143 | // Get the current feature set. |
| 8144 | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); |
| 8145 | |
| 8146 | // Get the instruction mnemonic, which is the first token. |
| 8147 | StringRef Mnemonic = ((MipsOperand &)*Operands[0]).getToken(); |
| 8148 | |
| 8149 | // Some state to try to produce better error messages. |
| 8150 | bool HadMatchOtherThanFeatures = false; |
| 8151 | bool HadMatchOtherThanPredicate = false; |
| 8152 | unsigned RetCode = Match_InvalidOperand; |
| 8153 | MissingFeatures.set(); |
| 8154 | // Set ErrorInfo to the operand that mismatches if it is |
| 8155 | // wrong for all instances of the instruction. |
| 8156 | ErrorInfo = ~0ULL; |
| 8157 | // Find the appropriate table for this asm variant. |
| 8158 | const MatchEntry *Start, *End; |
| 8159 | switch (VariantID) { |
| 8160 | default: llvm_unreachable("invalid variant!"); |
| 8161 | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
| 8162 | } |
| 8163 | // Search the table. |
| 8164 | auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); |
| 8165 | |
| 8166 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found "<< |
| 8167 | std::distance(MnemonicRange.first, MnemonicRange.second) << |
| 8168 | " encodings with mnemonic '"<< Mnemonic << "'\n"); |
| 8169 | |
| 8170 | // Return a more specific error code if no mnemonics match. |
| 8171 | if (MnemonicRange.first == MnemonicRange.second) |
| 8172 | return Match_MnemonicFail; |
| 8173 | |
| 8174 | for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; |
| 8175 | it != ie; ++it) { |
| 8176 | const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; |
| 8177 | bool HasRequiredFeatures = |
| 8178 | (AvailableFeatures & RequiredFeatures) == RequiredFeatures; |
| 8179 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " |
| 8180 | << MII.getName(it->Opcode) << "\n"); |
| 8181 | // equal_range guarantees that instruction mnemonic matches. |
| 8182 | assert(Mnemonic == it->getMnemonic()); |
| 8183 | bool OperandsValid = true; |
| 8184 | for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) { |
| 8185 | auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); |
| 8186 | DEBUG_WITH_TYPE("asm-matcher", |
| 8187 | dbgs() << " Matching formal operand class "<< getMatchClassName(Formal) |
| 8188 | << " against actual operand at index "<< ActualIdx); |
| 8189 | if (ActualIdx < Operands.size()) |
| 8190 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; |
| 8191 | Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); |
| 8192 | else |
| 8193 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); |
| 8194 | if (ActualIdx >= Operands.size()) { |
| 8195 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n"); |
| 8196 | if (Formal == InvalidMatchClass) { |
| 8197 | break; |
| 8198 | } |
| 8199 | if (isSubclass(Formal, OptionalMatchClass)) { |
| 8200 | continue; |
| 8201 | } |
| 8202 | OperandsValid = false; |
| 8203 | ErrorInfo = ActualIdx; |
| 8204 | break; |
| 8205 | } |
| 8206 | MCParsedAsmOperand &Actual = *Operands[ActualIdx]; |
| 8207 | unsigned Diag = validateOperandClass(Actual, Formal); |
| 8208 | if (Diag == Match_Success) { |
| 8209 | DEBUG_WITH_TYPE("asm-matcher", |
| 8210 | dbgs() << "match success using generic matcher\n"); |
| 8211 | ++ActualIdx; |
| 8212 | continue; |
| 8213 | } |
| 8214 | // If the generic handler indicates an invalid operand |
| 8215 | // failure, check for a special case. |
| 8216 | if (Diag != Match_Success) { |
| 8217 | unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); |
| 8218 | if (TargetDiag == Match_Success) { |
| 8219 | DEBUG_WITH_TYPE("asm-matcher", |
| 8220 | dbgs() << "match success using target matcher\n"); |
| 8221 | ++ActualIdx; |
| 8222 | continue; |
| 8223 | } |
| 8224 | // If the target matcher returned a specific error code use |
| 8225 | // that, else use the one from the generic matcher. |
| 8226 | if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) |
| 8227 | Diag = TargetDiag; |
| 8228 | } |
| 8229 | // If current formal operand wasn't matched and it is optional |
| 8230 | // then try to match next formal operand |
| 8231 | if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { |
| 8232 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); |
| 8233 | continue; |
| 8234 | } |
| 8235 | // If this operand is broken for all of the instances of this |
| 8236 | // mnemonic, keep track of it so we can report loc info. |
| 8237 | // If we already had a match that only failed due to a |
| 8238 | // target predicate, that diagnostic is preferred. |
| 8239 | if (!HadMatchOtherThanPredicate && |
| 8240 | (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { |
| 8241 | if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand)) |
| 8242 | RetCode = Diag; |
| 8243 | ErrorInfo = ActualIdx; |
| 8244 | } |
| 8245 | // Otherwise, just reject this instance of the mnemonic. |
| 8246 | OperandsValid = false; |
| 8247 | break; |
| 8248 | } |
| 8249 | |
| 8250 | if (!OperandsValid) { |
| 8251 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " |
| 8252 | "operand mismatches, ignoring " |
| 8253 | "this opcode\n"); |
| 8254 | continue; |
| 8255 | } |
| 8256 | if (!HasRequiredFeatures) { |
| 8257 | HadMatchOtherThanFeatures = true; |
| 8258 | FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; |
| 8259 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; |
| 8260 | for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) |
| 8261 | if (NewMissingFeatures[I]) |
| 8262 | dbgs() << ' ' << I; |
| 8263 | dbgs() << "\n"); |
| 8264 | if (NewMissingFeatures.count() <= |
| 8265 | MissingFeatures.count()) |
| 8266 | MissingFeatures = NewMissingFeatures; |
| 8267 | continue; |
| 8268 | } |
| 8269 | |
| 8270 | Inst.clear(); |
| 8271 | |
| 8272 | Inst.setOpcode(it->Opcode); |
| 8273 | // We have a potential match but have not rendered the operands. |
| 8274 | // Check the target predicate to handle any context sensitive |
| 8275 | // constraints. |
| 8276 | // For example, Ties that are referenced multiple times must be |
| 8277 | // checked here to ensure the input is the same for each match |
| 8278 | // constraints. If we leave it any later the ties will have been |
| 8279 | // canonicalized |
| 8280 | unsigned MatchResult; |
| 8281 | if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { |
| 8282 | Inst.clear(); |
| 8283 | DEBUG_WITH_TYPE( |
| 8284 | "asm-matcher", |
| 8285 | dbgs() << "Early target match predicate failed with diag code " |
| 8286 | << MatchResult << "\n"); |
| 8287 | RetCode = MatchResult; |
| 8288 | HadMatchOtherThanPredicate = true; |
| 8289 | continue; |
| 8290 | } |
| 8291 | |
| 8292 | if (matchingInlineAsm) { |
| 8293 | convertToMapAndConstraints(it->ConvertFn, Operands); |
| 8294 | if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, |
| 8295 | ErrorInfo)) |
| 8296 | return Match_InvalidTiedOperand; |
| 8297 | |
| 8298 | return Match_Success; |
| 8299 | } |
| 8300 | |
| 8301 | // We have selected a definite instruction, convert the parsed |
| 8302 | // operands into the appropriate MCInst. |
| 8303 | convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); |
| 8304 | |
| 8305 | // We have a potential match. Check the target predicate to |
| 8306 | // handle any context sensitive constraints. |
| 8307 | if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { |
| 8308 | DEBUG_WITH_TYPE("asm-matcher", |
| 8309 | dbgs() << "Target match predicate failed with diag code " |
| 8310 | << MatchResult << "\n"); |
| 8311 | Inst.clear(); |
| 8312 | RetCode = MatchResult; |
| 8313 | HadMatchOtherThanPredicate = true; |
| 8314 | continue; |
| 8315 | } |
| 8316 | |
| 8317 | if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, |
| 8318 | ErrorInfo)) |
| 8319 | return Match_InvalidTiedOperand; |
| 8320 | |
| 8321 | DEBUG_WITH_TYPE( |
| 8322 | "asm-matcher", |
| 8323 | dbgs() << "Opcode result: complete match, selecting this opcode\n"); |
| 8324 | return Match_Success; |
| 8325 | } |
| 8326 | |
| 8327 | // Okay, we had no match. Try to return a useful error code. |
| 8328 | if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) |
| 8329 | return RetCode; |
| 8330 | |
| 8331 | ErrorInfo = 0; |
| 8332 | return Match_MissingFeature; |
| 8333 | } |
| 8334 | |
| 8335 | namespace { |
| 8336 | struct OperandMatchEntry { |
| 8337 | uint16_t Mnemonic; |
| 8338 | uint8_t OperandMask; |
| 8339 | uint8_t Class; |
| 8340 | uint8_t RequiredFeaturesIdx; |
| 8341 | |
| 8342 | StringRef getMnemonic() const { |
| 8343 | return StringRef(MnemonicTable + Mnemonic + 1, |
| 8344 | MnemonicTable[Mnemonic]); |
| 8345 | } |
| 8346 | }; |
| 8347 | |
| 8348 | // Predicate for searching for an opcode. |
| 8349 | struct LessOpcodeOperand { |
| 8350 | bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { |
| 8351 | return LHS.getMnemonic() < RHS; |
| 8352 | } |
| 8353 | bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { |
| 8354 | return LHS < RHS.getMnemonic(); |
| 8355 | } |
| 8356 | bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { |
| 8357 | return LHS.getMnemonic() < RHS.getMnemonic(); |
| 8358 | } |
| 8359 | }; |
| 8360 | } // end anonymous namespace |
| 8361 | |
| 8362 | static const OperandMatchEntry OperandMatchTable[3313] = { |
| 8363 | /* Operand List Mnemonic, Mask, Operand Class, Features */ |
| 8364 | { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8365 | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 8366 | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 8367 | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 8368 | { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 8369 | { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 8370 | { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 8371 | { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8372 | { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8373 | { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8374 | { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8375 | { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8376 | { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8377 | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8378 | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8379 | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8380 | { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8381 | { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8382 | { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8383 | { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8384 | { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8385 | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8386 | { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8387 | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 8388 | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 8389 | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 8390 | { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 8391 | { 55 /* add.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8392 | { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 8393 | { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 8394 | { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 8395 | { 68 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8396 | { 76 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8397 | { 84 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8398 | { 92 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8399 | { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8400 | { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8401 | { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8402 | { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8403 | { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8404 | { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8405 | { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8406 | { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8407 | { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8408 | { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8409 | { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8410 | { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8411 | { 111 /* addiupc */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8412 | { 119 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
| 8413 | { 129 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
| 8414 | { 137 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8415 | { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8416 | { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8417 | { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8418 | { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8419 | { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8420 | { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8421 | { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8422 | { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8423 | { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8424 | { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8425 | { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8426 | { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8427 | { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8428 | { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8429 | { 218 /* addr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D }, |
| 8430 | { 226 /* adds_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8431 | { 235 /* adds_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8432 | { 244 /* adds_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8433 | { 253 /* adds_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8434 | { 262 /* adds_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8435 | { 271 /* adds_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8436 | { 280 /* adds_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8437 | { 289 /* adds_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8438 | { 298 /* adds_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8439 | { 307 /* adds_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8440 | { 316 /* adds_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8441 | { 325 /* adds_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8442 | { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8443 | { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8444 | { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8445 | { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8446 | { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8447 | { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8448 | { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8449 | { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8450 | { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8451 | { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8452 | { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8453 | { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8454 | { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8455 | { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8456 | { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8457 | { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8458 | { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8459 | { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8460 | { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8461 | { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8462 | { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8463 | { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8464 | { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8465 | { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8466 | { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8467 | { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8468 | { 408 /* addv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8469 | { 415 /* addv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8470 | { 422 /* addv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8471 | { 429 /* addv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8472 | { 436 /* addvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8473 | { 444 /* addvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8474 | { 452 /* addvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8475 | { 460 /* addvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8476 | { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8477 | { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8478 | { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8479 | { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8480 | { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8481 | { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8482 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8483 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8484 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8485 | { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8486 | { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 8487 | { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8488 | { 487 /* and */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
| 8489 | { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8490 | { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8491 | { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8492 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8493 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 8494 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8495 | { 487 /* and */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
| 8496 | { 491 /* and.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8497 | { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8498 | { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8499 | { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8500 | { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8501 | { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8502 | { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8503 | { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8504 | { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8505 | { 508 /* andi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8506 | { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8507 | { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8508 | { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8509 | { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8510 | { 529 /* asub_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8511 | { 538 /* asub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8512 | { 547 /* asub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8513 | { 556 /* asub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8514 | { 565 /* asub_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8515 | { 574 /* asub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8516 | { 583 /* asub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8517 | { 592 /* asub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8518 | { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8519 | { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8520 | { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8521 | { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8522 | { 611 /* ave_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8523 | { 619 /* ave_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8524 | { 627 /* ave_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8525 | { 635 /* ave_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8526 | { 643 /* ave_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8527 | { 651 /* ave_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8528 | { 659 /* ave_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8529 | { 667 /* ave_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8530 | { 675 /* aver_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8531 | { 684 /* aver_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8532 | { 693 /* aver_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8533 | { 702 /* aver_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8534 | { 711 /* aver_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8535 | { 720 /* aver_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8536 | { 729 /* aver_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8537 | { 738 /* aver_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8538 | { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8539 | { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
| 8540 | { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
| 8541 | { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None }, |
| 8542 | { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
| 8543 | { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8544 | { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
| 8545 | { 753 /* baddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8546 | { 753 /* baddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8547 | { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8548 | { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8549 | { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8550 | { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8551 | { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8552 | { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 8553 | { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 8554 | { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8555 | { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
| 8556 | { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8557 | { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
| 8558 | { 781 /* bbit032 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8559 | { 781 /* bbit032 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
| 8560 | { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8561 | { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
| 8562 | { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8563 | { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
| 8564 | { 795 /* bbit132 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 8565 | { 795 /* bbit132 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips }, |
| 8566 | { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8567 | { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8568 | { 806 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8569 | { 811 /* bc1eqz */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 8570 | { 811 /* bc1eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 8571 | { 818 /* bc1eqzc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 8572 | { 818 /* bc1eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 8573 | { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8574 | { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8575 | { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8576 | { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8577 | { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8578 | { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8579 | { 831 /* bc1fl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8580 | { 831 /* bc1fl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8581 | { 831 /* bc1fl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8582 | { 837 /* bc1nez */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 8583 | { 837 /* bc1nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 8584 | { 844 /* bc1nezc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 8585 | { 844 /* bc1nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 8586 | { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8587 | { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8588 | { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8589 | { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8590 | { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8591 | { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8592 | { 857 /* bc1tl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8593 | { 857 /* bc1tl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8594 | { 857 /* bc1tl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8595 | { 863 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8596 | { 863 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8597 | { 870 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8598 | { 870 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8599 | { 878 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8600 | { 878 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8601 | { 885 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8602 | { 885 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8603 | { 893 /* bclr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8604 | { 900 /* bclr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8605 | { 907 /* bclr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8606 | { 914 /* bclr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8607 | { 921 /* bclri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8608 | { 929 /* bclri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8609 | { 937 /* bclri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8610 | { 945 /* bclri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8611 | { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8612 | { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8613 | { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8614 | { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8615 | { 953 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8616 | { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8617 | { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8618 | { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8619 | { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8620 | { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8621 | { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8622 | { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8623 | { 962 /* beql */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8624 | { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8625 | { 962 /* beql */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8626 | { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8627 | { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
| 8628 | { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8629 | { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8630 | { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8631 | { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
| 8632 | { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
| 8633 | { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8634 | { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8635 | { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8636 | { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8637 | { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8638 | { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8639 | { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8640 | { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8641 | { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8642 | { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8643 | { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8644 | { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8645 | { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8646 | { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8647 | { 987 /* beqzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8648 | { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8649 | { 993 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8650 | { 993 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8651 | { 1001 /* beqzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 8652 | { 1001 /* beqzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 8653 | { 1007 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8654 | { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8655 | { 1007 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8656 | { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8657 | { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8658 | { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8659 | { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8660 | { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8661 | { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8662 | { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8663 | { 1016 /* bgel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8664 | { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8665 | { 1016 /* bgel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8666 | { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8667 | { 1021 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8668 | { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8669 | { 1021 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8670 | { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8671 | { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8672 | { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8673 | { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8674 | { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8675 | { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8676 | { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8677 | { 1032 /* bgeul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8678 | { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8679 | { 1032 /* bgeul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8680 | { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8681 | { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8682 | { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8683 | { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8684 | { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8685 | { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8686 | { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8687 | { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8688 | { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8689 | { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8690 | { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8691 | { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8692 | { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8693 | { 1058 /* bgezall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8694 | { 1058 /* bgezall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8695 | { 1066 /* bgezals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8696 | { 1066 /* bgezals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8697 | { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8698 | { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8699 | { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8700 | { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8701 | { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8702 | { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8703 | { 1080 /* bgezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8704 | { 1080 /* bgezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8705 | { 1086 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8706 | { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8707 | { 1086 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8708 | { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8709 | { 1090 /* bgtl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8710 | { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8711 | { 1090 /* bgtl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8712 | { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8713 | { 1095 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8714 | { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8715 | { 1095 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8716 | { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8717 | { 1100 /* bgtul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8718 | { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8719 | { 1100 /* bgtul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8720 | { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8721 | { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8722 | { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8723 | { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8724 | { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8725 | { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8726 | { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8727 | { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8728 | { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8729 | { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8730 | { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8731 | { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8732 | { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8733 | { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8734 | { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8735 | { 1125 /* bgtzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8736 | { 1125 /* bgtzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8737 | { 1131 /* binsl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8738 | { 1139 /* binsl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8739 | { 1147 /* binsl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8740 | { 1155 /* binsl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8741 | { 1163 /* binsli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8742 | { 1172 /* binsli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8743 | { 1181 /* binsli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8744 | { 1190 /* binsli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8745 | { 1199 /* binsr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8746 | { 1207 /* binsr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8747 | { 1215 /* binsr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8748 | { 1223 /* binsr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8749 | { 1231 /* binsri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8750 | { 1240 /* binsri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8751 | { 1249 /* binsri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8752 | { 1258 /* binsri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8753 | { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 8754 | { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 8755 | { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 8756 | { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8757 | { 1282 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8758 | { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8759 | { 1282 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8760 | { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8761 | { 1286 /* blel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8762 | { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8763 | { 1286 /* blel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8764 | { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8765 | { 1291 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8766 | { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8767 | { 1291 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8768 | { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8769 | { 1296 /* bleul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8770 | { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8771 | { 1296 /* bleul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8772 | { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8773 | { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8774 | { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8775 | { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8776 | { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8777 | { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8778 | { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8779 | { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8780 | { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8781 | { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8782 | { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8783 | { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8784 | { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8785 | { 1315 /* blezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8786 | { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8787 | { 1321 /* blezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8788 | { 1321 /* blezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8789 | { 1327 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8790 | { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8791 | { 1327 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8792 | { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8793 | { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8794 | { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8795 | { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8796 | { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8797 | { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8798 | { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8799 | { 1336 /* bltl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8800 | { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8801 | { 1336 /* bltl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8802 | { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8803 | { 1341 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8804 | { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8805 | { 1341 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8806 | { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8807 | { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8808 | { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8809 | { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8810 | { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8811 | { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8812 | { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8813 | { 1352 /* bltul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8814 | { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8815 | { 1352 /* bltul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8816 | { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8817 | { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8818 | { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8819 | { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8820 | { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8821 | { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8822 | { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8823 | { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8824 | { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8825 | { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8826 | { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8827 | { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8828 | { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8829 | { 1378 /* bltzall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8830 | { 1378 /* bltzall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8831 | { 1386 /* bltzals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8832 | { 1386 /* bltzals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8833 | { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8834 | { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8835 | { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8836 | { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8837 | { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8838 | { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8839 | { 1400 /* bltzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8840 | { 1400 /* bltzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8841 | { 1406 /* bmnz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8842 | { 1413 /* bmnzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8843 | { 1421 /* bmz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8844 | { 1427 /* bmzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8845 | { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8846 | { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8847 | { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8848 | { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8849 | { 1434 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 8850 | { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None }, |
| 8851 | { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8852 | { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8853 | { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8854 | { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8855 | { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8856 | { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8857 | { 1443 /* bneg.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8858 | { 1450 /* bneg.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8859 | { 1457 /* bneg.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8860 | { 1464 /* bneg.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8861 | { 1471 /* bnegi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8862 | { 1479 /* bnegi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8863 | { 1487 /* bnegi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8864 | { 1495 /* bnegi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8865 | { 1503 /* bnel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8866 | { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 8867 | { 1503 /* bnel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8868 | { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 }, |
| 8869 | { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
| 8870 | { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8871 | { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 8872 | { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 8873 | { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips }, |
| 8874 | { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode }, |
| 8875 | { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8876 | { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8877 | { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8878 | { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8879 | { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8880 | { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8881 | { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8882 | { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8883 | { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8884 | { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8885 | { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 8886 | { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 8887 | { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8888 | { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8889 | { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8890 | { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 8891 | { 1534 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8892 | { 1534 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8893 | { 1542 /* bnezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 8894 | { 1542 /* bnezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 8895 | { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8896 | { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8897 | { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8898 | { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8899 | { 1553 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8900 | { 1553 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8901 | { 1559 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8902 | { 1559 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8903 | { 1565 /* bnz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8904 | { 1565 /* bnz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8905 | { 1571 /* bnz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8906 | { 1571 /* bnz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8907 | { 1577 /* bnz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8908 | { 1577 /* bnz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8909 | { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8910 | { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 8911 | { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 8912 | { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 8913 | { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_HasDSP }, |
| 8914 | { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasDSP_NotInMicroMips }, |
| 8915 | { 1597 /* bposge32c */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasDSPR3 }, |
| 8916 | { 1621 /* bsel.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8917 | { 1628 /* bseli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8918 | { 1636 /* bset.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8919 | { 1643 /* bset.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8920 | { 1650 /* bset.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8921 | { 1657 /* bset.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8922 | { 1664 /* bseti.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8923 | { 1672 /* bseti.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8924 | { 1680 /* bseti.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8925 | { 1688 /* bseti.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8926 | { 1708 /* bz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8927 | { 1708 /* bz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8928 | { 1713 /* bz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8929 | { 1713 /* bz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8930 | { 1718 /* bz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8931 | { 1718 /* bz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8932 | { 1723 /* bz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8933 | { 1723 /* bz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8934 | { 1728 /* bz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 8935 | { 1728 /* bz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA }, |
| 8936 | { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8937 | { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8938 | { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8939 | { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8940 | { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8941 | { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8942 | { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8943 | { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8944 | { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8945 | { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8946 | { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8947 | { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8948 | { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8949 | { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8950 | { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8951 | { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8952 | { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8953 | { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8954 | { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8955 | { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8956 | { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8957 | { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8958 | { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8959 | { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8960 | { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8961 | { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8962 | { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8963 | { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8964 | { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8965 | { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8966 | { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8967 | { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8968 | { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8969 | { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8970 | { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8971 | { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8972 | { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8973 | { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8974 | { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8975 | { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8976 | { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8977 | { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8978 | { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8979 | { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8980 | { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8981 | { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8982 | { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8983 | { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8984 | { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8985 | { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8986 | { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8987 | { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8988 | { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8989 | { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 8990 | { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8991 | { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8992 | { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8993 | { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8994 | { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8995 | { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8996 | { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8997 | { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 8998 | { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 8999 | { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9000 | { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9001 | { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9002 | { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9003 | { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9004 | { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9005 | { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9006 | { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9007 | { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9008 | { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9009 | { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9010 | { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9011 | { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9012 | { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9013 | { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9014 | { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9015 | { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9016 | { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9017 | { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9018 | { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9019 | { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9020 | { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9021 | { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9022 | { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9023 | { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9024 | { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9025 | { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9026 | { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9027 | { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9028 | { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9029 | { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9030 | { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9031 | { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9032 | { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9033 | { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9034 | { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9035 | { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9036 | { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9037 | { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9038 | { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9039 | { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9040 | { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9041 | { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9042 | { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9043 | { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9044 | { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9045 | { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9046 | { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9047 | { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9048 | { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9049 | { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9050 | { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9051 | { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9052 | { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9053 | { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9054 | { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9055 | { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9056 | { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9057 | { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9058 | { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9059 | { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9060 | { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9061 | { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9062 | { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9063 | { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9064 | { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9065 | { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9066 | { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9067 | { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9068 | { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9069 | { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9070 | { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9071 | { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9072 | { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9073 | { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9074 | { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9075 | { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9076 | { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9077 | { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9078 | { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9079 | { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9080 | { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9081 | { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9082 | { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9083 | { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9084 | { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9085 | { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9086 | { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9087 | { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9088 | { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9089 | { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9090 | { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9091 | { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9092 | { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9093 | { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9094 | { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9095 | { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9096 | { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9097 | { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9098 | { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9099 | { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9100 | { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9101 | { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9102 | { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9103 | { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9104 | { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9105 | { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9106 | { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9107 | { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9108 | { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9109 | { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9110 | { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9111 | { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9112 | { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9113 | { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9114 | { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9115 | { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9116 | { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9117 | { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9118 | { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9119 | { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9120 | { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9121 | { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9122 | { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9123 | { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9124 | { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9125 | { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9126 | { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9127 | { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9128 | { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9129 | { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9130 | { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9131 | { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9132 | { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9133 | { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9134 | { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9135 | { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9136 | { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9137 | { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9138 | { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9139 | { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9140 | { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9141 | { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9142 | { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9143 | { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9144 | { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9145 | { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9146 | { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9147 | { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9148 | { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9149 | { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9150 | { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9151 | { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9152 | { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9153 | { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9154 | { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9155 | { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9156 | { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9157 | { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9158 | { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9159 | { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9160 | { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9161 | { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9162 | { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9163 | { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9164 | { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9165 | { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9166 | { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9167 | { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9168 | { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9169 | { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9170 | { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9171 | { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9172 | { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9173 | { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9174 | { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9175 | { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9176 | { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9177 | { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9178 | { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9179 | { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9180 | { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9181 | { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9182 | { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9183 | { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9184 | { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9185 | { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9186 | { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9187 | { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9188 | { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9189 | { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9190 | { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9191 | { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9192 | { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9193 | { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9194 | { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9195 | { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9196 | { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9197 | { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9198 | { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9199 | { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9200 | { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9201 | { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9202 | { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9203 | { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9204 | { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9205 | { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9206 | { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9207 | { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9208 | { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9209 | { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9210 | { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9211 | { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9212 | { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9213 | { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9214 | { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9215 | { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9216 | { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9217 | { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 9218 | { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9219 | { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9220 | { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9221 | { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9222 | { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9223 | { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 9224 | { 1977 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 9225 | { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9226 | { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 9227 | { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
| 9228 | { 1983 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 9229 | { 1983 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 9230 | { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
| 9231 | { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9232 | { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9233 | { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9234 | { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9235 | { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9236 | { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9237 | { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9238 | { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9239 | { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9240 | { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9241 | { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9242 | { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9243 | { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9244 | { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9245 | { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9246 | { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9247 | { 2026 /* ceq.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9248 | { 2032 /* ceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9249 | { 2038 /* ceq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9250 | { 2044 /* ceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9251 | { 2050 /* ceqi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9252 | { 2057 /* ceqi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9253 | { 2064 /* ceqi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9254 | { 2071 /* ceqi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9255 | { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9256 | { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9257 | { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9258 | { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9259 | { 2083 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips }, |
| 9260 | { 2083 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 9261 | { 2088 /* cfcmsa */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9262 | { 2088 /* cfcmsa */, 2 /* 1 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9263 | { 2095 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
| 9264 | { 2095 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 9265 | { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9266 | { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
| 9267 | { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9268 | { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
| 9269 | { 2106 /* cins32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9270 | { 2106 /* cins32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9271 | { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9272 | { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9273 | { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9274 | { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9275 | { 2129 /* cle_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9276 | { 2137 /* cle_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9277 | { 2145 /* cle_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9278 | { 2153 /* cle_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9279 | { 2161 /* cle_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9280 | { 2169 /* cle_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9281 | { 2177 /* cle_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9282 | { 2185 /* cle_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9283 | { 2193 /* clei_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9284 | { 2202 /* clei_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9285 | { 2211 /* clei_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9286 | { 2220 /* clei_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9287 | { 2229 /* clei_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9288 | { 2238 /* clei_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9289 | { 2247 /* clei_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9290 | { 2256 /* clei_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9291 | { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9292 | { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9293 | { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 9294 | { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 9295 | { 2269 /* clt_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9296 | { 2277 /* clt_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9297 | { 2285 /* clt_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9298 | { 2293 /* clt_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9299 | { 2301 /* clt_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9300 | { 2309 /* clt_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9301 | { 2317 /* clt_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9302 | { 2325 /* clt_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9303 | { 2333 /* clti_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9304 | { 2342 /* clti_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9305 | { 2351 /* clti_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9306 | { 2360 /* clti_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9307 | { 2369 /* clti_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9308 | { 2378 /* clti_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9309 | { 2387 /* clti_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9310 | { 2396 /* clti_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9311 | { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9312 | { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9313 | { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 9314 | { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 9315 | { 2413 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9316 | { 2413 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9317 | { 2413 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9318 | { 2413 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9319 | { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9320 | { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9321 | { 2431 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9322 | { 2431 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9323 | { 2431 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9324 | { 2431 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9325 | { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9326 | { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9327 | { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9328 | { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9329 | { 2459 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9330 | { 2459 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9331 | { 2459 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9332 | { 2459 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9333 | { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9334 | { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9335 | { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9336 | { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9337 | { 2487 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9338 | { 2487 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9339 | { 2487 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9340 | { 2487 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9341 | { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9342 | { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9343 | { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9344 | { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9345 | { 2515 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9346 | { 2515 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9347 | { 2515 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9348 | { 2515 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9349 | { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9350 | { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9351 | { 2535 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9352 | { 2535 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9353 | { 2535 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9354 | { 2535 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9355 | { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9356 | { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9357 | { 2555 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9358 | { 2555 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9359 | { 2555 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9360 | { 2555 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9361 | { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9362 | { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9363 | { 2575 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9364 | { 2575 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9365 | { 2575 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9366 | { 2575 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9367 | { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9368 | { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9369 | { 2595 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9370 | { 2595 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9371 | { 2595 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9372 | { 2595 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9373 | { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9374 | { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9375 | { 2617 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9376 | { 2617 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9377 | { 2617 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9378 | { 2617 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9379 | { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9380 | { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9381 | { 2639 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9382 | { 2639 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9383 | { 2639 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9384 | { 2639 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9385 | { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9386 | { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9387 | { 2661 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9388 | { 2661 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9389 | { 2661 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9390 | { 2661 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9391 | { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9392 | { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9393 | { 2681 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9394 | { 2681 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9395 | { 2681 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9396 | { 2681 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9397 | { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9398 | { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9399 | { 2701 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9400 | { 2701 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9401 | { 2701 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9402 | { 2701 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9403 | { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9404 | { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9405 | { 2721 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9406 | { 2721 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9407 | { 2721 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9408 | { 2721 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9409 | { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9410 | { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9411 | { 2741 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9412 | { 2741 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9413 | { 2741 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9414 | { 2741 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9415 | { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 9416 | { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9417 | { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9418 | { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9419 | { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9420 | { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9421 | { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9422 | { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9423 | { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9424 | { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9425 | { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9426 | { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9427 | { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9428 | { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9429 | { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9430 | { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9431 | { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9432 | { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9433 | { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9434 | { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9435 | { 2872 /* copy_s.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9436 | { 2872 /* copy_s.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9437 | { 2881 /* copy_s.d */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9438 | { 2881 /* copy_s.d */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9439 | { 2890 /* copy_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9440 | { 2890 /* copy_s.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9441 | { 2899 /* copy_s.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9442 | { 2899 /* copy_s.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9443 | { 2908 /* copy_u.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9444 | { 2908 /* copy_u.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9445 | { 2917 /* copy_u.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9446 | { 2917 /* copy_u.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9447 | { 2926 /* copy_u.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9448 | { 2926 /* copy_u.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9449 | { 2935 /* crc32b */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
| 9450 | { 2942 /* crc32cb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
| 9451 | { 2950 /* crc32cd */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips }, |
| 9452 | { 2958 /* crc32ch */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
| 9453 | { 2966 /* crc32cw */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
| 9454 | { 2974 /* crc32d */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips }, |
| 9455 | { 2981 /* crc32h */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
| 9456 | { 2988 /* crc32w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips }, |
| 9457 | { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9458 | { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9459 | { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9460 | { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9461 | { 3000 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips }, |
| 9462 | { 3000 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 9463 | { 3005 /* ctcmsa */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9464 | { 3005 /* ctcmsa */, 1 /* 0 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9465 | { 3012 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
| 9466 | { 3012 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 9467 | { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 9468 | { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 9469 | { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9470 | { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9471 | { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9472 | { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9473 | { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9474 | { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9475 | { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9476 | { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9477 | { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9478 | { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9479 | { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9480 | { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9481 | { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9482 | { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9483 | { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9484 | { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9485 | { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 9486 | { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9487 | { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9488 | { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 9489 | { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 9490 | { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9491 | { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9492 | { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9493 | { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9494 | { 3058 /* cvt.ps.pw */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D }, |
| 9495 | { 3068 /* cvt.ps.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9496 | { 3068 /* cvt.ps.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9497 | { 3077 /* cvt.pw.ps */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D }, |
| 9498 | { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9499 | { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9500 | { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9501 | { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9502 | { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9503 | { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9504 | { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9505 | { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9506 | { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 9507 | { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 9508 | { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 9509 | { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 9510 | { 3103 /* cvt.s.pl */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9511 | { 3103 /* cvt.s.pl */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9512 | { 3112 /* cvt.s.pu */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9513 | { 3112 /* cvt.s.pu */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 9514 | { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9515 | { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9516 | { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9517 | { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9518 | { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9519 | { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9520 | { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9521 | { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9522 | { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9523 | { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9524 | { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9525 | { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9526 | { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9527 | { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9528 | { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9529 | { 3145 /* dadd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9530 | { 3145 /* dadd */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9531 | { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9532 | { 3150 /* daddi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9533 | { 3150 /* daddi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9534 | { 3156 /* daddiu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9535 | { 3156 /* daddiu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9536 | { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9537 | { 3163 /* daddu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9538 | { 3163 /* daddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9539 | { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9540 | { 3169 /* dahi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9541 | { 3174 /* dalign */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9542 | { 3181 /* dati */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9543 | { 3186 /* daui */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9544 | { 3191 /* dbitswap */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9545 | { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips }, |
| 9546 | { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9547 | { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips }, |
| 9548 | { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9549 | { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9550 | { 3210 /* ddiv */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9551 | { 3210 /* ddiv */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9552 | { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9553 | { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9554 | { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9555 | { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9556 | { 3215 /* ddivu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9557 | { 3215 /* ddivu */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9558 | { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9559 | { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9560 | { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9561 | { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9562 | { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9563 | { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9564 | { 3232 /* dextm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9565 | { 3238 /* dextu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9566 | { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 9567 | { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9568 | { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 9569 | { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9570 | { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9571 | { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9572 | { 3252 /* dinsm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9573 | { 3258 /* dinsu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9574 | { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 9575 | { 3264 /* div */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9576 | { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9577 | { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9578 | { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9579 | { 3264 /* div */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9580 | { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9581 | { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 9582 | { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 9583 | { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9584 | { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9585 | { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9586 | { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9587 | { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9588 | { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9589 | { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 9590 | { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 9591 | { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 9592 | { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9593 | { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9594 | { 3280 /* div_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9595 | { 3288 /* div_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9596 | { 3296 /* div_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9597 | { 3304 /* div_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9598 | { 3312 /* div_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9599 | { 3320 /* div_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9600 | { 3328 /* div_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9601 | { 3336 /* div_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9602 | { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 9603 | { 3344 /* divu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9604 | { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9605 | { 3344 /* divu */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9606 | { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9607 | { 3344 /* divu */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9608 | { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9609 | { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 9610 | { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9611 | { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 9612 | { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9613 | { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 9614 | { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
| 9615 | { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
| 9616 | { 3349 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 9617 | { 3353 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
| 9618 | { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9619 | { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9620 | { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips }, |
| 9621 | { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips }, |
| 9622 | { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9623 | { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9624 | { 3368 /* dmfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
| 9625 | { 3368 /* dmfc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
| 9626 | { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None }, |
| 9627 | { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
| 9628 | { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 9629 | { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9630 | { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9631 | { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
| 9632 | { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
| 9633 | { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
| 9634 | { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
| 9635 | { 3387 /* dmod */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9636 | { 3392 /* dmodu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9637 | { 3398 /* dmt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 9638 | { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips }, |
| 9639 | { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips }, |
| 9640 | { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9641 | { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9642 | { 3408 /* dmtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
| 9643 | { 3408 /* dmtc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips }, |
| 9644 | { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None }, |
| 9645 | { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None }, |
| 9646 | { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 9647 | { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9648 | { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 }, |
| 9649 | { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
| 9650 | { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips }, |
| 9651 | { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
| 9652 | { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt }, |
| 9653 | { 3427 /* dmuh */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9654 | { 3432 /* dmuhu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9655 | { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 9656 | { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasMips3_NotMips64r6_NotCnMips }, |
| 9657 | { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9658 | { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 9659 | { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9660 | { 3443 /* dmulo */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9661 | { 3449 /* dmulou */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9662 | { 3456 /* dmult */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9663 | { 3462 /* dmultu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9664 | { 3469 /* dmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 9665 | { 3475 /* dneg */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9666 | { 3475 /* dneg */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9667 | { 3480 /* dnegu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9668 | { 3480 /* dnegu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9669 | { 3486 /* dotp_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9670 | { 3495 /* dotp_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9671 | { 3504 /* dotp_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9672 | { 3513 /* dotp_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9673 | { 3522 /* dotp_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9674 | { 3531 /* dotp_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9675 | { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9676 | { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9677 | { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9678 | { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9679 | { 3549 /* dpadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9680 | { 3559 /* dpadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9681 | { 3569 /* dpadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9682 | { 3579 /* dpadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9683 | { 3589 /* dpadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9684 | { 3599 /* dpadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9685 | { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9686 | { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9687 | { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9688 | { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9689 | { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9690 | { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9691 | { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9692 | { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9693 | { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9694 | { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9695 | { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9696 | { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9697 | { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9698 | { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9699 | { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9700 | { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9701 | { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9702 | { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9703 | { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9704 | { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9705 | { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9706 | { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9707 | { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9708 | { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9709 | { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9710 | { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9711 | { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9712 | { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9713 | { 3692 /* dpop */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 9714 | { 3692 /* dpop */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 9715 | { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9716 | { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9717 | { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9718 | { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9719 | { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9720 | { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9721 | { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9722 | { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9723 | { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9724 | { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9725 | { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9726 | { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9727 | { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9728 | { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9729 | { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9730 | { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9731 | { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9732 | { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9733 | { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9734 | { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9735 | { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9736 | { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9737 | { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9738 | { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9739 | { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9740 | { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9741 | { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9742 | { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9743 | { 3779 /* dpsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9744 | { 3789 /* dpsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9745 | { 3799 /* dpsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9746 | { 3809 /* dpsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9747 | { 3819 /* dpsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9748 | { 3829 /* dpsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9749 | { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9750 | { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 9751 | { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 9752 | { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 9753 | { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9754 | { 3849 /* drem */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9755 | { 3849 /* drem */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9756 | { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9757 | { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9758 | { 3854 /* dremu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9759 | { 3854 /* dremu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9760 | { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 9761 | { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9762 | { 3860 /* drol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9763 | { 3860 /* drol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9764 | { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9765 | { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9766 | { 3865 /* dror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9767 | { 3865 /* dror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9768 | { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 }, |
| 9769 | { 3870 /* drotr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9770 | { 3870 /* drotr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9771 | { 3876 /* drotr32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9772 | { 3876 /* drotr32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9773 | { 3884 /* drotrv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9774 | { 3884 /* drotrv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9775 | { 3891 /* dsbh */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9776 | { 3896 /* dshd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 9777 | { 3901 /* dsll */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9778 | { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9779 | { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9780 | { 3901 /* dsll */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9781 | { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9782 | { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9783 | { 3906 /* dsll32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9784 | { 3906 /* dsll32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9785 | { 3913 /* dsllv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9786 | { 3913 /* dsllv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9787 | { 3919 /* dsra */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9788 | { 3919 /* dsra */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3 }, |
| 9789 | { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3 }, |
| 9790 | { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9791 | { 3924 /* dsra32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9792 | { 3924 /* dsra32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9793 | { 3931 /* dsrav */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9794 | { 3931 /* dsrav */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9795 | { 3937 /* dsrl */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9796 | { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9797 | { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9798 | { 3937 /* dsrl */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9799 | { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9800 | { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9801 | { 3942 /* dsrl32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9802 | { 3942 /* dsrl32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9803 | { 3949 /* dsrlv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9804 | { 3949 /* dsrlv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9805 | { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9806 | { 3955 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9807 | { 3955 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9808 | { 3955 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9809 | { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9810 | { 3955 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9811 | { 3960 /* dsubi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9812 | { 3960 /* dsubi */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9813 | { 3960 /* dsubi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9814 | { 3960 /* dsubi */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 9815 | { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9816 | { 3966 /* dsubu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9817 | { 3966 /* dsubu */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9818 | { 3966 /* dsubu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9819 | { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9820 | { 3966 /* dsubu */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 9821 | { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 9822 | { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9823 | { 3976 /* dvpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 9824 | { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 9825 | { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9826 | { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 9827 | { 3988 /* emt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 9828 | { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 9829 | { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9830 | { 4008 /* evpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 9831 | { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 9832 | { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 9833 | { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 9834 | { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9835 | { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9836 | { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9837 | { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9838 | { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9839 | { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9840 | { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9841 | { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9842 | { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9843 | { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9844 | { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9845 | { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9846 | { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9847 | { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9848 | { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9849 | { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9850 | { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9851 | { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9852 | { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9853 | { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9854 | { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9855 | { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9856 | { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9857 | { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9858 | { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9859 | { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9860 | { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9861 | { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9862 | { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9863 | { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9864 | { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9865 | { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9866 | { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9867 | { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9868 | { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9869 | { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9870 | { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9871 | { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9872 | { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9873 | { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9874 | { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9875 | { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9876 | { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9877 | { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9878 | { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9879 | { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 9880 | { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 9881 | { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 9882 | { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9883 | { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
| 9884 | { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9885 | { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips }, |
| 9886 | { 4122 /* exts32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9887 | { 4122 /* exts32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips }, |
| 9888 | { 4129 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9889 | { 4136 /* fadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9890 | { 4143 /* fcaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9891 | { 4150 /* fcaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9892 | { 4157 /* fceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9893 | { 4164 /* fceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9894 | { 4171 /* fclass.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9895 | { 4180 /* fclass.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9896 | { 4189 /* fcle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9897 | { 4196 /* fcle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9898 | { 4203 /* fclt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9899 | { 4210 /* fclt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9900 | { 4217 /* fcne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9901 | { 4224 /* fcne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9902 | { 4231 /* fcor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9903 | { 4238 /* fcor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9904 | { 4245 /* fcueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9905 | { 4253 /* fcueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9906 | { 4261 /* fcule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9907 | { 4269 /* fcule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9908 | { 4277 /* fcult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9909 | { 4285 /* fcult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9910 | { 4293 /* fcun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9911 | { 4300 /* fcun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9912 | { 4307 /* fcune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9913 | { 4315 /* fcune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9914 | { 4323 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9915 | { 4330 /* fdiv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9916 | { 4337 /* fexdo.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9917 | { 4345 /* fexdo.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9918 | { 4353 /* fexp2.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9919 | { 4361 /* fexp2.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9920 | { 4369 /* fexupl.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9921 | { 4378 /* fexupl.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9922 | { 4387 /* fexupr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9923 | { 4396 /* fexupr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9924 | { 4405 /* ffint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9925 | { 4415 /* ffint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9926 | { 4425 /* ffint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9927 | { 4435 /* ffint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9928 | { 4445 /* ffql.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9929 | { 4452 /* ffql.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9930 | { 4459 /* ffqr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9931 | { 4466 /* ffqr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9932 | { 4473 /* fill.b */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9933 | { 4473 /* fill.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9934 | { 4480 /* fill.d */, 2 /* 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9935 | { 4480 /* fill.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 9936 | { 4487 /* fill.h */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9937 | { 4487 /* fill.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9938 | { 4494 /* fill.w */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9939 | { 4494 /* fill.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9940 | { 4501 /* flog2.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9941 | { 4509 /* flog2.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9942 | { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
| 9943 | { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9944 | { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9945 | { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9946 | { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9947 | { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9948 | { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9949 | { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9950 | { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9951 | { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9952 | { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9953 | { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 9954 | { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9955 | { 4537 /* floor.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9956 | { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 9957 | { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 9958 | { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 9959 | { 4557 /* fmadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9960 | { 4565 /* fmadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9961 | { 4573 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9962 | { 4580 /* fmax.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9963 | { 4587 /* fmax_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9964 | { 4596 /* fmax_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9965 | { 4605 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9966 | { 4612 /* fmin.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9967 | { 4619 /* fmin_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9968 | { 4628 /* fmin_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9969 | { 4637 /* fmsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9970 | { 4645 /* fmsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9971 | { 4653 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9972 | { 4660 /* fmul.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9973 | { 4667 /* fork */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 9974 | { 4672 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9975 | { 4679 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9976 | { 4686 /* frint.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9977 | { 4694 /* frint.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9978 | { 4702 /* frsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9979 | { 4711 /* frsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9980 | { 4720 /* fsaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9981 | { 4727 /* fsaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9982 | { 4734 /* fseq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9983 | { 4741 /* fseq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9984 | { 4748 /* fsle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9985 | { 4755 /* fsle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9986 | { 4762 /* fslt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9987 | { 4769 /* fslt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9988 | { 4776 /* fsne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9989 | { 4783 /* fsne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9990 | { 4790 /* fsor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9991 | { 4797 /* fsor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9992 | { 4804 /* fsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9993 | { 4812 /* fsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9994 | { 4820 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9995 | { 4827 /* fsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9996 | { 4834 /* fsueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9997 | { 4842 /* fsueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9998 | { 4850 /* fsule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 9999 | { 4858 /* fsule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10000 | { 4866 /* fsult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10001 | { 4874 /* fsult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10002 | { 4882 /* fsun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10003 | { 4889 /* fsun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10004 | { 4896 /* fsune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10005 | { 4904 /* fsune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10006 | { 4912 /* ftint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10007 | { 4922 /* ftint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10008 | { 4932 /* ftint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10009 | { 4942 /* ftint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10010 | { 4952 /* ftq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10011 | { 4958 /* ftq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10012 | { 4964 /* ftrunc_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10013 | { 4975 /* ftrunc_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10014 | { 4986 /* ftrunc_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10015 | { 4997 /* ftrunc_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10016 | { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips }, |
| 10017 | { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV }, |
| 10018 | { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips }, |
| 10019 | { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV }, |
| 10020 | { 5020 /* hadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10021 | { 5029 /* hadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10022 | { 5038 /* hadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10023 | { 5047 /* hadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10024 | { 5056 /* hadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10025 | { 5065 /* hadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10026 | { 5074 /* hsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10027 | { 5083 /* hsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10028 | { 5092 /* hsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10029 | { 5101 /* hsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10030 | { 5110 /* hsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10031 | { 5119 /* hsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10032 | { 5136 /* ilvev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10033 | { 5144 /* ilvev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10034 | { 5152 /* ilvev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10035 | { 5160 /* ilvev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10036 | { 5168 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10037 | { 5175 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10038 | { 5182 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10039 | { 5189 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10040 | { 5196 /* ilvod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10041 | { 5204 /* ilvod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10042 | { 5212 /* ilvod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10043 | { 5220 /* ilvod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10044 | { 5228 /* ilvr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10045 | { 5235 /* ilvr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10046 | { 5242 /* ilvr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10047 | { 5249 /* ilvr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10048 | { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 10049 | { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10050 | { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10051 | { 5260 /* insert.b */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10052 | { 5260 /* insert.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10053 | { 5269 /* insert.d */, 16 /* 4 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 10054 | { 5269 /* insert.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 }, |
| 10055 | { 5278 /* insert.h */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10056 | { 5278 /* insert.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10057 | { 5287 /* insert.w */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10058 | { 5287 /* insert.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10059 | { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10060 | { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10061 | { 5301 /* insve.b */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10062 | { 5309 /* insve.d */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10063 | { 5317 /* insve.h */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10064 | { 5325 /* insve.w */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10065 | { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10066 | { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10067 | { 5333 /* j */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10068 | { 5335 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10069 | { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10070 | { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 10071 | { 5335 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10072 | { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10073 | { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10074 | { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 10075 | { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards }, |
| 10076 | { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10077 | { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit }, |
| 10078 | { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotInMicroMips }, |
| 10079 | { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotInMicroMips }, |
| 10080 | { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32 }, |
| 10081 | { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips }, |
| 10082 | { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
| 10083 | { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10084 | { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
| 10085 | { 5352 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10086 | { 5358 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10087 | { 5358 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10088 | { 5367 /* jalrs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10089 | { 5373 /* jalrs16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10090 | { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10091 | { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 }, |
| 10092 | { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10093 | { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10094 | { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10095 | { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 10096 | { 5391 /* jialc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 10097 | { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 10098 | { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10099 | { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10100 | { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10101 | { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 }, |
| 10102 | { 5397 /* jic */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 10103 | { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 }, |
| 10104 | { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10105 | { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
| 10106 | { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10107 | { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips }, |
| 10108 | { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
| 10109 | { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6 }, |
| 10110 | { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10111 | { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips }, |
| 10112 | { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10113 | { 5410 /* jr16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10114 | { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6 }, |
| 10115 | { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10116 | { 5425 /* jrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
| 10117 | { 5429 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10118 | { 5446 /* l.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
| 10119 | { 5446 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
| 10120 | { 5446 /* l.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
| 10121 | { 5446 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
| 10122 | { 5450 /* l.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
| 10123 | { 5450 /* l.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
| 10124 | { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10125 | { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10126 | { 5454 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 10127 | { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10128 | { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10129 | { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10130 | { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10131 | { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10132 | { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 10133 | { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10134 | { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips }, |
| 10135 | { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10136 | { 5465 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10137 | { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 10138 | { 5465 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA }, |
| 10139 | { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10140 | { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10141 | { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10142 | { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 10143 | { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10144 | { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips }, |
| 10145 | { 5473 /* lbu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
| 10146 | { 5473 /* lbu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, |
| 10147 | { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10148 | { 5479 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10149 | { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 10150 | { 5479 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA }, |
| 10151 | { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10152 | { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10153 | { 5489 /* ld */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 }, |
| 10154 | { 5489 /* ld */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 }, |
| 10155 | { 5489 /* ld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 10156 | { 5489 /* ld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 10157 | { 5492 /* ld.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10158 | { 5492 /* ld.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA }, |
| 10159 | { 5497 /* ld.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10160 | { 5497 /* ld.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA }, |
| 10161 | { 5502 /* ld.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10162 | { 5502 /* ld.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA }, |
| 10163 | { 5507 /* ld.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10164 | { 5507 /* ld.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA }, |
| 10165 | { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 10166 | { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 10167 | { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10168 | { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10169 | { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 10170 | { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 10171 | { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 10172 | { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 10173 | { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10174 | { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10175 | { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10176 | { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10177 | { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10178 | { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 10179 | { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10180 | { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10181 | { 5522 /* ldc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
| 10182 | { 5522 /* ldc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
| 10183 | { 5527 /* ldi.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10184 | { 5533 /* ldi.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10185 | { 5539 /* ldi.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10186 | { 5545 /* ldi.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10187 | { 5551 /* ldl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 10188 | { 5551 /* ldl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 10189 | { 5555 /* ldpc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
| 10190 | { 5555 /* ldpc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips64r6 }, |
| 10191 | { 5560 /* ldr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 10192 | { 5560 /* ldr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 10193 | { 5564 /* ldxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10194 | { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10195 | { 5564 /* ldxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 10196 | { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 10197 | { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10198 | { 5570 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10199 | { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10200 | { 5570 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, |
| 10201 | { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10202 | { 5573 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10203 | { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 10204 | { 5573 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 10205 | { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10206 | { 5577 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10207 | { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10208 | { 5577 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips }, |
| 10209 | { 5581 /* lhu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
| 10210 | { 5581 /* lhu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, |
| 10211 | { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10212 | { 5587 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10213 | { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 10214 | { 5587 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 10215 | { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10216 | { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10217 | { 5596 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10218 | { 5599 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10219 | { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyAFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
| 10220 | { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyFGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
| 10221 | { 5604 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10222 | { 5604 /* li.s */, 1 /* 0 */, MCK_StrictlyFGR32AsmReg, AMFBS_IsNotSoftFloat }, |
| 10223 | { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10224 | { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10225 | { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
| 10226 | { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
| 10227 | { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
| 10228 | { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
| 10229 | { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10230 | { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 10231 | { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10232 | { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10233 | { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10234 | { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10235 | { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10236 | { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 10237 | { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10238 | { 5617 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10239 | { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 10240 | { 5617 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips }, |
| 10241 | { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10242 | { 5621 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10243 | { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 10244 | { 5621 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 10245 | { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10246 | { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10247 | { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10248 | { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10249 | { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10250 | { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10251 | { 5633 /* luxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10252 | { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10253 | { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10254 | { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10255 | { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10256 | { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10257 | { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10258 | { 5639 /* lw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips }, |
| 10259 | { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10260 | { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10261 | { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP }, |
| 10262 | { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP }, |
| 10263 | { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10264 | { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP }, |
| 10265 | { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10266 | { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
| 10267 | { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10268 | { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 10269 | { 5639 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
| 10270 | { 5639 /* lw */, 2 /* 1 */, MCK_MicroMipsMemGP, AMFBS_InMicroMips }, |
| 10271 | { 5642 /* lw16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips }, |
| 10272 | { 5642 /* lw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips }, |
| 10273 | { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10274 | { 5647 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10275 | { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10276 | { 5647 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10277 | { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10278 | { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10279 | { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10280 | { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 10281 | { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10282 | { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10283 | { 5657 /* lwc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
| 10284 | { 5657 /* lwc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
| 10285 | { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10286 | { 5662 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10287 | { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 10288 | { 5662 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 10289 | { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10290 | { 5666 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10291 | { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10292 | { 5666 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 10293 | { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 10294 | { 5670 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 10295 | { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 10296 | { 5670 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 10297 | { 5675 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 10298 | { 5675 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
| 10299 | { 5679 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 }, |
| 10300 | { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 }, |
| 10301 | { 5679 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 }, |
| 10302 | { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 }, |
| 10303 | { 5685 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 10304 | { 5685 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
| 10305 | { 5691 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10306 | { 5691 /* lwp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips }, |
| 10307 | { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 10308 | { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10309 | { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10310 | { 5700 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10311 | { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10312 | { 5700 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 10313 | { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 10314 | { 5704 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 10315 | { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 10316 | { 5704 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 10317 | { 5709 /* lwu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10318 | { 5709 /* lwu */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips_NotMips32r6 }, |
| 10319 | { 5709 /* lwu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 10320 | { 5709 /* lwu */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 10321 | { 5713 /* lwupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6 }, |
| 10322 | { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10323 | { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10324 | { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 10325 | { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 10326 | { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10327 | { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10328 | { 5729 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10329 | { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10330 | { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10331 | { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10332 | { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10333 | { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10334 | { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10335 | { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
| 10336 | { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10337 | { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
| 10338 | { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
| 10339 | { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10340 | { 5753 /* madd_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10341 | { 5762 /* madd_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10342 | { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10343 | { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10344 | { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10345 | { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10346 | { 5787 /* maddr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10347 | { 5797 /* maddr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10348 | { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10349 | { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10350 | { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10351 | { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10352 | { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10353 | { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10354 | { 5813 /* maddv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10355 | { 5821 /* maddv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10356 | { 5829 /* maddv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10357 | { 5837 /* maddv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10358 | { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10359 | { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10360 | { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10361 | { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10362 | { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10363 | { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10364 | { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10365 | { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10366 | { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10367 | { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10368 | { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10369 | { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10370 | { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10371 | { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10372 | { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10373 | { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10374 | { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10375 | { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10376 | { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10377 | { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10378 | { 5907 /* max_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10379 | { 5915 /* max_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10380 | { 5923 /* max_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10381 | { 5931 /* max_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10382 | { 5939 /* max_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10383 | { 5947 /* max_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10384 | { 5955 /* max_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10385 | { 5963 /* max_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10386 | { 5971 /* max_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10387 | { 5979 /* max_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10388 | { 5987 /* max_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10389 | { 5995 /* max_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10390 | { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10391 | { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10392 | { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10393 | { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10394 | { 6017 /* maxi_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10395 | { 6026 /* maxi_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10396 | { 6035 /* maxi_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10397 | { 6044 /* maxi_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10398 | { 6053 /* maxi_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10399 | { 6062 /* maxi_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10400 | { 6071 /* maxi_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10401 | { 6080 /* maxi_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10402 | { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10403 | { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10404 | { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10405 | { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10406 | { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10407 | { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10408 | { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10409 | { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10410 | { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10411 | { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10412 | { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10413 | { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10414 | { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10415 | { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10416 | { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10417 | { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10418 | { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10419 | { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10420 | { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10421 | { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10422 | { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10423 | { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10424 | { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10425 | { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10426 | { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10427 | { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10428 | { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10429 | { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10430 | { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10431 | { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10432 | { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10433 | { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10434 | { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10435 | { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10436 | { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10437 | { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10438 | { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10439 | { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10440 | { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10441 | { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10442 | { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10443 | { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10444 | { 6122 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10445 | { 6122 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10446 | { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10447 | { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10448 | { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10449 | { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10450 | { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10451 | { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10452 | { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10453 | { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10454 | { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10455 | { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10456 | { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10457 | { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10458 | { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10459 | { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10460 | { 6140 /* mfhi16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10461 | { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10462 | { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10463 | { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10464 | { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10465 | { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10466 | { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10467 | { 6152 /* mflo16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10468 | { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10469 | { 6159 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
| 10470 | { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10471 | { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10472 | { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10473 | { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT }, |
| 10474 | { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10475 | { 6172 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
| 10476 | { 6172 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10477 | { 6178 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10478 | { 6185 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10479 | { 6192 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
| 10480 | { 6192 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10481 | { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10482 | { 6199 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
| 10483 | { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10484 | { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10485 | { 6205 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
| 10486 | { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10487 | { 6211 /* mftr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 10488 | { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10489 | { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10490 | { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10491 | { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10492 | { 6228 /* min_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10493 | { 6236 /* min_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10494 | { 6244 /* min_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10495 | { 6252 /* min_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10496 | { 6260 /* min_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10497 | { 6268 /* min_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10498 | { 6276 /* min_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10499 | { 6284 /* min_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10500 | { 6292 /* min_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10501 | { 6300 /* min_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10502 | { 6308 /* min_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10503 | { 6316 /* min_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10504 | { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10505 | { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10506 | { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10507 | { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10508 | { 6338 /* mini_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10509 | { 6347 /* mini_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10510 | { 6356 /* mini_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10511 | { 6365 /* mini_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10512 | { 6374 /* mini_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10513 | { 6383 /* mini_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10514 | { 6392 /* mini_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10515 | { 6401 /* mini_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10516 | { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10517 | { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10518 | { 6414 /* mod_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10519 | { 6422 /* mod_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10520 | { 6430 /* mod_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10521 | { 6438 /* mod_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10522 | { 6446 /* mod_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10523 | { 6454 /* mod_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10524 | { 6462 /* mod_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10525 | { 6470 /* mod_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10526 | { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10527 | { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10528 | { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10529 | { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10530 | { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10531 | { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10532 | { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10533 | { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10534 | { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10535 | { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10536 | { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10537 | { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10538 | { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 10539 | { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 10540 | { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10541 | { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips }, |
| 10542 | { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips }, |
| 10543 | { 6507 /* move.v */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10544 | { 6514 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10545 | { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_NotMips32r6 }, |
| 10546 | { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_NotMips32r6 }, |
| 10547 | { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_NotMips32r6 }, |
| 10548 | { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 }, |
| 10549 | { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 }, |
| 10550 | { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 }, |
| 10551 | { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10552 | { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10553 | { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10554 | { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10555 | { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10556 | { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10557 | { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10558 | { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10559 | { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10560 | { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10561 | { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10562 | { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10563 | { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10564 | { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10565 | { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10566 | { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10567 | { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10568 | { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10569 | { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10570 | { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10571 | { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10572 | { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10573 | { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10574 | { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10575 | { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10576 | { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10577 | { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10578 | { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10579 | { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10580 | { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10581 | { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10582 | { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10583 | { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10584 | { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10585 | { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10586 | { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10587 | { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10588 | { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10589 | { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10590 | { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10591 | { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10592 | { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10593 | { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10594 | { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10595 | { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10596 | { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 10597 | { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10598 | { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10599 | { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10600 | { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10601 | { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10602 | { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 10603 | { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10604 | { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10605 | { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10606 | { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10607 | { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10608 | { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10609 | { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
| 10610 | { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10611 | { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
| 10612 | { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 }, |
| 10613 | { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10614 | { 6622 /* msub_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10615 | { 6631 /* msub_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10616 | { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10617 | { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10618 | { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10619 | { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10620 | { 6656 /* msubr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10621 | { 6666 /* msubr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10622 | { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10623 | { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10624 | { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10625 | { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10626 | { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10627 | { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10628 | { 6682 /* msubv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10629 | { 6690 /* msubv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10630 | { 6698 /* msubv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10631 | { 6706 /* msubv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10632 | { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10633 | { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10634 | { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10635 | { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10636 | { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10637 | { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10638 | { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10639 | { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10640 | { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10641 | { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10642 | { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10643 | { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10644 | { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10645 | { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10646 | { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10647 | { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10648 | { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10649 | { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10650 | { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10651 | { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10652 | { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10653 | { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10654 | { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10655 | { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10656 | { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10657 | { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10658 | { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10659 | { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10660 | { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10661 | { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10662 | { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10663 | { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10664 | { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10665 | { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10666 | { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10667 | { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10668 | { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10669 | { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10670 | { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10671 | { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10672 | { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10673 | { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10674 | { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10675 | { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10676 | { 6747 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10677 | { 6747 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10678 | { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10679 | { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10680 | { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10681 | { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10682 | { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10683 | { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips }, |
| 10684 | { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10685 | { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt }, |
| 10686 | { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10687 | { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10688 | { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10689 | { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10690 | { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10691 | { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP }, |
| 10692 | { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10693 | { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10694 | { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10695 | { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10696 | { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10697 | { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10698 | { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10699 | { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10700 | { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10701 | { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP }, |
| 10702 | { 6777 /* mtm0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 10703 | { 6782 /* mtm1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 10704 | { 6787 /* mtm2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 10705 | { 6792 /* mtp0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 10706 | { 6797 /* mtp1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 10707 | { 6802 /* mtp2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 10708 | { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10709 | { 6807 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
| 10710 | { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10711 | { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10712 | { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10713 | { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT }, |
| 10714 | { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10715 | { 6820 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
| 10716 | { 6820 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10717 | { 6826 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10718 | { 6833 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10719 | { 6840 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT }, |
| 10720 | { 6840 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10721 | { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10722 | { 6847 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
| 10723 | { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10724 | { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 10725 | { 6853 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT }, |
| 10726 | { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT }, |
| 10727 | { 6859 /* mttr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 10728 | { 6864 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10729 | { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10730 | { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10731 | { 6868 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10732 | { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10733 | { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10734 | { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10735 | { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10736 | { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10737 | { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10738 | { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10739 | { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10740 | { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10741 | { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10742 | { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10743 | { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10744 | { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10745 | { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10746 | { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10747 | { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10748 | { 6890 /* mul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10749 | { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 10750 | { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10751 | { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10752 | { 6903 /* mul_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10753 | { 6911 /* mul_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10754 | { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10755 | { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10756 | { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10757 | { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10758 | { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10759 | { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10760 | { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10761 | { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10762 | { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10763 | { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10764 | { 6986 /* mulo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10765 | { 6986 /* mulo */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10766 | { 6991 /* mulou */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10767 | { 6991 /* mulou */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10768 | { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10769 | { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10770 | { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10771 | { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10772 | { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10773 | { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10774 | { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10775 | { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10776 | { 7037 /* mulr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D }, |
| 10777 | { 7045 /* mulr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10778 | { 7054 /* mulr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10779 | { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10780 | { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10781 | { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 }, |
| 10782 | { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10783 | { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10784 | { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10785 | { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10786 | { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10787 | { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10788 | { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10789 | { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10790 | { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10791 | { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10792 | { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10793 | { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10794 | { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10795 | { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10796 | { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10797 | { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 10798 | { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10799 | { 7099 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10800 | { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10801 | { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10802 | { 7104 /* mulv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10803 | { 7111 /* mulv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10804 | { 7118 /* mulv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10805 | { 7125 /* mulv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10806 | { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10807 | { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10808 | { 7136 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10809 | { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10810 | { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10811 | { 7136 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10812 | { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10813 | { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10814 | { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 10815 | { 7140 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10816 | { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 10817 | { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat }, |
| 10818 | { 7146 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10819 | { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10820 | { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10821 | { 7152 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10822 | { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10823 | { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10824 | { 7152 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10825 | { 7157 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10826 | { 7164 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10827 | { 7171 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10828 | { 7178 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10829 | { 7185 /* nlzc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10830 | { 7192 /* nlzc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10831 | { 7199 /* nlzc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10832 | { 7206 /* nlzc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10833 | { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
| 10834 | { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10835 | { 7213 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
| 10836 | { 7221 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
| 10837 | { 7221 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10838 | { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
| 10839 | { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10840 | { 7229 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
| 10841 | { 7237 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips }, |
| 10842 | { 7237 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 }, |
| 10843 | { 7249 /* nor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit }, |
| 10844 | { 7249 /* nor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 10845 | { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10846 | { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10847 | { 7249 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10848 | { 7249 /* nor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit }, |
| 10849 | { 7249 /* nor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 10850 | { 7253 /* nor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10851 | { 7259 /* nori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10852 | { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10853 | { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10854 | { 7266 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10855 | { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10856 | { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10857 | { 7266 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10858 | { 7270 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10859 | { 7270 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10860 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10861 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10862 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10863 | { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10864 | { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 10865 | { 7276 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10866 | { 7276 /* or */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
| 10867 | { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10868 | { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10869 | { 7276 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10870 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10871 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 10872 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 10873 | { 7276 /* or */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
| 10874 | { 7279 /* or.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10875 | { 7284 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10876 | { 7284 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10877 | { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10878 | { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10879 | { 7289 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10880 | { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10881 | { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10882 | { 7289 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10883 | { 7293 /* ori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10884 | { 7299 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10885 | { 7299 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10886 | { 7315 /* pckev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10887 | { 7323 /* pckev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10888 | { 7331 /* pckev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10889 | { 7339 /* pckev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10890 | { 7347 /* pckod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10891 | { 7355 /* pckod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10892 | { 7363 /* pckod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10893 | { 7371 /* pckod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10894 | { 7379 /* pcnt.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10895 | { 7386 /* pcnt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10896 | { 7393 /* pcnt.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10897 | { 7400 /* pcnt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 10898 | { 7407 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10899 | { 7407 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10900 | { 7415 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10901 | { 7415 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10902 | { 7423 /* pll.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10903 | { 7430 /* plu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10904 | { 7437 /* pop */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasCnMips }, |
| 10905 | { 7437 /* pop */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasCnMips }, |
| 10906 | { 7441 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10907 | { 7441 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10908 | { 7454 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10909 | { 7454 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10910 | { 7467 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10911 | { 7467 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10912 | { 7482 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10913 | { 7482 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10914 | { 7498 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10915 | { 7498 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10916 | { 7513 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10917 | { 7513 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10918 | { 7529 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10919 | { 7529 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10920 | { 7543 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10921 | { 7543 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10922 | { 7558 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10923 | { 7558 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10924 | { 7572 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10925 | { 7572 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10926 | { 7587 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10927 | { 7587 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10928 | { 7599 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10929 | { 7599 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10930 | { 7614 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10931 | { 7614 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10932 | { 7631 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10933 | { 7631 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10934 | { 7643 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10935 | { 7643 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10936 | { 7656 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10937 | { 7656 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10938 | { 7671 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10939 | { 7671 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10940 | { 7687 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 10941 | { 7687 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 10942 | { 7687 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 10943 | { 7687 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
| 10944 | { 7692 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 10945 | { 7692 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 10946 | { 7698 /* prefx */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10947 | { 7704 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 10948 | { 7704 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 10949 | { 7712 /* pul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10950 | { 7719 /* puu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 10951 | { 7726 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10952 | { 7726 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10953 | { 7737 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10954 | { 7737 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10955 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10956 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10957 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10958 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10959 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10960 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10961 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 10962 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_IsGP64bit }, |
| 10963 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10964 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10965 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10966 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 10967 | { 7743 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10968 | { 7743 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 10969 | { 7749 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10970 | { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10971 | { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 10972 | { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10973 | { 7756 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 10974 | { 7764 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 10975 | { 7764 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 10976 | { 7772 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10977 | { 7772 /* rem */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10978 | { 7772 /* rem */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10979 | { 7772 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10980 | { 7776 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10981 | { 7776 /* remu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10982 | { 7776 /* remu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10983 | { 7776 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 10984 | { 7781 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10985 | { 7781 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10986 | { 7789 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10987 | { 7789 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10988 | { 7797 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10989 | { 7797 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10990 | { 7806 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 10991 | { 7806 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 10992 | { 7815 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10993 | { 7815 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10994 | { 7822 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 10995 | { 7822 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 10996 | { 7829 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10997 | { 7829 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10998 | { 7829 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 10999 | { 7829 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11000 | { 7833 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11001 | { 7833 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11002 | { 7833 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11003 | { 7833 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11004 | { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11005 | { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11006 | { 7837 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11007 | { 7837 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11008 | { 7837 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11009 | { 7842 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11010 | { 7842 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11011 | { 7848 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
| 11012 | { 7848 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11013 | { 7858 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11014 | { 7858 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11015 | { 7858 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11016 | { 7858 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11017 | { 7868 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11018 | { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11019 | { 7868 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11020 | { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11021 | { 7868 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11022 | { 7868 /* round.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11023 | { 7868 /* round.w.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11024 | { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11025 | { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11026 | { 7878 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11027 | { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 11028 | { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11029 | { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 11030 | { 7888 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 11031 | { 7896 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips }, |
| 11032 | { 7896 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11033 | { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
| 11034 | { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat }, |
| 11035 | { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
| 11036 | { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
| 11037 | { 7904 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
| 11038 | { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat }, |
| 11039 | { 7904 /* s.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
| 11040 | { 7904 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat }, |
| 11041 | { 7908 /* s.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
| 11042 | { 7908 /* s.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat }, |
| 11043 | { 7912 /* saa */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, |
| 11044 | { 7912 /* saa */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP }, |
| 11045 | { 7912 /* saa */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, |
| 11046 | { 7916 /* saad */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, |
| 11047 | { 7916 /* saad */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP }, |
| 11048 | { 7916 /* saad */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP }, |
| 11049 | { 7921 /* sat_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11050 | { 7929 /* sat_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11051 | { 7937 /* sat_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11052 | { 7945 /* sat_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11053 | { 7953 /* sat_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11054 | { 7961 /* sat_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11055 | { 7969 /* sat_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11056 | { 7977 /* sat_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11057 | { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11058 | { 7985 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11059 | { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11060 | { 7985 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
| 11061 | { 7985 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11062 | { 7985 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 11063 | { 7988 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, |
| 11064 | { 7988 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, |
| 11065 | { 7988 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, |
| 11066 | { 7988 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, |
| 11067 | { 7993 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11068 | { 7993 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11069 | { 7993 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 11070 | { 7993 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 11071 | { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
| 11072 | { 7997 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips }, |
| 11073 | { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
| 11074 | { 7997 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips }, |
| 11075 | { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11076 | { 7997 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 11077 | { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11078 | { 7997 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11079 | { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11080 | { 7997 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11081 | { 7997 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11082 | { 7997 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 11083 | { 8000 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 }, |
| 11084 | { 8000 /* scd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips32r6 }, |
| 11085 | { 8000 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 11086 | { 8000 /* scd */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 11087 | { 8004 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11088 | { 8004 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11089 | { 8004 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 11090 | { 8004 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 11091 | { 8008 /* sd */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 }, |
| 11092 | { 8008 /* sd */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 }, |
| 11093 | { 8008 /* sd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 11094 | { 8008 /* sd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips }, |
| 11095 | { 8025 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11096 | { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11097 | { 8025 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11098 | { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11099 | { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11100 | { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11101 | { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 11102 | { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat }, |
| 11103 | { 8025 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 11104 | { 8025 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 11105 | { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 11106 | { 8030 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 11107 | { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11108 | { 8030 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 11109 | { 8030 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11110 | { 8030 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11111 | { 8035 /* sdc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
| 11112 | { 8035 /* sdc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips }, |
| 11113 | { 8040 /* sdl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 11114 | { 8040 /* sdl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 11115 | { 8044 /* sdr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 11116 | { 8044 /* sdr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 }, |
| 11117 | { 8048 /* sdxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11118 | { 8048 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11119 | { 8048 /* sdxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 11120 | { 8048 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 11121 | { 8054 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11122 | { 8054 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11123 | { 8054 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11124 | { 8054 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11125 | { 8058 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11126 | { 8058 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11127 | { 8058 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11128 | { 8058 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11129 | { 8062 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 11130 | { 8062 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11131 | { 8068 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 11132 | { 8068 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11133 | { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
| 11134 | { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11135 | { 8074 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 }, |
| 11136 | { 8081 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 11137 | { 8081 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11138 | { 8090 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 11139 | { 8090 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11140 | { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips }, |
| 11141 | { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11142 | { 8099 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 }, |
| 11143 | { 8106 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 11144 | { 8106 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11145 | { 8115 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips }, |
| 11146 | { 8115 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11147 | { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11148 | { 8124 /* seq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11149 | { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11150 | { 8124 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11151 | { 8124 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11152 | { 8124 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11153 | { 8128 /* seqi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11154 | { 8128 /* seqi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11155 | { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11156 | { 8133 /* sge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11157 | { 8133 /* sge */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11158 | { 8133 /* sge */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11159 | { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11160 | { 8133 /* sge */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11161 | { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11162 | { 8137 /* sgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11163 | { 8137 /* sgeu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11164 | { 8137 /* sgeu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11165 | { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11166 | { 8137 /* sgeu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11167 | { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11168 | { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11169 | { 8142 /* sgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11170 | { 8142 /* sgt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11171 | { 8142 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11172 | { 8142 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11173 | { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11174 | { 8142 /* sgt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11175 | { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11176 | { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11177 | { 8146 /* sgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11178 | { 8146 /* sgtu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11179 | { 8146 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11180 | { 8146 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11181 | { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11182 | { 8146 /* sgtu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11183 | { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11184 | { 8151 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11185 | { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11186 | { 8151 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
| 11187 | { 8151 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11188 | { 8151 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 11189 | { 8154 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, |
| 11190 | { 8154 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, |
| 11191 | { 8154 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, |
| 11192 | { 8154 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, |
| 11193 | { 8159 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11194 | { 8159 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11195 | { 8159 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 11196 | { 8159 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 11197 | { 8163 /* shf.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11198 | { 8169 /* shf.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11199 | { 8175 /* shf.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11200 | { 8181 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11201 | { 8181 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 11202 | { 8187 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11203 | { 8187 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11204 | { 8187 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP }, |
| 11205 | { 8187 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11206 | { 8194 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11207 | { 8194 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11208 | { 8202 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11209 | { 8202 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11210 | { 8210 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11211 | { 8210 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11212 | { 8220 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11213 | { 8220 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11214 | { 8229 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11215 | { 8229 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11216 | { 8238 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11217 | { 8238 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11218 | { 8247 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11219 | { 8247 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11220 | { 8258 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11221 | { 8258 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11222 | { 8268 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11223 | { 8268 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11224 | { 8276 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11225 | { 8276 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11226 | { 8284 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11227 | { 8284 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11228 | { 8294 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11229 | { 8294 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11230 | { 8304 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11231 | { 8304 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11232 | { 8313 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11233 | { 8313 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11234 | { 8322 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11235 | { 8322 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11236 | { 8331 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11237 | { 8331 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11238 | { 8342 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11239 | { 8342 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11240 | { 8353 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11241 | { 8353 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11242 | { 8363 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11243 | { 8363 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11244 | { 8371 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11245 | { 8371 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11246 | { 8379 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11247 | { 8379 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11248 | { 8388 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11249 | { 8388 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11250 | { 8404 /* sld.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11251 | { 8404 /* sld.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11252 | { 8410 /* sld.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11253 | { 8410 /* sld.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11254 | { 8416 /* sld.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11255 | { 8416 /* sld.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11256 | { 8422 /* sld.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11257 | { 8422 /* sld.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11258 | { 8428 /* sldi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11259 | { 8435 /* sldi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11260 | { 8442 /* sldi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11261 | { 8449 /* sldi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11262 | { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11263 | { 8456 /* sle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11264 | { 8456 /* sle */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11265 | { 8456 /* sle */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11266 | { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11267 | { 8456 /* sle */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11268 | { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11269 | { 8460 /* sleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11270 | { 8460 /* sleu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11271 | { 8460 /* sleu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11272 | { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips }, |
| 11273 | { 8460 /* sleu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11274 | { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 11275 | { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11276 | { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11277 | { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11278 | { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11279 | { 8465 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11280 | { 8465 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 11281 | { 8465 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11282 | { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11283 | { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11284 | { 8465 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11285 | { 8469 /* sll.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11286 | { 8475 /* sll.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11287 | { 8481 /* sll.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11288 | { 8487 /* sll.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11289 | { 8493 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11290 | { 8493 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11291 | { 8499 /* slli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11292 | { 8506 /* slli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11293 | { 8513 /* slli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11294 | { 8520 /* slli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11295 | { 8527 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11296 | { 8527 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11297 | { 8532 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 11298 | { 8532 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11299 | { 8532 /* slt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11300 | { 8532 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11301 | { 8532 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11302 | { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 11303 | { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11304 | { 8532 /* slt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11305 | { 8536 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11306 | { 8536 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11307 | { 8541 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11308 | { 8541 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11309 | { 8547 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 11310 | { 8547 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11311 | { 8547 /* sltu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11312 | { 8547 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11313 | { 8547 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11314 | { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 11315 | { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11316 | { 8547 /* sltu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit }, |
| 11317 | { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11318 | { 8552 /* sne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11319 | { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11320 | { 8552 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11321 | { 8552 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips }, |
| 11322 | { 8552 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11323 | { 8556 /* snei */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11324 | { 8556 /* snei */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11325 | { 8561 /* splat.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11326 | { 8561 /* splat.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11327 | { 8569 /* splat.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11328 | { 8569 /* splat.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11329 | { 8577 /* splat.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11330 | { 8577 /* splat.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11331 | { 8585 /* splat.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11332 | { 8585 /* splat.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11333 | { 8593 /* splati.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11334 | { 8602 /* splati.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11335 | { 8611 /* splati.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11336 | { 8620 /* splati.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11337 | { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11338 | { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11339 | { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11340 | { 8629 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 11341 | { 8636 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11342 | { 8636 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11343 | { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 11344 | { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11345 | { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11346 | { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11347 | { 8643 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11348 | { 8643 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 11349 | { 8643 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11350 | { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11351 | { 8643 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11352 | { 8647 /* sra.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11353 | { 8653 /* sra.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11354 | { 8659 /* sra.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11355 | { 8665 /* sra.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11356 | { 8671 /* srai.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11357 | { 8678 /* srai.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11358 | { 8685 /* srai.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11359 | { 8692 /* srai.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11360 | { 8699 /* srar.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11361 | { 8706 /* srar.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11362 | { 8713 /* srar.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11363 | { 8720 /* srar.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11364 | { 8727 /* srari.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11365 | { 8735 /* srari.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11366 | { 8743 /* srari.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11367 | { 8751 /* srari.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11368 | { 8759 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11369 | { 8759 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11370 | { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 11371 | { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11372 | { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11373 | { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11374 | { 8764 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11375 | { 8764 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips }, |
| 11376 | { 8764 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11377 | { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11378 | { 8764 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11379 | { 8768 /* srl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11380 | { 8774 /* srl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11381 | { 8780 /* srl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11382 | { 8786 /* srl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11383 | { 8792 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11384 | { 8792 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11385 | { 8798 /* srli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11386 | { 8805 /* srli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11387 | { 8812 /* srli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11388 | { 8819 /* srli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11389 | { 8826 /* srlr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11390 | { 8833 /* srlr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11391 | { 8840 /* srlr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11392 | { 8847 /* srlr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11393 | { 8854 /* srlri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11394 | { 8862 /* srlri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11395 | { 8870 /* srlri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11396 | { 8878 /* srlri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11397 | { 8886 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11398 | { 8886 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11399 | { 8897 /* st.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11400 | { 8897 /* st.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA }, |
| 11401 | { 8902 /* st.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11402 | { 8902 /* st.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA }, |
| 11403 | { 8907 /* st.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11404 | { 8907 /* st.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA }, |
| 11405 | { 8912 /* st.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11406 | { 8912 /* st.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA }, |
| 11407 | { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11408 | { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11409 | { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11410 | { 8917 /* sub */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 11411 | { 8917 /* sub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 11412 | { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11413 | { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11414 | { 8917 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11415 | { 8917 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 11416 | { 8917 /* sub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 }, |
| 11417 | { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 11418 | { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11419 | { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips }, |
| 11420 | { 8921 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat }, |
| 11421 | { 8927 /* sub.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11422 | { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 11423 | { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11424 | { 8934 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11425 | { 8940 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11426 | { 8940 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11427 | { 8948 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11428 | { 8948 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11429 | { 8958 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11430 | { 8958 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11431 | { 8967 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11432 | { 8967 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11433 | { 8976 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11434 | { 8976 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11435 | { 8984 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11436 | { 8984 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11437 | { 8995 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11438 | { 8995 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11439 | { 9005 /* subs_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11440 | { 9014 /* subs_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11441 | { 9023 /* subs_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11442 | { 9032 /* subs_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11443 | { 9041 /* subs_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11444 | { 9050 /* subs_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11445 | { 9059 /* subs_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11446 | { 9068 /* subs_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11447 | { 9077 /* subsus_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11448 | { 9088 /* subsus_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11449 | { 9099 /* subsus_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11450 | { 9110 /* subsus_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11451 | { 9121 /* subsuu_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11452 | { 9132 /* subsuu_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11453 | { 9143 /* subsuu_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11454 | { 9154 /* subsuu_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11455 | { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11456 | { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11457 | { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11458 | { 9165 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11459 | { 9165 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None }, |
| 11460 | { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11461 | { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11462 | { 9165 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11463 | { 9165 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11464 | { 9165 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None }, |
| 11465 | { 9170 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11466 | { 9170 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11467 | { 9178 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11468 | { 9178 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11469 | { 9186 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11470 | { 9186 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11471 | { 9193 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11472 | { 9193 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11473 | { 9203 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11474 | { 9203 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP }, |
| 11475 | { 9213 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11476 | { 9213 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11477 | { 9222 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 }, |
| 11478 | { 9222 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 }, |
| 11479 | { 9233 /* subv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11480 | { 9240 /* subv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11481 | { 9247 /* subv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11482 | { 9254 /* subv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11483 | { 9261 /* subvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11484 | { 9269 /* subvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11485 | { 9277 /* subvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11486 | { 9285 /* subvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11487 | { 9293 /* suxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11488 | { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11489 | { 9293 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11490 | { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips }, |
| 11491 | { 9293 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 11492 | { 9293 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat }, |
| 11493 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11494 | { 9299 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_HasMips32r6 }, |
| 11495 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11496 | { 9299 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips }, |
| 11497 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11498 | { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11499 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP }, |
| 11500 | { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP }, |
| 11501 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11502 | { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP }, |
| 11503 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11504 | { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 }, |
| 11505 | { 9299 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11506 | { 9299 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 11507 | { 9302 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 }, |
| 11508 | { 9302 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 }, |
| 11509 | { 9302 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 }, |
| 11510 | { 9302 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 }, |
| 11511 | { 9307 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 11512 | { 9307 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips }, |
| 11513 | { 9307 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11514 | { 9307 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11515 | { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 11516 | { 9312 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips }, |
| 11517 | { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11518 | { 9312 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 11519 | { 9312 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11520 | { 9312 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11521 | { 9317 /* swc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
| 11522 | { 9317 /* swc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips }, |
| 11523 | { 9322 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11524 | { 9322 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips }, |
| 11525 | { 9322 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA }, |
| 11526 | { 9322 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA }, |
| 11527 | { 9326 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11528 | { 9326 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11529 | { 9326 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11530 | { 9326 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 11531 | { 9330 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 11532 | { 9330 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 11533 | { 9330 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 11534 | { 9330 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 11535 | { 9335 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 11536 | { 9335 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
| 11537 | { 9339 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 }, |
| 11538 | { 9339 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 }, |
| 11539 | { 9339 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 }, |
| 11540 | { 9339 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 }, |
| 11541 | { 9345 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips }, |
| 11542 | { 9345 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips }, |
| 11543 | { 9351 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11544 | { 9351 /* swp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips }, |
| 11545 | { 9355 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11546 | { 9355 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11547 | { 9355 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11548 | { 9355 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 }, |
| 11549 | { 9359 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 11550 | { 9359 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips }, |
| 11551 | { 9359 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 11552 | { 9359 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA }, |
| 11553 | { 9364 /* swsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11554 | { 9364 /* swsp */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_NotMips32r6 }, |
| 11555 | { 9369 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 11556 | { 9369 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat }, |
| 11557 | { 9369 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 11558 | { 9369 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat }, |
| 11559 | { 9380 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11560 | { 9380 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotMips32r6 }, |
| 11561 | { 9380 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 }, |
| 11562 | { 9424 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11563 | { 9424 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11564 | { 9424 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11565 | { 9424 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11566 | { 9428 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11567 | { 9428 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11568 | { 9433 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11569 | { 9433 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11570 | { 9433 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11571 | { 9433 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11572 | { 9437 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11573 | { 9437 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11574 | { 9442 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11575 | { 9442 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11576 | { 9448 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11577 | { 9448 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11578 | { 9448 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11579 | { 9448 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11580 | { 9533 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11581 | { 9533 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11582 | { 9533 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11583 | { 9533 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11584 | { 9537 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11585 | { 9537 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11586 | { 9542 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11587 | { 9542 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11588 | { 9548 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11589 | { 9548 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11590 | { 9548 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11591 | { 9548 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11592 | { 9553 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11593 | { 9553 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11594 | { 9553 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11595 | { 9553 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips }, |
| 11596 | { 9557 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips }, |
| 11597 | { 9557 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11598 | { 9562 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips }, |
| 11599 | { 9562 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11600 | { 9572 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11601 | { 9572 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11602 | { 9572 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11603 | { 9572 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11604 | { 9582 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11605 | { 9582 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11606 | { 9582 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11607 | { 9582 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat }, |
| 11608 | { 9582 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11609 | { 9582 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11610 | { 9582 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11611 | { 9582 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11612 | { 9582 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
| 11613 | { 9582 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
| 11614 | { 9582 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat }, |
| 11615 | { 9582 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
| 11616 | { 9582 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
| 11617 | { 9582 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat }, |
| 11618 | { 9592 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips }, |
| 11619 | { 9592 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat }, |
| 11620 | { 9592 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat }, |
| 11621 | { 9592 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None }, |
| 11622 | { 9592 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11623 | { 9602 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11624 | { 9602 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 11625 | { 9606 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11626 | { 9606 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 11627 | { 9611 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11628 | { 9611 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 11629 | { 9615 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11630 | { 9615 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 11631 | { 9619 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None }, |
| 11632 | { 9619 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None }, |
| 11633 | { 9623 /* v3mulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11634 | { 9623 /* v3mulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11635 | { 9630 /* vmm0 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11636 | { 9630 /* vmm0 */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11637 | { 9635 /* vmulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11638 | { 9635 /* vmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips }, |
| 11639 | { 9641 /* vshf.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11640 | { 9648 /* vshf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11641 | { 9655 /* vshf.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11642 | { 9662 /* vshf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11643 | { 9674 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips }, |
| 11644 | { 9674 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_InMicroMips }, |
| 11645 | { 9674 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP }, |
| 11646 | { 9674 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips }, |
| 11647 | { 9680 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11648 | { 9687 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips }, |
| 11649 | { 9687 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11650 | { 9687 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11651 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11652 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11653 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11654 | { 9692 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11655 | { 9692 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 11656 | { 9692 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11657 | { 9692 /* xor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
| 11658 | { 9692 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11659 | { 9692 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11660 | { 9692 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11661 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11662 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips }, |
| 11663 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips }, |
| 11664 | { 9692 /* xor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips }, |
| 11665 | { 9696 /* xor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11666 | { 9702 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11667 | { 9702 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11668 | { 9708 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11669 | { 9708 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11670 | { 9708 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11671 | { 9708 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 }, |
| 11672 | { 9708 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips }, |
| 11673 | { 9708 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 }, |
| 11674 | { 9713 /* xori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA }, |
| 11675 | { 9720 /* yield */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips }, |
| 11676 | { 9720 /* yield */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips }, |
| 11677 | }; |
| 11678 | |
| 11679 | ParseStatus MipsAsmParser:: |
| 11680 | tryCustomParseOperand(OperandVector &Operands, |
| 11681 | unsigned MCK) { |
| 11682 | |
| 11683 | switch(MCK) { |
| 11684 | case MCK_ACC64DSPAsmReg: |
| 11685 | return parseAnyRegister(Operands); |
| 11686 | case MCK_AFGR64AsmReg: |
| 11687 | return parseAnyRegister(Operands); |
| 11688 | case MCK_CCRAsmReg: |
| 11689 | return parseAnyRegister(Operands); |
| 11690 | case MCK_COP0AsmReg: |
| 11691 | return parseAnyRegister(Operands); |
| 11692 | case MCK_COP2AsmReg: |
| 11693 | return parseAnyRegister(Operands); |
| 11694 | case MCK_COP3AsmReg: |
| 11695 | return parseAnyRegister(Operands); |
| 11696 | case MCK_FCCAsmReg: |
| 11697 | return parseAnyRegister(Operands); |
| 11698 | case MCK_FGR32AsmReg: |
| 11699 | return parseAnyRegister(Operands); |
| 11700 | case MCK_FGR64AsmReg: |
| 11701 | return parseAnyRegister(Operands); |
| 11702 | case MCK_GPR32AsmReg: |
| 11703 | return parseAnyRegister(Operands); |
| 11704 | case MCK_GPR32NonZeroAsmReg: |
| 11705 | return parseAnyRegister(Operands); |
| 11706 | case MCK_GPR32ZeroAsmReg: |
| 11707 | return parseAnyRegister(Operands); |
| 11708 | case MCK_GPR64AsmReg: |
| 11709 | return parseAnyRegister(Operands); |
| 11710 | case MCK_GPRMM16AsmReg: |
| 11711 | return parseAnyRegister(Operands); |
| 11712 | case MCK_GPRMM16AsmRegMoveP: |
| 11713 | return parseAnyRegister(Operands); |
| 11714 | case MCK_GPRMM16AsmRegMovePPairFirst: |
| 11715 | return parseAnyRegister(Operands); |
| 11716 | case MCK_GPRMM16AsmRegMovePPairSecond: |
| 11717 | return parseAnyRegister(Operands); |
| 11718 | case MCK_GPRMM16AsmRegZero: |
| 11719 | return parseAnyRegister(Operands); |
| 11720 | case MCK_HI32DSPAsmReg: |
| 11721 | return parseAnyRegister(Operands); |
| 11722 | case MCK_HWRegsAsmReg: |
| 11723 | return parseAnyRegister(Operands); |
| 11724 | case MCK_LO32DSPAsmReg: |
| 11725 | return parseAnyRegister(Operands); |
| 11726 | case MCK_MSA128AsmReg: |
| 11727 | return parseAnyRegister(Operands); |
| 11728 | case MCK_MSACtrlAsmReg: |
| 11729 | return parseAnyRegister(Operands); |
| 11730 | case MCK_MicroMipsMemGP: |
| 11731 | return parseMemOperand(Operands); |
| 11732 | case MCK_MicroMipsMem: |
| 11733 | return parseMemOperand(Operands); |
| 11734 | case MCK_MicroMipsMemSP: |
| 11735 | return parseMemOperand(Operands); |
| 11736 | case MCK_InvNum: |
| 11737 | return parseInvNum(Operands); |
| 11738 | case MCK_JumpTarget: |
| 11739 | return parseJumpTarget(Operands); |
| 11740 | case MCK_MemOffsetSimmPtr: |
| 11741 | return parseMemOperand(Operands); |
| 11742 | case MCK_MemOffsetUimm4: |
| 11743 | return parseMemOperand(Operands); |
| 11744 | case MCK_MemOffsetSimm9_0: |
| 11745 | return parseMemOperand(Operands); |
| 11746 | case MCK_MemOffsetSimm10_0: |
| 11747 | return parseMemOperand(Operands); |
| 11748 | case MCK_MemOffsetSimm11_0: |
| 11749 | return parseMemOperand(Operands); |
| 11750 | case MCK_MemOffsetSimm12_0: |
| 11751 | return parseMemOperand(Operands); |
| 11752 | case MCK_MemOffsetSimm16_0: |
| 11753 | return parseMemOperand(Operands); |
| 11754 | case MCK_MemOffsetSimm10_1: |
| 11755 | return parseMemOperand(Operands); |
| 11756 | case MCK_MemOffsetSimm10_2: |
| 11757 | return parseMemOperand(Operands); |
| 11758 | case MCK_MemOffsetSimm10_3: |
| 11759 | return parseMemOperand(Operands); |
| 11760 | case MCK_Mem: |
| 11761 | return parseMemOperand(Operands); |
| 11762 | case MCK_RegList16: |
| 11763 | return parseRegisterList(Operands); |
| 11764 | case MCK_RegList: |
| 11765 | return parseRegisterList(Operands); |
| 11766 | case MCK_StrictlyAFGR64AsmReg: |
| 11767 | return parseAnyRegister(Operands); |
| 11768 | case MCK_StrictlyFGR32AsmReg: |
| 11769 | return parseAnyRegister(Operands); |
| 11770 | case MCK_StrictlyFGR64AsmReg: |
| 11771 | return parseAnyRegister(Operands); |
| 11772 | default: |
| 11773 | return ParseStatus::NoMatch; |
| 11774 | } |
| 11775 | return ParseStatus::NoMatch; |
| 11776 | } |
| 11777 | |
| 11778 | ParseStatus MipsAsmParser:: |
| 11779 | MatchOperandParserImpl(OperandVector &Operands, |
| 11780 | StringRef Mnemonic, |
| 11781 | bool ParseForAllFeatures) { |
| 11782 | // Get the current feature set. |
| 11783 | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); |
| 11784 | |
| 11785 | // Get the next operand index. |
| 11786 | unsigned NextOpNum = Operands.size() - 1; |
| 11787 | // Search the table. |
| 11788 | auto MnemonicRange = |
| 11789 | std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), |
| 11790 | Mnemonic, LessOpcodeOperand()); |
| 11791 | |
| 11792 | if (MnemonicRange.first == MnemonicRange.second) |
| 11793 | return ParseStatus::NoMatch; |
| 11794 | |
| 11795 | for (const OperandMatchEntry *it = MnemonicRange.first, |
| 11796 | *ie = MnemonicRange.second; it != ie; ++it) { |
| 11797 | // equal_range guarantees that instruction mnemonic matches. |
| 11798 | assert(Mnemonic == it->getMnemonic()); |
| 11799 | |
| 11800 | // check if the available features match |
| 11801 | const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; |
| 11802 | if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) |
| 11803 | continue; |
| 11804 | |
| 11805 | // check if the operand in question has a custom parser. |
| 11806 | if (!(it->OperandMask & (1 << NextOpNum))) |
| 11807 | continue; |
| 11808 | |
| 11809 | // call custom parse method to handle the operand |
| 11810 | ParseStatus Result = tryCustomParseOperand(Operands, it->Class); |
| 11811 | if (!Result.isNoMatch()) |
| 11812 | return Result; |
| 11813 | } |
| 11814 | |
| 11815 | // Okay, we had no match. |
| 11816 | return ParseStatus::NoMatch; |
| 11817 | } |
| 11818 | |
| 11819 | #endif // GET_MATCHER_IMPLEMENTATION |
| 11820 | |
| 11821 | |
| 11822 | #ifdef GET_MNEMONIC_SPELL_CHECKER |
| 11823 | #undef GET_MNEMONIC_SPELL_CHECKER |
| 11824 | |
| 11825 | static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { |
| 11826 | const unsigned MaxEditDist = 2; |
| 11827 | std::vector<StringRef> Candidates; |
| 11828 | StringRef Prev = ""; |
| 11829 | |
| 11830 | // Find the appropriate table for this asm variant. |
| 11831 | const MatchEntry *Start, *End; |
| 11832 | switch (VariantID) { |
| 11833 | default: llvm_unreachable("invalid variant!"); |
| 11834 | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
| 11835 | } |
| 11836 | |
| 11837 | for (auto I = Start; I < End; I++) { |
| 11838 | // Ignore unsupported instructions. |
| 11839 | const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; |
| 11840 | if ((FBS & RequiredFeatures) != RequiredFeatures) |
| 11841 | continue; |
| 11842 | |
| 11843 | StringRef T = I->getMnemonic(); |
| 11844 | // Avoid recomputing the edit distance for the same string. |
| 11845 | if (T == Prev) |
| 11846 | continue; |
| 11847 | |
| 11848 | Prev = T; |
| 11849 | unsigned Dist = S.edit_distance(T, false, MaxEditDist); |
| 11850 | if (Dist <= MaxEditDist) |
| 11851 | Candidates.push_back(T); |
| 11852 | } |
| 11853 | |
| 11854 | if (Candidates.empty()) |
| 11855 | return ""; |
| 11856 | |
| 11857 | std::string Res = ", did you mean: "; |
| 11858 | unsigned i = 0; |
| 11859 | for (; i < Candidates.size() - 1; i++) |
| 11860 | Res += Candidates[i].str() + ", "; |
| 11861 | return Res + Candidates[i].str() + "?"; |
| 11862 | } |
| 11863 | |
| 11864 | #endif // GET_MNEMONIC_SPELL_CHECKER |
| 11865 | |
| 11866 | |
| 11867 | #ifdef GET_MNEMONIC_CHECKER |
| 11868 | #undef GET_MNEMONIC_CHECKER |
| 11869 | |
| 11870 | static bool MipsCheckMnemonic(StringRef Mnemonic, |
| 11871 | const FeatureBitset &AvailableFeatures, |
| 11872 | unsigned VariantID) { |
| 11873 | // Find the appropriate table for this asm variant. |
| 11874 | const MatchEntry *Start, *End; |
| 11875 | switch (VariantID) { |
| 11876 | default: llvm_unreachable("invalid variant!"); |
| 11877 | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
| 11878 | } |
| 11879 | |
| 11880 | // Search the table. |
| 11881 | auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); |
| 11882 | |
| 11883 | if (MnemonicRange.first == MnemonicRange.second) |
| 11884 | return false; |
| 11885 | |
| 11886 | for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; |
| 11887 | it != ie; ++it) { |
| 11888 | const FeatureBitset &RequiredFeatures = |
| 11889 | FeatureBitsets[it->RequiredFeaturesIdx]; |
| 11890 | if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures) |
| 11891 | return true; |
| 11892 | } |
| 11893 | return false; |
| 11894 | } |
| 11895 | |
| 11896 | #endif // GET_MNEMONIC_CHECKER |
| 11897 | |
| 11898 |
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