1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 44;
11using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 mutable MatcherState State;
16 typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
19 static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 const uint8_t *getMatchTable() const override;
25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
26 bool testSimplePredicate(unsigned PredicateID) const override;
27 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
28#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
29
30#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
31, State(0),
32ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
33#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
34
35#ifdef GET_GLOBALISEL_IMPL
36// LLT Objects.
37enum {
38 GILLT_s16,
39 GILLT_s32,
40 GILLT_s64,
41 GILLT_v2s16,
42 GILLT_v2s64,
43 GILLT_v4s8,
44 GILLT_v4s32,
45 GILLT_v8s16,
46 GILLT_v16s8,
47};
48const static size_t NumTypeObjects = 9;
49const static LLT TypeObjects[] = {
50 LLT::scalar(16),
51 LLT::scalar(32),
52 LLT::scalar(64),
53 LLT::vector(ElementCount::getFixed(2), 16),
54 LLT::vector(ElementCount::getFixed(2), 64),
55 LLT::vector(ElementCount::getFixed(4), 8),
56 LLT::vector(ElementCount::getFixed(4), 32),
57 LLT::vector(ElementCount::getFixed(8), 16),
58 LLT::vector(ElementCount::getFixed(16), 8),
59};
60
61// Bits for subtarget features that participate in instruction matching.
62enum SubtargetFeatureBits : uint8_t {
63 Feature_HasMips2Bit = 7,
64 Feature_HasMips3Bit = 17,
65 Feature_HasMips4_32Bit = 27,
66 Feature_NotMips4_32Bit = 28,
67 Feature_HasMips4_32r2Bit = 18,
68 Feature_HasMips32Bit = 3,
69 Feature_HasMips32r2Bit = 6,
70 Feature_HasMips32r6Bit = 29,
71 Feature_NotMips32r6Bit = 4,
72 Feature_IsGP64bitBit = 22,
73 Feature_IsPTR64bitBit = 24,
74 Feature_HasMips64Bit = 25,
75 Feature_HasMips64r2Bit = 23,
76 Feature_HasMips64r6Bit = 30,
77 Feature_NotMips64r6Bit = 5,
78 Feature_InMips16ModeBit = 31,
79 Feature_NotInMips16ModeBit = 0,
80 Feature_HasCnMipsBit = 26,
81 Feature_NotCnMipsBit = 8,
82 Feature_IsSym32Bit = 38,
83 Feature_IsSym64Bit = 39,
84 Feature_IsN64Bit = 40,
85 Feature_RelocNotPICBit = 9,
86 Feature_RelocPICBit = 37,
87 Feature_NoNaNsFPMathBit = 21,
88 Feature_UseAbsBit = 14,
89 Feature_HasStdEncBit = 1,
90 Feature_NotDSPBit = 11,
91 Feature_InMicroMipsBit = 35,
92 Feature_NotInMicroMipsBit = 2,
93 Feature_IsLEBit = 42,
94 Feature_IsBEBit = 43,
95 Feature_IsNotNaClBit = 19,
96 Feature_HasEVABit = 36,
97 Feature_HasMSABit = 34,
98 Feature_HasMadd4Bit = 20,
99 Feature_UseIndirectJumpsHazardBit = 12,
100 Feature_NoIndirectJumpGuardsBit = 10,
101 Feature_AllowFPOpFusionBit = 41,
102 Feature_IsFP64bitBit = 16,
103 Feature_NotFP64bitBit = 15,
104 Feature_IsNotSoftFloatBit = 13,
105 Feature_HasDSPBit = 32,
106 Feature_HasDSPR2Bit = 33,
107};
108
109PredicateBitset MipsInstructionSelector::
110computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
111 PredicateBitset Features{};
112 if (Subtarget->hasMips2())
113 Features.set(Feature_HasMips2Bit);
114 if (Subtarget->hasMips3())
115 Features.set(Feature_HasMips3Bit);
116 if (Subtarget->hasMips4_32())
117 Features.set(Feature_HasMips4_32Bit);
118 if (!Subtarget->hasMips4_32())
119 Features.set(Feature_NotMips4_32Bit);
120 if (Subtarget->hasMips4_32r2())
121 Features.set(Feature_HasMips4_32r2Bit);
122 if (Subtarget->hasMips32())
123 Features.set(Feature_HasMips32Bit);
124 if (Subtarget->hasMips32r2())
125 Features.set(Feature_HasMips32r2Bit);
126 if (Subtarget->hasMips32r6())
127 Features.set(Feature_HasMips32r6Bit);
128 if (!Subtarget->hasMips32r6())
129 Features.set(Feature_NotMips32r6Bit);
130 if (Subtarget->isGP64bit())
131 Features.set(Feature_IsGP64bitBit);
132 if (Subtarget->isABI_N64())
133 Features.set(Feature_IsPTR64bitBit);
134 if (Subtarget->hasMips64())
135 Features.set(Feature_HasMips64Bit);
136 if (Subtarget->hasMips64r2())
137 Features.set(Feature_HasMips64r2Bit);
138 if (Subtarget->hasMips64r6())
139 Features.set(Feature_HasMips64r6Bit);
140 if (!Subtarget->hasMips64r6())
141 Features.set(Feature_NotMips64r6Bit);
142 if (Subtarget->inMips16Mode())
143 Features.set(Feature_InMips16ModeBit);
144 if (!Subtarget->inMips16Mode())
145 Features.set(Feature_NotInMips16ModeBit);
146 if (Subtarget->hasCnMips())
147 Features.set(Feature_HasCnMipsBit);
148 if (!Subtarget->hasCnMips())
149 Features.set(Feature_NotCnMipsBit);
150 if (Subtarget->hasSym32())
151 Features.set(Feature_IsSym32Bit);
152 if (!Subtarget->hasSym32())
153 Features.set(Feature_IsSym64Bit);
154 if (Subtarget->isABI_N64())
155 Features.set(Feature_IsN64Bit);
156 if (!TM.isPositionIndependent())
157 Features.set(Feature_RelocNotPICBit);
158 if (TM.isPositionIndependent())
159 Features.set(Feature_RelocPICBit);
160 if (TM.Options.NoNaNsFPMath)
161 Features.set(Feature_NoNaNsFPMathBit);
162 if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
163 Features.set(Feature_UseAbsBit);
164 if (Subtarget->hasStandardEncoding())
165 Features.set(Feature_HasStdEncBit);
166 if (!Subtarget->hasDSP())
167 Features.set(Feature_NotDSPBit);
168 if (Subtarget->inMicroMipsMode())
169 Features.set(Feature_InMicroMipsBit);
170 if (!Subtarget->inMicroMipsMode())
171 Features.set(Feature_NotInMicroMipsBit);
172 if (Subtarget->isLittle())
173 Features.set(Feature_IsLEBit);
174 if (!Subtarget->isLittle())
175 Features.set(Feature_IsBEBit);
176 if (!Subtarget->isTargetNaCl())
177 Features.set(Feature_IsNotNaClBit);
178 if (Subtarget->hasEVA())
179 Features.set(Feature_HasEVABit);
180 if (Subtarget->hasMSA())
181 Features.set(Feature_HasMSABit);
182 if (!Subtarget->disableMadd4())
183 Features.set(Feature_HasMadd4Bit);
184 if (Subtarget->useIndirectJumpsHazard())
185 Features.set(Feature_UseIndirectJumpsHazardBit);
186 if (!Subtarget->useIndirectJumpsHazard())
187 Features.set(Feature_NoIndirectJumpGuardsBit);
188 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
189 Features.set(Feature_AllowFPOpFusionBit);
190 if (Subtarget->isFP64bit())
191 Features.set(Feature_IsFP64bitBit);
192 if (!Subtarget->isFP64bit())
193 Features.set(Feature_NotFP64bitBit);
194 if (!Subtarget->useSoftFloat())
195 Features.set(Feature_IsNotSoftFloatBit);
196 if (Subtarget->hasDSP())
197 Features.set(Feature_HasDSPBit);
198 if (Subtarget->hasDSPR2())
199 Features.set(Feature_HasDSPR2Bit);
200 return Features;
201}
202
203void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
204 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
205}
206PredicateBitset MipsInstructionSelector::
207computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
208 PredicateBitset Features{};
209 return Features;
210}
211
212// Feature bitsets.
213enum {
214 GIFBS_Invalid,
215 GIFBS_HasCnMips,
216 GIFBS_HasDSP,
217 GIFBS_HasDSPR2,
218 GIFBS_HasMSA,
219 GIFBS_InMicroMips,
220 GIFBS_InMips16Mode,
221 GIFBS_IsFP64bit,
222 GIFBS_NotFP64bit,
223 GIFBS_HasDSP_InMicroMips,
224 GIFBS_HasDSP_NotInMicroMips,
225 GIFBS_HasDSPR2_InMicroMips,
226 GIFBS_HasMSA_HasStdEnc,
227 GIFBS_HasMSA_IsBE,
228 GIFBS_HasMSA_IsLE,
229 GIFBS_HasMips32r6_HasStdEnc,
230 GIFBS_HasMips32r6_InMicroMips,
231 GIFBS_HasMips64r2_HasStdEnc,
232 GIFBS_HasMips64r6_HasStdEnc,
233 GIFBS_HasStdEnc_IsNotSoftFloat,
234 GIFBS_HasStdEnc_NotInMicroMips,
235 GIFBS_HasStdEnc_NotMips4_32,
236 GIFBS_InMicroMips_IsFP64bit,
237 GIFBS_InMicroMips_IsNotSoftFloat,
238 GIFBS_InMicroMips_NotFP64bit,
239 GIFBS_InMicroMips_NotMips32r6,
240 GIFBS_IsGP64bit_NotInMips16Mode,
241 GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
242 GIFBS_HasMSA_HasMips64_HasStdEnc,
243 GIFBS_HasMips3_HasStdEnc_IsGP64bit,
244 GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
245 GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
246 GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
247 GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
248 GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
249 GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
250 GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
251 GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
252 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
253 GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
254 GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
255 GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
256 GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
257 GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
258 GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
259 GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
260 GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
261 GIFBS_InMicroMips_NotMips32r6_RelocPIC,
262 GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
263 GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
264 GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6,
265 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
266 GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
267 GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
268 GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
269 GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
270 GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
271 GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
272 GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
273 GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
274 GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
275 GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6,
276 GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
277 GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
278 GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
279 GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
280 GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
281 GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
282 GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
283 GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
284 GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
285 GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
286 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
287 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
288 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
289 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
290 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
291 GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
292};
293constexpr static PredicateBitset FeatureBitsets[] {
294 {}, // GIFBS_Invalid
295 {Feature_HasCnMipsBit, },
296 {Feature_HasDSPBit, },
297 {Feature_HasDSPR2Bit, },
298 {Feature_HasMSABit, },
299 {Feature_InMicroMipsBit, },
300 {Feature_InMips16ModeBit, },
301 {Feature_IsFP64bitBit, },
302 {Feature_NotFP64bitBit, },
303 {Feature_HasDSPBit, Feature_InMicroMipsBit, },
304 {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
305 {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
306 {Feature_HasMSABit, Feature_HasStdEncBit, },
307 {Feature_HasMSABit, Feature_IsBEBit, },
308 {Feature_HasMSABit, Feature_IsLEBit, },
309 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
310 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
311 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
312 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
313 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
314 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
315 {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
316 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
317 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
318 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
319 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
320 {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
321 {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
322 {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
323 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
324 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
325 {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
326 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
327 {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
328 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
329 {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
330 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
331 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
332 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
333 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
334 {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
335 {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
336 {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
337 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
338 {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
339 {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
340 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
341 {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
342 {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
343 {Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
344 {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, },
345 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
346 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
347 {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
348 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
349 {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
350 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
351 {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
352 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
353 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
354 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
355 {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
356 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
357 {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
358 {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
359 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
360 {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
361 {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
362 {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
363 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
364 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
365 {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
366 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
367 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
368 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
369 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
370 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
371 {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
372};
373
374// ComplexPattern predicates.
375enum {
376 GICP_Invalid,
377};
378// See constructor for table contents
379
380MipsInstructionSelector::ComplexMatcherMemFn
381MipsInstructionSelector::ComplexPredicateFns[] = {
382 nullptr, // GICP_Invalid
383};
384
385// PatFrag predicates.
386bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
387 const MachineFunction &MF = *MI.getParent()->getParent();
388 const MachineRegisterInfo &MRI = MF.getRegInfo();
389 const auto &Operands = State.RecordedOperands;
390 (void)Operands;
391 (void)MRI;
392 llvm_unreachable("Unknown predicate");
393 return false;
394}
395// PatFrag predicates.
396enum {
397 GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
398 GICXXPred_I64_Predicate_immSExt6,
399 GICXXPred_I64_Predicate_immSExt10,
400 GICXXPred_I64_Predicate_immSExtAddiur2,
401 GICXXPred_I64_Predicate_immSExtAddius5,
402 GICXXPred_I64_Predicate_immZExt1,
403 GICXXPred_I64_Predicate_immZExt1Ptr,
404 GICXXPred_I64_Predicate_immZExt2,
405 GICXXPred_I64_Predicate_immZExt2Lsa,
406 GICXXPred_I64_Predicate_immZExt2Ptr,
407 GICXXPred_I64_Predicate_immZExt2Shift,
408 GICXXPred_I64_Predicate_immZExt3,
409 GICXXPred_I64_Predicate_immZExt3Ptr,
410 GICXXPred_I64_Predicate_immZExt4,
411 GICXXPred_I64_Predicate_immZExt4Ptr,
412 GICXXPred_I64_Predicate_immZExt5,
413 GICXXPred_I64_Predicate_immZExt5_64,
414 GICXXPred_I64_Predicate_immZExt6,
415 GICXXPred_I64_Predicate_immZExt8,
416 GICXXPred_I64_Predicate_immZExt10,
417 GICXXPred_I64_Predicate_immZExtAndi16,
418 GICXXPred_I64_Predicate_immi32Cst7,
419 GICXXPred_I64_Predicate_immi32Cst15,
420 GICXXPred_I64_Predicate_immi32Cst31,
421 GICXXPred_I64_Predicate_timmSExt6,
422 GICXXPred_I64_Predicate_timmZExt1,
423 GICXXPred_I64_Predicate_timmZExt1Ptr,
424 GICXXPred_I64_Predicate_timmZExt2,
425 GICXXPred_I64_Predicate_timmZExt2Ptr,
426 GICXXPred_I64_Predicate_timmZExt3,
427 GICXXPred_I64_Predicate_timmZExt3Ptr,
428 GICXXPred_I64_Predicate_timmZExt4,
429 GICXXPred_I64_Predicate_timmZExt4Ptr,
430 GICXXPred_I64_Predicate_timmZExt5,
431 GICXXPred_I64_Predicate_timmZExt6,
432 GICXXPred_I64_Predicate_timmZExt8,
433 GICXXPred_I64_Predicate_timmZExt10,
434};
435bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
436 switch (PredicateID) {
437 case GICXXPred_I64_Predicate_immLi16: {
438 return Imm >= -1 && Imm <= 126;
439 }
440 case GICXXPred_I64_Predicate_immSExt6: {
441 return isInt<6>(Imm);
442 }
443 case GICXXPred_I64_Predicate_immSExt10: {
444 return isInt<10>(Imm);
445 }
446 case GICXXPred_I64_Predicate_immSExtAddiur2: {
447 return Imm == 1 || Imm == -1 ||
448 ((Imm % 4 == 0) &&
449 Imm < 28 && Imm > 0);
450 }
451 case GICXXPred_I64_Predicate_immSExtAddius5: {
452 return Imm >= -8 && Imm <= 7;
453 }
454 case GICXXPred_I64_Predicate_immZExt1: {
455 return isUInt<1>(Imm);
456 }
457 case GICXXPred_I64_Predicate_immZExt1Ptr: {
458 return isUInt<1>(Imm);
459 }
460 case GICXXPred_I64_Predicate_immZExt2: {
461 return isUInt<2>(Imm);
462 }
463 case GICXXPred_I64_Predicate_immZExt2Lsa: {
464 return isUInt<2>(Imm - 1);
465 }
466 case GICXXPred_I64_Predicate_immZExt2Ptr: {
467 return isUInt<2>(Imm);
468 }
469 case GICXXPred_I64_Predicate_immZExt2Shift: {
470 return Imm >= 1 && Imm <= 8;
471 }
472 case GICXXPred_I64_Predicate_immZExt3: {
473 return isUInt<3>(Imm);
474 }
475 case GICXXPred_I64_Predicate_immZExt3Ptr: {
476 return isUInt<3>(Imm);
477 }
478 case GICXXPred_I64_Predicate_immZExt4: {
479 return isUInt<4>(Imm);
480 }
481 case GICXXPred_I64_Predicate_immZExt4Ptr: {
482 return isUInt<4>(Imm);
483 }
484 case GICXXPred_I64_Predicate_immZExt5: {
485 return Imm == (Imm & 0x1f);
486 }
487 case GICXXPred_I64_Predicate_immZExt5_64: {
488 return Imm == (Imm & 0x1f);
489 }
490 case GICXXPred_I64_Predicate_immZExt6: {
491 return Imm == (Imm & 0x3f);
492 }
493 case GICXXPred_I64_Predicate_immZExt8: {
494 return isUInt<8>(Imm);
495 }
496 case GICXXPred_I64_Predicate_immZExt10: {
497 return isUInt<10>(Imm);
498 }
499 case GICXXPred_I64_Predicate_immZExtAndi16: {
500 return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
501 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
502 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
503 }
504 case GICXXPred_I64_Predicate_immi32Cst7: {
505 return isUInt<32>(Imm) && Imm == 7;
506 }
507 case GICXXPred_I64_Predicate_immi32Cst15: {
508 return isUInt<32>(Imm) && Imm == 15;
509 }
510 case GICXXPred_I64_Predicate_immi32Cst31: {
511 return isUInt<32>(Imm) && Imm == 31;
512 }
513 case GICXXPred_I64_Predicate_timmSExt6: {
514 return isInt<6>(Imm);
515 }
516 case GICXXPred_I64_Predicate_timmZExt1: {
517 return isUInt<1>(Imm);
518 }
519 case GICXXPred_I64_Predicate_timmZExt1Ptr: {
520 return isUInt<1>(Imm);
521 }
522 case GICXXPred_I64_Predicate_timmZExt2: {
523 return isUInt<2>(Imm);
524 }
525 case GICXXPred_I64_Predicate_timmZExt2Ptr: {
526 return isUInt<2>(Imm);
527 }
528 case GICXXPred_I64_Predicate_timmZExt3: {
529 return isUInt<3>(Imm);
530 }
531 case GICXXPred_I64_Predicate_timmZExt3Ptr: {
532 return isUInt<3>(Imm);
533 }
534 case GICXXPred_I64_Predicate_timmZExt4: {
535 return isUInt<4>(Imm);
536 }
537 case GICXXPred_I64_Predicate_timmZExt4Ptr: {
538 return isUInt<4>(Imm);
539 }
540 case GICXXPred_I64_Predicate_timmZExt5: {
541 return Imm == (Imm & 0x1f);
542 }
543 case GICXXPred_I64_Predicate_timmZExt6: {
544 return Imm == (Imm & 0x3f);
545 }
546 case GICXXPred_I64_Predicate_timmZExt8: {
547 return isUInt<8>(Imm);
548 }
549 case GICXXPred_I64_Predicate_timmZExt10: {
550 return isUInt<10>(Imm);
551 }
552 }
553 llvm_unreachable("Unknown predicate");
554 return false;
555}
556// PatFrag predicates.
557bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
558 llvm_unreachable("Unknown predicate");
559 return false;
560}
561// PatFrag predicates.
562enum {
563 GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
564 GICXXPred_APInt_Predicate_imm32ZExt16,
565};
566bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
567 switch (PredicateID) {
568 case GICXXPred_APInt_Predicate_imm32SExt16: {
569 return isInt<16>(Imm.getSExtValue());
570 }
571 case GICXXPred_APInt_Predicate_imm32ZExt16: {
572
573 return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
574
575 }
576 }
577 llvm_unreachable("Unknown predicate");
578 return false;
579}
580bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
581 llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
582 return false;
583}
584// Custom renderers.
585enum {
586 GICR_Invalid,
587};
588MipsInstructionSelector::CustomRendererFn
589MipsInstructionSelector::CustomRenderers[] = {
590 nullptr, // GICR_Invalid
591};
592
593bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
594 const PredicateBitset AvailableFeatures = getAvailableFeatures();
595 MachineIRBuilder B(I);
596 State.MIs.clear();
597 State.MIs.push_back(&I);
598
599 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
600 return true;
601 }
602
603 return false;
604}
605
606bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
607 llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
608}
609#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
610#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
611#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
612#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
613#else
614#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
615#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
616#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
617#endif
618const uint8_t *MipsInstructionSelector::getMatchTable() const {
619 constexpr static uint8_t MatchTable0[] = {
620 GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(51), GIMT_Encode2(274), /*)*//*default:*//*Label 64*/ GIMT_Encode4(66615),
621 /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(902),
622 /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2200),
623 /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2891),
624 /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3372),
625 /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3641),
626 /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(3910),
627 /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4179), GIMT_Encode4(0), GIMT_Encode4(0),
628 /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4448),
629 /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5004),
630 /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5408), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
631 /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6300),
632 /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6373), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
633 /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6714), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
634 /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(10905),
635 /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(10970),
636 /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(11038), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
637 /*TargetOpcode::G_BRCOND*//*Label 16*/ GIMT_Encode4(11106), GIMT_Encode4(0), GIMT_Encode4(0),
638 /*TargetOpcode::G_INTRINSIC*//*Label 17*/ GIMT_Encode4(15827),
639 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 18*/ GIMT_Encode4(30092), GIMT_Encode4(0), GIMT_Encode4(0),
640 /*TargetOpcode::G_ANYEXT*//*Label 19*/ GIMT_Encode4(34750),
641 /*TargetOpcode::G_TRUNC*//*Label 20*/ GIMT_Encode4(34816),
642 /*TargetOpcode::G_CONSTANT*//*Label 21*/ GIMT_Encode4(34880), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
643 /*TargetOpcode::G_SEXT*//*Label 22*/ GIMT_Encode4(34941), GIMT_Encode4(0),
644 /*TargetOpcode::G_ZEXT*//*Label 23*/ GIMT_Encode4(36405),
645 /*TargetOpcode::G_SHL*//*Label 24*/ GIMT_Encode4(36606),
646 /*TargetOpcode::G_LSHR*//*Label 25*/ GIMT_Encode4(38403),
647 /*TargetOpcode::G_ASHR*//*Label 26*/ GIMT_Encode4(40200), GIMT_Encode4(0), GIMT_Encode4(0),
648 /*TargetOpcode::G_ROTR*//*Label 27*/ GIMT_Encode4(41955), GIMT_Encode4(0),
649 /*TargetOpcode::G_ICMP*//*Label 28*/ GIMT_Encode4(42243),
650 /*TargetOpcode::G_FCMP*//*Label 29*/ GIMT_Encode4(44774), GIMT_Encode4(0), GIMT_Encode4(0),
651 /*TargetOpcode::G_SELECT*//*Label 30*/ GIMT_Encode4(46480), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
652 /*TargetOpcode::G_UMULH*//*Label 31*/ GIMT_Encode4(58518),
653 /*TargetOpcode::G_SMULH*//*Label 32*/ GIMT_Encode4(58627), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
654 /*TargetOpcode::G_FADD*//*Label 33*/ GIMT_Encode4(58736),
655 /*TargetOpcode::G_FSUB*//*Label 34*/ GIMT_Encode4(59649),
656 /*TargetOpcode::G_FMUL*//*Label 35*/ GIMT_Encode4(60261),
657 /*TargetOpcode::G_FMA*//*Label 36*/ GIMT_Encode4(60748), GIMT_Encode4(0),
658 /*TargetOpcode::G_FDIV*//*Label 37*/ GIMT_Encode4(60854), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
659 /*TargetOpcode::G_FEXP2*//*Label 38*/ GIMT_Encode4(61153), GIMT_Encode4(0), GIMT_Encode4(0),
660 /*TargetOpcode::G_FLOG2*//*Label 39*/ GIMT_Encode4(61231), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
661 /*TargetOpcode::G_FNEG*//*Label 40*/ GIMT_Encode4(61309),
662 /*TargetOpcode::G_FPEXT*//*Label 41*/ GIMT_Encode4(62678),
663 /*TargetOpcode::G_FPTRUNC*//*Label 42*/ GIMT_Encode4(62856),
664 /*TargetOpcode::G_FPTOSI*//*Label 43*/ GIMT_Encode4(63019),
665 /*TargetOpcode::G_FPTOUI*//*Label 44*/ GIMT_Encode4(63097),
666 /*TargetOpcode::G_SITOFP*//*Label 45*/ GIMT_Encode4(63175),
667 /*TargetOpcode::G_UITOFP*//*Label 46*/ GIMT_Encode4(63428),
668 /*TargetOpcode::G_FABS*//*Label 47*/ GIMT_Encode4(63506), GIMT_Encode4(0), GIMT_Encode4(0),
669 /*TargetOpcode::G_FCANONICALIZE*//*Label 48*/ GIMT_Encode4(63746), GIMT_Encode4(0), GIMT_Encode4(0),
670 /*TargetOpcode::G_FMINNUM_IEEE*//*Label 49*/ GIMT_Encode4(63820),
671 /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 50*/ GIMT_Encode4(63892), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
672 /*TargetOpcode::G_SMIN*//*Label 51*/ GIMT_Encode4(63964),
673 /*TargetOpcode::G_SMAX*//*Label 52*/ GIMT_Encode4(64132),
674 /*TargetOpcode::G_UMIN*//*Label 53*/ GIMT_Encode4(64300),
675 /*TargetOpcode::G_UMAX*//*Label 54*/ GIMT_Encode4(64468), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
676 /*TargetOpcode::G_BR*//*Label 55*/ GIMT_Encode4(64636), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
677 /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 56*/ GIMT_Encode4(64760),
678 /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 57*/ GIMT_Encode4(65324), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
679 /*TargetOpcode::G_CTLZ*//*Label 58*/ GIMT_Encode4(65376), GIMT_Encode4(0),
680 /*TargetOpcode::G_CTPOP*//*Label 59*/ GIMT_Encode4(65881),
681 /*TargetOpcode::G_BSWAP*//*Label 60*/ GIMT_Encode4(66087), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
682 /*TargetOpcode::G_FSQRT*//*Label 61*/ GIMT_Encode4(66251), GIMT_Encode4(0),
683 /*TargetOpcode::G_FRINT*//*Label 62*/ GIMT_Encode4(66491), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
684 /*TargetOpcode::G_TRAP*//*Label 63*/ GIMT_Encode4(66569),
685 // Label 0: @902
686 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 73*/ GIMT_Encode4(2199),
687 /*GILLT_s32*//*Label 65*/ GIMT_Encode4(945),
688 /*GILLT_s64*//*Label 66*/ GIMT_Encode4(1353),
689 /*GILLT_v2s16*//*Label 67*/ GIMT_Encode4(1519),
690 /*GILLT_v2s64*//*Label 68*/ GIMT_Encode4(1551),
691 /*GILLT_v4s8*//*Label 69*/ GIMT_Encode4(1705),
692 /*GILLT_v4s32*//*Label 70*/ GIMT_Encode4(1737),
693 /*GILLT_v8s16*//*Label 71*/ GIMT_Encode4(1891),
694 /*GILLT_v16s8*//*Label 72*/ GIMT_Encode4(2045),
695 // Label 65: @945
696 GIM_Try, /*On fail goto*//*Label 74*/ GIMT_Encode4(1352),
697 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
698 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
699 GIM_Try, /*On fail goto*//*Label 75*/ GIMT_Encode4(1023), // Rule ID 2372 //
700 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
702 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
703 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
704 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
705 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
706 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
707 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
708 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
709 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
710 // MIs[2] Operand 1
711 // No operand predicates
712 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
713 GIM_CheckIsSafeToFold, /*NumInsns*/2,
714 // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
718 GIR_RootToRootCopy, /*OpIdx*/2, // rt
719 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
720 GIR_RootConstrainSelectedInstOperands,
721 // GIR_Coverage, 2372,
722 GIR_EraseRootFromParent_Done,
723 // Label 75: @1023
724 GIM_Try, /*On fail goto*//*Label 76*/ GIMT_Encode4(1090), // Rule ID 834 //
725 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
726 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
727 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
728 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
729 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
730 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
732 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
733 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
734 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
735 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
736 // MIs[2] Operand 1
737 // No operand predicates
738 GIM_CheckIsSafeToFold, /*NumInsns*/2,
739 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
740 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
741 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
743 GIR_RootToRootCopy, /*OpIdx*/1, // rt
744 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
745 GIR_RootConstrainSelectedInstOperands,
746 // GIR_Coverage, 834,
747 GIR_EraseRootFromParent_Done,
748 // Label 76: @1090
749 GIM_Try, /*On fail goto*//*Label 77*/ GIMT_Encode4(1132), // Rule ID 40 //
750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
751 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
752 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
753 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
754 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
755 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
756 // MIs[1] Operand 1
757 // No operand predicates
758 GIM_CheckIsSafeToFold, /*NumInsns*/1,
759 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
762 GIR_RootToRootCopy, /*OpIdx*/1, // rs
763 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
764 GIR_RootConstrainSelectedInstOperands,
765 // GIR_Coverage, 40,
766 GIR_EraseRootFromParent_Done,
767 // Label 77: @1132
768 GIM_Try, /*On fail goto*//*Label 78*/ GIMT_Encode4(1174), // Rule ID 2141 //
769 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
770 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
771 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
773 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
774 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
775 // MIs[1] Operand 1
776 // No operand predicates
777 GIM_CheckIsSafeToFold, /*NumInsns*/1,
778 // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
779 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
780 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
781 GIR_RootToRootCopy, /*OpIdx*/1, // src
782 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
783 GIR_RootConstrainSelectedInstOperands,
784 // GIR_Coverage, 2141,
785 GIR_EraseRootFromParent_Done,
786 // Label 78: @1174
787 GIM_Try, /*On fail goto*//*Label 79*/ GIMT_Encode4(1216), // Rule ID 2142 //
788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
789 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
790 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
791 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
792 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
793 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
794 // MIs[1] Operand 1
795 // No operand predicates
796 GIM_CheckIsSafeToFold, /*NumInsns*/1,
797 // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
799 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
800 GIR_RootToRootCopy, /*OpIdx*/1, // src
801 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
802 GIR_RootConstrainSelectedInstOperands,
803 // GIR_Coverage, 2142,
804 GIR_EraseRootFromParent_Done,
805 // Label 79: @1216
806 GIM_Try, /*On fail goto*//*Label 80*/ GIMT_Encode4(1243), // Rule ID 1208 //
807 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
808 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
809 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
810 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
811 // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
813 GIR_RootConstrainSelectedInstOperands,
814 // GIR_Coverage, 1208,
815 GIR_Done,
816 // Label 80: @1243
817 GIM_Try, /*On fail goto*//*Label 81*/ GIMT_Encode4(1270), // Rule ID 46 //
818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
820 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
821 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
822 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
824 GIR_RootConstrainSelectedInstOperands,
825 // GIR_Coverage, 46,
826 GIR_Done,
827 // Label 81: @1270
828 GIM_Try, /*On fail goto*//*Label 82*/ GIMT_Encode4(1297), // Rule ID 1060 //
829 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
830 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
831 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
832 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
833 // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
834 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
835 GIR_RootConstrainSelectedInstOperands,
836 // GIR_Coverage, 1060,
837 GIR_Done,
838 // Label 82: @1297
839 GIM_Try, /*On fail goto*//*Label 83*/ GIMT_Encode4(1324), // Rule ID 1072 //
840 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
842 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
843 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
844 // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
845 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
846 GIR_RootConstrainSelectedInstOperands,
847 // GIR_Coverage, 1072,
848 GIR_Done,
849 // Label 83: @1324
850 GIM_Try, /*On fail goto*//*Label 84*/ GIMT_Encode4(1351), // Rule ID 1801 //
851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
852 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
853 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
854 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
855 // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
856 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
857 GIR_RootConstrainSelectedInstOperands,
858 // GIR_Coverage, 1801,
859 GIR_Done,
860 // Label 84: @1351
861 GIM_Reject,
862 // Label 74: @1352
863 GIM_Reject,
864 // Label 66: @1353
865 GIM_Try, /*On fail goto*//*Label 85*/ GIMT_Encode4(1518),
866 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
867 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
868 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
869 GIM_Try, /*On fail goto*//*Label 86*/ GIMT_Encode4(1431), // Rule ID 2373 //
870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
871 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
872 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
873 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
874 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
875 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
876 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
877 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
878 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
879 // MIs[2] Operand 1
880 // No operand predicates
881 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
882 GIM_CheckIsSafeToFold, /*NumInsns*/2,
883 // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
884 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
885 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
887 GIR_RootToRootCopy, /*OpIdx*/2, // rt
888 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
889 GIR_RootConstrainSelectedInstOperands,
890 // GIR_Coverage, 2373,
891 GIR_EraseRootFromParent_Done,
892 // Label 86: @1431
893 GIM_Try, /*On fail goto*//*Label 87*/ GIMT_Encode4(1494), // Rule ID 835 //
894 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
895 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
896 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
897 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
898 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
899 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
900 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
901 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
902 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
903 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
904 // MIs[2] Operand 1
905 // No operand predicates
906 GIM_CheckIsSafeToFold, /*NumInsns*/2,
907 // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
908 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
909 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
910 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
911 GIR_RootToRootCopy, /*OpIdx*/1, // rt
912 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
913 GIR_RootConstrainSelectedInstOperands,
914 // GIR_Coverage, 835,
915 GIR_EraseRootFromParent_Done,
916 // Label 87: @1494
917 GIM_Try, /*On fail goto*//*Label 88*/ GIMT_Encode4(1517), // Rule ID 202 //
918 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
919 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
920 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
921 // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
922 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
923 GIR_RootConstrainSelectedInstOperands,
924 // GIR_Coverage, 202,
925 GIR_Done,
926 // Label 88: @1517
927 GIM_Reject,
928 // Label 85: @1518
929 GIM_Reject,
930 // Label 67: @1519
931 GIM_Try, /*On fail goto*//*Label 89*/ GIMT_Encode4(1550), // Rule ID 1900 //
932 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
933 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
934 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
936 // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
937 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
938 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
939 GIR_RootConstrainSelectedInstOperands,
940 // GIR_Coverage, 1900,
941 GIR_Done,
942 // Label 89: @1550
943 GIM_Reject,
944 // Label 68: @1551
945 GIM_Try, /*On fail goto*//*Label 90*/ GIMT_Encode4(1704),
946 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
947 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
948 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
949 GIM_Try, /*On fail goto*//*Label 91*/ GIMT_Encode4(1623), // Rule ID 2377 //
950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
951 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
952 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
953 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
954 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
955 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
956 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
957 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
958 GIM_CheckIsSafeToFold, /*NumInsns*/1,
959 // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
960 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
961 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
962 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
965 GIR_RootConstrainSelectedInstOperands,
966 // GIR_Coverage, 2377,
967 GIR_EraseRootFromParent_Done,
968 // Label 91: @1623
969 GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(1680), // Rule ID 843 //
970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
971 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
972 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
973 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
974 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
975 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
976 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
977 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
978 GIM_CheckIsSafeToFold, /*NumInsns*/1,
979 // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
980 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
981 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
982 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
985 GIR_RootConstrainSelectedInstOperands,
986 // GIR_Coverage, 843,
987 GIR_EraseRootFromParent_Done,
988 // Label 92: @1680
989 GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1703), // Rule ID 510 //
990 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
991 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
992 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
993 // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
994 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
995 GIR_RootConstrainSelectedInstOperands,
996 // GIR_Coverage, 510,
997 GIR_Done,
998 // Label 93: @1703
999 GIM_Reject,
1000 // Label 90: @1704
1001 GIM_Reject,
1002 // Label 69: @1705
1003 GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1736), // Rule ID 1906 //
1004 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1005 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1006 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1007 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1008 // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
1010 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
1011 GIR_RootConstrainSelectedInstOperands,
1012 // GIR_Coverage, 1906,
1013 GIR_Done,
1014 // Label 94: @1736
1015 GIM_Reject,
1016 // Label 70: @1737
1017 GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1890),
1018 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1019 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1021 GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1809), // Rule ID 2376 //
1022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1023 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1024 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1025 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1026 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1027 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1028 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1029 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1030 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1031 // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1032 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1033 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1034 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1037 GIR_RootConstrainSelectedInstOperands,
1038 // GIR_Coverage, 2376,
1039 GIR_EraseRootFromParent_Done,
1040 // Label 96: @1809
1041 GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1866), // Rule ID 842 //
1042 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1043 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1044 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1045 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1046 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1047 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1048 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1049 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1050 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1051 // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1052 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
1053 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1054 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1057 GIR_RootConstrainSelectedInstOperands,
1058 // GIR_Coverage, 842,
1059 GIR_EraseRootFromParent_Done,
1060 // Label 97: @1866
1061 GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1889), // Rule ID 509 //
1062 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1063 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1064 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1065 // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1066 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
1067 GIR_RootConstrainSelectedInstOperands,
1068 // GIR_Coverage, 509,
1069 GIR_Done,
1070 // Label 98: @1889
1071 GIM_Reject,
1072 // Label 95: @1890
1073 GIM_Reject,
1074 // Label 71: @1891
1075 GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(2044),
1076 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1077 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1079 GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1963), // Rule ID 2375 //
1080 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1081 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1082 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1083 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1084 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1085 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1086 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1087 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1088 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1089 // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1090 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1091 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1092 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1095 GIR_RootConstrainSelectedInstOperands,
1096 // GIR_Coverage, 2375,
1097 GIR_EraseRootFromParent_Done,
1098 // Label 100: @1963
1099 GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(2020), // Rule ID 841 //
1100 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1101 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1102 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1103 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1104 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1105 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1106 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1107 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1108 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1109 // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
1111 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1112 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1113 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1114 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1115 GIR_RootConstrainSelectedInstOperands,
1116 // GIR_Coverage, 841,
1117 GIR_EraseRootFromParent_Done,
1118 // Label 101: @2020
1119 GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(2043), // Rule ID 508 //
1120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1121 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1122 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1123 // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
1125 GIR_RootConstrainSelectedInstOperands,
1126 // GIR_Coverage, 508,
1127 GIR_Done,
1128 // Label 102: @2043
1129 GIM_Reject,
1130 // Label 99: @2044
1131 GIM_Reject,
1132 // Label 72: @2045
1133 GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(2198),
1134 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1135 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1136 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1137 GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(2117), // Rule ID 2374 //
1138 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1140 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1141 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1142 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1143 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1144 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1145 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1146 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1147 // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1148 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1149 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1150 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
1151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1153 GIR_RootConstrainSelectedInstOperands,
1154 // GIR_Coverage, 2374,
1155 GIR_EraseRootFromParent_Done,
1156 // Label 104: @2117
1157 GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(2174), // Rule ID 840 //
1158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1159 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1160 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1161 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1162 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1163 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1164 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1165 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1166 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1167 // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1168 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
1169 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1170 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1172 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1173 GIR_RootConstrainSelectedInstOperands,
1174 // GIR_Coverage, 840,
1175 GIR_EraseRootFromParent_Done,
1176 // Label 105: @2174
1177 GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(2197), // Rule ID 507 //
1178 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1179 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1180 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1181 // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1182 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
1183 GIR_RootConstrainSelectedInstOperands,
1184 // GIR_Coverage, 507,
1185 GIR_Done,
1186 // Label 106: @2197
1187 GIM_Reject,
1188 // Label 103: @2198
1189 GIM_Reject,
1190 // Label 73: @2199
1191 GIM_Reject,
1192 // Label 1: @2200
1193 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 115*/ GIMT_Encode4(2890),
1194 /*GILLT_s32*//*Label 107*/ GIMT_Encode4(2243),
1195 /*GILLT_s64*//*Label 108*/ GIMT_Encode4(2420),
1196 /*GILLT_v2s16*//*Label 109*/ GIMT_Encode4(2454),
1197 /*GILLT_v2s64*//*Label 110*/ GIMT_Encode4(2486),
1198 /*GILLT_v4s8*//*Label 111*/ GIMT_Encode4(2579),
1199 /*GILLT_v4s32*//*Label 112*/ GIMT_Encode4(2611),
1200 /*GILLT_v8s16*//*Label 113*/ GIMT_Encode4(2704),
1201 /*GILLT_v16s8*//*Label 114*/ GIMT_Encode4(2797),
1202 // Label 107: @2243
1203 GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2419),
1204 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1205 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1206 GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(2283), // Rule ID 1800 //
1207 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1208 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1209 GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
1210 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1211 // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
1212 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
1213 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
1214 GIR_RootToRootCopy, /*OpIdx*/2, // r
1215 GIR_RootConstrainSelectedInstOperands,
1216 // GIR_Coverage, 1800,
1217 GIR_EraseRootFromParent_Done,
1218 // Label 117: @2283
1219 GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(2310), // Rule ID 1210 //
1220 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1222 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1223 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1224 // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1225 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
1226 GIR_RootConstrainSelectedInstOperands,
1227 // GIR_Coverage, 1210,
1228 GIR_Done,
1229 // Label 118: @2310
1230 GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2337), // Rule ID 47 //
1231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
1232 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1233 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1234 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1235 // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1236 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
1237 GIR_RootConstrainSelectedInstOperands,
1238 // GIR_Coverage, 47,
1239 GIR_Done,
1240 // Label 119: @2337
1241 GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2364), // Rule ID 1064 //
1242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1243 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1244 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1245 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
1246 // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
1247 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
1248 GIR_RootConstrainSelectedInstOperands,
1249 // GIR_Coverage, 1064,
1250 GIR_Done,
1251 // Label 120: @2364
1252 GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2391), // Rule ID 1073 //
1253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1254 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1255 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1257 // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1258 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
1259 GIR_RootConstrainSelectedInstOperands,
1260 // GIR_Coverage, 1073,
1261 GIR_Done,
1262 // Label 121: @2391
1263 GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2418), // Rule ID 1805 //
1264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1266 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1267 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1268 // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1269 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
1270 GIR_RootConstrainSelectedInstOperands,
1271 // GIR_Coverage, 1805,
1272 GIR_Done,
1273 // Label 122: @2418
1274 GIM_Reject,
1275 // Label 116: @2419
1276 GIM_Reject,
1277 // Label 108: @2420
1278 GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(2453), // Rule ID 203 //
1279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
1280 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1281 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1283 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1284 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1285 // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1286 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
1287 GIR_RootConstrainSelectedInstOperands,
1288 // GIR_Coverage, 203,
1289 GIR_Done,
1290 // Label 123: @2453
1291 GIM_Reject,
1292 // Label 109: @2454
1293 GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(2485), // Rule ID 1902 //
1294 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1295 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1296 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1298 // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1299 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
1300 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
1301 GIR_RootConstrainSelectedInstOperands,
1302 // GIR_Coverage, 1902,
1303 GIR_Done,
1304 // Label 124: @2485
1305 GIM_Reject,
1306 // Label 110: @2486
1307 GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(2578),
1308 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1309 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1310 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1311 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1312 GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(2558), // Rule ID 899 //
1313 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1314 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1315 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1316 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
1317 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
1318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1319 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1320 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1321 // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
1323 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1324 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1327 GIR_RootConstrainSelectedInstOperands,
1328 // GIR_Coverage, 899,
1329 GIR_EraseRootFromParent_Done,
1330 // Label 126: @2558
1331 GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(2577), // Rule ID 1028 //
1332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1333 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1334 // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1335 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
1336 GIR_RootConstrainSelectedInstOperands,
1337 // GIR_Coverage, 1028,
1338 GIR_Done,
1339 // Label 127: @2577
1340 GIM_Reject,
1341 // Label 125: @2578
1342 GIM_Reject,
1343 // Label 111: @2579
1344 GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(2610), // Rule ID 1908 //
1345 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
1346 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
1347 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
1348 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1349 // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
1350 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
1351 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
1352 GIR_RootConstrainSelectedInstOperands,
1353 // GIR_Coverage, 1908,
1354 GIR_Done,
1355 // Label 128: @2610
1356 GIM_Reject,
1357 // Label 112: @2611
1358 GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(2703),
1359 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1360 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1361 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1362 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1363 GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(2683), // Rule ID 898 //
1364 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1365 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1366 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1367 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1368 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
1369 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1370 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1371 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1372 // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1373 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
1374 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1375 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1378 GIR_RootConstrainSelectedInstOperands,
1379 // GIR_Coverage, 898,
1380 GIR_EraseRootFromParent_Done,
1381 // Label 130: @2683
1382 GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(2702), // Rule ID 1027 //
1383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1384 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1385 // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1386 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
1387 GIR_RootConstrainSelectedInstOperands,
1388 // GIR_Coverage, 1027,
1389 GIR_Done,
1390 // Label 131: @2702
1391 GIM_Reject,
1392 // Label 129: @2703
1393 GIM_Reject,
1394 // Label 113: @2704
1395 GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(2796),
1396 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1397 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1399 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1400 GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(2776), // Rule ID 897 //
1401 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1402 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1403 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1404 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
1405 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
1406 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1407 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1408 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1409 // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1410 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
1411 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1412 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1415 GIR_RootConstrainSelectedInstOperands,
1416 // GIR_Coverage, 897,
1417 GIR_EraseRootFromParent_Done,
1418 // Label 133: @2776
1419 GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(2795), // Rule ID 1026 //
1420 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1421 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1422 // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1423 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
1424 GIR_RootConstrainSelectedInstOperands,
1425 // GIR_Coverage, 1026,
1426 GIR_Done,
1427 // Label 134: @2795
1428 GIM_Reject,
1429 // Label 132: @2796
1430 GIM_Reject,
1431 // Label 114: @2797
1432 GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(2889),
1433 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1434 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1436 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1437 GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(2869), // Rule ID 896 //
1438 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1439 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1440 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1441 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
1442 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
1443 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1444 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1445 GIM_CheckIsSafeToFold, /*NumInsns*/1,
1446 // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
1448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
1449 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
1450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
1451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
1452 GIR_RootConstrainSelectedInstOperands,
1453 // GIR_Coverage, 896,
1454 GIR_EraseRootFromParent_Done,
1455 // Label 136: @2869
1456 GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(2888), // Rule ID 1025 //
1457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1458 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1459 // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
1461 GIR_RootConstrainSelectedInstOperands,
1462 // GIR_Coverage, 1025,
1463 GIR_Done,
1464 // Label 137: @2888
1465 GIM_Reject,
1466 // Label 135: @2889
1467 GIM_Reject,
1468 // Label 115: @2890
1469 GIM_Reject,
1470 // Label 2: @2891
1471 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 145*/ GIMT_Encode4(3371),
1472 /*GILLT_s32*//*Label 138*/ GIMT_Encode4(2934),
1473 /*GILLT_s64*//*Label 139*/ GIMT_Encode4(3118),
1474 /*GILLT_v2s16*//*Label 140*/ GIMT_Encode4(3203),
1475 /*GILLT_v2s64*//*Label 141*/ GIMT_Encode4(3235), GIMT_Encode4(0),
1476 /*GILLT_v4s32*//*Label 142*/ GIMT_Encode4(3269),
1477 /*GILLT_v8s16*//*Label 143*/ GIMT_Encode4(3303),
1478 /*GILLT_v16s8*//*Label 144*/ GIMT_Encode4(3337),
1479 // Label 138: @2934
1480 GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(3117),
1481 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1482 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1483 GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2984), // Rule ID 48 //
1484 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
1485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1486 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1487 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1488 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1489 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
1490 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1491 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1492 GIR_RootConstrainSelectedInstOperands,
1493 // GIR_Coverage, 48,
1494 GIR_Done,
1495 // Label 147: @2984
1496 GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(3011), // Rule ID 332 //
1497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1498 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1499 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1500 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1501 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
1503 GIR_RootConstrainSelectedInstOperands,
1504 // GIR_Coverage, 332,
1505 GIR_Done,
1506 // Label 148: @3011
1507 GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(3050), // Rule ID 1074 //
1508 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
1509 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1510 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1512 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1513 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
1514 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1515 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1516 GIR_RootConstrainSelectedInstOperands,
1517 // GIR_Coverage, 1074,
1518 GIR_Done,
1519 // Label 149: @3050
1520 GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(3077), // Rule ID 1179 //
1521 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1522 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1523 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1524 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1525 // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1526 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
1527 GIR_RootConstrainSelectedInstOperands,
1528 // GIR_Coverage, 1179,
1529 GIR_Done,
1530 // Label 150: @3077
1531 GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(3116), // Rule ID 1803 //
1532 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
1533 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1534 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1535 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
1536 // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
1537 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
1538 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1539 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1540 GIR_RootConstrainSelectedInstOperands,
1541 // GIR_Coverage, 1803,
1542 GIR_Done,
1543 // Label 151: @3116
1544 GIM_Reject,
1545 // Label 146: @3117
1546 GIM_Reject,
1547 // Label 139: @3118
1548 GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(3202),
1549 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1550 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1551 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1552 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1553 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1554 GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(3186), // Rule ID 274 //
1555 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
1556 // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1557 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
1558 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
1559 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
1560 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(RegState::Dead),
1561 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(RegState::Dead),
1562 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(RegState::Dead),
1563 GIR_RootConstrainSelectedInstOperands,
1564 // GIR_Coverage, 274,
1565 GIR_Done,
1566 // Label 153: @3186
1567 GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(3201), // Rule ID 347 //
1568 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1569 // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1570 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
1571 GIR_RootConstrainSelectedInstOperands,
1572 // GIR_Coverage, 347,
1573 GIR_Done,
1574 // Label 154: @3201
1575 GIM_Reject,
1576 // Label 152: @3202
1577 GIM_Reject,
1578 // Label 140: @3203
1579 GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(3234), // Rule ID 1904 //
1580 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
1581 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
1582 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
1583 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
1584 // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
1585 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
1586 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(RegState::Dead),
1587 GIR_RootConstrainSelectedInstOperands,
1588 // GIR_Coverage, 1904,
1589 GIR_Done,
1590 // Label 155: @3234
1591 GIM_Reject,
1592 // Label 141: @3235
1593 GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(3268), // Rule ID 907 //
1594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1595 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1598 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1599 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1600 // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1601 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
1602 GIR_RootConstrainSelectedInstOperands,
1603 // GIR_Coverage, 907,
1604 GIR_Done,
1605 // Label 156: @3268
1606 GIM_Reject,
1607 // Label 142: @3269
1608 GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(3302), // Rule ID 906 //
1609 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1610 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1613 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1614 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1615 // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1616 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
1617 GIR_RootConstrainSelectedInstOperands,
1618 // GIR_Coverage, 906,
1619 GIR_Done,
1620 // Label 157: @3302
1621 GIM_Reject,
1622 // Label 143: @3303
1623 GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(3336), // Rule ID 905 //
1624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1625 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1626 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1628 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1629 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1630 // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1631 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
1632 GIR_RootConstrainSelectedInstOperands,
1633 // GIR_Coverage, 905,
1634 GIR_Done,
1635 // Label 158: @3336
1636 GIM_Reject,
1637 // Label 144: @3337
1638 GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(3370), // Rule ID 904 //
1639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1640 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1641 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1643 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1644 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1645 // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
1647 GIR_RootConstrainSelectedInstOperands,
1648 // GIR_Coverage, 904,
1649 GIR_Done,
1650 // Label 159: @3370
1651 GIM_Reject,
1652 // Label 145: @3371
1653 GIM_Reject,
1654 // Label 3: @3372
1655 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 166*/ GIMT_Encode4(3640),
1656 /*GILLT_s32*//*Label 160*/ GIMT_Encode4(3415),
1657 /*GILLT_s64*//*Label 161*/ GIMT_Encode4(3470), GIMT_Encode4(0),
1658 /*GILLT_v2s64*//*Label 162*/ GIMT_Encode4(3504), GIMT_Encode4(0),
1659 /*GILLT_v4s32*//*Label 163*/ GIMT_Encode4(3538),
1660 /*GILLT_v8s16*//*Label 164*/ GIMT_Encode4(3572),
1661 /*GILLT_v16s8*//*Label 165*/ GIMT_Encode4(3606),
1662 // Label 160: @3415
1663 GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3469),
1664 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1665 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1666 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1667 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1668 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1669 GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3453), // Rule ID 326 //
1670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1671 // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1672 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
1673 GIR_RootConstrainSelectedInstOperands,
1674 // GIR_Coverage, 326,
1675 GIR_Done,
1676 // Label 168: @3453
1677 GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(3468), // Rule ID 1172 //
1678 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1679 // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1680 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
1681 GIR_RootConstrainSelectedInstOperands,
1682 // GIR_Coverage, 1172,
1683 GIR_Done,
1684 // Label 169: @3468
1685 GIM_Reject,
1686 // Label 167: @3469
1687 GIM_Reject,
1688 // Label 161: @3470
1689 GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3503), // Rule ID 341 //
1690 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1691 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1692 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1693 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1694 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1695 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1696 // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1697 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
1698 GIR_RootConstrainSelectedInstOperands,
1699 // GIR_Coverage, 341,
1700 GIR_Done,
1701 // Label 170: @3503
1702 GIM_Reject,
1703 // Label 162: @3504
1704 GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3537), // Rule ID 647 //
1705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1706 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1707 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1709 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1710 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1711 // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1712 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
1713 GIR_RootConstrainSelectedInstOperands,
1714 // GIR_Coverage, 647,
1715 GIR_Done,
1716 // Label 171: @3537
1717 GIM_Reject,
1718 // Label 163: @3538
1719 GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3571), // Rule ID 646 //
1720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1721 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1722 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1724 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1725 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1726 // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1727 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
1728 GIR_RootConstrainSelectedInstOperands,
1729 // GIR_Coverage, 646,
1730 GIR_Done,
1731 // Label 172: @3571
1732 GIM_Reject,
1733 // Label 164: @3572
1734 GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3605), // Rule ID 645 //
1735 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1736 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1737 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1738 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1739 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1740 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1741 // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1742 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
1743 GIR_RootConstrainSelectedInstOperands,
1744 // GIR_Coverage, 645,
1745 GIR_Done,
1746 // Label 173: @3605
1747 GIM_Reject,
1748 // Label 165: @3606
1749 GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3639), // Rule ID 644 //
1750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1751 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1752 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1753 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1754 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1755 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1756 // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1757 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
1758 GIR_RootConstrainSelectedInstOperands,
1759 // GIR_Coverage, 644,
1760 GIR_Done,
1761 // Label 174: @3639
1762 GIM_Reject,
1763 // Label 166: @3640
1764 GIM_Reject,
1765 // Label 4: @3641
1766 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 181*/ GIMT_Encode4(3909),
1767 /*GILLT_s32*//*Label 175*/ GIMT_Encode4(3684),
1768 /*GILLT_s64*//*Label 176*/ GIMT_Encode4(3739), GIMT_Encode4(0),
1769 /*GILLT_v2s64*//*Label 177*/ GIMT_Encode4(3773), GIMT_Encode4(0),
1770 /*GILLT_v4s32*//*Label 178*/ GIMT_Encode4(3807),
1771 /*GILLT_v8s16*//*Label 179*/ GIMT_Encode4(3841),
1772 /*GILLT_v16s8*//*Label 180*/ GIMT_Encode4(3875),
1773 // Label 175: @3684
1774 GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(3738),
1775 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1776 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1778 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1779 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1780 GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(3722), // Rule ID 327 //
1781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1782 // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1783 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
1784 GIR_RootConstrainSelectedInstOperands,
1785 // GIR_Coverage, 327,
1786 GIR_Done,
1787 // Label 183: @3722
1788 GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(3737), // Rule ID 1173 //
1789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1790 // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1791 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
1792 GIR_RootConstrainSelectedInstOperands,
1793 // GIR_Coverage, 1173,
1794 GIR_Done,
1795 // Label 184: @3737
1796 GIM_Reject,
1797 // Label 182: @3738
1798 GIM_Reject,
1799 // Label 176: @3739
1800 GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(3772), // Rule ID 342 //
1801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1802 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1803 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1804 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1805 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1806 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1807 // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1808 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
1809 GIR_RootConstrainSelectedInstOperands,
1810 // GIR_Coverage, 342,
1811 GIR_Done,
1812 // Label 185: @3772
1813 GIM_Reject,
1814 // Label 177: @3773
1815 GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(3806), // Rule ID 651 //
1816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1817 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1818 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1820 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1821 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1822 // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1823 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
1824 GIR_RootConstrainSelectedInstOperands,
1825 // GIR_Coverage, 651,
1826 GIR_Done,
1827 // Label 186: @3806
1828 GIM_Reject,
1829 // Label 178: @3807
1830 GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(3840), // Rule ID 650 //
1831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1832 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1833 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1835 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1836 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1837 // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1838 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
1839 GIR_RootConstrainSelectedInstOperands,
1840 // GIR_Coverage, 650,
1841 GIR_Done,
1842 // Label 187: @3840
1843 GIM_Reject,
1844 // Label 179: @3841
1845 GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(3874), // Rule ID 649 //
1846 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1847 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1848 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1849 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1850 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1851 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1852 // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1853 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
1854 GIR_RootConstrainSelectedInstOperands,
1855 // GIR_Coverage, 649,
1856 GIR_Done,
1857 // Label 188: @3874
1858 GIM_Reject,
1859 // Label 180: @3875
1860 GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3908), // Rule ID 648 //
1861 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1862 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1863 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1866 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1867 // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
1869 GIR_RootConstrainSelectedInstOperands,
1870 // GIR_Coverage, 648,
1871 GIR_Done,
1872 // Label 189: @3908
1873 GIM_Reject,
1874 // Label 181: @3909
1875 GIM_Reject,
1876 // Label 5: @3910
1877 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 196*/ GIMT_Encode4(4178),
1878 /*GILLT_s32*//*Label 190*/ GIMT_Encode4(3953),
1879 /*GILLT_s64*//*Label 191*/ GIMT_Encode4(4008), GIMT_Encode4(0),
1880 /*GILLT_v2s64*//*Label 192*/ GIMT_Encode4(4042), GIMT_Encode4(0),
1881 /*GILLT_v4s32*//*Label 193*/ GIMT_Encode4(4076),
1882 /*GILLT_v8s16*//*Label 194*/ GIMT_Encode4(4110),
1883 /*GILLT_v16s8*//*Label 195*/ GIMT_Encode4(4144),
1884 // Label 190: @3953
1885 GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(4007),
1886 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1887 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1888 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1889 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1890 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
1891 GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(3991), // Rule ID 328 //
1892 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
1893 // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1894 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
1895 GIR_RootConstrainSelectedInstOperands,
1896 // GIR_Coverage, 328,
1897 GIR_Done,
1898 // Label 198: @3991
1899 GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(4006), // Rule ID 1177 //
1900 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
1901 // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
1902 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
1903 GIR_RootConstrainSelectedInstOperands,
1904 // GIR_Coverage, 1177,
1905 GIR_Done,
1906 // Label 199: @4006
1907 GIM_Reject,
1908 // Label 197: @4007
1909 GIM_Reject,
1910 // Label 191: @4008
1911 GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(4041), // Rule ID 343 //
1912 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
1913 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
1914 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
1915 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1916 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1917 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
1918 // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
1919 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
1920 GIR_RootConstrainSelectedInstOperands,
1921 // GIR_Coverage, 343,
1922 GIR_Done,
1923 // Label 200: @4041
1924 GIM_Reject,
1925 // Label 192: @4042
1926 GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(4075), // Rule ID 887 //
1927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1928 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
1929 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
1930 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1931 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1932 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
1933 // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
1934 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
1935 GIR_RootConstrainSelectedInstOperands,
1936 // GIR_Coverage, 887,
1937 GIR_Done,
1938 // Label 201: @4075
1939 GIM_Reject,
1940 // Label 193: @4076
1941 GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(4109), // Rule ID 886 //
1942 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1943 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
1944 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
1945 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1946 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1947 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
1948 // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
1949 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
1950 GIR_RootConstrainSelectedInstOperands,
1951 // GIR_Coverage, 886,
1952 GIR_Done,
1953 // Label 202: @4109
1954 GIM_Reject,
1955 // Label 194: @4110
1956 GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(4143), // Rule ID 885 //
1957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1958 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
1959 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
1960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1961 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1962 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
1963 // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
1964 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
1965 GIR_RootConstrainSelectedInstOperands,
1966 // GIR_Coverage, 885,
1967 GIR_Done,
1968 // Label 203: @4143
1969 GIM_Reject,
1970 // Label 195: @4144
1971 GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(4177), // Rule ID 884 //
1972 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
1973 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
1974 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
1975 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1976 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1977 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
1978 // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
1979 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
1980 GIR_RootConstrainSelectedInstOperands,
1981 // GIR_Coverage, 884,
1982 GIR_Done,
1983 // Label 204: @4177
1984 GIM_Reject,
1985 // Label 196: @4178
1986 GIM_Reject,
1987 // Label 6: @4179
1988 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 211*/ GIMT_Encode4(4447),
1989 /*GILLT_s32*//*Label 205*/ GIMT_Encode4(4222),
1990 /*GILLT_s64*//*Label 206*/ GIMT_Encode4(4277), GIMT_Encode4(0),
1991 /*GILLT_v2s64*//*Label 207*/ GIMT_Encode4(4311), GIMT_Encode4(0),
1992 /*GILLT_v4s32*//*Label 208*/ GIMT_Encode4(4345),
1993 /*GILLT_v8s16*//*Label 209*/ GIMT_Encode4(4379),
1994 /*GILLT_v16s8*//*Label 210*/ GIMT_Encode4(4413),
1995 // Label 205: @4222
1996 GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(4276),
1997 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1998 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1999 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2000 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2001 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2002 GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(4260), // Rule ID 329 //
2003 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
2004 // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2005 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
2006 GIR_RootConstrainSelectedInstOperands,
2007 // GIR_Coverage, 329,
2008 GIR_Done,
2009 // Label 213: @4260
2010 GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(4275), // Rule ID 1178 //
2011 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2012 // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2013 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
2014 GIR_RootConstrainSelectedInstOperands,
2015 // GIR_Coverage, 1178,
2016 GIR_Done,
2017 // Label 214: @4275
2018 GIM_Reject,
2019 // Label 212: @4276
2020 GIM_Reject,
2021 // Label 206: @4277
2022 GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(4310), // Rule ID 344 //
2023 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
2024 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2025 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2026 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2027 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2028 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2029 // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2030 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
2031 GIR_RootConstrainSelectedInstOperands,
2032 // GIR_Coverage, 344,
2033 GIR_Done,
2034 // Label 215: @4310
2035 GIM_Reject,
2036 // Label 207: @4311
2037 GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(4344), // Rule ID 891 //
2038 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2039 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2040 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2041 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2042 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2043 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2044 // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2045 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
2046 GIR_RootConstrainSelectedInstOperands,
2047 // GIR_Coverage, 891,
2048 GIR_Done,
2049 // Label 216: @4344
2050 GIM_Reject,
2051 // Label 208: @4345
2052 GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(4378), // Rule ID 890 //
2053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2054 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2055 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2057 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2058 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2059 // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2060 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
2061 GIR_RootConstrainSelectedInstOperands,
2062 // GIR_Coverage, 890,
2063 GIR_Done,
2064 // Label 217: @4378
2065 GIM_Reject,
2066 // Label 209: @4379
2067 GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(4412), // Rule ID 889 //
2068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2069 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2070 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2071 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2072 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2073 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2074 // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2075 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
2076 GIR_RootConstrainSelectedInstOperands,
2077 // GIR_Coverage, 889,
2078 GIR_Done,
2079 // Label 218: @4412
2080 GIM_Reject,
2081 // Label 210: @4413
2082 GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(4446), // Rule ID 888 //
2083 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2084 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2085 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2086 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2087 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2088 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2089 // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2090 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
2091 GIR_RootConstrainSelectedInstOperands,
2092 // GIR_Coverage, 888,
2093 GIR_Done,
2094 // Label 219: @4446
2095 GIM_Reject,
2096 // Label 211: @4447
2097 GIM_Reject,
2098 // Label 7: @4448
2099 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 226*/ GIMT_Encode4(5003),
2100 /*GILLT_s32*//*Label 220*/ GIMT_Encode4(4491),
2101 /*GILLT_s64*//*Label 221*/ GIMT_Encode4(4765), GIMT_Encode4(0),
2102 /*GILLT_v2s64*//*Label 222*/ GIMT_Encode4(4867), GIMT_Encode4(0),
2103 /*GILLT_v4s32*//*Label 223*/ GIMT_Encode4(4901),
2104 /*GILLT_v8s16*//*Label 224*/ GIMT_Encode4(4935),
2105 /*GILLT_v16s8*//*Label 225*/ GIMT_Encode4(4969),
2106 // Label 220: @4491
2107 GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(4764),
2108 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2109 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2110 GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(4544), // Rule ID 41 //
2111 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2112 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2113 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2114 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2115 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2116 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2117 // MIs[1] Operand 1
2118 // No operand predicates
2119 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2120 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2121 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
2122 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2123 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2124 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2125 GIR_RootConstrainSelectedInstOperands,
2126 // GIR_Coverage, 41,
2127 GIR_EraseRootFromParent_Done,
2128 // Label 228: @4544
2129 GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(4586), // Rule ID 2144 //
2130 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2131 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2132 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2133 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2134 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2135 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2136 // MIs[1] Operand 1
2137 // No operand predicates
2138 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2139 // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2140 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
2141 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2142 GIR_RootToRootCopy, /*OpIdx*/1, // src
2143 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2144 GIR_RootConstrainSelectedInstOperands,
2145 // GIR_Coverage, 2144,
2146 GIR_EraseRootFromParent_Done,
2147 // Label 229: @4586
2148 GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(4628), // Rule ID 2303 //
2149 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2150 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2151 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2152 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2153 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2154 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
2155 // MIs[1] Operand 1
2156 // No operand predicates
2157 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2158 // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
2159 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
2160 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2161 GIR_RootToRootCopy, /*OpIdx*/1, // src
2162 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2163 GIR_RootConstrainSelectedInstOperands,
2164 // GIR_Coverage, 2303,
2165 GIR_EraseRootFromParent_Done,
2166 // Label 230: @4628
2167 GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(4655), // Rule ID 51 //
2168 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2169 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2170 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2171 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2172 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2173 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
2174 GIR_RootConstrainSelectedInstOperands,
2175 // GIR_Coverage, 51,
2176 GIR_Done,
2177 // Label 231: @4655
2178 GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4682), // Rule ID 1061 //
2179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2180 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2181 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2182 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2183 // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2184 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
2185 GIR_RootConstrainSelectedInstOperands,
2186 // GIR_Coverage, 1061,
2187 GIR_Done,
2188 // Label 232: @4682
2189 GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4709), // Rule ID 1077 //
2190 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2191 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2192 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2193 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2194 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
2196 GIR_RootConstrainSelectedInstOperands,
2197 // GIR_Coverage, 1077,
2198 GIR_Done,
2199 // Label 233: @4709
2200 GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4736), // Rule ID 1170 //
2201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2203 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2204 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2205 // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
2207 GIR_RootConstrainSelectedInstOperands,
2208 // GIR_Coverage, 1170,
2209 GIR_Done,
2210 // Label 234: @4736
2211 GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(4763), // Rule ID 1802 //
2212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2214 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2215 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2216 // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2217 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
2218 GIR_RootConstrainSelectedInstOperands,
2219 // GIR_Coverage, 1802,
2220 GIR_Done,
2221 // Label 235: @4763
2222 GIM_Reject,
2223 // Label 227: @4764
2224 GIM_Reject,
2225 // Label 221: @4765
2226 GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(4866),
2227 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2228 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2229 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2230 GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(4842), // Rule ID 269 //
2231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
2232 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2233 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
2234 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2235 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2236 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2237 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2238 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
2239 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2240 // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
2242 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2245 GIR_RootConstrainSelectedInstOperands,
2246 // GIR_Coverage, 269,
2247 GIR_EraseRootFromParent_Done,
2248 // Label 237: @4842
2249 GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(4865), // Rule ID 206 //
2250 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2251 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2252 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2253 // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2254 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
2255 GIR_RootConstrainSelectedInstOperands,
2256 // GIR_Coverage, 206,
2257 GIR_Done,
2258 // Label 238: @4865
2259 GIM_Reject,
2260 // Label 236: @4866
2261 GIM_Reject,
2262 // Label 222: @4867
2263 GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(4900), // Rule ID 518 //
2264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2265 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2266 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2267 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2268 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2269 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2270 // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2271 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
2272 GIR_RootConstrainSelectedInstOperands,
2273 // GIR_Coverage, 518,
2274 GIR_Done,
2275 // Label 239: @4900
2276 GIM_Reject,
2277 // Label 223: @4901
2278 GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(4934), // Rule ID 517 //
2279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2280 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2281 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2283 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2284 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2285 // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2286 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
2287 GIR_RootConstrainSelectedInstOperands,
2288 // GIR_Coverage, 517,
2289 GIR_Done,
2290 // Label 240: @4934
2291 GIM_Reject,
2292 // Label 224: @4935
2293 GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(4968), // Rule ID 516 //
2294 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2295 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2296 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2298 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2299 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2300 // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2301 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
2302 GIR_RootConstrainSelectedInstOperands,
2303 // GIR_Coverage, 516,
2304 GIR_Done,
2305 // Label 241: @4968
2306 GIM_Reject,
2307 // Label 225: @4969
2308 GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(5002), // Rule ID 515 //
2309 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2310 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2311 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2312 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2313 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2314 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2315 // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2316 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
2317 GIR_RootConstrainSelectedInstOperands,
2318 // GIR_Coverage, 515,
2319 GIR_Done,
2320 // Label 242: @5002
2321 GIM_Reject,
2322 // Label 226: @5003
2323 GIM_Reject,
2324 // Label 8: @5004
2325 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 249*/ GIMT_Encode4(5407),
2326 /*GILLT_s32*//*Label 243*/ GIMT_Encode4(5047),
2327 /*GILLT_s64*//*Label 244*/ GIMT_Encode4(5237), GIMT_Encode4(0),
2328 /*GILLT_v2s64*//*Label 245*/ GIMT_Encode4(5271), GIMT_Encode4(0),
2329 /*GILLT_v4s32*//*Label 246*/ GIMT_Encode4(5305),
2330 /*GILLT_v8s16*//*Label 247*/ GIMT_Encode4(5339),
2331 /*GILLT_v16s8*//*Label 248*/ GIMT_Encode4(5373),
2332 // Label 243: @5047
2333 GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(5236),
2334 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2335 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2336 GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(5100), // Rule ID 42 //
2337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2339 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2340 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2341 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2342 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2343 // MIs[1] Operand 1
2344 // No operand predicates
2345 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2346 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
2348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2349 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2350 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2351 GIR_RootConstrainSelectedInstOperands,
2352 // GIR_Coverage, 42,
2353 GIR_EraseRootFromParent_Done,
2354 // Label 251: @5100
2355 GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(5127), // Rule ID 52 //
2356 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2358 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2359 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2360 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2361 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
2362 GIR_RootConstrainSelectedInstOperands,
2363 // GIR_Coverage, 52,
2364 GIR_Done,
2365 // Label 252: @5127
2366 GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(5154), // Rule ID 1063 //
2367 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2368 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2369 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2370 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2371 // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2372 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
2373 GIR_RootConstrainSelectedInstOperands,
2374 // GIR_Coverage, 1063,
2375 GIR_Done,
2376 // Label 253: @5154
2377 GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(5181), // Rule ID 1078 //
2378 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2379 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2380 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2381 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2382 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2383 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
2384 GIR_RootConstrainSelectedInstOperands,
2385 // GIR_Coverage, 1078,
2386 GIR_Done,
2387 // Label 254: @5181
2388 GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(5208), // Rule ID 1183 //
2389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2390 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2391 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2392 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2393 // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2394 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
2395 GIR_RootConstrainSelectedInstOperands,
2396 // GIR_Coverage, 1183,
2397 GIR_Done,
2398 // Label 255: @5208
2399 GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(5235), // Rule ID 1804 //
2400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2401 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2402 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2403 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2404 // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2405 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
2406 GIR_RootConstrainSelectedInstOperands,
2407 // GIR_Coverage, 1804,
2408 GIR_Done,
2409 // Label 256: @5235
2410 GIM_Reject,
2411 // Label 250: @5236
2412 GIM_Reject,
2413 // Label 244: @5237
2414 GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(5270), // Rule ID 207 //
2415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2416 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2417 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2418 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2419 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2420 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2421 // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2422 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
2423 GIR_RootConstrainSelectedInstOperands,
2424 // GIR_Coverage, 207,
2425 GIR_Done,
2426 // Label 257: @5270
2427 GIM_Reject,
2428 // Label 245: @5271
2429 GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(5304), // Rule ID 924 //
2430 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2431 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2432 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2433 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2434 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2435 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2436 // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2437 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
2438 GIR_RootConstrainSelectedInstOperands,
2439 // GIR_Coverage, 924,
2440 GIR_Done,
2441 // Label 258: @5304
2442 GIM_Reject,
2443 // Label 246: @5305
2444 GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(5338), // Rule ID 923 //
2445 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2446 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2447 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2448 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2449 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2450 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2451 // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2452 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
2453 GIR_RootConstrainSelectedInstOperands,
2454 // GIR_Coverage, 923,
2455 GIR_Done,
2456 // Label 259: @5338
2457 GIM_Reject,
2458 // Label 247: @5339
2459 GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(5372), // Rule ID 922 //
2460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2461 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2463 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2464 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2465 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2466 // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2467 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
2468 GIR_RootConstrainSelectedInstOperands,
2469 // GIR_Coverage, 922,
2470 GIR_Done,
2471 // Label 260: @5372
2472 GIM_Reject,
2473 // Label 248: @5373
2474 GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(5406), // Rule ID 921 //
2475 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2476 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2477 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2478 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2479 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2480 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2481 // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2482 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
2483 GIR_RootConstrainSelectedInstOperands,
2484 // GIR_Coverage, 921,
2485 GIR_Done,
2486 // Label 261: @5406
2487 GIM_Reject,
2488 // Label 249: @5407
2489 GIM_Reject,
2490 // Label 9: @5408
2491 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 268*/ GIMT_Encode4(6299),
2492 /*GILLT_s32*//*Label 262*/ GIMT_Encode4(5451),
2493 /*GILLT_s64*//*Label 263*/ GIMT_Encode4(6068), GIMT_Encode4(0),
2494 /*GILLT_v2s64*//*Label 264*/ GIMT_Encode4(6163), GIMT_Encode4(0),
2495 /*GILLT_v4s32*//*Label 265*/ GIMT_Encode4(6197),
2496 /*GILLT_v8s16*//*Label 266*/ GIMT_Encode4(6231),
2497 /*GILLT_v16s8*//*Label 267*/ GIMT_Encode4(6265),
2498 // Label 262: @5451
2499 GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(6067),
2500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2501 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2502 GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5521), // Rule ID 54 //
2503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2504 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2505 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2506 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2507 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2508 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2509 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2510 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2511 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2512 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2513 // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2516 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2518 GIR_RootConstrainSelectedInstOperands,
2519 // GIR_Coverage, 54,
2520 GIR_EraseRootFromParent_Done,
2521 // Label 270: @5521
2522 GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(5580), // Rule ID 1080 //
2523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2524 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2525 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2526 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2527 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2528 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2529 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2530 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2531 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2532 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2533 // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2536 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2537 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2538 GIR_RootConstrainSelectedInstOperands,
2539 // GIR_Coverage, 1080,
2540 GIR_EraseRootFromParent_Done,
2541 // Label 271: @5580
2542 GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(5639), // Rule ID 1182 //
2543 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2545 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2546 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2547 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2548 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2549 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2550 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2551 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2552 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2553 // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2554 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2555 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2556 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2558 GIR_RootConstrainSelectedInstOperands,
2559 // GIR_Coverage, 1182,
2560 GIR_EraseRootFromParent_Done,
2561 // Label 272: @5639
2562 GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(5668), // Rule ID 1209 //
2563 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2565 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2566 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2567 // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2570 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2571 GIR_RootConstrainSelectedInstOperands,
2572 // GIR_Coverage, 1209,
2573 GIR_EraseRootFromParent_Done,
2574 // Label 273: @5668
2575 GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(5697), // Rule ID 1062 //
2576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2578 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2579 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2580 // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
2581 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2582 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2583 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2584 GIR_RootConstrainSelectedInstOperands,
2585 // GIR_Coverage, 1062,
2586 GIR_EraseRootFromParent_Done,
2587 // Label 274: @5697
2588 GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(5732), // Rule ID 1397 //
2589 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2590 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2591 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2592 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2593 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
2595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2596 GIR_RootToRootCopy, /*OpIdx*/1, // in
2597 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2598 GIR_RootConstrainSelectedInstOperands,
2599 // GIR_Coverage, 1397,
2600 GIR_EraseRootFromParent_Done,
2601 // Label 275: @5732
2602 GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5761), // Rule ID 1799 //
2603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2604 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2605 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2606 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2607 // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
2608 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
2609 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
2610 GIR_RootToRootCopy, /*OpIdx*/1, // r
2611 GIR_RootConstrainSelectedInstOperands,
2612 // GIR_Coverage, 1799,
2613 GIR_EraseRootFromParent_Done,
2614 // Label 276: @5761
2615 GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5790), // Rule ID 2139 //
2616 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2618 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2619 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2620 // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
2622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2623 GIR_RootToRootCopy, /*OpIdx*/1, // in
2624 GIR_RootConstrainSelectedInstOperands,
2625 // GIR_Coverage, 2139,
2626 GIR_EraseRootFromParent_Done,
2627 // Label 277: @5790
2628 GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5825), // Rule ID 2140 //
2629 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
2630 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2631 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2632 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2633 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2634 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
2635 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2636 GIR_RootToRootCopy, /*OpIdx*/1, // in
2637 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2638 GIR_RootConstrainSelectedInstOperands,
2639 // GIR_Coverage, 2140,
2640 GIR_EraseRootFromParent_Done,
2641 // Label 278: @5825
2642 GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5854), // Rule ID 2306 //
2643 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2644 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2645 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2646 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2647 // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
2648 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
2649 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2650 GIR_RootToRootCopy, /*OpIdx*/1, // in
2651 GIR_RootConstrainSelectedInstOperands,
2652 // GIR_Coverage, 2306,
2653 GIR_EraseRootFromParent_Done,
2654 // Label 279: @5854
2655 GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5889), // Rule ID 2307 //
2656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2657 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2658 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2659 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2660 // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
2661 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
2662 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2663 GIR_RootToRootCopy, /*OpIdx*/1, // in
2664 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2665 GIR_RootConstrainSelectedInstOperands,
2666 // GIR_Coverage, 2307,
2667 GIR_EraseRootFromParent_Done,
2668 // Label 280: @5889
2669 GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5931), // Rule ID 43 //
2670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2671 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2672 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2673 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2674 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2675 GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
2676 // MIs[1] Operand 1
2677 // No operand predicates
2678 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2679 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
2680 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
2681 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
2682 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2683 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
2684 GIR_RootConstrainSelectedInstOperands,
2685 // GIR_Coverage, 43,
2686 GIR_EraseRootFromParent_Done,
2687 // Label 281: @5931
2688 GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(5958), // Rule ID 53 //
2689 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
2690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2691 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2692 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2693 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2694 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
2695 GIR_RootConstrainSelectedInstOperands,
2696 // GIR_Coverage, 53,
2697 GIR_Done,
2698 // Label 282: @5958
2699 GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(5985), // Rule ID 1065 //
2700 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2702 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2703 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
2704 // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
2705 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
2706 GIR_RootConstrainSelectedInstOperands,
2707 // GIR_Coverage, 1065,
2708 GIR_Done,
2709 // Label 283: @5985
2710 GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(6012), // Rule ID 1079 //
2711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
2712 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2713 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2714 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2715 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
2717 GIR_RootConstrainSelectedInstOperands,
2718 // GIR_Coverage, 1079,
2719 GIR_Done,
2720 // Label 284: @6012
2721 GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(6039), // Rule ID 1186 //
2722 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
2723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2724 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2725 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2726 // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
2727 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
2728 GIR_RootConstrainSelectedInstOperands,
2729 // GIR_Coverage, 1186,
2730 GIR_Done,
2731 // Label 285: @6039
2732 GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(6066), // Rule ID 1806 //
2733 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
2734 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2735 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2736 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
2737 // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
2738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
2739 GIR_RootConstrainSelectedInstOperands,
2740 // GIR_Coverage, 1806,
2741 GIR_Done,
2742 // Label 286: @6066
2743 GIM_Reject,
2744 // Label 269: @6067
2745 GIM_Reject,
2746 // Label 263: @6068
2747 GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(6162),
2748 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2749 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2750 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2751 GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(6138), // Rule ID 209 //
2752 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2753 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2754 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
2755 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
2756 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
2757 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2758 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2759 GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
2760 GIM_CheckIsSafeToFold, /*NumInsns*/1,
2761 // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2762 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
2763 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
2764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
2765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
2766 GIR_RootConstrainSelectedInstOperands,
2767 // GIR_Coverage, 209,
2768 GIR_EraseRootFromParent_Done,
2769 // Label 288: @6138
2770 GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(6161), // Rule ID 208 //
2771 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
2772 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2774 // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
2775 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
2776 GIR_RootConstrainSelectedInstOperands,
2777 // GIR_Coverage, 208,
2778 GIR_Done,
2779 // Label 289: @6161
2780 GIM_Reject,
2781 // Label 287: @6162
2782 GIM_Reject,
2783 // Label 264: @6163
2784 GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(6196), // Rule ID 1040 //
2785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2786 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
2787 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
2788 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2789 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2790 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2791 // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
2792 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
2793 GIR_RootConstrainSelectedInstOperands,
2794 // GIR_Coverage, 1040,
2795 GIR_Done,
2796 // Label 290: @6196
2797 GIM_Reject,
2798 // Label 265: @6197
2799 GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(6230), // Rule ID 1039 //
2800 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2801 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
2802 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
2803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2804 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2805 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2806 // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
2807 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
2808 GIR_RootConstrainSelectedInstOperands,
2809 // GIR_Coverage, 1039,
2810 GIR_Done,
2811 // Label 291: @6230
2812 GIM_Reject,
2813 // Label 266: @6231
2814 GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(6264), // Rule ID 1038 //
2815 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2816 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
2817 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
2818 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2819 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2820 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2821 // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
2822 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
2823 GIR_RootConstrainSelectedInstOperands,
2824 // GIR_Coverage, 1038,
2825 GIR_Done,
2826 // Label 292: @6264
2827 GIM_Reject,
2828 // Label 267: @6265
2829 GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(6298), // Rule ID 1037 //
2830 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2831 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
2832 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
2833 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2834 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2835 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2836 // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
2837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
2838 GIR_RootConstrainSelectedInstOperands,
2839 // GIR_Coverage, 1037,
2840 GIR_Done,
2841 // Label 293: @6298
2842 GIM_Reject,
2843 // Label 268: @6299
2844 GIM_Reject,
2845 // Label 10: @6300
2846 GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(6372),
2847 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2848 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
2849 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
2851 GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(6344), // Rule ID 180 //
2852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
2853 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
2854 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2855 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2856 // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2857 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
2858 GIR_RootConstrainSelectedInstOperands,
2859 // GIR_Coverage, 180,
2860 GIR_Done,
2861 // Label 295: @6344
2862 GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(6371), // Rule ID 181 //
2863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode),
2864 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2865 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2866 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2867 // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
2868 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
2869 GIR_RootConstrainSelectedInstOperands,
2870 // GIR_Coverage, 181,
2871 GIR_Done,
2872 // Label 296: @6371
2873 GIM_Reject,
2874 // Label 294: @6372
2875 GIM_Reject,
2876 // Label 11: @6373
2877 GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(6444),
2878 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
2879 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
2880 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2881 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
2882 GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(6417), // Rule ID 719 //
2883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
2884 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
2885 // MIs[0] rs
2886 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2887 // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
2888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
2889 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2890 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2891 GIR_RootConstrainSelectedInstOperands,
2892 // GIR_Coverage, 719,
2893 GIR_EraseRootFromParent_Done,
2894 // Label 298: @6417
2895 GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(6443), // Rule ID 721 //
2896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2897 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
2898 // MIs[0] fs
2899 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2900 // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
2901 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
2902 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2903 GIR_RootToRootCopy, /*OpIdx*/1, // fs
2904 GIR_RootConstrainSelectedInstOperands,
2905 // GIR_Coverage, 721,
2906 GIR_EraseRootFromParent_Done,
2907 // Label 299: @6443
2908 GIM_Reject,
2909 // Label 297: @6444
2910 GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(6535),
2911 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
2912 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
2913 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
2915 GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6498), // Rule ID 718 //
2916 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2917 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2918 // MIs[0] rs
2919 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2920 // MIs[0] rs
2921 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2922 // MIs[0] rs
2923 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2924 // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
2925 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
2926 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2927 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2928 GIR_RootConstrainSelectedInstOperands,
2929 // GIR_Coverage, 718,
2930 GIR_EraseRootFromParent_Done,
2931 // Label 301: @6498
2932 GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6534), // Rule ID 720 //
2933 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2934 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
2935 // MIs[0] fs
2936 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2937 // MIs[0] fs
2938 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2939 // MIs[0] fs
2940 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2941 // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
2942 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
2943 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2944 GIR_RootToRootCopy, /*OpIdx*/1, // fs
2945 GIR_RootConstrainSelectedInstOperands,
2946 // GIR_Coverage, 720,
2947 GIR_EraseRootFromParent_Done,
2948 // Label 302: @6534
2949 GIM_Reject,
2950 // Label 300: @6535
2951 GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(6604), // Rule ID 717 //
2952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2953 GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
2954 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
2955 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2956 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
2957 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2958 // MIs[0] rs
2959 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2960 // MIs[0] rs
2961 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2962 // MIs[0] rs
2963 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2964 // MIs[0] rs
2965 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2966 // MIs[0] rs
2967 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2968 // MIs[0] rs
2969 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2970 // MIs[0] rs
2971 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
2972 // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
2973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
2974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
2975 GIR_RootToRootCopy, /*OpIdx*/1, // rs
2976 GIR_RootConstrainSelectedInstOperands,
2977 // GIR_Coverage, 717,
2978 GIR_EraseRootFromParent_Done,
2979 // Label 303: @6604
2980 GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(6713), // Rule ID 716 //
2981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
2982 GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
2983 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
2984 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
2985 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
2986 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
2987 // MIs[0] rs
2988 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
2989 // MIs[0] rs
2990 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
2991 // MIs[0] rs
2992 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
2993 // MIs[0] rs
2994 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
2995 // MIs[0] rs
2996 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
2997 // MIs[0] rs
2998 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
2999 // MIs[0] rs
3000 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
3001 // MIs[0] rs
3002 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
3003 // MIs[0] rs
3004 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
3005 // MIs[0] rs
3006 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
3007 // MIs[0] rs
3008 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
3009 // MIs[0] rs
3010 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
3011 // MIs[0] rs
3012 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
3013 // MIs[0] rs
3014 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
3015 // MIs[0] rs
3016 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
3017 // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
3018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
3019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
3020 GIR_RootToRootCopy, /*OpIdx*/1, // rs
3021 GIR_RootConstrainSelectedInstOperands,
3022 // GIR_Coverage, 716,
3023 GIR_EraseRootFromParent_Done,
3024 // Label 304: @6713
3025 GIM_Reject,
3026 // Label 12: @6714
3027 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 313*/ GIMT_Encode4(10904),
3028 /*GILLT_s32*//*Label 305*/ GIMT_Encode4(6757),
3029 /*GILLT_s64*//*Label 306*/ GIMT_Encode4(7034),
3030 /*GILLT_v2s16*//*Label 307*/ GIMT_Encode4(7090),
3031 /*GILLT_v2s64*//*Label 308*/ GIMT_Encode4(7150),
3032 /*GILLT_v4s8*//*Label 309*/ GIMT_Encode4(8249),
3033 /*GILLT_v4s32*//*Label 310*/ GIMT_Encode4(8309),
3034 /*GILLT_v8s16*//*Label 311*/ GIMT_Encode4(9348),
3035 /*GILLT_v16s8*//*Label 312*/ GIMT_Encode4(10243),
3036 // Label 305: @6757
3037 GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6783), // Rule ID 135 //
3038 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3039 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3040 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3041 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3042 // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3043 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
3044 GIR_RootConstrainSelectedInstOperands,
3045 // GIR_Coverage, 135,
3046 GIR_Done,
3047 // Label 314: @6783
3048 GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6809), // Rule ID 136 //
3049 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3050 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3051 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3052 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3053 // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3054 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
3055 GIR_RootConstrainSelectedInstOperands,
3056 // GIR_Coverage, 136,
3057 GIR_Done,
3058 // Label 315: @6809
3059 GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6835), // Rule ID 1160 //
3060 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3061 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3062 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3063 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3064 // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
3066 GIR_RootConstrainSelectedInstOperands,
3067 // GIR_Coverage, 1160,
3068 GIR_Done,
3069 // Label 316: @6835
3070 GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6861), // Rule ID 1161 //
3071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
3072 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3074 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3075 // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3076 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
3077 GIR_RootConstrainSelectedInstOperands,
3078 // GIR_Coverage, 1161,
3079 GIR_Done,
3080 // Label 317: @6861
3081 GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6887), // Rule ID 1175 //
3082 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3083 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3084 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3085 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3086 // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
3087 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
3088 GIR_RootConstrainSelectedInstOperands,
3089 // GIR_Coverage, 1175,
3090 GIR_Done,
3091 // Label 318: @6887
3092 GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6913), // Rule ID 1176 //
3093 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
3094 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3095 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3096 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3097 // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
3098 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
3099 GIR_RootConstrainSelectedInstOperands,
3100 // GIR_Coverage, 1176,
3101 GIR_Done,
3102 // Label 319: @6913
3103 GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6943), // Rule ID 1887 //
3104 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3105 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3106 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3107 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3108 // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
3109 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3110 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3111 // GIR_Coverage, 1887,
3112 GIR_Done,
3113 // Label 320: @6943
3114 GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6973), // Rule ID 1888 //
3115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3116 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3118 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3119 // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
3120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3121 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
3122 // GIR_Coverage, 1888,
3123 GIR_Done,
3124 // Label 321: @6973
3125 GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(7003), // Rule ID 1891 //
3126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3127 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
3128 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3129 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3130 // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
3131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3132 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3133 // GIR_Coverage, 1891,
3134 GIR_Done,
3135 // Label 322: @7003
3136 GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(7033), // Rule ID 1892 //
3137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3138 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
3139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3140 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3141 // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
3142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3143 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
3144 // GIR_Coverage, 1892,
3145 GIR_Done,
3146 // Label 323: @7033
3147 GIM_Reject,
3148 // Label 306: @7034
3149 GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(7089),
3150 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
3151 GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(7065), // Rule ID 137 //
3152 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3153 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3154 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3155 // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
3156 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
3157 GIR_RootConstrainSelectedInstOperands,
3158 // GIR_Coverage, 137,
3159 GIR_Done,
3160 // Label 325: @7065
3161 GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(7088), // Rule ID 138 //
3162 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
3163 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
3164 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
3165 // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
3166 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
3167 GIR_RootConstrainSelectedInstOperands,
3168 // GIR_Coverage, 138,
3169 GIR_Done,
3170 // Label 326: @7088
3171 GIM_Reject,
3172 // Label 324: @7089
3173 GIM_Reject,
3174 // Label 307: @7090
3175 GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(7149),
3176 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3177 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3178 GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(7125), // Rule ID 1889 //
3179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3180 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3181 // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3182 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3183 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3184 // GIR_Coverage, 1889,
3185 GIR_Done,
3186 // Label 328: @7125
3187 GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(7148), // Rule ID 1893 //
3188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3189 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3190 // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3192 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3193 // GIR_Coverage, 1893,
3194 GIR_Done,
3195 // Label 329: @7148
3196 GIM_Reject,
3197 // Label 327: @7149
3198 GIM_Reject,
3199 // Label 308: @7150
3200 GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(7176), // Rule ID 1974 //
3201 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3202 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3203 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3204 // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
3205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3206 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3207 // GIR_Coverage, 1974,
3208 GIR_Done,
3209 // Label 330: @7176
3210 GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(7202), // Rule ID 1977 //
3211 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3212 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3214 // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
3215 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3216 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3217 // GIR_Coverage, 1977,
3218 GIR_Done,
3219 // Label 331: @7202
3220 GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(7228), // Rule ID 1994 //
3221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3222 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3224 // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3225 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3226 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3227 // GIR_Coverage, 1994,
3228 GIR_Done,
3229 // Label 332: @7228
3230 GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(7254), // Rule ID 1995 //
3231 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3232 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3234 // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3235 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3236 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3237 // GIR_Coverage, 1995,
3238 GIR_Done,
3239 // Label 333: @7254
3240 GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(7280), // Rule ID 1996 //
3241 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3242 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3243 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3244 // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3245 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3246 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3247 // GIR_Coverage, 1996,
3248 GIR_Done,
3249 // Label 334: @7280
3250 GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(7306), // Rule ID 1997 //
3251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3252 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3254 // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3255 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3256 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3257 // GIR_Coverage, 1997,
3258 GIR_Done,
3259 // Label 335: @7306
3260 GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(7332), // Rule ID 1998 //
3261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3262 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3263 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3264 // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3265 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3266 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3267 // GIR_Coverage, 1998,
3268 GIR_Done,
3269 // Label 336: @7332
3270 GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(7358), // Rule ID 2004 //
3271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3272 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3273 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3274 // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
3275 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3276 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3277 // GIR_Coverage, 2004,
3278 GIR_Done,
3279 // Label 337: @7358
3280 GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(7384), // Rule ID 2005 //
3281 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3282 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3283 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3284 // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
3285 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3286 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3287 // GIR_Coverage, 2005,
3288 GIR_Done,
3289 // Label 338: @7384
3290 GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7410), // Rule ID 2006 //
3291 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3292 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3293 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3294 // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
3295 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3296 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3297 // GIR_Coverage, 2006,
3298 GIR_Done,
3299 // Label 339: @7410
3300 GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7436), // Rule ID 2007 //
3301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3302 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3304 // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
3305 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3306 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3307 // GIR_Coverage, 2007,
3308 GIR_Done,
3309 // Label 340: @7436
3310 GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7462), // Rule ID 2008 //
3311 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3312 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3313 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3314 // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
3315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3316 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3317 // GIR_Coverage, 2008,
3318 GIR_Done,
3319 // Label 341: @7462
3320 GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7573), // Rule ID 2013 //
3321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3322 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3323 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3324 // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3325 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3326 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3327 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3328 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3329 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3330 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3331 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3332 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3333 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3334 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3335 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3336 GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3337 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3338 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3339 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3340 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3341 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3342 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3343 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3344 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3345 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3346 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3349 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3350 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3351 // GIR_Coverage, 2013,
3352 GIR_EraseRootFromParent_Done,
3353 // Label 342: @7573
3354 GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7684), // Rule ID 2014 //
3355 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3356 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3358 // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3359 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3360 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3361 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
3362 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
3363 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3364 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3365 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
3366 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
3367 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3368 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3369 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
3370 GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
3371 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
3372 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3373 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3374 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
3375 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3376 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3377 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3378 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3379 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3380 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3383 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3384 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3385 // GIR_Coverage, 2014,
3386 GIR_EraseRootFromParent_Done,
3387 // Label 343: @7684
3388 GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7751), // Rule ID 2018 //
3389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3390 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3392 // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3393 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3394 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3395 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3396 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3397 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3398 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3399 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3400 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3401 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3402 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3403 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3406 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3407 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3408 // GIR_Coverage, 2018,
3409 GIR_EraseRootFromParent_Done,
3410 // Label 344: @7751
3411 GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7818), // Rule ID 2019 //
3412 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3413 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3414 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3415 // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3416 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3417 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3418 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3419 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3420 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3421 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3423 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3424 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3425 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3426 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3427 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3428 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3429 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3430 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3431 // GIR_Coverage, 2019,
3432 GIR_EraseRootFromParent_Done,
3433 // Label 345: @7818
3434 GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7885), // Rule ID 2023 //
3435 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3436 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3437 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3438 // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3439 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3440 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3441 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3442 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3443 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3444 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3445 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3446 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3447 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3448 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3449 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3452 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3453 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3454 // GIR_Coverage, 2023,
3455 GIR_EraseRootFromParent_Done,
3456 // Label 346: @7885
3457 GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7952), // Rule ID 2024 //
3458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3459 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3460 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3461 // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
3462 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3463 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3464 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3465 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3466 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3467 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3468 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3469 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3470 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3471 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3472 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3473 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3474 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3475 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3476 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3477 // GIR_Coverage, 2024,
3478 GIR_EraseRootFromParent_Done,
3479 // Label 347: @7952
3480 GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(8026), // Rule ID 2028 //
3481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3482 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3484 // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3485 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3486 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3487 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3488 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3489 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3490 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3491 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3492 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3493 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3494 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3495 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3498 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3499 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3500 // GIR_Coverage, 2028,
3501 GIR_EraseRootFromParent_Done,
3502 // Label 348: @8026
3503 GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(8100), // Rule ID 2029 //
3504 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3505 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3507 // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3508 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3509 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3510 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3511 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3512 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3513 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3514 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3515 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3516 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3517 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3518 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3519 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3520 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3521 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3522 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3523 // GIR_Coverage, 2029,
3524 GIR_EraseRootFromParent_Done,
3525 // Label 349: @8100
3526 GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(8174), // Rule ID 2033 //
3527 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3528 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3529 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3530 // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3531 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3532 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3533 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3534 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3535 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3536 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3539 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3540 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3541 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3542 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3543 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3544 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3545 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3546 // GIR_Coverage, 2033,
3547 GIR_EraseRootFromParent_Done,
3548 // Label 350: @8174
3549 GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(8248), // Rule ID 2034 //
3550 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3551 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
3553 // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
3554 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3555 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3556 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3557 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3558 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3559 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3560 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3561 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3562 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3563 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3564 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3567 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3568 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
3569 // GIR_Coverage, 2034,
3570 GIR_EraseRootFromParent_Done,
3571 // Label 351: @8248
3572 GIM_Reject,
3573 // Label 309: @8249
3574 GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(8308),
3575 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
3576 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
3577 GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(8284), // Rule ID 1890 //
3578 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3579 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
3580 // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
3581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3582 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3583 // GIR_Coverage, 1890,
3584 GIR_Done,
3585 // Label 353: @8284
3586 GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(8307), // Rule ID 1894 //
3587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
3588 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
3589 // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
3590 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3591 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
3592 // GIR_Coverage, 1894,
3593 GIR_Done,
3594 // Label 354: @8307
3595 GIM_Reject,
3596 // Label 352: @8308
3597 GIM_Reject,
3598 // Label 310: @8309
3599 GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(8335), // Rule ID 1973 //
3600 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3601 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3602 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3603 // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
3604 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3605 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3606 // GIR_Coverage, 1973,
3607 GIR_Done,
3608 // Label 355: @8335
3609 GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(8361), // Rule ID 1976 //
3610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3611 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3613 // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
3614 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3615 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3616 // GIR_Coverage, 1976,
3617 GIR_Done,
3618 // Label 356: @8361
3619 GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(8387), // Rule ID 1989 //
3620 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3621 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3622 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3623 // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3624 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3625 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3626 // GIR_Coverage, 1989,
3627 GIR_Done,
3628 // Label 357: @8387
3629 GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(8413), // Rule ID 1990 //
3630 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3631 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3632 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3633 // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3634 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3635 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3636 // GIR_Coverage, 1990,
3637 GIR_Done,
3638 // Label 358: @8413
3639 GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(8439), // Rule ID 1991 //
3640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3641 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3643 // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3645 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3646 // GIR_Coverage, 1991,
3647 GIR_Done,
3648 // Label 359: @8439
3649 GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(8465), // Rule ID 1992 //
3650 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3651 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3652 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3653 // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3655 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3656 // GIR_Coverage, 1992,
3657 GIR_Done,
3658 // Label 360: @8465
3659 GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(8491), // Rule ID 1993 //
3660 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3661 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3663 // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3664 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3665 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3666 // GIR_Coverage, 1993,
3667 GIR_Done,
3668 // Label 361: @8491
3669 GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(8517), // Rule ID 1999 //
3670 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3671 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3673 // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
3674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3675 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3676 // GIR_Coverage, 1999,
3677 GIR_Done,
3678 // Label 362: @8517
3679 GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(8543), // Rule ID 2000 //
3680 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3681 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3682 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3683 // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
3684 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3685 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3686 // GIR_Coverage, 2000,
3687 GIR_Done,
3688 // Label 363: @8543
3689 GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(8569), // Rule ID 2001 //
3690 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3691 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3692 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3693 // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
3694 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3695 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3696 // GIR_Coverage, 2001,
3697 GIR_Done,
3698 // Label 364: @8569
3699 GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(8595), // Rule ID 2002 //
3700 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3701 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3702 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3703 // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
3704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3705 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3706 // GIR_Coverage, 2002,
3707 GIR_Done,
3708 // Label 365: @8595
3709 GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8621), // Rule ID 2003 //
3710 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3711 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3712 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3713 // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
3714 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3715 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3716 // GIR_Coverage, 2003,
3717 GIR_Done,
3718 // Label 366: @8621
3719 GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8688), // Rule ID 2011 //
3720 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3721 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3722 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3723 // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3724 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3725 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3726 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3727 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3728 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3729 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3730 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3731 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3732 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3733 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3734 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3737 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3738 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3739 // GIR_Coverage, 2011,
3740 GIR_EraseRootFromParent_Done,
3741 // Label 367: @8688
3742 GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8755), // Rule ID 2012 //
3743 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3744 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3746 // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
3747 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
3748 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
3749 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3750 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3751 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3752 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3753 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
3754 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3755 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3756 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
3757 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3760 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3761 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3762 // GIR_Coverage, 2012,
3763 GIR_EraseRootFromParent_Done,
3764 // Label 368: @8755
3765 GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8829), // Rule ID 2016 //
3766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3767 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3769 // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3770 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3771 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3772 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3773 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3774 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3775 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3776 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3777 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3778 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3779 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3780 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3781 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3782 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3783 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3784 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3785 // GIR_Coverage, 2016,
3786 GIR_EraseRootFromParent_Done,
3787 // Label 369: @8829
3788 GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8903), // Rule ID 2017 //
3789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3790 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3791 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3792 // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3793 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3794 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3795 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3796 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3797 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3798 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3799 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3800 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3801 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3802 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3803 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3806 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3807 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3808 // GIR_Coverage, 2017,
3809 GIR_EraseRootFromParent_Done,
3810 // Label 370: @8903
3811 GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8977), // Rule ID 2021 //
3812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3813 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3814 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3815 // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3816 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3817 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3818 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3819 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3820 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3821 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3822 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3823 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3824 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3825 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3826 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3828 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3829 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3830 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3831 // GIR_Coverage, 2021,
3832 GIR_EraseRootFromParent_Done,
3833 // Label 371: @8977
3834 GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(9051), // Rule ID 2022 //
3835 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3836 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3837 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3838 // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3839 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
3840 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
3841 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3842 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3843 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3844 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
3846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3847 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3848 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3849 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3850 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3851 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3852 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3853 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3854 // GIR_Coverage, 2022,
3855 GIR_EraseRootFromParent_Done,
3856 // Label 372: @9051
3857 GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(9125), // Rule ID 2038 //
3858 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3859 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3861 // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3862 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3863 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3864 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3865 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3866 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3867 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3868 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3869 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3870 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3871 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3872 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3875 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3876 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3877 // GIR_Coverage, 2038,
3878 GIR_EraseRootFromParent_Done,
3879 // Label 373: @9125
3880 GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(9199), // Rule ID 2039 //
3881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3882 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3883 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3884 // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3885 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3886 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3887 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3888 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3889 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3890 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3891 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3892 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3893 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3894 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3895 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3896 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3897 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3898 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3899 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3900 // GIR_Coverage, 2039,
3901 GIR_EraseRootFromParent_Done,
3902 // Label 374: @9199
3903 GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(9273), // Rule ID 2043 //
3904 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3905 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3906 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3907 // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3908 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3909 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3910 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3911 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3912 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3913 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3914 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3915 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3916 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3917 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3918 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3921 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3922 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3923 // GIR_Coverage, 2043,
3924 GIR_EraseRootFromParent_Done,
3925 // Label 375: @9273
3926 GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(9347), // Rule ID 2044 //
3927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
3928 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
3930 // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
3931 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3932 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
3933 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3934 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3935 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
3936 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
3937 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
3938 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
3939 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
3940 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
3941 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
3942 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3943 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
3944 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3945 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
3946 // GIR_Coverage, 2044,
3947 GIR_EraseRootFromParent_Done,
3948 // Label 376: @9347
3949 GIM_Reject,
3950 // Label 311: @9348
3951 GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(9374), // Rule ID 1972 //
3952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3953 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3954 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3955 // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
3956 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3957 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3958 // GIR_Coverage, 1972,
3959 GIR_Done,
3960 // Label 377: @9374
3961 GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(9400), // Rule ID 1975 //
3962 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
3963 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3964 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3965 // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
3966 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3967 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3968 // GIR_Coverage, 1975,
3969 GIR_Done,
3970 // Label 378: @9400
3971 GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(9426), // Rule ID 1984 //
3972 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3973 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3974 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3975 // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
3976 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3977 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3978 // GIR_Coverage, 1984,
3979 GIR_Done,
3980 // Label 379: @9426
3981 GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(9452), // Rule ID 1985 //
3982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3983 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3984 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3985 // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
3986 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3987 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3988 // GIR_Coverage, 1985,
3989 GIR_Done,
3990 // Label 380: @9452
3991 GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(9478), // Rule ID 1986 //
3992 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
3993 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3994 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
3995 // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
3996 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
3997 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
3998 // GIR_Coverage, 1986,
3999 GIR_Done,
4000 // Label 381: @9478
4001 GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(9504), // Rule ID 1987 //
4002 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4003 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4005 // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
4006 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4007 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4008 // GIR_Coverage, 1987,
4009 GIR_Done,
4010 // Label 382: @9504
4011 GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(9530), // Rule ID 1988 //
4012 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4013 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4014 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4015 // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
4016 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4017 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4018 // GIR_Coverage, 1988,
4019 GIR_Done,
4020 // Label 383: @9530
4021 GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(9604), // Rule ID 2009 //
4022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4023 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4024 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4025 // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4026 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4027 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4028 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4029 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4030 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4031 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4032 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4033 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4034 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4035 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4036 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4037 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4038 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4039 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4040 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4041 // GIR_Coverage, 2009,
4042 GIR_EraseRootFromParent_Done,
4043 // Label 384: @9604
4044 GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(9678), // Rule ID 2010 //
4045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4046 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4047 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4048 // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4049 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4050 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4051 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4052 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4053 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4054 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4055 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4056 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4057 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4058 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4059 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4060 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4061 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4062 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4063 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4064 // GIR_Coverage, 2010,
4065 GIR_EraseRootFromParent_Done,
4066 // Label 385: @9678
4067 GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(9752), // Rule ID 2026 //
4068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4069 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4070 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4071 // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4072 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4073 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4074 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4075 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4076 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4077 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4078 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4079 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4080 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4081 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4082 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4083 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4084 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4085 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4086 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4087 // GIR_Coverage, 2026,
4088 GIR_EraseRootFromParent_Done,
4089 // Label 386: @9752
4090 GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(9826), // Rule ID 2027 //
4091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4092 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4094 // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4095 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4096 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4097 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4098 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4099 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4100 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4101 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4102 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4103 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4104 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4105 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4106 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4107 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4108 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4109 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4110 // GIR_Coverage, 2027,
4111 GIR_EraseRootFromParent_Done,
4112 // Label 387: @9826
4113 GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(9900), // Rule ID 2031 //
4114 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4115 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4116 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4117 // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4118 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4119 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4120 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4121 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4122 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4123 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4124 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4125 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4126 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4127 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4128 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4129 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4130 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4131 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4132 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4133 // GIR_Coverage, 2031,
4134 GIR_EraseRootFromParent_Done,
4135 // Label 388: @9900
4136 GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(9974), // Rule ID 2032 //
4137 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4138 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4139 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4140 // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
4141 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4142 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4143 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4144 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4145 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4146 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4147 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4148 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4149 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4150 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4151 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4152 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4153 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4154 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4155 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4156 // GIR_Coverage, 2032,
4157 GIR_EraseRootFromParent_Done,
4158 // Label 389: @9974
4159 GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(10041), // Rule ID 2036 //
4160 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4161 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4162 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4163 // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4164 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4165 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4166 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4167 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4168 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4169 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4170 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4171 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4172 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4173 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4174 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4175 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4176 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4177 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4178 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4179 // GIR_Coverage, 2036,
4180 GIR_EraseRootFromParent_Done,
4181 // Label 390: @10041
4182 GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(10108), // Rule ID 2037 //
4183 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4184 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4185 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4186 // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4187 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4188 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4189 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4190 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4191 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4192 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4193 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4194 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4195 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4196 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4197 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4200 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4201 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4202 // GIR_Coverage, 2037,
4203 GIR_EraseRootFromParent_Done,
4204 // Label 391: @10108
4205 GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(10175), // Rule ID 2041 //
4206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4207 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4208 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4209 // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4210 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4211 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4212 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4213 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4214 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4215 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4216 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4217 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4218 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4219 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4220 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4221 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4222 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4223 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4224 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4225 // GIR_Coverage, 2041,
4226 GIR_EraseRootFromParent_Done,
4227 // Label 392: @10175
4228 GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(10242), // Rule ID 2042 //
4229 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4230 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
4232 // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
4233 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
4234 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
4235 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4236 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4237 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4238 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4239 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
4240 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4241 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4242 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4243 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4244 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4245 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4246 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4247 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
4248 // GIR_Coverage, 2042,
4249 GIR_EraseRootFromParent_Done,
4250 // Label 393: @10242
4251 GIM_Reject,
4252 // Label 312: @10243
4253 GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(10269), // Rule ID 1978 //
4254 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4255 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4256 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4257 // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
4258 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4259 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4260 // GIR_Coverage, 1978,
4261 GIR_Done,
4262 // Label 394: @10269
4263 GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(10295), // Rule ID 1979 //
4264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4265 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4266 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4267 // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
4268 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4269 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4270 // GIR_Coverage, 1979,
4271 GIR_Done,
4272 // Label 395: @10295
4273 GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(10321), // Rule ID 1980 //
4274 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4275 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4276 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4277 // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
4278 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4279 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4280 // GIR_Coverage, 1980,
4281 GIR_Done,
4282 // Label 396: @10321
4283 GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(10347), // Rule ID 1981 //
4284 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4285 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4286 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4287 // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
4288 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4289 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4290 // GIR_Coverage, 1981,
4291 GIR_Done,
4292 // Label 397: @10347
4293 GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(10373), // Rule ID 1982 //
4294 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4295 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4296 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4297 // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
4298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4299 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4300 // GIR_Coverage, 1982,
4301 GIR_Done,
4302 // Label 398: @10373
4303 GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(10399), // Rule ID 1983 //
4304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
4305 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4306 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4307 // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
4308 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4309 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4310 // GIR_Coverage, 1983,
4311 GIR_Done,
4312 // Label 399: @10399
4313 GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(10473), // Rule ID 2015 //
4314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4315 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4316 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4317 // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4318 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4319 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4320 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4321 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4322 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4323 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4324 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4325 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4326 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4327 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4328 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4329 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4330 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4331 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4332 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4333 // GIR_Coverage, 2015,
4334 GIR_EraseRootFromParent_Done,
4335 // Label 400: @10473
4336 GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(10547), // Rule ID 2020 //
4337 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4338 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4340 // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4341 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4342 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4343 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4344 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4345 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4346 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4347 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4348 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4349 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4350 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4351 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4352 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4353 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4354 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4355 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4356 // GIR_Coverage, 2020,
4357 GIR_EraseRootFromParent_Done,
4358 // Label 401: @10547
4359 GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(10614), // Rule ID 2025 //
4360 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4361 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4362 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4363 // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4364 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4365 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4366 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4367 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4368 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4369 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4371 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4372 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4373 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4374 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4377 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4378 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4379 // GIR_Coverage, 2025,
4380 GIR_EraseRootFromParent_Done,
4381 // Label 402: @10614
4382 GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(10681), // Rule ID 2030 //
4383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4384 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4385 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4386 // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
4387 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
4388 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
4389 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4390 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4391 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
4392 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4393 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4394 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4395 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4396 GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
4397 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4398 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4399 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4400 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4401 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4402 // GIR_Coverage, 2030,
4403 GIR_EraseRootFromParent_Done,
4404 // Label 403: @10681
4405 GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(10792), // Rule ID 2035 //
4406 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4407 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4408 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4409 // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4410 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4411 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4412 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4413 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4414 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4415 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4416 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4417 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4418 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4419 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4420 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4421 GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4422 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4423 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4424 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4425 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4426 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4427 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4428 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4429 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4430 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4431 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4433 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4434 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4435 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4436 // GIR_Coverage, 2035,
4437 GIR_EraseRootFromParent_Done,
4438 // Label 404: @10792
4439 GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(10903), // Rule ID 2040 //
4440 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
4441 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4442 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
4443 // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
4444 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4445 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
4446 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
4447 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
4448 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4449 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4450 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
4451 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
4452 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
4453 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4454 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
4455 GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
4456 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
4457 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4458 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4459 GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
4460 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
4461 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
4462 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
4463 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
4464 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
4465 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
4466 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
4467 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
4468 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4469 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
4470 // GIR_Coverage, 2040,
4471 GIR_EraseRootFromParent_Done,
4472 // Label 405: @10903
4473 GIM_Reject,
4474 // Label 313: @10904
4475 GIM_Reject,
4476 // Label 13: @10905
4477 GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(10969), // Rule ID 1963 //
4478 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4479 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4480 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
4481 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4482 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4483 // MIs[0] Operand 1
4484 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4485 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4486 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4487 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4488 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4489 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4490 // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4491 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
4492 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4495 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4496 GIR_RootConstrainSelectedInstOperands,
4497 // GIR_Coverage, 1963,
4498 GIR_EraseRootFromParent_Done,
4499 // Label 406: @10969
4500 GIM_Reject,
4501 // Label 14: @10970
4502 GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(11037), // Rule ID 1962 //
4503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4504 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4505 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
4506 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4508 // MIs[0] Operand 1
4509 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4511 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4512 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4513 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4514 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4515 // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4516 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
4517 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4520 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4521 GIR_RootConstrainSelectedInstOperands,
4522 // GIR_Coverage, 1962,
4523 GIR_EraseRootFromParent_Done,
4524 // Label 407: @11037
4525 GIM_Reject,
4526 // Label 15: @11038
4527 GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(11105), // Rule ID 1961 //
4528 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
4529 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
4530 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
4531 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
4532 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4533 // MIs[0] Operand 1
4534 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
4535 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4536 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
4537 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4538 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4539 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4540 // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
4541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
4542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
4543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
4544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
4545 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
4546 GIR_RootConstrainSelectedInstOperands,
4547 // GIR_Coverage, 1961,
4548 GIR_EraseRootFromParent_Done,
4549 // Label 408: @11105
4550 GIM_Reject,
4551 // Label 16: @11106
4552 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 411*/ GIMT_Encode4(15826),
4553 /*GILLT_s32*//*Label 409*/ GIMT_Encode4(11125),
4554 /*GILLT_s64*//*Label 410*/ GIMT_Encode4(15792),
4555 // Label 409: @11125
4556 GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(11233), // Rule ID 2337 //
4557 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4558 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4559 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4560 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4561 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4562 // MIs[1] Operand 1
4563 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
4564 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4565 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4566 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4567 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4568 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
4569 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4570 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4571 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4572 GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
4573 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4574 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4575 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4576 // MIs[4] Operand 1
4577 // No operand predicates
4578 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4579 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4580 // MIs[0] offset
4581 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4582 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4583 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4584 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
4585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
4586 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4587 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4588 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4589 GIR_RootConstrainSelectedInstOperands,
4590 // GIR_Coverage, 2337,
4591 GIR_EraseRootFromParent_Done,
4592 // Label 412: @11233
4593 GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(11348), // Rule ID 2338 //
4594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4595 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4596 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4597 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4598 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4599 // MIs[1] Operand 1
4600 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
4601 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4602 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4603 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4604 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4605 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
4606 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4607 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4608 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4609 GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
4610 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4611 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4612 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4613 // MIs[4] Operand 1
4614 // No operand predicates
4615 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4616 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4617 // MIs[0] offset
4618 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4619 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4620 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
4622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
4623 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4624 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4625 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4626 GIR_RootConstrainSelectedInstOperands,
4627 // GIR_Coverage, 2338,
4628 GIR_EraseRootFromParent_Done,
4629 // Label 413: @11348
4630 GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(11456), // Rule ID 2339 //
4631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4632 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4633 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4634 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4635 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4636 // MIs[1] Operand 1
4637 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
4638 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4639 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4640 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4641 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4642 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
4643 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4644 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4645 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4646 GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
4647 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4648 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4649 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4650 // MIs[4] Operand 1
4651 // No operand predicates
4652 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4653 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4654 // MIs[0] offset
4655 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4656 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4657 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4658 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
4659 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
4660 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4661 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4662 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4663 GIR_RootConstrainSelectedInstOperands,
4664 // GIR_Coverage, 2339,
4665 GIR_EraseRootFromParent_Done,
4666 // Label 414: @11456
4667 GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(11571), // Rule ID 2340 //
4668 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4669 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4670 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4671 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4672 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4673 // MIs[1] Operand 1
4674 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
4675 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4676 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4677 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4678 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4679 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
4680 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4681 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4682 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4683 GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
4684 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4685 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4686 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4687 // MIs[4] Operand 1
4688 // No operand predicates
4689 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4690 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4691 // MIs[0] offset
4692 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4693 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4694 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4695 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
4696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
4697 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4698 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4699 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4700 GIR_RootConstrainSelectedInstOperands,
4701 // GIR_Coverage, 2340,
4702 GIR_EraseRootFromParent_Done,
4703 // Label 415: @11571
4704 GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(11679), // Rule ID 270 //
4705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4706 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4707 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4708 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4709 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4710 // MIs[1] Operand 1
4711 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
4712 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4713 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4714 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4715 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4716 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4717 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4718 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4719 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4720 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4721 GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
4722 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4723 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4724 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4725 // MIs[4] Operand 1
4726 // No operand predicates
4727 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4728 // MIs[0] offset
4729 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4730 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4731 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4732 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
4733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
4734 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4735 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4736 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4737 GIR_RootConstrainSelectedInstOperands,
4738 // GIR_Coverage, 270,
4739 GIR_EraseRootFromParent_Done,
4740 // Label 416: @11679
4741 GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(11794), // Rule ID 271 //
4742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4744 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4745 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4746 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4747 // MIs[1] Operand 1
4748 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
4749 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4750 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4751 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4752 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4753 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4754 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4755 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4756 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4757 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4758 GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
4759 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4760 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4761 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4762 // MIs[4] Operand 1
4763 // No operand predicates
4764 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4765 // MIs[0] offset
4766 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4767 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4768 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4769 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
4770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
4771 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4772 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4773 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4774 GIR_RootConstrainSelectedInstOperands,
4775 // GIR_Coverage, 271,
4776 GIR_EraseRootFromParent_Done,
4777 // Label 417: @11794
4778 GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(11902), // Rule ID 272 //
4779 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4780 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4781 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4782 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4783 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4784 // MIs[1] Operand 1
4785 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
4786 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4787 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4788 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4789 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4790 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4791 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4792 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4793 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4794 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4795 GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
4796 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4797 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4798 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4799 // MIs[4] Operand 1
4800 // No operand predicates
4801 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4802 // MIs[0] offset
4803 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4804 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4805 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4806 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
4807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
4808 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4809 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4810 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4811 GIR_RootConstrainSelectedInstOperands,
4812 // GIR_Coverage, 272,
4813 GIR_EraseRootFromParent_Done,
4814 // Label 418: @11902
4815 GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(12017), // Rule ID 273 //
4816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
4817 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4818 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4819 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4820 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4821 // MIs[1] Operand 1
4822 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
4823 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
4824 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
4825 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
4826 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
4827 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4828 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
4829 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
4830 GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
4831 GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
4832 GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
4833 GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
4834 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4835 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
4836 // MIs[4] Operand 1
4837 // No operand predicates
4838 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4839 // MIs[0] offset
4840 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4841 GIM_CheckIsSafeToFold, /*NumInsns*/4,
4842 // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
4843 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
4844 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
4845 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
4846 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4847 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4848 GIR_RootConstrainSelectedInstOperands,
4849 // GIR_Coverage, 273,
4850 GIR_EraseRootFromParent_Done,
4851 // Label 419: @12017
4852 GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(12074), // Rule ID 94 //
4853 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
4854 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4855 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4856 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4857 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
4858 // MIs[1] Operand 1
4859 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
4860 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4861 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4862 // MIs[0] offset
4863 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4864 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4865 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
4866 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
4867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
4868 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4869 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4870 GIR_RootConstrainSelectedInstOperands,
4871 // GIR_Coverage, 94,
4872 GIR_EraseRootFromParent_Done,
4873 // Label 420: @12074
4874 GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(12131), // Rule ID 95 //
4875 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
4876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4877 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4878 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4879 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
4880 // MIs[1] Operand 1
4881 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
4882 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4883 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4884 // MIs[0] offset
4885 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4886 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4887 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
4888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
4889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
4890 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4891 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4892 GIR_RootConstrainSelectedInstOperands,
4893 // GIR_Coverage, 95,
4894 GIR_EraseRootFromParent_Done,
4895 // Label 421: @12131
4896 GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(12188), // Rule ID 96 //
4897 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
4898 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4899 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4900 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4901 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
4902 // MIs[1] Operand 1
4903 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
4904 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4905 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4906 // MIs[0] offset
4907 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4908 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4909 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
4910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
4911 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
4912 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4913 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4914 GIR_RootConstrainSelectedInstOperands,
4915 // GIR_Coverage, 96,
4916 GIR_EraseRootFromParent_Done,
4917 // Label 422: @12188
4918 GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(12245), // Rule ID 97 //
4919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
4920 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4921 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4922 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4923 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
4924 // MIs[1] Operand 1
4925 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
4926 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
4927 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4928 // MIs[0] offset
4929 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4930 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4931 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
4932 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
4933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
4934 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4935 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4936 GIR_RootConstrainSelectedInstOperands,
4937 // GIR_Coverage, 97,
4938 GIR_EraseRootFromParent_Done,
4939 // Label 423: @12245
4940 GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(12302), // Rule ID 245 //
4941 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
4942 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4943 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4944 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4945 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4946 // MIs[1] Operand 1
4947 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
4948 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4949 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4950 // MIs[0] offset
4951 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4952 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4953 // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
4954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
4955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
4956 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4957 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4958 GIR_RootConstrainSelectedInstOperands,
4959 // GIR_Coverage, 245,
4960 GIR_EraseRootFromParent_Done,
4961 // Label 424: @12302
4962 GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(12359), // Rule ID 246 //
4963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
4964 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4965 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4966 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4967 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4968 // MIs[1] Operand 1
4969 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
4970 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4971 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4972 // MIs[0] offset
4973 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4974 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4975 // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
4976 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
4977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
4978 GIR_RootToRootCopy, /*OpIdx*/1, // offset
4979 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
4980 GIR_RootConstrainSelectedInstOperands,
4981 // GIR_Coverage, 246,
4982 GIR_EraseRootFromParent_Done,
4983 // Label 425: @12359
4984 GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(12416), // Rule ID 247 //
4985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
4986 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
4987 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
4988 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
4989 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
4990 // MIs[1] Operand 1
4991 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
4992 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
4993 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
4994 // MIs[0] offset
4995 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
4996 GIM_CheckIsSafeToFold, /*NumInsns*/1,
4997 // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
4998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
4999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5000 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5001 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5002 GIR_RootConstrainSelectedInstOperands,
5003 // GIR_Coverage, 247,
5004 GIR_EraseRootFromParent_Done,
5005 // Label 426: @12416
5006 GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(12473), // Rule ID 248 //
5007 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5008 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5009 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5010 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5011 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5012 // MIs[1] Operand 1
5013 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5014 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5015 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5016 // MIs[0] offset
5017 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5018 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5019 // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
5020 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
5021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5022 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5023 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5024 GIR_RootConstrainSelectedInstOperands,
5025 // GIR_Coverage, 248,
5026 GIR_EraseRootFromParent_Done,
5027 // Label 427: @12473
5028 GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(12530), // Rule ID 1109 //
5029 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5030 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5031 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5032 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5033 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5034 // MIs[1] Operand 1
5035 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5036 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5037 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5038 // MIs[0] offset
5039 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5040 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5041 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5044 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5045 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5046 GIR_RootConstrainSelectedInstOperands,
5047 // GIR_Coverage, 1109,
5048 GIR_EraseRootFromParent_Done,
5049 // Label 428: @12530
5050 GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(12587), // Rule ID 1110 //
5051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5052 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5053 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5054 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5055 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5056 // MIs[1] Operand 1
5057 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5058 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5059 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5060 // MIs[0] offset
5061 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5062 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5063 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
5065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5066 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5067 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5068 GIR_RootConstrainSelectedInstOperands,
5069 // GIR_Coverage, 1110,
5070 GIR_EraseRootFromParent_Done,
5071 // Label 429: @12587
5072 GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(12644), // Rule ID 1111 //
5073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5074 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5075 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5076 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5077 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5078 // MIs[1] Operand 1
5079 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5080 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5081 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5082 // MIs[0] offset
5083 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5084 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5085 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5088 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5089 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5090 GIR_RootConstrainSelectedInstOperands,
5091 // GIR_Coverage, 1111,
5092 GIR_EraseRootFromParent_Done,
5093 // Label 430: @12644
5094 GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(12701), // Rule ID 1112 //
5095 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5096 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5097 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5098 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5099 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5100 // MIs[1] Operand 1
5101 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5102 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5103 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5104 // MIs[0] offset
5105 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5106 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5107 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
5108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
5109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5110 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5111 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5112 GIR_RootConstrainSelectedInstOperands,
5113 // GIR_Coverage, 1112,
5114 GIR_EraseRootFromParent_Done,
5115 // Label 431: @12701
5116 GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(12764), // Rule ID 1402 //
5117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5118 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5119 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5120 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5121 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5122 // MIs[1] Operand 1
5123 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5124 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5125 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5126 // MIs[0] dst
5127 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5128 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5129 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5130 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5132 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5133 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5134 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5135 GIR_RootConstrainSelectedInstOperands,
5136 // GIR_Coverage, 1402,
5137 GIR_EraseRootFromParent_Done,
5138 // Label 432: @12764
5139 GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(12827), // Rule ID 1403 //
5140 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5141 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5142 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5143 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5144 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5145 // MIs[1] Operand 1
5146 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5147 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5148 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5149 // MIs[0] dst
5150 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5151 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5152 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5155 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5156 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5157 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5158 GIR_RootConstrainSelectedInstOperands,
5159 // GIR_Coverage, 1403,
5160 GIR_EraseRootFromParent_Done,
5161 // Label 433: @12827
5162 GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(12890), // Rule ID 1546 //
5163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5164 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5165 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5166 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5167 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5168 // MIs[1] Operand 1
5169 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5170 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5171 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5172 // MIs[0] dst
5173 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5174 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5175 // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
5176 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
5177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5178 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5179 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5180 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5181 GIR_RootConstrainSelectedInstOperands,
5182 // GIR_Coverage, 1546,
5183 GIR_EraseRootFromParent_Done,
5184 // Label 434: @12890
5185 GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(12953), // Rule ID 1547 //
5186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5188 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5189 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5190 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5191 // MIs[1] Operand 1
5192 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5193 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5194 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5195 // MIs[0] dst
5196 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5197 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5198 // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
5199 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
5200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5201 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5202 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5203 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5204 GIR_RootConstrainSelectedInstOperands,
5205 // GIR_Coverage, 1547,
5206 GIR_EraseRootFromParent_Done,
5207 // Label 435: @12953
5208 GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(13007), // Rule ID 1830 //
5209 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5210 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5211 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5212 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5213 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5214 // MIs[1] Operand 1
5215 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5216 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5217 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5218 // MIs[0] targ16
5219 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5220 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5221 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
5222 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
5223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5224 GIR_RootToRootCopy, /*OpIdx*/1, // targ16
5225 GIR_RootConstrainSelectedInstOperands,
5226 // GIR_Coverage, 1830,
5227 GIR_EraseRootFromParent_Done,
5228 // Label 436: @13007
5229 GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(13061), // Rule ID 1839 //
5230 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5232 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5233 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5234 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5235 // MIs[1] Operand 1
5236 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5237 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5238 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5239 // MIs[0] targ16
5240 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5241 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5242 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
5243 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
5244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5245 GIR_RootToRootCopy, /*OpIdx*/1, // targ16
5246 GIR_RootConstrainSelectedInstOperands,
5247 // GIR_Coverage, 1839,
5248 GIR_EraseRootFromParent_Done,
5249 // Label 437: @13061
5250 GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(13124), // Rule ID 2167 //
5251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5252 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5253 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5254 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5255 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5256 // MIs[1] Operand 1
5257 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5258 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5259 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5260 // MIs[0] dst
5261 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5262 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5263 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5264 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
5265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5266 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5267 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5268 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5269 GIR_RootConstrainSelectedInstOperands,
5270 // GIR_Coverage, 2167,
5271 GIR_EraseRootFromParent_Done,
5272 // Label 438: @13124
5273 GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(13187), // Rule ID 2168 //
5274 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5275 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5276 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5277 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5278 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5279 // MIs[1] Operand 1
5280 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5281 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5282 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5283 // MIs[0] dst
5284 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5285 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5286 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
5288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5289 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5290 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5291 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5292 GIR_RootConstrainSelectedInstOperands,
5293 // GIR_Coverage, 2168,
5294 GIR_EraseRootFromParent_Done,
5295 // Label 439: @13187
5296 GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(13244), // Rule ID 2314 //
5297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
5298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5300 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5301 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5302 // MIs[1] Operand 1
5303 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5304 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5305 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5306 // MIs[0] dst
5307 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5308 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5309 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5310 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
5311 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5312 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5313 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5314 GIR_RootConstrainSelectedInstOperands,
5315 // GIR_Coverage, 2314,
5316 GIR_EraseRootFromParent_Done,
5317 // Label 440: @13244
5318 GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(13301), // Rule ID 2315 //
5319 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
5320 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5321 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5322 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5323 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5324 // MIs[1] Operand 1
5325 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5326 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5327 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
5328 // MIs[0] dst
5329 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5330 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5331 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5332 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
5333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5334 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5335 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5336 GIR_RootConstrainSelectedInstOperands,
5337 // GIR_Coverage, 2315,
5338 GIR_EraseRootFromParent_Done,
5339 // Label 441: @13301
5340 GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(13353), // Rule ID 1413 //
5341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5342 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5343 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5344 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5345 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5346 // MIs[1] Operand 1
5347 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5348 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5349 // MIs[0] dst
5350 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5351 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5352 // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5353 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
5354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5355 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5356 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5357 GIR_RootConstrainSelectedInstOperands,
5358 // GIR_Coverage, 1413,
5359 GIR_EraseRootFromParent_Done,
5360 // Label 442: @13353
5361 GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(13405), // Rule ID 1414 //
5362 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5363 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5364 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5365 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5366 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5367 // MIs[1] Operand 1
5368 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5369 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
5370 // MIs[0] dst
5371 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5372 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5373 // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5374 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
5375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5376 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5377 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5378 GIR_RootConstrainSelectedInstOperands,
5379 // GIR_Coverage, 1414,
5380 GIR_EraseRootFromParent_Done,
5381 // Label 443: @13405
5382 GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(13457), // Rule ID 1557 //
5383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5384 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5385 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5386 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5387 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5388 // MIs[1] Operand 1
5389 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5390 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5391 // MIs[0] dst
5392 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5393 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5394 // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
5395 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
5396 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5397 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5398 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5399 GIR_RootConstrainSelectedInstOperands,
5400 // GIR_Coverage, 1557,
5401 GIR_EraseRootFromParent_Done,
5402 // Label 444: @13457
5403 GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(13509), // Rule ID 1558 //
5404 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5405 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5406 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5407 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5408 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5409 // MIs[1] Operand 1
5410 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5411 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
5412 // MIs[0] dst
5413 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5414 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5415 // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
5416 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
5417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5418 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5419 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5420 GIR_RootConstrainSelectedInstOperands,
5421 // GIR_Coverage, 1558,
5422 GIR_EraseRootFromParent_Done,
5423 // Label 445: @13509
5424 GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(13561), // Rule ID 2178 //
5425 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5426 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5427 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5428 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5429 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5430 // MIs[1] Operand 1
5431 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5432 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
5433 // MIs[0] dst
5434 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5435 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5436 // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5437 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
5438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5439 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5440 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5441 GIR_RootConstrainSelectedInstOperands,
5442 // GIR_Coverage, 2178,
5443 GIR_EraseRootFromParent_Done,
5444 // Label 446: @13561
5445 GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(13613), // Rule ID 2179 //
5446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5447 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5448 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5449 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5450 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5451 // MIs[1] Operand 1
5452 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5453 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, uint8_t(-1),
5454 // MIs[0] dst
5455 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5456 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5457 // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
5458 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
5459 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5460 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5461 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5462 GIR_RootConstrainSelectedInstOperands,
5463 // GIR_Coverage, 2179,
5464 GIR_EraseRootFromParent_Done,
5465 // Label 447: @13613
5466 GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(13675), // Rule ID 92 //
5467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5468 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5469 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5470 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5471 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5472 // MIs[1] Operand 1
5473 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5474 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5475 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5476 // MIs[0] offset
5477 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5478 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5479 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
5480 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
5483 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5484 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5485 GIR_RootConstrainSelectedInstOperands,
5486 // GIR_Coverage, 92,
5487 GIR_EraseRootFromParent_Done,
5488 // Label 448: @13675
5489 GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(13737), // Rule ID 93 //
5490 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5491 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5492 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5493 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5494 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5495 // MIs[1] Operand 1
5496 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5497 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5498 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5499 // MIs[0] offset
5500 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5501 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5502 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
5503 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
5504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
5506 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5507 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5508 GIR_RootConstrainSelectedInstOperands,
5509 // GIR_Coverage, 93,
5510 GIR_EraseRootFromParent_Done,
5511 // Label 449: @13737
5512 GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(13799), // Rule ID 243 //
5513 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5514 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5515 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5516 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5517 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5518 // MIs[1] Operand 1
5519 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5520 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5521 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5522 // MIs[0] offset
5523 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5524 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5525 // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
5526 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
5527 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5528 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
5529 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5530 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5531 GIR_RootConstrainSelectedInstOperands,
5532 // GIR_Coverage, 243,
5533 GIR_EraseRootFromParent_Done,
5534 // Label 450: @13799
5535 GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(13861), // Rule ID 244 //
5536 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
5537 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5538 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5539 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5540 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5541 // MIs[1] Operand 1
5542 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5543 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5544 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5545 // MIs[0] offset
5546 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5547 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5548 // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
5549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
5550 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
5552 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5553 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5554 GIR_RootConstrainSelectedInstOperands,
5555 // GIR_Coverage, 244,
5556 GIR_EraseRootFromParent_Done,
5557 // Label 451: @13861
5558 GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(13923), // Rule ID 1107 //
5559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5561 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5562 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5563 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5564 // MIs[1] Operand 1
5565 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5566 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5567 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5568 // MIs[0] offset
5569 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5570 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5571 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
5572 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
5573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
5575 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5576 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5577 GIR_RootConstrainSelectedInstOperands,
5578 // GIR_Coverage, 1107,
5579 GIR_EraseRootFromParent_Done,
5580 // Label 452: @13923
5581 GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(13985), // Rule ID 1108 //
5582 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5583 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5584 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5585 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5586 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5587 // MIs[1] Operand 1
5588 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5590 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5591 // MIs[0] offset
5592 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5593 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5594 // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) => (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
5595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
5596 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
5597 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
5598 GIR_RootToRootCopy, /*OpIdx*/1, // offset
5599 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5600 GIR_RootConstrainSelectedInstOperands,
5601 // GIR_Coverage, 1108,
5602 GIR_EraseRootFromParent_Done,
5603 // Label 453: @13985
5604 GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(14070), // Rule ID 1404 //
5605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5606 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5607 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5608 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5609 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5610 // MIs[1] Operand 1
5611 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5613 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5614 // MIs[0] dst
5615 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5616 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5617 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5618 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5619 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
5620 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5621 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5622 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5623 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5625 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5626 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5627 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5628 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5629 GIR_RootConstrainSelectedInstOperands,
5630 // GIR_Coverage, 1404,
5631 GIR_EraseRootFromParent_Done,
5632 // Label 454: @14070
5633 GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(14155), // Rule ID 1405 //
5634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5635 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5636 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5637 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5638 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5639 // MIs[1] Operand 1
5640 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
5641 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5642 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5643 // MIs[0] dst
5644 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5645 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5646 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5647 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5648 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
5649 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5650 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5651 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5652 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5653 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5654 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5655 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5656 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5657 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5658 GIR_RootConstrainSelectedInstOperands,
5659 // GIR_Coverage, 1405,
5660 GIR_EraseRootFromParent_Done,
5661 // Label 455: @14155
5662 GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(14240), // Rule ID 1410 //
5663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5665 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5666 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5667 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5668 // MIs[1] Operand 1
5669 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5670 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5671 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5672 // MIs[0] dst
5673 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5674 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5675 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5676 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5677 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
5678 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5679 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5680 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5681 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5682 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5683 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5684 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5685 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5686 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5687 GIR_RootConstrainSelectedInstOperands,
5688 // GIR_Coverage, 1410,
5689 GIR_EraseRootFromParent_Done,
5690 // Label 456: @14240
5691 GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(14325), // Rule ID 1411 //
5692 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
5693 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5694 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5695 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5696 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5697 // MIs[1] Operand 1
5698 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
5699 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5700 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5701 // MIs[0] dst
5702 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5703 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5704 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5705 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5706 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
5707 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5708 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5709 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5710 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5711 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5712 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5713 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5714 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5715 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5716 GIR_RootConstrainSelectedInstOperands,
5717 // GIR_Coverage, 1411,
5718 GIR_EraseRootFromParent_Done,
5719 // Label 457: @14325
5720 GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(14410), // Rule ID 1548 //
5721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5722 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5723 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5724 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5725 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5726 // MIs[1] Operand 1
5727 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5728 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5729 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5730 // MIs[0] dst
5731 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5732 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5733 // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5734 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5735 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
5736 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5737 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5738 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5739 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5740 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5741 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5742 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5743 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5744 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5745 GIR_RootConstrainSelectedInstOperands,
5746 // GIR_Coverage, 1548,
5747 GIR_EraseRootFromParent_Done,
5748 // Label 458: @14410
5749 GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(14495), // Rule ID 1549 //
5750 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5751 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5752 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5753 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5754 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5755 // MIs[1] Operand 1
5756 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
5757 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5758 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5759 // MIs[0] dst
5760 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5761 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5762 // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5763 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5764 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
5765 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5766 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5767 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5768 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5769 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5770 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5771 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5772 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5773 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5774 GIR_RootConstrainSelectedInstOperands,
5775 // GIR_Coverage, 1549,
5776 GIR_EraseRootFromParent_Done,
5777 // Label 459: @14495
5778 GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(14580), // Rule ID 1554 //
5779 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5780 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5781 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5782 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5783 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5784 // MIs[1] Operand 1
5785 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5786 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5787 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5788 // MIs[0] dst
5789 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5790 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5791 // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5792 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5793 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
5794 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5795 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5796 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5797 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5799 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5800 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5801 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5802 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5803 GIR_RootConstrainSelectedInstOperands,
5804 // GIR_Coverage, 1554,
5805 GIR_EraseRootFromParent_Done,
5806 // Label 460: @14580
5807 GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(14665), // Rule ID 1555 //
5808 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
5809 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5810 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5811 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
5812 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
5813 // MIs[1] Operand 1
5814 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
5815 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5816 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
5817 // MIs[0] dst
5818 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5819 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5820 // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5821 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5822 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
5823 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5824 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5825 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5826 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
5828 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5829 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5830 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5831 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5832 GIR_RootConstrainSelectedInstOperands,
5833 // GIR_Coverage, 1555,
5834 GIR_EraseRootFromParent_Done,
5835 // Label 461: @14665
5836 GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(14724), // Rule ID 1828 //
5837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5838 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5839 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5840 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5841 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5842 // MIs[1] Operand 1
5843 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
5844 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5845 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5846 // MIs[0] imm16
5847 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5848 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5849 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
5850 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
5851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
5853 GIR_RootToRootCopy, /*OpIdx*/1, // imm16
5854 GIR_RootConstrainSelectedInstOperands,
5855 // GIR_Coverage, 1828,
5856 GIR_EraseRootFromParent_Done,
5857 // Label 462: @14724
5858 GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(14783), // Rule ID 1831 //
5859 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5860 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5861 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5862 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5863 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5864 // MIs[1] Operand 1
5865 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
5866 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5867 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5868 // MIs[0] imm16
5869 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5870 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5871 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
5872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
5873 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
5874 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5875 GIR_RootToRootCopy, /*OpIdx*/1, // imm16
5876 GIR_RootConstrainSelectedInstOperands,
5877 // GIR_Coverage, 1831,
5878 GIR_EraseRootFromParent_Done,
5879 // Label 463: @14783
5880 GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(14842), // Rule ID 1832 //
5881 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5882 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5883 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5884 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5885 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5886 // MIs[1] Operand 1
5887 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5888 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5889 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5890 // MIs[0] imm16
5891 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5892 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5893 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
5894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
5895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
5897 GIR_RootToRootCopy, /*OpIdx*/1, // imm16
5898 GIR_RootConstrainSelectedInstOperands,
5899 // GIR_Coverage, 1832,
5900 GIR_EraseRootFromParent_Done,
5901 // Label 464: @14842
5902 GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(14901), // Rule ID 1834 //
5903 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5905 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5906 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5907 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5908 // MIs[1] Operand 1
5909 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
5910 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5911 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5912 // MIs[0] imm16
5913 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5914 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5915 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
5916 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
5917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
5919 GIR_RootToRootCopy, /*OpIdx*/1, // imm16
5920 GIR_RootConstrainSelectedInstOperands,
5921 // GIR_Coverage, 1834,
5922 GIR_EraseRootFromParent_Done,
5923 // Label 465: @14901
5924 GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(14960), // Rule ID 1836 //
5925 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5926 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5927 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5928 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5929 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5930 // MIs[1] Operand 1
5931 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
5932 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5933 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5934 // MIs[0] imm16
5935 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5936 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5937 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
5938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
5939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
5940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5941 GIR_RootToRootCopy, /*OpIdx*/1, // imm16
5942 GIR_RootConstrainSelectedInstOperands,
5943 // GIR_Coverage, 1836,
5944 GIR_EraseRootFromParent_Done,
5945 // Label 466: @14960
5946 GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(15019), // Rule ID 1837 //
5947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
5948 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5949 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5950 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5951 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5952 // MIs[1] Operand 1
5953 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
5954 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5955 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
5956 // MIs[0] imm16
5957 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5958 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5959 // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) => (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
5960 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
5961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
5962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
5963 GIR_RootToRootCopy, /*OpIdx*/1, // imm16
5964 GIR_RootConstrainSelectedInstOperands,
5965 // GIR_Coverage, 1837,
5966 GIR_EraseRootFromParent_Done,
5967 // Label 467: @15019
5968 GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(15104), // Rule ID 2169 //
5969 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5970 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
5971 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
5972 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5973 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
5974 // MIs[1] Operand 1
5975 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
5976 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5977 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
5978 // MIs[0] dst
5979 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
5980 GIM_CheckIsSafeToFold, /*NumInsns*/1,
5981 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
5982 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
5983 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
5984 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
5985 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
5986 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
5987 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
5988 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
5989 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5990 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5991 GIR_RootToRootCopy, /*OpIdx*/1, // dst
5992 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
5993 GIR_RootConstrainSelectedInstOperands,
5994 // GIR_Coverage, 2169,
5995 GIR_EraseRootFromParent_Done,
5996 // Label 468: @15104
5997 GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(15189), // Rule ID 2170 //
5998 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
5999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6000 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6001 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6002 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6003 // MIs[1] Operand 1
6004 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6005 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6006 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6007 // MIs[0] dst
6008 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6009 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6010 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6011 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6012 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6013 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6014 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6015 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6016 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6018 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6019 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6020 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6021 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6022 GIR_RootConstrainSelectedInstOperands,
6023 // GIR_Coverage, 2170,
6024 GIR_EraseRootFromParent_Done,
6025 // Label 469: @15189
6026 GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(15274), // Rule ID 2175 //
6027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6028 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6029 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6030 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6031 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6032 // MIs[1] Operand 1
6033 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6034 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6035 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6036 // MIs[0] dst
6037 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6038 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6039 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6040 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6041 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6042 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6043 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6044 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6045 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6047 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6048 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6049 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6050 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6051 GIR_RootConstrainSelectedInstOperands,
6052 // GIR_Coverage, 2175,
6053 GIR_EraseRootFromParent_Done,
6054 // Label 470: @15274
6055 GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(15359), // Rule ID 2176 //
6056 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6057 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6058 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6059 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6060 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6061 // MIs[1] Operand 1
6062 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6065 // MIs[0] dst
6066 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6067 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6068 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6069 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6070 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6071 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6072 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6073 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6074 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
6076 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6077 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6078 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6079 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6080 GIR_RootConstrainSelectedInstOperands,
6081 // GIR_Coverage, 2176,
6082 GIR_EraseRootFromParent_Done,
6083 // Label 471: @15359
6084 GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(15438), // Rule ID 2316 //
6085 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6086 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6087 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6088 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6089 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6090 // MIs[1] Operand 1
6091 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
6092 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6093 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6094 // MIs[0] dst
6095 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6096 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6097 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
6098 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6099 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6100 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6101 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6102 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6103 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6104 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6105 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6106 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6107 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6108 GIR_RootConstrainSelectedInstOperands,
6109 // GIR_Coverage, 2316,
6110 GIR_EraseRootFromParent_Done,
6111 // Label 472: @15438
6112 GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(15517), // Rule ID 2317 //
6113 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6114 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6115 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6116 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6117 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6118 // MIs[1] Operand 1
6119 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
6120 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6121 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6122 // MIs[0] dst
6123 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6124 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6125 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
6126 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6127 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6128 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6129 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6130 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6131 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6132 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6133 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6134 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6135 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6136 GIR_RootConstrainSelectedInstOperands,
6137 // GIR_Coverage, 2317,
6138 GIR_EraseRootFromParent_Done,
6139 // Label 473: @15517
6140 GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(15596), // Rule ID 2322 //
6141 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6142 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6143 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6144 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6145 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6146 // MIs[1] Operand 1
6147 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
6148 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6149 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6150 // MIs[0] dst
6151 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6152 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6153 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
6154 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6155 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
6156 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6157 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6158 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6159 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6160 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6161 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6162 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6163 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6164 GIR_RootConstrainSelectedInstOperands,
6165 // GIR_Coverage, 2322,
6166 GIR_EraseRootFromParent_Done,
6167 // Label 474: @15596
6168 GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(15675), // Rule ID 2323 //
6169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
6171 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
6172 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6173 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
6174 // MIs[1] Operand 1
6175 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
6176 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6177 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6178 // MIs[0] dst
6179 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6180 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6181 // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) => (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
6182 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
6183 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
6184 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
6185 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
6186 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
6187 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
6188 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
6189 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6190 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6191 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6192 GIR_RootConstrainSelectedInstOperands,
6193 // GIR_Coverage, 2323,
6194 GIR_EraseRootFromParent_Done,
6195 // Label 475: @15675
6196 GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(15708), // Rule ID 1412 //
6197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
6198 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6199 // MIs[0] dst
6200 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6201 // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6202 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
6203 GIR_RootToRootCopy, /*OpIdx*/0, // cond
6204 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6205 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6206 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6207 GIR_RootConstrainSelectedInstOperands,
6208 // GIR_Coverage, 1412,
6209 GIR_EraseRootFromParent_Done,
6210 // Label 476: @15708
6211 GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(15730), // Rule ID 1840 //
6212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
6213 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
6214 // MIs[0] targ16
6215 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6216 // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) => (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
6217 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
6218 GIR_RootConstrainSelectedInstOperands,
6219 // GIR_Coverage, 1840,
6220 GIR_Done,
6221 // Label 477: @15730
6222 GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(15763), // Rule ID 2177 //
6223 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
6224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6225 // MIs[0] dst
6226 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6227 // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
6228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
6229 GIR_RootToRootCopy, /*OpIdx*/0, // cond
6230 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6231 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6232 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6233 GIR_RootConstrainSelectedInstOperands,
6234 // GIR_Coverage, 2177,
6235 GIR_EraseRootFromParent_Done,
6236 // Label 478: @15763
6237 GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(15791), // Rule ID 2324 //
6238 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
6239 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6240 // MIs[0] dst
6241 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6242 // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) => (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
6243 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
6244 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
6245 GIR_RootConstrainSelectedInstOperands,
6246 // GIR_Coverage, 2324,
6247 GIR_Done,
6248 // Label 479: @15791
6249 GIM_Reject,
6250 // Label 410: @15792
6251 GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(15825), // Rule ID 1556 //
6252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
6253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
6254 // MIs[0] dst
6255 GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
6256 // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) => (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
6257 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
6258 GIR_RootToRootCopy, /*OpIdx*/0, // cond
6259 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6260 GIR_RootToRootCopy, /*OpIdx*/1, // dst
6261 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
6262 GIR_RootConstrainSelectedInstOperands,
6263 // GIR_Coverage, 1556,
6264 GIR_EraseRootFromParent_Done,
6265 // Label 480: @15825
6266 GIM_Reject,
6267 // Label 411: @15826
6268 GIM_Reject,
6269 // Label 17: @15827
6270 GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(17824),
6271 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
6272 GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(15882), // Rule ID 428 //
6273 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6274 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
6275 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
6276 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6277 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6278 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6279 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6280 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
6281 // MIs[1] Operand 1
6282 // No operand predicates
6283 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6284 // (intrinsic_wo_chain:{ *:[v4i8] } 7714:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
6285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
6286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6287 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6288 GIR_RootConstrainSelectedInstOperands,
6289 // GIR_Coverage, 428,
6290 GIR_EraseRootFromParent_Done,
6291 // Label 482: @15882
6292 GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(15929), // Rule ID 429 //
6293 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6294 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
6295 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6296 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6300 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
6301 // MIs[1] Operand 1
6302 // No operand predicates
6303 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6304 // (intrinsic_wo_chain:{ *:[v2i16] } 7713:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
6305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
6306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6307 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6308 GIR_RootConstrainSelectedInstOperands,
6309 // GIR_Coverage, 429,
6310 GIR_EraseRootFromParent_Done,
6311 // Label 483: @15929
6312 GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(15976), // Rule ID 1288 //
6313 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6314 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
6315 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6316 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6317 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6318 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6319 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6320 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
6321 // MIs[1] Operand 1
6322 // No operand predicates
6323 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6324 // (intrinsic_wo_chain:{ *:[v2i16] } 7713:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
6325 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
6326 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6327 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6328 GIR_RootConstrainSelectedInstOperands,
6329 // GIR_Coverage, 1288,
6330 GIR_EraseRootFromParent_Done,
6331 // Label 484: @15976
6332 GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(16023), // Rule ID 1289 //
6333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
6335 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
6336 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6338 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6339 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6340 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
6341 // MIs[1] Operand 1
6342 // No operand predicates
6343 GIM_CheckIsSafeToFold, /*NumInsns*/1,
6344 // (intrinsic_wo_chain:{ *:[v4i8] } 7714:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
6345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
6346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6347 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6348 GIR_RootConstrainSelectedInstOperands,
6349 // GIR_Coverage, 1289,
6350 GIR_EraseRootFromParent_Done,
6351 // Label 485: @16023
6352 GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(16059), // Rule ID 362 //
6353 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
6355 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6356 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6358 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6359 // (intrinsic_wo_chain:{ *:[i32] } 7711:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
6360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
6361 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6362 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6363 GIR_RootConstrainSelectedInstOperands,
6364 // GIR_Coverage, 362,
6365 GIR_EraseRootFromParent_Done,
6366 // Label 486: @16059
6367 GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(16095), // Rule ID 369 //
6368 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6369 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
6370 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6371 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
6372 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6373 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6374 // (intrinsic_wo_chain:{ *:[i32] } 7693:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
6375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
6376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6377 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6378 GIR_RootConstrainSelectedInstOperands,
6379 // GIR_Coverage, 369,
6380 GIR_EraseRootFromParent_Done,
6381 // Label 487: @16095
6382 GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(16131), // Rule ID 370 //
6383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6384 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
6385 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6386 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
6387 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6388 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6389 // (intrinsic_wo_chain:{ *:[i32] } 7694:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
6390 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
6391 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6392 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6393 GIR_RootConstrainSelectedInstOperands,
6394 // GIR_Coverage, 370,
6395 GIR_EraseRootFromParent_Done,
6396 // Label 488: @16131
6397 GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(16167), // Rule ID 371 //
6398 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6399 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
6400 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6401 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6402 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6403 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6404 // (intrinsic_wo_chain:{ *:[v2i16] } 7695:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
6406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6407 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6408 GIR_RootConstrainSelectedInstOperands,
6409 // GIR_Coverage, 371,
6410 GIR_EraseRootFromParent_Done,
6411 // Label 489: @16167
6412 GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(16203), // Rule ID 372 //
6413 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
6415 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6416 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6417 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6418 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6419 // (intrinsic_wo_chain:{ *:[v2i16] } 7697:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6420 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
6421 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6422 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6423 GIR_RootConstrainSelectedInstOperands,
6424 // GIR_Coverage, 372,
6425 GIR_EraseRootFromParent_Done,
6426 // Label 490: @16203
6427 GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(16239), // Rule ID 373 //
6428 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6429 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
6430 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6431 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6432 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6433 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6434 // (intrinsic_wo_chain:{ *:[v2i16] } 7696:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
6436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6437 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6438 GIR_RootConstrainSelectedInstOperands,
6439 // GIR_Coverage, 373,
6440 GIR_EraseRootFromParent_Done,
6441 // Label 491: @16239
6442 GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(16275), // Rule ID 374 //
6443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6444 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
6445 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6446 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6448 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6449 // (intrinsic_wo_chain:{ *:[v2i16] } 7698:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
6451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6452 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6453 GIR_RootConstrainSelectedInstOperands,
6454 // GIR_Coverage, 374,
6455 GIR_EraseRootFromParent_Done,
6456 // Label 492: @16275
6457 GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(16311), // Rule ID 375 //
6458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
6460 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6461 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6462 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6463 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6464 // (intrinsic_wo_chain:{ *:[v2i16] } 7699:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6465 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
6466 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6467 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6468 GIR_RootConstrainSelectedInstOperands,
6469 // GIR_Coverage, 375,
6470 GIR_EraseRootFromParent_Done,
6471 // Label 493: @16311
6472 GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(16347), // Rule ID 376 //
6473 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6474 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
6475 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6476 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6477 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6478 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6479 // (intrinsic_wo_chain:{ *:[v2i16] } 7701:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6480 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
6481 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6482 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6483 GIR_RootConstrainSelectedInstOperands,
6484 // GIR_Coverage, 376,
6485 GIR_EraseRootFromParent_Done,
6486 // Label 494: @16347
6487 GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(16383), // Rule ID 377 //
6488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
6490 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6491 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6492 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6493 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6494 // (intrinsic_wo_chain:{ *:[v2i16] } 7700:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
6496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6497 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6498 GIR_RootConstrainSelectedInstOperands,
6499 // GIR_Coverage, 377,
6500 GIR_EraseRootFromParent_Done,
6501 // Label 495: @16383
6502 GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(16419), // Rule ID 378 //
6503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
6505 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6506 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6507 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6508 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6509 // (intrinsic_wo_chain:{ *:[v2i16] } 7702:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
6510 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
6511 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6512 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6513 GIR_RootConstrainSelectedInstOperands,
6514 // GIR_Coverage, 378,
6515 GIR_EraseRootFromParent_Done,
6516 // Label 496: @16419
6517 GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(16455), // Rule ID 426 //
6518 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6519 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
6520 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6521 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6522 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6523 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6524 // (intrinsic_wo_chain:{ *:[i32] } 7267:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
6525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
6526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6527 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6528 GIR_RootConstrainSelectedInstOperands,
6529 // GIR_Coverage, 426,
6530 GIR_EraseRootFromParent_Done,
6531 // Label 497: @16455
6532 GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(16491), // Rule ID 430 //
6533 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
6535 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
6536 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6537 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6538 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6539 // (intrinsic_wo_chain:{ *:[v4i8] } 7714:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
6540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
6541 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6542 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6543 GIR_RootConstrainSelectedInstOperands,
6544 // GIR_Coverage, 430,
6545 GIR_EraseRootFromParent_Done,
6546 // Label 498: @16491
6547 GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(16527), // Rule ID 431 //
6548 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
6549 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
6550 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6551 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6553 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6554 // (intrinsic_wo_chain:{ *:[v2i16] } 7713:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
6555 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
6556 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
6557 GIR_RootToRootCopy, /*OpIdx*/2, // rt
6558 GIR_RootConstrainSelectedInstOperands,
6559 // GIR_Coverage, 431,
6560 GIR_EraseRootFromParent_Done,
6561 // Label 499: @16527
6562 GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(16563), // Rule ID 680 //
6563 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6564 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
6565 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6566 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6567 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6568 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6569 // (intrinsic_wo_chain:{ *:[v4i32] } 7419:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6570 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
6571 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6572 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6573 GIR_RootConstrainSelectedInstOperands,
6574 // GIR_Coverage, 680,
6575 GIR_EraseRootFromParent_Done,
6576 // Label 500: @16563
6577 GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(16599), // Rule ID 681 //
6578 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6579 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
6580 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6581 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
6582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6583 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6584 // (intrinsic_wo_chain:{ *:[v2i64] } 7418:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
6585 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
6586 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6587 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6588 GIR_RootConstrainSelectedInstOperands,
6589 // GIR_Coverage, 681,
6590 GIR_EraseRootFromParent_Done,
6591 // Label 501: @16599
6592 GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(16635), // Rule ID 704 //
6593 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
6595 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6598 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
6599 // (intrinsic_wo_chain:{ *:[v4f32] } 7445:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
6600 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
6601 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6602 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6603 GIR_RootConstrainSelectedInstOperands,
6604 // GIR_Coverage, 704,
6605 GIR_EraseRootFromParent_Done,
6606 // Label 502: @16635
6607 GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(16671), // Rule ID 705 //
6608 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6609 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
6610 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6613 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6614 // (intrinsic_wo_chain:{ *:[v2f64] } 7444:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
6616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6617 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6618 GIR_RootConstrainSelectedInstOperands,
6619 // GIR_Coverage, 705,
6620 GIR_EraseRootFromParent_Done,
6621 // Label 503: @16671
6622 GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(16707), // Rule ID 706 //
6623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6624 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
6625 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6626 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6627 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6628 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
6629 // (intrinsic_wo_chain:{ *:[v4f32] } 7447:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
6630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
6631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6632 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6633 GIR_RootConstrainSelectedInstOperands,
6634 // GIR_Coverage, 706,
6635 GIR_EraseRootFromParent_Done,
6636 // Label 504: @16707
6637 GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(16743), // Rule ID 707 //
6638 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6639 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
6640 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6641 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6643 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6644 // (intrinsic_wo_chain:{ *:[v2f64] } 7446:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6645 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
6646 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6647 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6648 GIR_RootConstrainSelectedInstOperands,
6649 // GIR_Coverage, 707,
6650 GIR_EraseRootFromParent_Done,
6651 // Label 505: @16743
6652 GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(16779), // Rule ID 712 //
6653 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6654 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
6655 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6656 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6657 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6658 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
6659 // (intrinsic_wo_chain:{ *:[v4f32] } 7453:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
6660 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
6661 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6662 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6663 GIR_RootConstrainSelectedInstOperands,
6664 // GIR_Coverage, 712,
6665 GIR_EraseRootFromParent_Done,
6666 // Label 506: @16779
6667 GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(16815), // Rule ID 713 //
6668 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
6670 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6673 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6674 // (intrinsic_wo_chain:{ *:[v2f64] } 7452:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
6675 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
6676 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6677 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6678 GIR_RootConstrainSelectedInstOperands,
6679 // GIR_Coverage, 713,
6680 GIR_EraseRootFromParent_Done,
6681 // Label 507: @16815
6682 GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(16851), // Rule ID 714 //
6683 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
6685 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6686 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6687 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6688 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
6689 // (intrinsic_wo_chain:{ *:[v4f32] } 7455:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
6690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
6691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6692 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6693 GIR_RootConstrainSelectedInstOperands,
6694 // GIR_Coverage, 714,
6695 GIR_EraseRootFromParent_Done,
6696 // Label 508: @16851
6697 GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(16887), // Rule ID 715 //
6698 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6699 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
6700 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6701 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6702 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6703 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6704 // (intrinsic_wo_chain:{ *:[v2f64] } 7454:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
6705 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
6706 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6707 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6708 GIR_RootConstrainSelectedInstOperands,
6709 // GIR_Coverage, 715,
6710 GIR_EraseRootFromParent_Done,
6711 // Label 509: @16887
6712 GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(16923), // Rule ID 740 //
6713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
6715 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6716 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6718 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6719 // (intrinsic_wo_chain:{ *:[v4f32] } 7477:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
6721 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6722 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6723 GIR_RootConstrainSelectedInstOperands,
6724 // GIR_Coverage, 740,
6725 GIR_EraseRootFromParent_Done,
6726 // Label 510: @16923
6727 GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(16959), // Rule ID 741 //
6728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6729 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
6730 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6731 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
6732 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6733 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6734 // (intrinsic_wo_chain:{ *:[v2f64] } 7476:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
6735 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
6736 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6737 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6738 GIR_RootConstrainSelectedInstOperands,
6739 // GIR_Coverage, 741,
6740 GIR_EraseRootFromParent_Done,
6741 // Label 511: @16959
6742 GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(16995), // Rule ID 742 //
6743 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6744 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
6745 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6746 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6747 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6748 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6749 // (intrinsic_wo_chain:{ *:[v4f32] } 7481:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
6751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6752 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6753 GIR_RootConstrainSelectedInstOperands,
6754 // GIR_Coverage, 742,
6755 GIR_EraseRootFromParent_Done,
6756 // Label 512: @16995
6757 GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(17031), // Rule ID 743 //
6758 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6759 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
6760 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6761 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
6762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6763 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6764 // (intrinsic_wo_chain:{ *:[v2f64] } 7480:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
6765 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
6766 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6767 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6768 GIR_RootConstrainSelectedInstOperands,
6769 // GIR_Coverage, 743,
6770 GIR_EraseRootFromParent_Done,
6771 // Label 513: @17031
6772 GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(17067), // Rule ID 770 //
6773 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6774 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
6775 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6776 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6777 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6778 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6779 // (intrinsic_wo_chain:{ *:[v4i32] } 7509:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6780 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
6781 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6782 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6783 GIR_RootConstrainSelectedInstOperands,
6784 // GIR_Coverage, 770,
6785 GIR_EraseRootFromParent_Done,
6786 // Label 514: @17067
6787 GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(17103), // Rule ID 771 //
6788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6789 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
6790 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6791 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
6792 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6793 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6794 // (intrinsic_wo_chain:{ *:[v2i64] } 7508:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
6795 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
6796 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6797 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6798 GIR_RootConstrainSelectedInstOperands,
6799 // GIR_Coverage, 771,
6800 GIR_EraseRootFromParent_Done,
6801 // Label 515: @17103
6802 GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(17139), // Rule ID 772 //
6803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
6805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6807 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6808 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6809 // (intrinsic_wo_chain:{ *:[v4i32] } 7511:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
6810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
6811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6812 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6813 GIR_RootConstrainSelectedInstOperands,
6814 // GIR_Coverage, 772,
6815 GIR_EraseRootFromParent_Done,
6816 // Label 516: @17139
6817 GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(17175), // Rule ID 773 //
6818 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6819 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
6820 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6821 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
6822 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6823 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6824 // (intrinsic_wo_chain:{ *:[v2i64] } 7510:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
6825 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
6826 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6827 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6828 GIR_RootConstrainSelectedInstOperands,
6829 // GIR_Coverage, 773,
6830 GIR_EraseRootFromParent_Done,
6831 // Label 517: @17175
6832 GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(17211), // Rule ID 908 //
6833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
6835 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
6836 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
6837 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
6838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
6839 // (intrinsic_wo_chain:{ *:[v16i8] } 7666:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
6840 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
6841 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6842 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6843 GIR_RootConstrainSelectedInstOperands,
6844 // GIR_Coverage, 908,
6845 GIR_EraseRootFromParent_Done,
6846 // Label 518: @17211
6847 GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(17247), // Rule ID 909 //
6848 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6849 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
6850 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
6851 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6852 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
6853 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
6854 // (intrinsic_wo_chain:{ *:[v8i16] } 7668:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
6855 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
6856 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6857 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6858 GIR_RootConstrainSelectedInstOperands,
6859 // GIR_Coverage, 909,
6860 GIR_EraseRootFromParent_Done,
6861 // Label 519: @17247
6862 GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(17283), // Rule ID 910 //
6863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6864 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
6865 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
6866 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6867 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6868 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
6869 // (intrinsic_wo_chain:{ *:[v4i32] } 7669:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
6870 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
6871 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6872 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6873 GIR_RootConstrainSelectedInstOperands,
6874 // GIR_Coverage, 910,
6875 GIR_EraseRootFromParent_Done,
6876 // Label 520: @17283
6877 GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(17319), // Rule ID 911 //
6878 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
6879 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
6880 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
6881 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
6882 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6883 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
6884 // (intrinsic_wo_chain:{ *:[v2i64] } 7667:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
6885 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
6886 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
6887 GIR_RootToRootCopy, /*OpIdx*/2, // ws
6888 GIR_RootConstrainSelectedInstOperands,
6889 // GIR_Coverage, 911,
6890 GIR_EraseRootFromParent_Done,
6891 // Label 521: @17319
6892 GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(17355), // Rule ID 1251 //
6893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
6895 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6896 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
6897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6898 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6899 // (intrinsic_wo_chain:{ *:[i32] } 7693:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
6900 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
6901 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6902 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6903 GIR_RootConstrainSelectedInstOperands,
6904 // GIR_Coverage, 1251,
6905 GIR_EraseRootFromParent_Done,
6906 // Label 522: @17355
6907 GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(17391), // Rule ID 1252 //
6908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6909 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
6910 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6911 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
6912 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
6913 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6914 // (intrinsic_wo_chain:{ *:[i32] } 7694:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
6915 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
6916 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6917 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6918 GIR_RootConstrainSelectedInstOperands,
6919 // GIR_Coverage, 1252,
6920 GIR_EraseRootFromParent_Done,
6921 // Label 523: @17391
6922 GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(17427), // Rule ID 1253 //
6923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
6925 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6926 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6928 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6929 // (intrinsic_wo_chain:{ *:[v2i16] } 7695:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
6930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
6931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6932 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6933 GIR_RootConstrainSelectedInstOperands,
6934 // GIR_Coverage, 1253,
6935 GIR_EraseRootFromParent_Done,
6936 // Label 524: @17427
6937 GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(17463), // Rule ID 1254 //
6938 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6939 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
6940 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6941 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6944 // (intrinsic_wo_chain:{ *:[v2i16] } 7696:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
6945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
6946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6947 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6948 GIR_RootConstrainSelectedInstOperands,
6949 // GIR_Coverage, 1254,
6950 GIR_EraseRootFromParent_Done,
6951 // Label 525: @17463
6952 GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(17499), // Rule ID 1255 //
6953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6954 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
6955 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6956 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6958 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6959 // (intrinsic_wo_chain:{ *:[v2i16] } 7697:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
6960 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
6961 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6962 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6963 GIR_RootConstrainSelectedInstOperands,
6964 // GIR_Coverage, 1255,
6965 GIR_EraseRootFromParent_Done,
6966 // Label 526: @17499
6967 GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(17535), // Rule ID 1256 //
6968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
6970 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6972 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6973 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6974 // (intrinsic_wo_chain:{ *:[v2i16] } 7698:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
6975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
6976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6977 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6978 GIR_RootConstrainSelectedInstOperands,
6979 // GIR_Coverage, 1256,
6980 GIR_EraseRootFromParent_Done,
6981 // Label 527: @17535
6982 GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(17571), // Rule ID 1257 //
6983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
6985 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
6986 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
6987 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6988 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
6989 // (intrinsic_wo_chain:{ *:[v2i16] } 7699:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
6990 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
6991 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
6992 GIR_RootToRootCopy, /*OpIdx*/2, // rs
6993 GIR_RootConstrainSelectedInstOperands,
6994 // GIR_Coverage, 1257,
6995 GIR_EraseRootFromParent_Done,
6996 // Label 528: @17571
6997 GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(17607), // Rule ID 1258 //
6998 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
6999 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
7000 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7001 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7002 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7003 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7004 // (intrinsic_wo_chain:{ *:[v2i16] } 7700:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7005 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
7006 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7007 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7008 GIR_RootConstrainSelectedInstOperands,
7009 // GIR_Coverage, 1258,
7010 GIR_EraseRootFromParent_Done,
7011 // Label 529: @17607
7012 GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(17643), // Rule ID 1259 //
7013 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7014 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
7015 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7016 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7017 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7018 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7019 // (intrinsic_wo_chain:{ *:[v2i16] } 7701:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7020 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
7021 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7022 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7023 GIR_RootConstrainSelectedInstOperands,
7024 // GIR_Coverage, 1259,
7025 GIR_EraseRootFromParent_Done,
7026 // Label 530: @17643
7027 GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(17679), // Rule ID 1260 //
7028 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7029 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
7030 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7031 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7033 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7034 // (intrinsic_wo_chain:{ *:[v2i16] } 7702:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
7035 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
7036 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7037 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7038 GIR_RootConstrainSelectedInstOperands,
7039 // GIR_Coverage, 1260,
7040 GIR_EraseRootFromParent_Done,
7041 // Label 531: @17679
7042 GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(17715), // Rule ID 1286 //
7043 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
7045 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7046 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7047 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7048 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7049 // (intrinsic_wo_chain:{ *:[i32] } 7711:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
7050 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
7051 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7052 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7053 GIR_RootConstrainSelectedInstOperands,
7054 // GIR_Coverage, 1286,
7055 GIR_EraseRootFromParent_Done,
7056 // Label 532: @17715
7057 GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(17751), // Rule ID 1290 //
7058 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7059 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
7060 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7061 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7062 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7063 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7064 // (intrinsic_wo_chain:{ *:[v2i16] } 7713:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
7065 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
7066 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7067 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7068 GIR_RootConstrainSelectedInstOperands,
7069 // GIR_Coverage, 1290,
7070 GIR_EraseRootFromParent_Done,
7071 // Label 533: @17751
7072 GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(17787), // Rule ID 1291 //
7073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
7075 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7077 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7078 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7079 // (intrinsic_wo_chain:{ *:[v4i8] } 7714:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
7080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
7081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7082 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7083 GIR_RootConstrainSelectedInstOperands,
7084 // GIR_Coverage, 1291,
7085 GIR_EraseRootFromParent_Done,
7086 // Label 534: @17787
7087 GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(17823), // Rule ID 1301 //
7088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
7090 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7091 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7092 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7093 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7094 // (intrinsic_wo_chain:{ *:[i32] } 7267:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
7095 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
7096 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7097 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7098 GIR_RootConstrainSelectedInstOperands,
7099 // GIR_Coverage, 1301,
7100 GIR_EraseRootFromParent_Done,
7101 // Label 535: @17823
7102 GIM_Reject,
7103 // Label 481: @17824
7104 GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(27577),
7105 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
7106 GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(17878), // Rule ID 938 //
7107 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
7109 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7110 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7111 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7112 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7113 // MIs[0] m
7114 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7115 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
7116 // (intrinsic_wo_chain:{ *:[v16i8] } 7715:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
7117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
7118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7119 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7120 GIR_RootToRootCopy, /*OpIdx*/3, // m
7121 GIR_RootConstrainSelectedInstOperands,
7122 // GIR_Coverage, 938,
7123 GIR_EraseRootFromParent_Done,
7124 // Label 537: @17878
7125 GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(17924), // Rule ID 939 //
7126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7127 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
7128 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7129 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7130 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7131 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7132 // MIs[0] m
7133 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7134 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
7135 // (intrinsic_wo_chain:{ *:[v8i16] } 7717:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
7136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
7137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7138 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7139 GIR_RootToRootCopy, /*OpIdx*/3, // m
7140 GIR_RootConstrainSelectedInstOperands,
7141 // GIR_Coverage, 939,
7142 GIR_EraseRootFromParent_Done,
7143 // Label 538: @17924
7144 GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(17970), // Rule ID 940 //
7145 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
7147 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7148 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7149 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7150 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7151 // MIs[0] m
7152 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7153 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
7154 // (intrinsic_wo_chain:{ *:[v4i32] } 7718:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
7155 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
7156 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7157 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7158 GIR_RootToRootCopy, /*OpIdx*/3, // m
7159 GIR_RootConstrainSelectedInstOperands,
7160 // GIR_Coverage, 940,
7161 GIR_EraseRootFromParent_Done,
7162 // Label 539: @17970
7163 GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(18016), // Rule ID 941 //
7164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7165 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
7166 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7167 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7168 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7169 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7170 // MIs[0] m
7171 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7172 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
7173 // (intrinsic_wo_chain:{ *:[v2i64] } 7716:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
7174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
7175 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7176 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7177 GIR_RootToRootCopy, /*OpIdx*/3, // m
7178 GIR_RootConstrainSelectedInstOperands,
7179 // GIR_Coverage, 941,
7180 GIR_EraseRootFromParent_Done,
7181 // Label 540: @18016
7182 GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(18062), // Rule ID 942 //
7183 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7184 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
7185 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7188 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7189 // MIs[0] m
7190 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7191 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
7192 // (intrinsic_wo_chain:{ *:[v16i8] } 7719:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
7193 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
7194 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7195 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7196 GIR_RootToRootCopy, /*OpIdx*/3, // m
7197 GIR_RootConstrainSelectedInstOperands,
7198 // GIR_Coverage, 942,
7199 GIR_EraseRootFromParent_Done,
7200 // Label 541: @18062
7201 GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(18108), // Rule ID 943 //
7202 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7203 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
7204 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7205 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7206 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7207 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7208 // MIs[0] m
7209 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7210 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
7211 // (intrinsic_wo_chain:{ *:[v8i16] } 7721:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
7212 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
7213 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7214 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7215 GIR_RootToRootCopy, /*OpIdx*/3, // m
7216 GIR_RootConstrainSelectedInstOperands,
7217 // GIR_Coverage, 943,
7218 GIR_EraseRootFromParent_Done,
7219 // Label 542: @18108
7220 GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(18154), // Rule ID 944 //
7221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7222 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
7223 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7224 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7225 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7226 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7227 // MIs[0] m
7228 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7229 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
7230 // (intrinsic_wo_chain:{ *:[v4i32] } 7722:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
7231 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
7232 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7233 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7234 GIR_RootToRootCopy, /*OpIdx*/3, // m
7235 GIR_RootConstrainSelectedInstOperands,
7236 // GIR_Coverage, 944,
7237 GIR_EraseRootFromParent_Done,
7238 // Label 543: @18154
7239 GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(18200), // Rule ID 945 //
7240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7241 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
7242 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7243 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7244 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7245 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7246 // MIs[0] m
7247 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7248 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
7249 // (intrinsic_wo_chain:{ *:[v2i64] } 7720:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
7250 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
7251 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7252 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7253 GIR_RootToRootCopy, /*OpIdx*/3, // m
7254 GIR_RootConstrainSelectedInstOperands,
7255 // GIR_Coverage, 945,
7256 GIR_EraseRootFromParent_Done,
7257 // Label 544: @18200
7258 GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(18246), // Rule ID 985 //
7259 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7260 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
7261 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7262 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7263 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7264 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7265 // MIs[0] m
7266 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7267 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
7268 // (intrinsic_wo_chain:{ *:[v16i8] } 7774:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
7269 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
7270 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7271 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7272 GIR_RootToRootCopy, /*OpIdx*/3, // m
7273 GIR_RootConstrainSelectedInstOperands,
7274 // GIR_Coverage, 985,
7275 GIR_EraseRootFromParent_Done,
7276 // Label 545: @18246
7277 GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(18292), // Rule ID 986 //
7278 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7279 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
7280 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7281 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7282 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7283 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7284 // MIs[0] m
7285 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7286 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
7287 // (intrinsic_wo_chain:{ *:[v8i16] } 7776:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
7288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
7289 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7290 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7291 GIR_RootToRootCopy, /*OpIdx*/3, // m
7292 GIR_RootConstrainSelectedInstOperands,
7293 // GIR_Coverage, 986,
7294 GIR_EraseRootFromParent_Done,
7295 // Label 546: @18292
7296 GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(18338), // Rule ID 987 //
7297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
7299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7301 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7302 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7303 // MIs[0] m
7304 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7305 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
7306 // (intrinsic_wo_chain:{ *:[v4i32] } 7777:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
7307 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
7308 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7309 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7310 GIR_RootToRootCopy, /*OpIdx*/3, // m
7311 GIR_RootConstrainSelectedInstOperands,
7312 // GIR_Coverage, 987,
7313 GIR_EraseRootFromParent_Done,
7314 // Label 547: @18338
7315 GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(18384), // Rule ID 988 //
7316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7317 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
7318 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7319 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7321 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7322 // MIs[0] m
7323 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7324 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
7325 // (intrinsic_wo_chain:{ *:[v2i64] } 7775:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
7326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
7327 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7328 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7329 GIR_RootToRootCopy, /*OpIdx*/3, // m
7330 GIR_RootConstrainSelectedInstOperands,
7331 // GIR_Coverage, 988,
7332 GIR_EraseRootFromParent_Done,
7333 // Label 548: @18384
7334 GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(18430), // Rule ID 1001 //
7335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7336 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
7337 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
7338 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7339 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7340 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
7341 // MIs[0] m
7342 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7343 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
7344 // (intrinsic_wo_chain:{ *:[v16i8] } 7790:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
7345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
7346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7347 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7348 GIR_RootToRootCopy, /*OpIdx*/3, // m
7349 GIR_RootConstrainSelectedInstOperands,
7350 // GIR_Coverage, 1001,
7351 GIR_EraseRootFromParent_Done,
7352 // Label 549: @18430
7353 GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(18476), // Rule ID 1002 //
7354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7355 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
7356 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
7357 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7358 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7359 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
7360 // MIs[0] m
7361 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7362 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
7363 // (intrinsic_wo_chain:{ *:[v8i16] } 7792:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
7364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
7365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7366 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7367 GIR_RootToRootCopy, /*OpIdx*/3, // m
7368 GIR_RootConstrainSelectedInstOperands,
7369 // GIR_Coverage, 1002,
7370 GIR_EraseRootFromParent_Done,
7371 // Label 550: @18476
7372 GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(18522), // Rule ID 1003 //
7373 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
7375 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
7376 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7377 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7378 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
7379 // MIs[0] m
7380 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7381 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
7382 // (intrinsic_wo_chain:{ *:[v4i32] } 7793:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
7383 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
7384 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7385 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7386 GIR_RootToRootCopy, /*OpIdx*/3, // m
7387 GIR_RootConstrainSelectedInstOperands,
7388 // GIR_Coverage, 1003,
7389 GIR_EraseRootFromParent_Done,
7390 // Label 551: @18522
7391 GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(18568), // Rule ID 1004 //
7392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
7393 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
7394 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
7395 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7396 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7397 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
7398 // MIs[0] m
7399 GIM_CheckIsImm, /*MI*/0, /*Op*/3,
7400 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
7401 // (intrinsic_wo_chain:{ *:[v2i64] } 7791:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
7402 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
7403 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
7404 GIR_RootToRootCopy, /*OpIdx*/2, // ws
7405 GIR_RootToRootCopy, /*OpIdx*/3, // m
7406 GIR_RootConstrainSelectedInstOperands,
7407 // GIR_Coverage, 1004,
7408 GIR_EraseRootFromParent_Done,
7409 // Label 552: @18568
7410 GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(18624), // Rule ID 385 //
7411 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7412 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
7413 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7414 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7415 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7416 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7417 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7418 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7419 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7420 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
7421 // MIs[1] Operand 1
7422 // No operand predicates
7423 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7424 // (intrinsic_wo_chain:{ *:[v2i16] } 7733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
7425 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
7426 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7427 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7428 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
7429 GIR_RootConstrainSelectedInstOperands,
7430 // GIR_Coverage, 385,
7431 GIR_EraseRootFromParent_Done,
7432 // Label 553: @18624
7433 GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(18680), // Rule ID 389 //
7434 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7435 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
7436 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7437 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7438 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7440 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7441 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7442 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7443 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
7444 // MIs[1] Operand 1
7445 // No operand predicates
7446 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7447 // (intrinsic_wo_chain:{ *:[i32] } 7735:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
7448 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
7449 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7450 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7451 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
7452 GIR_RootConstrainSelectedInstOperands,
7453 // GIR_Coverage, 389,
7454 GIR_EraseRootFromParent_Done,
7455 // Label 554: @18680
7456 GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(18736), // Rule ID 480 //
7457 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7458 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
7459 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7460 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7461 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7462 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7463 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7464 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7465 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7466 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
7467 // MIs[1] Operand 1
7468 // No operand predicates
7469 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7470 // (intrinsic_wo_chain:{ *:[v4i8] } 7734:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
7471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
7472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7473 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7474 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
7475 GIR_RootConstrainSelectedInstOperands,
7476 // GIR_Coverage, 480,
7477 GIR_EraseRootFromParent_Done,
7478 // Label 555: @18736
7479 GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(18792), // Rule ID 1245 //
7480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7481 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
7482 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7484 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7486 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7487 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7488 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7489 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
7490 // MIs[1] Operand 1
7491 // No operand predicates
7492 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7493 // (intrinsic_wo_chain:{ *:[v2i16] } 7733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
7494 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
7495 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7496 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7497 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
7498 GIR_RootConstrainSelectedInstOperands,
7499 // GIR_Coverage, 1245,
7500 GIR_EraseRootFromParent_Done,
7501 // Label 556: @18792
7502 GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(18848), // Rule ID 1249 //
7503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
7504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
7505 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7506 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7507 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7508 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7509 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7510 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7511 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7512 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
7513 // MIs[1] Operand 1
7514 // No operand predicates
7515 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7516 // (intrinsic_wo_chain:{ *:[i32] } 7735:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
7517 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
7518 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7519 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7520 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
7521 GIR_RootConstrainSelectedInstOperands,
7522 // GIR_Coverage, 1249,
7523 GIR_EraseRootFromParent_Done,
7524 // Label 557: @18848
7525 GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(18904), // Rule ID 1324 //
7526 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
7527 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
7528 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7529 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7530 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7531 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7532 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7533 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7534 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7535 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
7536 // MIs[1] Operand 1
7537 // No operand predicates
7538 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7539 // (intrinsic_wo_chain:{ *:[v4i8] } 7734:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
7540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
7541 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
7542 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7543 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
7544 GIR_RootConstrainSelectedInstOperands,
7545 // GIR_Coverage, 1324,
7546 GIR_EraseRootFromParent_Done,
7547 // Label 558: @18904
7548 GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(18956), // Rule ID 1917 //
7549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
7551 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7552 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7553 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7554 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7555 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7556 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7557 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
7558 // MIs[1] Operand 1
7559 // No operand predicates
7560 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7561 // (intrinsic_wo_chain:{ *:[v2i16] } 7731:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
7562 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
7563 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7564 GIR_RootToRootCopy, /*OpIdx*/2, // a
7565 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
7566 GIR_RootConstrainSelectedInstOperands,
7567 // GIR_Coverage, 1917,
7568 GIR_EraseRootFromParent_Done,
7569 // Label 559: @18956
7570 GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(19008), // Rule ID 1918 //
7571 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7572 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
7573 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7574 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7575 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7576 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7578 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7579 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
7580 // MIs[1] Operand 1
7581 // No operand predicates
7582 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7583 // (intrinsic_wo_chain:{ *:[v2i16] } 7736:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
7584 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
7585 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7586 GIR_RootToRootCopy, /*OpIdx*/2, // a
7587 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
7588 GIR_RootConstrainSelectedInstOperands,
7589 // GIR_Coverage, 1918,
7590 GIR_EraseRootFromParent_Done,
7591 // Label 560: @19008
7592 GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(19060), // Rule ID 1923 //
7593 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
7595 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7597 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7598 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7599 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7600 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7601 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
7602 // MIs[1] Operand 1
7603 // No operand predicates
7604 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7605 // (intrinsic_wo_chain:{ *:[v4i8] } 7732:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
7606 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
7607 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7608 GIR_RootToRootCopy, /*OpIdx*/2, // a
7609 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
7610 GIR_RootConstrainSelectedInstOperands,
7611 // GIR_Coverage, 1923,
7612 GIR_EraseRootFromParent_Done,
7613 // Label 561: @19060
7614 GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(19112), // Rule ID 1924 //
7615 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
7617 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7618 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7619 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7621 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
7622 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7623 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
7624 // MIs[1] Operand 1
7625 // No operand predicates
7626 GIM_CheckIsSafeToFold, /*NumInsns*/1,
7627 // (intrinsic_wo_chain:{ *:[v4i8] } 7737:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
7628 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
7629 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7630 GIR_RootToRootCopy, /*OpIdx*/2, // a
7631 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
7632 GIR_RootConstrainSelectedInstOperands,
7633 // GIR_Coverage, 1924,
7634 GIR_EraseRootFromParent_Done,
7635 // Label 562: @19112
7636 GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(19160), // Rule ID 355 //
7637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7638 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
7639 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7640 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7641 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
7642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7643 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7644 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7645 // (intrinsic_wo_chain:{ *:[v4i8] } 7203:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7646 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
7647 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7648 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7649 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7650 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
7651 GIR_RootConstrainSelectedInstOperands,
7652 // GIR_Coverage, 355,
7653 GIR_EraseRootFromParent_Done,
7654 // Label 563: @19160
7655 GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(19208), // Rule ID 356 //
7656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
7658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7660 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
7661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7662 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7663 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7664 // (intrinsic_wo_chain:{ *:[v4i8] } 7826:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7665 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
7666 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7667 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7668 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7669 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
7670 GIR_RootConstrainSelectedInstOperands,
7671 // GIR_Coverage, 356,
7672 GIR_EraseRootFromParent_Done,
7673 // Label 564: @19208
7674 GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(19256), // Rule ID 357 //
7675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
7677 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7678 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7679 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7680 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7681 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7682 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7683 // (intrinsic_wo_chain:{ *:[v2i16] } 7181:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7684 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
7685 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7686 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7687 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7688 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
7689 GIR_RootConstrainSelectedInstOperands,
7690 // GIR_Coverage, 357,
7691 GIR_EraseRootFromParent_Done,
7692 // Label 565: @19256
7693 GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(19304), // Rule ID 358 //
7694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7695 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
7696 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7697 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7698 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7700 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7701 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7702 // (intrinsic_wo_chain:{ *:[v2i16] } 7801:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
7704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7705 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7706 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7707 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
7708 GIR_RootConstrainSelectedInstOperands,
7709 // GIR_Coverage, 358,
7710 GIR_EraseRootFromParent_Done,
7711 // Label 566: @19304
7712 GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(19349), // Rule ID 361 //
7713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7714 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
7715 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7716 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7717 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7718 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7719 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7720 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7721 // (intrinsic_wo_chain:{ *:[i32] } 7631:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
7722 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
7723 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7724 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7725 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7726 GIR_RootConstrainSelectedInstOperands,
7727 // GIR_Coverage, 361,
7728 GIR_EraseRootFromParent_Done,
7729 // Label 567: @19349
7730 GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(19394), // Rule ID 365 //
7731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7732 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
7733 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7734 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7735 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7736 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7737 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7738 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7739 // (intrinsic_wo_chain:{ *:[v4i8] } 7707:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7740 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
7741 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7742 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7743 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7744 GIR_RootConstrainSelectedInstOperands,
7745 // GIR_Coverage, 365,
7746 GIR_EraseRootFromParent_Done,
7747 // Label 568: @19394
7748 GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(19439), // Rule ID 366 //
7749 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7750 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
7751 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7752 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7753 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7754 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7755 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7756 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7757 // (intrinsic_wo_chain:{ *:[v2i16] } 7706:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
7758 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
7759 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7760 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7761 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7762 GIR_RootConstrainSelectedInstOperands,
7763 // GIR_Coverage, 366,
7764 GIR_EraseRootFromParent_Done,
7765 // Label 569: @19439
7766 GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(19484), // Rule ID 380 //
7767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7768 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
7769 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7770 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7771 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7774 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7775 // (intrinsic_wo_chain:{ *:[v4i8] } 7737:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
7776 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
7777 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7778 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7779 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
7780 GIR_RootConstrainSelectedInstOperands,
7781 // GIR_Coverage, 380,
7782 GIR_EraseRootFromParent_Done,
7783 // Label 570: @19484
7784 GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(19529), // Rule ID 384 //
7785 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7786 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
7787 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7788 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7789 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7790 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7791 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7792 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7793 // (intrinsic_wo_chain:{ *:[v2i16] } 7731:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
7794 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
7795 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7796 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7797 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
7798 GIR_RootConstrainSelectedInstOperands,
7799 // GIR_Coverage, 384,
7800 GIR_EraseRootFromParent_Done,
7801 // Label 571: @19529
7802 GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(19574), // Rule ID 386 //
7803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
7805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7807 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7808 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7809 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7810 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7811 // (intrinsic_wo_chain:{ *:[v2i16] } 7733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
7812 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
7813 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7814 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7815 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
7816 GIR_RootConstrainSelectedInstOperands,
7817 // GIR_Coverage, 386,
7818 GIR_EraseRootFromParent_Done,
7819 // Label 572: @19574
7820 GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(19619), // Rule ID 390 //
7821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
7823 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
7824 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7825 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
7826 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7827 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7828 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
7829 // (intrinsic_wo_chain:{ *:[i32] } 7735:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
7830 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
7831 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7832 GIR_RootToRootCopy, /*OpIdx*/2, // rt
7833 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
7834 GIR_RootConstrainSelectedInstOperands,
7835 // GIR_Coverage, 390,
7836 GIR_EraseRootFromParent_Done,
7837 // Label 573: @19619
7838 GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(19664), // Rule ID 427 //
7839 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
7840 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
7841 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7842 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7843 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7844 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7845 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7846 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7847 // (intrinsic_wo_chain:{ *:[v2i16] } 7678:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
7849 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7850 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7851 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7852 GIR_RootConstrainSelectedInstOperands,
7853 // GIR_Coverage, 427,
7854 GIR_EraseRootFromParent_Done,
7855 // Label 574: @19664
7856 GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(19709), // Rule ID 451 //
7857 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7858 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
7859 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7860 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7861 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
7862 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7863 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7864 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7865 // (intrinsic_wo_chain:{ *:[v4i8] } 7204:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7866 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
7867 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7868 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7869 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7870 GIR_RootConstrainSelectedInstOperands,
7871 // GIR_Coverage, 451,
7872 GIR_EraseRootFromParent_Done,
7873 // Label 575: @19709
7874 GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(19754), // Rule ID 452 //
7875 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
7877 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7878 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7879 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
7880 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7881 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7882 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7883 // (intrinsic_wo_chain:{ *:[v4i8] } 7205:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7884 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
7885 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7886 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7887 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7888 GIR_RootConstrainSelectedInstOperands,
7889 // GIR_Coverage, 452,
7890 GIR_EraseRootFromParent_Done,
7891 // Label 576: @19754
7892 GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(19799), // Rule ID 453 //
7893 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7894 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
7895 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7896 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7897 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
7898 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7899 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7900 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7901 // (intrinsic_wo_chain:{ *:[v4i8] } 7827:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7902 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
7903 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7904 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7905 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7906 GIR_RootConstrainSelectedInstOperands,
7907 // GIR_Coverage, 453,
7908 GIR_EraseRootFromParent_Done,
7909 // Label 577: @19799
7910 GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(19844), // Rule ID 454 //
7911 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
7913 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
7914 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
7915 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
7916 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7917 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7918 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7919 // (intrinsic_wo_chain:{ *:[v4i8] } 7828:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
7920 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
7921 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7922 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7923 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7924 GIR_RootConstrainSelectedInstOperands,
7925 // GIR_Coverage, 454,
7926 GIR_EraseRootFromParent_Done,
7927 // Label 578: @19844
7928 GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(19889), // Rule ID 455 //
7929 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
7931 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7932 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7933 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7934 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7935 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7936 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7937 // (intrinsic_wo_chain:{ *:[v2i16] } 7183:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7938 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
7939 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7940 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7941 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7942 GIR_RootConstrainSelectedInstOperands,
7943 // GIR_Coverage, 455,
7944 GIR_EraseRootFromParent_Done,
7945 // Label 579: @19889
7946 GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(19934), // Rule ID 456 //
7947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7948 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
7949 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7950 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7951 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7952 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7953 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7954 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7955 // (intrinsic_wo_chain:{ *:[v2i16] } 7184:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7956 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
7957 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7958 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7959 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7960 GIR_RootConstrainSelectedInstOperands,
7961 // GIR_Coverage, 456,
7962 GIR_EraseRootFromParent_Done,
7963 // Label 580: @19934
7964 GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(19979), // Rule ID 457 //
7965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7966 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
7967 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7968 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7969 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7970 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7971 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7972 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7973 // (intrinsic_wo_chain:{ *:[v2i16] } 7803:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7974 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
7975 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7976 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7977 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7978 GIR_RootConstrainSelectedInstOperands,
7979 // GIR_Coverage, 457,
7980 GIR_EraseRootFromParent_Done,
7981 // Label 581: @19979
7982 GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(20024), // Rule ID 458 //
7983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
7984 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
7985 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
7986 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
7987 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
7988 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7989 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7990 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
7991 // (intrinsic_wo_chain:{ *:[v2i16] } 7804:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
7992 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
7993 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
7994 GIR_RootToRootCopy, /*OpIdx*/2, // rs
7995 GIR_RootToRootCopy, /*OpIdx*/3, // rt
7996 GIR_RootConstrainSelectedInstOperands,
7997 // GIR_Coverage, 458,
7998 GIR_EraseRootFromParent_Done,
7999 // Label 582: @20024
8000 GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(20069), // Rule ID 459 //
8001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8002 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
8003 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8004 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8005 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8006 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8007 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8008 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8009 // (intrinsic_wo_chain:{ *:[i32] } 7186:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
8011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8012 GIR_RootToRootCopy, /*OpIdx*/2, // rs
8013 GIR_RootToRootCopy, /*OpIdx*/3, // rt
8014 GIR_RootConstrainSelectedInstOperands,
8015 // GIR_Coverage, 459,
8016 GIR_EraseRootFromParent_Done,
8017 // Label 583: @20069
8018 GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(20114), // Rule ID 460 //
8019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8020 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
8021 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8022 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8023 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8024 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8025 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8026 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8027 // (intrinsic_wo_chain:{ *:[i32] } 7185:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8028 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
8029 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8030 GIR_RootToRootCopy, /*OpIdx*/2, // rs
8031 GIR_RootToRootCopy, /*OpIdx*/3, // rt
8032 GIR_RootConstrainSelectedInstOperands,
8033 // GIR_Coverage, 460,
8034 GIR_EraseRootFromParent_Done,
8035 // Label 584: @20114
8036 GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(20159), // Rule ID 461 //
8037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
8039 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8040 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8041 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8042 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8043 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8044 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8045 // (intrinsic_wo_chain:{ *:[i32] } 7806:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8046 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
8047 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8048 GIR_RootToRootCopy, /*OpIdx*/2, // rs
8049 GIR_RootToRootCopy, /*OpIdx*/3, // rt
8050 GIR_RootConstrainSelectedInstOperands,
8051 // GIR_Coverage, 461,
8052 GIR_EraseRootFromParent_Done,
8053 // Label 585: @20159
8054 GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(20204), // Rule ID 462 //
8055 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8056 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
8057 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
8058 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
8059 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8060 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8061 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8062 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8063 // (intrinsic_wo_chain:{ *:[i32] } 7805:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
8064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
8065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8066 GIR_RootToRootCopy, /*OpIdx*/2, // rs
8067 GIR_RootToRootCopy, /*OpIdx*/3, // rt
8068 GIR_RootConstrainSelectedInstOperands,
8069 // GIR_Coverage, 462,
8070 GIR_EraseRootFromParent_Done,
8071 // Label 586: @20204
8072 GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(20249), // Rule ID 479 //
8073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
8075 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8077 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8079 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8080 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8081 // (intrinsic_wo_chain:{ *:[v4i8] } 7732:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8082 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
8083 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8084 GIR_RootToRootCopy, /*OpIdx*/2, // rt
8085 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8086 GIR_RootConstrainSelectedInstOperands,
8087 // GIR_Coverage, 479,
8088 GIR_EraseRootFromParent_Done,
8089 // Label 587: @20249
8090 GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(20294), // Rule ID 481 //
8091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8092 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
8093 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
8094 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
8095 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8096 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8097 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8098 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8099 // (intrinsic_wo_chain:{ *:[v4i8] } 7734:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8100 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
8101 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8102 GIR_RootToRootCopy, /*OpIdx*/2, // rt
8103 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8104 GIR_RootConstrainSelectedInstOperands,
8105 // GIR_Coverage, 481,
8106 GIR_EraseRootFromParent_Done,
8107 // Label 588: @20294
8108 GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(20339), // Rule ID 482 //
8109 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
8110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
8111 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
8112 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
8113 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
8114 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8115 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
8116 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
8117 // (intrinsic_wo_chain:{ *:[v2i16] } 7736:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
8118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
8119 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
8120 GIR_RootToRootCopy, /*OpIdx*/2, // rt
8121 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
8122 GIR_RootConstrainSelectedInstOperands,
8123 // GIR_Coverage, 482,
8124 GIR_EraseRootFromParent_Done,
8125 // Label 589: @20339
8126 GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(20384), // Rule ID 491 //
8127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8128 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
8129 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8130 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8131 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8132 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8133 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8134 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8135 // (intrinsic_wo_chain:{ *:[v16i8] } 7176:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
8137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8138 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8139 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8140 GIR_RootConstrainSelectedInstOperands,
8141 // GIR_Coverage, 491,
8142 GIR_EraseRootFromParent_Done,
8143 // Label 590: @20384
8144 GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(20429), // Rule ID 492 //
8145 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8146 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
8147 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8148 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8149 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8150 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8151 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8152 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8153 // (intrinsic_wo_chain:{ *:[v8i16] } 7178:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8154 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
8155 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8156 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8157 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8158 GIR_RootConstrainSelectedInstOperands,
8159 // GIR_Coverage, 492,
8160 GIR_EraseRootFromParent_Done,
8161 // Label 591: @20429
8162 GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(20474), // Rule ID 493 //
8163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8164 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
8165 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8166 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8167 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8168 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8169 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8170 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8171 // (intrinsic_wo_chain:{ *:[v4i32] } 7179:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8172 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
8173 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8174 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8175 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8176 GIR_RootConstrainSelectedInstOperands,
8177 // GIR_Coverage, 493,
8178 GIR_EraseRootFromParent_Done,
8179 // Label 592: @20474
8180 GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(20519), // Rule ID 494 //
8181 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8182 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
8183 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8184 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8185 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8186 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8187 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8188 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8189 // (intrinsic_wo_chain:{ *:[v2i64] } 7177:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
8191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8192 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8193 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8194 GIR_RootConstrainSelectedInstOperands,
8195 // GIR_Coverage, 494,
8196 GIR_EraseRootFromParent_Done,
8197 // Label 593: @20519
8198 GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(20564), // Rule ID 495 //
8199 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8200 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
8201 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8202 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8203 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8205 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8206 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8207 // (intrinsic_wo_chain:{ *:[v16i8] } 7187:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8208 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
8209 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8210 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8211 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8212 GIR_RootConstrainSelectedInstOperands,
8213 // GIR_Coverage, 495,
8214 GIR_EraseRootFromParent_Done,
8215 // Label 594: @20564
8216 GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(20609), // Rule ID 496 //
8217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
8219 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8221 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8222 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8223 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8224 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8225 // (intrinsic_wo_chain:{ *:[v8i16] } 7189:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8226 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
8227 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8228 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8229 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8230 GIR_RootConstrainSelectedInstOperands,
8231 // GIR_Coverage, 496,
8232 GIR_EraseRootFromParent_Done,
8233 // Label 595: @20609
8234 GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(20654), // Rule ID 497 //
8235 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8236 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
8237 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8238 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8239 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8240 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8241 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8242 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8243 // (intrinsic_wo_chain:{ *:[v4i32] } 7190:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8244 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
8245 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8246 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8247 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8248 GIR_RootConstrainSelectedInstOperands,
8249 // GIR_Coverage, 497,
8250 GIR_EraseRootFromParent_Done,
8251 // Label 596: @20654
8252 GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(20699), // Rule ID 498 //
8253 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8254 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
8255 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8256 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8257 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8258 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8259 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8260 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8261 // (intrinsic_wo_chain:{ *:[v2i64] } 7188:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8262 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
8263 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8264 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8265 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8266 GIR_RootConstrainSelectedInstOperands,
8267 // GIR_Coverage, 498,
8268 GIR_EraseRootFromParent_Done,
8269 // Label 597: @20699
8270 GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(20744), // Rule ID 499 //
8271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
8273 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8275 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8276 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8277 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8278 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8279 // (intrinsic_wo_chain:{ *:[v16i8] } 7191:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8280 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
8281 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8282 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8283 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8284 GIR_RootConstrainSelectedInstOperands,
8285 // GIR_Coverage, 499,
8286 GIR_EraseRootFromParent_Done,
8287 // Label 598: @20744
8288 GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(20789), // Rule ID 500 //
8289 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8290 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
8291 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8292 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8293 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8294 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8295 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8296 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8297 // (intrinsic_wo_chain:{ *:[v8i16] } 7193:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8298 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
8299 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8300 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8301 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8302 GIR_RootConstrainSelectedInstOperands,
8303 // GIR_Coverage, 500,
8304 GIR_EraseRootFromParent_Done,
8305 // Label 599: @20789
8306 GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(20834), // Rule ID 501 //
8307 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
8309 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8310 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8311 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8312 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8313 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8314 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8315 // (intrinsic_wo_chain:{ *:[v4i32] } 7194:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8316 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
8317 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8318 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8319 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8320 GIR_RootConstrainSelectedInstOperands,
8321 // GIR_Coverage, 501,
8322 GIR_EraseRootFromParent_Done,
8323 // Label 600: @20834
8324 GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(20879), // Rule ID 502 //
8325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
8327 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8328 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8329 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8331 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8332 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8333 // (intrinsic_wo_chain:{ *:[v2i64] } 7192:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8334 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
8335 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8336 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8337 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8338 GIR_RootConstrainSelectedInstOperands,
8339 // GIR_Coverage, 502,
8340 GIR_EraseRootFromParent_Done,
8341 // Label 601: @20879
8342 GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(20924), // Rule ID 503 //
8343 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8344 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
8345 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8346 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8347 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8348 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8349 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8350 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8351 // (intrinsic_wo_chain:{ *:[v16i8] } 7195:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8352 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
8353 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8354 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8355 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8356 GIR_RootConstrainSelectedInstOperands,
8357 // GIR_Coverage, 503,
8358 GIR_EraseRootFromParent_Done,
8359 // Label 602: @20924
8360 GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(20969), // Rule ID 504 //
8361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8362 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
8363 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8364 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8365 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8366 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8367 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8368 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8369 // (intrinsic_wo_chain:{ *:[v8i16] } 7197:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8370 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
8371 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8372 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8373 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8374 GIR_RootConstrainSelectedInstOperands,
8375 // GIR_Coverage, 504,
8376 GIR_EraseRootFromParent_Done,
8377 // Label 603: @20969
8378 GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(21014), // Rule ID 505 //
8379 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
8381 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8382 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8383 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8384 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8385 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8386 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8387 // (intrinsic_wo_chain:{ *:[v4i32] } 7198:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8388 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
8389 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8390 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8391 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8392 GIR_RootConstrainSelectedInstOperands,
8393 // GIR_Coverage, 505,
8394 GIR_EraseRootFromParent_Done,
8395 // Label 604: @21014
8396 GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(21059), // Rule ID 506 //
8397 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8398 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
8399 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8402 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8403 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8404 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8405 // (intrinsic_wo_chain:{ *:[v2i64] } 7196:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8406 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
8407 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8408 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8409 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8410 GIR_RootConstrainSelectedInstOperands,
8411 // GIR_Coverage, 506,
8412 GIR_EraseRootFromParent_Done,
8413 // Label 605: @21059
8414 GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(21104), // Rule ID 520 //
8415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8416 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
8417 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8418 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8419 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8420 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8421 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8422 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8423 // (intrinsic_wo_chain:{ *:[v16i8] } 7218:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8424 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
8425 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8426 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8427 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8428 GIR_RootConstrainSelectedInstOperands,
8429 // GIR_Coverage, 520,
8430 GIR_EraseRootFromParent_Done,
8431 // Label 606: @21104
8432 GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(21149), // Rule ID 521 //
8433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
8435 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8436 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8437 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8439 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8440 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8441 // (intrinsic_wo_chain:{ *:[v8i16] } 7220:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8442 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
8443 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8444 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8445 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8446 GIR_RootConstrainSelectedInstOperands,
8447 // GIR_Coverage, 521,
8448 GIR_EraseRootFromParent_Done,
8449 // Label 607: @21149
8450 GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(21194), // Rule ID 522 //
8451 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8452 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
8453 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8454 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8455 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8456 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8457 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8458 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8459 // (intrinsic_wo_chain:{ *:[v4i32] } 7221:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8460 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
8461 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8462 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8463 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8464 GIR_RootConstrainSelectedInstOperands,
8465 // GIR_Coverage, 522,
8466 GIR_EraseRootFromParent_Done,
8467 // Label 608: @21194
8468 GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(21239), // Rule ID 523 //
8469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
8471 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8472 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8473 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8474 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8475 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8476 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8477 // (intrinsic_wo_chain:{ *:[v2i64] } 7219:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
8479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8480 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8481 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8482 GIR_RootConstrainSelectedInstOperands,
8483 // GIR_Coverage, 523,
8484 GIR_EraseRootFromParent_Done,
8485 // Label 609: @21239
8486 GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(21284), // Rule ID 524 //
8487 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8488 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
8489 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8490 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8491 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8492 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8493 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8494 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8495 // (intrinsic_wo_chain:{ *:[v16i8] } 7222:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
8497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8498 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8499 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8500 GIR_RootConstrainSelectedInstOperands,
8501 // GIR_Coverage, 524,
8502 GIR_EraseRootFromParent_Done,
8503 // Label 610: @21284
8504 GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(21329), // Rule ID 525 //
8505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
8507 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8508 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8509 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8512 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8513 // (intrinsic_wo_chain:{ *:[v8i16] } 7224:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
8515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8516 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8517 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8518 GIR_RootConstrainSelectedInstOperands,
8519 // GIR_Coverage, 525,
8520 GIR_EraseRootFromParent_Done,
8521 // Label 611: @21329
8522 GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(21374), // Rule ID 526 //
8523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
8525 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8526 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8527 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8528 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8529 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8530 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8531 // (intrinsic_wo_chain:{ *:[v4i32] } 7225:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8532 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
8533 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8534 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8535 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8536 GIR_RootConstrainSelectedInstOperands,
8537 // GIR_Coverage, 526,
8538 GIR_EraseRootFromParent_Done,
8539 // Label 612: @21374
8540 GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(21419), // Rule ID 527 //
8541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
8543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8545 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8546 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8547 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8548 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8549 // (intrinsic_wo_chain:{ *:[v2i64] } 7223:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8550 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
8551 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8552 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8553 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8554 GIR_RootConstrainSelectedInstOperands,
8555 // GIR_Coverage, 527,
8556 GIR_EraseRootFromParent_Done,
8557 // Label 613: @21419
8558 GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(21464), // Rule ID 528 //
8559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8560 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
8561 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8562 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8563 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8565 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8566 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8567 // (intrinsic_wo_chain:{ *:[v16i8] } 7226:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
8569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8570 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8571 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8572 GIR_RootConstrainSelectedInstOperands,
8573 // GIR_Coverage, 528,
8574 GIR_EraseRootFromParent_Done,
8575 // Label 614: @21464
8576 GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(21509), // Rule ID 529 //
8577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
8579 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8583 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8584 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8585 // (intrinsic_wo_chain:{ *:[v8i16] } 7228:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8586 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
8587 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8588 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8589 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8590 GIR_RootConstrainSelectedInstOperands,
8591 // GIR_Coverage, 529,
8592 GIR_EraseRootFromParent_Done,
8593 // Label 615: @21509
8594 GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(21554), // Rule ID 530 //
8595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8596 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
8597 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8598 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8599 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8600 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8601 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8602 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8603 // (intrinsic_wo_chain:{ *:[v4i32] } 7229:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
8605 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8606 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8607 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8608 GIR_RootConstrainSelectedInstOperands,
8609 // GIR_Coverage, 530,
8610 GIR_EraseRootFromParent_Done,
8611 // Label 616: @21554
8612 GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(21599), // Rule ID 531 //
8613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
8615 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8616 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8617 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8618 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8619 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8620 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8621 // (intrinsic_wo_chain:{ *:[v2i64] } 7227:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
8623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8624 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8625 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8626 GIR_RootConstrainSelectedInstOperands,
8627 // GIR_Coverage, 531,
8628 GIR_EraseRootFromParent_Done,
8629 // Label 617: @21599
8630 GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(21644), // Rule ID 532 //
8631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
8633 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8635 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8636 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8637 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8638 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8639 // (intrinsic_wo_chain:{ *:[v16i8] } 7230:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8640 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
8641 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8642 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8643 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8644 GIR_RootConstrainSelectedInstOperands,
8645 // GIR_Coverage, 532,
8646 GIR_EraseRootFromParent_Done,
8647 // Label 618: @21644
8648 GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(21689), // Rule ID 533 //
8649 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8650 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
8651 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8652 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8653 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8654 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8655 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8656 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8657 // (intrinsic_wo_chain:{ *:[v8i16] } 7232:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8658 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
8659 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8660 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8661 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8662 GIR_RootConstrainSelectedInstOperands,
8663 // GIR_Coverage, 533,
8664 GIR_EraseRootFromParent_Done,
8665 // Label 619: @21689
8666 GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(21734), // Rule ID 534 //
8667 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8668 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
8669 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8670 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8671 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8672 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8673 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8674 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8675 // (intrinsic_wo_chain:{ *:[v4i32] } 7233:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8676 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
8677 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8678 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8679 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8680 GIR_RootConstrainSelectedInstOperands,
8681 // GIR_Coverage, 534,
8682 GIR_EraseRootFromParent_Done,
8683 // Label 620: @21734
8684 GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(21779), // Rule ID 535 //
8685 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8686 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
8687 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8688 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8689 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8691 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8692 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8693 // (intrinsic_wo_chain:{ *:[v2i64] } 7231:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8694 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
8695 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8696 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8697 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8698 GIR_RootConstrainSelectedInstOperands,
8699 // GIR_Coverage, 535,
8700 GIR_EraseRootFromParent_Done,
8701 // Label 621: @21779
8702 GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(21824), // Rule ID 536 //
8703 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8704 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
8705 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8706 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8707 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8709 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8710 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8711 // (intrinsic_wo_chain:{ *:[v16i8] } 7234:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8712 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
8713 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8714 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8715 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8716 GIR_RootConstrainSelectedInstOperands,
8717 // GIR_Coverage, 536,
8718 GIR_EraseRootFromParent_Done,
8719 // Label 622: @21824
8720 GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(21869), // Rule ID 537 //
8721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
8723 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8724 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8725 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8726 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8727 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8728 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8729 // (intrinsic_wo_chain:{ *:[v8i16] } 7236:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
8731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8732 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8733 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8734 GIR_RootConstrainSelectedInstOperands,
8735 // GIR_Coverage, 537,
8736 GIR_EraseRootFromParent_Done,
8737 // Label 623: @21869
8738 GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(21914), // Rule ID 538 //
8739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8740 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
8741 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8742 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8743 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8745 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8746 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8747 // (intrinsic_wo_chain:{ *:[v4i32] } 7237:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8748 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
8749 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8750 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8751 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8752 GIR_RootConstrainSelectedInstOperands,
8753 // GIR_Coverage, 538,
8754 GIR_EraseRootFromParent_Done,
8755 // Label 624: @21914
8756 GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(21959), // Rule ID 539 //
8757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8758 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
8759 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8760 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8761 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8762 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8763 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8764 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8765 // (intrinsic_wo_chain:{ *:[v2i64] } 7235:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8766 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
8767 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8768 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8769 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8770 GIR_RootConstrainSelectedInstOperands,
8771 // GIR_Coverage, 539,
8772 GIR_EraseRootFromParent_Done,
8773 // Label 625: @21959
8774 GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(22004), // Rule ID 540 //
8775 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8776 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
8777 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
8778 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8779 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8780 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8781 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8782 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8783 // (intrinsic_wo_chain:{ *:[v16i8] } 7238:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8784 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
8785 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8786 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8787 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8788 GIR_RootConstrainSelectedInstOperands,
8789 // GIR_Coverage, 540,
8790 GIR_EraseRootFromParent_Done,
8791 // Label 626: @22004
8792 GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(22049), // Rule ID 541 //
8793 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
8795 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8796 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8797 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8798 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8799 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8800 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8801 // (intrinsic_wo_chain:{ *:[v8i16] } 7240:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8802 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
8803 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8804 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8805 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8806 GIR_RootConstrainSelectedInstOperands,
8807 // GIR_Coverage, 541,
8808 GIR_EraseRootFromParent_Done,
8809 // Label 627: @22049
8810 GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(22094), // Rule ID 542 //
8811 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8812 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
8813 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8814 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8815 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8816 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8817 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8818 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8819 // (intrinsic_wo_chain:{ *:[v4i32] } 7241:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8820 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
8821 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8822 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8823 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8824 GIR_RootConstrainSelectedInstOperands,
8825 // GIR_Coverage, 542,
8826 GIR_EraseRootFromParent_Done,
8827 // Label 628: @22094
8828 GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(22139), // Rule ID 543 //
8829 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8830 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
8831 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8832 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8833 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8834 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8835 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8836 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8837 // (intrinsic_wo_chain:{ *:[v2i64] } 7239:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
8838 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
8839 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8840 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8841 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8842 GIR_RootConstrainSelectedInstOperands,
8843 // GIR_Coverage, 543,
8844 GIR_EraseRootFromParent_Done,
8845 // Label 629: @22139
8846 GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(22184), // Rule ID 652 //
8847 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
8849 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8851 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8852 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8853 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8854 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8855 // (intrinsic_wo_chain:{ *:[v8i16] } 7373:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
8857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8858 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8859 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8860 GIR_RootConstrainSelectedInstOperands,
8861 // GIR_Coverage, 652,
8862 GIR_EraseRootFromParent_Done,
8863 // Label 630: @22184
8864 GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(22229), // Rule ID 653 //
8865 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8866 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
8867 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8868 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8869 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8870 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8871 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8872 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8873 // (intrinsic_wo_chain:{ *:[v4i32] } 7374:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
8875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8876 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8877 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8878 GIR_RootConstrainSelectedInstOperands,
8879 // GIR_Coverage, 653,
8880 GIR_EraseRootFromParent_Done,
8881 // Label 631: @22229
8882 GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(22274), // Rule ID 654 //
8883 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8884 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
8885 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8886 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8887 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8888 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8889 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8890 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8891 // (intrinsic_wo_chain:{ *:[v2i64] } 7372:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8892 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
8893 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8894 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8895 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8896 GIR_RootConstrainSelectedInstOperands,
8897 // GIR_Coverage, 654,
8898 GIR_EraseRootFromParent_Done,
8899 // Label 632: @22274
8900 GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(22319), // Rule ID 655 //
8901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8902 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
8903 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8904 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
8905 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
8906 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8907 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8908 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
8909 // (intrinsic_wo_chain:{ *:[v8i16] } 7376:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
8910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
8911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8912 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8913 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8914 GIR_RootConstrainSelectedInstOperands,
8915 // GIR_Coverage, 655,
8916 GIR_EraseRootFromParent_Done,
8917 // Label 633: @22319
8918 GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(22364), // Rule ID 656 //
8919 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8920 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
8921 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8922 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
8923 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
8924 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8925 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8926 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8927 // (intrinsic_wo_chain:{ *:[v4i32] } 7377:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
8928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
8929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8930 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8931 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8932 GIR_RootConstrainSelectedInstOperands,
8933 // GIR_Coverage, 656,
8934 GIR_EraseRootFromParent_Done,
8935 // Label 634: @22364
8936 GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(22409), // Rule ID 657 //
8937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8938 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
8939 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8940 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8941 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8942 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8943 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8944 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8945 // (intrinsic_wo_chain:{ *:[v2i64] } 7375:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
8946 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
8947 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8948 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8949 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8950 GIR_RootConstrainSelectedInstOperands,
8951 // GIR_Coverage, 657,
8952 GIR_EraseRootFromParent_Done,
8953 // Label 635: @22409
8954 GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(22454), // Rule ID 672 //
8955 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
8957 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
8958 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8959 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8960 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8961 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8962 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8963 // (intrinsic_wo_chain:{ *:[v4i32] } 7415:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
8964 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
8965 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8966 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8967 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8968 GIR_RootConstrainSelectedInstOperands,
8969 // GIR_Coverage, 672,
8970 GIR_EraseRootFromParent_Done,
8971 // Label 636: @22454
8972 GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(22499), // Rule ID 673 //
8973 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
8975 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
8976 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
8977 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
8978 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8979 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8980 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
8981 // (intrinsic_wo_chain:{ *:[v2i64] } 7414:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
8982 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
8983 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
8984 GIR_RootToRootCopy, /*OpIdx*/2, // ws
8985 GIR_RootToRootCopy, /*OpIdx*/3, // wt
8986 GIR_RootConstrainSelectedInstOperands,
8987 // GIR_Coverage, 673,
8988 GIR_EraseRootFromParent_Done,
8989 // Label 637: @22499
8990 GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(22544), // Rule ID 698 //
8991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
8992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
8993 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
8994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
8995 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
8996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
8997 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8998 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
8999 // (intrinsic_wo_chain:{ *:[v8f16] } 7440:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9000 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
9001 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9002 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9003 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9004 GIR_RootConstrainSelectedInstOperands,
9005 // GIR_Coverage, 698,
9006 GIR_EraseRootFromParent_Done,
9007 // Label 638: @22544
9008 GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(22589), // Rule ID 699 //
9009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9010 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
9011 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9012 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9013 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9014 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9016 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9017 // (intrinsic_wo_chain:{ *:[v4f32] } 7441:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
9019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9020 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9021 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9022 GIR_RootConstrainSelectedInstOperands,
9023 // GIR_Coverage, 699,
9024 GIR_EraseRootFromParent_Done,
9025 // Label 639: @22589
9026 GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(22634), // Rule ID 726 //
9027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9028 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
9029 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9030 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9033 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9034 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9035 // (intrinsic_wo_chain:{ *:[v4f32] } 7467:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
9037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9038 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9039 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9040 GIR_RootConstrainSelectedInstOperands,
9041 // GIR_Coverage, 726,
9042 GIR_EraseRootFromParent_Done,
9043 // Label 640: @22634
9044 GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(22679), // Rule ID 727 //
9045 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9046 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
9047 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9048 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9049 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9050 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9051 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9052 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9053 // (intrinsic_wo_chain:{ *:[v2f64] } 7466:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
9055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9056 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9057 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9058 GIR_RootConstrainSelectedInstOperands,
9059 // GIR_Coverage, 727,
9060 GIR_EraseRootFromParent_Done,
9061 // Label 641: @22679
9062 GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(22724), // Rule ID 728 //
9063 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9064 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
9065 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9067 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9068 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9069 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9070 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9071 // (intrinsic_wo_chain:{ *:[v4f32] } 7465:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9072 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
9073 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9074 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9075 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9076 GIR_RootConstrainSelectedInstOperands,
9077 // GIR_Coverage, 728,
9078 GIR_EraseRootFromParent_Done,
9079 // Label 642: @22724
9080 GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(22769), // Rule ID 729 //
9081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9082 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
9083 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9084 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9085 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9086 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9087 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9088 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9089 // (intrinsic_wo_chain:{ *:[v2f64] } 7464:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9090 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
9091 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9092 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9093 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9094 GIR_RootConstrainSelectedInstOperands,
9095 // GIR_Coverage, 729,
9096 GIR_EraseRootFromParent_Done,
9097 // Label 643: @22769
9098 GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(22814), // Rule ID 730 //
9099 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9100 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
9101 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9102 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9103 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9104 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9105 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9106 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9107 // (intrinsic_wo_chain:{ *:[v4f32] } 7471:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
9109 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9110 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9111 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9112 GIR_RootConstrainSelectedInstOperands,
9113 // GIR_Coverage, 730,
9114 GIR_EraseRootFromParent_Done,
9115 // Label 644: @22814
9116 GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(22859), // Rule ID 731 //
9117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
9119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9123 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9124 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9125 // (intrinsic_wo_chain:{ *:[v2f64] } 7470:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9126 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
9127 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9128 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9129 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9130 GIR_RootConstrainSelectedInstOperands,
9131 // GIR_Coverage, 731,
9132 GIR_EraseRootFromParent_Done,
9133 // Label 645: @22859
9134 GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(22904), // Rule ID 732 //
9135 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9136 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
9137 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9138 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9139 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9140 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9141 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9142 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9143 // (intrinsic_wo_chain:{ *:[v4f32] } 7469:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9144 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
9145 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9146 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9147 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9148 GIR_RootConstrainSelectedInstOperands,
9149 // GIR_Coverage, 732,
9150 GIR_EraseRootFromParent_Done,
9151 // Label 646: @22904
9152 GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(22949), // Rule ID 733 //
9153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
9155 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9156 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9157 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9159 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9160 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9161 // (intrinsic_wo_chain:{ *:[v2f64] } 7468:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9162 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
9163 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9164 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9165 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9166 GIR_RootConstrainSelectedInstOperands,
9167 // GIR_Coverage, 733,
9168 GIR_EraseRootFromParent_Done,
9169 // Label 647: @22949
9170 GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(22994), // Rule ID 744 //
9171 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9172 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
9173 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9174 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9175 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9176 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9177 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9178 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9179 // (intrinsic_wo_chain:{ *:[v4i32] } 7483:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9180 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
9181 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9182 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9183 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9184 GIR_RootConstrainSelectedInstOperands,
9185 // GIR_Coverage, 744,
9186 GIR_EraseRootFromParent_Done,
9187 // Label 648: @22994
9188 GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(23039), // Rule ID 745 //
9189 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
9191 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9192 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9193 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9195 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9196 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9197 // (intrinsic_wo_chain:{ *:[v2i64] } 7482:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
9199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9200 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9201 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9202 GIR_RootConstrainSelectedInstOperands,
9203 // GIR_Coverage, 745,
9204 GIR_EraseRootFromParent_Done,
9205 // Label 649: @23039
9206 GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(23084), // Rule ID 746 //
9207 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9208 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
9209 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9210 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9211 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9212 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9213 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9214 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9215 // (intrinsic_wo_chain:{ *:[v4i32] } 7485:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9216 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
9217 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9218 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9219 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9220 GIR_RootConstrainSelectedInstOperands,
9221 // GIR_Coverage, 746,
9222 GIR_EraseRootFromParent_Done,
9223 // Label 650: @23084
9224 GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(23129), // Rule ID 747 //
9225 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9226 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
9227 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9228 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9229 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9230 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9231 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9232 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9233 // (intrinsic_wo_chain:{ *:[v2i64] } 7484:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9234 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
9235 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9236 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9237 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9238 GIR_RootConstrainSelectedInstOperands,
9239 // GIR_Coverage, 747,
9240 GIR_EraseRootFromParent_Done,
9241 // Label 651: @23129
9242 GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(23174), // Rule ID 748 //
9243 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9244 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
9245 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9246 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9247 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9248 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9249 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9250 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9251 // (intrinsic_wo_chain:{ *:[v4i32] } 7487:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9252 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
9253 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9254 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9255 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9256 GIR_RootConstrainSelectedInstOperands,
9257 // GIR_Coverage, 748,
9258 GIR_EraseRootFromParent_Done,
9259 // Label 652: @23174
9260 GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(23219), // Rule ID 749 //
9261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9262 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
9263 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9265 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9266 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9267 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9268 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9269 // (intrinsic_wo_chain:{ *:[v2i64] } 7486:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
9271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9272 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9273 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9274 GIR_RootConstrainSelectedInstOperands,
9275 // GIR_Coverage, 749,
9276 GIR_EraseRootFromParent_Done,
9277 // Label 653: @23219
9278 GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(23264), // Rule ID 750 //
9279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9280 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
9281 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9282 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9283 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9285 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9286 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9287 // (intrinsic_wo_chain:{ *:[v4i32] } 7489:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9288 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
9289 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9290 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9291 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9292 GIR_RootConstrainSelectedInstOperands,
9293 // GIR_Coverage, 750,
9294 GIR_EraseRootFromParent_Done,
9295 // Label 654: @23264
9296 GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(23309), // Rule ID 751 //
9297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9298 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
9299 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9300 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9301 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9302 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9303 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9304 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9305 // (intrinsic_wo_chain:{ *:[v2i64] } 7488:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
9307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9308 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9309 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9310 GIR_RootConstrainSelectedInstOperands,
9311 // GIR_Coverage, 751,
9312 GIR_EraseRootFromParent_Done,
9313 // Label 655: @23309
9314 GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(23354), // Rule ID 752 //
9315 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
9317 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9318 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9319 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9321 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9322 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9323 // (intrinsic_wo_chain:{ *:[v4i32] } 7491:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9324 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
9325 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9326 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9327 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9328 GIR_RootConstrainSelectedInstOperands,
9329 // GIR_Coverage, 752,
9330 GIR_EraseRootFromParent_Done,
9331 // Label 656: @23354
9332 GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(23399), // Rule ID 753 //
9333 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9334 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
9335 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9336 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9337 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9338 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9339 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9340 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9341 // (intrinsic_wo_chain:{ *:[v2i64] } 7490:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9342 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
9343 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9344 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9345 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9346 GIR_RootConstrainSelectedInstOperands,
9347 // GIR_Coverage, 753,
9348 GIR_EraseRootFromParent_Done,
9349 // Label 657: @23399
9350 GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(23444), // Rule ID 754 //
9351 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
9353 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9354 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9355 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9356 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9357 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9358 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9359 // (intrinsic_wo_chain:{ *:[v4i32] } 7493:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
9361 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9362 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9363 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9364 GIR_RootConstrainSelectedInstOperands,
9365 // GIR_Coverage, 754,
9366 GIR_EraseRootFromParent_Done,
9367 // Label 658: @23444
9368 GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(23489), // Rule ID 755 //
9369 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9370 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
9371 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9372 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9373 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9374 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9375 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9376 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9377 // (intrinsic_wo_chain:{ *:[v2i64] } 7492:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9378 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
9379 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9380 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9381 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9382 GIR_RootConstrainSelectedInstOperands,
9383 // GIR_Coverage, 755,
9384 GIR_EraseRootFromParent_Done,
9385 // Label 659: @23489
9386 GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(23534), // Rule ID 760 //
9387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9388 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
9389 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9390 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9391 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9392 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9393 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9394 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9395 // (intrinsic_wo_chain:{ *:[v4i32] } 7499:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9396 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
9397 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9398 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9399 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9400 GIR_RootConstrainSelectedInstOperands,
9401 // GIR_Coverage, 760,
9402 GIR_EraseRootFromParent_Done,
9403 // Label 660: @23534
9404 GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(23579), // Rule ID 761 //
9405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
9407 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9408 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9409 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9410 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9411 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9412 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9413 // (intrinsic_wo_chain:{ *:[v2i64] } 7498:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9414 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
9415 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9416 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9417 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9418 GIR_RootConstrainSelectedInstOperands,
9419 // GIR_Coverage, 761,
9420 GIR_EraseRootFromParent_Done,
9421 // Label 661: @23579
9422 GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(23624), // Rule ID 762 //
9423 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9424 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
9425 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9426 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9427 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9428 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9429 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9430 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9431 // (intrinsic_wo_chain:{ *:[v4i32] } 7501:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
9433 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9434 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9435 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9436 GIR_RootConstrainSelectedInstOperands,
9437 // GIR_Coverage, 762,
9438 GIR_EraseRootFromParent_Done,
9439 // Label 662: @23624
9440 GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(23669), // Rule ID 763 //
9441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9442 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
9443 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9444 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9445 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9446 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9447 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9448 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9449 // (intrinsic_wo_chain:{ *:[v2i64] } 7500:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
9451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9452 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9453 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9454 GIR_RootConstrainSelectedInstOperands,
9455 // GIR_Coverage, 763,
9456 GIR_EraseRootFromParent_Done,
9457 // Label 663: @23669
9458 GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(23714), // Rule ID 764 //
9459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9460 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
9461 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9463 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9465 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9466 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9467 // (intrinsic_wo_chain:{ *:[v4i32] } 7503:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9468 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
9469 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9470 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9471 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9472 GIR_RootConstrainSelectedInstOperands,
9473 // GIR_Coverage, 764,
9474 GIR_EraseRootFromParent_Done,
9475 // Label 664: @23714
9476 GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(23759), // Rule ID 765 //
9477 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9478 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
9479 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9482 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9483 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9484 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9485 // (intrinsic_wo_chain:{ *:[v2i64] } 7502:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9486 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
9487 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9488 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9489 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9490 GIR_RootConstrainSelectedInstOperands,
9491 // GIR_Coverage, 765,
9492 GIR_EraseRootFromParent_Done,
9493 // Label 665: @23759
9494 GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(23804), // Rule ID 766 //
9495 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9496 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
9497 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9498 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9499 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9500 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9501 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9502 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9503 // (intrinsic_wo_chain:{ *:[v4i32] } 7505:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
9505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9506 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9507 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9508 GIR_RootConstrainSelectedInstOperands,
9509 // GIR_Coverage, 766,
9510 GIR_EraseRootFromParent_Done,
9511 // Label 666: @23804
9512 GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(23849), // Rule ID 767 //
9513 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9514 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
9515 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9516 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9517 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9518 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9519 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9520 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9521 // (intrinsic_wo_chain:{ *:[v2i64] } 7504:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9522 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
9523 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9524 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9525 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9526 GIR_RootConstrainSelectedInstOperands,
9527 // GIR_Coverage, 767,
9528 GIR_EraseRootFromParent_Done,
9529 // Label 667: @23849
9530 GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(23894), // Rule ID 768 //
9531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
9533 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9534 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9535 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9537 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9538 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9539 // (intrinsic_wo_chain:{ *:[v4i32] } 7507:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9540 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
9541 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9542 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9543 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9544 GIR_RootConstrainSelectedInstOperands,
9545 // GIR_Coverage, 768,
9546 GIR_EraseRootFromParent_Done,
9547 // Label 668: @23894
9548 GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(23939), // Rule ID 769 //
9549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
9551 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9552 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9553 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9554 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9555 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9556 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9557 // (intrinsic_wo_chain:{ *:[v2i64] } 7506:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9558 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
9559 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9560 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9561 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9562 GIR_RootConstrainSelectedInstOperands,
9563 // GIR_Coverage, 769,
9564 GIR_EraseRootFromParent_Done,
9565 // Label 669: @23939
9566 GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(23984), // Rule ID 774 //
9567 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
9569 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9570 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9571 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9572 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9573 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9574 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9575 // (intrinsic_wo_chain:{ *:[v8i16] } 7512:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
9576 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
9577 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9578 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9579 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9580 GIR_RootConstrainSelectedInstOperands,
9581 // GIR_Coverage, 774,
9582 GIR_EraseRootFromParent_Done,
9583 // Label 670: @23984
9584 GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(24029), // Rule ID 775 //
9585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9586 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
9587 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9588 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9589 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9590 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9591 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9592 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9593 // (intrinsic_wo_chain:{ *:[v4i32] } 7513:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
9594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
9595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9596 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9597 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9598 GIR_RootConstrainSelectedInstOperands,
9599 // GIR_Coverage, 775,
9600 GIR_EraseRootFromParent_Done,
9601 // Label 671: @24029
9602 GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(24074), // Rule ID 780 //
9603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9604 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
9605 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9606 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9607 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9608 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9609 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9610 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9611 // (intrinsic_wo_chain:{ *:[v8i16] } 7519:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9612 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
9613 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9614 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9615 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9616 GIR_RootConstrainSelectedInstOperands,
9617 // GIR_Coverage, 780,
9618 GIR_EraseRootFromParent_Done,
9619 // Label 672: @24074
9620 GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(24119), // Rule ID 781 //
9621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
9623 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9625 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9626 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9627 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9628 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9629 // (intrinsic_wo_chain:{ *:[v4i32] } 7520:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
9631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9632 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9633 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9634 GIR_RootConstrainSelectedInstOperands,
9635 // GIR_Coverage, 781,
9636 GIR_EraseRootFromParent_Done,
9637 // Label 673: @24119
9638 GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(24164), // Rule ID 782 //
9639 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9640 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
9641 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9642 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9643 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9644 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9645 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9646 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9647 // (intrinsic_wo_chain:{ *:[v2i64] } 7518:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9648 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
9649 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9650 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9651 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9652 GIR_RootConstrainSelectedInstOperands,
9653 // GIR_Coverage, 782,
9654 GIR_EraseRootFromParent_Done,
9655 // Label 674: @24164
9656 GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(24209), // Rule ID 783 //
9657 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9658 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
9659 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9663 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9664 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9665 // (intrinsic_wo_chain:{ *:[v8i16] } 7522:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9666 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
9667 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9668 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9669 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9670 GIR_RootConstrainSelectedInstOperands,
9671 // GIR_Coverage, 783,
9672 GIR_EraseRootFromParent_Done,
9673 // Label 675: @24209
9674 GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(24254), // Rule ID 784 //
9675 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9676 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
9677 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9678 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9679 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9680 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9681 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9682 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9683 // (intrinsic_wo_chain:{ *:[v4i32] } 7523:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9684 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
9685 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9686 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9687 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9688 GIR_RootConstrainSelectedInstOperands,
9689 // GIR_Coverage, 784,
9690 GIR_EraseRootFromParent_Done,
9691 // Label 676: @24254
9692 GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(24299), // Rule ID 785 //
9693 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9694 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
9695 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9696 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9697 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9698 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9699 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9700 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9701 // (intrinsic_wo_chain:{ *:[v2i64] } 7521:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9702 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
9703 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9704 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9705 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9706 GIR_RootConstrainSelectedInstOperands,
9707 // GIR_Coverage, 785,
9708 GIR_EraseRootFromParent_Done,
9709 // Label 677: @24299
9710 GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(24344), // Rule ID 786 //
9711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9712 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
9713 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9714 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9715 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9716 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9717 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9718 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9719 // (intrinsic_wo_chain:{ *:[v8i16] } 7525:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
9721 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9722 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9723 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9724 GIR_RootConstrainSelectedInstOperands,
9725 // GIR_Coverage, 786,
9726 GIR_EraseRootFromParent_Done,
9727 // Label 678: @24344
9728 GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(24389), // Rule ID 787 //
9729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9730 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
9731 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9732 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9733 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9734 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9735 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9736 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9737 // (intrinsic_wo_chain:{ *:[v4i32] } 7526:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9738 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
9739 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9740 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9741 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9742 GIR_RootConstrainSelectedInstOperands,
9743 // GIR_Coverage, 787,
9744 GIR_EraseRootFromParent_Done,
9745 // Label 679: @24389
9746 GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(24434), // Rule ID 788 //
9747 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9748 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
9749 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9750 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9752 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9753 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9754 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9755 // (intrinsic_wo_chain:{ *:[v2i64] } 7524:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9756 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
9757 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9758 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9759 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9760 GIR_RootConstrainSelectedInstOperands,
9761 // GIR_Coverage, 788,
9762 GIR_EraseRootFromParent_Done,
9763 // Label 680: @24434
9764 GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(24479), // Rule ID 789 //
9765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
9767 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9768 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9769 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9770 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9771 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9772 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9773 // (intrinsic_wo_chain:{ *:[v8i16] } 7528:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9774 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
9775 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9776 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9777 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9778 GIR_RootConstrainSelectedInstOperands,
9779 // GIR_Coverage, 789,
9780 GIR_EraseRootFromParent_Done,
9781 // Label 681: @24479
9782 GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(24524), // Rule ID 790 //
9783 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9784 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
9785 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9786 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9787 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9788 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9789 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9790 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9791 // (intrinsic_wo_chain:{ *:[v4i32] } 7529:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9792 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
9793 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9794 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9795 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9796 GIR_RootConstrainSelectedInstOperands,
9797 // GIR_Coverage, 790,
9798 GIR_EraseRootFromParent_Done,
9799 // Label 682: @24524
9800 GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(24569), // Rule ID 791 //
9801 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
9803 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9804 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9805 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9806 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9807 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9808 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9809 // (intrinsic_wo_chain:{ *:[v2i64] } 7527:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9810 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
9811 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9812 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9813 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9814 GIR_RootConstrainSelectedInstOperands,
9815 // GIR_Coverage, 791,
9816 GIR_EraseRootFromParent_Done,
9817 // Label 683: @24569
9818 GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(24614), // Rule ID 844 //
9819 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9820 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
9821 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9822 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9823 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9824 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9825 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9826 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9827 // (intrinsic_wo_chain:{ *:[v16i8] } 7583:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
9829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9830 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9831 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9832 GIR_RootConstrainSelectedInstOperands,
9833 // GIR_Coverage, 844,
9834 GIR_EraseRootFromParent_Done,
9835 // Label 684: @24614
9836 GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(24659), // Rule ID 845 //
9837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9838 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
9839 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9840 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9841 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9842 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9843 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9844 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9845 // (intrinsic_wo_chain:{ *:[v8i16] } 7585:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9846 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
9847 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9848 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9849 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9850 GIR_RootConstrainSelectedInstOperands,
9851 // GIR_Coverage, 845,
9852 GIR_EraseRootFromParent_Done,
9853 // Label 685: @24659
9854 GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(24704), // Rule ID 846 //
9855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9856 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
9857 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9859 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9861 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9862 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9863 // (intrinsic_wo_chain:{ *:[v4i32] } 7586:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9864 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
9865 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9866 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9867 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9868 GIR_RootConstrainSelectedInstOperands,
9869 // GIR_Coverage, 846,
9870 GIR_EraseRootFromParent_Done,
9871 // Label 686: @24704
9872 GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(24749), // Rule ID 847 //
9873 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9874 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
9875 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9876 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9877 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9878 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9879 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9880 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9881 // (intrinsic_wo_chain:{ *:[v2i64] } 7584:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9882 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
9883 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9884 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9885 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9886 GIR_RootConstrainSelectedInstOperands,
9887 // GIR_Coverage, 847,
9888 GIR_EraseRootFromParent_Done,
9889 // Label 687: @24749
9890 GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(24794), // Rule ID 864 //
9891 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9892 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
9893 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
9894 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9895 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
9896 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9897 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9898 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
9899 // (intrinsic_wo_chain:{ *:[v16i8] } 7603:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
9900 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
9901 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9902 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9903 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9904 GIR_RootConstrainSelectedInstOperands,
9905 // GIR_Coverage, 864,
9906 GIR_EraseRootFromParent_Done,
9907 // Label 688: @24794
9908 GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(24839), // Rule ID 865 //
9909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
9911 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9912 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9913 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9915 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9916 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9917 // (intrinsic_wo_chain:{ *:[v8i16] } 7605:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
9919 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9920 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9921 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9922 GIR_RootConstrainSelectedInstOperands,
9923 // GIR_Coverage, 865,
9924 GIR_EraseRootFromParent_Done,
9925 // Label 689: @24839
9926 GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(24884), // Rule ID 866 //
9927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9928 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
9929 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9930 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9931 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9932 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9933 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9934 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9935 // (intrinsic_wo_chain:{ *:[v4i32] } 7606:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9936 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
9937 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9938 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9939 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9940 GIR_RootConstrainSelectedInstOperands,
9941 // GIR_Coverage, 866,
9942 GIR_EraseRootFromParent_Done,
9943 // Label 690: @24884
9944 GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(24929), // Rule ID 867 //
9945 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
9947 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
9948 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9949 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
9950 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9951 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9952 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
9953 // (intrinsic_wo_chain:{ *:[v2i64] } 7604:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
9954 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
9955 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9956 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9957 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9958 GIR_RootConstrainSelectedInstOperands,
9959 // GIR_Coverage, 867,
9960 GIR_EraseRootFromParent_Done,
9961 // Label 691: @24929
9962 GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(24974), // Rule ID 900 //
9963 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9964 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
9965 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
9966 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9967 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
9968 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9969 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9970 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
9971 // (intrinsic_wo_chain:{ *:[v8i16] } 7645:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
9972 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
9973 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9974 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9975 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9976 GIR_RootConstrainSelectedInstOperands,
9977 // GIR_Coverage, 900,
9978 GIR_EraseRootFromParent_Done,
9979 // Label 692: @24974
9980 GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(25019), // Rule ID 901 //
9981 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
9982 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
9983 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
9984 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9985 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
9986 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9987 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9988 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
9989 // (intrinsic_wo_chain:{ *:[v4i32] } 7646:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
9990 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
9991 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
9992 GIR_RootToRootCopy, /*OpIdx*/2, // ws
9993 GIR_RootToRootCopy, /*OpIdx*/3, // wt
9994 GIR_RootConstrainSelectedInstOperands,
9995 // GIR_Coverage, 901,
9996 GIR_EraseRootFromParent_Done,
9997 // Label 693: @25019
9998 GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(25064), // Rule ID 902 //
9999 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
10001 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10002 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10003 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10004 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10005 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10006 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10007 // (intrinsic_wo_chain:{ *:[v8i16] } 7656:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10008 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
10009 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10010 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10011 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10012 GIR_RootConstrainSelectedInstOperands,
10013 // GIR_Coverage, 902,
10014 GIR_EraseRootFromParent_Done,
10015 // Label 694: @25064
10016 GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(25109), // Rule ID 903 //
10017 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
10019 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10020 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10021 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10022 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10023 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10024 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10025 // (intrinsic_wo_chain:{ *:[v4i32] } 7657:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10026 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
10027 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10028 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10029 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10030 GIR_RootConstrainSelectedInstOperands,
10031 // GIR_Coverage, 903,
10032 GIR_EraseRootFromParent_Done,
10033 // Label 695: @25109
10034 GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(25154), // Rule ID 981 //
10035 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10036 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
10037 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10038 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10039 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10040 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10041 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10042 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10043 // (intrinsic_wo_chain:{ *:[v16i8] } 7770:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10044 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
10045 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10046 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10047 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10048 GIR_RootConstrainSelectedInstOperands,
10049 // GIR_Coverage, 981,
10050 GIR_EraseRootFromParent_Done,
10051 // Label 696: @25154
10052 GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(25199), // Rule ID 982 //
10053 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10054 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
10055 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10056 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10057 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10058 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10059 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10060 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10061 // (intrinsic_wo_chain:{ *:[v8i16] } 7772:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10062 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
10063 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10064 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10065 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10066 GIR_RootConstrainSelectedInstOperands,
10067 // GIR_Coverage, 982,
10068 GIR_EraseRootFromParent_Done,
10069 // Label 697: @25199
10070 GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(25244), // Rule ID 983 //
10071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10072 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
10073 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10074 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10075 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10076 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10077 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10078 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10079 // (intrinsic_wo_chain:{ *:[v4i32] } 7773:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10080 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
10081 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10082 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10083 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10084 GIR_RootConstrainSelectedInstOperands,
10085 // GIR_Coverage, 983,
10086 GIR_EraseRootFromParent_Done,
10087 // Label 698: @25244
10088 GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(25289), // Rule ID 984 //
10089 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10090 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
10091 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10092 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10093 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10094 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10095 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10096 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10097 // (intrinsic_wo_chain:{ *:[v2i64] } 7771:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10098 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
10099 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10100 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10101 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10102 GIR_RootConstrainSelectedInstOperands,
10103 // GIR_Coverage, 984,
10104 GIR_EraseRootFromParent_Done,
10105 // Label 699: @25289
10106 GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(25334), // Rule ID 997 //
10107 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10108 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
10109 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10110 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10111 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10112 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10113 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10114 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10115 // (intrinsic_wo_chain:{ *:[v16i8] } 7786:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10116 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
10117 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10118 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10119 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10120 GIR_RootConstrainSelectedInstOperands,
10121 // GIR_Coverage, 997,
10122 GIR_EraseRootFromParent_Done,
10123 // Label 700: @25334
10124 GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(25379), // Rule ID 998 //
10125 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10126 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
10127 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10128 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10129 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10130 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10131 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10132 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10133 // (intrinsic_wo_chain:{ *:[v8i16] } 7788:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
10135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10136 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10137 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10138 GIR_RootConstrainSelectedInstOperands,
10139 // GIR_Coverage, 998,
10140 GIR_EraseRootFromParent_Done,
10141 // Label 701: @25379
10142 GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(25424), // Rule ID 999 //
10143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10144 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
10145 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10146 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10147 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10148 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10149 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10150 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10151 // (intrinsic_wo_chain:{ *:[v4i32] } 7789:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10152 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
10153 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10154 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10155 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10156 GIR_RootConstrainSelectedInstOperands,
10157 // GIR_Coverage, 999,
10158 GIR_EraseRootFromParent_Done,
10159 // Label 702: @25424
10160 GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(25469), // Rule ID 1000 //
10161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
10163 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10165 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10166 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10167 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10168 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10169 // (intrinsic_wo_chain:{ *:[v2i64] } 7787:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10170 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
10171 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10172 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10173 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10174 GIR_RootConstrainSelectedInstOperands,
10175 // GIR_Coverage, 1000,
10176 GIR_EraseRootFromParent_Done,
10177 // Label 703: @25469
10178 GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(25514), // Rule ID 1009 //
10179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10180 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
10181 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10182 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10183 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10184 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10185 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10186 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10187 // (intrinsic_wo_chain:{ *:[v16i8] } 7807:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10188 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
10189 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10190 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10191 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10192 GIR_RootConstrainSelectedInstOperands,
10193 // GIR_Coverage, 1009,
10194 GIR_EraseRootFromParent_Done,
10195 // Label 704: @25514
10196 GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(25559), // Rule ID 1010 //
10197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
10199 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10200 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10201 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10202 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10203 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10204 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10205 // (intrinsic_wo_chain:{ *:[v8i16] } 7809:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
10207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10208 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10209 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10210 GIR_RootConstrainSelectedInstOperands,
10211 // GIR_Coverage, 1010,
10212 GIR_EraseRootFromParent_Done,
10213 // Label 705: @25559
10214 GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(25604), // Rule ID 1011 //
10215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10216 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
10217 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10218 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10219 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10220 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10221 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10222 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10223 // (intrinsic_wo_chain:{ *:[v4i32] } 7810:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
10225 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10226 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10227 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10228 GIR_RootConstrainSelectedInstOperands,
10229 // GIR_Coverage, 1011,
10230 GIR_EraseRootFromParent_Done,
10231 // Label 706: @25604
10232 GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(25649), // Rule ID 1012 //
10233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10234 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
10235 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10236 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10237 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10238 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10239 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10240 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10241 // (intrinsic_wo_chain:{ *:[v2i64] } 7808:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10242 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
10243 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10244 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10245 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10246 GIR_RootConstrainSelectedInstOperands,
10247 // GIR_Coverage, 1012,
10248 GIR_EraseRootFromParent_Done,
10249 // Label 707: @25649
10250 GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(25694), // Rule ID 1013 //
10251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
10253 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10254 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10255 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10256 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10257 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10258 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10259 // (intrinsic_wo_chain:{ *:[v16i8] } 7811:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10260 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
10261 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10262 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10263 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10264 GIR_RootConstrainSelectedInstOperands,
10265 // GIR_Coverage, 1013,
10266 GIR_EraseRootFromParent_Done,
10267 // Label 708: @25694
10268 GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(25739), // Rule ID 1014 //
10269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10270 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
10271 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10272 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10273 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10274 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10275 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10276 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10277 // (intrinsic_wo_chain:{ *:[v8i16] } 7813:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10278 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
10279 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10280 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10281 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10282 GIR_RootConstrainSelectedInstOperands,
10283 // GIR_Coverage, 1014,
10284 GIR_EraseRootFromParent_Done,
10285 // Label 709: @25739
10286 GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(25784), // Rule ID 1015 //
10287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10288 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
10289 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10290 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10291 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10292 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10293 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10294 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10295 // (intrinsic_wo_chain:{ *:[v4i32] } 7814:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10296 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
10297 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10298 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10299 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10300 GIR_RootConstrainSelectedInstOperands,
10301 // GIR_Coverage, 1015,
10302 GIR_EraseRootFromParent_Done,
10303 // Label 710: @25784
10304 GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(25829), // Rule ID 1016 //
10305 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10306 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
10307 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10308 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10309 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10310 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10311 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10312 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10313 // (intrinsic_wo_chain:{ *:[v2i64] } 7812:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10314 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
10315 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10316 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10317 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10318 GIR_RootConstrainSelectedInstOperands,
10319 // GIR_Coverage, 1016,
10320 GIR_EraseRootFromParent_Done,
10321 // Label 711: @25829
10322 GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(25874), // Rule ID 1017 //
10323 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10324 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
10325 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10326 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10327 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10328 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10329 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10330 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10331 // (intrinsic_wo_chain:{ *:[v16i8] } 7815:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10332 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
10333 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10334 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10335 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10336 GIR_RootConstrainSelectedInstOperands,
10337 // GIR_Coverage, 1017,
10338 GIR_EraseRootFromParent_Done,
10339 // Label 712: @25874
10340 GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(25919), // Rule ID 1018 //
10341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
10343 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10344 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10345 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10346 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10347 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10348 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10349 // (intrinsic_wo_chain:{ *:[v8i16] } 7817:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10350 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
10351 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10352 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10353 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10354 GIR_RootConstrainSelectedInstOperands,
10355 // GIR_Coverage, 1018,
10356 GIR_EraseRootFromParent_Done,
10357 // Label 713: @25919
10358 GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(25964), // Rule ID 1019 //
10359 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10360 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
10361 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10362 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10363 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10364 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10365 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10366 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10367 // (intrinsic_wo_chain:{ *:[v4i32] } 7818:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
10369 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10370 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10371 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10372 GIR_RootConstrainSelectedInstOperands,
10373 // GIR_Coverage, 1019,
10374 GIR_EraseRootFromParent_Done,
10375 // Label 714: @25964
10376 GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(26009), // Rule ID 1020 //
10377 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10378 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
10379 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10381 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10382 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10383 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10384 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10385 // (intrinsic_wo_chain:{ *:[v2i64] } 7816:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10386 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
10387 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10388 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10389 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10390 GIR_RootConstrainSelectedInstOperands,
10391 // GIR_Coverage, 1020,
10392 GIR_EraseRootFromParent_Done,
10393 // Label 715: @26009
10394 GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(26054), // Rule ID 1021 //
10395 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
10397 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
10398 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10399 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
10400 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10401 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10402 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
10403 // (intrinsic_wo_chain:{ *:[v16i8] } 7819:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
10404 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
10405 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10406 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10407 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10408 GIR_RootConstrainSelectedInstOperands,
10409 // GIR_Coverage, 1021,
10410 GIR_EraseRootFromParent_Done,
10411 // Label 716: @26054
10412 GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(26099), // Rule ID 1022 //
10413 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10414 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
10415 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
10416 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10417 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
10418 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10419 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10420 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
10421 // (intrinsic_wo_chain:{ *:[v8i16] } 7821:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
10422 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
10423 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10424 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10425 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10426 GIR_RootConstrainSelectedInstOperands,
10427 // GIR_Coverage, 1022,
10428 GIR_EraseRootFromParent_Done,
10429 // Label 717: @26099
10430 GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(26144), // Rule ID 1023 //
10431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10432 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
10433 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
10434 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10435 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
10436 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10437 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10438 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
10439 // (intrinsic_wo_chain:{ *:[v4i32] } 7822:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
10440 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
10441 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10442 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10443 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10444 GIR_RootConstrainSelectedInstOperands,
10445 // GIR_Coverage, 1023,
10446 GIR_EraseRootFromParent_Done,
10447 // Label 718: @26144
10448 GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(26189), // Rule ID 1024 //
10449 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
10450 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
10451 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
10452 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10453 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
10454 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10455 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10456 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
10457 // (intrinsic_wo_chain:{ *:[v2i64] } 7820:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
10458 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
10459 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
10460 GIR_RootToRootCopy, /*OpIdx*/2, // ws
10461 GIR_RootToRootCopy, /*OpIdx*/3, // wt
10462 GIR_RootConstrainSelectedInstOperands,
10463 // GIR_Coverage, 1024,
10464 GIR_EraseRootFromParent_Done,
10465 // Label 719: @26189
10466 GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(26237), // Rule ID 1223 //
10467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
10469 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10471 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10472 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10474 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10475 // (intrinsic_wo_chain:{ *:[v2i16] } 7181:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10476 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
10477 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10478 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10479 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10480 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
10481 GIR_RootConstrainSelectedInstOperands,
10482 // GIR_Coverage, 1223,
10483 GIR_EraseRootFromParent_Done,
10484 // Label 720: @26237
10485 GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(26285), // Rule ID 1225 //
10486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10487 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
10488 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10489 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10490 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10491 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10492 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10493 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10494 // (intrinsic_wo_chain:{ *:[v4i8] } 7203:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10495 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
10496 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10497 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10498 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10499 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
10500 GIR_RootConstrainSelectedInstOperands,
10501 // GIR_Coverage, 1225,
10502 GIR_EraseRootFromParent_Done,
10503 // Label 721: @26285
10504 GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(26330), // Rule ID 1246 //
10505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10506 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
10507 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10508 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10509 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10510 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10512 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10513 // (intrinsic_wo_chain:{ *:[v2i16] } 7731:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
10515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10516 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10517 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10518 GIR_RootConstrainSelectedInstOperands,
10519 // GIR_Coverage, 1246,
10520 GIR_EraseRootFromParent_Done,
10521 // Label 722: @26330
10522 GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(26375), // Rule ID 1247 //
10523 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
10525 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10526 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10527 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10528 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10529 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10530 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10531 // (intrinsic_wo_chain:{ *:[v2i16] } 7733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10532 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
10533 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10534 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10535 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10536 GIR_RootConstrainSelectedInstOperands,
10537 // GIR_Coverage, 1247,
10538 GIR_EraseRootFromParent_Done,
10539 // Label 723: @26375
10540 GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(26420), // Rule ID 1248 //
10541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
10543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
10544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10545 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10546 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10547 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10548 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10549 // (intrinsic_wo_chain:{ *:[i32] } 7735:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10550 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
10551 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10552 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10553 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10554 GIR_RootConstrainSelectedInstOperands,
10555 // GIR_Coverage, 1248,
10556 GIR_EraseRootFromParent_Done,
10557 // Label 724: @26420
10558 GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(26465), // Rule ID 1250 //
10559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10560 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
10561 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10562 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10563 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10564 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10565 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10566 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10567 // (intrinsic_wo_chain:{ *:[v4i8] } 7737:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
10569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10570 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10571 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10572 GIR_RootConstrainSelectedInstOperands,
10573 // GIR_Coverage, 1250,
10574 GIR_EraseRootFromParent_Done,
10575 // Label 725: @26465
10576 GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(26513), // Rule ID 1261 //
10577 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10578 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
10579 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10583 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10584 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10585 // (intrinsic_wo_chain:{ *:[v2i16] } 7801:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10586 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
10587 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10588 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10589 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10590 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
10591 GIR_RootConstrainSelectedInstOperands,
10592 // GIR_Coverage, 1261,
10593 GIR_EraseRootFromParent_Done,
10594 // Label 726: @26513
10595 GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(26561), // Rule ID 1263 //
10596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10597 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
10598 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10599 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10600 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10601 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10602 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10603 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10604 // (intrinsic_wo_chain:{ *:[v4i8] } 7826:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10605 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
10606 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10607 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10608 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10609 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
10610 GIR_RootConstrainSelectedInstOperands,
10611 // GIR_Coverage, 1263,
10612 GIR_EraseRootFromParent_Done,
10613 // Label 727: @26561
10614 GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(26606), // Rule ID 1273 //
10615 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10616 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
10617 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10618 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10619 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10621 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10622 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10623 // (intrinsic_wo_chain:{ *:[v2i16] } 7706:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10624 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
10625 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10626 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10627 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10628 GIR_RootConstrainSelectedInstOperands,
10629 // GIR_Coverage, 1273,
10630 GIR_EraseRootFromParent_Done,
10631 // Label 728: @26606
10632 GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(26651), // Rule ID 1274 //
10633 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10634 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
10635 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10636 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10637 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10638 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10639 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10640 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10641 // (intrinsic_wo_chain:{ *:[v4i8] } 7707:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10642 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
10643 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10644 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10645 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10646 GIR_RootConstrainSelectedInstOperands,
10647 // GIR_Coverage, 1274,
10648 GIR_EraseRootFromParent_Done,
10649 // Label 729: @26651
10650 GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(26696), // Rule ID 1293 //
10651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10652 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
10653 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10654 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10655 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10656 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10657 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10658 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10659 // (intrinsic_wo_chain:{ *:[v2i16] } 7678:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10660 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
10661 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10662 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10663 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10664 GIR_RootConstrainSelectedInstOperands,
10665 // GIR_Coverage, 1293,
10666 GIR_EraseRootFromParent_Done,
10667 // Label 730: @26696
10668 GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(26741), // Rule ID 1299 //
10669 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
10670 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
10671 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
10672 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10673 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10674 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10675 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10676 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10677 // (intrinsic_wo_chain:{ *:[i32] } 7631:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10678 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
10679 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10680 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10681 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10682 GIR_RootConstrainSelectedInstOperands,
10683 // GIR_Coverage, 1299,
10684 GIR_EraseRootFromParent_Done,
10685 // Label 731: @26741
10686 GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(26786), // Rule ID 1312 //
10687 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10688 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
10689 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10690 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10691 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10692 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10693 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10694 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10695 // (intrinsic_wo_chain:{ *:[v2i16] } 7183:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10696 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
10697 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10698 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10699 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10700 GIR_RootConstrainSelectedInstOperands,
10701 // GIR_Coverage, 1312,
10702 GIR_EraseRootFromParent_Done,
10703 // Label 732: @26786
10704 GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(26831), // Rule ID 1313 //
10705 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10706 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
10707 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10708 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10709 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10710 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10711 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10712 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10713 // (intrinsic_wo_chain:{ *:[v2i16] } 7184:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
10715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10716 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10717 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10718 GIR_RootConstrainSelectedInstOperands,
10719 // GIR_Coverage, 1313,
10720 GIR_EraseRootFromParent_Done,
10721 // Label 733: @26831
10722 GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(26876), // Rule ID 1314 //
10723 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10724 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
10725 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
10726 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10727 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10728 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10729 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10730 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10731 // (intrinsic_wo_chain:{ *:[i32] } 7186:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10732 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
10733 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10734 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10735 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10736 GIR_RootConstrainSelectedInstOperands,
10737 // GIR_Coverage, 1314,
10738 GIR_EraseRootFromParent_Done,
10739 // Label 734: @26876
10740 GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(26921), // Rule ID 1315 //
10741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10742 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
10743 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
10744 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10745 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10746 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10747 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10748 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10749 // (intrinsic_wo_chain:{ *:[i32] } 7185:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
10751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10752 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10753 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10754 GIR_RootConstrainSelectedInstOperands,
10755 // GIR_Coverage, 1315,
10756 GIR_EraseRootFromParent_Done,
10757 // Label 735: @26921
10758 GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(26966), // Rule ID 1318 //
10759 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
10761 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10762 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10763 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10764 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10765 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10766 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10767 // (intrinsic_wo_chain:{ *:[v4i8] } 7204:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10768 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
10769 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10770 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10771 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10772 GIR_RootConstrainSelectedInstOperands,
10773 // GIR_Coverage, 1318,
10774 GIR_EraseRootFromParent_Done,
10775 // Label 736: @26966
10776 GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(27011), // Rule ID 1319 //
10777 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10778 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
10779 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10780 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10781 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10782 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10783 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10784 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10785 // (intrinsic_wo_chain:{ *:[v4i8] } 7205:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10786 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
10787 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10788 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10789 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10790 GIR_RootConstrainSelectedInstOperands,
10791 // GIR_Coverage, 1319,
10792 GIR_EraseRootFromParent_Done,
10793 // Label 737: @27011
10794 GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(27056), // Rule ID 1325 //
10795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10796 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
10797 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10798 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10799 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10800 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10801 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10802 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10803 // (intrinsic_wo_chain:{ *:[v4i8] } 7732:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
10805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10806 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10807 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10808 GIR_RootConstrainSelectedInstOperands,
10809 // GIR_Coverage, 1325,
10810 GIR_EraseRootFromParent_Done,
10811 // Label 738: @27056
10812 GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(27101), // Rule ID 1326 //
10813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10814 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
10815 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10816 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10817 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10818 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10819 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10820 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10821 // (intrinsic_wo_chain:{ *:[v4i8] } 7734:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10822 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
10823 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10824 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10825 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10826 GIR_RootConstrainSelectedInstOperands,
10827 // GIR_Coverage, 1326,
10828 GIR_EraseRootFromParent_Done,
10829 // Label 739: @27101
10830 GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(27146), // Rule ID 1331 //
10831 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10832 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
10833 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10834 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10835 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10836 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10837 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10838 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10839 // (intrinsic_wo_chain:{ *:[v2i16] } 7736:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
10840 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
10841 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10842 GIR_RootToRootCopy, /*OpIdx*/2, // rt
10843 GIR_RootToRootCopy, /*OpIdx*/3, // rs
10844 GIR_RootConstrainSelectedInstOperands,
10845 // GIR_Coverage, 1331,
10846 GIR_EraseRootFromParent_Done,
10847 // Label 740: @27146
10848 GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(27191), // Rule ID 1332 //
10849 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10850 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
10851 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10852 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10853 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10854 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10855 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10856 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10857 // (intrinsic_wo_chain:{ *:[v2i16] } 7803:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10858 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
10859 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10860 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10861 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10862 GIR_RootConstrainSelectedInstOperands,
10863 // GIR_Coverage, 1332,
10864 GIR_EraseRootFromParent_Done,
10865 // Label 741: @27191
10866 GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(27236), // Rule ID 1333 //
10867 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
10869 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10870 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10871 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10873 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10874 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10875 // (intrinsic_wo_chain:{ *:[v2i16] } 7804:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
10876 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
10877 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10878 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10879 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10880 GIR_RootConstrainSelectedInstOperands,
10881 // GIR_Coverage, 1333,
10882 GIR_EraseRootFromParent_Done,
10883 // Label 742: @27236
10884 GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(27281), // Rule ID 1334 //
10885 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
10887 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
10888 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10889 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10891 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10892 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10893 // (intrinsic_wo_chain:{ *:[i32] } 7806:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10894 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
10895 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10896 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10897 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10898 GIR_RootConstrainSelectedInstOperands,
10899 // GIR_Coverage, 1334,
10900 GIR_EraseRootFromParent_Done,
10901 // Label 743: @27281
10902 GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(27326), // Rule ID 1335 //
10903 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
10905 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
10906 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
10907 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
10908 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10909 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10910 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
10911 // (intrinsic_wo_chain:{ *:[i32] } 7805:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
10912 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
10913 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10914 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10915 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10916 GIR_RootConstrainSelectedInstOperands,
10917 // GIR_Coverage, 1335,
10918 GIR_EraseRootFromParent_Done,
10919 // Label 744: @27326
10920 GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(27371), // Rule ID 1338 //
10921 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10922 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
10923 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10924 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10925 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10927 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10928 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10929 // (intrinsic_wo_chain:{ *:[v4i8] } 7827:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10930 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
10931 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10932 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10933 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10934 GIR_RootConstrainSelectedInstOperands,
10935 // GIR_Coverage, 1338,
10936 GIR_EraseRootFromParent_Done,
10937 // Label 745: @27371
10938 GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(27416), // Rule ID 1339 //
10939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
10940 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
10941 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10942 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10943 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10944 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10945 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10946 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10947 // (intrinsic_wo_chain:{ *:[v4i8] } 7828:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
10948 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
10949 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10950 GIR_RootToRootCopy, /*OpIdx*/2, // rs
10951 GIR_RootToRootCopy, /*OpIdx*/3, // rt
10952 GIR_RootConstrainSelectedInstOperands,
10953 // GIR_Coverage, 1339,
10954 GIR_EraseRootFromParent_Done,
10955 // Label 746: @27416
10956 GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(27456), // Rule ID 1899 //
10957 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
10958 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
10959 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10960 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10961 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10962 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10963 // (intrinsic_wo_chain:{ *:[v2i16] } 7180:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
10964 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
10965 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10966 GIR_RootToRootCopy, /*OpIdx*/2, // a
10967 GIR_RootToRootCopy, /*OpIdx*/3, // b
10968 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
10969 GIR_RootConstrainSelectedInstOperands,
10970 // GIR_Coverage, 1899,
10971 GIR_EraseRootFromParent_Done,
10972 // Label 747: @27456
10973 GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(27496), // Rule ID 1901 //
10974 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
10975 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
10976 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
10977 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
10978 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
10979 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10980 // (intrinsic_wo_chain:{ *:[v2i16] } 7800:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
10981 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
10982 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
10983 GIR_RootToRootCopy, /*OpIdx*/2, // a
10984 GIR_RootToRootCopy, /*OpIdx*/3, // b
10985 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
10986 GIR_RootConstrainSelectedInstOperands,
10987 // GIR_Coverage, 1901,
10988 GIR_EraseRootFromParent_Done,
10989 // Label 748: @27496
10990 GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(27536), // Rule ID 1905 //
10991 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
10992 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
10993 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
10994 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
10995 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
10996 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
10997 // (intrinsic_wo_chain:{ *:[v4i8] } 7201:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
10998 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
10999 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11000 GIR_RootToRootCopy, /*OpIdx*/2, // a
11001 GIR_RootToRootCopy, /*OpIdx*/3, // b
11002 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11003 GIR_RootConstrainSelectedInstOperands,
11004 // GIR_Coverage, 1905,
11005 GIR_EraseRootFromParent_Done,
11006 // Label 749: @27536
11007 GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(27576), // Rule ID 1907 //
11008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
11009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
11010 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
11011 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
11012 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
11013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11014 // (intrinsic_wo_chain:{ *:[v4i8] } 7824:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
11015 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
11016 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
11017 GIR_RootToRootCopy, /*OpIdx*/2, // a
11018 GIR_RootToRootCopy, /*OpIdx*/3, // b
11019 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
11020 GIR_RootConstrainSelectedInstOperands,
11021 // GIR_Coverage, 1907,
11022 GIR_EraseRootFromParent_Done,
11023 // Label 750: @27576
11024 GIM_Reject,
11025 // Label 536: @27577
11026 GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(30091),
11027 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
11028 GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(27640), // Rule ID 477 //
11029 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11030 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11031 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11032 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11033 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11034 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11035 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11036 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11037 // MIs[0] sa
11038 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11039 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11040 // (intrinsic_wo_chain:{ *:[v2i16] } 7704:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
11042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11043 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11044 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11045 GIR_RootToRootCopy, /*OpIdx*/2, // src
11046 GIR_RootConstrainSelectedInstOperands,
11047 // GIR_Coverage, 477,
11048 GIR_EraseRootFromParent_Done,
11049 // Label 752: @27640
11050 GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(27695), // Rule ID 478 //
11051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11053 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11054 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11055 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11057 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11058 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11059 // MIs[0] sa
11060 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11061 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11062 // (intrinsic_wo_chain:{ *:[v2i16] } 7705:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11063 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
11064 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11065 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11066 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11067 GIR_RootToRootCopy, /*OpIdx*/2, // src
11068 GIR_RootConstrainSelectedInstOperands,
11069 // GIR_Coverage, 478,
11070 GIR_EraseRootFromParent_Done,
11071 // Label 753: @27695
11072 GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(27750), // Rule ID 483 //
11073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11074 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
11075 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11076 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11077 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11078 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11079 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11080 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11081 // MIs[0] sa
11082 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11083 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11084 // (intrinsic_wo_chain:{ *:[i32] } 7217:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11085 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
11086 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11087 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11088 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11089 GIR_RootToRootCopy, /*OpIdx*/2, // src
11090 GIR_RootConstrainSelectedInstOperands,
11091 // GIR_Coverage, 483,
11092 GIR_EraseRootFromParent_Done,
11093 // Label 754: @27750
11094 GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(27805), // Rule ID 484 //
11095 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11096 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
11097 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11098 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11099 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11100 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11101 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11102 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11103 // MIs[0] sa
11104 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11105 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11106 // (intrinsic_wo_chain:{ *:[i32] } 7242:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11107 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
11108 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11109 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11110 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11111 GIR_RootToRootCopy, /*OpIdx*/2, // src
11112 GIR_RootConstrainSelectedInstOperands,
11113 // GIR_Coverage, 484,
11114 GIR_EraseRootFromParent_Done,
11115 // Label 755: @27805
11116 GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(27860), // Rule ID 485 //
11117 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
11118 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
11119 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11123 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11124 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11125 // MIs[0] sa
11126 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11127 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11128 // (intrinsic_wo_chain:{ *:[i32] } 7710:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11129 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
11130 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11131 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11132 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11133 GIR_RootToRootCopy, /*OpIdx*/2, // src
11134 GIR_RootConstrainSelectedInstOperands,
11135 // GIR_Coverage, 485,
11136 GIR_EraseRootFromParent_Done,
11137 // Label 756: @27860
11138 GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(27915), // Rule ID 953 //
11139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11140 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
11141 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11142 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11143 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11144 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11145 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11146 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11147 // MIs[0] n
11148 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11149 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
11150 // (intrinsic_wo_chain:{ *:[v16i8] } 7742:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
11151 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
11152 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11153 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11154 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11155 GIR_RootToRootCopy, /*OpIdx*/4, // n
11156 GIR_RootConstrainSelectedInstOperands,
11157 // GIR_Coverage, 953,
11158 GIR_EraseRootFromParent_Done,
11159 // Label 757: @27915
11160 GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(27970), // Rule ID 954 //
11161 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11162 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
11163 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11164 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11165 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11166 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11167 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11168 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11169 // MIs[0] n
11170 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11171 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
11172 // (intrinsic_wo_chain:{ *:[v8i16] } 7744:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
11173 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
11174 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11175 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11176 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11177 GIR_RootToRootCopy, /*OpIdx*/4, // n
11178 GIR_RootConstrainSelectedInstOperands,
11179 // GIR_Coverage, 954,
11180 GIR_EraseRootFromParent_Done,
11181 // Label 758: @27970
11182 GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(28025), // Rule ID 955 //
11183 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11184 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
11185 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11187 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11189 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11190 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11191 // MIs[0] n
11192 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11193 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
11194 // (intrinsic_wo_chain:{ *:[v4i32] } 7745:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
11195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
11196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11197 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11198 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11199 GIR_RootToRootCopy, /*OpIdx*/4, // n
11200 GIR_RootConstrainSelectedInstOperands,
11201 // GIR_Coverage, 955,
11202 GIR_EraseRootFromParent_Done,
11203 // Label 759: @28025
11204 GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(28080), // Rule ID 956 //
11205 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11206 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
11207 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11208 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11209 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11210 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11211 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11212 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11213 // MIs[0] n
11214 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11215 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
11216 // (intrinsic_wo_chain:{ *:[v2i64] } 7743:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
11217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
11218 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11219 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11220 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11221 GIR_RootToRootCopy, /*OpIdx*/4, // n
11222 GIR_RootConstrainSelectedInstOperands,
11223 // GIR_Coverage, 956,
11224 GIR_EraseRootFromParent_Done,
11225 // Label 760: @28080
11226 GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(28135), // Rule ID 1349 //
11227 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11228 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
11229 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11230 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11231 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11232 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11233 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11234 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11235 // MIs[0] sa
11236 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11237 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11238 // (intrinsic_wo_chain:{ *:[v2i16] } 7704:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11239 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
11240 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11241 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11242 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11243 GIR_RootToRootCopy, /*OpIdx*/2, // src
11244 GIR_RootConstrainSelectedInstOperands,
11245 // GIR_Coverage, 1349,
11246 GIR_EraseRootFromParent_Done,
11247 // Label 761: @28135
11248 GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(28190), // Rule ID 1350 //
11249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11250 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
11251 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
11252 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11253 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11254 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
11255 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11256 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11257 // MIs[0] sa
11258 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11259 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11260 // (intrinsic_wo_chain:{ *:[v2i16] } 7705:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11261 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
11262 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11263 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11264 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11265 GIR_RootToRootCopy, /*OpIdx*/2, // src
11266 GIR_RootConstrainSelectedInstOperands,
11267 // GIR_Coverage, 1350,
11268 GIR_EraseRootFromParent_Done,
11269 // Label 762: @28190
11270 GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(28245), // Rule ID 1351 //
11271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11272 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
11273 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11274 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11275 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11276 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11277 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11278 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11279 // MIs[0] sa
11280 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11281 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11282 // (intrinsic_wo_chain:{ *:[i32] } 7710:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11283 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
11284 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11285 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11286 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11287 GIR_RootToRootCopy, /*OpIdx*/2, // src
11288 GIR_RootConstrainSelectedInstOperands,
11289 // GIR_Coverage, 1351,
11290 GIR_EraseRootFromParent_Done,
11291 // Label 763: @28245
11292 GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(28300), // Rule ID 1352 //
11293 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11294 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
11295 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11296 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11297 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11298 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11299 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11300 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11301 // MIs[0] sa
11302 GIM_CheckIsImm, /*MI*/0, /*Op*/4,
11303 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
11304 // (intrinsic_wo_chain:{ *:[i32] } 7217:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
11305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
11306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11307 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11308 GIR_RootToRootCopy, /*OpIdx*/4, // sa
11309 GIR_RootToRootCopy, /*OpIdx*/2, // src
11310 GIR_RootConstrainSelectedInstOperands,
11311 // GIR_Coverage, 1352,
11312 GIR_EraseRootFromParent_Done,
11313 // Label 764: @28300
11314 GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(28362), // Rule ID 1327 //
11315 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
11316 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
11317 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
11318 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
11319 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
11320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11321 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11322 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11323 // MIs[0] bp
11324 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
11325 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
11326 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
11327 // MIs[1] Operand 1
11328 // No operand predicates
11329 GIM_CheckIsSafeToFold, /*NumInsns*/1,
11330 // (intrinsic_wo_chain:{ *:[i32] } 7242:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
11331 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
11332 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
11333 GIR_RootToRootCopy, /*OpIdx*/3, // rs
11334 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
11335 GIR_RootToRootCopy, /*OpIdx*/2, // src
11336 GIR_RootConstrainSelectedInstOperands,
11337 // GIR_Coverage, 1327,
11338 GIR_EraseRootFromParent_Done,
11339 // Label 765: @28362
11340 GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(28416), // Rule ID 552 //
11341 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
11343 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11344 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11345 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11346 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
11347 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11348 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11349 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11350 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11351 // (intrinsic_wo_chain:{ *:[v16i8] } 7251:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11352 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
11353 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11354 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11355 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11356 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11357 GIR_RootConstrainSelectedInstOperands,
11358 // GIR_Coverage, 552,
11359 GIR_EraseRootFromParent_Done,
11360 // Label 766: @28416
11361 GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(28470), // Rule ID 553 //
11362 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11363 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
11364 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11365 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11366 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11367 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11368 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11369 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11370 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11371 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11372 // (intrinsic_wo_chain:{ *:[v8i16] } 7253:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11373 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
11374 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11375 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11376 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11377 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11378 GIR_RootConstrainSelectedInstOperands,
11379 // GIR_Coverage, 553,
11380 GIR_EraseRootFromParent_Done,
11381 // Label 767: @28470
11382 GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(28524), // Rule ID 554 //
11383 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11384 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
11385 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11386 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11387 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11388 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11389 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11390 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11391 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11392 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11393 // (intrinsic_wo_chain:{ *:[v4i32] } 7254:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
11395 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11396 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11397 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11398 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11399 GIR_RootConstrainSelectedInstOperands,
11400 // GIR_Coverage, 554,
11401 GIR_EraseRootFromParent_Done,
11402 // Label 768: @28524
11403 GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(28578), // Rule ID 555 //
11404 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11405 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
11406 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11407 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11408 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11409 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
11410 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11411 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11412 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11413 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11414 // (intrinsic_wo_chain:{ *:[v2i64] } 7252:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
11416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11417 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11418 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11419 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11420 GIR_RootConstrainSelectedInstOperands,
11421 // GIR_Coverage, 555,
11422 GIR_EraseRootFromParent_Done,
11423 // Label 769: @28578
11424 GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(28632), // Rule ID 560 //
11425 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11426 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
11427 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11428 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11429 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11430 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
11431 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11432 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11433 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11434 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11435 // (intrinsic_wo_chain:{ *:[v16i8] } 7259:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11436 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
11437 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11438 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11439 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11440 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11441 GIR_RootConstrainSelectedInstOperands,
11442 // GIR_Coverage, 560,
11443 GIR_EraseRootFromParent_Done,
11444 // Label 770: @28632
11445 GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(28686), // Rule ID 561 //
11446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11447 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
11448 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11449 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11450 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11451 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11453 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11454 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11455 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11456 // (intrinsic_wo_chain:{ *:[v8i16] } 7261:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11457 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
11458 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11459 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11460 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11461 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11462 GIR_RootConstrainSelectedInstOperands,
11463 // GIR_Coverage, 561,
11464 GIR_EraseRootFromParent_Done,
11465 // Label 771: @28686
11466 GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(28740), // Rule ID 562 //
11467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11468 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
11469 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11470 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11471 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11472 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11473 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11474 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11475 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11476 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11477 // (intrinsic_wo_chain:{ *:[v4i32] } 7262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11478 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
11479 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11480 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11481 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11482 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11483 GIR_RootConstrainSelectedInstOperands,
11484 // GIR_Coverage, 562,
11485 GIR_EraseRootFromParent_Done,
11486 // Label 772: @28740
11487 GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(28794), // Rule ID 563 //
11488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11489 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
11490 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11491 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11492 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11493 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
11494 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11495 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11496 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11497 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11498 // (intrinsic_wo_chain:{ *:[v2i64] } 7260:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
11499 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
11500 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11501 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11502 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11503 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11504 GIR_RootConstrainSelectedInstOperands,
11505 // GIR_Coverage, 563,
11506 GIR_EraseRootFromParent_Done,
11507 // Label 773: @28794
11508 GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(28848), // Rule ID 658 //
11509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11510 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
11511 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11512 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11513 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11514 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
11515 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11516 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11517 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11518 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11519 // (intrinsic_wo_chain:{ *:[v8i16] } 7380:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11520 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
11521 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11522 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11523 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11524 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11525 GIR_RootConstrainSelectedInstOperands,
11526 // GIR_Coverage, 658,
11527 GIR_EraseRootFromParent_Done,
11528 // Label 774: @28848
11529 GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(28902), // Rule ID 659 //
11530 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11531 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
11532 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11533 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11534 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11535 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11537 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11538 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11539 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11540 // (intrinsic_wo_chain:{ *:[v4i32] } 7381:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
11542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11543 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11544 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11545 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11546 GIR_RootConstrainSelectedInstOperands,
11547 // GIR_Coverage, 659,
11548 GIR_EraseRootFromParent_Done,
11549 // Label 775: @28902
11550 GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(28956), // Rule ID 660 //
11551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11552 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
11553 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11554 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11555 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11556 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11557 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11558 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11559 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11560 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11561 // (intrinsic_wo_chain:{ *:[v2i64] } 7379:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11562 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
11563 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11564 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11565 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11566 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11567 GIR_RootConstrainSelectedInstOperands,
11568 // GIR_Coverage, 660,
11569 GIR_EraseRootFromParent_Done,
11570 // Label 776: @28956
11571 GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(29010), // Rule ID 661 //
11572 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11573 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
11574 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11575 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11576 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11577 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
11578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11579 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11580 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11581 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11582 // (intrinsic_wo_chain:{ *:[v8i16] } 7383:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
11584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11585 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11586 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11587 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11588 GIR_RootConstrainSelectedInstOperands,
11589 // GIR_Coverage, 661,
11590 GIR_EraseRootFromParent_Done,
11591 // Label 777: @29010
11592 GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(29064), // Rule ID 662 //
11593 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11594 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
11595 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11597 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11598 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11600 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11601 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11602 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11603 // (intrinsic_wo_chain:{ *:[v4i32] } 7384:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11604 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
11605 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11606 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11607 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11608 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11609 GIR_RootConstrainSelectedInstOperands,
11610 // GIR_Coverage, 662,
11611 GIR_EraseRootFromParent_Done,
11612 // Label 778: @29064
11613 GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(29118), // Rule ID 663 //
11614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
11616 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11617 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11618 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11619 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11621 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11622 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11623 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11624 // (intrinsic_wo_chain:{ *:[v2i64] } 7382:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11625 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
11626 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11627 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11628 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11629 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11630 GIR_RootConstrainSelectedInstOperands,
11631 // GIR_Coverage, 663,
11632 GIR_EraseRootFromParent_Done,
11633 // Label 779: @29118
11634 GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(29172), // Rule ID 664 //
11635 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11636 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
11637 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11638 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11639 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11640 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
11641 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11642 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11643 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11644 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11645 // (intrinsic_wo_chain:{ *:[v8i16] } 7400:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11646 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
11647 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11648 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11649 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11650 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11651 GIR_RootConstrainSelectedInstOperands,
11652 // GIR_Coverage, 664,
11653 GIR_EraseRootFromParent_Done,
11654 // Label 780: @29172
11655 GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(29226), // Rule ID 665 //
11656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11657 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
11658 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11659 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11660 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11661 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11663 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11664 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11665 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11666 // (intrinsic_wo_chain:{ *:[v4i32] } 7401:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11667 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
11668 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11669 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11670 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11671 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11672 GIR_RootConstrainSelectedInstOperands,
11673 // GIR_Coverage, 665,
11674 GIR_EraseRootFromParent_Done,
11675 // Label 781: @29226
11676 GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(29280), // Rule ID 666 //
11677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11678 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
11679 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11680 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11681 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11682 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11683 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11684 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11685 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11686 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11687 // (intrinsic_wo_chain:{ *:[v2i64] } 7399:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11688 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
11689 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11690 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11691 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11692 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11693 GIR_RootConstrainSelectedInstOperands,
11694 // GIR_Coverage, 666,
11695 GIR_EraseRootFromParent_Done,
11696 // Label 782: @29280
11697 GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(29334), // Rule ID 667 //
11698 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11699 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
11700 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11701 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11702 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11703 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
11704 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11705 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11706 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11707 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11708 // (intrinsic_wo_chain:{ *:[v8i16] } 7403:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
11709 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
11710 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11711 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11712 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11713 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11714 GIR_RootConstrainSelectedInstOperands,
11715 // GIR_Coverage, 667,
11716 GIR_EraseRootFromParent_Done,
11717 // Label 783: @29334
11718 GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(29388), // Rule ID 668 //
11719 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11720 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
11721 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11722 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11723 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11724 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11725 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11726 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11727 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11728 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11729 // (intrinsic_wo_chain:{ *:[v4i32] } 7404:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
11731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11732 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11733 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11734 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11735 GIR_RootConstrainSelectedInstOperands,
11736 // GIR_Coverage, 668,
11737 GIR_EraseRootFromParent_Done,
11738 // Label 784: @29388
11739 GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(29442), // Rule ID 669 //
11740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
11742 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11743 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11744 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11745 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11746 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11747 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11748 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11749 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11750 // (intrinsic_wo_chain:{ *:[v2i64] } 7402:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
11752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11753 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11754 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11755 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11756 GIR_RootConstrainSelectedInstOperands,
11757 // GIR_Coverage, 669,
11758 GIR_EraseRootFromParent_Done,
11759 // Label 785: @29442
11760 GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(29496), // Rule ID 836 //
11761 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11762 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
11763 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11764 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11765 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11766 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11767 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11768 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11769 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11770 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11771 // (intrinsic_wo_chain:{ *:[v8i16] } 7570:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11772 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
11773 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11774 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11775 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11776 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11777 GIR_RootConstrainSelectedInstOperands,
11778 // GIR_Coverage, 836,
11779 GIR_EraseRootFromParent_Done,
11780 // Label 786: @29496
11781 GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(29550), // Rule ID 837 //
11782 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11783 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
11784 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11785 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11786 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11787 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11788 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11789 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11790 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11791 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11792 // (intrinsic_wo_chain:{ *:[v4i32] } 7571:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11793 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
11794 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11795 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11796 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11797 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11798 GIR_RootConstrainSelectedInstOperands,
11799 // GIR_Coverage, 837,
11800 GIR_EraseRootFromParent_Done,
11801 // Label 787: @29550
11802 GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(29604), // Rule ID 838 //
11803 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11804 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
11805 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11806 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11807 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11808 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11809 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11810 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11811 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11812 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11813 // (intrinsic_wo_chain:{ *:[v8i16] } 7572:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11814 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
11815 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11816 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11817 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11818 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11819 GIR_RootConstrainSelectedInstOperands,
11820 // GIR_Coverage, 838,
11821 GIR_EraseRootFromParent_Done,
11822 // Label 788: @29604
11823 GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(29658), // Rule ID 839 //
11824 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11825 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
11826 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11827 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11828 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11829 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11830 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11831 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11832 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11833 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11834 // (intrinsic_wo_chain:{ *:[v4i32] } 7573:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
11836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11837 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11838 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11839 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11840 GIR_RootConstrainSelectedInstOperands,
11841 // GIR_Coverage, 839,
11842 GIR_EraseRootFromParent_Done,
11843 // Label 789: @29658
11844 GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(29712), // Rule ID 892 //
11845 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
11847 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11848 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11849 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11850 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11852 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11853 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11854 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11855 // (intrinsic_wo_chain:{ *:[v8i16] } 7634:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11856 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
11857 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11858 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11859 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11860 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11861 GIR_RootConstrainSelectedInstOperands,
11862 // GIR_Coverage, 892,
11863 GIR_EraseRootFromParent_Done,
11864 // Label 790: @29712
11865 GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(29766), // Rule ID 893 //
11866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11867 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
11868 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11869 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11870 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11871 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11873 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11874 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11875 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11876 // (intrinsic_wo_chain:{ *:[v4i32] } 7635:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
11878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11879 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11880 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11881 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11882 GIR_RootConstrainSelectedInstOperands,
11883 // GIR_Coverage, 893,
11884 GIR_EraseRootFromParent_Done,
11885 // Label 791: @29766
11886 GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(29820), // Rule ID 894 //
11887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11888 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
11889 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11890 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11891 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11892 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
11893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11894 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11895 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11896 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11897 // (intrinsic_wo_chain:{ *:[v8i16] } 7636:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
11898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
11899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11900 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11901 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11902 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11903 GIR_RootConstrainSelectedInstOperands,
11904 // GIR_Coverage, 894,
11905 GIR_EraseRootFromParent_Done,
11906 // Label 792: @29820
11907 GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(29874), // Rule ID 895 //
11908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11909 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
11910 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11911 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11912 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11913 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
11914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11915 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11916 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11917 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11918 // (intrinsic_wo_chain:{ *:[v4i32] } 7637:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
11919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
11920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11921 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11922 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11923 GIR_RootToRootCopy, /*OpIdx*/4, // wt
11924 GIR_RootConstrainSelectedInstOperands,
11925 // GIR_Coverage, 895,
11926 GIR_EraseRootFromParent_Done,
11927 // Label 793: @29874
11928 GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(29928), // Rule ID 949 //
11929 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11930 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
11931 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
11932 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
11933 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
11934 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
11935 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11936 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11937 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
11938 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11939 // (intrinsic_wo_chain:{ *:[v16i8] } 7738:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
11940 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
11941 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11942 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11943 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11944 GIR_RootToRootCopy, /*OpIdx*/4, // rt
11945 GIR_RootConstrainSelectedInstOperands,
11946 // GIR_Coverage, 949,
11947 GIR_EraseRootFromParent_Done,
11948 // Label 794: @29928
11949 GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(29982), // Rule ID 950 //
11950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11951 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
11952 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
11953 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
11954 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
11955 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
11956 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11957 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11958 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
11959 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11960 // (intrinsic_wo_chain:{ *:[v8i16] } 7740:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
11961 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
11962 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11963 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11964 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11965 GIR_RootToRootCopy, /*OpIdx*/4, // rt
11966 GIR_RootConstrainSelectedInstOperands,
11967 // GIR_Coverage, 950,
11968 GIR_EraseRootFromParent_Done,
11969 // Label 795: @29982
11970 GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(30036), // Rule ID 951 //
11971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11972 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
11973 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
11974 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
11975 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
11976 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
11977 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11978 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11979 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
11980 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
11981 // (intrinsic_wo_chain:{ *:[v4i32] } 7741:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
11982 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
11983 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
11984 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
11985 GIR_RootToRootCopy, /*OpIdx*/3, // ws
11986 GIR_RootToRootCopy, /*OpIdx*/4, // rt
11987 GIR_RootConstrainSelectedInstOperands,
11988 // GIR_Coverage, 951,
11989 GIR_EraseRootFromParent_Done,
11990 // Label 796: @30036
11991 GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(30090), // Rule ID 952 //
11992 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
11993 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
11994 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
11995 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
11996 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
11997 GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
11998 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
11999 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12000 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
12001 GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12002 // (intrinsic_wo_chain:{ *:[v2i64] } 7739:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
12003 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
12004 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
12005 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
12006 GIR_RootToRootCopy, /*OpIdx*/3, // ws
12007 GIR_RootToRootCopy, /*OpIdx*/4, // rt
12008 GIR_RootConstrainSelectedInstOperands,
12009 // GIR_Coverage, 952,
12010 GIR_EraseRootFromParent_Done,
12011 // Label 797: @30090
12012 GIM_Reject,
12013 // Label 751: @30091
12014 GIM_Reject,
12015 // Label 18: @30092
12016 GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(30123), // Rule ID 354 //
12017 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
12018 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
12019 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12020 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12021 // (intrinsic_w_chain:{ *:[i32] } 7285:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
12022 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
12023 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
12024 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12025 GIR_RootConstrainSelectedInstOperands,
12026 // GIR_Coverage, 354,
12027 GIR_EraseRootFromParent_Done,
12028 // Label 798: @30123
12029 GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(31060),
12030 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
12031 GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(30172), // Rule ID 441 //
12032 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12033 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
12034 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12036 // MIs[0] mask
12037 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12038 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12039 // (intrinsic_w_chain:{ *:[i32] } 7712:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
12041 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12042 GIR_RootToRootCopy, /*OpIdx*/2, // mask
12043 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12044 GIR_RootConstrainSelectedInstOperands,
12045 // GIR_Coverage, 441,
12046 GIR_EraseRootFromParent_Done,
12047 // Label 800: @30172
12048 GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(30208), // Rule ID 1287 //
12049 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12050 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
12051 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12052 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12053 // MIs[0] mask
12054 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12055 // (intrinsic_w_chain:{ *:[i32] } 7712:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
12056 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
12057 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12058 GIR_RootToRootCopy, /*OpIdx*/2, // mask
12059 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12060 GIR_RootConstrainSelectedInstOperands,
12061 // GIR_Coverage, 1287,
12062 GIR_EraseRootFromParent_Done,
12063 // Label 801: @30208
12064 GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(30249), // Rule ID 442 //
12065 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
12066 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
12067 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12068 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12069 // MIs[0] mask
12070 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12071 GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
12072 // (intrinsic_void 7841:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
12073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
12074 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12075 GIR_RootToRootCopy, /*OpIdx*/2, // mask
12076 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12077 GIR_RootConstrainSelectedInstOperands,
12078 // GIR_Coverage, 442,
12079 GIR_EraseRootFromParent_Done,
12080 // Label 802: @30249
12081 GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(30285), // Rule ID 1298 //
12082 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12083 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
12084 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
12085 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12086 // MIs[0] mask
12087 GIM_CheckIsImm, /*MI*/0, /*Op*/2,
12088 // (intrinsic_void 7841:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
12089 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
12090 GIR_RootToRootCopy, /*OpIdx*/1, // rt
12091 GIR_RootToRootCopy, /*OpIdx*/2, // mask
12092 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12093 GIR_RootConstrainSelectedInstOperands,
12094 // GIR_Coverage, 1298,
12095 GIR_EraseRootFromParent_Done,
12096 // Label 803: @30285
12097 GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(30328), // Rule ID 363 //
12098 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12099 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12100 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12101 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12102 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12103 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12104 // (intrinsic_w_chain:{ *:[v2i16] } 7173:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
12105 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
12106 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12107 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12108 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12109 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12110 GIR_RootConstrainSelectedInstOperands,
12111 // GIR_Coverage, 363,
12112 GIR_EraseRootFromParent_Done,
12113 // Label 804: @30328
12114 GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(30371), // Rule ID 364 //
12115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12116 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12117 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12118 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12119 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12120 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12121 // (intrinsic_w_chain:{ *:[i32] } 7175:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
12122 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
12123 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12124 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12125 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12126 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12127 GIR_RootConstrainSelectedInstOperands,
12128 // GIR_Coverage, 364,
12129 GIR_EraseRootFromParent_Done,
12130 // Label 805: @30371
12131 GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(30414), // Rule ID 450 //
12132 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12133 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12134 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12135 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12136 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12137 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12138 // (intrinsic_w_chain:{ *:[v4i8] } 7174:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
12139 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
12140 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12141 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12142 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12143 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12144 GIR_RootConstrainSelectedInstOperands,
12145 // GIR_Coverage, 450,
12146 GIR_EraseRootFromParent_Done,
12147 // Label 806: @30414
12148 GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(30457), // Rule ID 1230 //
12149 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12150 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
12151 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12152 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12153 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12154 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12155 // (intrinsic_w_chain:{ *:[v2i16] } 7173:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
12156 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
12157 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12158 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12159 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12160 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12161 GIR_RootConstrainSelectedInstOperands,
12162 // GIR_Coverage, 1230,
12163 GIR_EraseRootFromParent_Done,
12164 // Label 807: @30457
12165 GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(30500), // Rule ID 1231 //
12166 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12167 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
12168 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12169 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12171 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12172 // (intrinsic_w_chain:{ *:[i32] } 7175:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
12173 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
12174 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12175 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12176 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12177 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12178 GIR_RootConstrainSelectedInstOperands,
12179 // GIR_Coverage, 1231,
12180 GIR_EraseRootFromParent_Done,
12181 // Label 808: @30500
12182 GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(30543), // Rule ID 1311 //
12183 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
12184 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
12185 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12187 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12188 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12189 // (intrinsic_w_chain:{ *:[v4i8] } 7174:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
12190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
12191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12192 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12193 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12194 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12195 GIR_RootConstrainSelectedInstOperands,
12196 // GIR_Coverage, 1311,
12197 GIR_EraseRootFromParent_Done,
12198 // Label 809: @30543
12199 GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(30586), // Rule ID 417 //
12200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12201 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
12202 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12203 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12204 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12205 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12206 // (intrinsic_void 7351:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
12208 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12209 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12210 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12211 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12212 GIR_RootConstrainSelectedInstOperands,
12213 // GIR_Coverage, 417,
12214 GIR_EraseRootFromParent_Done,
12215 // Label 810: @30586
12216 GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(30629), // Rule ID 418 //
12217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12218 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
12219 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12220 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12221 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12222 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12223 // (intrinsic_void 7353:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12224 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
12225 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12226 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12227 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12228 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12229 GIR_RootConstrainSelectedInstOperands,
12230 // GIR_Coverage, 418,
12231 GIR_EraseRootFromParent_Done,
12232 // Label 811: @30629
12233 GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(30672), // Rule ID 419 //
12234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12235 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
12236 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12237 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12238 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12239 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12240 // (intrinsic_void 7352:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12241 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
12242 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12243 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12244 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12245 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12246 GIR_RootConstrainSelectedInstOperands,
12247 // GIR_Coverage, 419,
12248 GIR_EraseRootFromParent_Done,
12249 // Label 812: @30672
12250 GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(30715), // Rule ID 423 //
12251 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12252 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
12253 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12254 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12255 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12256 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12257 // (intrinsic_void 7342:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12258 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
12259 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12260 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12261 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12262 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12263 GIR_RootConstrainSelectedInstOperands,
12264 // GIR_Coverage, 423,
12265 GIR_EraseRootFromParent_Done,
12266 // Label 813: @30715
12267 GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(30758), // Rule ID 424 //
12268 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12269 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
12270 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12271 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12272 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12273 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12274 // (intrinsic_void 7344:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
12276 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12277 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12278 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12279 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12280 GIR_RootConstrainSelectedInstOperands,
12281 // GIR_Coverage, 424,
12282 GIR_EraseRootFromParent_Done,
12283 // Label 814: @30758
12284 GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(30801), // Rule ID 425 //
12285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
12287 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12288 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12289 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12290 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12291 // (intrinsic_void 7343:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
12293 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12294 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12295 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12296 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12297 GIR_RootConstrainSelectedInstOperands,
12298 // GIR_Coverage, 425,
12299 GIR_EraseRootFromParent_Done,
12300 // Label 815: @30801
12301 GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(30844), // Rule ID 1302 //
12302 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12303 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
12304 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12305 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12306 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12307 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12308 // (intrinsic_void 7342:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12309 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
12310 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12311 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12312 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12313 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12314 GIR_RootConstrainSelectedInstOperands,
12315 // GIR_Coverage, 1302,
12316 GIR_EraseRootFromParent_Done,
12317 // Label 816: @30844
12318 GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(30887), // Rule ID 1303 //
12319 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12320 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
12321 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12322 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12323 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12324 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12325 // (intrinsic_void 7344:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
12327 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12328 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12329 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12330 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12331 GIR_RootConstrainSelectedInstOperands,
12332 // GIR_Coverage, 1303,
12333 GIR_EraseRootFromParent_Done,
12334 // Label 817: @30887
12335 GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(30930), // Rule ID 1304 //
12336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12337 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
12338 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
12339 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12340 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12341 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12342 // (intrinsic_void 7343:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12343 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
12344 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12345 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12346 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12347 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12348 GIR_RootConstrainSelectedInstOperands,
12349 // GIR_Coverage, 1304,
12350 GIR_EraseRootFromParent_Done,
12351 // Label 818: @30930
12352 GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(30973), // Rule ID 1308 //
12353 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12354 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
12355 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12356 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12357 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12358 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12359 // (intrinsic_void 7351:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12360 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
12361 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12362 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12363 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12364 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12365 GIR_RootConstrainSelectedInstOperands,
12366 // GIR_Coverage, 1308,
12367 GIR_EraseRootFromParent_Done,
12368 // Label 819: @30973
12369 GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(31016), // Rule ID 1309 //
12370 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12371 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
12372 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12373 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12374 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12375 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12376 // (intrinsic_void 7353:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12377 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
12378 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12379 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12380 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12381 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12382 GIR_RootConstrainSelectedInstOperands,
12383 // GIR_Coverage, 1309,
12384 GIR_EraseRootFromParent_Done,
12385 // Label 820: @31016
12386 GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(31059), // Rule ID 1310 //
12387 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12388 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
12389 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
12390 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12391 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12392 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12393 // (intrinsic_void 7352:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12394 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
12395 GIR_RootToRootCopy, /*OpIdx*/1, // rs
12396 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12397 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
12398 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12399 GIR_RootConstrainSelectedInstOperands,
12400 // GIR_Coverage, 1310,
12401 GIR_EraseRootFromParent_Done,
12402 // Label 821: @31059
12403 GIM_Reject,
12404 // Label 799: @31060
12405 GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(34749),
12406 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
12407 GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(31132), // Rule ID 382 //
12408 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12409 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
12410 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12411 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12412 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12413 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12414 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12415 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
12416 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12417 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
12418 // MIs[1] Operand 1
12419 // No operand predicates
12420 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12421 // (intrinsic_w_chain:{ *:[v2i16] } 7729:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
12422 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
12423 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12424 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12425 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
12426 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12427 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
12428 GIR_RootConstrainSelectedInstOperands,
12429 // GIR_Coverage, 382,
12430 GIR_EraseRootFromParent_Done,
12431 // Label 823: @31132
12432 GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(31196), // Rule ID 387 //
12433 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12434 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
12435 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12436 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12437 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12438 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12439 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12440 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
12441 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12442 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
12443 // MIs[1] Operand 1
12444 // No operand predicates
12445 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12446 // (intrinsic_w_chain:{ *:[i32] } 7730:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
12447 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
12448 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12449 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12450 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
12451 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12452 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
12453 GIR_RootConstrainSelectedInstOperands,
12454 // GIR_Coverage, 387,
12455 GIR_EraseRootFromParent_Done,
12456 // Label 824: @31196
12457 GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(31260), // Rule ID 1239 //
12458 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12459 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
12460 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12461 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12462 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12463 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12464 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12465 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
12466 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12467 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
12468 // MIs[1] Operand 1
12469 // No operand predicates
12470 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12471 // (intrinsic_w_chain:{ *:[v2i16] } 7729:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
12472 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
12473 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12474 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12475 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
12476 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12477 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
12478 GIR_RootConstrainSelectedInstOperands,
12479 // GIR_Coverage, 1239,
12480 GIR_EraseRootFromParent_Done,
12481 // Label 825: @31260
12482 GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(31324), // Rule ID 1244 //
12483 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
12484 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
12485 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12486 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12487 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12488 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12489 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12490 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
12491 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12492 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
12493 // MIs[1] Operand 1
12494 // No operand predicates
12495 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12496 // (intrinsic_w_chain:{ *:[i32] } 7730:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
12497 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
12498 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12499 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12500 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
12501 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12502 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
12503 GIR_RootConstrainSelectedInstOperands,
12504 // GIR_Coverage, 1244,
12505 GIR_EraseRootFromParent_Done,
12506 // Label 826: @31324
12507 GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(31379), // Rule ID 1916 //
12508 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12509 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
12510 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12511 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12512 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12513 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12514 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
12515 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12516 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
12517 // MIs[1] Operand 1
12518 // No operand predicates
12519 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12520 // (intrinsic_w_chain:{ *:[v2i16] } 7727:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
12521 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
12522 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12523 GIR_RootToRootCopy, /*OpIdx*/2, // a
12524 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12525 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12526 GIR_RootConstrainSelectedInstOperands,
12527 // GIR_Coverage, 1916,
12528 GIR_EraseRootFromParent_Done,
12529 // Label 827: @31379
12530 GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(31434), // Rule ID 1922 //
12531 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
12533 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12534 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12535 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12536 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12537 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
12538 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
12539 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
12540 // MIs[1] Operand 1
12541 // No operand predicates
12542 GIM_CheckIsSafeToFold, /*NumInsns*/1,
12543 // (intrinsic_w_chain:{ *:[v4i8] } 7728:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
12544 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
12545 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12546 GIR_RootToRootCopy, /*OpIdx*/2, // a
12547 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
12548 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12549 GIR_RootConstrainSelectedInstOperands,
12550 // GIR_Coverage, 1922,
12551 GIR_EraseRootFromParent_Done,
12552 // Label 828: @31434
12553 GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(31486), // Rule ID 359 //
12554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12555 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
12556 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12557 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12558 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12559 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12560 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12561 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12562 // (intrinsic_w_chain:{ *:[i32] } 7182:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12563 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
12564 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12565 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12566 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12567 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12568 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12569 GIR_RootConstrainSelectedInstOperands,
12570 // GIR_Coverage, 359,
12571 GIR_EraseRootFromParent_Done,
12572 // Label 829: @31486
12573 GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(31538), // Rule ID 360 //
12574 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12575 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
12576 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12577 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12578 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12579 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12580 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12581 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12582 // (intrinsic_w_chain:{ *:[i32] } 7802:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12583 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
12584 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12585 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12586 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12587 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12588 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12589 GIR_RootConstrainSelectedInstOperands,
12590 // GIR_Coverage, 360,
12591 GIR_EraseRootFromParent_Done,
12592 // Label 830: @31538
12593 GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(31590), // Rule ID 367 //
12594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12595 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
12596 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12597 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12598 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12599 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12600 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12601 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12602 // (intrinsic_w_chain:{ *:[v2i16] } 7708:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
12603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
12604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12605 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12606 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12607 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12608 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12609 GIR_RootConstrainSelectedInstOperands,
12610 // GIR_Coverage, 367,
12611 GIR_EraseRootFromParent_Done,
12612 // Label 831: @31590
12613 GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(31642), // Rule ID 368 //
12614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12615 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
12616 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12617 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12618 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12619 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12620 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12621 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12622 // (intrinsic_w_chain:{ *:[v4i8] } 7709:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12623 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
12624 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12625 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12626 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12627 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12628 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12629 GIR_RootConstrainSelectedInstOperands,
12630 // GIR_Coverage, 368,
12631 GIR_EraseRootFromParent_Done,
12632 // Label 832: @31642
12633 GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(31694), // Rule ID 379 //
12634 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12635 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
12636 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12637 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12638 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12639 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12640 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12641 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12642 // (intrinsic_w_chain:{ *:[v4i8] } 7728:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
12643 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
12644 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12645 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12646 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
12647 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12648 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12649 GIR_RootConstrainSelectedInstOperands,
12650 // GIR_Coverage, 379,
12651 GIR_EraseRootFromParent_Done,
12652 // Label 833: @31694
12653 GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(31746), // Rule ID 381 //
12654 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12655 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
12656 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12657 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12658 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12659 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12660 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12661 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12662 // (intrinsic_w_chain:{ *:[v2i16] } 7727:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
12663 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
12664 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12665 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12666 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
12667 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12668 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12669 GIR_RootConstrainSelectedInstOperands,
12670 // GIR_Coverage, 381,
12671 GIR_EraseRootFromParent_Done,
12672 // Label 834: @31746
12673 GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(31798), // Rule ID 383 //
12674 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12675 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
12676 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12677 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12678 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12680 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12681 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12682 // (intrinsic_w_chain:{ *:[v2i16] } 7729:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
12683 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
12684 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12685 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12686 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
12687 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12688 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12689 GIR_RootConstrainSelectedInstOperands,
12690 // GIR_Coverage, 383,
12691 GIR_EraseRootFromParent_Done,
12692 // Label 835: @31798
12693 GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(31850), // Rule ID 388 //
12694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12695 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
12696 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12697 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12698 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12699 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12700 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12701 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12702 // (intrinsic_w_chain:{ *:[i32] } 7730:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
12703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
12704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12705 GIR_RootToRootCopy, /*OpIdx*/2, // rt
12706 GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
12707 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
12708 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12709 GIR_RootConstrainSelectedInstOperands,
12710 // GIR_Coverage, 388,
12711 GIR_EraseRootFromParent_Done,
12712 // Label 836: @31850
12713 GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(31902), // Rule ID 391 //
12714 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12715 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
12716 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12717 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12718 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12719 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12721 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12722 // (intrinsic_w_chain:{ *:[v2i16] } 7650:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12723 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
12724 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12725 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12726 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12727 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
12728 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12729 GIR_RootConstrainSelectedInstOperands,
12730 // GIR_Coverage, 391,
12731 GIR_EraseRootFromParent_Done,
12732 // Label 837: @31902
12733 GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(31954), // Rule ID 392 //
12734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12735 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
12736 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12737 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12738 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12739 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12740 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12741 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12742 // (intrinsic_w_chain:{ *:[v2i16] } 7651:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12743 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
12744 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12745 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12746 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12747 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
12748 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12749 GIR_RootConstrainSelectedInstOperands,
12750 // GIR_Coverage, 392,
12751 GIR_EraseRootFromParent_Done,
12752 // Label 838: @31954
12753 GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(32006), // Rule ID 393 //
12754 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12755 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
12756 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12757 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12758 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12759 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12760 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12761 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12762 // (intrinsic_w_chain:{ *:[i32] } 7648:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12763 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
12764 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12765 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12766 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12767 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
12768 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12769 GIR_RootConstrainSelectedInstOperands,
12770 // GIR_Coverage, 393,
12771 GIR_EraseRootFromParent_Done,
12772 // Label 839: @32006
12773 GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(32058), // Rule ID 394 //
12774 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12775 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
12776 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12777 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12778 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12779 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12780 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12781 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12782 // (intrinsic_w_chain:{ *:[i32] } 7649:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12783 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
12784 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12785 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12786 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12787 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
12788 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12789 GIR_RootConstrainSelectedInstOperands,
12790 // GIR_Coverage, 394,
12791 GIR_EraseRootFromParent_Done,
12792 // Label 840: @32058
12793 GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(32110), // Rule ID 395 //
12794 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12795 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
12796 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12797 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12798 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12799 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12800 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12801 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12802 // (intrinsic_w_chain:{ *:[v2i16] } 7652:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
12804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12805 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12806 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12807 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
12808 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12809 GIR_RootConstrainSelectedInstOperands,
12810 // GIR_Coverage, 395,
12811 GIR_EraseRootFromParent_Done,
12812 // Label 841: @32110
12813 GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(32159), // Rule ID 420 //
12814 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12815 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
12816 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12817 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12818 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12820 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12821 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12822 // (intrinsic_w_chain:{ *:[i32] } 7348:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
12824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12825 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12826 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12827 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12828 GIR_RootConstrainSelectedInstOperands,
12829 // GIR_Coverage, 420,
12830 GIR_EraseRootFromParent_Done,
12831 // Label 842: @32159
12832 GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(32208), // Rule ID 421 //
12833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12834 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
12835 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12836 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12837 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12838 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12839 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12840 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12841 // (intrinsic_w_chain:{ *:[i32] } 7350:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
12843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12844 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12845 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12846 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12847 GIR_RootConstrainSelectedInstOperands,
12848 // GIR_Coverage, 421,
12849 GIR_EraseRootFromParent_Done,
12850 // Label 843: @32208
12851 GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(32257), // Rule ID 422 //
12852 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12853 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
12854 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12855 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12856 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12857 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12858 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12859 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12860 // (intrinsic_w_chain:{ *:[i32] } 7349:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12861 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
12862 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12863 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12864 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12865 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12866 GIR_RootConstrainSelectedInstOperands,
12867 // GIR_Coverage, 422,
12868 GIR_EraseRootFromParent_Done,
12869 // Label 844: @32257
12870 GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(32306), // Rule ID 432 //
12871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12872 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
12873 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
12874 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
12875 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
12876 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12877 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12878 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12879 // (intrinsic_w_chain:{ *:[v4i8] } 7692:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
12880 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
12881 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12882 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12883 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12884 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12885 GIR_RootConstrainSelectedInstOperands,
12886 // GIR_Coverage, 432,
12887 GIR_EraseRootFromParent_Done,
12888 // Label 845: @32306
12889 GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(32355), // Rule ID 433 //
12890 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12891 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
12892 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12893 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12894 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12895 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12896 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12897 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12898 // (intrinsic_w_chain:{ *:[v2i16] } 7691:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12899 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
12900 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12901 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12902 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12903 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12904 GIR_RootConstrainSelectedInstOperands,
12905 // GIR_Coverage, 433,
12906 GIR_EraseRootFromParent_Done,
12907 // Label 846: @32355
12908 GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(32404), // Rule ID 437 //
12909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
12910 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
12911 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
12912 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
12913 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
12914 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12915 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12916 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
12917 // (intrinsic_w_chain:{ *:[i32] } 7550:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
12918 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
12919 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
12920 GIR_RootToRootCopy, /*OpIdx*/2, // src
12921 GIR_RootToRootCopy, /*OpIdx*/3, // rs
12922 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12923 GIR_RootConstrainSelectedInstOperands,
12924 // GIR_Coverage, 437,
12925 GIR_EraseRootFromParent_Done,
12926 // Label 847: @32404
12927 GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(32456), // Rule ID 443 //
12928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12929 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
12930 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12931 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12932 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12933 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12934 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12935 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12936 // (intrinsic_w_chain:{ *:[v2i16] } 7200:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
12938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12939 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12940 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12941 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12942 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12943 GIR_RootConstrainSelectedInstOperands,
12944 // GIR_Coverage, 443,
12945 GIR_EraseRootFromParent_Done,
12946 // Label 848: @32456
12947 GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(32508), // Rule ID 444 //
12948 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12949 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
12950 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12951 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12952 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12953 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12954 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12955 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12956 // (intrinsic_w_chain:{ *:[v2i16] } 7202:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12957 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
12958 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12959 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12960 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12961 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12962 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12963 GIR_RootConstrainSelectedInstOperands,
12964 // GIR_Coverage, 444,
12965 GIR_EraseRootFromParent_Done,
12966 // Label 849: @32508
12967 GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(32560), // Rule ID 445 //
12968 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12969 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
12970 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12972 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12974 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12975 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12976 // (intrinsic_w_chain:{ *:[v2i16] } 7823:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12977 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
12978 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12979 GIR_RootToRootCopy, /*OpIdx*/2, // rs
12980 GIR_RootToRootCopy, /*OpIdx*/3, // rt
12981 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
12982 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
12983 GIR_RootConstrainSelectedInstOperands,
12984 // GIR_Coverage, 445,
12985 GIR_EraseRootFromParent_Done,
12986 // Label 850: @32560
12987 GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(32612), // Rule ID 446 //
12988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
12989 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
12990 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
12991 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
12992 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
12993 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12994 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12995 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
12996 // (intrinsic_w_chain:{ *:[v2i16] } 7825:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
12997 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
12998 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
12999 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13000 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13001 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13002 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13003 GIR_RootConstrainSelectedInstOperands,
13004 // GIR_Coverage, 446,
13005 GIR_EraseRootFromParent_Done,
13006 // Label 851: @32612
13007 GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(32664), // Rule ID 447 //
13008 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13009 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
13010 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13011 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13012 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13013 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13014 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13015 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13016 // (intrinsic_w_chain:{ *:[i32] } 7345:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13017 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
13018 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13019 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13020 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13021 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13022 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13023 GIR_RootConstrainSelectedInstOperands,
13024 // GIR_Coverage, 447,
13025 GIR_EraseRootFromParent_Done,
13026 // Label 852: @32664
13027 GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(32716), // Rule ID 448 //
13028 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13029 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
13030 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13031 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13032 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13033 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13034 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13035 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13036 // (intrinsic_w_chain:{ *:[i32] } 7347:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13037 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
13038 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13039 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13040 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13041 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13042 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13043 GIR_RootConstrainSelectedInstOperands,
13044 // GIR_Coverage, 448,
13045 GIR_EraseRootFromParent_Done,
13046 // Label 853: @32716
13047 GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(32768), // Rule ID 449 //
13048 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13049 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
13050 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13051 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13052 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13053 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13054 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13055 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13056 // (intrinsic_w_chain:{ *:[i32] } 7346:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13057 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
13058 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13059 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13060 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13061 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13062 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13063 GIR_RootConstrainSelectedInstOperands,
13064 // GIR_Coverage, 449,
13065 GIR_EraseRootFromParent_Done,
13066 // Label 854: @32768
13067 GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(32820), // Rule ID 463 //
13068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13069 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
13070 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13071 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13072 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13073 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13074 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13075 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13076 // (intrinsic_w_chain:{ *:[v2i16] } 7647:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
13078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13079 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13080 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13081 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13082 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13083 GIR_RootConstrainSelectedInstOperands,
13084 // GIR_Coverage, 463,
13085 GIR_EraseRootFromParent_Done,
13086 // Label 855: @32820
13087 GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(32872), // Rule ID 464 //
13088 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13089 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
13090 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13091 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13092 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13093 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13094 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13095 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13096 // (intrinsic_w_chain:{ *:[i32] } 7655:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13097 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
13098 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13099 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13100 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13101 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13102 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13103 GIR_RootConstrainSelectedInstOperands,
13104 // GIR_Coverage, 464,
13105 GIR_EraseRootFromParent_Done,
13106 // Label 856: @32872
13107 GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(32924), // Rule ID 465 //
13108 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13109 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
13110 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13111 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13112 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13114 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13115 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13116 // (intrinsic_w_chain:{ *:[i32] } 7653:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13117 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
13118 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13119 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13120 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13121 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13122 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13123 GIR_RootConstrainSelectedInstOperands,
13124 // GIR_Coverage, 465,
13125 GIR_EraseRootFromParent_Done,
13126 // Label 857: @32924
13127 GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(32976), // Rule ID 466 //
13128 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13129 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
13130 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13131 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13132 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13133 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13134 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13135 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13136 // (intrinsic_w_chain:{ *:[v2i16] } 7654:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13137 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
13138 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13139 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13140 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13141 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13142 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13143 GIR_RootConstrainSelectedInstOperands,
13144 // GIR_Coverage, 466,
13145 GIR_EraseRootFromParent_Done,
13146 // Label 858: @32976
13147 GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(33025), // Rule ID 476 //
13148 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13149 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
13150 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13151 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13152 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13153 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13154 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13155 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13156 // (intrinsic_w_chain:{ *:[v4i8] } 7703:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13157 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
13158 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13159 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13160 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13161 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13162 GIR_RootConstrainSelectedInstOperands,
13163 // GIR_Coverage, 476,
13164 GIR_EraseRootFromParent_Done,
13165 // Label 859: @33025
13166 GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(33077), // Rule ID 1224 //
13167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13168 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
13169 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13170 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13171 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13172 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13173 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13174 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13175 // (intrinsic_w_chain:{ *:[i32] } 7182:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13176 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
13177 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13178 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13179 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13180 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13181 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13182 GIR_RootConstrainSelectedInstOperands,
13183 // GIR_Coverage, 1224,
13184 GIR_EraseRootFromParent_Done,
13185 // Label 860: @33077
13186 GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(33126), // Rule ID 1232 //
13187 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13188 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
13189 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13190 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13191 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13192 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13193 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13194 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13195 // (intrinsic_w_chain:{ *:[i32] } 7550:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
13196 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
13197 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
13198 GIR_RootToRootCopy, /*OpIdx*/2, // src
13199 GIR_RootToRootCopy, /*OpIdx*/3, // rs
13200 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13201 GIR_RootConstrainSelectedInstOperands,
13202 // GIR_Coverage, 1232,
13203 GIR_EraseRootFromParent_Done,
13204 // Label 861: @33126
13205 GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(33178), // Rule ID 1240 //
13206 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13207 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
13208 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13209 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13210 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13211 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13212 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13213 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13214 // (intrinsic_w_chain:{ *:[v2i16] } 7727:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13215 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
13216 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13217 GIR_RootToRootCopy, /*OpIdx*/2, // rt
13218 GIR_RootToRootCopy, /*OpIdx*/3, // rs
13219 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13220 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13221 GIR_RootConstrainSelectedInstOperands,
13222 // GIR_Coverage, 1240,
13223 GIR_EraseRootFromParent_Done,
13224 // Label 862: @33178
13225 GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(33230), // Rule ID 1241 //
13226 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13227 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
13228 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13229 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13230 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13231 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13232 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13233 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13234 // (intrinsic_w_chain:{ *:[v2i16] } 7729:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13235 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
13236 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13237 GIR_RootToRootCopy, /*OpIdx*/2, // rt
13238 GIR_RootToRootCopy, /*OpIdx*/3, // rs
13239 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13240 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13241 GIR_RootConstrainSelectedInstOperands,
13242 // GIR_Coverage, 1241,
13243 GIR_EraseRootFromParent_Done,
13244 // Label 863: @33230
13245 GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(33282), // Rule ID 1242 //
13246 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
13248 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13249 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13250 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13251 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13252 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13253 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13254 // (intrinsic_w_chain:{ *:[v4i8] } 7728:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13255 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
13256 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13257 GIR_RootToRootCopy, /*OpIdx*/2, // rt
13258 GIR_RootToRootCopy, /*OpIdx*/3, // rs
13259 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13260 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13261 GIR_RootConstrainSelectedInstOperands,
13262 // GIR_Coverage, 1242,
13263 GIR_EraseRootFromParent_Done,
13264 // Label 864: @33282
13265 GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(33334), // Rule ID 1243 //
13266 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13267 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
13268 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13269 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13270 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13271 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13272 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13273 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13274 // (intrinsic_w_chain:{ *:[i32] } 7730:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
13275 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
13276 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13277 GIR_RootToRootCopy, /*OpIdx*/2, // rt
13278 GIR_RootToRootCopy, /*OpIdx*/3, // rs
13279 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13280 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13281 GIR_RootConstrainSelectedInstOperands,
13282 // GIR_Coverage, 1243,
13283 GIR_EraseRootFromParent_Done,
13284 // Label 865: @33334
13285 GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(33386), // Rule ID 1262 //
13286 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13287 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
13288 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13289 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13290 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13291 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13292 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13293 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13294 // (intrinsic_w_chain:{ *:[i32] } 7802:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
13296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13297 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13298 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13299 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13300 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13301 GIR_RootConstrainSelectedInstOperands,
13302 // GIR_Coverage, 1262,
13303 GIR_EraseRootFromParent_Done,
13304 // Label 866: @33386
13305 GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(33438), // Rule ID 1268 //
13306 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13307 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
13308 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13309 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13310 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13311 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13312 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13313 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13314 // (intrinsic_w_chain:{ *:[i32] } 7648:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13315 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
13316 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13317 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13318 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13319 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13320 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13321 GIR_RootConstrainSelectedInstOperands,
13322 // GIR_Coverage, 1268,
13323 GIR_EraseRootFromParent_Done,
13324 // Label 867: @33438
13325 GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(33490), // Rule ID 1269 //
13326 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13327 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
13328 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13329 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13330 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13331 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13332 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13333 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13334 // (intrinsic_w_chain:{ *:[i32] } 7649:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13335 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
13336 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13337 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13338 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13339 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13340 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13341 GIR_RootConstrainSelectedInstOperands,
13342 // GIR_Coverage, 1269,
13343 GIR_EraseRootFromParent_Done,
13344 // Label 868: @33490
13345 GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(33542), // Rule ID 1270 //
13346 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13347 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
13348 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13349 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13350 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13351 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13352 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13353 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13354 // (intrinsic_w_chain:{ *:[v2i16] } 7650:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13355 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
13356 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13357 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13358 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13359 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13360 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13361 GIR_RootConstrainSelectedInstOperands,
13362 // GIR_Coverage, 1270,
13363 GIR_EraseRootFromParent_Done,
13364 // Label 869: @33542
13365 GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(33594), // Rule ID 1271 //
13366 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13367 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
13368 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13369 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13370 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13371 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13372 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13373 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13374 // (intrinsic_w_chain:{ *:[v2i16] } 7651:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13375 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
13376 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13377 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13378 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13379 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13380 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13381 GIR_RootConstrainSelectedInstOperands,
13382 // GIR_Coverage, 1271,
13383 GIR_EraseRootFromParent_Done,
13384 // Label 870: @33594
13385 GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(33646), // Rule ID 1272 //
13386 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13387 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
13388 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13389 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13390 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13391 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13392 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13393 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13394 // (intrinsic_w_chain:{ *:[v2i16] } 7652:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13395 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
13396 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13397 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13398 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13399 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13400 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13401 GIR_RootConstrainSelectedInstOperands,
13402 // GIR_Coverage, 1272,
13403 GIR_EraseRootFromParent_Done,
13404 // Label 871: @33646
13405 GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(33698), // Rule ID 1275 //
13406 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13407 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
13408 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13409 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13410 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13411 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13413 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13414 // (intrinsic_w_chain:{ *:[v4i8] } 7709:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
13416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13417 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13418 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13419 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13420 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13421 GIR_RootConstrainSelectedInstOperands,
13422 // GIR_Coverage, 1275,
13423 GIR_EraseRootFromParent_Done,
13424 // Label 872: @33698
13425 GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(33750), // Rule ID 1276 //
13426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13427 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
13428 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13429 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13430 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13431 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13432 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13433 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13434 // (intrinsic_w_chain:{ *:[v2i16] } 7708:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
13436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13437 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13438 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13439 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
13440 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13441 GIR_RootConstrainSelectedInstOperands,
13442 // GIR_Coverage, 1276,
13443 GIR_EraseRootFromParent_Done,
13444 // Label 873: @33750
13445 GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(33799), // Rule ID 1294 //
13446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13447 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
13448 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13449 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13450 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13451 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13452 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13453 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13454 // (intrinsic_w_chain:{ *:[v2i16] } 7691:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13455 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
13456 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13457 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13458 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13459 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13460 GIR_RootConstrainSelectedInstOperands,
13461 // GIR_Coverage, 1294,
13462 GIR_EraseRootFromParent_Done,
13463 // Label 874: @33799
13464 GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(33848), // Rule ID 1295 //
13465 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13466 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
13467 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13468 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13469 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13471 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13472 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13473 // (intrinsic_w_chain:{ *:[v4i8] } 7692:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13474 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
13475 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13476 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13477 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13478 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13479 GIR_RootConstrainSelectedInstOperands,
13480 // GIR_Coverage, 1295,
13481 GIR_EraseRootFromParent_Done,
13482 // Label 875: @33848
13483 GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(33897), // Rule ID 1305 //
13484 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13485 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
13486 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13487 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13488 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13489 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13490 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13491 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13492 // (intrinsic_w_chain:{ *:[i32] } 7348:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13493 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
13494 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13495 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13496 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13497 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13498 GIR_RootConstrainSelectedInstOperands,
13499 // GIR_Coverage, 1305,
13500 GIR_EraseRootFromParent_Done,
13501 // Label 876: @33897
13502 GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(33946), // Rule ID 1306 //
13503 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13504 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
13505 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13506 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13507 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13508 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13509 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13510 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13511 // (intrinsic_w_chain:{ *:[i32] } 7350:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13512 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
13513 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13514 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13515 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13516 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13517 GIR_RootConstrainSelectedInstOperands,
13518 // GIR_Coverage, 1306,
13519 GIR_EraseRootFromParent_Done,
13520 // Label 877: @33946
13521 GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(33995), // Rule ID 1307 //
13522 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
13523 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
13524 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13525 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13526 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13528 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13529 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13530 // (intrinsic_w_chain:{ *:[i32] } 7349:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13531 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
13532 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13533 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13534 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13535 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13536 GIR_RootConstrainSelectedInstOperands,
13537 // GIR_Coverage, 1307,
13538 GIR_EraseRootFromParent_Done,
13539 // Label 878: @33995
13540 GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(34047), // Rule ID 1316 //
13541 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13542 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
13543 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13544 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13545 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13546 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13547 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13548 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13549 // (intrinsic_w_chain:{ *:[v2i16] } 7200:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13550 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
13551 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13552 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13553 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13554 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13555 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13556 GIR_RootConstrainSelectedInstOperands,
13557 // GIR_Coverage, 1316,
13558 GIR_EraseRootFromParent_Done,
13559 // Label 879: @34047
13560 GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(34099), // Rule ID 1317 //
13561 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13562 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
13563 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13564 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13565 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13567 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13568 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13569 // (intrinsic_w_chain:{ *:[v2i16] } 7202:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13570 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
13571 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13572 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13573 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13574 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13575 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13576 GIR_RootConstrainSelectedInstOperands,
13577 // GIR_Coverage, 1317,
13578 GIR_EraseRootFromParent_Done,
13579 // Label 880: @34099
13580 GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(34151), // Rule ID 1328 //
13581 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13582 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
13583 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13584 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13585 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13586 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13587 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13588 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13589 // (intrinsic_w_chain:{ *:[i32] } 7345:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13590 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
13591 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13592 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13593 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13594 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13595 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13596 GIR_RootConstrainSelectedInstOperands,
13597 // GIR_Coverage, 1328,
13598 GIR_EraseRootFromParent_Done,
13599 // Label 881: @34151
13600 GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(34203), // Rule ID 1329 //
13601 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13602 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
13603 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13604 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13605 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13606 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13607 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13608 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13609 // (intrinsic_w_chain:{ *:[i32] } 7347:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
13611 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13612 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13613 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13614 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13615 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13616 GIR_RootConstrainSelectedInstOperands,
13617 // GIR_Coverage, 1329,
13618 GIR_EraseRootFromParent_Done,
13619 // Label 882: @34203
13620 GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(34255), // Rule ID 1330 //
13621 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
13623 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13624 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
13625 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
13626 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13627 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13628 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13629 // (intrinsic_w_chain:{ *:[i32] } 7346:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
13630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
13631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13632 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13633 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13634 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
13635 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13636 GIR_RootConstrainSelectedInstOperands,
13637 // GIR_Coverage, 1330,
13638 GIR_EraseRootFromParent_Done,
13639 // Label 883: @34255
13640 GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(34307), // Rule ID 1336 //
13641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
13643 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13644 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13645 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13646 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13647 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13648 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13649 // (intrinsic_w_chain:{ *:[v2i16] } 7823:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13650 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
13651 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13652 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13653 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13654 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13655 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13656 GIR_RootConstrainSelectedInstOperands,
13657 // GIR_Coverage, 1336,
13658 GIR_EraseRootFromParent_Done,
13659 // Label 884: @34307
13660 GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(34359), // Rule ID 1337 //
13661 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
13663 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13664 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13665 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13666 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13667 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13668 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13669 // (intrinsic_w_chain:{ *:[v2i16] } 7825:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13670 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
13671 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13672 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13673 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13674 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13675 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13676 GIR_RootConstrainSelectedInstOperands,
13677 // GIR_Coverage, 1337,
13678 GIR_EraseRootFromParent_Done,
13679 // Label 885: @34359
13680 GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(34411), // Rule ID 1344 //
13681 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
13683 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13684 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13685 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13686 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13687 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13688 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13689 // (intrinsic_w_chain:{ *:[v2i16] } 7647:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
13691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13692 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13693 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13694 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13695 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13696 GIR_RootConstrainSelectedInstOperands,
13697 // GIR_Coverage, 1344,
13698 GIR_EraseRootFromParent_Done,
13699 // Label 886: @34411
13700 GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(34463), // Rule ID 1345 //
13701 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13702 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
13703 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13704 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13705 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13706 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13707 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13708 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13709 // (intrinsic_w_chain:{ *:[i32] } 7653:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13710 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
13711 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13712 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13713 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13714 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13715 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13716 GIR_RootConstrainSelectedInstOperands,
13717 // GIR_Coverage, 1345,
13718 GIR_EraseRootFromParent_Done,
13719 // Label 887: @34463
13720 GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(34515), // Rule ID 1346 //
13721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
13723 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13724 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13725 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13726 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13727 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13728 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13729 // (intrinsic_w_chain:{ *:[v2i16] } 7654:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
13731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13732 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13733 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13734 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13735 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13736 GIR_RootConstrainSelectedInstOperands,
13737 // GIR_Coverage, 1346,
13738 GIR_EraseRootFromParent_Done,
13739 // Label 888: @34515
13740 GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(34567), // Rule ID 1347 //
13741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13742 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
13743 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13744 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13745 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13746 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13747 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13748 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13749 // (intrinsic_w_chain:{ *:[i32] } 7655:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
13750 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
13751 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13752 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13753 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13754 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13755 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13756 GIR_RootConstrainSelectedInstOperands,
13757 // GIR_Coverage, 1347,
13758 GIR_EraseRootFromParent_Done,
13759 // Label 889: @34567
13760 GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(34616), // Rule ID 1348 //
13761 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
13762 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
13763 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
13764 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13765 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13766 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13767 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13768 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13769 // (intrinsic_w_chain:{ *:[v4i8] } 7703:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
13770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
13771 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13772 GIR_RootToRootCopy, /*OpIdx*/2, // rs
13773 GIR_RootToRootCopy, /*OpIdx*/3, // rt
13774 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13775 GIR_RootConstrainSelectedInstOperands,
13776 // GIR_Coverage, 1348,
13777 GIR_EraseRootFromParent_Done,
13778 // Label 890: @34616
13779 GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(34660), // Rule ID 1903 //
13780 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
13781 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
13782 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
13783 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
13784 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
13785 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
13786 // (intrinsic_w_chain:{ *:[v2i16] } 7644:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
13787 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
13788 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13789 GIR_RootToRootCopy, /*OpIdx*/2, // a
13790 GIR_RootToRootCopy, /*OpIdx*/3, // b
13791 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
13792 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13793 GIR_RootConstrainSelectedInstOperands,
13794 // GIR_Coverage, 1903,
13795 GIR_EraseRootFromParent_Done,
13796 // Label 891: @34660
13797 GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(34704), // Rule ID 1909 //
13798 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13799 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
13800 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13801 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13802 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13803 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13804 // (intrinsic_w_chain:{ *:[i32] } 7199:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
13805 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
13806 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13807 GIR_RootToRootCopy, /*OpIdx*/2, // a
13808 GIR_RootToRootCopy, /*OpIdx*/3, // b
13809 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
13810 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13811 GIR_RootConstrainSelectedInstOperands,
13812 // GIR_Coverage, 1909,
13813 GIR_EraseRootFromParent_Done,
13814 // Label 892: @34704
13815 GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(34748), // Rule ID 1911 //
13816 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
13817 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
13818 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13819 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
13820 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
13821 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13822 // (intrinsic_w_chain:{ *:[i32] } 7214:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
13823 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
13824 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13825 GIR_RootToRootCopy, /*OpIdx*/2, // a
13826 GIR_RootToRootCopy, /*OpIdx*/3, // b
13827 GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
13828 GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
13829 GIR_RootConstrainSelectedInstOperands,
13830 // GIR_Coverage, 1911,
13831 GIR_EraseRootFromParent_Done,
13832 // Label 893: @34748
13833 GIM_Reject,
13834 // Label 822: @34749
13835 GIM_Reject,
13836 // Label 19: @34750
13837 GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(34815), // Rule ID 1578 //
13838 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
13839 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
13840 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
13842 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13843 // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
13844 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13847 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13848 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
13849 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13850 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13851 GIR_RootToRootCopy, /*OpIdx*/1, // src
13852 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
13853 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
13854 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
13855 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
13856 // GIR_Coverage, 1578,
13857 GIR_EraseRootFromParent_Done,
13858 // Label 894: @34815
13859 GIM_Reject,
13860 // Label 20: @34816
13861 GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(34879), // Rule ID 1573 //
13862 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
13863 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13864 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13866 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
13867 // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
13868 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
13869 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13870 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13871 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
13872 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
13873 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
13874 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
13875 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13876 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13877 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13878 GIR_RootConstrainSelectedInstOperands,
13879 // GIR_Coverage, 1573,
13880 GIR_EraseRootFromParent_Done,
13881 // Label 895: @34879
13882 GIM_Reject,
13883 // Label 21: @34880
13884 GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(34940),
13885 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
13886 GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(34914), // Rule ID 2134 //
13887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
13888 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
13889 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
13890 // MIs[0] Operand 1
13891 // No operand predicates
13892 // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
13893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
13894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
13895 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
13896 GIR_RootConstrainSelectedInstOperands,
13897 // GIR_Coverage, 2134,
13898 GIR_EraseRootFromParent_Done,
13899 // Label 897: @34914
13900 GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(34939), // Rule ID 1827 //
13901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
13902 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
13903 // MIs[0] Operand 1
13904 // No operand predicates
13905 // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
13906 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
13907 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
13908 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
13909 GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
13910 GIR_RootConstrainSelectedInstOperands,
13911 // GIR_Coverage, 1827,
13912 GIR_EraseRootFromParent_Done,
13913 // Label 898: @34939
13914 GIM_Reject,
13915 // Label 896: @34940
13916 GIM_Reject,
13917 // Label 22: @34941
13918 GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(36404),
13919 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
13920 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13921 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
13922 GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(35061), // Rule ID 1612 //
13923 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13924 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
13925 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13926 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13927 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13928 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13929 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13930 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13931 // MIs[2] Operand 1
13932 // No operand predicates
13933 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13934 // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
13935 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13936 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13937 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
13938 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13939 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
13940 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
13941 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13942 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13943 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13944 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
13946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13947 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13948 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
13949 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
13950 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
13951 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
13952 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
13953 // GIR_Coverage, 1612,
13954 GIR_EraseRootFromParent_Done,
13955 // Label 900: @35061
13956 GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(35166), // Rule ID 1610 //
13957 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13958 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
13959 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13960 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13961 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13962 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13963 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13964 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13965 // MIs[2] Operand 1
13966 // No operand predicates
13967 GIM_CheckIsSafeToFold, /*NumInsns*/2,
13968 // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
13969 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
13970 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
13971 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
13972 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13973 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
13974 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
13975 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
13976 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13977 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
13978 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
13979 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
13980 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
13981 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13982 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
13983 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
13984 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
13985 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
13986 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
13987 // GIR_Coverage, 1610,
13988 GIR_EraseRootFromParent_Done,
13989 // Label 901: @35166
13990 GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(35271), // Rule ID 1608 //
13991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
13992 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
13993 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
13994 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
13995 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
13996 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
13997 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
13998 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
13999 // MIs[2] Operand 1
14000 // No operand predicates
14001 GIM_CheckIsSafeToFold, /*NumInsns*/2,
14002 // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
14003 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14004 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14005 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
14006 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14007 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14008 GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
14009 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14010 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14011 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14012 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14014 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14015 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14016 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14017 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14018 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14019 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14020 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14021 // GIR_Coverage, 1608,
14022 GIR_EraseRootFromParent_Done,
14023 // Label 902: @35271
14024 GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(35370), // Rule ID 1603 //
14025 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14026 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
14027 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14028 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14029 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14030 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14031 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14032 // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14033 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14034 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14035 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
14036 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14037 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14038 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14039 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14040 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14041 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14042 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14045 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14046 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14047 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14048 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14049 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14050 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14051 // GIR_Coverage, 1603,
14052 GIR_EraseRootFromParent_Done,
14053 // Label 903: @35370
14054 GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(35469), // Rule ID 1613 //
14055 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14056 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
14057 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14058 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14059 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14060 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14061 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14062 // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14063 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14064 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14065 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
14066 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14067 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14068 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14069 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14070 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14071 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14072 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14073 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14074 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14075 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14076 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14077 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14078 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14079 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14080 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14081 // GIR_Coverage, 1613,
14082 GIR_EraseRootFromParent_Done,
14083 // Label 904: @35469
14084 GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(35568), // Rule ID 1611 //
14085 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14086 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
14087 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14088 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14089 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14090 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14091 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14092 // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14093 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14094 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14095 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
14096 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14097 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14098 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14099 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14100 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14101 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14102 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14103 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14104 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14105 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14106 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14107 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14108 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14109 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14110 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14111 // GIR_Coverage, 1611,
14112 GIR_EraseRootFromParent_Done,
14113 // Label 905: @35568
14114 GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(35676), // Rule ID 1605 //
14115 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6),
14116 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14117 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
14118 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14119 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14120 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14121 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14122 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14123 // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14124 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14125 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14126 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
14127 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14128 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14129 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14130 GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
14131 GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
14132 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14134 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14135 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14136 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14137 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14138 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14139 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14140 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14141 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14142 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14143 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14144 // GIR_Coverage, 1605,
14145 GIR_EraseRootFromParent_Done,
14146 // Label 906: @35676
14147 GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(35778), // Rule ID 1794 //
14148 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
14149 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14150 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
14151 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14152 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14153 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14154 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14155 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14156 // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14157 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14158 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14159 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
14160 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14161 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14162 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14163 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14164 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14165 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14166 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14167 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14168 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14169 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14170 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14171 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14172 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14173 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14174 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14175 // GIR_Coverage, 1794,
14176 GIR_EraseRootFromParent_Done,
14177 // Label 907: @35778
14178 GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(35880), // Rule ID 1795 //
14179 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
14180 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14181 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
14182 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14183 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14184 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14185 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14186 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14187 // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14188 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14189 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14190 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
14191 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14192 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14193 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14194 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14195 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14196 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14197 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14200 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14201 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14202 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14203 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14204 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14205 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14206 // GIR_Coverage, 1795,
14207 GIR_EraseRootFromParent_Done,
14208 // Label 908: @35880
14209 GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(35979), // Rule ID 1609 //
14210 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14211 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
14212 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14213 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14214 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14215 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14216 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14217 // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14218 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14219 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14220 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
14221 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14222 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14223 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14224 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14225 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14226 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14227 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14229 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14230 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14231 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14232 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14233 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14234 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14235 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14236 // GIR_Coverage, 1609,
14237 GIR_EraseRootFromParent_Done,
14238 // Label 909: @35979
14239 GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(36081), // Rule ID 1797 //
14240 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
14241 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14242 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
14243 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14244 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14245 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14246 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14247 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14248 // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14249 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14250 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14251 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
14252 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14253 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14254 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14255 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14256 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14257 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14258 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14259 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14260 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14261 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14262 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14263 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14264 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14265 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14266 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14267 // GIR_Coverage, 1797,
14268 GIR_EraseRootFromParent_Done,
14269 // Label 910: @36081
14270 GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(36180), // Rule ID 1604 //
14271 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14272 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
14273 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14274 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14275 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14276 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14277 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14278 // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14279 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14280 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14281 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
14282 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14283 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14284 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14285 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14286 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14287 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14288 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14291 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14292 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14293 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14294 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14295 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14296 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14297 // GIR_Coverage, 1604,
14298 GIR_EraseRootFromParent_Done,
14299 // Label 911: @36180
14300 GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(36282), // Rule ID 1796 //
14301 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
14302 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14303 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
14304 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14305 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14306 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14307 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14308 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14309 // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14310 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14311 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14312 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
14313 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14314 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14315 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14316 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14317 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14318 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14319 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14320 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14321 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14322 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14323 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14324 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14325 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14326 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14327 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14328 // GIR_Coverage, 1796,
14329 GIR_EraseRootFromParent_Done,
14330 // Label 912: @36282
14331 GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(36384), // Rule ID 1798 //
14332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
14333 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14334 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
14335 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
14336 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
14337 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14338 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14339 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14340 // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
14341 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14342 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
14343 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
14344 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14345 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
14346 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
14347 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
14348 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14349 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14350 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
14352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
14353 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14354 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
14355 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
14356 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
14357 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14358 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
14359 // GIR_Coverage, 1798,
14360 GIR_EraseRootFromParent_Done,
14361 // Label 913: @36384
14362 GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(36403), // Rule ID 1580 //
14363 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
14364 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14365 // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
14366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
14367 GIR_RootConstrainSelectedInstOperands,
14368 // GIR_Coverage, 1580,
14369 GIR_Done,
14370 // Label 914: @36403
14371 GIM_Reject,
14372 // Label 899: @36404
14373 GIM_Reject,
14374 // Label 23: @36405
14375 GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(36605),
14376 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
14377 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14378 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14379 GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(36476), // Rule ID 280 //
14380 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
14381 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14382 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
14383 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14384 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
14385 // MIs[1] Operand 1
14386 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
14387 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14388 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14389 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14390 // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
14391 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
14392 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
14394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
14395 GIR_RootConstrainSelectedInstOperands,
14396 // GIR_Coverage, 280,
14397 GIR_EraseRootFromParent_Done,
14398 // Label 916: @36476
14399 GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(36532), // Rule ID 282 //
14400 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
14401 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
14402 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
14403 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
14404 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
14405 // MIs[1] Operand 1
14406 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
14407 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14408 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14409 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14410 // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
14411 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
14412 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
14414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
14415 GIR_RootConstrainSelectedInstOperands,
14416 // GIR_Coverage, 282,
14417 GIR_EraseRootFromParent_Done,
14418 // Label 917: @36532
14419 GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(36604),
14420 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14421 GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(36580), // Rule ID 1579 //
14422 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
14423 // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
14424 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
14425 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
14426 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14427 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
14428 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14429 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
14430 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14431 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14432 GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
14433 GIR_RootConstrainSelectedInstOperands,
14434 // GIR_Coverage, 1579,
14435 GIR_EraseRootFromParent_Done,
14436 // Label 919: @36580
14437 GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(36603), // Rule ID 1581 //
14438 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips),
14439 // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
14440 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
14441 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
14442 GIR_RootToRootCopy, /*OpIdx*/1, // src
14443 GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14444 GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
14445 GIR_RootConstrainSelectedInstOperands,
14446 // GIR_Coverage, 1581,
14447 GIR_EraseRootFromParent_Done,
14448 // Label 920: @36603
14449 GIM_Reject,
14450 // Label 918: @36604
14451 GIM_Reject,
14452 // Label 915: @36605
14453 GIM_Reject,
14454 // Label 24: @36606
14455 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 927*/ GIMT_Encode4(38402),
14456 /*GILLT_s32*//*Label 921*/ GIMT_Encode4(36649),
14457 /*GILLT_s64*//*Label 922*/ GIMT_Encode4(36911), GIMT_Encode4(0),
14458 /*GILLT_v2s64*//*Label 923*/ GIMT_Encode4(37052), GIMT_Encode4(0),
14459 /*GILLT_v4s32*//*Label 924*/ GIMT_Encode4(37086),
14460 /*GILLT_v8s16*//*Label 925*/ GIMT_Encode4(37354),
14461 /*GILLT_v16s8*//*Label 926*/ GIMT_Encode4(37750),
14462 // Label 921: @36649
14463 GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(36910),
14464 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14465 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14466 GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(36702), // Rule ID 55 //
14467 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
14468 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14469 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14470 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14471 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14472 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14473 // MIs[1] Operand 1
14474 // No operand predicates
14475 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14476 // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
14477 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
14478 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14479 GIR_RootToRootCopy, /*OpIdx*/1, // rt
14480 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14481 GIR_RootConstrainSelectedInstOperands,
14482 // GIR_Coverage, 55,
14483 GIR_EraseRootFromParent_Done,
14484 // Label 929: @36702
14485 GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(36744), // Rule ID 1809 //
14486 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
14487 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14488 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14489 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14490 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14491 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14492 // MIs[1] Operand 1
14493 // No operand predicates
14494 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14495 // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14496 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
14497 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
14498 GIR_RootToRootCopy, /*OpIdx*/1, // in
14499 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14500 GIR_RootConstrainSelectedInstOperands,
14501 // GIR_Coverage, 1809,
14502 GIR_EraseRootFromParent_Done,
14503 // Label 930: @36744
14504 GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(36786), // Rule ID 2146 //
14505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
14506 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
14507 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
14508 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14509 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14510 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
14511 // MIs[1] Operand 1
14512 // No operand predicates
14513 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14514 // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
14515 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
14516 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14517 GIR_RootToRootCopy, /*OpIdx*/1, // src
14518 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14519 GIR_RootConstrainSelectedInstOperands,
14520 // GIR_Coverage, 2146,
14521 GIR_EraseRootFromParent_Done,
14522 // Label 931: @36786
14523 GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(36828), // Rule ID 2147 //
14524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
14525 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14526 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14527 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14528 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14529 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
14530 // MIs[1] Operand 1
14531 // No operand predicates
14532 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14533 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
14534 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
14535 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14536 GIR_RootToRootCopy, /*OpIdx*/1, // src
14537 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
14538 GIR_RootConstrainSelectedInstOperands,
14539 // GIR_Coverage, 2147,
14540 GIR_EraseRootFromParent_Done,
14541 // Label 932: @36828
14542 GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(36855), // Rule ID 61 //
14543 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
14544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14545 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14546 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14547 // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14548 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
14549 GIR_RootConstrainSelectedInstOperands,
14550 // GIR_Coverage, 61,
14551 GIR_Done,
14552 // Label 933: @36855
14553 GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(36882), // Rule ID 1812 //
14554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
14555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14556 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14557 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
14558 // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
14559 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
14560 GIR_RootConstrainSelectedInstOperands,
14561 // GIR_Coverage, 1812,
14562 GIR_Done,
14563 // Label 934: @36882
14564 GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(36909), // Rule ID 2148 //
14565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
14566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14568 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14569 // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
14570 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
14571 GIR_RootConstrainSelectedInstOperands,
14572 // GIR_Coverage, 2148,
14573 GIR_Done,
14574 // Label 935: @36909
14575 GIM_Reject,
14576 // Label 928: @36910
14577 GIM_Reject,
14578 // Label 922: @36911
14579 GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(37051),
14580 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14581 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14583 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14584 GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(36964), // Rule ID 210 //
14585 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
14586 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14587 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14588 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
14589 // MIs[1] Operand 1
14590 // No operand predicates
14591 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14592 // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
14593 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
14594 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14595 GIR_RootToRootCopy, /*OpIdx*/1, // rt
14596 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
14597 GIR_RootConstrainSelectedInstOperands,
14598 // GIR_Coverage, 210,
14599 GIR_EraseRootFromParent_Done,
14600 // Label 937: @36964
14601 GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(37031), // Rule ID 1574 //
14602 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
14603 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14604 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
14605 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
14606 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
14607 GIM_CheckIsSafeToFold, /*NumInsns*/1,
14608 // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
14609 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14610 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14611 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
14612 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
14613 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
14614 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
14615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
14616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
14617 GIR_RootToRootCopy, /*OpIdx*/1, // rt
14618 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14619 GIR_RootConstrainSelectedInstOperands,
14620 // GIR_Coverage, 1574,
14621 GIR_EraseRootFromParent_Done,
14622 // Label 938: @37031
14623 GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(37050), // Rule ID 216 //
14624 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
14625 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
14626 // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
14627 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
14628 GIR_RootConstrainSelectedInstOperands,
14629 // GIR_Coverage, 216,
14630 GIR_Done,
14631 // Label 939: @37050
14632 GIM_Reject,
14633 // Label 936: @37051
14634 GIM_Reject,
14635 // Label 923: @37052
14636 GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(37085), // Rule ID 960 //
14637 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
14638 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14639 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
14640 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14641 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14642 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
14643 // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
14644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
14645 GIR_RootConstrainSelectedInstOperands,
14646 // GIR_Coverage, 960,
14647 GIR_Done,
14648 // Label 940: @37085
14649 GIM_Reject,
14650 // Label 924: @37086
14651 GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(37353),
14652 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14653 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14654 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14655 GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(37215), // Rule ID 2438 //
14656 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
14657 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14658 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14659 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14660 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14661 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14662 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
14663 GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14664 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14665 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14666 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14667 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14668 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14669 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14670 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14671 // MIs[3] Operand 1
14672 // No operand predicates
14673 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14674 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14675 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14676 // MIs[4] Operand 1
14677 // No operand predicates
14678 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14679 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14680 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14681 // MIs[5] Operand 1
14682 // No operand predicates
14683 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14684 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14685 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14686 // MIs[6] Operand 1
14687 // No operand predicates
14688 GIM_CheckIsSafeToFold, /*NumInsns*/6,
14689 // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14690 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
14691 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
14692 GIR_RootToRootCopy, /*OpIdx*/1, // ws
14693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14694 GIR_RootConstrainSelectedInstOperands,
14695 // GIR_Coverage, 2438,
14696 GIR_EraseRootFromParent_Done,
14697 // Label 942: @37215
14698 GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(37329), // Rule ID 2049 //
14699 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
14700 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14701 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14702 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
14703 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
14704 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14705 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
14706 GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
14707 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14708 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14709 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14710 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14711 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14712 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14713 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14714 // MIs[3] Operand 1
14715 // No operand predicates
14716 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14717 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14718 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14719 // MIs[4] Operand 1
14720 // No operand predicates
14721 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14722 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14723 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14724 // MIs[5] Operand 1
14725 // No operand predicates
14726 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14727 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14728 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
14729 // MIs[6] Operand 1
14730 // No operand predicates
14731 GIM_CheckIsSafeToFold, /*NumInsns*/6,
14732 // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
14733 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
14734 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
14735 GIR_RootToRootCopy, /*OpIdx*/1, // ws
14736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14737 GIR_RootConstrainSelectedInstOperands,
14738 // GIR_Coverage, 2049,
14739 GIR_EraseRootFromParent_Done,
14740 // Label 943: @37329
14741 GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(37352), // Rule ID 959 //
14742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
14743 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14744 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
14745 // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
14746 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
14747 GIR_RootConstrainSelectedInstOperands,
14748 // GIR_Coverage, 959,
14749 GIR_Done,
14750 // Label 944: @37352
14751 GIM_Reject,
14752 // Label 941: @37353
14753 GIM_Reject,
14754 // Label 925: @37354
14755 GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(37749),
14756 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14757 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14758 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
14759 GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(37547), // Rule ID 2437 //
14760 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
14761 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14762 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14763 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14764 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14765 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14766 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
14767 GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14768 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14769 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14770 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14771 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14772 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14773 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14774 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14775 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14776 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14777 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14778 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14779 // MIs[3] Operand 1
14780 // No operand predicates
14781 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14782 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14783 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14784 // MIs[4] Operand 1
14785 // No operand predicates
14786 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14787 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14788 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14789 // MIs[5] Operand 1
14790 // No operand predicates
14791 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14792 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14793 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14794 // MIs[6] Operand 1
14795 // No operand predicates
14796 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14797 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14798 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14799 // MIs[7] Operand 1
14800 // No operand predicates
14801 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14802 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14803 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14804 // MIs[8] Operand 1
14805 // No operand predicates
14806 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14807 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14808 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14809 // MIs[9] Operand 1
14810 // No operand predicates
14811 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14812 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14813 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14814 // MIs[10] Operand 1
14815 // No operand predicates
14816 GIM_CheckIsSafeToFold, /*NumInsns*/10,
14817 // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
14818 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
14819 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
14820 GIR_RootToRootCopy, /*OpIdx*/1, // ws
14821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
14822 GIR_RootConstrainSelectedInstOperands,
14823 // GIR_Coverage, 2437,
14824 GIR_EraseRootFromParent_Done,
14825 // Label 946: @37547
14826 GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(37725), // Rule ID 2048 //
14827 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
14828 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14829 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14830 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
14831 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
14832 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
14833 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
14834 GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
14835 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14836 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14837 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14838 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14839 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14840 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14841 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14842 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14843 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14844 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14845 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14846 // MIs[3] Operand 1
14847 // No operand predicates
14848 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14849 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14850 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14851 // MIs[4] Operand 1
14852 // No operand predicates
14853 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14854 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14855 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14856 // MIs[5] Operand 1
14857 // No operand predicates
14858 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14859 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14860 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14861 // MIs[6] Operand 1
14862 // No operand predicates
14863 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14864 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14865 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14866 // MIs[7] Operand 1
14867 // No operand predicates
14868 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14869 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14870 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14871 // MIs[8] Operand 1
14872 // No operand predicates
14873 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14874 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14875 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14876 // MIs[9] Operand 1
14877 // No operand predicates
14878 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14879 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14880 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
14881 // MIs[10] Operand 1
14882 // No operand predicates
14883 GIM_CheckIsSafeToFold, /*NumInsns*/10,
14884 // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
14885 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
14886 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
14887 GIR_RootToRootCopy, /*OpIdx*/1, // ws
14888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
14889 GIR_RootConstrainSelectedInstOperands,
14890 // GIR_Coverage, 2048,
14891 GIR_EraseRootFromParent_Done,
14892 // Label 947: @37725
14893 GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(37748), // Rule ID 958 //
14894 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
14895 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
14896 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
14897 // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
14898 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
14899 GIR_RootConstrainSelectedInstOperands,
14900 // GIR_Coverage, 958,
14901 GIR_Done,
14902 // Label 948: @37748
14903 GIM_Reject,
14904 // Label 945: @37749
14905 GIM_Reject,
14906 // Label 926: @37750
14907 GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(38401),
14908 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14909 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14910 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
14911 GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(38071), // Rule ID 2436 //
14912 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
14913 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
14914 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
14915 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
14916 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
14917 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
14918 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
14919 GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
14920 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
14921 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
14922 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
14923 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
14924 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
14925 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
14926 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
14927 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
14928 GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
14929 GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
14930 GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
14931 GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
14932 GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
14933 GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
14934 GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
14935 GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
14936 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
14937 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14938 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14939 // MIs[3] Operand 1
14940 // No operand predicates
14941 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
14942 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14943 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14944 // MIs[4] Operand 1
14945 // No operand predicates
14946 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
14947 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14948 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14949 // MIs[5] Operand 1
14950 // No operand predicates
14951 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
14952 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14953 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14954 // MIs[6] Operand 1
14955 // No operand predicates
14956 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
14957 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14958 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14959 // MIs[7] Operand 1
14960 // No operand predicates
14961 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
14962 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14963 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14964 // MIs[8] Operand 1
14965 // No operand predicates
14966 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
14967 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14968 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14969 // MIs[9] Operand 1
14970 // No operand predicates
14971 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
14972 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14973 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14974 // MIs[10] Operand 1
14975 // No operand predicates
14976 GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
14977 GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14978 GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14979 // MIs[11] Operand 1
14980 // No operand predicates
14981 GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
14982 GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14983 GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14984 // MIs[12] Operand 1
14985 // No operand predicates
14986 GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
14987 GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14988 GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14989 // MIs[13] Operand 1
14990 // No operand predicates
14991 GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
14992 GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14993 GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14994 // MIs[14] Operand 1
14995 // No operand predicates
14996 GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
14997 GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
14998 GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
14999 // MIs[15] Operand 1
15000 // No operand predicates
15001 GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15002 GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15003 GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15004 // MIs[16] Operand 1
15005 // No operand predicates
15006 GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15007 GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15008 GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15009 // MIs[17] Operand 1
15010 // No operand predicates
15011 GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15012 GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15013 GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15014 // MIs[18] Operand 1
15015 // No operand predicates
15016 GIM_CheckIsSafeToFold, /*NumInsns*/18,
15017 // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15018 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15019 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15020 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15021 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15022 GIR_RootConstrainSelectedInstOperands,
15023 // GIR_Coverage, 2436,
15024 GIR_EraseRootFromParent_Done,
15025 // Label 950: @38071
15026 GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(38377), // Rule ID 2047 //
15027 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15028 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15029 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15030 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15031 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15032 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15033 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15034 GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15035 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15036 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15037 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15038 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15039 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15040 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15041 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15042 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15043 GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15044 GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15045 GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15046 GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15047 GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15048 GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15049 GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15050 GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15051 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15052 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15053 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15054 // MIs[3] Operand 1
15055 // No operand predicates
15056 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15057 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15058 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15059 // MIs[4] Operand 1
15060 // No operand predicates
15061 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15062 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15063 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15064 // MIs[5] Operand 1
15065 // No operand predicates
15066 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15067 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15068 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15069 // MIs[6] Operand 1
15070 // No operand predicates
15071 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15072 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15073 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15074 // MIs[7] Operand 1
15075 // No operand predicates
15076 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15077 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15078 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15079 // MIs[8] Operand 1
15080 // No operand predicates
15081 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15082 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15083 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15084 // MIs[9] Operand 1
15085 // No operand predicates
15086 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15087 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15088 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15089 // MIs[10] Operand 1
15090 // No operand predicates
15091 GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15092 GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15093 GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15094 // MIs[11] Operand 1
15095 // No operand predicates
15096 GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15097 GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15098 GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15099 // MIs[12] Operand 1
15100 // No operand predicates
15101 GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15102 GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15103 GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15104 // MIs[13] Operand 1
15105 // No operand predicates
15106 GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15107 GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15108 GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15109 // MIs[14] Operand 1
15110 // No operand predicates
15111 GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15112 GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15113 GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15114 // MIs[15] Operand 1
15115 // No operand predicates
15116 GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15117 GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15118 GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15119 // MIs[16] Operand 1
15120 // No operand predicates
15121 GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15122 GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15123 GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15124 // MIs[17] Operand 1
15125 // No operand predicates
15126 GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15127 GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15128 GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15129 // MIs[18] Operand 1
15130 // No operand predicates
15131 GIM_CheckIsSafeToFold, /*NumInsns*/18,
15132 // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15133 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15134 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15135 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15137 GIR_RootConstrainSelectedInstOperands,
15138 // GIR_Coverage, 2047,
15139 GIR_EraseRootFromParent_Done,
15140 // Label 951: @38377
15141 GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(38400), // Rule ID 957 //
15142 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15143 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15144 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15145 // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
15146 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
15147 GIR_RootConstrainSelectedInstOperands,
15148 // GIR_Coverage, 957,
15149 GIR_Done,
15150 // Label 952: @38400
15151 GIM_Reject,
15152 // Label 949: @38401
15153 GIM_Reject,
15154 // Label 927: @38402
15155 GIM_Reject,
15156 // Label 25: @38403
15157 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 959*/ GIMT_Encode4(40199),
15158 /*GILLT_s32*//*Label 953*/ GIMT_Encode4(38446),
15159 /*GILLT_s64*//*Label 954*/ GIMT_Encode4(38708), GIMT_Encode4(0),
15160 /*GILLT_v2s64*//*Label 955*/ GIMT_Encode4(38849), GIMT_Encode4(0),
15161 /*GILLT_v4s32*//*Label 956*/ GIMT_Encode4(38883),
15162 /*GILLT_v8s16*//*Label 957*/ GIMT_Encode4(39151),
15163 /*GILLT_v16s8*//*Label 958*/ GIMT_Encode4(39547),
15164 // Label 953: @38446
15165 GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(38707),
15166 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15167 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15168 GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(38499), // Rule ID 57 //
15169 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
15170 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15171 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15172 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15173 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15174 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15175 // MIs[1] Operand 1
15176 // No operand predicates
15177 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15178 // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15179 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
15180 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15181 GIR_RootToRootCopy, /*OpIdx*/1, // rt
15182 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15183 GIR_RootConstrainSelectedInstOperands,
15184 // GIR_Coverage, 57,
15185 GIR_EraseRootFromParent_Done,
15186 // Label 961: @38499
15187 GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(38541), // Rule ID 1810 //
15188 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15189 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15190 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15191 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15192 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15193 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15194 // MIs[1] Operand 1
15195 // No operand predicates
15196 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15197 // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15198 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
15199 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15200 GIR_RootToRootCopy, /*OpIdx*/1, // in
15201 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15202 GIR_RootConstrainSelectedInstOperands,
15203 // GIR_Coverage, 1810,
15204 GIR_EraseRootFromParent_Done,
15205 // Label 962: @38541
15206 GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(38583), // Rule ID 2149 //
15207 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15208 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15209 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
15210 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15211 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15212 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
15213 // MIs[1] Operand 1
15214 // No operand predicates
15215 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15216 // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
15217 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
15218 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15219 GIR_RootToRootCopy, /*OpIdx*/1, // src
15220 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15221 GIR_RootConstrainSelectedInstOperands,
15222 // GIR_Coverage, 2149,
15223 GIR_EraseRootFromParent_Done,
15224 // Label 963: @38583
15225 GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(38625), // Rule ID 2150 //
15226 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15227 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15228 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15230 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15231 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15232 // MIs[1] Operand 1
15233 // No operand predicates
15234 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15235 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15236 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
15237 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15238 GIR_RootToRootCopy, /*OpIdx*/1, // src
15239 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15240 GIR_RootConstrainSelectedInstOperands,
15241 // GIR_Coverage, 2150,
15242 GIR_EraseRootFromParent_Done,
15243 // Label 964: @38625
15244 GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(38652), // Rule ID 63 //
15245 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
15246 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15247 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15248 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15249 // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15250 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
15251 GIR_RootConstrainSelectedInstOperands,
15252 // GIR_Coverage, 63,
15253 GIR_Done,
15254 // Label 965: @38652
15255 GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(38679), // Rule ID 1814 //
15256 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15257 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15258 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15259 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15260 // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
15261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
15262 GIR_RootConstrainSelectedInstOperands,
15263 // GIR_Coverage, 1814,
15264 GIR_Done,
15265 // Label 966: @38679
15266 GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(38706), // Rule ID 2151 //
15267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15269 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15270 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15271 // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
15272 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
15273 GIR_RootConstrainSelectedInstOperands,
15274 // GIR_Coverage, 2151,
15275 GIR_Done,
15276 // Label 967: @38706
15277 GIM_Reject,
15278 // Label 960: @38707
15279 GIM_Reject,
15280 // Label 954: @38708
15281 GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(38848),
15282 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15283 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15284 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15285 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15286 GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(38761), // Rule ID 212 //
15287 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
15288 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15289 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15290 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
15291 // MIs[1] Operand 1
15292 // No operand predicates
15293 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15294 // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
15295 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
15296 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15297 GIR_RootToRootCopy, /*OpIdx*/1, // rt
15298 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15299 GIR_RootConstrainSelectedInstOperands,
15300 // GIR_Coverage, 212,
15301 GIR_EraseRootFromParent_Done,
15302 // Label 969: @38761
15303 GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(38828), // Rule ID 1575 //
15304 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15305 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15306 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
15307 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15308 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15309 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15310 // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
15311 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15312 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15313 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15314 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
15315 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15316 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
15317 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
15318 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15319 GIR_RootToRootCopy, /*OpIdx*/1, // rt
15320 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15321 GIR_RootConstrainSelectedInstOperands,
15322 // GIR_Coverage, 1575,
15323 GIR_EraseRootFromParent_Done,
15324 // Label 970: @38828
15325 GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(38847), // Rule ID 220 //
15326 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
15327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15328 // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15329 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
15330 GIR_RootConstrainSelectedInstOperands,
15331 // GIR_Coverage, 220,
15332 GIR_Done,
15333 // Label 971: @38847
15334 GIM_Reject,
15335 // Label 968: @38848
15336 GIM_Reject,
15337 // Label 955: @38849
15338 GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(38882), // Rule ID 992 //
15339 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15340 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
15341 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15342 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15343 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15344 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
15345 // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
15346 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
15347 GIR_RootConstrainSelectedInstOperands,
15348 // GIR_Coverage, 992,
15349 GIR_Done,
15350 // Label 972: @38882
15351 GIM_Reject,
15352 // Label 956: @38883
15353 GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(39150),
15354 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
15355 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15356 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15357 GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(39012), // Rule ID 2454 //
15358 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15359 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15360 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15361 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15362 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15363 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15364 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15365 GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
15366 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15367 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15368 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15369 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15370 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15371 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15372 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15373 // MIs[3] Operand 1
15374 // No operand predicates
15375 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15376 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15377 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15378 // MIs[4] Operand 1
15379 // No operand predicates
15380 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15381 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15382 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15383 // MIs[5] Operand 1
15384 // No operand predicates
15385 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15386 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15387 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15388 // MIs[6] Operand 1
15389 // No operand predicates
15390 GIM_CheckIsSafeToFold, /*NumInsns*/6,
15391 // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15392 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
15393 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15394 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15396 GIR_RootConstrainSelectedInstOperands,
15397 // GIR_Coverage, 2454,
15398 GIR_EraseRootFromParent_Done,
15399 // Label 974: @39012
15400 GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(39126), // Rule ID 2057 //
15401 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15402 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15403 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15404 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
15405 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
15406 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15407 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15408 GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
15409 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15410 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15411 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15412 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15413 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15414 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15415 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15416 // MIs[3] Operand 1
15417 // No operand predicates
15418 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15419 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15420 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15421 // MIs[4] Operand 1
15422 // No operand predicates
15423 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15424 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15425 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15426 // MIs[5] Operand 1
15427 // No operand predicates
15428 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15429 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15430 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
15431 // MIs[6] Operand 1
15432 // No operand predicates
15433 GIM_CheckIsSafeToFold, /*NumInsns*/6,
15434 // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
15435 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
15436 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15437 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15438 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15439 GIR_RootConstrainSelectedInstOperands,
15440 // GIR_Coverage, 2057,
15441 GIR_EraseRootFromParent_Done,
15442 // Label 975: @39126
15443 GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(39149), // Rule ID 991 //
15444 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15445 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
15447 // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
15448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
15449 GIR_RootConstrainSelectedInstOperands,
15450 // GIR_Coverage, 991,
15451 GIR_Done,
15452 // Label 976: @39149
15453 GIM_Reject,
15454 // Label 973: @39150
15455 GIM_Reject,
15456 // Label 957: @39151
15457 GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(39546),
15458 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
15459 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15460 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15461 GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(39344), // Rule ID 2453 //
15462 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15463 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15464 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15465 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15466 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15467 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15468 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15469 GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15470 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15471 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15472 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15473 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15474 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15475 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15476 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15477 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15478 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15479 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15480 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15481 // MIs[3] Operand 1
15482 // No operand predicates
15483 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15484 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15485 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15486 // MIs[4] Operand 1
15487 // No operand predicates
15488 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15489 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15490 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15491 // MIs[5] Operand 1
15492 // No operand predicates
15493 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15494 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15495 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15496 // MIs[6] Operand 1
15497 // No operand predicates
15498 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15499 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15500 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15501 // MIs[7] Operand 1
15502 // No operand predicates
15503 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15504 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15505 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15506 // MIs[8] Operand 1
15507 // No operand predicates
15508 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15509 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15510 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15511 // MIs[9] Operand 1
15512 // No operand predicates
15513 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15514 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15515 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15516 // MIs[10] Operand 1
15517 // No operand predicates
15518 GIM_CheckIsSafeToFold, /*NumInsns*/10,
15519 // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15520 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
15521 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15522 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15524 GIR_RootConstrainSelectedInstOperands,
15525 // GIR_Coverage, 2453,
15526 GIR_EraseRootFromParent_Done,
15527 // Label 978: @39344
15528 GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(39522), // Rule ID 2056 //
15529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15530 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15531 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15532 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
15533 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
15534 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15535 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15536 GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
15537 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15538 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15539 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15540 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15541 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15542 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15543 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15544 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15545 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15546 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15547 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15548 // MIs[3] Operand 1
15549 // No operand predicates
15550 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15551 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15552 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15553 // MIs[4] Operand 1
15554 // No operand predicates
15555 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15556 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15557 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15558 // MIs[5] Operand 1
15559 // No operand predicates
15560 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15561 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15562 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15563 // MIs[6] Operand 1
15564 // No operand predicates
15565 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15566 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15567 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15568 // MIs[7] Operand 1
15569 // No operand predicates
15570 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15571 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15572 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15573 // MIs[8] Operand 1
15574 // No operand predicates
15575 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15576 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15577 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15578 // MIs[9] Operand 1
15579 // No operand predicates
15580 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15581 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15582 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
15583 // MIs[10] Operand 1
15584 // No operand predicates
15585 GIM_CheckIsSafeToFold, /*NumInsns*/10,
15586 // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
15587 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
15588 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15589 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15591 GIR_RootConstrainSelectedInstOperands,
15592 // GIR_Coverage, 2056,
15593 GIR_EraseRootFromParent_Done,
15594 // Label 979: @39522
15595 GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(39545), // Rule ID 990 //
15596 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15597 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15598 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
15599 // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
15600 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
15601 GIR_RootConstrainSelectedInstOperands,
15602 // GIR_Coverage, 990,
15603 GIR_Done,
15604 // Label 980: @39545
15605 GIM_Reject,
15606 // Label 977: @39546
15607 GIM_Reject,
15608 // Label 958: @39547
15609 GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(40198),
15610 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
15611 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15613 GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(39868), // Rule ID 2452 //
15614 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15615 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15616 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15617 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15618 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15619 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
15620 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15621 GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15622 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15623 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15624 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15625 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15626 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15627 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15628 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15629 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15630 GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15631 GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15632 GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15633 GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15634 GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15635 GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15636 GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15637 GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15638 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15639 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15640 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15641 // MIs[3] Operand 1
15642 // No operand predicates
15643 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15644 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15645 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15646 // MIs[4] Operand 1
15647 // No operand predicates
15648 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15649 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15650 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15651 // MIs[5] Operand 1
15652 // No operand predicates
15653 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15654 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15655 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15656 // MIs[6] Operand 1
15657 // No operand predicates
15658 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15659 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15660 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15661 // MIs[7] Operand 1
15662 // No operand predicates
15663 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15664 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15665 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15666 // MIs[8] Operand 1
15667 // No operand predicates
15668 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15669 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15670 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15671 // MIs[9] Operand 1
15672 // No operand predicates
15673 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15674 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15675 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15676 // MIs[10] Operand 1
15677 // No operand predicates
15678 GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15679 GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15680 GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15681 // MIs[11] Operand 1
15682 // No operand predicates
15683 GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15684 GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15685 GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15686 // MIs[12] Operand 1
15687 // No operand predicates
15688 GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15689 GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15690 GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15691 // MIs[13] Operand 1
15692 // No operand predicates
15693 GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15694 GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15695 GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15696 // MIs[14] Operand 1
15697 // No operand predicates
15698 GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15699 GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15700 GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15701 // MIs[15] Operand 1
15702 // No operand predicates
15703 GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15704 GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15705 GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15706 // MIs[16] Operand 1
15707 // No operand predicates
15708 GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15709 GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15710 GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15711 // MIs[17] Operand 1
15712 // No operand predicates
15713 GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15714 GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15715 GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15716 // MIs[18] Operand 1
15717 // No operand predicates
15718 GIM_CheckIsSafeToFold, /*NumInsns*/18,
15719 // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15720 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
15721 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15722 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15723 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
15724 GIR_RootConstrainSelectedInstOperands,
15725 // GIR_Coverage, 2452,
15726 GIR_EraseRootFromParent_Done,
15727 // Label 982: @39868
15728 GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(40174), // Rule ID 2055 //
15729 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
15730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
15732 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
15733 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
15734 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
15735 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
15736 GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
15737 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
15738 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
15739 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
15740 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
15741 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
15742 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
15743 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
15744 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
15745 GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
15746 GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
15747 GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
15748 GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
15749 GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
15750 GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
15751 GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
15752 GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
15753 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
15754 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15755 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15756 // MIs[3] Operand 1
15757 // No operand predicates
15758 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
15759 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15760 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15761 // MIs[4] Operand 1
15762 // No operand predicates
15763 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
15764 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15765 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15766 // MIs[5] Operand 1
15767 // No operand predicates
15768 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
15769 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15770 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15771 // MIs[6] Operand 1
15772 // No operand predicates
15773 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
15774 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15775 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15776 // MIs[7] Operand 1
15777 // No operand predicates
15778 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
15779 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15780 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15781 // MIs[8] Operand 1
15782 // No operand predicates
15783 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
15784 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15785 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15786 // MIs[9] Operand 1
15787 // No operand predicates
15788 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
15789 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15790 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15791 // MIs[10] Operand 1
15792 // No operand predicates
15793 GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
15794 GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15795 GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15796 // MIs[11] Operand 1
15797 // No operand predicates
15798 GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
15799 GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15800 GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15801 // MIs[12] Operand 1
15802 // No operand predicates
15803 GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
15804 GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15805 GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15806 // MIs[13] Operand 1
15807 // No operand predicates
15808 GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
15809 GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15810 GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15811 // MIs[14] Operand 1
15812 // No operand predicates
15813 GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
15814 GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15815 GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15816 // MIs[15] Operand 1
15817 // No operand predicates
15818 GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
15819 GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15820 GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15821 // MIs[16] Operand 1
15822 // No operand predicates
15823 GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
15824 GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15825 GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15826 // MIs[17] Operand 1
15827 // No operand predicates
15828 GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
15829 GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15830 GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
15831 // MIs[18] Operand 1
15832 // No operand predicates
15833 GIM_CheckIsSafeToFold, /*NumInsns*/18,
15834 // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
15835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
15836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
15837 GIR_RootToRootCopy, /*OpIdx*/1, // ws
15838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
15839 GIR_RootConstrainSelectedInstOperands,
15840 // GIR_Coverage, 2055,
15841 GIR_EraseRootFromParent_Done,
15842 // Label 983: @40174
15843 GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(40197), // Rule ID 989 //
15844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
15845 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15846 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
15847 // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
15848 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
15849 GIR_RootConstrainSelectedInstOperands,
15850 // GIR_Coverage, 989,
15851 GIR_Done,
15852 // Label 984: @40197
15853 GIM_Reject,
15854 // Label 981: @40198
15855 GIM_Reject,
15856 // Label 959: @40199
15857 GIM_Reject,
15858 // Label 26: @40200
15859 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 991*/ GIMT_Encode4(41954),
15860 /*GILLT_s32*//*Label 985*/ GIMT_Encode4(40243),
15861 /*GILLT_s64*//*Label 986*/ GIMT_Encode4(40463), GIMT_Encode4(0),
15862 /*GILLT_v2s64*//*Label 987*/ GIMT_Encode4(40604), GIMT_Encode4(0),
15863 /*GILLT_v4s32*//*Label 988*/ GIMT_Encode4(40638),
15864 /*GILLT_v8s16*//*Label 989*/ GIMT_Encode4(40906),
15865 /*GILLT_v16s8*//*Label 990*/ GIMT_Encode4(41302),
15866 // Label 985: @40243
15867 GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(40462),
15868 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15869 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15870 GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(40296), // Rule ID 59 //
15871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
15872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15873 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15875 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15876 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15877 // MIs[1] Operand 1
15878 // No operand predicates
15879 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15880 // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
15881 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
15882 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15883 GIR_RootToRootCopy, /*OpIdx*/1, // rt
15884 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15885 GIR_RootConstrainSelectedInstOperands,
15886 // GIR_Coverage, 59,
15887 GIR_EraseRootFromParent_Done,
15888 // Label 993: @40296
15889 GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(40338), // Rule ID 1811 //
15890 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15892 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15893 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15894 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15895 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15896 // MIs[1] Operand 1
15897 // No operand predicates
15898 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15899 // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15900 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
15901 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
15902 GIR_RootToRootCopy, /*OpIdx*/1, // in
15903 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15904 GIR_RootConstrainSelectedInstOperands,
15905 // GIR_Coverage, 1811,
15906 GIR_EraseRootFromParent_Done,
15907 // Label 994: @40338
15908 GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(40380), // Rule ID 2152 //
15909 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15910 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15911 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15913 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15914 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
15915 // MIs[1] Operand 1
15916 // No operand predicates
15917 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15918 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
15919 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
15920 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15921 GIR_RootToRootCopy, /*OpIdx*/1, // src
15922 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
15923 GIR_RootConstrainSelectedInstOperands,
15924 // GIR_Coverage, 2152,
15925 GIR_EraseRootFromParent_Done,
15926 // Label 995: @40380
15927 GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(40407), // Rule ID 65 //
15928 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
15929 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15930 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15931 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15932 // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
15933 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
15934 GIR_RootConstrainSelectedInstOperands,
15935 // GIR_Coverage, 65,
15936 GIR_Done,
15937 // Label 996: @40407
15938 GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(40434), // Rule ID 1813 //
15939 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
15940 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15941 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15942 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
15943 // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
15944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
15945 GIR_RootConstrainSelectedInstOperands,
15946 // GIR_Coverage, 1813,
15947 GIR_Done,
15948 // Label 997: @40434
15949 GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(40461), // Rule ID 2153 //
15950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
15951 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15952 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15953 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
15954 // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
15955 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
15956 GIR_RootConstrainSelectedInstOperands,
15957 // GIR_Coverage, 2153,
15958 GIR_Done,
15959 // Label 998: @40461
15960 GIM_Reject,
15961 // Label 992: @40462
15962 GIM_Reject,
15963 // Label 986: @40463
15964 GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(40603),
15965 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
15966 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15967 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15968 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15969 GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(40516), // Rule ID 214 //
15970 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
15971 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15972 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
15973 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
15974 // MIs[1] Operand 1
15975 // No operand predicates
15976 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15977 // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
15978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
15979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
15980 GIR_RootToRootCopy, /*OpIdx*/1, // rt
15981 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
15982 GIR_RootConstrainSelectedInstOperands,
15983 // GIR_Coverage, 214,
15984 GIR_EraseRootFromParent_Done,
15985 // Label 1000: @40516
15986 GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(40583), // Rule ID 1576 //
15987 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
15988 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
15989 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
15990 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
15991 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
15992 GIM_CheckIsSafeToFold, /*NumInsns*/1,
15993 // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
15994 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15995 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
15996 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
15997 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
15998 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
15999 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16000 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
16001 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16002 GIR_RootToRootCopy, /*OpIdx*/1, // rt
16003 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16004 GIR_RootConstrainSelectedInstOperands,
16005 // GIR_Coverage, 1576,
16006 GIR_EraseRootFromParent_Done,
16007 // Label 1001: @40583
16008 GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(40602), // Rule ID 218 //
16009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
16010 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16011 // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16012 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
16013 GIR_RootConstrainSelectedInstOperands,
16014 // GIR_Coverage, 218,
16015 GIR_Done,
16016 // Label 1002: @40602
16017 GIM_Reject,
16018 // Label 999: @40603
16019 GIM_Reject,
16020 // Label 987: @40604
16021 GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(40637), // Rule ID 976 //
16022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16023 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
16024 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16026 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16027 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
16028 // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
16029 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
16030 GIR_RootConstrainSelectedInstOperands,
16031 // GIR_Coverage, 976,
16032 GIR_Done,
16033 // Label 1003: @40637
16034 GIM_Reject,
16035 // Label 988: @40638
16036 GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(40905),
16037 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
16038 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16040 GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(40767), // Rule ID 2458 //
16041 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16042 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16043 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16044 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16045 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16046 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16047 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16048 GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16049 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16050 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16051 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16052 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16053 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16054 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16055 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16056 // MIs[3] Operand 1
16057 // No operand predicates
16058 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16059 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16060 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16061 // MIs[4] Operand 1
16062 // No operand predicates
16063 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16064 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16065 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16066 // MIs[5] Operand 1
16067 // No operand predicates
16068 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16069 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16070 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16071 // MIs[6] Operand 1
16072 // No operand predicates
16073 GIM_CheckIsSafeToFold, /*NumInsns*/6,
16074 // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
16076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16077 GIR_RootToRootCopy, /*OpIdx*/1, // ws
16078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16079 GIR_RootConstrainSelectedInstOperands,
16080 // GIR_Coverage, 2458,
16081 GIR_EraseRootFromParent_Done,
16082 // Label 1005: @40767
16083 GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(40881), // Rule ID 2061 //
16084 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16085 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16086 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16087 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16088 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
16089 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16090 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16091 GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
16092 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16093 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16094 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16095 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16096 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16097 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16098 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16099 // MIs[3] Operand 1
16100 // No operand predicates
16101 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16102 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16103 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16104 // MIs[4] Operand 1
16105 // No operand predicates
16106 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16107 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16108 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16109 // MIs[5] Operand 1
16110 // No operand predicates
16111 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16112 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16113 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
16114 // MIs[6] Operand 1
16115 // No operand predicates
16116 GIM_CheckIsSafeToFold, /*NumInsns*/6,
16117 // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
16118 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
16119 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16120 GIR_RootToRootCopy, /*OpIdx*/1, // ws
16121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16122 GIR_RootConstrainSelectedInstOperands,
16123 // GIR_Coverage, 2061,
16124 GIR_EraseRootFromParent_Done,
16125 // Label 1006: @40881
16126 GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(40904), // Rule ID 975 //
16127 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16128 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16129 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
16130 // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
16131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
16132 GIR_RootConstrainSelectedInstOperands,
16133 // GIR_Coverage, 975,
16134 GIR_Done,
16135 // Label 1007: @40904
16136 GIM_Reject,
16137 // Label 1004: @40905
16138 GIM_Reject,
16139 // Label 989: @40906
16140 GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(41301),
16141 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
16142 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16143 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16144 GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(41099), // Rule ID 2457 //
16145 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16146 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16147 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16148 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16149 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16150 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16151 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16152 GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16153 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16154 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16155 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16156 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16157 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16158 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16159 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16160 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16161 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16162 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16163 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16164 // MIs[3] Operand 1
16165 // No operand predicates
16166 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16167 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16168 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16169 // MIs[4] Operand 1
16170 // No operand predicates
16171 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16172 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16173 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16174 // MIs[5] Operand 1
16175 // No operand predicates
16176 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16177 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16178 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16179 // MIs[6] Operand 1
16180 // No operand predicates
16181 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16182 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16183 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16184 // MIs[7] Operand 1
16185 // No operand predicates
16186 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16187 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16188 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16189 // MIs[8] Operand 1
16190 // No operand predicates
16191 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16192 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16193 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16194 // MIs[9] Operand 1
16195 // No operand predicates
16196 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16197 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16198 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16199 // MIs[10] Operand 1
16200 // No operand predicates
16201 GIM_CheckIsSafeToFold, /*NumInsns*/10,
16202 // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16203 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
16204 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16205 GIR_RootToRootCopy, /*OpIdx*/1, // ws
16206 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16207 GIR_RootConstrainSelectedInstOperands,
16208 // GIR_Coverage, 2457,
16209 GIR_EraseRootFromParent_Done,
16210 // Label 1009: @41099
16211 GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(41277), // Rule ID 2060 //
16212 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16213 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16214 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16215 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16216 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
16217 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16218 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16219 GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
16220 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16221 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16222 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16223 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16224 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16225 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16226 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16227 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16228 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16229 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16230 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16231 // MIs[3] Operand 1
16232 // No operand predicates
16233 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16234 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16235 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16236 // MIs[4] Operand 1
16237 // No operand predicates
16238 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16239 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16240 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16241 // MIs[5] Operand 1
16242 // No operand predicates
16243 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16244 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16245 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16246 // MIs[6] Operand 1
16247 // No operand predicates
16248 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16249 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16250 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16251 // MIs[7] Operand 1
16252 // No operand predicates
16253 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16254 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16255 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16256 // MIs[8] Operand 1
16257 // No operand predicates
16258 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16259 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16260 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16261 // MIs[9] Operand 1
16262 // No operand predicates
16263 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16264 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16265 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
16266 // MIs[10] Operand 1
16267 // No operand predicates
16268 GIM_CheckIsSafeToFold, /*NumInsns*/10,
16269 // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
16270 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
16271 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16272 GIR_RootToRootCopy, /*OpIdx*/1, // ws
16273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16274 GIR_RootConstrainSelectedInstOperands,
16275 // GIR_Coverage, 2060,
16276 GIR_EraseRootFromParent_Done,
16277 // Label 1010: @41277
16278 GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(41300), // Rule ID 974 //
16279 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16280 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16281 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
16282 // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
16283 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
16284 GIR_RootConstrainSelectedInstOperands,
16285 // GIR_Coverage, 974,
16286 GIR_Done,
16287 // Label 1011: @41300
16288 GIM_Reject,
16289 // Label 1008: @41301
16290 GIM_Reject,
16291 // Label 990: @41302
16292 GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(41953),
16293 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
16294 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16295 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16296 GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(41623), // Rule ID 2456 //
16297 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16298 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16299 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16300 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16301 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16302 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
16303 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16304 GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16305 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16306 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16307 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16308 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16309 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16310 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16311 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16312 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16313 GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16314 GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16315 GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16316 GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16317 GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16318 GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16319 GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16320 GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16321 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16322 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16323 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16324 // MIs[3] Operand 1
16325 // No operand predicates
16326 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16327 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16328 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16329 // MIs[4] Operand 1
16330 // No operand predicates
16331 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16332 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16333 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16334 // MIs[5] Operand 1
16335 // No operand predicates
16336 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16337 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16338 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16339 // MIs[6] Operand 1
16340 // No operand predicates
16341 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16342 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16343 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16344 // MIs[7] Operand 1
16345 // No operand predicates
16346 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16347 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16348 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16349 // MIs[8] Operand 1
16350 // No operand predicates
16351 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16352 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16353 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16354 // MIs[9] Operand 1
16355 // No operand predicates
16356 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16357 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16358 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16359 // MIs[10] Operand 1
16360 // No operand predicates
16361 GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16362 GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16363 GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16364 // MIs[11] Operand 1
16365 // No operand predicates
16366 GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16367 GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16368 GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16369 // MIs[12] Operand 1
16370 // No operand predicates
16371 GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16372 GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16373 GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16374 // MIs[13] Operand 1
16375 // No operand predicates
16376 GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16377 GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16378 GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16379 // MIs[14] Operand 1
16380 // No operand predicates
16381 GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16382 GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16383 GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16384 // MIs[15] Operand 1
16385 // No operand predicates
16386 GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16387 GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16388 GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16389 // MIs[16] Operand 1
16390 // No operand predicates
16391 GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16392 GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16393 GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16394 // MIs[17] Operand 1
16395 // No operand predicates
16396 GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16397 GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16398 GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16399 // MIs[18] Operand 1
16400 // No operand predicates
16401 GIM_CheckIsSafeToFold, /*NumInsns*/18,
16402 // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16403 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
16404 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16405 GIR_RootToRootCopy, /*OpIdx*/1, // ws
16406 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
16407 GIR_RootConstrainSelectedInstOperands,
16408 // GIR_Coverage, 2456,
16409 GIR_EraseRootFromParent_Done,
16410 // Label 1013: @41623
16411 GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(41929), // Rule ID 2059 //
16412 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
16413 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16414 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
16415 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
16416 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
16417 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16418 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
16419 GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
16420 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
16421 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
16422 GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
16423 GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
16424 GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
16425 GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
16426 GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
16427 GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
16428 GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
16429 GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
16430 GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
16431 GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
16432 GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
16433 GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
16434 GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
16435 GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
16436 GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
16437 GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16438 GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16439 // MIs[3] Operand 1
16440 // No operand predicates
16441 GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
16442 GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16443 GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16444 // MIs[4] Operand 1
16445 // No operand predicates
16446 GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
16447 GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16448 GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16449 // MIs[5] Operand 1
16450 // No operand predicates
16451 GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
16452 GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16453 GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16454 // MIs[6] Operand 1
16455 // No operand predicates
16456 GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
16457 GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16458 GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16459 // MIs[7] Operand 1
16460 // No operand predicates
16461 GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
16462 GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16463 GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16464 // MIs[8] Operand 1
16465 // No operand predicates
16466 GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
16467 GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16468 GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16469 // MIs[9] Operand 1
16470 // No operand predicates
16471 GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
16472 GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16473 GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16474 // MIs[10] Operand 1
16475 // No operand predicates
16476 GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
16477 GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16478 GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16479 // MIs[11] Operand 1
16480 // No operand predicates
16481 GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
16482 GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16483 GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16484 // MIs[12] Operand 1
16485 // No operand predicates
16486 GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
16487 GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16488 GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16489 // MIs[13] Operand 1
16490 // No operand predicates
16491 GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
16492 GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16493 GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16494 // MIs[14] Operand 1
16495 // No operand predicates
16496 GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
16497 GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16498 GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16499 // MIs[15] Operand 1
16500 // No operand predicates
16501 GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
16502 GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16503 GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16504 // MIs[16] Operand 1
16505 // No operand predicates
16506 GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
16507 GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16508 GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16509 // MIs[17] Operand 1
16510 // No operand predicates
16511 GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
16512 GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16513 GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
16514 // MIs[18] Operand 1
16515 // No operand predicates
16516 GIM_CheckIsSafeToFold, /*NumInsns*/18,
16517 // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
16518 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
16519 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
16520 GIR_RootToRootCopy, /*OpIdx*/1, // ws
16521 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
16522 GIR_RootConstrainSelectedInstOperands,
16523 // GIR_Coverage, 2059,
16524 GIR_EraseRootFromParent_Done,
16525 // Label 1014: @41929
16526 GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(41952), // Rule ID 973 //
16527 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
16528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16529 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
16530 // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
16531 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
16532 GIR_RootConstrainSelectedInstOperands,
16533 // GIR_Coverage, 973,
16534 GIR_Done,
16535 // Label 1015: @41952
16536 GIM_Reject,
16537 // Label 1012: @41953
16538 GIM_Reject,
16539 // Label 991: @41954
16540 GIM_Reject,
16541 // Label 27: @41955
16542 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1018*/ GIMT_Encode4(42242),
16543 /*GILLT_s32*//*Label 1016*/ GIMT_Encode4(41974),
16544 /*GILLT_s64*//*Label 1017*/ GIMT_Encode4(42101),
16545 // Label 1016: @41974
16546 GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(42100),
16547 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
16548 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16549 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16550 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16551 GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(42027), // Rule ID 67 //
16552 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
16553 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16554 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16555 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16556 // MIs[1] Operand 1
16557 // No operand predicates
16558 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16559 // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16560 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
16561 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16562 GIR_RootToRootCopy, /*OpIdx*/1, // rt
16563 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16564 GIR_RootConstrainSelectedInstOperands,
16565 // GIR_Coverage, 67,
16566 GIR_EraseRootFromParent_Done,
16567 // Label 1020: @42027
16568 GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(42061), // Rule ID 1081 //
16569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16570 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16571 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16572 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
16573 // MIs[1] Operand 1
16574 // No operand predicates
16575 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16576 // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
16577 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
16578 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16579 GIR_RootToRootCopy, /*OpIdx*/1, // rt
16580 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16581 GIR_RootConstrainSelectedInstOperands,
16582 // GIR_Coverage, 1081,
16583 GIR_EraseRootFromParent_Done,
16584 // Label 1021: @42061
16585 GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(42080), // Rule ID 68 //
16586 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
16587 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16588 // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16589 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
16590 GIR_RootConstrainSelectedInstOperands,
16591 // GIR_Coverage, 68,
16592 GIR_Done,
16593 // Label 1022: @42080
16594 GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(42099), // Rule ID 1082 //
16595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16596 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16597 // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16598 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
16599 GIR_RootConstrainSelectedInstOperands,
16600 // GIR_Coverage, 1082,
16601 GIR_Done,
16602 // Label 1023: @42099
16603 GIM_Reject,
16604 // Label 1019: @42100
16605 GIM_Reject,
16606 // Label 1017: @42101
16607 GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(42241),
16608 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
16609 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16610 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16611 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16612 GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(42154), // Rule ID 222 //
16613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
16614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16615 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16616 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
16617 // MIs[1] Operand 1
16618 // No operand predicates
16619 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16620 // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
16621 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
16622 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16623 GIR_RootToRootCopy, /*OpIdx*/1, // rt
16624 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
16625 GIR_RootConstrainSelectedInstOperands,
16626 // GIR_Coverage, 222,
16627 GIR_EraseRootFromParent_Done,
16628 // Label 1025: @42154
16629 GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(42221), // Rule ID 1577 //
16630 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
16631 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16632 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
16633 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
16634 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16635 GIM_CheckIsSafeToFold, /*NumInsns*/1,
16636 // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
16637 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16638 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16639 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16640 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
16641 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
16642 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
16643 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
16644 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16645 GIR_RootToRootCopy, /*OpIdx*/1, // rt
16646 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16647 GIR_RootConstrainSelectedInstOperands,
16648 // GIR_Coverage, 1577,
16649 GIR_EraseRootFromParent_Done,
16650 // Label 1026: @42221
16651 GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(42240), // Rule ID 223 //
16652 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
16653 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16654 // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
16655 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
16656 GIR_RootConstrainSelectedInstOperands,
16657 // GIR_Coverage, 223,
16658 GIR_Done,
16659 // Label 1027: @42240
16660 GIM_Reject,
16661 // Label 1024: @42241
16662 GIM_Reject,
16663 // Label 1018: @42242
16664 GIM_Reject,
16665 // Label 28: @42243
16666 GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(44773),
16667 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16668 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1031*/ GIMT_Encode4(42436),
16669 /*GILLT_s32*//*Label 1029*/ GIMT_Encode4(42270),
16670 /*GILLT_s64*//*Label 1030*/ GIMT_Encode4(42353),
16671 // Label 1029: @42270
16672 GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(42352),
16673 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16674 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16675 GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(42315), // Rule ID 1415 //
16676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16677 // MIs[0] Operand 1
16678 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16679 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16680 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16681 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
16682 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
16683 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16684 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16685 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16686 GIR_RootConstrainSelectedInstOperands,
16687 // GIR_Coverage, 1415,
16688 GIR_EraseRootFromParent_Done,
16689 // Label 1033: @42315
16690 GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(42351), // Rule ID 1416 //
16691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16692 // MIs[0] Operand 1
16693 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16694 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16695 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16696 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
16697 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
16698 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16699 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16700 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16701 GIR_RootConstrainSelectedInstOperands,
16702 // GIR_Coverage, 1416,
16703 GIR_EraseRootFromParent_Done,
16704 // Label 1034: @42351
16705 GIM_Reject,
16706 // Label 1032: @42352
16707 GIM_Reject,
16708 // Label 1030: @42353
16709 GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(42435),
16710 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
16711 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16712 GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(42398), // Rule ID 1559 //
16713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
16714 // MIs[0] Operand 1
16715 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16716 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16717 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16718 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
16719 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
16720 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16721 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16722 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16723 GIR_RootConstrainSelectedInstOperands,
16724 // GIR_Coverage, 1559,
16725 GIR_EraseRootFromParent_Done,
16726 // Label 1036: @42398
16727 GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(42434), // Rule ID 1560 //
16728 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
16729 // MIs[0] Operand 1
16730 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16731 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16732 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16733 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
16734 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
16735 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16736 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16737 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16738 GIR_RootConstrainSelectedInstOperands,
16739 // GIR_Coverage, 1560,
16740 GIR_EraseRootFromParent_Done,
16741 // Label 1037: @42434
16742 GIM_Reject,
16743 // Label 1035: @42435
16744 GIM_Reject,
16745 // Label 1031: @42436
16746 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1040*/ GIMT_Encode4(42819),
16747 /*GILLT_s32*//*Label 1038*/ GIMT_Encode4(42455),
16748 /*GILLT_s64*//*Label 1039*/ GIMT_Encode4(42741),
16749 // Label 1038: @42455
16750 GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(42740),
16751 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16752 GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(42500), // Rule ID 1861 //
16753 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16754 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16755 // MIs[0] Operand 1
16756 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16757 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16758 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16759 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
16760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
16761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
16762 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16763 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16764 GIR_RootConstrainSelectedInstOperands,
16765 // GIR_Coverage, 1861,
16766 GIR_EraseRootFromParent_Done,
16767 // Label 1042: @42500
16768 GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(42590), // Rule ID 1863 //
16769 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
16770 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16771 // MIs[0] Operand 1
16772 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
16773 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
16774 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-32769),
16775 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
16776 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16777 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
16778 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
16779 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16780 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
16781 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16782 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
16783 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16784 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16785 GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(-32768),
16786 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16787 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
16788 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
16789 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16790 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
16791 GIR_RootConstrainSelectedInstOperands,
16792 // GIR_Coverage, 1863,
16793 GIR_EraseRootFromParent_Done,
16794 // Label 1043: @42590
16795 GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(42627), // Rule ID 2180 //
16796 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16797 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16798 // MIs[0] Operand 1
16799 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16800 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16801 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16802 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
16803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
16804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16805 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16806 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16807 GIR_RootConstrainSelectedInstOperands,
16808 // GIR_Coverage, 2180,
16809 GIR_EraseRootFromParent_Done,
16810 // Label 1044: @42627
16811 GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(42667), // Rule ID 2181 //
16812 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16814 // MIs[0] Operand 1
16815 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16816 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16817 GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16818 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
16819 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
16820 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16821 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16822 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
16823 GIR_RootConstrainSelectedInstOperands,
16824 // GIR_Coverage, 2181,
16825 GIR_EraseRootFromParent_Done,
16826 // Label 1045: @42667
16827 GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(42703), // Rule ID 49 //
16828 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16829 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16830 // MIs[0] Operand 1
16831 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
16832 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16833 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16834 // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
16835 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
16836 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16837 GIR_RootToRootCopy, /*OpIdx*/2, // rs
16838 GIR_RootToRootCopy, /*OpIdx*/3, // rt
16839 GIR_RootConstrainSelectedInstOperands,
16840 // GIR_Coverage, 49,
16841 GIR_EraseRootFromParent_Done,
16842 // Label 1046: @42703
16843 GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(42739), // Rule ID 50 //
16844 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16845 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16846 // MIs[0] Operand 1
16847 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
16848 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16849 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16850 // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
16851 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
16852 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16853 GIR_RootToRootCopy, /*OpIdx*/2, // rs
16854 GIR_RootToRootCopy, /*OpIdx*/3, // rt
16855 GIR_RootConstrainSelectedInstOperands,
16856 // GIR_Coverage, 50,
16857 GIR_EraseRootFromParent_Done,
16858 // Label 1047: @42739
16859 GIM_Reject,
16860 // Label 1041: @42740
16861 GIM_Reject,
16862 // Label 1039: @42741
16863 GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(42818),
16864 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
16865 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16866 GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(42785), // Rule ID 204 //
16867 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
16868 // MIs[0] Operand 1
16869 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
16870 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16871 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16872 // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
16873 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
16874 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16875 GIR_RootToRootCopy, /*OpIdx*/2, // rs
16876 GIR_RootToRootCopy, /*OpIdx*/3, // rt
16877 GIR_RootConstrainSelectedInstOperands,
16878 // GIR_Coverage, 204,
16879 GIR_EraseRootFromParent_Done,
16880 // Label 1049: @42785
16881 GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(42817), // Rule ID 205 //
16882 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
16883 // MIs[0] Operand 1
16884 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
16885 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16886 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
16887 // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
16888 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
16889 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16890 GIR_RootToRootCopy, /*OpIdx*/2, // rs
16891 GIR_RootToRootCopy, /*OpIdx*/3, // rt
16892 GIR_RootConstrainSelectedInstOperands,
16893 // GIR_Coverage, 205,
16894 GIR_EraseRootFromParent_Done,
16895 // Label 1050: @42817
16896 GIM_Reject,
16897 // Label 1048: @42818
16898 GIM_Reject,
16899 // Label 1040: @42819
16900 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1053*/ GIMT_Encode4(43736),
16901 /*GILLT_s32*//*Label 1051*/ GIMT_Encode4(42838),
16902 /*GILLT_s64*//*Label 1052*/ GIMT_Encode4(43319),
16903 // Label 1051: @42838
16904 GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(43318),
16905 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16906 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16907 GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(42882), // Rule ID 1075 //
16908 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16909 // MIs[0] Operand 1
16910 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
16911 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16912 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16913 // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
16914 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
16915 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16916 GIR_RootToRootCopy, /*OpIdx*/2, // rs
16917 GIR_RootToRootCopy, /*OpIdx*/3, // rt
16918 GIR_RootConstrainSelectedInstOperands,
16919 // GIR_Coverage, 1075,
16920 GIR_EraseRootFromParent_Done,
16921 // Label 1055: @42882
16922 GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(42914), // Rule ID 1076 //
16923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
16924 // MIs[0] Operand 1
16925 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
16926 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16927 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16928 // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
16929 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
16930 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16931 GIR_RootToRootCopy, /*OpIdx*/2, // rs
16932 GIR_RootToRootCopy, /*OpIdx*/3, // rt
16933 GIR_RootConstrainSelectedInstOperands,
16934 // GIR_Coverage, 1076,
16935 GIR_EraseRootFromParent_Done,
16936 // Label 1056: @42914
16937 GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(42970), // Rule ID 1417 //
16938 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16939 // MIs[0] Operand 1
16940 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
16941 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16942 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16943 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
16944 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16945 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
16946 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16947 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16948 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16949 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16950 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
16951 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16952 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16953 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16954 GIR_RootConstrainSelectedInstOperands,
16955 // GIR_Coverage, 1417,
16956 GIR_EraseRootFromParent_Done,
16957 // Label 1057: @42970
16958 GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(43029), // Rule ID 1418 //
16959 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16960 // MIs[0] Operand 1
16961 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
16962 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16963 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16964 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
16965 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16966 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
16967 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16968 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16969 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16970 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16971 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
16972 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
16973 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16974 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16975 GIR_RootConstrainSelectedInstOperands,
16976 // GIR_Coverage, 1418,
16977 GIR_EraseRootFromParent_Done,
16978 // Label 1058: @43029
16979 GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(43085), // Rule ID 1419 //
16980 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
16981 // MIs[0] Operand 1
16982 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
16983 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16984 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
16985 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
16986 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16987 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
16988 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
16989 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
16990 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
16991 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
16992 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
16993 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
16994 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16995 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
16996 GIR_RootConstrainSelectedInstOperands,
16997 // GIR_Coverage, 1419,
16998 GIR_EraseRootFromParent_Done,
16999 // Label 1059: @43085
17000 GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(43141), // Rule ID 1420 //
17001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17002 // MIs[0] Operand 1
17003 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
17004 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17005 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17006 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17007 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17008 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17009 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17010 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17011 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17012 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17013 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17014 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17015 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17016 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17017 GIR_RootConstrainSelectedInstOperands,
17018 // GIR_Coverage, 1420,
17019 GIR_EraseRootFromParent_Done,
17020 // Label 1060: @43141
17021 GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(43173), // Rule ID 1421 //
17022 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17023 // MIs[0] Operand 1
17024 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17025 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17026 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17027 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17028 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
17029 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17030 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17031 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17032 GIR_RootConstrainSelectedInstOperands,
17033 // GIR_Coverage, 1421,
17034 GIR_EraseRootFromParent_Done,
17035 // Label 1061: @43173
17036 GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(43205), // Rule ID 1422 //
17037 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17038 // MIs[0] Operand 1
17039 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
17040 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17041 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17042 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17043 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17044 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17045 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17046 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17047 GIR_RootConstrainSelectedInstOperands,
17048 // GIR_Coverage, 1422,
17049 GIR_EraseRootFromParent_Done,
17050 // Label 1062: @43205
17051 GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(43261), // Rule ID 1423 //
17052 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17053 // MIs[0] Operand 1
17054 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17055 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17056 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17057 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17058 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17059 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
17060 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17061 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17062 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17063 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17064 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17065 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17066 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17067 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17068 GIR_RootConstrainSelectedInstOperands,
17069 // GIR_Coverage, 1423,
17070 GIR_EraseRootFromParent_Done,
17071 // Label 1063: @43261
17072 GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(43317), // Rule ID 1424 //
17073 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
17074 // MIs[0] Operand 1
17075 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
17076 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17077 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17078 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17079 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17080 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
17081 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17082 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17083 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17084 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17085 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17086 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17087 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17088 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17089 GIR_RootConstrainSelectedInstOperands,
17090 // GIR_Coverage, 1424,
17091 GIR_EraseRootFromParent_Done,
17092 // Label 1064: @43317
17093 GIM_Reject,
17094 // Label 1054: @43318
17095 GIM_Reject,
17096 // Label 1052: @43319
17097 GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(43735),
17098 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
17099 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17100 GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(43387), // Rule ID 1561 //
17101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17102 // MIs[0] Operand 1
17103 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17104 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17105 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17106 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
17107 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
17108 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
17109 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17110 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17111 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17112 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17113 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
17114 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17115 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17116 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17117 GIR_RootConstrainSelectedInstOperands,
17118 // GIR_Coverage, 1561,
17119 GIR_EraseRootFromParent_Done,
17120 // Label 1066: @43387
17121 GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(43446), // Rule ID 1562 //
17122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17123 // MIs[0] Operand 1
17124 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17125 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17126 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17127 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
17128 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
17129 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
17130 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17131 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17132 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17133 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17134 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
17135 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17136 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17137 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17138 GIR_RootConstrainSelectedInstOperands,
17139 // GIR_Coverage, 1562,
17140 GIR_EraseRootFromParent_Done,
17141 // Label 1067: @43446
17142 GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(43502), // Rule ID 1563 //
17143 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17144 // MIs[0] Operand 1
17145 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
17146 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17147 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17148 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
17149 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17150 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
17151 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17152 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17153 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17154 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17155 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17156 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17157 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17158 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17159 GIR_RootConstrainSelectedInstOperands,
17160 // GIR_Coverage, 1563,
17161 GIR_EraseRootFromParent_Done,
17162 // Label 1068: @43502
17163 GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(43558), // Rule ID 1564 //
17164 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17165 // MIs[0] Operand 1
17166 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
17167 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17168 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17169 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
17170 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17171 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
17172 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17173 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17174 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17175 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17176 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17177 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17178 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17179 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17180 GIR_RootConstrainSelectedInstOperands,
17181 // GIR_Coverage, 1564,
17182 GIR_EraseRootFromParent_Done,
17183 // Label 1069: @43558
17184 GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(43590), // Rule ID 1565 //
17185 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17186 // MIs[0] Operand 1
17187 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17188 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17189 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17190 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
17191 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
17192 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17193 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17194 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17195 GIR_RootConstrainSelectedInstOperands,
17196 // GIR_Coverage, 1565,
17197 GIR_EraseRootFromParent_Done,
17198 // Label 1070: @43590
17199 GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(43622), // Rule ID 1566 //
17200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17201 // MIs[0] Operand 1
17202 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
17203 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17204 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17205 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
17206 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
17207 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17208 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17209 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17210 GIR_RootConstrainSelectedInstOperands,
17211 // GIR_Coverage, 1566,
17212 GIR_EraseRootFromParent_Done,
17213 // Label 1071: @43622
17214 GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(43678), // Rule ID 1567 //
17215 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17216 // MIs[0] Operand 1
17217 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17218 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17219 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17220 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
17221 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17222 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
17223 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17224 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17225 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17226 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17227 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17228 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17229 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17230 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17231 GIR_RootConstrainSelectedInstOperands,
17232 // GIR_Coverage, 1567,
17233 GIR_EraseRootFromParent_Done,
17234 // Label 1072: @43678
17235 GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(43734), // Rule ID 1568 //
17236 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
17237 // MIs[0] Operand 1
17238 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
17239 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17240 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
17241 // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
17242 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
17244 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17245 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17246 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17247 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17248 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
17249 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17250 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17251 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17252 GIR_RootConstrainSelectedInstOperands,
17253 // GIR_Coverage, 1568,
17254 GIR_EraseRootFromParent_Done,
17255 // Label 1073: @43734
17256 GIM_Reject,
17257 // Label 1065: @43735
17258 GIM_Reject,
17259 // Label 1053: @43736
17260 GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(44772),
17261 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17262 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17263 GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(43807), // Rule ID 1860 //
17264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17266 // MIs[0] Operand 1
17267 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17268 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17269 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17270 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17271 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17273 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17274 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17275 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17276 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17277 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
17278 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17279 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17280 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17281 GIR_RootConstrainSelectedInstOperands,
17282 // GIR_Coverage, 1860,
17283 GIR_EraseRootFromParent_Done,
17284 // Label 1075: @43807
17285 GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(43884), // Rule ID 1862 //
17286 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17288 // MIs[0] Operand 1
17289 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17290 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17291 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17292 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17293 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17294 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17295 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17296 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17297 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17298 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17299 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17300 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17301 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17302 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17303 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17304 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17305 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17306 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17307 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17308 GIR_RootConstrainSelectedInstOperands,
17309 // GIR_Coverage, 1862,
17310 GIR_EraseRootFromParent_Done,
17311 // Label 1076: @43884
17312 GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(43920), // Rule ID 1864 //
17313 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17314 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17315 // MIs[0] Operand 1
17316 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17317 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17318 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17319 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
17320 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17321 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17322 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17323 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17324 GIR_RootConstrainSelectedInstOperands,
17325 // GIR_Coverage, 1864,
17326 GIR_EraseRootFromParent_Done,
17327 // Label 1077: @43920
17328 GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(43997), // Rule ID 1865 //
17329 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17330 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17331 // MIs[0] Operand 1
17332 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
17333 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17334 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17335 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
17336 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17337 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17338 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
17339 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17340 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17341 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17342 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17343 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17344 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17345 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17346 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17347 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17348 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17349 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17350 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17351 GIR_RootConstrainSelectedInstOperands,
17352 // GIR_Coverage, 1865,
17353 GIR_EraseRootFromParent_Done,
17354 // Label 1078: @43997
17355 GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(44033), // Rule ID 1866 //
17356 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17357 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17358 // MIs[0] Operand 1
17359 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
17360 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17361 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17362 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
17363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
17364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17365 GIR_RootToRootCopy, /*OpIdx*/2, // rx
17366 GIR_RootToRootCopy, /*OpIdx*/3, // ry
17367 GIR_RootConstrainSelectedInstOperands,
17368 // GIR_Coverage, 1866,
17369 GIR_EraseRootFromParent_Done,
17370 // Label 1079: @44033
17371 GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(44110), // Rule ID 1868 //
17372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17374 // MIs[0] Operand 1
17375 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17376 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17377 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17378 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
17379 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17380 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17381 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17382 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17383 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17384 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17385 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17386 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17387 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17388 GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
17389 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17390 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17391 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17392 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17393 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17394 GIR_RootConstrainSelectedInstOperands,
17395 // GIR_Coverage, 1868,
17396 GIR_EraseRootFromParent_Done,
17397 // Label 1080: @44110
17398 GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(44187), // Rule ID 1869 //
17399 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17400 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17401 // MIs[0] Operand 1
17402 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
17403 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17404 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17405 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17406 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17407 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17408 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17409 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17410 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17411 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17412 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17413 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17414 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17415 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17416 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17417 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17418 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17419 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17420 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17421 GIR_RootConstrainSelectedInstOperands,
17422 // GIR_Coverage, 1869,
17423 GIR_EraseRootFromParent_Done,
17424 // Label 1081: @44187
17425 GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(44223), // Rule ID 1870 //
17426 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17427 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17428 // MIs[0] Operand 1
17429 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
17430 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17431 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17432 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
17433 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17434 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17435 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17436 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17437 GIR_RootConstrainSelectedInstOperands,
17438 // GIR_Coverage, 1870,
17439 GIR_EraseRootFromParent_Done,
17440 // Label 1082: @44223
17441 GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(44300), // Rule ID 1871 //
17442 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17443 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17444 // MIs[0] Operand 1
17445 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
17446 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17447 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17448 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
17449 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17450 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
17451 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
17452 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17453 GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
17454 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17455 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17456 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17457 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17458 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17459 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17460 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
17461 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
17462 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17463 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
17464 GIR_RootConstrainSelectedInstOperands,
17465 // GIR_Coverage, 1871,
17466 GIR_EraseRootFromParent_Done,
17467 // Label 1083: @44300
17468 GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(44336), // Rule ID 1872 //
17469 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
17470 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17471 // MIs[0] Operand 1
17472 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
17473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17474 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
17475 // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
17476 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
17477 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
17478 GIR_RootToRootCopy, /*OpIdx*/2, // rx
17479 GIR_RootToRootCopy, /*OpIdx*/3, // ry
17480 GIR_RootConstrainSelectedInstOperands,
17481 // GIR_Coverage, 1872,
17482 GIR_EraseRootFromParent_Done,
17483 // Label 1084: @44336
17484 GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(44396), // Rule ID 2182 //
17485 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17486 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17487 // MIs[0] Operand 1
17488 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
17489 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17490 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17491 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17492 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17493 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
17494 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17495 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17496 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17497 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17498 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
17499 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17500 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17501 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17502 GIR_RootConstrainSelectedInstOperands,
17503 // GIR_Coverage, 2182,
17504 GIR_EraseRootFromParent_Done,
17505 // Label 1085: @44396
17506 GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(44459), // Rule ID 2183 //
17507 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17508 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17509 // MIs[0] Operand 1
17510 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
17511 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17512 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17513 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
17514 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17515 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
17516 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17517 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17518 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17519 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17520 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17521 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17522 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17523 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17524 GIR_RootConstrainSelectedInstOperands,
17525 // GIR_Coverage, 2183,
17526 GIR_EraseRootFromParent_Done,
17527 // Label 1086: @44459
17528 GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(44519), // Rule ID 2184 //
17529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17530 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17531 // MIs[0] Operand 1
17532 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
17533 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17534 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17535 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17536 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
17538 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17539 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17540 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17541 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17542 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
17543 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17544 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17545 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17546 GIR_RootConstrainSelectedInstOperands,
17547 // GIR_Coverage, 2184,
17548 GIR_EraseRootFromParent_Done,
17549 // Label 1087: @44519
17550 GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(44579), // Rule ID 2185 //
17551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17552 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17553 // MIs[0] Operand 1
17554 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
17555 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17556 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17557 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
17558 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17559 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17560 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17561 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17562 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17563 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17564 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
17565 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17566 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17567 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17568 GIR_RootConstrainSelectedInstOperands,
17569 // GIR_Coverage, 2185,
17570 GIR_EraseRootFromParent_Done,
17571 // Label 1088: @44579
17572 GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(44615), // Rule ID 2186 //
17573 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17574 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17575 // MIs[0] Operand 1
17576 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
17577 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17578 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17579 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17580 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
17581 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17582 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17583 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17584 GIR_RootConstrainSelectedInstOperands,
17585 // GIR_Coverage, 2186,
17586 GIR_EraseRootFromParent_Done,
17587 // Label 1089: @44615
17588 GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(44651), // Rule ID 2187 //
17589 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17590 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17591 // MIs[0] Operand 1
17592 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
17593 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17594 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17595 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
17596 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17597 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
17598 GIR_RootToRootCopy, /*OpIdx*/3, // rhs
17599 GIR_RootToRootCopy, /*OpIdx*/2, // lhs
17600 GIR_RootConstrainSelectedInstOperands,
17601 // GIR_Coverage, 2187,
17602 GIR_EraseRootFromParent_Done,
17603 // Label 1090: @44651
17604 GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(44711), // Rule ID 2188 //
17605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17606 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17607 // MIs[0] Operand 1
17608 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
17609 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17610 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17611 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17612 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17613 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
17614 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17615 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17616 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17617 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17618 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
17619 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17620 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17621 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17622 GIR_RootConstrainSelectedInstOperands,
17623 // GIR_Coverage, 2188,
17624 GIR_EraseRootFromParent_Done,
17625 // Label 1091: @44711
17626 GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(44771), // Rule ID 2189 //
17627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
17628 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17629 // MIs[0] Operand 1
17630 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
17631 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17632 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
17633 // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
17634 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17635 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
17636 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
17637 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
17638 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
17639 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
17640 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
17641 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
17642 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17643 GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
17644 GIR_RootConstrainSelectedInstOperands,
17645 // GIR_Coverage, 2189,
17646 GIR_EraseRootFromParent_Done,
17647 // Label 1092: @44771
17648 GIM_Reject,
17649 // Label 1074: @44772
17650 GIM_Reject,
17651 // Label 1028: @44773
17652 GIM_Reject,
17653 // Label 29: @44774
17654 GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(46479),
17655 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17656 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1096*/ GIMT_Encode4(45277),
17657 /*GILLT_s32*//*Label 1094*/ GIMT_Encode4(44801),
17658 /*GILLT_s64*//*Label 1095*/ GIMT_Encode4(45039),
17659 // Label 1094: @44801
17660 GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(45038),
17661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
17663 GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(44845), // Rule ID 312 //
17664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17665 // MIs[0] Operand 1
17666 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
17667 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17668 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17669 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17670 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
17671 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17672 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17673 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17674 GIR_RootConstrainSelectedInstOperands,
17675 // GIR_Coverage, 312,
17676 GIR_EraseRootFromParent_Done,
17677 // Label 1098: @44845
17678 GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(44877), // Rule ID 313 //
17679 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17680 // MIs[0] Operand 1
17681 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
17682 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17683 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17684 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17685 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
17686 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17687 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17688 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17689 GIR_RootConstrainSelectedInstOperands,
17690 // GIR_Coverage, 313,
17691 GIR_EraseRootFromParent_Done,
17692 // Label 1099: @44877
17693 GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(44909), // Rule ID 314 //
17694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17695 // MIs[0] Operand 1
17696 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
17697 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17698 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17699 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17700 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
17701 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17702 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17703 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17704 GIR_RootConstrainSelectedInstOperands,
17705 // GIR_Coverage, 314,
17706 GIR_EraseRootFromParent_Done,
17707 // Label 1100: @44909
17708 GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(44941), // Rule ID 315 //
17709 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17710 // MIs[0] Operand 1
17711 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
17712 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17713 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17714 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17715 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
17716 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17717 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17718 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17719 GIR_RootConstrainSelectedInstOperands,
17720 // GIR_Coverage, 315,
17721 GIR_EraseRootFromParent_Done,
17722 // Label 1101: @44941
17723 GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(44973), // Rule ID 316 //
17724 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17725 // MIs[0] Operand 1
17726 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
17727 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17728 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17729 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
17731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17732 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17733 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17734 GIR_RootConstrainSelectedInstOperands,
17735 // GIR_Coverage, 316,
17736 GIR_EraseRootFromParent_Done,
17737 // Label 1102: @44973
17738 GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(45005), // Rule ID 317 //
17739 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17740 // MIs[0] Operand 1
17741 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
17742 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17743 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17744 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17745 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
17746 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17747 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17748 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17749 GIR_RootConstrainSelectedInstOperands,
17750 // GIR_Coverage, 317,
17751 GIR_EraseRootFromParent_Done,
17752 // Label 1103: @45005
17753 GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(45037), // Rule ID 318 //
17754 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17755 // MIs[0] Operand 1
17756 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
17757 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17758 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17759 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17760 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
17761 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17762 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17763 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17764 GIR_RootConstrainSelectedInstOperands,
17765 // GIR_Coverage, 318,
17766 GIR_EraseRootFromParent_Done,
17767 // Label 1104: @45037
17768 GIM_Reject,
17769 // Label 1097: @45038
17770 GIM_Reject,
17771 // Label 1095: @45039
17772 GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(45276),
17773 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
17774 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
17775 GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(45083), // Rule ID 319 //
17776 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17777 // MIs[0] Operand 1
17778 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
17779 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17780 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17781 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17782 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
17783 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17784 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17785 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17786 GIR_RootConstrainSelectedInstOperands,
17787 // GIR_Coverage, 319,
17788 GIR_EraseRootFromParent_Done,
17789 // Label 1106: @45083
17790 GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(45115), // Rule ID 320 //
17791 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17792 // MIs[0] Operand 1
17793 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
17794 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17795 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17796 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17797 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
17798 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17799 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17800 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17801 GIR_RootConstrainSelectedInstOperands,
17802 // GIR_Coverage, 320,
17803 GIR_EraseRootFromParent_Done,
17804 // Label 1107: @45115
17805 GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(45147), // Rule ID 321 //
17806 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17807 // MIs[0] Operand 1
17808 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
17809 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17810 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17811 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17812 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
17813 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17814 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17815 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17816 GIR_RootConstrainSelectedInstOperands,
17817 // GIR_Coverage, 321,
17818 GIR_EraseRootFromParent_Done,
17819 // Label 1108: @45147
17820 GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(45179), // Rule ID 322 //
17821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17822 // MIs[0] Operand 1
17823 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
17824 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17825 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17826 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17827 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
17828 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17829 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17830 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17831 GIR_RootConstrainSelectedInstOperands,
17832 // GIR_Coverage, 322,
17833 GIR_EraseRootFromParent_Done,
17834 // Label 1109: @45179
17835 GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(45211), // Rule ID 323 //
17836 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17837 // MIs[0] Operand 1
17838 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
17839 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17840 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17841 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17842 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
17843 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17844 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17845 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17846 GIR_RootConstrainSelectedInstOperands,
17847 // GIR_Coverage, 323,
17848 GIR_EraseRootFromParent_Done,
17849 // Label 1110: @45211
17850 GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(45243), // Rule ID 324 //
17851 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17852 // MIs[0] Operand 1
17853 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
17854 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17855 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17856 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17857 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
17858 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17859 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17860 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17861 GIR_RootConstrainSelectedInstOperands,
17862 // GIR_Coverage, 324,
17863 GIR_EraseRootFromParent_Done,
17864 // Label 1111: @45243
17865 GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(45275), // Rule ID 325 //
17866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
17867 // MIs[0] Operand 1
17868 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
17869 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17870 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
17871 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
17872 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
17873 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17874 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17875 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17876 GIR_RootConstrainSelectedInstOperands,
17877 // GIR_Coverage, 325,
17878 GIR_EraseRootFromParent_Done,
17879 // Label 1112: @45275
17880 GIM_Reject,
17881 // Label 1105: @45276
17882 GIM_Reject,
17883 // Label 1096: @45277
17884 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1115*/ GIMT_Encode4(45772),
17885 /*GILLT_s32*//*Label 1113*/ GIMT_Encode4(45296),
17886 /*GILLT_s64*//*Label 1114*/ GIMT_Encode4(45534),
17887 // Label 1113: @45296
17888 GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(45533),
17889 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17890 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
17891 GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(45340), // Rule ID 1193 //
17892 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17893 // MIs[0] Operand 1
17894 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
17895 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17896 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17897 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17898 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
17899 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17900 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17901 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17902 GIR_RootConstrainSelectedInstOperands,
17903 // GIR_Coverage, 1193,
17904 GIR_EraseRootFromParent_Done,
17905 // Label 1117: @45340
17906 GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(45372), // Rule ID 1194 //
17907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17908 // MIs[0] Operand 1
17909 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
17910 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17911 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17912 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17913 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
17914 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17915 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17916 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17917 GIR_RootConstrainSelectedInstOperands,
17918 // GIR_Coverage, 1194,
17919 GIR_EraseRootFromParent_Done,
17920 // Label 1118: @45372
17921 GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(45404), // Rule ID 1195 //
17922 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17923 // MIs[0] Operand 1
17924 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
17925 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17926 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17927 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17928 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
17929 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17930 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17931 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17932 GIR_RootConstrainSelectedInstOperands,
17933 // GIR_Coverage, 1195,
17934 GIR_EraseRootFromParent_Done,
17935 // Label 1119: @45404
17936 GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(45436), // Rule ID 1196 //
17937 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17938 // MIs[0] Operand 1
17939 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
17940 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17941 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17942 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
17944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17945 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17946 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17947 GIR_RootConstrainSelectedInstOperands,
17948 // GIR_Coverage, 1196,
17949 GIR_EraseRootFromParent_Done,
17950 // Label 1120: @45436
17951 GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(45468), // Rule ID 1197 //
17952 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17953 // MIs[0] Operand 1
17954 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
17955 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17956 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17957 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17958 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
17959 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17960 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17961 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17962 GIR_RootConstrainSelectedInstOperands,
17963 // GIR_Coverage, 1197,
17964 GIR_EraseRootFromParent_Done,
17965 // Label 1121: @45468
17966 GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(45500), // Rule ID 1198 //
17967 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17968 // MIs[0] Operand 1
17969 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
17970 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17971 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17972 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17973 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
17974 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17975 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17976 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17977 GIR_RootConstrainSelectedInstOperands,
17978 // GIR_Coverage, 1198,
17979 GIR_EraseRootFromParent_Done,
17980 // Label 1122: @45500
17981 GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(45532), // Rule ID 1199 //
17982 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
17983 // MIs[0] Operand 1
17984 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
17985 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17986 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
17987 // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
17988 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
17989 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
17990 GIR_RootToRootCopy, /*OpIdx*/2, // fs
17991 GIR_RootToRootCopy, /*OpIdx*/3, // ft
17992 GIR_RootConstrainSelectedInstOperands,
17993 // GIR_Coverage, 1199,
17994 GIR_EraseRootFromParent_Done,
17995 // Label 1123: @45532
17996 GIM_Reject,
17997 // Label 1116: @45533
17998 GIM_Reject,
17999 // Label 1114: @45534
18000 GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(45771),
18001 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18002 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
18003 GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(45578), // Rule ID 1200 //
18004 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18005 // MIs[0] Operand 1
18006 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
18007 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18008 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18009 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18010 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
18011 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18012 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18013 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18014 GIR_RootConstrainSelectedInstOperands,
18015 // GIR_Coverage, 1200,
18016 GIR_EraseRootFromParent_Done,
18017 // Label 1125: @45578
18018 GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(45610), // Rule ID 1201 //
18019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18020 // MIs[0] Operand 1
18021 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
18022 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18023 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18024 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
18026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18027 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18028 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18029 GIR_RootConstrainSelectedInstOperands,
18030 // GIR_Coverage, 1201,
18031 GIR_EraseRootFromParent_Done,
18032 // Label 1126: @45610
18033 GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(45642), // Rule ID 1202 //
18034 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18035 // MIs[0] Operand 1
18036 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
18037 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18038 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18039 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18040 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
18041 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18042 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18043 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18044 GIR_RootConstrainSelectedInstOperands,
18045 // GIR_Coverage, 1202,
18046 GIR_EraseRootFromParent_Done,
18047 // Label 1127: @45642
18048 GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(45674), // Rule ID 1203 //
18049 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18050 // MIs[0] Operand 1
18051 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
18052 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18053 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18054 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18055 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
18056 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18057 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18058 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18059 GIR_RootConstrainSelectedInstOperands,
18060 // GIR_Coverage, 1203,
18061 GIR_EraseRootFromParent_Done,
18062 // Label 1128: @45674
18063 GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(45706), // Rule ID 1204 //
18064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18065 // MIs[0] Operand 1
18066 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
18067 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18068 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18069 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18070 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
18071 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18072 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18073 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18074 GIR_RootConstrainSelectedInstOperands,
18075 // GIR_Coverage, 1204,
18076 GIR_EraseRootFromParent_Done,
18077 // Label 1129: @45706
18078 GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(45738), // Rule ID 1205 //
18079 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18080 // MIs[0] Operand 1
18081 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
18082 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18083 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18084 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18085 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
18086 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18087 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18088 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18089 GIR_RootConstrainSelectedInstOperands,
18090 // GIR_Coverage, 1205,
18091 GIR_EraseRootFromParent_Done,
18092 // Label 1130: @45738
18093 GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(45770), // Rule ID 1206 //
18094 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
18095 // MIs[0] Operand 1
18096 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
18097 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18098 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
18099 // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
18100 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
18101 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18102 GIR_RootToRootCopy, /*OpIdx*/2, // fs
18103 GIR_RootToRootCopy, /*OpIdx*/3, // ft
18104 GIR_RootConstrainSelectedInstOperands,
18105 // GIR_Coverage, 1206,
18106 GIR_EraseRootFromParent_Done,
18107 // Label 1131: @45770
18108 GIM_Reject,
18109 // Label 1124: @45771
18110 GIM_Reject,
18111 // Label 1115: @45772
18112 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1134*/ GIMT_Encode4(46125),
18113 /*GILLT_s32*//*Label 1132*/ GIMT_Encode4(45791),
18114 /*GILLT_s64*//*Label 1133*/ GIMT_Encode4(45958),
18115 // Label 1132: @45791
18116 GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(45957),
18117 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18118 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18119 GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(45854), // Rule ID 1735 //
18120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
18121 // MIs[0] Operand 1
18122 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
18123 // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
18124 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18125 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
18126 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18127 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18128 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18129 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18130 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
18131 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18132 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18133 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18134 GIR_RootConstrainSelectedInstOperands,
18135 // GIR_Coverage, 1735,
18136 GIR_EraseRootFromParent_Done,
18137 // Label 1136: @45854
18138 GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(45905), // Rule ID 1736 //
18139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
18140 // MIs[0] Operand 1
18141 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
18142 // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
18143 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18144 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
18145 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18146 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18147 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18148 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18149 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
18150 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18151 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18152 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18153 GIR_RootConstrainSelectedInstOperands,
18154 // GIR_Coverage, 1736,
18155 GIR_EraseRootFromParent_Done,
18156 // Label 1137: @45905
18157 GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(45956), // Rule ID 1737 //
18158 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
18159 // MIs[0] Operand 1
18160 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
18161 // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
18162 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18163 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
18164 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18165 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18166 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18167 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18168 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
18169 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18170 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18171 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18172 GIR_RootConstrainSelectedInstOperands,
18173 // GIR_Coverage, 1737,
18174 GIR_EraseRootFromParent_Done,
18175 // Label 1138: @45956
18176 GIM_Reject,
18177 // Label 1135: @45957
18178 GIM_Reject,
18179 // Label 1133: @45958
18180 GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(46124),
18181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18182 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18183 GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(46021), // Rule ID 1744 //
18184 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
18185 // MIs[0] Operand 1
18186 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
18187 // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
18188 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18189 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
18190 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18191 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18192 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18193 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18194 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
18195 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18196 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18197 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18198 GIR_RootConstrainSelectedInstOperands,
18199 // GIR_Coverage, 1744,
18200 GIR_EraseRootFromParent_Done,
18201 // Label 1140: @46021
18202 GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(46072), // Rule ID 1745 //
18203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
18204 // MIs[0] Operand 1
18205 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
18206 // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
18207 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18208 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
18209 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18210 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18211 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18212 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18213 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
18214 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18215 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18216 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18217 GIR_RootConstrainSelectedInstOperands,
18218 // GIR_Coverage, 1745,
18219 GIR_EraseRootFromParent_Done,
18220 // Label 1141: @46072
18221 GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(46123), // Rule ID 1746 //
18222 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
18223 // MIs[0] Operand 1
18224 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
18225 // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
18226 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18227 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
18228 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18229 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18230 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18231 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
18233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18234 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18235 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18236 GIR_RootConstrainSelectedInstOperands,
18237 // GIR_Coverage, 1746,
18238 GIR_EraseRootFromParent_Done,
18239 // Label 1142: @46123
18240 GIM_Reject,
18241 // Label 1139: @46124
18242 GIM_Reject,
18243 // Label 1134: @46125
18244 GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1145*/ GIMT_Encode4(46478),
18245 /*GILLT_s32*//*Label 1143*/ GIMT_Encode4(46144),
18246 /*GILLT_s64*//*Label 1144*/ GIMT_Encode4(46311),
18247 // Label 1143: @46144
18248 GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(46310),
18249 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18250 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18251 GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(46207), // Rule ID 2281 //
18252 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
18253 // MIs[0] Operand 1
18254 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
18255 // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
18256 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18257 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
18258 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18259 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18260 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18261 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18262 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
18263 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18264 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18265 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18266 GIR_RootConstrainSelectedInstOperands,
18267 // GIR_Coverage, 2281,
18268 GIR_EraseRootFromParent_Done,
18269 // Label 1147: @46207
18270 GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(46258), // Rule ID 2282 //
18271 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
18272 // MIs[0] Operand 1
18273 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
18274 // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
18275 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18276 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
18277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18278 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18279 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18280 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18281 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
18282 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18283 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18284 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18285 GIR_RootConstrainSelectedInstOperands,
18286 // GIR_Coverage, 2282,
18287 GIR_EraseRootFromParent_Done,
18288 // Label 1148: @46258
18289 GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(46309), // Rule ID 2283 //
18290 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
18291 // MIs[0] Operand 1
18292 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
18293 // (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
18294 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18295 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
18296 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18297 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18298 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18299 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18300 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
18301 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18302 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18303 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18304 GIR_RootConstrainSelectedInstOperands,
18305 // GIR_Coverage, 2283,
18306 GIR_EraseRootFromParent_Done,
18307 // Label 1149: @46309
18308 GIM_Reject,
18309 // Label 1146: @46310
18310 GIM_Reject,
18311 // Label 1144: @46311
18312 GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(46477),
18313 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
18314 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18315 GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(46374), // Rule ID 2290 //
18316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
18317 // MIs[0] Operand 1
18318 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
18319 // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
18320 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18321 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
18322 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18323 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18324 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18325 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18326 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
18327 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18328 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18329 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18330 GIR_RootConstrainSelectedInstOperands,
18331 // GIR_Coverage, 2290,
18332 GIR_EraseRootFromParent_Done,
18333 // Label 1151: @46374
18334 GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(46425), // Rule ID 2291 //
18335 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
18336 // MIs[0] Operand 1
18337 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
18338 // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
18339 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18340 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
18341 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18342 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18343 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18344 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18345 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
18346 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18347 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18348 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18349 GIR_RootConstrainSelectedInstOperands,
18350 // GIR_Coverage, 2291,
18351 GIR_EraseRootFromParent_Done,
18352 // Label 1152: @46425
18353 GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(46476), // Rule ID 2292 //
18354 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
18355 // MIs[0] Operand 1
18356 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
18357 // (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
18358 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18359 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
18360 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18361 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
18362 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
18363 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18364 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
18365 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18366 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18367 GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18368 GIR_RootConstrainSelectedInstOperands,
18369 // GIR_Coverage, 2292,
18370 GIR_EraseRootFromParent_Done,
18371 // Label 1153: @46476
18372 GIM_Reject,
18373 // Label 1150: @46477
18374 GIM_Reject,
18375 // Label 1145: @46478
18376 GIM_Reject,
18377 // Label 1093: @46479
18378 GIM_Reject,
18379 // Label 30: @46480
18380 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1160*/ GIMT_Encode4(58517),
18381 /*GILLT_s32*//*Label 1154*/ GIMT_Encode4(46523),
18382 /*GILLT_s64*//*Label 1155*/ GIMT_Encode4(53200), GIMT_Encode4(0),
18383 /*GILLT_v2s64*//*Label 1156*/ GIMT_Encode4(58227), GIMT_Encode4(0),
18384 /*GILLT_v4s32*//*Label 1157*/ GIMT_Encode4(58301),
18385 /*GILLT_v8s16*//*Label 1158*/ GIMT_Encode4(58375),
18386 /*GILLT_v16s8*//*Label 1159*/ GIMT_Encode4(58422),
18387 // Label 1154: @46523
18388 GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(46599), // Rule ID 1623 //
18389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18390 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18391 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18392 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18393 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18394 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18395 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18396 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18397 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18398 // MIs[1] Operand 1
18399 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18400 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18401 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18402 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18403 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18404 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18405 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18406 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18407 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18408 GIR_RootToRootCopy, /*OpIdx*/2, // T
18409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18410 GIR_RootToRootCopy, /*OpIdx*/3, // F
18411 GIR_RootConstrainSelectedInstOperands,
18412 // GIR_Coverage, 1623,
18413 GIR_EraseRootFromParent_Done,
18414 // Label 1161: @46599
18415 GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(46675), // Rule ID 1627 //
18416 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18417 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18418 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18419 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18420 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18421 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18422 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18423 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18424 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18425 // MIs[1] Operand 1
18426 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18427 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18428 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18429 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18430 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18431 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18432 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18433 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
18434 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18435 GIR_RootToRootCopy, /*OpIdx*/2, // T
18436 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18437 GIR_RootToRootCopy, /*OpIdx*/3, // F
18438 GIR_RootConstrainSelectedInstOperands,
18439 // GIR_Coverage, 1627,
18440 GIR_EraseRootFromParent_Done,
18441 // Label 1162: @46675
18442 GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(46751), // Rule ID 1655 //
18443 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
18444 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18445 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18446 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18448 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18449 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18450 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18451 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18452 // MIs[1] Operand 1
18453 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18454 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18455 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18456 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18457 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18458 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18459 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
18460 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
18461 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18462 GIR_RootToRootCopy, /*OpIdx*/2, // T
18463 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18464 GIR_RootToRootCopy, /*OpIdx*/3, // F
18465 GIR_RootConstrainSelectedInstOperands,
18466 // GIR_Coverage, 1655,
18467 GIR_EraseRootFromParent_Done,
18468 // Label 1163: @46751
18469 GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(46827), // Rule ID 1666 //
18470 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
18471 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18472 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18473 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18474 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18475 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18476 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18477 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18478 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18479 // MIs[1] Operand 1
18480 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18481 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18482 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18483 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18484 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18485 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18486 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
18487 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
18488 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18489 GIR_RootToRootCopy, /*OpIdx*/2, // T
18490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18491 GIR_RootToRootCopy, /*OpIdx*/3, // F
18492 GIR_RootConstrainSelectedInstOperands,
18493 // GIR_Coverage, 1666,
18494 GIR_EraseRootFromParent_Done,
18495 // Label 1164: @46827
18496 GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(46903), // Rule ID 1679 //
18497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18498 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18499 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18500 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18502 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18503 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18504 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18505 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18506 // MIs[1] Operand 1
18507 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18508 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18509 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18510 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18511 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18512 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18513 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
18514 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
18515 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18516 GIR_RootToRootCopy, /*OpIdx*/2, // T
18517 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18518 GIR_RootToRootCopy, /*OpIdx*/3, // F
18519 GIR_RootConstrainSelectedInstOperands,
18520 // GIR_Coverage, 1679,
18521 GIR_EraseRootFromParent_Done,
18522 // Label 1165: @46903
18523 GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(46979), // Rule ID 1682 //
18524 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18525 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18526 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18527 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18528 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18529 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18530 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18531 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18532 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18533 // MIs[1] Operand 1
18534 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18535 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18536 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18537 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18538 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18539 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18540 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
18541 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
18542 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18543 GIR_RootToRootCopy, /*OpIdx*/2, // T
18544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18545 GIR_RootToRootCopy, /*OpIdx*/3, // F
18546 GIR_RootConstrainSelectedInstOperands,
18547 // GIR_Coverage, 1682,
18548 GIR_EraseRootFromParent_Done,
18549 // Label 1166: @46979
18550 GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(47055), // Rule ID 1692 //
18551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
18552 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18553 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18554 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18556 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18557 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18558 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18559 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18560 // MIs[1] Operand 1
18561 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18562 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18563 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18564 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18565 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18566 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18567 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
18568 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
18569 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18570 GIR_RootToRootCopy, /*OpIdx*/2, // T
18571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18572 GIR_RootToRootCopy, /*OpIdx*/3, // F
18573 GIR_RootConstrainSelectedInstOperands,
18574 // GIR_Coverage, 1692,
18575 GIR_EraseRootFromParent_Done,
18576 // Label 1167: @47055
18577 GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(47131), // Rule ID 1695 //
18578 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
18579 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18580 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18581 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18582 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18583 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18584 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18585 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
18586 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
18587 // MIs[1] Operand 1
18588 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
18590 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18591 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18592 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18593 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18594 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
18595 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
18596 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18597 GIR_RootToRootCopy, /*OpIdx*/2, // T
18598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18599 GIR_RootToRootCopy, /*OpIdx*/3, // F
18600 GIR_RootConstrainSelectedInstOperands,
18601 // GIR_Coverage, 1695,
18602 GIR_EraseRootFromParent_Done,
18603 // Label 1168: @47131
18604 GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(47207), // Rule ID 1854 //
18605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18606 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18607 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18608 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18611 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18612 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18613 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18614 // MIs[1] Operand 1
18615 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18616 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18617 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18618 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18619 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18620 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18621 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
18622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
18623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
18624 GIR_RootToRootCopy, /*OpIdx*/2, // x
18625 GIR_RootToRootCopy, /*OpIdx*/3, // y
18626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18627 GIR_RootConstrainSelectedInstOperands,
18628 // GIR_Coverage, 1854,
18629 GIR_EraseRootFromParent_Done,
18630 // Label 1169: @47207
18631 GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(47283), // Rule ID 1857 //
18632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
18633 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18635 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18636 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18637 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18638 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18639 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18640 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18641 // MIs[1] Operand 1
18642 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18643 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18644 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18645 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18646 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
18647 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18648 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
18649 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
18650 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
18651 GIR_RootToRootCopy, /*OpIdx*/2, // x
18652 GIR_RootToRootCopy, /*OpIdx*/3, // y
18653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
18654 GIR_RootConstrainSelectedInstOperands,
18655 // GIR_Coverage, 1857,
18656 GIR_EraseRootFromParent_Done,
18657 // Label 1170: @47283
18658 GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(47359), // Rule ID 2201 //
18659 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
18660 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18661 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18662 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18663 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18664 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18665 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18666 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18667 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18668 // MIs[1] Operand 1
18669 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18670 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18671 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18672 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18673 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18674 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18675 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18676 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
18677 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18678 GIR_RootToRootCopy, /*OpIdx*/2, // T
18679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18680 GIR_RootToRootCopy, /*OpIdx*/3, // F
18681 GIR_RootConstrainSelectedInstOperands,
18682 // GIR_Coverage, 2201,
18683 GIR_EraseRootFromParent_Done,
18684 // Label 1171: @47359
18685 GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(47435), // Rule ID 2205 //
18686 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
18687 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18688 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18689 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18690 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18691 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18692 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18693 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18694 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18695 // MIs[1] Operand 1
18696 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18697 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18698 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18699 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18700 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18701 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18702 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18703 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
18704 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18705 GIR_RootToRootCopy, /*OpIdx*/2, // T
18706 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18707 GIR_RootToRootCopy, /*OpIdx*/3, // F
18708 GIR_RootConstrainSelectedInstOperands,
18709 // GIR_Coverage, 2205,
18710 GIR_EraseRootFromParent_Done,
18711 // Label 1172: @47435
18712 GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(47511), // Rule ID 2215 //
18713 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
18714 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18715 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18716 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18717 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18718 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18719 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18720 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18721 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18722 // MIs[1] Operand 1
18723 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18724 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18725 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18726 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18727 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18728 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18729 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18730 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
18731 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18732 GIR_RootToRootCopy, /*OpIdx*/2, // T
18733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18734 GIR_RootToRootCopy, /*OpIdx*/3, // F
18735 GIR_RootConstrainSelectedInstOperands,
18736 // GIR_Coverage, 2215,
18737 GIR_EraseRootFromParent_Done,
18738 // Label 1173: @47511
18739 GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(47587), // Rule ID 2219 //
18740 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
18741 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18742 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18743 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18744 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18745 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18746 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18747 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18748 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18749 // MIs[1] Operand 1
18750 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18751 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18752 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18753 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18754 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18755 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18756 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
18757 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
18758 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18759 GIR_RootToRootCopy, /*OpIdx*/2, // T
18760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18761 GIR_RootToRootCopy, /*OpIdx*/3, // F
18762 GIR_RootConstrainSelectedInstOperands,
18763 // GIR_Coverage, 2219,
18764 GIR_EraseRootFromParent_Done,
18765 // Label 1174: @47587
18766 GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(47663), // Rule ID 2249 //
18767 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
18768 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18769 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18770 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18771 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18773 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18774 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18775 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18776 // MIs[1] Operand 1
18777 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18778 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18779 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18780 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18781 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18782 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18783 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
18784 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
18785 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18786 GIR_RootToRootCopy, /*OpIdx*/2, // T
18787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18788 GIR_RootToRootCopy, /*OpIdx*/3, // F
18789 GIR_RootConstrainSelectedInstOperands,
18790 // GIR_Coverage, 2249,
18791 GIR_EraseRootFromParent_Done,
18792 // Label 1175: @47663
18793 GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(47739), // Rule ID 2252 //
18794 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
18795 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18796 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18797 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18798 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18800 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18801 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18802 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18803 // MIs[1] Operand 1
18804 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18805 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18806 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
18807 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18808 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
18809 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18810 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
18811 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
18812 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
18813 GIR_RootToRootCopy, /*OpIdx*/2, // T
18814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18815 GIR_RootToRootCopy, /*OpIdx*/3, // F
18816 GIR_RootConstrainSelectedInstOperands,
18817 // GIR_Coverage, 2252,
18818 GIR_EraseRootFromParent_Done,
18819 // Label 1176: @47739
18820 GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(47837), // Rule ID 1614 //
18821 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18822 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18823 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18824 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18825 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18826 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18827 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18828 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18829 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18830 // MIs[1] Operand 1
18831 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
18832 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18833 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18834 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18835 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18836 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18837 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18838 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18839 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18840 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18841 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18842 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18843 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18844 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18845 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18846 GIR_RootToRootCopy, /*OpIdx*/2, // T
18847 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18848 GIR_RootToRootCopy, /*OpIdx*/3, // F
18849 GIR_RootConstrainSelectedInstOperands,
18850 // GIR_Coverage, 1614,
18851 GIR_EraseRootFromParent_Done,
18852 // Label 1177: @47837
18853 GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(47935), // Rule ID 1615 //
18854 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18855 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18856 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18857 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18858 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18859 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18860 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18861 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18862 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18863 // MIs[1] Operand 1
18864 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
18865 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18866 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18867 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18868 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18869 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18870 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18871 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18872 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18873 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18874 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18875 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18876 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18877 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18878 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18879 GIR_RootToRootCopy, /*OpIdx*/2, // T
18880 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18881 GIR_RootToRootCopy, /*OpIdx*/3, // F
18882 GIR_RootConstrainSelectedInstOperands,
18883 // GIR_Coverage, 1615,
18884 GIR_EraseRootFromParent_Done,
18885 // Label 1178: @47935
18886 GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(48033), // Rule ID 1618 //
18887 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18888 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18889 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18890 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18891 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18892 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18893 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18894 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18895 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18896 // MIs[1] Operand 1
18897 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
18898 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18899 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18900 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18901 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18902 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18903 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
18904 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18905 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
18906 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18907 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18908 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18909 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18910 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18911 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18912 GIR_RootToRootCopy, /*OpIdx*/2, // T
18913 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18914 GIR_RootToRootCopy, /*OpIdx*/3, // F
18915 GIR_RootConstrainSelectedInstOperands,
18916 // GIR_Coverage, 1618,
18917 GIR_EraseRootFromParent_Done,
18918 // Label 1179: @48033
18919 GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(48131), // Rule ID 1619 //
18920 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18921 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18922 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18923 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18924 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18925 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18926 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18927 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18928 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18929 // MIs[1] Operand 1
18930 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
18931 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18932 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18933 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18934 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18935 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18936 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
18937 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18938 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
18939 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18940 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18941 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18942 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18943 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18944 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18945 GIR_RootToRootCopy, /*OpIdx*/2, // T
18946 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18947 GIR_RootToRootCopy, /*OpIdx*/3, // F
18948 GIR_RootConstrainSelectedInstOperands,
18949 // GIR_Coverage, 1619,
18950 GIR_EraseRootFromParent_Done,
18951 // Label 1180: @48131
18952 GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(48229), // Rule ID 1622 //
18953 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18954 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18955 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18956 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18957 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18959 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18960 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18961 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18962 // MIs[1] Operand 1
18963 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
18964 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18965 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18966 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18967 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18968 GIM_CheckIsSafeToFold, /*NumInsns*/1,
18969 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
18970 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
18971 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
18972 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
18973 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
18974 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
18975 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
18976 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
18977 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
18978 GIR_RootToRootCopy, /*OpIdx*/2, // T
18979 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18980 GIR_RootToRootCopy, /*OpIdx*/3, // F
18981 GIR_RootConstrainSelectedInstOperands,
18982 // GIR_Coverage, 1622,
18983 GIR_EraseRootFromParent_Done,
18984 // Label 1181: @48229
18985 GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(48327), // Rule ID 1625 //
18986 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
18987 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
18988 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18989 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18990 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
18992 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
18993 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
18994 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
18995 // MIs[1] Operand 1
18996 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
18997 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18998 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
18999 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19000 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19001 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19002 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19003 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19004 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19005 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19006 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19007 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19008 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19009 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
19010 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19011 GIR_RootToRootCopy, /*OpIdx*/2, // T
19012 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19013 GIR_RootToRootCopy, /*OpIdx*/3, // F
19014 GIR_RootConstrainSelectedInstOperands,
19015 // GIR_Coverage, 1625,
19016 GIR_EraseRootFromParent_Done,
19017 // Label 1182: @48327
19018 GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(48425), // Rule ID 1636 //
19019 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19020 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19021 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19022 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19023 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19024 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19025 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19026 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19027 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19028 // MIs[1] Operand 1
19029 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19030 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19031 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19032 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19033 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19034 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19035 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19036 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19037 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19038 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19039 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19040 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19041 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19042 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19043 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19044 GIR_RootToRootCopy, /*OpIdx*/2, // T
19045 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19046 GIR_RootToRootCopy, /*OpIdx*/3, // F
19047 GIR_RootConstrainSelectedInstOperands,
19048 // GIR_Coverage, 1636,
19049 GIR_EraseRootFromParent_Done,
19050 // Label 1183: @48425
19051 GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(48523), // Rule ID 1637 //
19052 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19053 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19054 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19055 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19056 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19057 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19058 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19059 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19060 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19061 // MIs[1] Operand 1
19062 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19064 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19065 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19066 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19067 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19068 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19069 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19070 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19071 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19072 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19073 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19074 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19077 GIR_RootToRootCopy, /*OpIdx*/2, // T
19078 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19079 GIR_RootToRootCopy, /*OpIdx*/3, // F
19080 GIR_RootConstrainSelectedInstOperands,
19081 // GIR_Coverage, 1637,
19082 GIR_EraseRootFromParent_Done,
19083 // Label 1184: @48523
19084 GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(48621), // Rule ID 1640 //
19085 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19086 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19087 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19088 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19089 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19090 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19091 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19092 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19093 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19094 // MIs[1] Operand 1
19095 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19096 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19097 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19098 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19099 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19100 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19101 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
19102 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19103 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19104 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19105 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19106 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19107 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19108 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19109 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19110 GIR_RootToRootCopy, /*OpIdx*/2, // T
19111 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19112 GIR_RootToRootCopy, /*OpIdx*/3, // F
19113 GIR_RootConstrainSelectedInstOperands,
19114 // GIR_Coverage, 1640,
19115 GIR_EraseRootFromParent_Done,
19116 // Label 1185: @48621
19117 GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(48719), // Rule ID 1641 //
19118 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19119 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19120 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19121 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19122 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19123 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19124 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19125 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19126 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19127 // MIs[1] Operand 1
19128 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19129 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19130 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19131 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19132 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19133 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19134 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
19135 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19137 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19138 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19139 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19140 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19141 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
19142 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19143 GIR_RootToRootCopy, /*OpIdx*/2, // T
19144 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19145 GIR_RootToRootCopy, /*OpIdx*/3, // F
19146 GIR_RootConstrainSelectedInstOperands,
19147 // GIR_Coverage, 1641,
19148 GIR_EraseRootFromParent_Done,
19149 // Label 1186: @48719
19150 GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(48817), // Rule ID 1654 //
19151 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19152 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19153 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19154 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19155 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19156 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19157 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19158 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19159 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19160 // MIs[1] Operand 1
19161 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19162 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19163 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19164 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19165 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19166 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19167 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19168 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19169 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19170 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19171 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19172 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19173 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19174 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
19175 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19176 GIR_RootToRootCopy, /*OpIdx*/2, // T
19177 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19178 GIR_RootToRootCopy, /*OpIdx*/3, // F
19179 GIR_RootConstrainSelectedInstOperands,
19180 // GIR_Coverage, 1654,
19181 GIR_EraseRootFromParent_Done,
19182 // Label 1187: @48817
19183 GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(48915), // Rule ID 1664 //
19184 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19185 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19186 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19187 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19188 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19189 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19190 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19191 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19192 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19193 // MIs[1] Operand 1
19194 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19195 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19196 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19197 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19198 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19199 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19200 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
19201 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19202 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19203 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19204 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19205 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19206 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19207 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
19208 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19209 GIR_RootToRootCopy, /*OpIdx*/2, // T
19210 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19211 GIR_RootToRootCopy, /*OpIdx*/3, // F
19212 GIR_RootConstrainSelectedInstOperands,
19213 // GIR_Coverage, 1664,
19214 GIR_EraseRootFromParent_Done,
19215 // Label 1188: @48915
19216 GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(49013), // Rule ID 1670 //
19217 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19218 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19220 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19221 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19222 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19223 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19224 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19225 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19226 // MIs[1] Operand 1
19227 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19228 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19230 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19231 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19232 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19233 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19234 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19235 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19236 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19237 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19238 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19239 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19240 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19241 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19242 GIR_RootToRootCopy, /*OpIdx*/2, // T
19243 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19244 GIR_RootToRootCopy, /*OpIdx*/3, // F
19245 GIR_RootConstrainSelectedInstOperands,
19246 // GIR_Coverage, 1670,
19247 GIR_EraseRootFromParent_Done,
19248 // Label 1189: @49013
19249 GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(49111), // Rule ID 1671 //
19250 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19251 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19252 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19253 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19254 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19255 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19256 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19257 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19258 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19259 // MIs[1] Operand 1
19260 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19261 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19262 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19263 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19264 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19265 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19266 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19267 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19268 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19269 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19270 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19271 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19272 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19275 GIR_RootToRootCopy, /*OpIdx*/2, // T
19276 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19277 GIR_RootToRootCopy, /*OpIdx*/3, // F
19278 GIR_RootConstrainSelectedInstOperands,
19279 // GIR_Coverage, 1671,
19280 GIR_EraseRootFromParent_Done,
19281 // Label 1190: @49111
19282 GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(49209), // Rule ID 1674 //
19283 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19284 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19285 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19286 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19288 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19289 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19290 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19291 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19292 // MIs[1] Operand 1
19293 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19294 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19295 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19296 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19297 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19298 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19299 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19300 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19301 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
19302 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19303 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19304 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19305 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19306 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19307 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19308 GIR_RootToRootCopy, /*OpIdx*/2, // T
19309 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19310 GIR_RootToRootCopy, /*OpIdx*/3, // F
19311 GIR_RootConstrainSelectedInstOperands,
19312 // GIR_Coverage, 1674,
19313 GIR_EraseRootFromParent_Done,
19314 // Label 1191: @49209
19315 GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(49307), // Rule ID 1675 //
19316 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19317 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19318 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19319 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19320 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19321 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19322 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19323 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19324 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19325 // MIs[1] Operand 1
19326 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19327 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19328 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19329 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19330 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19331 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19332 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
19333 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19334 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
19335 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19336 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19337 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19338 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19341 GIR_RootToRootCopy, /*OpIdx*/2, // T
19342 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19343 GIR_RootToRootCopy, /*OpIdx*/3, // F
19344 GIR_RootConstrainSelectedInstOperands,
19345 // GIR_Coverage, 1675,
19346 GIR_EraseRootFromParent_Done,
19347 // Label 1192: @49307
19348 GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(49405), // Rule ID 1678 //
19349 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19350 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19351 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19352 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19354 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19355 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19356 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19357 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19358 // MIs[1] Operand 1
19359 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19360 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19361 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19362 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19363 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19364 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19365 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19366 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19367 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19368 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19369 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19370 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19371 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19372 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19373 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19374 GIR_RootToRootCopy, /*OpIdx*/2, // T
19375 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19376 GIR_RootToRootCopy, /*OpIdx*/3, // F
19377 GIR_RootConstrainSelectedInstOperands,
19378 // GIR_Coverage, 1678,
19379 GIR_EraseRootFromParent_Done,
19380 // Label 1193: @49405
19381 GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(49503), // Rule ID 1680 //
19382 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
19383 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19384 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19385 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19386 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19387 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19388 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19389 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19390 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19391 // MIs[1] Operand 1
19392 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19393 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19394 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19395 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19396 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19397 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19398 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
19399 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19400 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
19401 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19402 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19403 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19404 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19405 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
19406 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19407 GIR_RootToRootCopy, /*OpIdx*/2, // T
19408 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19409 GIR_RootToRootCopy, /*OpIdx*/3, // F
19410 GIR_RootConstrainSelectedInstOperands,
19411 // GIR_Coverage, 1680,
19412 GIR_EraseRootFromParent_Done,
19413 // Label 1194: @49503
19414 GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(49601), // Rule ID 1683 //
19415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19416 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19417 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19418 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19419 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19420 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19421 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19422 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19423 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19424 // MIs[1] Operand 1
19425 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19426 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19427 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19428 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19429 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19430 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19431 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19432 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19433 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19434 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19435 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19436 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19437 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19438 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19439 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19440 GIR_RootToRootCopy, /*OpIdx*/2, // T
19441 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19442 GIR_RootToRootCopy, /*OpIdx*/3, // F
19443 GIR_RootConstrainSelectedInstOperands,
19444 // GIR_Coverage, 1683,
19445 GIR_EraseRootFromParent_Done,
19446 // Label 1195: @49601
19447 GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(49699), // Rule ID 1684 //
19448 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19449 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19450 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19451 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19453 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19454 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19455 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19456 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19457 // MIs[1] Operand 1
19458 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19459 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19460 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19461 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19462 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19463 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19464 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19465 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19466 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19467 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19468 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19469 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19470 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19471 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19472 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19473 GIR_RootToRootCopy, /*OpIdx*/2, // T
19474 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19475 GIR_RootToRootCopy, /*OpIdx*/3, // F
19476 GIR_RootConstrainSelectedInstOperands,
19477 // GIR_Coverage, 1684,
19478 GIR_EraseRootFromParent_Done,
19479 // Label 1196: @49699
19480 GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(49797), // Rule ID 1687 //
19481 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19482 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19483 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19484 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19485 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19486 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19487 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19488 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19489 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19490 // MIs[1] Operand 1
19491 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19492 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19493 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19494 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19495 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19496 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19497 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
19498 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19499 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
19500 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19501 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19502 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19503 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19504 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19505 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19506 GIR_RootToRootCopy, /*OpIdx*/2, // T
19507 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19508 GIR_RootToRootCopy, /*OpIdx*/3, // F
19509 GIR_RootConstrainSelectedInstOperands,
19510 // GIR_Coverage, 1687,
19511 GIR_EraseRootFromParent_Done,
19512 // Label 1197: @49797
19513 GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(49895), // Rule ID 1688 //
19514 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19515 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19516 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19517 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19518 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19519 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19520 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19521 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19522 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19523 // MIs[1] Operand 1
19524 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19525 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19526 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19527 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19528 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19529 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19530 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
19531 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19532 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
19533 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19534 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19535 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19536 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19537 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
19538 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19539 GIR_RootToRootCopy, /*OpIdx*/2, // T
19540 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19541 GIR_RootToRootCopy, /*OpIdx*/3, // F
19542 GIR_RootConstrainSelectedInstOperands,
19543 // GIR_Coverage, 1688,
19544 GIR_EraseRootFromParent_Done,
19545 // Label 1198: @49895
19546 GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(49993), // Rule ID 1691 //
19547 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19548 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19549 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19550 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19551 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19552 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19553 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19554 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19555 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19556 // MIs[1] Operand 1
19557 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19558 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19559 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19560 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19561 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19562 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19563 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19564 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19565 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19566 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19567 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19568 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19569 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19570 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
19571 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19572 GIR_RootToRootCopy, /*OpIdx*/2, // T
19573 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19574 GIR_RootToRootCopy, /*OpIdx*/3, // F
19575 GIR_RootConstrainSelectedInstOperands,
19576 // GIR_Coverage, 1691,
19577 GIR_EraseRootFromParent_Done,
19578 // Label 1199: @49993
19579 GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(50091), // Rule ID 1693 //
19580 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
19581 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19582 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19583 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19584 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19586 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19587 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
19588 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
19589 // MIs[1] Operand 1
19590 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19591 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19592 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
19593 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19594 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
19595 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19596 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
19597 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
19598 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
19599 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19600 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19601 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19602 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
19604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
19605 GIR_RootToRootCopy, /*OpIdx*/2, // T
19606 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19607 GIR_RootToRootCopy, /*OpIdx*/3, // F
19608 GIR_RootConstrainSelectedInstOperands,
19609 // GIR_Coverage, 1693,
19610 GIR_EraseRootFromParent_Done,
19611 // Label 1200: @50091
19612 GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(50172), // Rule ID 1846 //
19613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19614 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19615 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19616 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19618 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19619 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19620 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19621 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19622 // MIs[1] Operand 1
19623 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19624 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19625 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19626 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19627 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19628 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19629 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
19630 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
19631 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19632 GIR_RootToRootCopy, /*OpIdx*/2, // x
19633 GIR_RootToRootCopy, /*OpIdx*/3, // y
19634 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19636 GIR_RootConstrainSelectedInstOperands,
19637 // GIR_Coverage, 1846,
19638 GIR_EraseRootFromParent_Done,
19639 // Label 1201: @50172
19640 GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(50253), // Rule ID 1847 //
19641 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19642 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19643 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19644 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19645 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19646 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19647 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19648 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19649 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19650 // MIs[1] Operand 1
19651 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
19652 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19653 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19654 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19655 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19656 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19657 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19658 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
19659 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19660 GIR_RootToRootCopy, /*OpIdx*/2, // x
19661 GIR_RootToRootCopy, /*OpIdx*/3, // y
19662 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19664 GIR_RootConstrainSelectedInstOperands,
19665 // GIR_Coverage, 1847,
19666 GIR_EraseRootFromParent_Done,
19667 // Label 1202: @50253
19668 GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(50334), // Rule ID 1848 //
19669 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19670 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19671 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19672 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19673 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19674 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19675 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19676 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19677 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19678 // MIs[1] Operand 1
19679 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19680 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19681 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19682 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19683 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19684 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19685 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
19686 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
19687 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19688 GIR_RootToRootCopy, /*OpIdx*/2, // x
19689 GIR_RootToRootCopy, /*OpIdx*/3, // y
19690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19692 GIR_RootConstrainSelectedInstOperands,
19693 // GIR_Coverage, 1848,
19694 GIR_EraseRootFromParent_Done,
19695 // Label 1203: @50334
19696 GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(50415), // Rule ID 1849 //
19697 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19698 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19700 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19701 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19702 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19703 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19704 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19705 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19706 // MIs[1] Operand 1
19707 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
19708 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19709 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19710 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19711 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19712 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19713 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
19715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19716 GIR_RootToRootCopy, /*OpIdx*/2, // x
19717 GIR_RootToRootCopy, /*OpIdx*/3, // y
19718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19719 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19720 GIR_RootConstrainSelectedInstOperands,
19721 // GIR_Coverage, 1849,
19722 GIR_EraseRootFromParent_Done,
19723 // Label 1204: @50415
19724 GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(50496), // Rule ID 1851 //
19725 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19726 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19727 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19728 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19729 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19731 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19732 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19733 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19734 // MIs[1] Operand 1
19735 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19736 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19737 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19738 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19739 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19740 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19741 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19742 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
19743 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19744 GIR_RootToRootCopy, /*OpIdx*/2, // x
19745 GIR_RootToRootCopy, /*OpIdx*/3, // y
19746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19747 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19748 GIR_RootConstrainSelectedInstOperands,
19749 // GIR_Coverage, 1851,
19750 GIR_EraseRootFromParent_Done,
19751 // Label 1205: @50496
19752 GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(50577), // Rule ID 1852 //
19753 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19754 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19755 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19756 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19757 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19758 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19759 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19760 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19761 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19762 // MIs[1] Operand 1
19763 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19764 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19765 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19766 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19767 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19768 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19769 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19770 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
19771 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19772 GIR_RootToRootCopy, /*OpIdx*/2, // x
19773 GIR_RootToRootCopy, /*OpIdx*/3, // y
19774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19776 GIR_RootConstrainSelectedInstOperands,
19777 // GIR_Coverage, 1852,
19778 GIR_EraseRootFromParent_Done,
19779 // Label 1206: @50577
19780 GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(50658), // Rule ID 1853 //
19781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19782 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19783 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19784 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19785 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19786 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19787 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19788 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19789 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19790 // MIs[1] Operand 1
19791 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19792 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19793 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19794 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19795 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19796 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19797 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19798 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
19799 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19800 GIR_RootToRootCopy, /*OpIdx*/2, // x
19801 GIR_RootToRootCopy, /*OpIdx*/3, // y
19802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19804 GIR_RootConstrainSelectedInstOperands,
19805 // GIR_Coverage, 1853,
19806 GIR_EraseRootFromParent_Done,
19807 // Label 1207: @50658
19808 GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(50739), // Rule ID 1856 //
19809 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
19810 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19811 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19812 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19814 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19815 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19816 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19817 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19818 // MIs[1] Operand 1
19819 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
19820 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19822 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19823 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
19824 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19825 // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
19826 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
19827 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
19828 GIR_RootToRootCopy, /*OpIdx*/2, // x
19829 GIR_RootToRootCopy, /*OpIdx*/3, // y
19830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
19831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
19832 GIR_RootConstrainSelectedInstOperands,
19833 // GIR_Coverage, 1856,
19834 GIR_EraseRootFromParent_Done,
19835 // Label 1208: @50739
19836 GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(50837), // Rule ID 2192 //
19837 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19838 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19839 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19840 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19841 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19842 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19843 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19844 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19845 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19846 // MIs[1] Operand 1
19847 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
19848 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19849 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19850 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19851 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19852 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19853 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19854 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19855 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19856 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19857 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19858 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19859 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19860 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19861 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19862 GIR_RootToRootCopy, /*OpIdx*/2, // T
19863 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19864 GIR_RootToRootCopy, /*OpIdx*/3, // F
19865 GIR_RootConstrainSelectedInstOperands,
19866 // GIR_Coverage, 2192,
19867 GIR_EraseRootFromParent_Done,
19868 // Label 1209: @50837
19869 GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(50935), // Rule ID 2193 //
19870 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19871 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19872 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19873 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19874 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19876 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19877 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19878 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19879 // MIs[1] Operand 1
19880 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
19881 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19882 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19883 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19884 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19885 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19886 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19887 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19888 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19889 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19890 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19891 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19892 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19893 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19894 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19895 GIR_RootToRootCopy, /*OpIdx*/2, // T
19896 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19897 GIR_RootToRootCopy, /*OpIdx*/3, // F
19898 GIR_RootConstrainSelectedInstOperands,
19899 // GIR_Coverage, 2193,
19900 GIR_EraseRootFromParent_Done,
19901 // Label 1210: @50935
19902 GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(51033), // Rule ID 2196 //
19903 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19904 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19905 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19906 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19907 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19908 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19909 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19910 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19911 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19912 // MIs[1] Operand 1
19913 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
19914 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19915 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19916 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19917 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19918 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19919 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19920 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19921 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
19922 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19923 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19924 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19925 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19926 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19927 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19928 GIR_RootToRootCopy, /*OpIdx*/2, // T
19929 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19930 GIR_RootToRootCopy, /*OpIdx*/3, // F
19931 GIR_RootConstrainSelectedInstOperands,
19932 // GIR_Coverage, 2196,
19933 GIR_EraseRootFromParent_Done,
19934 // Label 1211: @51033
19935 GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(51131), // Rule ID 2197 //
19936 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19937 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19938 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19939 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19940 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19941 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19942 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19943 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19944 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19945 // MIs[1] Operand 1
19946 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
19947 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19948 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19949 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19950 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19951 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19952 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
19953 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19954 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
19955 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19956 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19957 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19958 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19959 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19960 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19961 GIR_RootToRootCopy, /*OpIdx*/2, // T
19962 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19963 GIR_RootToRootCopy, /*OpIdx*/3, // F
19964 GIR_RootConstrainSelectedInstOperands,
19965 // GIR_Coverage, 2197,
19966 GIR_EraseRootFromParent_Done,
19967 // Label 1212: @51131
19968 GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(51229), // Rule ID 2200 //
19969 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
19970 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
19971 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19972 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19973 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19974 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
19975 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
19976 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
19977 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
19978 // MIs[1] Operand 1
19979 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
19980 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19981 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19982 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19983 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
19984 GIM_CheckIsSafeToFold, /*NumInsns*/1,
19985 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
19986 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
19987 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
19988 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
19989 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
19990 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
19991 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
19992 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
19993 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
19994 GIR_RootToRootCopy, /*OpIdx*/2, // T
19995 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
19996 GIR_RootToRootCopy, /*OpIdx*/3, // F
19997 GIR_RootConstrainSelectedInstOperands,
19998 // GIR_Coverage, 2200,
19999 GIR_EraseRootFromParent_Done,
20000 // Label 1213: @51229
20001 GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(51327), // Rule ID 2203 //
20002 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
20003 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20004 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20005 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20006 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20007 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20008 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20009 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20010 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20011 // MIs[1] Operand 1
20012 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20013 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20014 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20015 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20016 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20017 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20018 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20019 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20020 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20021 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20022 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20023 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20024 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20025 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20026 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20027 GIR_RootToRootCopy, /*OpIdx*/2, // T
20028 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20029 GIR_RootToRootCopy, /*OpIdx*/3, // F
20030 GIR_RootConstrainSelectedInstOperands,
20031 // GIR_Coverage, 2203,
20032 GIR_EraseRootFromParent_Done,
20033 // Label 1214: @51327
20034 GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(51425), // Rule ID 2206 //
20035 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20036 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20037 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20038 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20039 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20040 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20041 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20042 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20043 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20044 // MIs[1] Operand 1
20045 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20046 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20047 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20048 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20049 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20050 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20051 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20052 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20053 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20054 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20055 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20056 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20057 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20058 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20059 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20060 GIR_RootToRootCopy, /*OpIdx*/2, // T
20061 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20062 GIR_RootToRootCopy, /*OpIdx*/3, // F
20063 GIR_RootConstrainSelectedInstOperands,
20064 // GIR_Coverage, 2206,
20065 GIR_EraseRootFromParent_Done,
20066 // Label 1215: @51425
20067 GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(51523), // Rule ID 2207 //
20068 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20069 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20070 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20071 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20072 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20073 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20074 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20075 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20076 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20077 // MIs[1] Operand 1
20078 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20079 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20080 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20081 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20082 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20083 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20084 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20085 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20086 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20087 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20088 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20089 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20090 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20091 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20092 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20093 GIR_RootToRootCopy, /*OpIdx*/2, // T
20094 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20095 GIR_RootToRootCopy, /*OpIdx*/3, // F
20096 GIR_RootConstrainSelectedInstOperands,
20097 // GIR_Coverage, 2207,
20098 GIR_EraseRootFromParent_Done,
20099 // Label 1216: @51523
20100 GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(51621), // Rule ID 2210 //
20101 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20102 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20103 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20104 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20105 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20106 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20107 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20108 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20109 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20110 // MIs[1] Operand 1
20111 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20112 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20113 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20114 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20115 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20116 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20117 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20118 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20119 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20120 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20121 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20122 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20123 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20124 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20125 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20126 GIR_RootToRootCopy, /*OpIdx*/2, // T
20127 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20128 GIR_RootToRootCopy, /*OpIdx*/3, // F
20129 GIR_RootConstrainSelectedInstOperands,
20130 // GIR_Coverage, 2210,
20131 GIR_EraseRootFromParent_Done,
20132 // Label 1217: @51621
20133 GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(51719), // Rule ID 2211 //
20134 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20135 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20136 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20137 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20138 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20139 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20140 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20141 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20142 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20143 // MIs[1] Operand 1
20144 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20145 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20146 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20147 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20148 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20149 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20150 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
20151 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20152 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20153 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20154 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20155 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20156 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20157 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20158 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20159 GIR_RootToRootCopy, /*OpIdx*/2, // T
20160 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20161 GIR_RootToRootCopy, /*OpIdx*/3, // F
20162 GIR_RootConstrainSelectedInstOperands,
20163 // GIR_Coverage, 2211,
20164 GIR_EraseRootFromParent_Done,
20165 // Label 1218: @51719
20166 GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(51817), // Rule ID 2214 //
20167 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20168 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20169 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20170 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20171 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20172 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20173 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20174 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20175 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20176 // MIs[1] Operand 1
20177 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20178 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20179 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20180 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20181 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20182 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20183 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20184 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20185 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20186 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20187 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20188 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20189 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20190 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
20191 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20192 GIR_RootToRootCopy, /*OpIdx*/2, // T
20193 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20194 GIR_RootToRootCopy, /*OpIdx*/3, // F
20195 GIR_RootConstrainSelectedInstOperands,
20196 // GIR_Coverage, 2214,
20197 GIR_EraseRootFromParent_Done,
20198 // Label 1219: @51817
20199 GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(51915), // Rule ID 2217 //
20200 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20201 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20202 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20203 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20204 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20205 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20206 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20207 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20208 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20209 // MIs[1] Operand 1
20210 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20211 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20212 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20213 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20214 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20215 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20216 // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
20217 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20218 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20219 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20220 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20221 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20222 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20223 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20224 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20225 GIR_RootToRootCopy, /*OpIdx*/2, // T
20226 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20227 GIR_RootToRootCopy, /*OpIdx*/3, // F
20228 GIR_RootConstrainSelectedInstOperands,
20229 // GIR_Coverage, 2217,
20230 GIR_EraseRootFromParent_Done,
20231 // Label 1220: @51915
20232 GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(52013), // Rule ID 2240 //
20233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20234 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20235 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20236 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20237 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20238 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20239 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20240 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20241 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20242 // MIs[1] Operand 1
20243 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
20244 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20245 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20246 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20247 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20248 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20249 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20250 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20251 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20252 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20253 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20254 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20255 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20256 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20257 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20258 GIR_RootToRootCopy, /*OpIdx*/2, // T
20259 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20260 GIR_RootToRootCopy, /*OpIdx*/3, // F
20261 GIR_RootConstrainSelectedInstOperands,
20262 // GIR_Coverage, 2240,
20263 GIR_EraseRootFromParent_Done,
20264 // Label 1221: @52013
20265 GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(52111), // Rule ID 2241 //
20266 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20267 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20268 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20269 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20270 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20271 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20272 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20273 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20274 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20275 // MIs[1] Operand 1
20276 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
20277 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20278 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20279 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20280 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20281 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20282 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20283 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20284 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20285 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20286 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20287 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20288 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20289 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20290 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20291 GIR_RootToRootCopy, /*OpIdx*/2, // T
20292 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20293 GIR_RootToRootCopy, /*OpIdx*/3, // F
20294 GIR_RootConstrainSelectedInstOperands,
20295 // GIR_Coverage, 2241,
20296 GIR_EraseRootFromParent_Done,
20297 // Label 1222: @52111
20298 GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(52209), // Rule ID 2244 //
20299 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20302 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20303 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20304 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20305 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20306 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20307 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20308 // MIs[1] Operand 1
20309 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
20310 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20311 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20312 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20313 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20314 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20315 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20316 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20317 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
20318 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20319 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20320 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20321 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20323 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20324 GIR_RootToRootCopy, /*OpIdx*/2, // T
20325 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20326 GIR_RootToRootCopy, /*OpIdx*/3, // F
20327 GIR_RootConstrainSelectedInstOperands,
20328 // GIR_Coverage, 2244,
20329 GIR_EraseRootFromParent_Done,
20330 // Label 1223: @52209
20331 GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(52307), // Rule ID 2245 //
20332 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20333 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20334 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20335 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20336 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20337 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20338 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20339 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20340 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20341 // MIs[1] Operand 1
20342 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
20343 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20344 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20345 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20346 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20347 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20348 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
20349 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20350 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
20351 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20352 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20353 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20354 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20355 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20356 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20357 GIR_RootToRootCopy, /*OpIdx*/2, // T
20358 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20359 GIR_RootToRootCopy, /*OpIdx*/3, // F
20360 GIR_RootConstrainSelectedInstOperands,
20361 // GIR_Coverage, 2245,
20362 GIR_EraseRootFromParent_Done,
20363 // Label 1224: @52307
20364 GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(52405), // Rule ID 2248 //
20365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20366 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20367 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20368 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20369 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20370 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20371 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20372 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20373 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20374 // MIs[1] Operand 1
20375 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20376 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20377 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20378 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20379 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20380 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20381 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20382 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20383 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20384 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20385 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20386 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20387 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20388 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
20389 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20390 GIR_RootToRootCopy, /*OpIdx*/2, // T
20391 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20392 GIR_RootToRootCopy, /*OpIdx*/3, // F
20393 GIR_RootConstrainSelectedInstOperands,
20394 // GIR_Coverage, 2248,
20395 GIR_EraseRootFromParent_Done,
20396 // Label 1225: @52405
20397 GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(52503), // Rule ID 2250 //
20398 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20399 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20400 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20401 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20402 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20403 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20404 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20405 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20406 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20407 // MIs[1] Operand 1
20408 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20409 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20410 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20411 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20412 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20413 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20414 // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
20415 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20416 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
20417 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20418 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20419 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
20420 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20421 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20422 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20423 GIR_RootToRootCopy, /*OpIdx*/2, // T
20424 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20425 GIR_RootToRootCopy, /*OpIdx*/3, // F
20426 GIR_RootConstrainSelectedInstOperands,
20427 // GIR_Coverage, 2250,
20428 GIR_EraseRootFromParent_Done,
20429 // Label 1226: @52503
20430 GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(52543), // Rule ID 295 //
20431 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
20432 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20433 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20434 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20435 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20436 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20437 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20438 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20439 // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
20440 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
20441 GIR_RootConstrainSelectedInstOperands,
20442 // GIR_Coverage, 295,
20443 GIR_Done,
20444 // Label 1227: @52543
20445 GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(52583), // Rule ID 297 //
20446 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
20447 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20448 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20449 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20450 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20451 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20452 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20453 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20454 // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
20455 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
20456 GIR_RootConstrainSelectedInstOperands,
20457 // GIR_Coverage, 297,
20458 GIR_Done,
20459 // Label 1228: @52583
20460 GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(52629), // Rule ID 334 //
20461 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
20462 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20463 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20464 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20466 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
20467 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20468 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20469 // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
20470 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
20471 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20472 GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
20473 GIR_RootToRootCopy, /*OpIdx*/3, // fs
20474 GIR_RootToRootCopy, /*OpIdx*/2, // ft
20475 GIR_RootConstrainSelectedInstOperands,
20476 // GIR_Coverage, 334,
20477 GIR_EraseRootFromParent_Done,
20478 // Label 1229: @52629
20479 GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(52675), // Rule ID 1213 //
20480 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
20481 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20482 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20483 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20484 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20485 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGRCCRegClassID),
20486 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20487 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20488 // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
20489 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
20490 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20491 GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
20492 GIR_RootToRootCopy, /*OpIdx*/3, // fs
20493 GIR_RootToRootCopy, /*OpIdx*/2, // ft
20494 GIR_RootConstrainSelectedInstOperands,
20495 // GIR_Coverage, 1213,
20496 GIR_EraseRootFromParent_Done,
20497 // Label 1230: @52675
20498 GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(52721), // Rule ID 1626 //
20499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20501 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20502 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20503 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20504 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20505 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20506 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20507 // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20508 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
20509 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20510 GIR_RootToRootCopy, /*OpIdx*/2, // T
20511 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20512 GIR_RootToRootCopy, /*OpIdx*/3, // F
20513 GIR_RootConstrainSelectedInstOperands,
20514 // GIR_Coverage, 1626,
20515 GIR_EraseRootFromParent_Done,
20516 // Label 1231: @52721
20517 GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(52767), // Rule ID 1665 //
20518 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20519 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
20520 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20521 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20522 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20523 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20524 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20525 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20526 // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
20527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
20528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20529 GIR_RootToRootCopy, /*OpIdx*/2, // T
20530 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20531 GIR_RootToRootCopy, /*OpIdx*/3, // F
20532 GIR_RootConstrainSelectedInstOperands,
20533 // GIR_Coverage, 1665,
20534 GIR_EraseRootFromParent_Done,
20535 // Label 1232: @52767
20536 GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(52813), // Rule ID 1681 //
20537 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
20538 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20539 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20540 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20541 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20542 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20543 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20544 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20545 // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20546 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
20547 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20548 GIR_RootToRootCopy, /*OpIdx*/2, // T
20549 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20550 GIR_RootToRootCopy, /*OpIdx*/3, // F
20551 GIR_RootConstrainSelectedInstOperands,
20552 // GIR_Coverage, 1681,
20553 GIR_EraseRootFromParent_Done,
20554 // Label 1233: @52813
20555 GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(52859), // Rule ID 1694 //
20556 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20557 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
20558 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20559 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20560 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20561 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20562 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20563 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20564 // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
20565 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
20566 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20567 GIR_RootToRootCopy, /*OpIdx*/2, // T
20568 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20569 GIR_RootToRootCopy, /*OpIdx*/3, // F
20570 GIR_RootConstrainSelectedInstOperands,
20571 // GIR_Coverage, 1694,
20572 GIR_EraseRootFromParent_Done,
20573 // Label 1234: @52859
20574 GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(52905), // Rule ID 1858 //
20575 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
20576 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20577 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20578 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20579 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20580 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20581 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20582 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
20583 // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
20584 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
20585 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
20586 GIR_RootToRootCopy, /*OpIdx*/2, // x
20587 GIR_RootToRootCopy, /*OpIdx*/3, // y
20588 GIR_RootToRootCopy, /*OpIdx*/1, // a
20589 GIR_RootConstrainSelectedInstOperands,
20590 // GIR_Coverage, 1858,
20591 GIR_EraseRootFromParent_Done,
20592 // Label 1235: @52905
20593 GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(52951), // Rule ID 2204 //
20594 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
20595 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20596 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20597 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20598 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20599 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20600 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20601 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20602 // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20603 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20604 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20605 GIR_RootToRootCopy, /*OpIdx*/2, // T
20606 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20607 GIR_RootToRootCopy, /*OpIdx*/3, // F
20608 GIR_RootConstrainSelectedInstOperands,
20609 // GIR_Coverage, 2204,
20610 GIR_EraseRootFromParent_Done,
20611 // Label 1236: @52951
20612 GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(52997), // Rule ID 2218 //
20613 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20614 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20615 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20616 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20617 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20618 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20619 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20620 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20621 // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
20622 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
20623 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20624 GIR_RootToRootCopy, /*OpIdx*/2, // T
20625 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20626 GIR_RootToRootCopy, /*OpIdx*/3, // F
20627 GIR_RootConstrainSelectedInstOperands,
20628 // GIR_Coverage, 2218,
20629 GIR_EraseRootFromParent_Done,
20630 // Label 1237: @52997
20631 GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(53043), // Rule ID 2251 //
20632 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
20633 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20634 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20635 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20636 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20637 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20638 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20639 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
20640 // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
20641 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
20642 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20643 GIR_RootToRootCopy, /*OpIdx*/2, // T
20644 GIR_RootToRootCopy, /*OpIdx*/1, // cond
20645 GIR_RootToRootCopy, /*OpIdx*/3, // F
20646 GIR_RootConstrainSelectedInstOperands,
20647 // GIR_Coverage, 2251,
20648 GIR_EraseRootFromParent_Done,
20649 // Label 1238: @53043
20650 GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(53121), // Rule ID 1763 //
20651 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
20652 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20653 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20654 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20655 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20656 // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
20657 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20658 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
20659 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
20660 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20661 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
20662 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
20663 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20664 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
20665 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20666 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
20667 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20668 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20669 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
20670 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20671 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20672 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
20673 GIR_RootConstrainSelectedInstOperands,
20674 // GIR_Coverage, 1763,
20675 GIR_EraseRootFromParent_Done,
20676 // Label 1239: @53121
20677 GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(53199), // Rule ID 2268 //
20678 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
20679 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20680 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20681 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20682 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20683 // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
20684 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
20685 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
20686 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
20687 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20688 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
20689 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
20690 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
20691 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
20692 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
20693 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
20694 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
20695 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
20696 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
20697 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20698 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
20699 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
20700 GIR_RootConstrainSelectedInstOperands,
20701 // GIR_Coverage, 2268,
20702 GIR_EraseRootFromParent_Done,
20703 // Label 1240: @53199
20704 GIM_Reject,
20705 // Label 1155: @53200
20706 GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(53276), // Rule ID 1653 //
20707 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20708 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20709 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20710 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20711 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20712 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20713 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20714 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20715 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20716 // MIs[1] Operand 1
20717 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20718 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20719 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20720 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20721 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20722 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20723 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
20724 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
20725 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20726 GIR_RootToRootCopy, /*OpIdx*/2, // T
20727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20728 GIR_RootToRootCopy, /*OpIdx*/3, // F
20729 GIR_RootConstrainSelectedInstOperands,
20730 // GIR_Coverage, 1653,
20731 GIR_EraseRootFromParent_Done,
20732 // Label 1241: @53276
20733 GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(53352), // Rule ID 1657 //
20734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20735 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20736 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20737 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20738 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20739 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20740 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20741 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20742 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20743 // MIs[1] Operand 1
20744 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20745 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20746 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20747 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20748 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20749 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20750 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
20751 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
20752 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20753 GIR_RootToRootCopy, /*OpIdx*/2, // T
20754 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20755 GIR_RootToRootCopy, /*OpIdx*/3, // F
20756 GIR_RootConstrainSelectedInstOperands,
20757 // GIR_Coverage, 1657,
20758 GIR_EraseRootFromParent_Done,
20759 // Label 1242: @53352
20760 GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(53428), // Rule ID 1663 //
20761 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20762 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20763 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20764 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20765 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20766 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20767 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20768 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20769 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20770 // MIs[1] Operand 1
20771 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20772 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20773 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20774 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20775 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20776 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20777 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
20778 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
20779 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20780 GIR_RootToRootCopy, /*OpIdx*/2, // T
20781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20782 GIR_RootToRootCopy, /*OpIdx*/3, // F
20783 GIR_RootConstrainSelectedInstOperands,
20784 // GIR_Coverage, 1663,
20785 GIR_EraseRootFromParent_Done,
20786 // Label 1243: @53428
20787 GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(53504), // Rule ID 1669 //
20788 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20789 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20790 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20791 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20792 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20793 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20794 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20795 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20796 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20797 // MIs[1] Operand 1
20798 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20800 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20801 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20802 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20803 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20804 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
20805 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
20806 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
20807 GIR_RootToRootCopy, /*OpIdx*/2, // T
20808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20809 GIR_RootToRootCopy, /*OpIdx*/3, // F
20810 GIR_RootConstrainSelectedInstOperands,
20811 // GIR_Coverage, 1669,
20812 GIR_EraseRootFromParent_Done,
20813 // Label 1244: @53504
20814 GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(53580), // Rule ID 1705 //
20815 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20816 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20817 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20818 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20819 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20821 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20822 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20823 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20824 // MIs[1] Operand 1
20825 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20826 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20827 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20828 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20829 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20830 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20831 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20832 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
20833 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20834 GIR_RootToRootCopy, /*OpIdx*/2, // T
20835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20836 GIR_RootToRootCopy, /*OpIdx*/3, // F
20837 GIR_RootConstrainSelectedInstOperands,
20838 // GIR_Coverage, 1705,
20839 GIR_EraseRootFromParent_Done,
20840 // Label 1245: @53580
20841 GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(53656), // Rule ID 1708 //
20842 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20843 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20844 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20845 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20846 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20848 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20849 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20850 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20851 // MIs[1] Operand 1
20852 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20853 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20854 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20855 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20856 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20857 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20858 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20859 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
20860 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20861 GIR_RootToRootCopy, /*OpIdx*/2, // T
20862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20863 GIR_RootToRootCopy, /*OpIdx*/3, // F
20864 GIR_RootConstrainSelectedInstOperands,
20865 // GIR_Coverage, 1708,
20866 GIR_EraseRootFromParent_Done,
20867 // Label 1246: @53656
20868 GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(53732), // Rule ID 1726 //
20869 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20870 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20871 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20872 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20873 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20874 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20875 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20876 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20877 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20878 // MIs[1] Operand 1
20879 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20880 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20881 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20882 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20883 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20884 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20885 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
20886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
20887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20888 GIR_RootToRootCopy, /*OpIdx*/2, // T
20889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20890 GIR_RootToRootCopy, /*OpIdx*/3, // F
20891 GIR_RootConstrainSelectedInstOperands,
20892 // GIR_Coverage, 1726,
20893 GIR_EraseRootFromParent_Done,
20894 // Label 1247: @53732
20895 GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(53808), // Rule ID 1728 //
20896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20897 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20898 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20899 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20900 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20901 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20902 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20903 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20904 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20905 // MIs[1] Operand 1
20906 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20907 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20908 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20909 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20910 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20911 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20912 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
20913 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
20914 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20915 GIR_RootToRootCopy, /*OpIdx*/2, // T
20916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20917 GIR_RootToRootCopy, /*OpIdx*/3, // F
20918 GIR_RootConstrainSelectedInstOperands,
20919 // GIR_Coverage, 1728,
20920 GIR_EraseRootFromParent_Done,
20921 // Label 1248: @53808
20922 GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(53884), // Rule ID 1731 //
20923 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20924 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20925 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20926 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20927 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20928 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20929 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20930 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20931 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20932 // MIs[1] Operand 1
20933 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20934 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20935 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20936 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20937 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20938 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20939 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
20940 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
20941 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20942 GIR_RootToRootCopy, /*OpIdx*/2, // T
20943 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20944 GIR_RootToRootCopy, /*OpIdx*/3, // F
20945 GIR_RootConstrainSelectedInstOperands,
20946 // GIR_Coverage, 1731,
20947 GIR_EraseRootFromParent_Done,
20948 // Label 1249: @53884
20949 GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(53960), // Rule ID 1734 //
20950 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
20951 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20952 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20953 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20954 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20955 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20956 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20957 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
20958 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
20959 // MIs[1] Operand 1
20960 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
20961 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
20962 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20963 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20964 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
20965 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20966 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
20967 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
20968 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20969 GIR_RootToRootCopy, /*OpIdx*/2, // T
20970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20971 GIR_RootToRootCopy, /*OpIdx*/3, // F
20972 GIR_RootConstrainSelectedInstOperands,
20973 // GIR_Coverage, 1734,
20974 GIR_EraseRootFromParent_Done,
20975 // Label 1250: @53960
20976 GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(54036), // Rule ID 2262 //
20977 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
20978 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
20979 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20980 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20981 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20982 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
20983 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
20984 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
20985 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
20986 // MIs[1] Operand 1
20987 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
20988 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
20989 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
20990 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20991 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
20992 GIM_CheckIsSafeToFold, /*NumInsns*/1,
20993 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
20994 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
20995 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
20996 GIR_RootToRootCopy, /*OpIdx*/2, // T
20997 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
20998 GIR_RootToRootCopy, /*OpIdx*/3, // F
20999 GIR_RootConstrainSelectedInstOperands,
21000 // GIR_Coverage, 2262,
21001 GIR_EraseRootFromParent_Done,
21002 // Label 1251: @54036
21003 GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(54112), // Rule ID 2265 //
21004 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
21005 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21006 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21007 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21008 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21009 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21010 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21011 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21012 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21013 // MIs[1] Operand 1
21014 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21015 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21016 GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
21017 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21018 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21019 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21020 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
21021 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
21022 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21023 GIR_RootToRootCopy, /*OpIdx*/2, // T
21024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21025 GIR_RootToRootCopy, /*OpIdx*/3, // F
21026 GIR_RootConstrainSelectedInstOperands,
21027 // GIR_Coverage, 2265,
21028 GIR_EraseRootFromParent_Done,
21029 // Label 1252: @54112
21030 GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(54210), // Rule ID 1628 //
21031 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21032 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21033 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21034 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21035 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21036 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21037 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21038 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21039 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21040 // MIs[1] Operand 1
21041 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21042 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21043 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21044 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21045 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21046 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21047 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21048 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21049 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21050 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21051 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21052 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21053 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21056 GIR_RootToRootCopy, /*OpIdx*/2, // T
21057 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21058 GIR_RootToRootCopy, /*OpIdx*/3, // F
21059 GIR_RootConstrainSelectedInstOperands,
21060 // GIR_Coverage, 1628,
21061 GIR_EraseRootFromParent_Done,
21062 // Label 1253: @54210
21063 GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(54308), // Rule ID 1629 //
21064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21065 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21066 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21067 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21068 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21069 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21070 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21071 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21072 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21073 // MIs[1] Operand 1
21074 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21075 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21076 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21077 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21078 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21079 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21080 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21081 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21082 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21083 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21084 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21085 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21086 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21087 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21088 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21089 GIR_RootToRootCopy, /*OpIdx*/2, // T
21090 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21091 GIR_RootToRootCopy, /*OpIdx*/3, // F
21092 GIR_RootConstrainSelectedInstOperands,
21093 // GIR_Coverage, 1629,
21094 GIR_EraseRootFromParent_Done,
21095 // Label 1254: @54308
21096 GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(54406), // Rule ID 1632 //
21097 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21098 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21099 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21100 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21101 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21102 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21103 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21104 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21105 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21106 // MIs[1] Operand 1
21107 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21108 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21109 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21110 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21111 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21112 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21113 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
21114 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21115 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21116 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21117 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21118 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21119 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21120 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21121 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21122 GIR_RootToRootCopy, /*OpIdx*/2, // T
21123 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21124 GIR_RootToRootCopy, /*OpIdx*/3, // F
21125 GIR_RootConstrainSelectedInstOperands,
21126 // GIR_Coverage, 1632,
21127 GIR_EraseRootFromParent_Done,
21128 // Label 1255: @54406
21129 GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(54504), // Rule ID 1633 //
21130 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21131 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21132 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21133 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21134 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21135 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21136 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21137 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21138 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21139 // MIs[1] Operand 1
21140 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21141 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21142 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21143 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21144 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21145 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21146 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
21147 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21148 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21149 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21150 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21151 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21152 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21153 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21154 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21155 GIR_RootToRootCopy, /*OpIdx*/2, // T
21156 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21157 GIR_RootToRootCopy, /*OpIdx*/3, // F
21158 GIR_RootConstrainSelectedInstOperands,
21159 // GIR_Coverage, 1633,
21160 GIR_EraseRootFromParent_Done,
21161 // Label 1256: @54504
21162 GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(54602), // Rule ID 1644 //
21163 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21164 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21165 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21166 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21167 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21168 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21169 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21170 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21171 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21172 // MIs[1] Operand 1
21173 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21174 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21175 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21176 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21177 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21178 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21179 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21180 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21181 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21182 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21183 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21184 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21185 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21186 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21187 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21188 GIR_RootToRootCopy, /*OpIdx*/2, // T
21189 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21190 GIR_RootToRootCopy, /*OpIdx*/3, // F
21191 GIR_RootConstrainSelectedInstOperands,
21192 // GIR_Coverage, 1644,
21193 GIR_EraseRootFromParent_Done,
21194 // Label 1257: @54602
21195 GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(54700), // Rule ID 1645 //
21196 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21197 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21198 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21199 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21200 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21201 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21202 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21203 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21204 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21205 // MIs[1] Operand 1
21206 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21207 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21208 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21209 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21210 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21211 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21212 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21213 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21215 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21216 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21217 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21218 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21219 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21220 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21221 GIR_RootToRootCopy, /*OpIdx*/2, // T
21222 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21223 GIR_RootToRootCopy, /*OpIdx*/3, // F
21224 GIR_RootConstrainSelectedInstOperands,
21225 // GIR_Coverage, 1645,
21226 GIR_EraseRootFromParent_Done,
21227 // Label 1258: @54700
21228 GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(54798), // Rule ID 1648 //
21229 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21230 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21231 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21232 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21233 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21234 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21235 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21236 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21237 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21238 // MIs[1] Operand 1
21239 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21240 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21241 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21242 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21243 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21244 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21245 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
21246 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21247 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21248 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21249 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21250 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21251 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21252 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21253 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21254 GIR_RootToRootCopy, /*OpIdx*/2, // T
21255 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21256 GIR_RootToRootCopy, /*OpIdx*/3, // F
21257 GIR_RootConstrainSelectedInstOperands,
21258 // GIR_Coverage, 1648,
21259 GIR_EraseRootFromParent_Done,
21260 // Label 1259: @54798
21261 GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(54896), // Rule ID 1649 //
21262 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21263 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21265 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21266 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21267 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21268 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21269 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21270 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21271 // MIs[1] Operand 1
21272 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21273 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21274 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21275 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21276 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21277 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21278 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
21279 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21280 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21281 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21282 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21283 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21284 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21285 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21286 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21287 GIR_RootToRootCopy, /*OpIdx*/2, // T
21288 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21289 GIR_RootToRootCopy, /*OpIdx*/3, // F
21290 GIR_RootConstrainSelectedInstOperands,
21291 // GIR_Coverage, 1649,
21292 GIR_EraseRootFromParent_Done,
21293 // Label 1260: @54896
21294 GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(54994), // Rule ID 1652 //
21295 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21296 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21297 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21298 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21299 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21300 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21301 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21302 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21303 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21304 // MIs[1] Operand 1
21305 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21306 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21307 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21308 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21309 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21310 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21311 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21312 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21313 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21314 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21315 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21316 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21317 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21318 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
21319 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21320 GIR_RootToRootCopy, /*OpIdx*/2, // T
21321 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21322 GIR_RootToRootCopy, /*OpIdx*/3, // F
21323 GIR_RootConstrainSelectedInstOperands,
21324 // GIR_Coverage, 1652,
21325 GIR_EraseRootFromParent_Done,
21326 // Label 1261: @54994
21327 GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(55092), // Rule ID 1656 //
21328 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21329 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21330 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21331 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21332 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21333 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21334 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21335 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21336 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21337 // MIs[1] Operand 1
21338 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21339 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21340 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21341 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21342 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21343 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21344 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21345 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21346 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21347 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21348 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21349 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21350 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21351 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
21352 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21353 GIR_RootToRootCopy, /*OpIdx*/2, // T
21354 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21355 GIR_RootToRootCopy, /*OpIdx*/3, // F
21356 GIR_RootConstrainSelectedInstOperands,
21357 // GIR_Coverage, 1656,
21358 GIR_EraseRootFromParent_Done,
21359 // Label 1262: @55092
21360 GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(55190), // Rule ID 1661 //
21361 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21362 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21363 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21364 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21365 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21366 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21367 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21368 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21369 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21370 // MIs[1] Operand 1
21371 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21372 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21373 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21374 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21375 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21376 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21377 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
21378 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21379 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21380 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21381 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21382 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21383 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21384 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
21385 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21386 GIR_RootToRootCopy, /*OpIdx*/2, // T
21387 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21388 GIR_RootToRootCopy, /*OpIdx*/3, // F
21389 GIR_RootConstrainSelectedInstOperands,
21390 // GIR_Coverage, 1661,
21391 GIR_EraseRootFromParent_Done,
21392 // Label 1263: @55190
21393 GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(55288), // Rule ID 1667 //
21394 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21395 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21396 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21397 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21398 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21399 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21400 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21401 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21402 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21403 // MIs[1] Operand 1
21404 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21405 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21406 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21407 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21408 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21409 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21410 // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
21411 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21412 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21413 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21414 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21415 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21416 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21417 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
21418 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
21419 GIR_RootToRootCopy, /*OpIdx*/2, // T
21420 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21421 GIR_RootToRootCopy, /*OpIdx*/3, // F
21422 GIR_RootConstrainSelectedInstOperands,
21423 // GIR_Coverage, 1667,
21424 GIR_EraseRootFromParent_Done,
21425 // Label 1264: @55288
21426 GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(55386), // Rule ID 1696 //
21427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21428 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21429 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21430 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21431 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21432 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21433 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21434 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21435 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21436 // MIs[1] Operand 1
21437 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21438 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21439 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21440 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21441 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21442 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21443 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21444 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21445 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21446 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21447 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21448 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21449 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21450 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21451 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21452 GIR_RootToRootCopy, /*OpIdx*/2, // T
21453 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21454 GIR_RootToRootCopy, /*OpIdx*/3, // F
21455 GIR_RootConstrainSelectedInstOperands,
21456 // GIR_Coverage, 1696,
21457 GIR_EraseRootFromParent_Done,
21458 // Label 1265: @55386
21459 GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(55484), // Rule ID 1697 //
21460 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21461 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21462 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21463 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21464 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21465 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21466 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21467 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21468 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21469 // MIs[1] Operand 1
21470 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21471 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21472 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21473 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21474 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21475 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21476 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21477 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21478 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21479 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21480 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21481 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21482 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21483 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21484 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21485 GIR_RootToRootCopy, /*OpIdx*/2, // T
21486 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21487 GIR_RootToRootCopy, /*OpIdx*/3, // F
21488 GIR_RootConstrainSelectedInstOperands,
21489 // GIR_Coverage, 1697,
21490 GIR_EraseRootFromParent_Done,
21491 // Label 1266: @55484
21492 GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(55582), // Rule ID 1700 //
21493 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21494 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21495 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21496 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21497 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21499 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21500 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21501 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21502 // MIs[1] Operand 1
21503 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21504 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21505 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21506 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21507 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21508 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21509 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21510 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21511 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21512 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21513 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21514 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21515 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21516 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21517 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21518 GIR_RootToRootCopy, /*OpIdx*/2, // T
21519 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21520 GIR_RootToRootCopy, /*OpIdx*/3, // F
21521 GIR_RootConstrainSelectedInstOperands,
21522 // GIR_Coverage, 1700,
21523 GIR_EraseRootFromParent_Done,
21524 // Label 1267: @55582
21525 GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(55680), // Rule ID 1701 //
21526 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21527 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21528 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21529 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21530 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21531 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21532 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21533 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21534 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21535 // MIs[1] Operand 1
21536 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21537 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21538 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21539 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21540 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21541 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21542 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
21543 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21544 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21545 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21546 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21547 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21548 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21549 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21550 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21551 GIR_RootToRootCopy, /*OpIdx*/2, // T
21552 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21553 GIR_RootToRootCopy, /*OpIdx*/3, // F
21554 GIR_RootConstrainSelectedInstOperands,
21555 // GIR_Coverage, 1701,
21556 GIR_EraseRootFromParent_Done,
21557 // Label 1268: @55680
21558 GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(55778), // Rule ID 1704 //
21559 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21560 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21561 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21562 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21563 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21565 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21566 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21567 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21568 // MIs[1] Operand 1
21569 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21570 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21571 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21572 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21573 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21574 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21575 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21576 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21577 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21578 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21579 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21580 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21581 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21582 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
21583 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21584 GIR_RootToRootCopy, /*OpIdx*/2, // T
21585 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21586 GIR_RootToRootCopy, /*OpIdx*/3, // F
21587 GIR_RootConstrainSelectedInstOperands,
21588 // GIR_Coverage, 1704,
21589 GIR_EraseRootFromParent_Done,
21590 // Label 1269: @55778
21591 GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(55876), // Rule ID 1706 //
21592 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21593 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21594 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21595 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21596 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21597 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21598 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21599 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21600 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21601 // MIs[1] Operand 1
21602 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21603 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21604 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21605 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21606 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
21607 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21608 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
21609 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21610 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21611 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21612 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21613 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21614 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21615 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
21616 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21617 GIR_RootToRootCopy, /*OpIdx*/2, // T
21618 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21619 GIR_RootToRootCopy, /*OpIdx*/3, // F
21620 GIR_RootConstrainSelectedInstOperands,
21621 // GIR_Coverage, 1706,
21622 GIR_EraseRootFromParent_Done,
21623 // Label 1270: @55876
21624 GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(55974), // Rule ID 1709 //
21625 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21626 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21627 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21628 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21631 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21632 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21633 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21634 // MIs[1] Operand 1
21635 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21636 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21637 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21638 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21639 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21640 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21641 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21642 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21643 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21644 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21645 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21646 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21647 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21648 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21649 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21650 GIR_RootToRootCopy, /*OpIdx*/2, // T
21651 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21652 GIR_RootToRootCopy, /*OpIdx*/3, // F
21653 GIR_RootConstrainSelectedInstOperands,
21654 // GIR_Coverage, 1709,
21655 GIR_EraseRootFromParent_Done,
21656 // Label 1271: @55974
21657 GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(56072), // Rule ID 1710 //
21658 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21659 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21660 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21661 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21662 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21663 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21664 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21665 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21666 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21667 // MIs[1] Operand 1
21668 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21669 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21670 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21671 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21672 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21673 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21674 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21675 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21676 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21677 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21678 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21679 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21680 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21681 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21682 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21683 GIR_RootToRootCopy, /*OpIdx*/2, // T
21684 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21685 GIR_RootToRootCopy, /*OpIdx*/3, // F
21686 GIR_RootConstrainSelectedInstOperands,
21687 // GIR_Coverage, 1710,
21688 GIR_EraseRootFromParent_Done,
21689 // Label 1272: @56072
21690 GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(56170), // Rule ID 1713 //
21691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21692 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21693 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21694 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21695 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21696 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21697 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21698 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21699 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21700 // MIs[1] Operand 1
21701 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21702 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21703 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21704 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21705 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21706 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21707 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
21708 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21709 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
21710 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21711 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21712 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21713 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21714 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21715 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21716 GIR_RootToRootCopy, /*OpIdx*/2, // T
21717 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21718 GIR_RootToRootCopy, /*OpIdx*/3, // F
21719 GIR_RootConstrainSelectedInstOperands,
21720 // GIR_Coverage, 1713,
21721 GIR_EraseRootFromParent_Done,
21722 // Label 1273: @56170
21723 GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(56268), // Rule ID 1714 //
21724 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21725 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21726 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21727 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21728 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21729 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21730 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21731 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21732 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21733 // MIs[1] Operand 1
21734 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21735 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21736 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21737 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21738 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21739 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21740 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
21741 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21742 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
21743 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21744 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21745 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21746 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21747 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21748 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21749 GIR_RootToRootCopy, /*OpIdx*/2, // T
21750 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21751 GIR_RootToRootCopy, /*OpIdx*/3, // F
21752 GIR_RootConstrainSelectedInstOperands,
21753 // GIR_Coverage, 1714,
21754 GIR_EraseRootFromParent_Done,
21755 // Label 1274: @56268
21756 GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(56366), // Rule ID 1717 //
21757 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21758 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21759 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21760 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21761 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21762 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21763 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21764 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21765 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21766 // MIs[1] Operand 1
21767 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
21768 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21769 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21770 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21771 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21772 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21773 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21774 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21775 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21776 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21777 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21778 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21779 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21780 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21781 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21782 GIR_RootToRootCopy, /*OpIdx*/2, // T
21783 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21784 GIR_RootToRootCopy, /*OpIdx*/3, // F
21785 GIR_RootConstrainSelectedInstOperands,
21786 // GIR_Coverage, 1717,
21787 GIR_EraseRootFromParent_Done,
21788 // Label 1275: @56366
21789 GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(56464), // Rule ID 1718 //
21790 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21791 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21792 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21793 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21794 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21795 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21796 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21797 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21798 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21799 // MIs[1] Operand 1
21800 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
21801 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21802 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21803 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21804 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21805 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21806 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21807 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21808 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21809 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21810 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21811 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21812 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21813 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21814 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21815 GIR_RootToRootCopy, /*OpIdx*/2, // T
21816 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21817 GIR_RootToRootCopy, /*OpIdx*/3, // F
21818 GIR_RootConstrainSelectedInstOperands,
21819 // GIR_Coverage, 1718,
21820 GIR_EraseRootFromParent_Done,
21821 // Label 1276: @56464
21822 GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(56562), // Rule ID 1721 //
21823 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21824 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21825 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21826 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21827 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21828 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21829 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21830 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21831 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21832 // MIs[1] Operand 1
21833 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
21834 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21835 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21836 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21837 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21838 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21839 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21840 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21841 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
21842 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21843 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21844 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21845 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21846 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21847 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21848 GIR_RootToRootCopy, /*OpIdx*/2, // T
21849 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21850 GIR_RootToRootCopy, /*OpIdx*/3, // F
21851 GIR_RootConstrainSelectedInstOperands,
21852 // GIR_Coverage, 1721,
21853 GIR_EraseRootFromParent_Done,
21854 // Label 1277: @56562
21855 GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(56660), // Rule ID 1722 //
21856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21857 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21858 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21859 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21860 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21861 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21862 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21863 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21864 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21865 // MIs[1] Operand 1
21866 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
21867 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21868 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21869 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21870 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21871 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21872 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
21873 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21874 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
21875 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21876 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21877 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21878 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21879 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21880 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21881 GIR_RootToRootCopy, /*OpIdx*/2, // T
21882 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21883 GIR_RootToRootCopy, /*OpIdx*/3, // F
21884 GIR_RootConstrainSelectedInstOperands,
21885 // GIR_Coverage, 1722,
21886 GIR_EraseRootFromParent_Done,
21887 // Label 1278: @56660
21888 GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(56758), // Rule ID 1725 //
21889 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21890 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21891 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21892 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21893 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21894 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21895 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21896 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21897 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21898 // MIs[1] Operand 1
21899 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21900 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21901 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21902 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21903 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21904 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21905 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21906 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21907 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21908 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21909 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21910 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21911 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21912 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
21913 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21914 GIR_RootToRootCopy, /*OpIdx*/2, // T
21915 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21916 GIR_RootToRootCopy, /*OpIdx*/3, // F
21917 GIR_RootConstrainSelectedInstOperands,
21918 // GIR_Coverage, 1725,
21919 GIR_EraseRootFromParent_Done,
21920 // Label 1279: @56758
21921 GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(56856), // Rule ID 1727 //
21922 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21923 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21924 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21925 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21926 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21927 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21928 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21929 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21930 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21931 // MIs[1] Operand 1
21932 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
21933 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21934 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
21935 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21936 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21937 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21938 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
21939 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
21940 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
21941 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21942 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21943 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21944 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21945 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
21946 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21947 GIR_RootToRootCopy, /*OpIdx*/2, // T
21948 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21949 GIR_RootToRootCopy, /*OpIdx*/3, // F
21950 GIR_RootConstrainSelectedInstOperands,
21951 // GIR_Coverage, 1727,
21952 GIR_EraseRootFromParent_Done,
21953 // Label 1280: @56856
21954 GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(56954), // Rule ID 1729 //
21955 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21956 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21957 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21958 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21959 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21960 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21961 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21962 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
21963 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
21964 // MIs[1] Operand 1
21965 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21966 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21967 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
21968 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21969 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21970 GIM_CheckIsSafeToFold, /*NumInsns*/1,
21971 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
21972 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
21973 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
21974 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
21975 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
21976 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
21977 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
21978 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
21979 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
21980 GIR_RootToRootCopy, /*OpIdx*/2, // T
21981 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
21982 GIR_RootToRootCopy, /*OpIdx*/3, // F
21983 GIR_RootConstrainSelectedInstOperands,
21984 // GIR_Coverage, 1729,
21985 GIR_EraseRootFromParent_Done,
21986 // Label 1281: @56954
21987 GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(57052), // Rule ID 1732 //
21988 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
21989 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
21990 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21991 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21992 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
21993 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
21994 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
21995 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
21996 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
21997 // MIs[1] Operand 1
21998 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
21999 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22000 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22001 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22002 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22003 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22004 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
22005 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22006 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
22007 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22008 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22009 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22010 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22013 GIR_RootToRootCopy, /*OpIdx*/2, // T
22014 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22015 GIR_RootToRootCopy, /*OpIdx*/3, // F
22016 GIR_RootConstrainSelectedInstOperands,
22017 // GIR_Coverage, 1732,
22018 GIR_EraseRootFromParent_Done,
22019 // Label 1282: @57052
22020 GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(57150), // Rule ID 2253 //
22021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22022 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22023 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22024 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22025 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22026 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22027 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22028 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22029 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22030 // MIs[1] Operand 1
22031 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
22032 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22033 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22034 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22035 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22036 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22037 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22038 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22039 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
22040 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22041 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22042 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22043 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22044 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22045 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22046 GIR_RootToRootCopy, /*OpIdx*/2, // T
22047 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22048 GIR_RootToRootCopy, /*OpIdx*/3, // F
22049 GIR_RootConstrainSelectedInstOperands,
22050 // GIR_Coverage, 2253,
22051 GIR_EraseRootFromParent_Done,
22052 // Label 1283: @57150
22053 GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(57248), // Rule ID 2254 //
22054 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22055 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22056 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22057 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22058 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22060 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22061 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22062 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22063 // MIs[1] Operand 1
22064 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
22065 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22066 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22067 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22068 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22069 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22070 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22071 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22072 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
22073 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22074 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22075 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22076 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22077 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22078 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22079 GIR_RootToRootCopy, /*OpIdx*/2, // T
22080 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22081 GIR_RootToRootCopy, /*OpIdx*/3, // F
22082 GIR_RootConstrainSelectedInstOperands,
22083 // GIR_Coverage, 2254,
22084 GIR_EraseRootFromParent_Done,
22085 // Label 1284: @57248
22086 GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(57346), // Rule ID 2257 //
22087 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22088 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22089 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22090 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22091 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22092 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22093 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22094 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22095 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22096 // MIs[1] Operand 1
22097 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
22098 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22099 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22100 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22101 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22102 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22103 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
22104 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22105 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
22106 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22107 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22108 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22109 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22110 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22111 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22112 GIR_RootToRootCopy, /*OpIdx*/2, // T
22113 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22114 GIR_RootToRootCopy, /*OpIdx*/3, // F
22115 GIR_RootConstrainSelectedInstOperands,
22116 // GIR_Coverage, 2257,
22117 GIR_EraseRootFromParent_Done,
22118 // Label 1285: @57346
22119 GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(57444), // Rule ID 2258 //
22120 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22121 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22122 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22123 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22126 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22127 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22128 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22129 // MIs[1] Operand 1
22130 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
22131 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22132 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22133 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22134 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22135 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22136 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
22137 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22138 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
22139 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22140 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22141 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22142 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22143 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22144 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22145 GIR_RootToRootCopy, /*OpIdx*/2, // T
22146 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22147 GIR_RootToRootCopy, /*OpIdx*/3, // F
22148 GIR_RootConstrainSelectedInstOperands,
22149 // GIR_Coverage, 2258,
22150 GIR_EraseRootFromParent_Done,
22151 // Label 1286: @57444
22152 GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(57542), // Rule ID 2261 //
22153 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22154 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22155 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22156 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22157 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22158 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22159 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22160 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22161 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22162 // MIs[1] Operand 1
22163 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
22164 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22165 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22166 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22167 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22168 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22169 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22170 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22171 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22172 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22173 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22174 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22175 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22176 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
22177 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22178 GIR_RootToRootCopy, /*OpIdx*/2, // T
22179 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22180 GIR_RootToRootCopy, /*OpIdx*/3, // F
22181 GIR_RootConstrainSelectedInstOperands,
22182 // GIR_Coverage, 2261,
22183 GIR_EraseRootFromParent_Done,
22184 // Label 1287: @57542
22185 GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(57640), // Rule ID 2263 //
22186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22187 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22188 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22189 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22190 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22191 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22192 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
22193 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22194 GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
22195 // MIs[1] Operand 1
22196 GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
22197 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22198 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22199 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22200 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22201 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22202 // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
22203 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
22204 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
22205 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22206 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
22207 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
22208 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22209 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22210 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22211 GIR_RootToRootCopy, /*OpIdx*/2, // T
22212 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22213 GIR_RootToRootCopy, /*OpIdx*/3, // F
22214 GIR_RootConstrainSelectedInstOperands,
22215 // GIR_Coverage, 2263,
22216 GIR_EraseRootFromParent_Done,
22217 // Label 1288: @57640
22218 GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(57680), // Rule ID 296 //
22219 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
22220 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22221 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22222 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22224 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22225 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22226 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22227 // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
22228 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
22229 GIR_RootConstrainSelectedInstOperands,
22230 // GIR_Coverage, 296,
22231 GIR_Done,
22232 // Label 1289: @57680
22233 GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(57720), // Rule ID 298 //
22234 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotMips4_32),
22235 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22236 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22237 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22238 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22239 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22240 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22241 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22242 // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
22243 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
22244 GIR_RootConstrainSelectedInstOperands,
22245 // GIR_Coverage, 298,
22246 GIR_Done,
22247 // Label 1290: @57720
22248 GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(57760), // Rule ID 299 //
22249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotMips4_32),
22250 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22251 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22252 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22253 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22254 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22255 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22256 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22257 // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
22258 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
22259 GIR_RootConstrainSelectedInstOperands,
22260 // GIR_Coverage, 299,
22261 GIR_Done,
22262 // Label 1291: @57760
22263 GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(57806), // Rule ID 1662 //
22264 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22265 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22266 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22267 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22268 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22269 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22270 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22271 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22272 // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
22273 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
22274 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22275 GIR_RootToRootCopy, /*OpIdx*/2, // T
22276 GIR_RootToRootCopy, /*OpIdx*/1, // cond
22277 GIR_RootToRootCopy, /*OpIdx*/3, // F
22278 GIR_RootConstrainSelectedInstOperands,
22279 // GIR_Coverage, 1662,
22280 GIR_EraseRootFromParent_Done,
22281 // Label 1292: @57806
22282 GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(57852), // Rule ID 1668 //
22283 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22284 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22285 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22286 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22287 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22288 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22289 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22290 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22291 // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
22292 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
22293 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22294 GIR_RootToRootCopy, /*OpIdx*/2, // T
22295 GIR_RootToRootCopy, /*OpIdx*/1, // cond
22296 GIR_RootToRootCopy, /*OpIdx*/3, // F
22297 GIR_RootConstrainSelectedInstOperands,
22298 // GIR_Coverage, 1668,
22299 GIR_EraseRootFromParent_Done,
22300 // Label 1293: @57852
22301 GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(57898), // Rule ID 1707 //
22302 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22303 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22304 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22305 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22306 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22307 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22308 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22309 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22310 // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22311 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
22312 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22313 GIR_RootToRootCopy, /*OpIdx*/2, // T
22314 GIR_RootToRootCopy, /*OpIdx*/1, // cond
22315 GIR_RootToRootCopy, /*OpIdx*/3, // F
22316 GIR_RootConstrainSelectedInstOperands,
22317 // GIR_Coverage, 1707,
22318 GIR_EraseRootFromParent_Done,
22319 // Label 1294: @57898
22320 GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(57944), // Rule ID 1730 //
22321 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22322 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22323 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22324 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22325 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22326 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22327 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22328 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22329 // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
22330 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
22331 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22332 GIR_RootToRootCopy, /*OpIdx*/2, // T
22333 GIR_RootToRootCopy, /*OpIdx*/1, // cond
22334 GIR_RootToRootCopy, /*OpIdx*/3, // F
22335 GIR_RootConstrainSelectedInstOperands,
22336 // GIR_Coverage, 1730,
22337 GIR_EraseRootFromParent_Done,
22338 // Label 1295: @57944
22339 GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(57990), // Rule ID 1733 //
22340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22341 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22342 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22343 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22344 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22345 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22346 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22347 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22348 // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
22349 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
22350 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22351 GIR_RootToRootCopy, /*OpIdx*/2, // T
22352 GIR_RootToRootCopy, /*OpIdx*/1, // cond
22353 GIR_RootToRootCopy, /*OpIdx*/3, // F
22354 GIR_RootConstrainSelectedInstOperands,
22355 // GIR_Coverage, 1733,
22356 GIR_EraseRootFromParent_Done,
22357 // Label 1296: @57990
22358 GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(58036), // Rule ID 2264 //
22359 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
22360 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22361 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22362 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22363 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22364 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22365 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22366 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22367 // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
22368 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
22369 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22370 GIR_RootToRootCopy, /*OpIdx*/2, // T
22371 GIR_RootToRootCopy, /*OpIdx*/1, // cond
22372 GIR_RootToRootCopy, /*OpIdx*/3, // F
22373 GIR_RootConstrainSelectedInstOperands,
22374 // GIR_Coverage, 2264,
22375 GIR_EraseRootFromParent_Done,
22376 // Label 1297: @58036
22377 GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(58114), // Rule ID 1772 //
22378 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
22379 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22380 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22381 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22382 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22383 // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
22384 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22385 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
22386 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
22387 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22388 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
22389 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22390 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22391 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
22392 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22393 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22394 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
22395 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22396 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
22397 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22398 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22399 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
22400 GIR_RootConstrainSelectedInstOperands,
22401 // GIR_Coverage, 1772,
22402 GIR_EraseRootFromParent_Done,
22403 // Label 1298: @58114
22404 GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(58226), // Rule ID 1783 //
22405 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
22406 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22407 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22408 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22409 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22410 // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
22411 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
22412 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
22413 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
22414 GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
22415 GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
22416 GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22417 GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
22418 GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
22419 GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
22420 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22421 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
22422 GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
22423 GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
22424 GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
22425 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22426 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
22427 GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
22428 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
22429 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
22430 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
22431 GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
22432 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
22433 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
22434 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
22435 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
22436 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
22437 GIR_RootConstrainSelectedInstOperands,
22438 // GIR_Coverage, 1783,
22439 GIR_EraseRootFromParent_Done,
22440 // Label 1299: @58226
22441 GIM_Reject,
22442 // Label 1156: @58227
22443 GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(58300),
22444 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22445 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22446 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22447 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22448 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22449 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22450 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22451 GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(58278), // Rule ID 583 //
22452 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22453 // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) => (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
22454 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
22455 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22456 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22457 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22458 GIR_RootToRootCopy, /*OpIdx*/2, // wt
22459 GIR_RootConstrainSelectedInstOperands,
22460 // GIR_Coverage, 583,
22461 GIR_EraseRootFromParent_Done,
22462 // Label 1301: @58278
22463 GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(58299), // Rule ID 585 //
22464 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22465 // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) => (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22466 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
22467 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22468 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22469 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22470 GIR_RootToRootCopy, /*OpIdx*/2, // wt
22471 GIR_RootConstrainSelectedInstOperands,
22472 // GIR_Coverage, 585,
22473 GIR_EraseRootFromParent_Done,
22474 // Label 1302: @58299
22475 GIM_Reject,
22476 // Label 1300: @58300
22477 GIM_Reject,
22478 // Label 1157: @58301
22479 GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(58374),
22480 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22481 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22482 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22483 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22484 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22485 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22486 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22487 GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(58352), // Rule ID 582 //
22488 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22489 // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) => (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
22490 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
22491 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22492 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22493 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22494 GIR_RootToRootCopy, /*OpIdx*/2, // wt
22495 GIR_RootConstrainSelectedInstOperands,
22496 // GIR_Coverage, 582,
22497 GIR_EraseRootFromParent_Done,
22498 // Label 1304: @58352
22499 GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(58373), // Rule ID 584 //
22500 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22501 // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) => (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22502 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
22503 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22504 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22505 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22506 GIR_RootToRootCopy, /*OpIdx*/2, // wt
22507 GIR_RootConstrainSelectedInstOperands,
22508 // GIR_Coverage, 584,
22509 GIR_EraseRootFromParent_Done,
22510 // Label 1305: @58373
22511 GIM_Reject,
22512 // Label 1303: @58374
22513 GIM_Reject,
22514 // Label 1158: @58375
22515 GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(58421), // Rule ID 581 //
22516 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22517 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
22518 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22519 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22520 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22521 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22522 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22523 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
22524 // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) => (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
22525 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
22526 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22527 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22528 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22529 GIR_RootToRootCopy, /*OpIdx*/2, // wt
22530 GIR_RootConstrainSelectedInstOperands,
22531 // GIR_Coverage, 581,
22532 GIR_EraseRootFromParent_Done,
22533 // Label 1306: @58421
22534 GIM_Reject,
22535 // Label 1159: @58422
22536 GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(58516),
22537 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
22538 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22539 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22541 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22542 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22543 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
22544 GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(58473), // Rule ID 568 //
22545 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22546 // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22547 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
22548 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22549 GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
22550 GIR_RootToRootCopy, /*OpIdx*/2, // ws
22551 GIR_RootToRootCopy, /*OpIdx*/1, // wt
22552 GIR_RootConstrainSelectedInstOperands,
22553 // GIR_Coverage, 568,
22554 GIR_EraseRootFromParent_Done,
22555 // Label 1308: @58473
22556 GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(58494), // Rule ID 570 //
22557 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22558 // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22559 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
22560 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22561 GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
22562 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22563 GIR_RootToRootCopy, /*OpIdx*/1, // wt
22564 GIR_RootConstrainSelectedInstOperands,
22565 // GIR_Coverage, 570,
22566 GIR_EraseRootFromParent_Done,
22567 // Label 1309: @58494
22568 GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(58515), // Rule ID 580 //
22569 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22570 // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) => (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
22571 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
22572 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22573 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
22574 GIR_RootToRootCopy, /*OpIdx*/3, // ws
22575 GIR_RootToRootCopy, /*OpIdx*/2, // wt
22576 GIR_RootConstrainSelectedInstOperands,
22577 // GIR_Coverage, 580,
22578 GIR_EraseRootFromParent_Done,
22579 // Label 1310: @58515
22580 GIM_Reject,
22581 // Label 1307: @58516
22582 GIM_Reject,
22583 // Label 1160: @58517
22584 GIM_Reject,
22585 // Label 31: @58518
22586 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1313*/ GIMT_Encode4(58626),
22587 /*GILLT_s32*//*Label 1311*/ GIMT_Encode4(58537),
22588 /*GILLT_s64*//*Label 1312*/ GIMT_Encode4(58592),
22589 // Label 1311: @58537
22590 GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(58591),
22591 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22592 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22593 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22594 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22595 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22596 GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(58575), // Rule ID 331 //
22597 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
22598 // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
22600 GIR_RootConstrainSelectedInstOperands,
22601 // GIR_Coverage, 331,
22602 GIR_Done,
22603 // Label 1315: @58575
22604 GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(58590), // Rule ID 1181 //
22605 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
22606 // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22607 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
22608 GIR_RootConstrainSelectedInstOperands,
22609 // GIR_Coverage, 1181,
22610 GIR_Done,
22611 // Label 1316: @58590
22612 GIM_Reject,
22613 // Label 1314: @58591
22614 GIM_Reject,
22615 // Label 1312: @58592
22616 GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(58625), // Rule ID 346 //
22617 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
22618 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22619 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22620 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22621 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22622 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22623 // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
22624 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
22625 GIR_RootConstrainSelectedInstOperands,
22626 // GIR_Coverage, 346,
22627 GIR_Done,
22628 // Label 1317: @58625
22629 GIM_Reject,
22630 // Label 1313: @58626
22631 GIM_Reject,
22632 // Label 32: @58627
22633 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1320*/ GIMT_Encode4(58735),
22634 /*GILLT_s32*//*Label 1318*/ GIMT_Encode4(58646),
22635 /*GILLT_s64*//*Label 1319*/ GIMT_Encode4(58701),
22636 // Label 1318: @58646
22637 GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(58700),
22638 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22639 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22640 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22641 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22642 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
22643 GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(58684), // Rule ID 330 //
22644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
22645 // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22646 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
22647 GIR_RootConstrainSelectedInstOperands,
22648 // GIR_Coverage, 330,
22649 GIR_Done,
22650 // Label 1322: @58684
22651 GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(58699), // Rule ID 1180 //
22652 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
22653 // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
22654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
22655 GIR_RootConstrainSelectedInstOperands,
22656 // GIR_Coverage, 1180,
22657 GIR_Done,
22658 // Label 1323: @58699
22659 GIM_Reject,
22660 // Label 1321: @58700
22661 GIM_Reject,
22662 // Label 1319: @58701
22663 GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(58734), // Rule ID 345 //
22664 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
22665 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22666 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22667 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22668 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22669 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
22670 // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
22671 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
22672 GIR_RootConstrainSelectedInstOperands,
22673 // GIR_Coverage, 345,
22674 GIR_Done,
22675 // Label 1324: @58734
22676 GIM_Reject,
22677 // Label 1320: @58735
22678 GIM_Reject,
22679 // Label 33: @58736
22680 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1329*/ GIMT_Encode4(59648),
22681 /*GILLT_s32*//*Label 1325*/ GIMT_Encode4(58771),
22682 /*GILLT_s64*//*Label 1326*/ GIMT_Encode4(58975), GIMT_Encode4(0),
22683 /*GILLT_v2s64*//*Label 1327*/ GIMT_Encode4(59340), GIMT_Encode4(0),
22684 /*GILLT_v4s32*//*Label 1328*/ GIMT_Encode4(59494),
22685 // Label 1325: @58771
22686 GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(58974),
22687 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
22688 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22689 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22690 GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(58843), // Rule ID 163 //
22691 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22692 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22693 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22694 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22695 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22696 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22697 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22698 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22699 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22700 // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22701 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22702 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22703 GIR_RootToRootCopy, /*OpIdx*/2, // fr
22704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22706 GIR_RootConstrainSelectedInstOperands,
22707 // GIR_Coverage, 163,
22708 GIR_EraseRootFromParent_Done,
22709 // Label 1331: @58843
22710 GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(58900), // Rule ID 2328 //
22711 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22712 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22713 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22714 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22715 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
22716 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
22717 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22718 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22719 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22720 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22721 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
22722 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22723 GIR_RootToRootCopy, /*OpIdx*/1, // fr
22724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22725 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22726 GIR_RootConstrainSelectedInstOperands,
22727 // GIR_Coverage, 2328,
22728 GIR_EraseRootFromParent_Done,
22729 // Label 1332: @58900
22730 GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(58923), // Rule ID 151 //
22731 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
22732 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22733 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22734 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22735 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
22736 GIR_RootConstrainSelectedInstOperands,
22737 // GIR_Coverage, 151,
22738 GIR_Done,
22739 // Label 1333: @58923
22740 GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(58946), // Rule ID 1130 //
22741 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
22742 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22743 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22744 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
22745 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
22746 GIR_RootConstrainSelectedInstOperands,
22747 // GIR_Coverage, 1130,
22748 GIR_Done,
22749 // Label 1334: @58946
22750 GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(58973), // Rule ID 1188 //
22751 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
22752 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22753 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
22754 // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
22755 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
22756 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22757 GIR_RootToRootCopy, /*OpIdx*/2, // ft
22758 GIR_RootToRootCopy, /*OpIdx*/1, // fs
22759 GIR_RootConstrainSelectedInstOperands,
22760 // GIR_Coverage, 1188,
22761 GIR_EraseRootFromParent_Done,
22762 // Label 1335: @58973
22763 GIM_Reject,
22764 // Label 1330: @58974
22765 GIM_Reject,
22766 // Label 1326: @58975
22767 GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(59339),
22768 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
22769 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22770 GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(59047), // Rule ID 165 //
22771 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22772 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22773 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22774 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22775 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22776 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22777 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22778 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22779 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22780 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22781 // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22782 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22783 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22784 GIR_RootToRootCopy, /*OpIdx*/2, // fr
22785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22787 GIR_RootConstrainSelectedInstOperands,
22788 // GIR_Coverage, 165,
22789 GIR_EraseRootFromParent_Done,
22790 // Label 1337: @59047
22791 GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(59108), // Rule ID 167 //
22792 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22793 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22794 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22795 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22796 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22797 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22798 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22800 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22801 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22802 // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22803 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22804 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22805 GIR_RootToRootCopy, /*OpIdx*/2, // fr
22806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22808 GIR_RootConstrainSelectedInstOperands,
22809 // GIR_Coverage, 167,
22810 GIR_EraseRootFromParent_Done,
22811 // Label 1338: @59108
22812 GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(59169), // Rule ID 2329 //
22813 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
22814 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22815 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22817 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22818 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22819 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22820 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22822 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22823 // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22824 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
22825 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22826 GIR_RootToRootCopy, /*OpIdx*/1, // fr
22827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22829 GIR_RootConstrainSelectedInstOperands,
22830 // GIR_Coverage, 2329,
22831 GIR_EraseRootFromParent_Done,
22832 // Label 1339: @59169
22833 GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(59230), // Rule ID 2330 //
22834 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
22835 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22836 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22837 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22838 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22839 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
22840 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
22841 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22842 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22843 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22844 // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22845 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
22846 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
22847 GIR_RootToRootCopy, /*OpIdx*/1, // fr
22848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
22849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
22850 GIR_RootConstrainSelectedInstOperands,
22851 // GIR_Coverage, 2330,
22852 GIR_EraseRootFromParent_Done,
22853 // Label 1340: @59230
22854 GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(59257), // Rule ID 152 //
22855 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
22856 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22857 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22858 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22859 // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22860 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
22861 GIR_RootConstrainSelectedInstOperands,
22862 // GIR_Coverage, 152,
22863 GIR_Done,
22864 // Label 1341: @59257
22865 GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(59284), // Rule ID 153 //
22866 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
22867 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22868 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22869 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22870 // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22871 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
22872 GIR_RootConstrainSelectedInstOperands,
22873 // GIR_Coverage, 153,
22874 GIR_Done,
22875 // Label 1342: @59284
22876 GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(59311), // Rule ID 1134 //
22877 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
22878 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22879 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22880 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
22881 // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
22882 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
22883 GIR_RootConstrainSelectedInstOperands,
22884 // GIR_Coverage, 1134,
22885 GIR_Done,
22886 // Label 1343: @59311
22887 GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(59338), // Rule ID 1135 //
22888 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
22889 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22890 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22891 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
22892 // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
22893 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
22894 GIR_RootConstrainSelectedInstOperands,
22895 // GIR_Coverage, 1135,
22896 GIR_Done,
22897 // Label 1344: @59338
22898 GIM_Reject,
22899 // Label 1336: @59339
22900 GIM_Reject,
22901 // Label 1327: @59340
22902 GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(59493),
22903 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
22904 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22905 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22906 GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(59412), // Rule ID 2435 //
22907 GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
22908 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22909 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22910 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22911 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
22912 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22913 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22914 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22915 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22916 // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22917 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
22918 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22919 GIR_RootToRootCopy, /*OpIdx*/2, // wd
22920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22922 GIR_RootConstrainSelectedInstOperands,
22923 // GIR_Coverage, 2435,
22924 GIR_EraseRootFromParent_Done,
22925 // Label 1346: @59412
22926 GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(59469), // Rule ID 1967 //
22927 GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
22928 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22929 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22930 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22931 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
22932 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
22933 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22934 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22935 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22936 // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22937 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
22938 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22939 GIR_RootToRootCopy, /*OpIdx*/1, // wd
22940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22942 GIR_RootConstrainSelectedInstOperands,
22943 // GIR_Coverage, 1967,
22944 GIR_EraseRootFromParent_Done,
22945 // Label 1347: @59469
22946 GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(59492), // Rule ID 671 //
22947 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
22948 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22949 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
22950 // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
22951 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
22952 GIR_RootConstrainSelectedInstOperands,
22953 // GIR_Coverage, 671,
22954 GIR_Done,
22955 // Label 1348: @59492
22956 GIM_Reject,
22957 // Label 1345: @59493
22958 GIM_Reject,
22959 // Label 1328: @59494
22960 GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(59647),
22961 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
22962 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22963 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22964 GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(59566), // Rule ID 2434 //
22965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
22966 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
22967 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22968 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22969 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22970 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22971 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22972 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22973 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22974 // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22975 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
22976 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22977 GIR_RootToRootCopy, /*OpIdx*/2, // wd
22978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
22980 GIR_RootConstrainSelectedInstOperands,
22981 // GIR_Coverage, 2434,
22982 GIR_EraseRootFromParent_Done,
22983 // Label 1350: @59566
22984 GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(59623), // Rule ID 1966 //
22985 GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
22986 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22987 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
22988 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
22989 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
22990 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
22991 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22992 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
22993 GIM_CheckIsSafeToFold, /*NumInsns*/1,
22994 // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
22995 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
22996 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
22997 GIR_RootToRootCopy, /*OpIdx*/1, // wd
22998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
22999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23000 GIR_RootConstrainSelectedInstOperands,
23001 // GIR_Coverage, 1966,
23002 GIR_EraseRootFromParent_Done,
23003 // Label 1351: @59623
23004 GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(59646), // Rule ID 670 //
23005 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23006 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23007 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23008 // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23009 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
23010 GIR_RootConstrainSelectedInstOperands,
23011 // GIR_Coverage, 670,
23012 GIR_Done,
23013 // Label 1352: @59646
23014 GIM_Reject,
23015 // Label 1349: @59647
23016 GIM_Reject,
23017 // Label 1329: @59648
23018 GIM_Reject,
23019 // Label 34: @59649
23020 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1357*/ GIMT_Encode4(60260),
23021 /*GILLT_s32*//*Label 1353*/ GIMT_Encode4(59684),
23022 /*GILLT_s64*//*Label 1354*/ GIMT_Encode4(59831), GIMT_Encode4(0),
23023 /*GILLT_v2s64*//*Label 1355*/ GIMT_Encode4(60074), GIMT_Encode4(0),
23024 /*GILLT_v4s32*//*Label 1356*/ GIMT_Encode4(60167),
23025 // Label 1353: @59684
23026 GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(59830),
23027 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23028 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23029 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23030 GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(59756), // Rule ID 164 //
23031 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23032 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23033 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23034 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23035 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23036 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23037 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23038 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23039 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23040 // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23041 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
23042 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23043 GIR_RootToRootCopy, /*OpIdx*/2, // fr
23044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23046 GIR_RootConstrainSelectedInstOperands,
23047 // GIR_Coverage, 164,
23048 GIR_EraseRootFromParent_Done,
23049 // Label 1359: @59756
23050 GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(59779), // Rule ID 160 //
23051 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
23052 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23053 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23054 // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23055 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
23056 GIR_RootConstrainSelectedInstOperands,
23057 // GIR_Coverage, 160,
23058 GIR_Done,
23059 // Label 1360: @59779
23060 GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(59802), // Rule ID 1133 //
23061 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
23062 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23063 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23064 // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
23066 GIR_RootConstrainSelectedInstOperands,
23067 // GIR_Coverage, 1133,
23068 GIR_Done,
23069 // Label 1361: @59802
23070 GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(59829), // Rule ID 1189 //
23071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
23072 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23073 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23074 // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23075 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
23076 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23077 GIR_RootToRootCopy, /*OpIdx*/2, // ft
23078 GIR_RootToRootCopy, /*OpIdx*/1, // fs
23079 GIR_RootConstrainSelectedInstOperands,
23080 // GIR_Coverage, 1189,
23081 GIR_EraseRootFromParent_Done,
23082 // Label 1362: @59829
23083 GIM_Reject,
23084 // Label 1358: @59830
23085 GIM_Reject,
23086 // Label 1354: @59831
23087 GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(60073),
23088 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23089 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23090 GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(59903), // Rule ID 166 //
23091 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23092 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23093 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23094 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23095 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23096 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23097 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23098 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23099 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23100 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23101 // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23102 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
23103 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23104 GIR_RootToRootCopy, /*OpIdx*/2, // fr
23105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23107 GIR_RootConstrainSelectedInstOperands,
23108 // GIR_Coverage, 166,
23109 GIR_EraseRootFromParent_Done,
23110 // Label 1364: @59903
23111 GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(59964), // Rule ID 168 //
23112 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
23113 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23114 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23115 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23116 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23117 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23118 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23119 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23120 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23121 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23122 // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23123 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
23124 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23125 GIR_RootToRootCopy, /*OpIdx*/2, // fr
23126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
23127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
23128 GIR_RootConstrainSelectedInstOperands,
23129 // GIR_Coverage, 168,
23130 GIR_EraseRootFromParent_Done,
23131 // Label 1365: @59964
23132 GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(59991), // Rule ID 161 //
23133 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
23134 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23135 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23136 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23137 // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
23139 GIR_RootConstrainSelectedInstOperands,
23140 // GIR_Coverage, 161,
23141 GIR_Done,
23142 // Label 1366: @59991
23143 GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(60018), // Rule ID 162 //
23144 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
23145 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23146 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23147 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23148 // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23149 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
23150 GIR_RootConstrainSelectedInstOperands,
23151 // GIR_Coverage, 162,
23152 GIR_Done,
23153 // Label 1367: @60018
23154 GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(60045), // Rule ID 1140 //
23155 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
23156 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23157 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23158 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23159 // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23160 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
23161 GIR_RootConstrainSelectedInstOperands,
23162 // GIR_Coverage, 1140,
23163 GIR_Done,
23164 // Label 1368: @60045
23165 GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(60072), // Rule ID 1141 //
23166 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
23167 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23168 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23169 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23170 // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23171 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
23172 GIR_RootConstrainSelectedInstOperands,
23173 // GIR_Coverage, 1141,
23174 GIR_Done,
23175 // Label 1369: @60072
23176 GIM_Reject,
23177 // Label 1363: @60073
23178 GIM_Reject,
23179 // Label 1355: @60074
23180 GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(60166),
23181 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23182 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23184 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23185 GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(60146), // Rule ID 1965 //
23186 GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
23187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23188 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23189 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23190 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
23191 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23192 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23193 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23194 // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23195 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
23196 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23197 GIR_RootToRootCopy, /*OpIdx*/1, // wd
23198 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23200 GIR_RootConstrainSelectedInstOperands,
23201 // GIR_Coverage, 1965,
23202 GIR_EraseRootFromParent_Done,
23203 // Label 1371: @60146
23204 GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(60165), // Rule ID 759 //
23205 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23206 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23207 // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23208 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
23209 GIR_RootConstrainSelectedInstOperands,
23210 // GIR_Coverage, 759,
23211 GIR_Done,
23212 // Label 1372: @60165
23213 GIM_Reject,
23214 // Label 1370: @60166
23215 GIM_Reject,
23216 // Label 1356: @60167
23217 GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(60259),
23218 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23220 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23221 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23222 GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(60239), // Rule ID 1964 //
23223 GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
23224 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23225 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
23226 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23227 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
23228 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23229 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23230 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23231 // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23232 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
23233 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23234 GIR_RootToRootCopy, /*OpIdx*/1, // wd
23235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
23236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
23237 GIR_RootConstrainSelectedInstOperands,
23238 // GIR_Coverage, 1964,
23239 GIR_EraseRootFromParent_Done,
23240 // Label 1374: @60239
23241 GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(60258), // Rule ID 758 //
23242 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23243 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23244 // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23245 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
23246 GIR_RootConstrainSelectedInstOperands,
23247 // GIR_Coverage, 758,
23248 GIR_Done,
23249 // Label 1375: @60258
23250 GIM_Reject,
23251 // Label 1373: @60259
23252 GIM_Reject,
23253 // Label 1357: @60260
23254 GIM_Reject,
23255 // Label 35: @60261
23256 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1380*/ GIMT_Encode4(60747),
23257 /*GILLT_s32*//*Label 1376*/ GIMT_Encode4(60296),
23258 /*GILLT_s64*//*Label 1377*/ GIMT_Encode4(60370), GIMT_Encode4(0),
23259 /*GILLT_v2s64*//*Label 1378*/ GIMT_Encode4(60491), GIMT_Encode4(0),
23260 /*GILLT_v4s32*//*Label 1379*/ GIMT_Encode4(60619),
23261 // Label 1376: @60296
23262 GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(60369),
23263 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23266 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23267 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23268 GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(60334), // Rule ID 157 //
23269 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
23270 // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23271 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
23272 GIR_RootConstrainSelectedInstOperands,
23273 // GIR_Coverage, 157,
23274 GIR_Done,
23275 // Label 1382: @60334
23276 GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(60349), // Rule ID 1132 //
23277 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
23278 // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23279 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
23280 GIR_RootConstrainSelectedInstOperands,
23281 // GIR_Coverage, 1132,
23282 GIR_Done,
23283 // Label 1383: @60349
23284 GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(60368), // Rule ID 1190 //
23285 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
23286 // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23287 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
23288 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23289 GIR_RootToRootCopy, /*OpIdx*/2, // ft
23290 GIR_RootToRootCopy, /*OpIdx*/1, // fs
23291 GIR_RootConstrainSelectedInstOperands,
23292 // GIR_Coverage, 1190,
23293 GIR_EraseRootFromParent_Done,
23294 // Label 1384: @60368
23295 GIM_Reject,
23296 // Label 1381: @60369
23297 GIM_Reject,
23298 // Label 1377: @60370
23299 GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(60490),
23300 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23301 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23302 GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(60408), // Rule ID 158 //
23303 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
23304 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23305 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23306 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23307 // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23308 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
23309 GIR_RootConstrainSelectedInstOperands,
23310 // GIR_Coverage, 158,
23311 GIR_Done,
23312 // Label 1386: @60408
23313 GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(60435), // Rule ID 159 //
23314 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
23315 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23316 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23317 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23318 // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23319 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
23320 GIR_RootConstrainSelectedInstOperands,
23321 // GIR_Coverage, 159,
23322 GIR_Done,
23323 // Label 1387: @60435
23324 GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(60462), // Rule ID 1138 //
23325 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
23326 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23327 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23328 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23329 // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23330 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
23331 GIR_RootConstrainSelectedInstOperands,
23332 // GIR_Coverage, 1138,
23333 GIR_Done,
23334 // Label 1388: @60462
23335 GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(60489), // Rule ID 1139 //
23336 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
23337 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23338 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23339 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23340 // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23341 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
23342 GIR_RootConstrainSelectedInstOperands,
23343 // GIR_Coverage, 1139,
23344 GIR_Done,
23345 // Label 1389: @60489
23346 GIM_Reject,
23347 // Label 1385: @60490
23348 GIM_Reject,
23349 // Label 1378: @60491
23350 GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(60618),
23351 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23352 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23353 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23354 GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(60550), // Rule ID 2371 //
23355 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23356 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23357 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23358 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23359 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23360 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23361 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23362 // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23363 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
23364 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23365 GIR_RootToRootCopy, /*OpIdx*/2, // ws
23366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23367 GIR_RootConstrainSelectedInstOperands,
23368 // GIR_Coverage, 2371,
23369 GIR_EraseRootFromParent_Done,
23370 // Label 1391: @60550
23371 GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(60594), // Rule ID 701 //
23372 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23373 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23374 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23375 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23376 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
23377 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23378 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23379 // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23380 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
23381 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23382 GIR_RootToRootCopy, /*OpIdx*/1, // ws
23383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23384 GIR_RootConstrainSelectedInstOperands,
23385 // GIR_Coverage, 701,
23386 GIR_EraseRootFromParent_Done,
23387 // Label 1392: @60594
23388 GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(60617), // Rule ID 737 //
23389 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23390 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23391 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23392 // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
23394 GIR_RootConstrainSelectedInstOperands,
23395 // GIR_Coverage, 737,
23396 GIR_Done,
23397 // Label 1393: @60617
23398 GIM_Reject,
23399 // Label 1390: @60618
23400 GIM_Reject,
23401 // Label 1379: @60619
23402 GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(60746),
23403 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23404 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23406 GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(60678), // Rule ID 2370 //
23407 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23408 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23409 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23410 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23411 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23412 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23413 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23414 // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23415 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
23416 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23417 GIR_RootToRootCopy, /*OpIdx*/2, // ws
23418 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23419 GIR_RootConstrainSelectedInstOperands,
23420 // GIR_Coverage, 2370,
23421 GIR_EraseRootFromParent_Done,
23422 // Label 1395: @60678
23423 GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(60722), // Rule ID 700 //
23424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23425 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23426 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
23427 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
23428 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
23429 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23430 GIM_CheckIsSafeToFold, /*NumInsns*/1,
23431 // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23432 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
23433 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
23434 GIR_RootToRootCopy, /*OpIdx*/1, // ws
23435 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
23436 GIR_RootConstrainSelectedInstOperands,
23437 // GIR_Coverage, 700,
23438 GIR_EraseRootFromParent_Done,
23439 // Label 1396: @60722
23440 GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(60745), // Rule ID 736 //
23441 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23442 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23443 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23444 // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23445 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
23446 GIR_RootConstrainSelectedInstOperands,
23447 // GIR_Coverage, 736,
23448 GIR_Done,
23449 // Label 1397: @60745
23450 GIM_Reject,
23451 // Label 1394: @60746
23452 GIM_Reject,
23453 // Label 1380: @60747
23454 GIM_Reject,
23455 // Label 36: @60748
23456 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1400*/ GIMT_Encode4(60853),
23457 /*GILLT_v2s64*//*Label 1398*/ GIMT_Encode4(60771), GIMT_Encode4(0),
23458 /*GILLT_v4s32*//*Label 1399*/ GIMT_Encode4(60812),
23459 // Label 1398: @60771
23460 GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(60811), // Rule ID 725 //
23461 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23462 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23463 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23464 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23466 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23467 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23468 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23469 // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23470 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
23471 GIR_RootConstrainSelectedInstOperands,
23472 // GIR_Coverage, 725,
23473 GIR_Done,
23474 // Label 1401: @60811
23475 GIM_Reject,
23476 // Label 1399: @60812
23477 GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(60852), // Rule ID 724 //
23478 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23479 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23480 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23481 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23482 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23483 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23484 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23485 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23486 // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23487 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
23488 GIR_RootConstrainSelectedInstOperands,
23489 // GIR_Coverage, 724,
23490 GIR_Done,
23491 // Label 1402: @60852
23492 GIM_Reject,
23493 // Label 1400: @60853
23494 GIM_Reject,
23495 // Label 37: @60854
23496 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1407*/ GIMT_Encode4(61152),
23497 /*GILLT_s32*//*Label 1403*/ GIMT_Encode4(60889),
23498 /*GILLT_s64*//*Label 1404*/ GIMT_Encode4(60963), GIMT_Encode4(0),
23499 /*GILLT_v2s64*//*Label 1405*/ GIMT_Encode4(61084), GIMT_Encode4(0),
23500 /*GILLT_v4s32*//*Label 1406*/ GIMT_Encode4(61118),
23501 // Label 1403: @60889
23502 GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(60962),
23503 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23504 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23505 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23506 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23507 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23508 GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(60927), // Rule ID 154 //
23509 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
23510 // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23511 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
23512 GIR_RootConstrainSelectedInstOperands,
23513 // GIR_Coverage, 154,
23514 GIR_Done,
23515 // Label 1409: @60927
23516 GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(60942), // Rule ID 1131 //
23517 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
23518 // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23519 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
23520 GIR_RootConstrainSelectedInstOperands,
23521 // GIR_Coverage, 1131,
23522 GIR_Done,
23523 // Label 1410: @60942
23524 GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(60961), // Rule ID 1191 //
23525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
23526 // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
23527 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
23528 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23529 GIR_RootToRootCopy, /*OpIdx*/2, // ft
23530 GIR_RootToRootCopy, /*OpIdx*/1, // fs
23531 GIR_RootConstrainSelectedInstOperands,
23532 // GIR_Coverage, 1191,
23533 GIR_EraseRootFromParent_Done,
23534 // Label 1411: @60961
23535 GIM_Reject,
23536 // Label 1408: @60962
23537 GIM_Reject,
23538 // Label 1404: @60963
23539 GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(61083),
23540 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23541 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23542 GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(61001), // Rule ID 155 //
23543 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
23544 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23545 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23546 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23547 // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23548 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
23549 GIR_RootConstrainSelectedInstOperands,
23550 // GIR_Coverage, 155,
23551 GIR_Done,
23552 // Label 1413: @61001
23553 GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(61028), // Rule ID 156 //
23554 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
23555 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23556 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23557 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23558 // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23559 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
23560 GIR_RootConstrainSelectedInstOperands,
23561 // GIR_Coverage, 156,
23562 GIR_Done,
23563 // Label 1414: @61028
23564 GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(61055), // Rule ID 1136 //
23565 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
23566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23568 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23569 // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23570 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
23571 GIR_RootConstrainSelectedInstOperands,
23572 // GIR_Coverage, 1136,
23573 GIR_Done,
23574 // Label 1415: @61055
23575 GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(61082), // Rule ID 1137 //
23576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
23577 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23578 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23579 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23580 // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
23582 GIR_RootConstrainSelectedInstOperands,
23583 // GIR_Coverage, 1137,
23584 GIR_Done,
23585 // Label 1416: @61082
23586 GIM_Reject,
23587 // Label 1412: @61083
23588 GIM_Reject,
23589 // Label 1405: @61084
23590 GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(61117), // Rule ID 697 //
23591 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23592 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23593 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23594 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23595 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23596 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23597 // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
23598 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
23599 GIR_RootConstrainSelectedInstOperands,
23600 // GIR_Coverage, 697,
23601 GIR_Done,
23602 // Label 1417: @61117
23603 GIM_Reject,
23604 // Label 1406: @61118
23605 GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(61151), // Rule ID 696 //
23606 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23607 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23608 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23609 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23610 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23611 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23612 // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
23613 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
23614 GIR_RootConstrainSelectedInstOperands,
23615 // GIR_Coverage, 696,
23616 GIR_Done,
23617 // Label 1418: @61151
23618 GIM_Reject,
23619 // Label 1407: @61152
23620 GIM_Reject,
23621 // Label 38: @61153
23622 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1421*/ GIMT_Encode4(61230),
23623 /*GILLT_v2s64*//*Label 1419*/ GIMT_Encode4(61176), GIMT_Encode4(0),
23624 /*GILLT_v4s32*//*Label 1420*/ GIMT_Encode4(61203),
23625 // Label 1419: @61176
23626 GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(61202), // Rule ID 703 //
23627 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23628 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23629 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23630 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23631 // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
23632 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
23633 GIR_RootConstrainSelectedInstOperands,
23634 // GIR_Coverage, 703,
23635 GIR_Done,
23636 // Label 1422: @61202
23637 GIM_Reject,
23638 // Label 1420: @61203
23639 GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(61229), // Rule ID 702 //
23640 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23641 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23642 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23643 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23644 // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
23645 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
23646 GIR_RootConstrainSelectedInstOperands,
23647 // GIR_Coverage, 702,
23648 GIR_Done,
23649 // Label 1423: @61229
23650 GIM_Reject,
23651 // Label 1421: @61230
23652 GIM_Reject,
23653 // Label 39: @61231
23654 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1426*/ GIMT_Encode4(61308),
23655 /*GILLT_v2s64*//*Label 1424*/ GIMT_Encode4(61254), GIMT_Encode4(0),
23656 /*GILLT_v4s32*//*Label 1425*/ GIMT_Encode4(61281),
23657 // Label 1424: @61254
23658 GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(61280), // Rule ID 723 //
23659 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23660 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
23661 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23662 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
23663 // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
23664 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
23665 GIR_RootConstrainSelectedInstOperands,
23666 // GIR_Coverage, 723,
23667 GIR_Done,
23668 // Label 1427: @61280
23669 GIM_Reject,
23670 // Label 1425: @61281
23671 GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(61307), // Rule ID 722 //
23672 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
23673 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
23674 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23675 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
23676 // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
23677 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
23678 GIR_RootConstrainSelectedInstOperands,
23679 // GIR_Coverage, 722,
23680 GIR_Done,
23681 // Label 1428: @61307
23682 GIM_Reject,
23683 // Label 1426: @61308
23684 GIM_Reject,
23685 // Label 40: @61309
23686 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1431*/ GIMT_Encode4(62677),
23687 /*GILLT_s32*//*Label 1429*/ GIMT_Encode4(61328),
23688 /*GILLT_s64*//*Label 1430*/ GIMT_Encode4(61855),
23689 // Label 1429: @61328
23690 GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(61854),
23691 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
23692 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23693 GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(61416), // Rule ID 1458 //
23694 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
23695 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23696 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23697 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23698 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23699 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23700 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23701 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23702 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
23703 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23704 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23705 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23706 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23707 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23708 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
23709 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23711 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23713 GIR_RootConstrainSelectedInstOperands,
23714 // GIR_Coverage, 1458,
23715 GIR_EraseRootFromParent_Done,
23716 // Label 1433: @61416
23717 GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(61492), // Rule ID 2220 //
23718 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
23719 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23720 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23721 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23722 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23723 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23724 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23725 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23726 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
23727 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23728 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23729 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23730 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23731 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23732 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
23733 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23735 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23737 GIR_RootConstrainSelectedInstOperands,
23738 // GIR_Coverage, 2220,
23739 GIR_EraseRootFromParent_Done,
23740 // Label 1434: @61492
23741 GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(61568), // Rule ID 2406 //
23742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
23743 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23744 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23745 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23746 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23747 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23748 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23749 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23750 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23751 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
23752 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23753 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23754 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23755 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23756 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
23757 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23761 GIR_RootConstrainSelectedInstOperands,
23762 // GIR_Coverage, 2406,
23763 GIR_EraseRootFromParent_Done,
23764 // Label 1435: @61568
23765 GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(61644), // Rule ID 2492 //
23766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
23767 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23768 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23769 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23770 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23771 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23772 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23773 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23774 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23775 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
23776 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23777 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23778 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23779 // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23780 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
23781 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23785 GIR_RootConstrainSelectedInstOperands,
23786 // GIR_Coverage, 2492,
23787 GIR_EraseRootFromParent_Done,
23788 // Label 1436: @61644
23789 GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(61720), // Rule ID 1459 //
23790 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
23791 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23792 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
23793 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23794 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23795 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23796 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23797 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23798 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
23799 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23800 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23801 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23802 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23803 // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23804 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S),
23805 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23808 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23809 GIR_RootConstrainSelectedInstOperands,
23810 // GIR_Coverage, 1459,
23811 GIR_EraseRootFromParent_Done,
23812 // Label 1437: @61720
23813 GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(61796), // Rule ID 2221 //
23814 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
23815 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23816 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
23817 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
23818 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
23819 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23820 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23821 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
23822 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
23823 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23824 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23825 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23826 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23827 // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
23828 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S_MM),
23829 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23830 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23833 GIR_RootConstrainSelectedInstOperands,
23834 // GIR_Coverage, 2221,
23835 GIR_EraseRootFromParent_Done,
23836 // Label 1438: @61796
23837 GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(61815), // Rule ID 129 //
23838 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat),
23839 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23840 // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23841 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
23842 GIR_RootConstrainSelectedInstOperands,
23843 // GIR_Coverage, 129,
23844 GIR_Done,
23845 // Label 1439: @61815
23846 GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(61834), // Rule ID 1153 //
23847 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
23848 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23849 // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23850 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
23851 GIR_RootConstrainSelectedInstOperands,
23852 // GIR_Coverage, 1153,
23853 GIR_Done,
23854 // Label 1440: @61834
23855 GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(61853), // Rule ID 1192 //
23856 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
23857 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
23858 // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
23859 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
23860 GIR_RootConstrainSelectedInstOperands,
23861 // GIR_Coverage, 1192,
23862 GIR_Done,
23863 // Label 1441: @61853
23864 GIM_Reject,
23865 // Label 1432: @61854
23866 GIM_Reject,
23867 // Label 1430: @61855
23868 GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(62676),
23869 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
23870 GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(61943), // Rule ID 1460 //
23871 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23872 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23873 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23874 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23875 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23876 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23877 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23878 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23879 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23880 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23881 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23882 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23883 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23884 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23885 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23886 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
23887 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23891 GIR_RootConstrainSelectedInstOperands,
23892 // GIR_Coverage, 1460,
23893 GIR_EraseRootFromParent_Done,
23894 // Label 1443: @61943
23895 GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(62023), // Rule ID 1462 //
23896 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
23897 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23898 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23899 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23900 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23901 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23902 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23903 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23904 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23905 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23906 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23907 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23908 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23909 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23910 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23911 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
23912 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23916 GIR_RootConstrainSelectedInstOperands,
23917 // GIR_Coverage, 1462,
23918 GIR_EraseRootFromParent_Done,
23919 // Label 1444: @62023
23920 GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(62103), // Rule ID 2222 //
23921 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
23922 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23923 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23924 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23925 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23926 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23927 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
23928 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23929 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23930 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23931 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23932 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23933 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23934 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23935 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23936 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
23937 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
23939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23941 GIR_RootConstrainSelectedInstOperands,
23942 // GIR_Coverage, 2222,
23943 GIR_EraseRootFromParent_Done,
23944 // Label 1445: @62103
23945 GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(62183), // Rule ID 2407 //
23946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
23947 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23948 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23949 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23950 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23951 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23952 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23953 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23954 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23955 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23956 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23957 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23958 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23959 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23960 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
23961 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
23962 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23964 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23966 GIR_RootConstrainSelectedInstOperands,
23967 // GIR_Coverage, 2407,
23968 GIR_EraseRootFromParent_Done,
23969 // Label 1446: @62183
23970 GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(62263), // Rule ID 2408 //
23971 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
23972 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23973 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23974 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
23975 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
23976 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
23977 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23978 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
23979 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
23980 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
23981 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
23982 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23983 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
23984 GIM_CheckIsSafeToFold, /*NumInsns*/2,
23985 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
23986 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
23987 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
23988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
23989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
23990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
23991 GIR_RootConstrainSelectedInstOperands,
23992 // GIR_Coverage, 2408,
23993 GIR_EraseRootFromParent_Done,
23994 // Label 1447: @62263
23995 GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(62343), // Rule ID 2493 //
23996 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
23997 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
23998 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
23999 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
24000 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24001 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24002 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24003 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
24004 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24005 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
24006 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
24007 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24008 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24009 GIM_CheckIsSafeToFold, /*NumInsns*/2,
24010 // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24011 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
24012 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
24014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24016 GIR_RootConstrainSelectedInstOperands,
24017 // GIR_Coverage, 2493,
24018 GIR_EraseRootFromParent_Done,
24019 // Label 1448: @62343
24020 GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(62423), // Rule ID 1461 //
24021 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
24022 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24023 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24024 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
24025 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24026 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24027 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24028 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24029 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
24030 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
24031 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24032 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24033 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24034 GIM_CheckIsSafeToFold, /*NumInsns*/2,
24035 // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24036 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32),
24037 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24041 GIR_RootConstrainSelectedInstOperands,
24042 // GIR_Coverage, 1461,
24043 GIR_EraseRootFromParent_Done,
24044 // Label 1449: @62423
24045 GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(62503), // Rule ID 1463 //
24046 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
24047 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24048 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24049 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
24050 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24051 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24052 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24053 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24054 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
24055 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
24056 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24057 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24058 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24059 GIM_CheckIsSafeToFold, /*NumInsns*/2,
24060 // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
24061 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D64),
24062 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24066 GIR_RootConstrainSelectedInstOperands,
24067 // GIR_Coverage, 1463,
24068 GIR_EraseRootFromParent_Done,
24069 // Label 1450: @62503
24070 GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(62583), // Rule ID 2223 //
24071 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
24072 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24073 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
24074 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
24075 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
24076 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
24077 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
24078 GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
24079 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
24080 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
24081 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24082 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24083 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24084 GIM_CheckIsSafeToFold, /*NumInsns*/2,
24085 // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
24086 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32_MM),
24087 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
24089 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
24090 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
24091 GIR_RootConstrainSelectedInstOperands,
24092 // GIR_Coverage, 2223,
24093 GIR_EraseRootFromParent_Done,
24094 // Label 1451: @62583
24095 GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(62606), // Rule ID 130 //
24096 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
24097 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24098 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24099 // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
24101 GIR_RootConstrainSelectedInstOperands,
24102 // GIR_Coverage, 130,
24103 GIR_Done,
24104 // Label 1452: @62606
24105 GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(62629), // Rule ID 131 //
24106 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
24107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24109 // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24110 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
24111 GIR_RootConstrainSelectedInstOperands,
24112 // GIR_Coverage, 131,
24113 GIR_Done,
24114 // Label 1453: @62629
24115 GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(62652), // Rule ID 1154 //
24116 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24117 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24118 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24119 // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
24121 GIR_RootConstrainSelectedInstOperands,
24122 // GIR_Coverage, 1154,
24123 GIR_Done,
24124 // Label 1454: @62652
24125 GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(62675), // Rule ID 1155 //
24126 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24127 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24128 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24129 // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
24131 GIR_RootConstrainSelectedInstOperands,
24132 // GIR_Coverage, 1155,
24133 GIR_Done,
24134 // Label 1455: @62675
24135 GIM_Reject,
24136 // Label 1442: @62676
24137 GIM_Reject,
24138 // Label 1431: @62677
24139 GIM_Reject,
24140 // Label 41: @62678
24141 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1458*/ GIMT_Encode4(62855),
24142 /*GILLT_s32*//*Label 1456*/ GIMT_Encode4(62697),
24143 /*GILLT_s64*//*Label 1457*/ GIMT_Encode4(62724),
24144 // Label 1456: @62697
24145 GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(62723), // Rule ID 1056 //
24146 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
24147 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
24148 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24149 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
24150 // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
24151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_W_PSEUDO),
24152 GIR_RootConstrainSelectedInstOperands,
24153 // GIR_Coverage, 1056,
24154 GIR_Done,
24155 // Label 1459: @62723
24156 GIM_Reject,
24157 // Label 1457: @62724
24158 GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(62750), // Rule ID 1058 //
24159 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
24160 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
24161 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24162 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
24163 // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
24164 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_D_PSEUDO),
24165 GIR_RootConstrainSelectedInstOperands,
24166 // GIR_Coverage, 1058,
24167 GIR_Done,
24168 // Label 1460: @62750
24169 GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(62776), // Rule ID 1447 //
24170 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
24171 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24172 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24173 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24174 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
24175 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
24176 GIR_RootConstrainSelectedInstOperands,
24177 // GIR_Coverage, 1447,
24178 GIR_Done,
24179 // Label 1461: @62776
24180 GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(62802), // Rule ID 1457 //
24181 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
24182 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24183 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24184 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24185 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
24186 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
24187 GIR_RootConstrainSelectedInstOperands,
24188 // GIR_Coverage, 1457,
24189 GIR_Done,
24190 // Label 1462: @62802
24191 GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(62828), // Rule ID 2234 //
24192 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
24193 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24194 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24195 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24196 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
24197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
24198 GIR_RootConstrainSelectedInstOperands,
24199 // GIR_Coverage, 2234,
24200 GIR_Done,
24201 // Label 1463: @62828
24202 GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(62854), // Rule ID 2236 //
24203 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
24204 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24205 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24206 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24207 // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
24208 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
24209 GIR_RootConstrainSelectedInstOperands,
24210 // GIR_Coverage, 2236,
24211 GIR_Done,
24212 // Label 1464: @62854
24213 GIM_Reject,
24214 // Label 1458: @62855
24215 GIM_Reject,
24216 // Label 42: @62856
24217 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1467*/ GIMT_Encode4(63018),
24218 /*GILLT_s16*//*Label 1465*/ GIMT_Encode4(62875),
24219 /*GILLT_s32*//*Label 1466*/ GIMT_Encode4(62928),
24220 // Label 1465: @62875
24221 GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(62901), // Rule ID 1057 //
24222 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
24223 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24224 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
24225 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24226 // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
24227 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_W_PSEUDO),
24228 GIR_RootConstrainSelectedInstOperands,
24229 // GIR_Coverage, 1057,
24230 GIR_Done,
24231 // Label 1468: @62901
24232 GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(62927), // Rule ID 1059 //
24233 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
24234 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24235 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
24236 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24237 // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
24238 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_D_PSEUDO),
24239 GIR_RootConstrainSelectedInstOperands,
24240 // GIR_Coverage, 1059,
24241 GIR_Done,
24242 // Label 1469: @62927
24243 GIM_Reject,
24244 // Label 1466: @62928
24245 GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(63017),
24246 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24247 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24248 GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(62959), // Rule ID 1446 //
24249 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
24250 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24251 // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
24252 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
24253 GIR_RootConstrainSelectedInstOperands,
24254 // GIR_Coverage, 1446,
24255 GIR_Done,
24256 // Label 1471: @62959
24257 GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(62978), // Rule ID 1456 //
24258 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
24259 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24260 // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
24261 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
24262 GIR_RootConstrainSelectedInstOperands,
24263 // GIR_Coverage, 1456,
24264 GIR_Done,
24265 // Label 1472: @62978
24266 GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(62997), // Rule ID 2233 //
24267 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
24268 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24269 // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
24270 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
24271 GIR_RootConstrainSelectedInstOperands,
24272 // GIR_Coverage, 2233,
24273 GIR_Done,
24274 // Label 1473: @62997
24275 GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(63016), // Rule ID 2235 //
24276 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
24277 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24278 // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
24279 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
24280 GIR_RootConstrainSelectedInstOperands,
24281 // GIR_Coverage, 2235,
24282 GIR_Done,
24283 // Label 1474: @63016
24284 GIM_Reject,
24285 // Label 1470: @63017
24286 GIM_Reject,
24287 // Label 1467: @63018
24288 GIM_Reject,
24289 // Label 43: @63019
24290 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1477*/ GIMT_Encode4(63096),
24291 /*GILLT_v2s64*//*Label 1475*/ GIMT_Encode4(63042), GIMT_Encode4(0),
24292 /*GILLT_v4s32*//*Label 1476*/ GIMT_Encode4(63069),
24293 // Label 1475: @63042
24294 GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(63068), // Rule ID 777 //
24295 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24296 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24297 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24298 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24299 // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24300 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
24301 GIR_RootConstrainSelectedInstOperands,
24302 // GIR_Coverage, 777,
24303 GIR_Done,
24304 // Label 1478: @63068
24305 GIM_Reject,
24306 // Label 1476: @63069
24307 GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(63095), // Rule ID 776 //
24308 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24309 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24310 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24311 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24312 // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24313 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
24314 GIR_RootConstrainSelectedInstOperands,
24315 // GIR_Coverage, 776,
24316 GIR_Done,
24317 // Label 1479: @63095
24318 GIM_Reject,
24319 // Label 1477: @63096
24320 GIM_Reject,
24321 // Label 44: @63097
24322 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1482*/ GIMT_Encode4(63174),
24323 /*GILLT_v2s64*//*Label 1480*/ GIMT_Encode4(63120), GIMT_Encode4(0),
24324 /*GILLT_v4s32*//*Label 1481*/ GIMT_Encode4(63147),
24325 // Label 1480: @63120
24326 GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(63146), // Rule ID 779 //
24327 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24328 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24329 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24330 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24331 // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24332 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
24333 GIR_RootConstrainSelectedInstOperands,
24334 // GIR_Coverage, 779,
24335 GIR_Done,
24336 // Label 1483: @63146
24337 GIM_Reject,
24338 // Label 1481: @63147
24339 GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(63173), // Rule ID 778 //
24340 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24341 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24342 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24343 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24344 // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24345 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
24346 GIR_RootConstrainSelectedInstOperands,
24347 // GIR_Coverage, 778,
24348 GIR_Done,
24349 // Label 1484: @63173
24350 GIM_Reject,
24351 // Label 1482: @63174
24352 GIM_Reject,
24353 // Label 45: @63175
24354 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1489*/ GIMT_Encode4(63427),
24355 /*GILLT_s32*//*Label 1485*/ GIMT_Encode4(63210),
24356 /*GILLT_s64*//*Label 1486*/ GIMT_Encode4(63294), GIMT_Encode4(0),
24357 /*GILLT_v2s64*//*Label 1487*/ GIMT_Encode4(63373), GIMT_Encode4(0),
24358 /*GILLT_v4s32*//*Label 1488*/ GIMT_Encode4(63400),
24359 // Label 1485: @63210
24360 GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(63233), // Rule ID 1441 //
24361 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24362 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24363 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24364 // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
24365 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
24366 GIR_RootConstrainSelectedInstOperands,
24367 // GIR_Coverage, 1441,
24368 GIR_Done,
24369 // Label 1490: @63233
24370 GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(63293), // Rule ID 1451 //
24371 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
24372 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24373 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24374 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24375 // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
24376 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
24377 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
24378 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
24379 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
24380 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24381 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24382 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24383 GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
24384 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
24385 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
24386 // GIR_Coverage, 1451,
24387 GIR_EraseRootFromParent_Done,
24388 // Label 1491: @63293
24389 GIM_Reject,
24390 // Label 1486: @63294
24391 GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(63320), // Rule ID 1444 //
24392 GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotFP64bit),
24393 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24394 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24395 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24396 // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
24397 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
24398 GIR_RootConstrainSelectedInstOperands,
24399 // GIR_Coverage, 1444,
24400 GIR_Done,
24401 // Label 1492: @63320
24402 GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(63346), // Rule ID 1450 //
24403 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
24404 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24405 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24406 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
24407 // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
24408 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
24409 GIR_RootConstrainSelectedInstOperands,
24410 // GIR_Coverage, 1450,
24411 GIR_Done,
24412 // Label 1493: @63346
24413 GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(63372), // Rule ID 1452 //
24414 GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
24415 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24416 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24417 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
24418 // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
24419 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
24420 GIR_RootConstrainSelectedInstOperands,
24421 // GIR_Coverage, 1452,
24422 GIR_Done,
24423 // Label 1494: @63372
24424 GIM_Reject,
24425 // Label 1487: @63373
24426 GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(63399), // Rule ID 709 //
24427 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24428 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24429 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24430 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24431 // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24432 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
24433 GIR_RootConstrainSelectedInstOperands,
24434 // GIR_Coverage, 709,
24435 GIR_Done,
24436 // Label 1495: @63399
24437 GIM_Reject,
24438 // Label 1488: @63400
24439 GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(63426), // Rule ID 708 //
24440 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24441 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24442 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24443 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24444 // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24445 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
24446 GIR_RootConstrainSelectedInstOperands,
24447 // GIR_Coverage, 708,
24448 GIR_Done,
24449 // Label 1496: @63426
24450 GIM_Reject,
24451 // Label 1489: @63427
24452 GIM_Reject,
24453 // Label 46: @63428
24454 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1499*/ GIMT_Encode4(63505),
24455 /*GILLT_v2s64*//*Label 1497*/ GIMT_Encode4(63451), GIMT_Encode4(0),
24456 /*GILLT_v4s32*//*Label 1498*/ GIMT_Encode4(63478),
24457 // Label 1497: @63451
24458 GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(63477), // Rule ID 711 //
24459 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24460 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24461 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24462 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24463 // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
24464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
24465 GIR_RootConstrainSelectedInstOperands,
24466 // GIR_Coverage, 711,
24467 GIR_Done,
24468 // Label 1500: @63477
24469 GIM_Reject,
24470 // Label 1498: @63478
24471 GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(63504), // Rule ID 710 //
24472 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24473 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24474 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24475 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24476 // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
24477 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
24478 GIR_RootConstrainSelectedInstOperands,
24479 // GIR_Coverage, 710,
24480 GIR_Done,
24481 // Label 1501: @63504
24482 GIM_Reject,
24483 // Label 1499: @63505
24484 GIM_Reject,
24485 // Label 47: @63506
24486 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1506*/ GIMT_Encode4(63745),
24487 /*GILLT_s32*//*Label 1502*/ GIMT_Encode4(63541),
24488 /*GILLT_s64*//*Label 1503*/ GIMT_Encode4(63589), GIMT_Encode4(0),
24489 /*GILLT_v2s64*//*Label 1504*/ GIMT_Encode4(63691), GIMT_Encode4(0),
24490 /*GILLT_v4s32*//*Label 1505*/ GIMT_Encode4(63718),
24491 // Label 1502: @63541
24492 GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(63588),
24493 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24494 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24495 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24496 GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(63572), // Rule ID 126 //
24497 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs),
24498 // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24499 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S),
24500 GIR_RootConstrainSelectedInstOperands,
24501 // GIR_Coverage, 126,
24502 GIR_Done,
24503 // Label 1508: @63572
24504 GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(63587), // Rule ID 1152 //
24505 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_UseAbs),
24506 // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
24507 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S_MM),
24508 GIR_RootConstrainSelectedInstOperands,
24509 // GIR_Coverage, 1152,
24510 GIR_Done,
24511 // Label 1509: @63587
24512 GIM_Reject,
24513 // Label 1507: @63588
24514 GIM_Reject,
24515 // Label 1503: @63589
24516 GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(63690),
24517 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24518 GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(63620), // Rule ID 127 //
24519 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs),
24520 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24521 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24522 // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24523 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32),
24524 GIR_RootConstrainSelectedInstOperands,
24525 // GIR_Coverage, 127,
24526 GIR_Done,
24527 // Label 1511: @63620
24528 GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(63643), // Rule ID 128 //
24529 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs),
24530 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24531 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24532 // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24533 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64),
24534 GIR_RootConstrainSelectedInstOperands,
24535 // GIR_Coverage, 128,
24536 GIR_Done,
24537 // Label 1512: @63643
24538 GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(63666), // Rule ID 1150 //
24539 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
24540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24541 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
24542 // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
24543 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
24544 GIR_RootConstrainSelectedInstOperands,
24545 // GIR_Coverage, 1150,
24546 GIR_Done,
24547 // Label 1513: @63666
24548 GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(63689), // Rule ID 1151 //
24549 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
24550 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24551 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24552 // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
24553 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
24554 GIR_RootConstrainSelectedInstOperands,
24555 // GIR_Coverage, 1151,
24556 GIR_Done,
24557 // Label 1514: @63689
24558 GIM_Reject,
24559 // Label 1510: @63690
24560 GIM_Reject,
24561 // Label 1504: @63691
24562 GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(63717), // Rule ID 1043 //
24563 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24564 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24565 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24566 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24567 // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
24568 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
24569 GIR_RootConstrainSelectedInstOperands,
24570 // GIR_Coverage, 1043,
24571 GIR_Done,
24572 // Label 1515: @63717
24573 GIM_Reject,
24574 // Label 1505: @63718
24575 GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(63744), // Rule ID 1042 //
24576 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24577 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24578 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24579 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24580 // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
24581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
24582 GIR_RootConstrainSelectedInstOperands,
24583 // GIR_Coverage, 1042,
24584 GIR_Done,
24585 // Label 1516: @63744
24586 GIM_Reject,
24587 // Label 1506: @63745
24588 GIM_Reject,
24589 // Label 48: @63746
24590 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1519*/ GIMT_Encode4(63819),
24591 /*GILLT_s32*//*Label 1517*/ GIMT_Encode4(63765),
24592 /*GILLT_s64*//*Label 1518*/ GIMT_Encode4(63792),
24593 // Label 1517: @63765
24594 GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(63791), // Rule ID 1770 //
24595 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24596 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24597 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24598 // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
24599 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24600 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24601 GIR_RootToRootCopy, /*OpIdx*/1, // src
24602 GIR_RootToRootCopy, /*OpIdx*/1, // src
24603 GIR_RootConstrainSelectedInstOperands,
24604 // GIR_Coverage, 1770,
24605 GIR_EraseRootFromParent_Done,
24606 // Label 1520: @63791
24607 GIM_Reject,
24608 // Label 1518: @63792
24609 GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(63818), // Rule ID 1771 //
24610 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24611 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24612 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24613 // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
24614 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24615 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
24616 GIR_RootToRootCopy, /*OpIdx*/1, // src
24617 GIR_RootToRootCopy, /*OpIdx*/1, // src
24618 GIR_RootConstrainSelectedInstOperands,
24619 // GIR_Coverage, 1771,
24620 GIR_EraseRootFromParent_Done,
24621 // Label 1521: @63818
24622 GIM_Reject,
24623 // Label 1519: @63819
24624 GIM_Reject,
24625 // Label 49: @63820
24626 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1524*/ GIMT_Encode4(63891),
24627 /*GILLT_s32*//*Label 1522*/ GIMT_Encode4(63839),
24628 /*GILLT_s64*//*Label 1523*/ GIMT_Encode4(63865),
24629 // Label 1522: @63839
24630 GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(63864), // Rule ID 1768 //
24631 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24632 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24633 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24634 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24635 // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24636 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
24637 GIR_RootConstrainSelectedInstOperands,
24638 // GIR_Coverage, 1768,
24639 GIR_Done,
24640 // Label 1525: @63864
24641 GIM_Reject,
24642 // Label 1523: @63865
24643 GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(63890), // Rule ID 1769 //
24644 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24645 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24646 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24647 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24648 // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24649 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
24650 GIR_RootConstrainSelectedInstOperands,
24651 // GIR_Coverage, 1769,
24652 GIR_Done,
24653 // Label 1526: @63890
24654 GIM_Reject,
24655 // Label 1524: @63891
24656 GIM_Reject,
24657 // Label 50: @63892
24658 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1529*/ GIMT_Encode4(63963),
24659 /*GILLT_s32*//*Label 1527*/ GIMT_Encode4(63911),
24660 /*GILLT_s64*//*Label 1528*/ GIMT_Encode4(63937),
24661 // Label 1527: @63911
24662 GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(63936), // Rule ID 1766 //
24663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24664 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
24665 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24666 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
24667 // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs) => (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
24668 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
24669 GIR_RootConstrainSelectedInstOperands,
24670 // GIR_Coverage, 1766,
24671 GIR_Done,
24672 // Label 1530: @63936
24673 GIM_Reject,
24674 // Label 1528: @63937
24675 GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(63962), // Rule ID 1767 //
24676 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
24677 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
24678 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
24679 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
24680 // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs) => (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
24681 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
24682 GIR_RootConstrainSelectedInstOperands,
24683 // GIR_Coverage, 1767,
24684 GIR_Done,
24685 // Label 1531: @63962
24686 GIM_Reject,
24687 // Label 1529: @63963
24688 GIM_Reject,
24689 // Label 51: @63964
24690 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1536*/ GIMT_Encode4(64131),
24691 /*GILLT_v2s64*//*Label 1532*/ GIMT_Encode4(63995), GIMT_Encode4(0),
24692 /*GILLT_v4s32*//*Label 1533*/ GIMT_Encode4(64029),
24693 /*GILLT_v8s16*//*Label 1534*/ GIMT_Encode4(64063),
24694 /*GILLT_v16s8*//*Label 1535*/ GIMT_Encode4(64097),
24695 // Label 1532: @63995
24696 GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(64028), // Rule ID 871 //
24697 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24698 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24699 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24700 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24701 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24702 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24703 // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
24705 GIR_RootConstrainSelectedInstOperands,
24706 // GIR_Coverage, 871,
24707 GIR_Done,
24708 // Label 1537: @64028
24709 GIM_Reject,
24710 // Label 1533: @64029
24711 GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(64062), // Rule ID 870 //
24712 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24713 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24714 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24715 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24716 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24717 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24718 // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24719 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
24720 GIR_RootConstrainSelectedInstOperands,
24721 // GIR_Coverage, 870,
24722 GIR_Done,
24723 // Label 1538: @64062
24724 GIM_Reject,
24725 // Label 1534: @64063
24726 GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(64096), // Rule ID 869 //
24727 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24728 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24729 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24730 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24731 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24732 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24733 // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24734 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
24735 GIR_RootConstrainSelectedInstOperands,
24736 // GIR_Coverage, 869,
24737 GIR_Done,
24738 // Label 1539: @64096
24739 GIM_Reject,
24740 // Label 1535: @64097
24741 GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(64130), // Rule ID 868 //
24742 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24743 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24744 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24745 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24746 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24747 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24748 // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24749 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
24750 GIR_RootConstrainSelectedInstOperands,
24751 // GIR_Coverage, 868,
24752 GIR_Done,
24753 // Label 1540: @64130
24754 GIM_Reject,
24755 // Label 1536: @64131
24756 GIM_Reject,
24757 // Label 52: @64132
24758 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1545*/ GIMT_Encode4(64299),
24759 /*GILLT_v2s64*//*Label 1541*/ GIMT_Encode4(64163), GIMT_Encode4(0),
24760 /*GILLT_v4s32*//*Label 1542*/ GIMT_Encode4(64197),
24761 /*GILLT_v8s16*//*Label 1543*/ GIMT_Encode4(64231),
24762 /*GILLT_v16s8*//*Label 1544*/ GIMT_Encode4(64265),
24763 // Label 1541: @64163
24764 GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(64196), // Rule ID 851 //
24765 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24766 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24767 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24769 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24770 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24771 // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24772 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
24773 GIR_RootConstrainSelectedInstOperands,
24774 // GIR_Coverage, 851,
24775 GIR_Done,
24776 // Label 1546: @64196
24777 GIM_Reject,
24778 // Label 1542: @64197
24779 GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(64230), // Rule ID 850 //
24780 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24781 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24782 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24783 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24784 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24785 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24786 // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
24788 GIR_RootConstrainSelectedInstOperands,
24789 // GIR_Coverage, 850,
24790 GIR_Done,
24791 // Label 1547: @64230
24792 GIM_Reject,
24793 // Label 1543: @64231
24794 GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(64264), // Rule ID 849 //
24795 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24796 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24797 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24798 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24799 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24800 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24801 // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24802 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
24803 GIR_RootConstrainSelectedInstOperands,
24804 // GIR_Coverage, 849,
24805 GIR_Done,
24806 // Label 1548: @64264
24807 GIM_Reject,
24808 // Label 1544: @64265
24809 GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(64298), // Rule ID 848 //
24810 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24811 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24812 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24813 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24814 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24815 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24816 // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24817 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
24818 GIR_RootConstrainSelectedInstOperands,
24819 // GIR_Coverage, 848,
24820 GIR_Done,
24821 // Label 1549: @64298
24822 GIM_Reject,
24823 // Label 1545: @64299
24824 GIM_Reject,
24825 // Label 53: @64300
24826 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1554*/ GIMT_Encode4(64467),
24827 /*GILLT_v2s64*//*Label 1550*/ GIMT_Encode4(64331), GIMT_Encode4(0),
24828 /*GILLT_v4s32*//*Label 1551*/ GIMT_Encode4(64365),
24829 /*GILLT_v8s16*//*Label 1552*/ GIMT_Encode4(64399),
24830 /*GILLT_v16s8*//*Label 1553*/ GIMT_Encode4(64433),
24831 // Label 1550: @64331
24832 GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(64364), // Rule ID 875 //
24833 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24834 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24835 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24836 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24837 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24838 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24839 // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24840 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
24841 GIR_RootConstrainSelectedInstOperands,
24842 // GIR_Coverage, 875,
24843 GIR_Done,
24844 // Label 1555: @64364
24845 GIM_Reject,
24846 // Label 1551: @64365
24847 GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(64398), // Rule ID 874 //
24848 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24849 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24850 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24851 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24852 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24853 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24854 // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24855 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
24856 GIR_RootConstrainSelectedInstOperands,
24857 // GIR_Coverage, 874,
24858 GIR_Done,
24859 // Label 1556: @64398
24860 GIM_Reject,
24861 // Label 1552: @64399
24862 GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(64432), // Rule ID 873 //
24863 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24864 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24865 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24866 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24867 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24868 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24869 // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24870 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
24871 GIR_RootConstrainSelectedInstOperands,
24872 // GIR_Coverage, 873,
24873 GIR_Done,
24874 // Label 1557: @64432
24875 GIM_Reject,
24876 // Label 1553: @64433
24877 GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(64466), // Rule ID 872 //
24878 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24879 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24880 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24881 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24882 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24883 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24884 // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24885 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
24886 GIR_RootConstrainSelectedInstOperands,
24887 // GIR_Coverage, 872,
24888 GIR_Done,
24889 // Label 1558: @64466
24890 GIM_Reject,
24891 // Label 1554: @64467
24892 GIM_Reject,
24893 // Label 54: @64468
24894 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1563*/ GIMT_Encode4(64635),
24895 /*GILLT_v2s64*//*Label 1559*/ GIMT_Encode4(64499), GIMT_Encode4(0),
24896 /*GILLT_v4s32*//*Label 1560*/ GIMT_Encode4(64533),
24897 /*GILLT_v8s16*//*Label 1561*/ GIMT_Encode4(64567),
24898 /*GILLT_v16s8*//*Label 1562*/ GIMT_Encode4(64601),
24899 // Label 1559: @64499
24900 GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(64532), // Rule ID 855 //
24901 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24902 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
24903 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
24904 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24905 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24906 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
24907 // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
24908 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
24909 GIR_RootConstrainSelectedInstOperands,
24910 // GIR_Coverage, 855,
24911 GIR_Done,
24912 // Label 1564: @64532
24913 GIM_Reject,
24914 // Label 1560: @64533
24915 GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(64566), // Rule ID 854 //
24916 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24917 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
24918 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24919 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24920 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24921 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
24922 // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
24923 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
24924 GIR_RootConstrainSelectedInstOperands,
24925 // GIR_Coverage, 854,
24926 GIR_Done,
24927 // Label 1565: @64566
24928 GIM_Reject,
24929 // Label 1561: @64567
24930 GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(64600), // Rule ID 853 //
24931 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24932 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
24933 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24934 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24935 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24936 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
24937 // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
24938 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
24939 GIR_RootConstrainSelectedInstOperands,
24940 // GIR_Coverage, 853,
24941 GIR_Done,
24942 // Label 1566: @64600
24943 GIM_Reject,
24944 // Label 1562: @64601
24945 GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(64634), // Rule ID 852 //
24946 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
24947 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
24948 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24949 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24950 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24951 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
24952 // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
24953 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
24954 GIR_RootConstrainSelectedInstOperands,
24955 // GIR_Coverage, 852,
24956 GIR_Done,
24957 // Label 1567: @64634
24958 GIM_Reject,
24959 // Label 1563: @64635
24960 GIM_Reject,
24961 // Label 55: @64636
24962 GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(64759),
24963 GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
24964 GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(64665), // Rule ID 91 //
24965 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC),
24966 // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
24967 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
24968 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
24969 GIR_RootConstrainSelectedInstOperands,
24970 // GIR_Coverage, 91,
24971 GIR_Done,
24972 // Label 1569: @64665
24973 GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(64686), // Rule ID 98 //
24974 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
24975 // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
24976 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
24977 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
24978 GIR_RootConstrainSelectedInstOperands,
24979 // GIR_Coverage, 98,
24980 GIR_Done,
24981 // Label 1570: @64686
24982 GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(64707), // Rule ID 1104 //
24983 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC),
24984 // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
24985 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
24986 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
24987 GIR_RootConstrainSelectedInstOperands,
24988 // GIR_Coverage, 1104,
24989 GIR_Done,
24990 // Label 1571: @64707
24991 GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(64728), // Rule ID 1113 //
24992 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC),
24993 // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
24994 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
24995 GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
24996 GIR_RootConstrainSelectedInstOperands,
24997 // GIR_Coverage, 1113,
24998 GIR_Done,
24999 // Label 1572: @64728
25000 GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(64743), // Rule ID 1171 //
25001 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
25002 // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
25003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
25004 GIR_RootConstrainSelectedInstOperands,
25005 // GIR_Coverage, 1171,
25006 GIR_Done,
25007 // Label 1573: @64743
25008 GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(64758), // Rule ID 1841 //
25009 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
25010 // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
25011 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
25012 GIR_RootConstrainSelectedInstOperands,
25013 // GIR_Coverage, 1841,
25014 GIR_Done,
25015 // Label 1574: @64758
25016 GIM_Reject,
25017 // Label 1568: @64759
25018 GIM_Reject,
25019 // Label 56: @64760
25020 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1579*/ GIMT_Encode4(65323),
25021 /*GILLT_v2s64*//*Label 1575*/ GIMT_Encode4(64791), GIMT_Encode4(0),
25022 /*GILLT_v4s32*//*Label 1576*/ GIMT_Encode4(64964),
25023 /*GILLT_v8s16*//*Label 1577*/ GIMT_Encode4(65137),
25024 /*GILLT_v16s8*//*Label 1578*/ GIMT_Encode4(65230),
25025 // Label 1575: @64791
25026 GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(64963),
25027 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25028 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
25029 GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(64842), // Rule ID 821 //
25030 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25031 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25032 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25033 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25034 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25035 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25036 // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
25037 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
25038 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25039 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25040 GIR_RootToRootCopy, /*OpIdx*/3, // n
25041 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25042 GIR_RootConstrainSelectedInstOperands,
25043 // GIR_Coverage, 821,
25044 GIR_EraseRootFromParent_Done,
25045 // Label 1581: @64842
25046 GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(64882), // Rule ID 823 //
25047 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25048 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25049 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25050 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25051 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25052 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25053 // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
25054 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
25055 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25056 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25057 GIR_RootToRootCopy, /*OpIdx*/3, // n
25058 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25059 GIR_RootConstrainSelectedInstOperands,
25060 // GIR_Coverage, 823,
25061 GIR_EraseRootFromParent_Done,
25062 // Label 1582: @64882
25063 GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(64922), // Rule ID 827 //
25064 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25065 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25066 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25067 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25068 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25069 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25070 // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
25071 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
25072 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25073 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25074 GIR_RootToRootCopy, /*OpIdx*/3, // n
25075 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25076 GIR_RootConstrainSelectedInstOperands,
25077 // GIR_Coverage, 827,
25078 GIR_EraseRootFromParent_Done,
25079 // Label 1583: @64922
25080 GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(64962), // Rule ID 829 //
25081 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25082 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25083 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25084 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25085 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25086 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25087 // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
25088 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
25089 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25090 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25091 GIR_RootToRootCopy, /*OpIdx*/3, // n
25092 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25093 GIR_RootConstrainSelectedInstOperands,
25094 // GIR_Coverage, 829,
25095 GIR_EraseRootFromParent_Done,
25096 // Label 1584: @64962
25097 GIM_Reject,
25098 // Label 1580: @64963
25099 GIM_Reject,
25100 // Label 1576: @64964
25101 GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(65136),
25102 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25103 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25104 GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(65015), // Rule ID 820 //
25105 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25106 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25107 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25108 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25109 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25110 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25111 // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
25112 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
25113 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25114 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25115 GIR_RootToRootCopy, /*OpIdx*/3, // n
25116 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25117 GIR_RootConstrainSelectedInstOperands,
25118 // GIR_Coverage, 820,
25119 GIR_EraseRootFromParent_Done,
25120 // Label 1586: @65015
25121 GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(65055), // Rule ID 822 //
25122 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25123 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25124 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25125 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25126 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25127 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25128 // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
25129 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
25130 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25131 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25132 GIR_RootToRootCopy, /*OpIdx*/3, // n
25133 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25134 GIR_RootConstrainSelectedInstOperands,
25135 // GIR_Coverage, 822,
25136 GIR_EraseRootFromParent_Done,
25137 // Label 1587: @65055
25138 GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(65095), // Rule ID 826 //
25139 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25140 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25141 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25142 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25143 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25144 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25145 // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
25146 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
25147 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25148 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25149 GIR_RootToRootCopy, /*OpIdx*/3, // n
25150 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25151 GIR_RootConstrainSelectedInstOperands,
25152 // GIR_Coverage, 826,
25153 GIR_EraseRootFromParent_Done,
25154 // Label 1588: @65095
25155 GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(65135), // Rule ID 828 //
25156 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25157 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25158 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25159 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25160 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25161 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25162 // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
25163 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
25164 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25165 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25166 GIR_RootToRootCopy, /*OpIdx*/3, // n
25167 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25168 GIR_RootConstrainSelectedInstOperands,
25169 // GIR_Coverage, 828,
25170 GIR_EraseRootFromParent_Done,
25171 // Label 1589: @65135
25172 GIM_Reject,
25173 // Label 1585: @65136
25174 GIM_Reject,
25175 // Label 1577: @65137
25176 GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(65229),
25177 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25178 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25179 GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(65188), // Rule ID 819 //
25180 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25181 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25182 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25183 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25184 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25185 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25186 // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
25187 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
25188 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25189 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25190 GIR_RootToRootCopy, /*OpIdx*/3, // n
25191 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25192 GIR_RootConstrainSelectedInstOperands,
25193 // GIR_Coverage, 819,
25194 GIR_EraseRootFromParent_Done,
25195 // Label 1591: @65188
25196 GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(65228), // Rule ID 825 //
25197 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25198 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25199 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25200 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25201 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25202 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25203 // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
25204 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
25205 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25206 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25207 GIR_RootToRootCopy, /*OpIdx*/3, // n
25208 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25209 GIR_RootConstrainSelectedInstOperands,
25210 // GIR_Coverage, 825,
25211 GIR_EraseRootFromParent_Done,
25212 // Label 1592: @65228
25213 GIM_Reject,
25214 // Label 1590: @65229
25215 GIM_Reject,
25216 // Label 1578: @65230
25217 GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(65322),
25218 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25219 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25220 GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(65281), // Rule ID 818 //
25221 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25222 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25223 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25224 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25225 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25226 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25227 // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) => (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
25228 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
25229 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25230 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25231 GIR_RootToRootCopy, /*OpIdx*/3, // n
25232 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25233 GIR_RootConstrainSelectedInstOperands,
25234 // GIR_Coverage, 818,
25235 GIR_EraseRootFromParent_Done,
25236 // Label 1594: @65281
25237 GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(65321), // Rule ID 824 //
25238 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25239 GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
25240 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25241 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25242 GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25243 GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25244 // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) => (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
25245 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
25246 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
25247 GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
25248 GIR_RootToRootCopy, /*OpIdx*/3, // n
25249 GIR_RootToRootCopy, /*OpIdx*/2, // fs
25250 GIR_RootConstrainSelectedInstOperands,
25251 // GIR_Coverage, 824,
25252 GIR_EraseRootFromParent_Done,
25253 // Label 1595: @65321
25254 GIM_Reject,
25255 // Label 1593: @65322
25256 GIM_Reject,
25257 // Label 1579: @65323
25258 GIM_Reject,
25259 // Label 57: @65324
25260 GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(65375), // Rule ID 1968 //
25261 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
25262 GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25263 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25264 GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25265 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25266 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25267 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
25268 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25269 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
25270 // MIs[1] Operand 1
25271 // No operand predicates
25272 GIM_CheckIsSafeToFold, /*NumInsns*/1,
25273 // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
25274 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
25275 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25276 GIR_RootToRootCopy, /*OpIdx*/1, // ws
25277 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
25278 GIR_RootConstrainSelectedInstOperands,
25279 // GIR_Coverage, 1968,
25280 GIR_EraseRootFromParent_Done,
25281 // Label 1596: @65375
25282 GIM_Reject,
25283 // Label 58: @65376
25284 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1603*/ GIMT_Encode4(65880),
25285 /*GILLT_s32*//*Label 1597*/ GIMT_Encode4(65419),
25286 /*GILLT_s64*//*Label 1598*/ GIMT_Encode4(65628), GIMT_Encode4(0),
25287 /*GILLT_v2s64*//*Label 1599*/ GIMT_Encode4(65772), GIMT_Encode4(0),
25288 /*GILLT_v4s32*//*Label 1600*/ GIMT_Encode4(65799),
25289 /*GILLT_v8s16*//*Label 1601*/ GIMT_Encode4(65826),
25290 /*GILLT_v16s8*//*Label 1602*/ GIMT_Encode4(65853),
25291 // Label 1597: @65419
25292 GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(65627),
25293 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25294 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25295 GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(65477), // Rule ID 109 //
25296 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
25297 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25298 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25299 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25300 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25301 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25302 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
25303 GIM_CheckIsSafeToFold, /*NumInsns*/1,
25304 // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25305 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
25306 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25308 GIR_RootConstrainSelectedInstOperands,
25309 // GIR_Coverage, 109,
25310 GIR_EraseRootFromParent_Done,
25311 // Label 1605: @65477
25312 GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(65523), // Rule ID 310 //
25313 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
25314 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25315 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25316 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25317 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25319 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
25320 GIM_CheckIsSafeToFold, /*NumInsns*/1,
25321 // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25322 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
25323 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25325 GIR_RootConstrainSelectedInstOperands,
25326 // GIR_Coverage, 310,
25327 GIR_EraseRootFromParent_Done,
25328 // Label 1606: @65523
25329 GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(65569), // Rule ID 1100 //
25330 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
25331 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25332 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25333 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
25334 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
25335 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25336 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
25337 GIM_CheckIsSafeToFold, /*NumInsns*/1,
25338 // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25339 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
25340 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25342 GIR_RootConstrainSelectedInstOperands,
25343 // GIR_Coverage, 1100,
25344 GIR_EraseRootFromParent_Done,
25345 // Label 1607: @65569
25346 GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(65588), // Rule ID 108 //
25347 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
25348 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25349 // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25350 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
25351 GIR_RootConstrainSelectedInstOperands,
25352 // GIR_Coverage, 108,
25353 GIR_Done,
25354 // Label 1608: @65588
25355 GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(65607), // Rule ID 311 //
25356 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
25357 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25358 // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25359 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
25360 GIR_RootConstrainSelectedInstOperands,
25361 // GIR_Coverage, 311,
25362 GIR_Done,
25363 // Label 1609: @65607
25364 GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(65626), // Rule ID 1099 //
25365 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
25366 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25367 // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25368 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
25369 GIR_RootConstrainSelectedInstOperands,
25370 // GIR_Coverage, 1099,
25371 GIR_Done,
25372 // Label 1610: @65626
25373 GIM_Reject,
25374 // Label 1604: @65627
25375 GIM_Reject,
25376 // Label 1598: @65628
25377 GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(65771),
25378 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25379 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25380 GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(65686), // Rule ID 264 //
25381 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
25382 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25383 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25384 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25385 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25386 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25387 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
25388 GIM_CheckIsSafeToFold, /*NumInsns*/1,
25389 // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25390 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
25391 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25393 GIR_RootConstrainSelectedInstOperands,
25394 // GIR_Coverage, 264,
25395 GIR_EraseRootFromParent_Done,
25396 // Label 1612: @65686
25397 GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(65732), // Rule ID 339 //
25398 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
25399 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
25400 GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
25401 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
25402 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
25403 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25404 GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
25405 GIM_CheckIsSafeToFold, /*NumInsns*/1,
25406 // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25407 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
25408 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
25410 GIR_RootConstrainSelectedInstOperands,
25411 // GIR_Coverage, 339,
25412 GIR_EraseRootFromParent_Done,
25413 // Label 1613: @65732
25414 GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(65751), // Rule ID 263 //
25415 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
25416 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25417 // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
25419 GIR_RootConstrainSelectedInstOperands,
25420 // GIR_Coverage, 263,
25421 GIR_Done,
25422 // Label 1614: @65751
25423 GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(65770), // Rule ID 340 //
25424 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
25425 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25426 // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25427 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
25428 GIR_RootConstrainSelectedInstOperands,
25429 // GIR_Coverage, 340,
25430 GIR_Done,
25431 // Label 1615: @65770
25432 GIM_Reject,
25433 // Label 1611: @65771
25434 GIM_Reject,
25435 // Label 1599: @65772
25436 GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(65798), // Rule ID 915 //
25437 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25438 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25439 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25440 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25441 // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25442 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
25443 GIR_RootConstrainSelectedInstOperands,
25444 // GIR_Coverage, 915,
25445 GIR_Done,
25446 // Label 1616: @65798
25447 GIM_Reject,
25448 // Label 1600: @65799
25449 GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(65825), // Rule ID 914 //
25450 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25451 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25452 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25453 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25454 // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25455 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
25456 GIR_RootConstrainSelectedInstOperands,
25457 // GIR_Coverage, 914,
25458 GIR_Done,
25459 // Label 1617: @65825
25460 GIM_Reject,
25461 // Label 1601: @65826
25462 GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(65852), // Rule ID 913 //
25463 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25464 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25465 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25466 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25467 // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
25468 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
25469 GIR_RootConstrainSelectedInstOperands,
25470 // GIR_Coverage, 913,
25471 GIR_Done,
25472 // Label 1618: @65852
25473 GIM_Reject,
25474 // Label 1602: @65853
25475 GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(65879), // Rule ID 912 //
25476 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25477 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25478 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25479 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25480 // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
25481 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
25482 GIR_RootConstrainSelectedInstOperands,
25483 // GIR_Coverage, 912,
25484 GIR_Done,
25485 // Label 1619: @65879
25486 GIM_Reject,
25487 // Label 1603: @65880
25488 GIM_Reject,
25489 // Label 59: @65881
25490 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1626*/ GIMT_Encode4(66086),
25491 /*GILLT_s32*//*Label 1620*/ GIMT_Encode4(65924),
25492 /*GILLT_s64*//*Label 1621*/ GIMT_Encode4(65951), GIMT_Encode4(0),
25493 /*GILLT_v2s64*//*Label 1622*/ GIMT_Encode4(65978), GIMT_Encode4(0),
25494 /*GILLT_v4s32*//*Label 1623*/ GIMT_Encode4(66005),
25495 /*GILLT_v8s16*//*Label 1624*/ GIMT_Encode4(66032),
25496 /*GILLT_v16s8*//*Label 1625*/ GIMT_Encode4(66059),
25497 // Label 1620: @65924
25498 GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(65950), // Rule ID 278 //
25499 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
25500 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25501 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25502 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25503 // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
25504 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
25505 GIR_RootConstrainSelectedInstOperands,
25506 // GIR_Coverage, 278,
25507 GIR_Done,
25508 // Label 1627: @65950
25509 GIM_Reject,
25510 // Label 1621: @65951
25511 GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(65977), // Rule ID 279 //
25512 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
25513 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25514 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25515 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25516 // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
25517 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
25518 GIR_RootConstrainSelectedInstOperands,
25519 // GIR_Coverage, 279,
25520 GIR_Done,
25521 // Label 1628: @65977
25522 GIM_Reject,
25523 // Label 1622: @65978
25524 GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(66004), // Rule ID 937 //
25525 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25526 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25527 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25528 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25529 // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
25530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
25531 GIR_RootConstrainSelectedInstOperands,
25532 // GIR_Coverage, 937,
25533 GIR_Done,
25534 // Label 1629: @66004
25535 GIM_Reject,
25536 // Label 1623: @66005
25537 GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(66031), // Rule ID 936 //
25538 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25539 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25540 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25541 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25542 // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
25543 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
25544 GIR_RootConstrainSelectedInstOperands,
25545 // GIR_Coverage, 936,
25546 GIR_Done,
25547 // Label 1630: @66031
25548 GIM_Reject,
25549 // Label 1624: @66032
25550 GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(66058), // Rule ID 935 //
25551 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25552 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
25553 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25554 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
25555 // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
25556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
25557 GIR_RootConstrainSelectedInstOperands,
25558 // GIR_Coverage, 935,
25559 GIR_Done,
25560 // Label 1631: @66058
25561 GIM_Reject,
25562 // Label 1625: @66059
25563 GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(66085), // Rule ID 934 //
25564 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25565 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
25566 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25567 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
25568 // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
25569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
25570 GIR_RootConstrainSelectedInstOperands,
25571 // GIR_Coverage, 934,
25572 GIR_Done,
25573 // Label 1632: @66085
25574 GIM_Reject,
25575 // Label 1626: @66086
25576 GIM_Reject,
25577 // Label 60: @66087
25578 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1635*/ GIMT_Encode4(66250),
25579 /*GILLT_s32*//*Label 1633*/ GIMT_Encode4(66106),
25580 /*GILLT_s64*//*Label 1634*/ GIMT_Encode4(66202),
25581 // Label 1633: @66106
25582 GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(66201),
25583 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25584 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25585 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
25586 GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(66161), // Rule ID 1427 //
25587 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
25588 // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
25589 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
25590 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
25591 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25592 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25593 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25594 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
25595 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25596 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25597 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
25598 GIR_RootConstrainSelectedInstOperands,
25599 // GIR_Coverage, 1427,
25600 GIR_EraseRootFromParent_Done,
25601 // Label 1637: @66161
25602 GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(66200), // Rule ID 2163 //
25603 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
25604 // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
25605 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
25606 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
25607 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25608 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25609 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25610 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
25611 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25612 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25613 GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
25614 GIR_RootConstrainSelectedInstOperands,
25615 // GIR_Coverage, 2163,
25616 GIR_EraseRootFromParent_Done,
25617 // Label 1638: @66200
25618 GIM_Reject,
25619 // Label 1636: @66201
25620 GIM_Reject,
25621 // Label 1634: @66202
25622 GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(66249), // Rule ID 1584 //
25623 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc),
25624 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25625 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25626 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
25627 // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
25628 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
25629 GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
25630 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
25631 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
25632 GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
25633 GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
25634 GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
25635 GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25636 GIR_RootConstrainSelectedInstOperands,
25637 // GIR_Coverage, 1584,
25638 GIR_EraseRootFromParent_Done,
25639 // Label 1639: @66249
25640 GIM_Reject,
25641 // Label 1635: @66250
25642 GIM_Reject,
25643 // Label 61: @66251
25644 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1644*/ GIMT_Encode4(66490),
25645 /*GILLT_s32*//*Label 1640*/ GIMT_Encode4(66286),
25646 /*GILLT_s64*//*Label 1641*/ GIMT_Encode4(66334), GIMT_Encode4(0),
25647 /*GILLT_v2s64*//*Label 1642*/ GIMT_Encode4(66436), GIMT_Encode4(0),
25648 /*GILLT_v4s32*//*Label 1643*/ GIMT_Encode4(66463),
25649 // Label 1640: @66286
25650 GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(66333),
25651 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
25652 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25653 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
25654 GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(66317), // Rule ID 132 //
25655 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
25656 // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25657 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
25658 GIR_RootConstrainSelectedInstOperands,
25659 // GIR_Coverage, 132,
25660 GIR_Done,
25661 // Label 1646: @66317
25662 GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(66332), // Rule ID 1162 //
25663 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
25664 // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
25665 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
25666 GIR_RootConstrainSelectedInstOperands,
25667 // GIR_Coverage, 1162,
25668 GIR_Done,
25669 // Label 1647: @66332
25670 GIM_Reject,
25671 // Label 1645: @66333
25672 GIM_Reject,
25673 // Label 1641: @66334
25674 GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(66435),
25675 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
25676 GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(66365), // Rule ID 133 //
25677 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
25678 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25679 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25680 // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25681 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
25682 GIR_RootConstrainSelectedInstOperands,
25683 // GIR_Coverage, 133,
25684 GIR_Done,
25685 // Label 1649: @66365
25686 GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(66388), // Rule ID 134 //
25687 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
25688 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25689 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25690 // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25691 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
25692 GIR_RootConstrainSelectedInstOperands,
25693 // GIR_Coverage, 134,
25694 GIR_Done,
25695 // Label 1650: @66388
25696 GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(66411), // Rule ID 1148 //
25697 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
25698 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25699 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
25700 // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
25701 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
25702 GIR_RootConstrainSelectedInstOperands,
25703 // GIR_Coverage, 1148,
25704 GIR_Done,
25705 // Label 1651: @66411
25706 GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(66434), // Rule ID 1149 //
25707 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
25708 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25709 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
25710 // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
25711 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
25712 GIR_RootConstrainSelectedInstOperands,
25713 // GIR_Coverage, 1149,
25714 GIR_Done,
25715 // Label 1652: @66434
25716 GIM_Reject,
25717 // Label 1648: @66435
25718 GIM_Reject,
25719 // Label 1642: @66436
25720 GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(66462), // Rule ID 757 //
25721 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25722 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25723 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25724 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25725 // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25726 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
25727 GIR_RootConstrainSelectedInstOperands,
25728 // GIR_Coverage, 757,
25729 GIR_Done,
25730 // Label 1653: @66462
25731 GIM_Reject,
25732 // Label 1643: @66463
25733 GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(66489), // Rule ID 756 //
25734 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25735 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25736 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25737 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25738 // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25739 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
25740 GIR_RootConstrainSelectedInstOperands,
25741 // GIR_Coverage, 756,
25742 GIR_Done,
25743 // Label 1654: @66489
25744 GIM_Reject,
25745 // Label 1644: @66490
25746 GIM_Reject,
25747 // Label 62: @66491
25748 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1657*/ GIMT_Encode4(66568),
25749 /*GILLT_v2s64*//*Label 1655*/ GIMT_Encode4(66514), GIMT_Encode4(0),
25750 /*GILLT_v4s32*//*Label 1656*/ GIMT_Encode4(66541),
25751 // Label 1655: @66514
25752 GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(66540), // Rule ID 739 //
25753 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25754 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
25755 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25756 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
25757 // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
25758 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
25759 GIR_RootConstrainSelectedInstOperands,
25760 // GIR_Coverage, 739,
25761 GIR_Done,
25762 // Label 1658: @66540
25763 GIM_Reject,
25764 // Label 1656: @66541
25765 GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(66567), // Rule ID 738 //
25766 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
25767 GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
25768 GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25769 GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
25770 // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
25771 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
25772 GIR_RootConstrainSelectedInstOperands,
25773 // GIR_Coverage, 738,
25774 GIR_Done,
25775 // Label 1659: @66567
25776 GIM_Reject,
25777 // Label 1657: @66568
25778 GIM_Reject,
25779 // Label 63: @66569
25780 GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(66584), // Rule ID 90 //
25781 GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
25782 // (trap) => (TRAP)
25783 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
25784 GIR_RootConstrainSelectedInstOperands,
25785 // GIR_Coverage, 90,
25786 GIR_Done,
25787 // Label 1660: @66584
25788 GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(66599), // Rule ID 1115 //
25789 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
25790 // (trap) => (TRAP_MM)
25791 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
25792 GIR_RootConstrainSelectedInstOperands,
25793 // GIR_Coverage, 1115,
25794 GIR_Done,
25795 // Label 1661: @66599
25796 GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(66614), // Rule ID 1884 //
25797 GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
25798 // (trap) => (Break16)
25799 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
25800 GIR_RootConstrainSelectedInstOperands,
25801 // GIR_Coverage, 1884,
25802 GIR_Done,
25803 // Label 1662: @66614
25804 GIM_Reject,
25805 // Label 64: @66615
25806 GIM_Reject,
25807 }; // Size: 66616 bytes
25808 return MatchTable0;
25809}
25810#undef GIMT_Encode2
25811#undef GIMT_Encode4
25812#undef GIMT_Encode8
25813
25814#endif // ifdef GET_GLOBALISEL_IMPL
25815
25816#ifdef GET_GLOBALISEL_PREDICATES_DECL
25817PredicateBitset AvailableModuleFeatures;
25818mutable PredicateBitset AvailableFunctionFeatures;
25819PredicateBitset getAvailableFeatures() const {
25820 return AvailableModuleFeatures | AvailableFunctionFeatures;
25821}
25822PredicateBitset
25823computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
25824PredicateBitset
25825computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
25826 const MachineFunction *MF) const;
25827void setupGeneratedPerFunctionState(MachineFunction &MF) override;
25828#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
25829#ifdef GET_GLOBALISEL_PREDICATES_INIT
25830AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
25831AvailableFunctionFeatures()
25832#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
25833