1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace Mips {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 FPRBRegBankID = 0,
16 GPRBRegBankID = 1,
17 NumRegisterBanks,
18};
19} // end namespace Mips
20} // end namespace llvm
21#endif // GET_REGBANK_DECLARATIONS
22
23#ifdef GET_TARGET_REGBANK_CLASS
24#undef GET_TARGET_REGBANK_CLASS
25private:
26 static const RegisterBank *RegBanks[];
27 static const unsigned Sizes[];
28
29protected:
30 MipsGenRegisterBankInfo(unsigned HwMode = 0);
31
32#endif // GET_TARGET_REGBANK_CLASS
33
34#ifdef GET_TARGET_REGBANK_IMPL
35#undef GET_TARGET_REGBANK_IMPL
36namespace llvm {
37namespace Mips {
38const uint32_t FPRBRegBankCoverageData[] = {
39 // 0-31
40 (1u << (Mips::FGR32RegClassID - 0)) |
41 (1u << (Mips::FGRCCRegClassID - 0)) |
42 0,
43 // 32-63
44 (1u << (Mips::FGR64RegClassID - 32)) |
45 (1u << (Mips::AFGR64RegClassID - 32)) |
46 0,
47 // 64-95
48 (1u << (Mips::MSA128DRegClassID - 64)) |
49 (1u << (Mips::MSA128BRegClassID - 64)) |
50 (1u << (Mips::MSA128HRegClassID - 64)) |
51 (1u << (Mips::MSA128WRegClassID - 64)) |
52 (1u << (Mips::MSA128WEvensRegClassID - 64)) |
53 0,
54};
55const uint32_t GPRBRegBankCoverageData[] = {
56 // 0-31
57 (1u << (Mips::GPR32RegClassID - 0)) |
58 (1u << (Mips::GPR32NONZERORegClassID - 0)) |
59 (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
60 (1u << (Mips::CPU16RegsRegClassID - 0)) |
61 (1u << (Mips::GPRMM16RegClassID - 0)) |
62 (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
63 (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
64 (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
65 (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
66 (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
67 (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
68 (1u << (Mips::CPUSPRegRegClassID - 0)) |
69 (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
70 (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
71 (1u << (Mips::CPURARegRegClassID - 0)) |
72 (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
73 (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
74 (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
75 0,
76 // 32-63
77 (1u << (Mips::SP32RegClassID - 32)) |
78 (1u << (Mips::GP32RegClassID - 32)) |
79 (1u << (Mips::GPR32ZERORegClassID - 32)) |
80 0,
81 // 64-95
82 0,
83};
84
85constexpr RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
86constexpr RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
87} // end namespace Mips
88
89const RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
90 &Mips::FPRBRegBank,
91 &Mips::GPRBRegBank,
92};
93
94const unsigned MipsGenRegisterBankInfo::Sizes[] = {
95 // Mode = 0 (Default)
96 128,
97 32,
98};
99
100MipsGenRegisterBankInfo::MipsGenRegisterBankInfo(unsigned HwMode)
101 : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks, Sizes, HwMode) {
102 // Assert that RegBank indices match their ID's
103#ifndef NDEBUG
104 for (auto RB : enumerate(RegBanks))
105 assert(RB.index() == RB.value()->getID() && "Index != ID");
106#endif // NDEBUG
107}
108} // end namespace llvm
109#endif // GET_TARGET_REGBANK_IMPL
110