1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Subtarget Enumeration Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_SUBTARGETINFO_ENUM
11#undef GET_SUBTARGETINFO_ENUM
12
13namespace llvm {
14namespace NVPTX {
15enum {
16 PTX32 = 0,
17 PTX40 = 1,
18 PTX41 = 2,
19 PTX42 = 3,
20 PTX43 = 4,
21 PTX50 = 5,
22 PTX60 = 6,
23 PTX61 = 7,
24 PTX62 = 8,
25 PTX63 = 9,
26 PTX64 = 10,
27 PTX65 = 11,
28 PTX70 = 12,
29 PTX71 = 13,
30 PTX72 = 14,
31 PTX73 = 15,
32 PTX74 = 16,
33 PTX75 = 17,
34 PTX76 = 18,
35 PTX77 = 19,
36 PTX78 = 20,
37 PTX80 = 21,
38 PTX81 = 22,
39 PTX82 = 23,
40 PTX83 = 24,
41 PTX84 = 25,
42 PTX85 = 26,
43 SM20 = 27,
44 SM21 = 28,
45 SM30 = 29,
46 SM32 = 30,
47 SM35 = 31,
48 SM37 = 32,
49 SM50 = 33,
50 SM52 = 34,
51 SM53 = 35,
52 SM60 = 36,
53 SM61 = 37,
54 SM62 = 38,
55 SM70 = 39,
56 SM72 = 40,
57 SM75 = 41,
58 SM80 = 42,
59 SM86 = 43,
60 SM87 = 44,
61 SM89 = 45,
62 SM90 = 46,
63 SM90a = 47,
64 NumSubtargetFeatures = 48
65};
66} // end namespace NVPTX
67} // end namespace llvm
68
69#endif // GET_SUBTARGETINFO_ENUM
70
71
72#ifdef GET_SUBTARGETINFO_MACRO
73#undef GET_SUBTARGETINFO_MACRO
74#endif // GET_SUBTARGETINFO_MACRO
75
76
77#ifdef GET_SUBTARGETINFO_MC_DESC
78#undef GET_SUBTARGETINFO_MC_DESC
79
80namespace llvm {
81// Sorted (by key) array of values for CPU features.
82extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {
83 { "ptx32", "Use PTX version 32", NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
84 { "ptx40", "Use PTX version 40", NVPTX::PTX40, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
85 { "ptx41", "Use PTX version 41", NVPTX::PTX41, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
86 { "ptx42", "Use PTX version 42", NVPTX::PTX42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
87 { "ptx43", "Use PTX version 43", NVPTX::PTX43, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
88 { "ptx50", "Use PTX version 50", NVPTX::PTX50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
89 { "ptx60", "Use PTX version 60", NVPTX::PTX60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
90 { "ptx61", "Use PTX version 61", NVPTX::PTX61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
91 { "ptx62", "Use PTX version 62", NVPTX::PTX62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
92 { "ptx63", "Use PTX version 63", NVPTX::PTX63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
93 { "ptx64", "Use PTX version 64", NVPTX::PTX64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
94 { "ptx65", "Use PTX version 65", NVPTX::PTX65, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
95 { "ptx70", "Use PTX version 70", NVPTX::PTX70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
96 { "ptx71", "Use PTX version 71", NVPTX::PTX71, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
97 { "ptx72", "Use PTX version 72", NVPTX::PTX72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
98 { "ptx73", "Use PTX version 73", NVPTX::PTX73, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
99 { "ptx74", "Use PTX version 74", NVPTX::PTX74, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
100 { "ptx75", "Use PTX version 75", NVPTX::PTX75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
101 { "ptx76", "Use PTX version 76", NVPTX::PTX76, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
102 { "ptx77", "Use PTX version 77", NVPTX::PTX77, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
103 { "ptx78", "Use PTX version 78", NVPTX::PTX78, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
104 { "ptx80", "Use PTX version 80", NVPTX::PTX80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
105 { "ptx81", "Use PTX version 81", NVPTX::PTX81, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
106 { "ptx82", "Use PTX version 82", NVPTX::PTX82, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
107 { "ptx83", "Use PTX version 83", NVPTX::PTX83, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
108 { "ptx84", "Use PTX version 84", NVPTX::PTX84, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
109 { "ptx85", "Use PTX version 85", NVPTX::PTX85, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
110 { "sm_20", "Target SM 20", NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
111 { "sm_21", "Target SM 21", NVPTX::SM21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
112 { "sm_30", "Target SM 30", NVPTX::SM30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
113 { "sm_32", "Target SM 32", NVPTX::SM32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
114 { "sm_35", "Target SM 35", NVPTX::SM35, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
115 { "sm_37", "Target SM 37", NVPTX::SM37, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
116 { "sm_50", "Target SM 50", NVPTX::SM50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
117 { "sm_52", "Target SM 52", NVPTX::SM52, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
118 { "sm_53", "Target SM 53", NVPTX::SM53, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
119 { "sm_60", "Target SM 60", NVPTX::SM60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
120 { "sm_61", "Target SM 61", NVPTX::SM61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
121 { "sm_62", "Target SM 62", NVPTX::SM62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
122 { "sm_70", "Target SM 70", NVPTX::SM70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
123 { "sm_72", "Target SM 72", NVPTX::SM72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
124 { "sm_75", "Target SM 75", NVPTX::SM75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
125 { "sm_80", "Target SM 80", NVPTX::SM80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
126 { "sm_86", "Target SM 86", NVPTX::SM86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
127 { "sm_87", "Target SM 87", NVPTX::SM87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
128 { "sm_89", "Target SM 89", NVPTX::SM89, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
129 { "sm_90", "Target SM 90", NVPTX::SM90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
130 { "sm_90a", "Target SM 90a", NVPTX::SM90a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },
131};
132
133#ifdef DBGFIELD
134#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
135#endif
136#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
137#define DBGFIELD(x) x,
138#else
139#define DBGFIELD(x)
140#endif
141
142// ===============================================================
143// Data tables for the new per-operand machine model.
144
145// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
146extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {
147 { 0, 0, 0 }, // Invalid
148}; // NVPTXWriteProcResTable
149
150// {Cycles, WriteResourceID}
151extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {
152 { 0, 0}, // Invalid
153}; // NVPTXWriteLatencyTable
154
155// {UseIdx, WriteResourceID, Cycles}
156extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {
157 {0, 0, 0}, // Invalid
158}; // NVPTXReadAdvanceTable
159
160#undef DBGFIELD
161
162static const llvm::MCSchedModel NoSchedModel = {
163 MCSchedModel::DefaultIssueWidth,
164 MCSchedModel::DefaultMicroOpBufferSize,
165 MCSchedModel::DefaultLoopMicroOpBufferSize,
166 MCSchedModel::DefaultLoadLatency,
167 MCSchedModel::DefaultHighLatency,
168 MCSchedModel::DefaultMispredictPenalty,
169 false, // PostRAScheduler
170 false, // CompleteModel
171 false, // EnableIntervals
172 0, // Processor ID
173 nullptr, nullptr, 0, 0, // No instruction-level machine model.
174 nullptr, // No Itinerary
175 nullptr // No extra processor descriptor
176};
177
178// Sorted (by key) array of values for CPU subtype.
179extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[] = {
180 { "sm_20", { { { 0x8000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
181 { "sm_21", { { { 0x10000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
182 { "sm_30", { { { 0x20000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
183 { "sm_32", { { { 0x40000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
184 { "sm_35", { { { 0x80000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
185 { "sm_37", { { { 0x100000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
186 { "sm_50", { { { 0x200000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
187 { "sm_52", { { { 0x400000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
188 { "sm_53", { { { 0x800000008ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
189 { "sm_60", { { { 0x1000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
190 { "sm_61", { { { 0x2000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
191 { "sm_62", { { { 0x4000000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
192 { "sm_70", { { { 0x8000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
193 { "sm_72", { { { 0x10000000080ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
194 { "sm_75", { { { 0x20000000200ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
195 { "sm_80", { { { 0x40000001000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
196 { "sm_86", { { { 0x80000002000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
197 { "sm_87", { { { 0x100000010000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
198 { "sm_89", { { { 0x200000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
199 { "sm_90", { { { 0x400000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
200 { "sm_90a", { { { 0x800000200000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
201};
202
203namespace NVPTX_MC {
204unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
205 const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
206 // Don't know how to resolve this scheduling class.
207 return 0;
208}
209} // end namespace NVPTX_MC
210
211struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {
212 NVPTXGenMCSubtargetInfo(const Triple &TT,
213 StringRef CPU, StringRef TuneCPU, StringRef FS,
214 ArrayRef<SubtargetFeatureKV> PF,
215 ArrayRef<SubtargetSubTypeKV> PD,
216 const MCWriteProcResEntry *WPR,
217 const MCWriteLatencyEntry *WL,
218 const MCReadAdvanceEntry *RA, const InstrStage *IS,
219 const unsigned *OC, const unsigned *FP) :
220 MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
221 WPR, WL, RA, IS, OC, FP) { }
222
223 unsigned resolveVariantSchedClass(unsigned SchedClass,
224 const MCInst *MI, const MCInstrInfo *MCII,
225 unsigned CPUID) const override {
226 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
227 }
228};
229
230static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
231 return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, NVPTXFeatureKV, NVPTXSubTypeKV,
232 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
233 nullptr, nullptr, nullptr);
234}
235
236} // end namespace llvm
237
238#endif // GET_SUBTARGETINFO_MC_DESC
239
240
241#ifdef GET_SUBTARGETINFO_TARGET_DESC
242#undef GET_SUBTARGETINFO_TARGET_DESC
243
244#include "llvm/Support/Debug.h"
245#include "llvm/Support/raw_ostream.h"
246
247// ParseSubtargetFeatures - Parses features string setting specified
248// subtarget options.
249void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
250 LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
251 LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
252 LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
253 InitMCProcessorInfo(CPU, TuneCPU, FS);
254 const FeatureBitset &Bits = getFeatureBits();
255 if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;
256 if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;
257 if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;
258 if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;
259 if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;
260 if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;
261 if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;
262 if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;
263 if (Bits[NVPTX::PTX62] && PTXVersion < 62) PTXVersion = 62;
264 if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;
265 if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;
266 if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;
267 if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;
268 if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;
269 if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;
270 if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;
271 if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;
272 if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;
273 if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;
274 if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;
275 if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;
276 if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;
277 if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;
278 if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;
279 if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;
280 if (Bits[NVPTX::PTX84] && PTXVersion < 84) PTXVersion = 84;
281 if (Bits[NVPTX::PTX85] && PTXVersion < 85) PTXVersion = 85;
282 if (Bits[NVPTX::SM20] && FullSmVersion < 200) FullSmVersion = 200;
283 if (Bits[NVPTX::SM21] && FullSmVersion < 210) FullSmVersion = 210;
284 if (Bits[NVPTX::SM30] && FullSmVersion < 300) FullSmVersion = 300;
285 if (Bits[NVPTX::SM32] && FullSmVersion < 320) FullSmVersion = 320;
286 if (Bits[NVPTX::SM35] && FullSmVersion < 350) FullSmVersion = 350;
287 if (Bits[NVPTX::SM37] && FullSmVersion < 370) FullSmVersion = 370;
288 if (Bits[NVPTX::SM50] && FullSmVersion < 500) FullSmVersion = 500;
289 if (Bits[NVPTX::SM52] && FullSmVersion < 520) FullSmVersion = 520;
290 if (Bits[NVPTX::SM53] && FullSmVersion < 530) FullSmVersion = 530;
291 if (Bits[NVPTX::SM60] && FullSmVersion < 600) FullSmVersion = 600;
292 if (Bits[NVPTX::SM61] && FullSmVersion < 610) FullSmVersion = 610;
293 if (Bits[NVPTX::SM62] && FullSmVersion < 620) FullSmVersion = 620;
294 if (Bits[NVPTX::SM70] && FullSmVersion < 700) FullSmVersion = 700;
295 if (Bits[NVPTX::SM72] && FullSmVersion < 720) FullSmVersion = 720;
296 if (Bits[NVPTX::SM75] && FullSmVersion < 750) FullSmVersion = 750;
297 if (Bits[NVPTX::SM80] && FullSmVersion < 800) FullSmVersion = 800;
298 if (Bits[NVPTX::SM86] && FullSmVersion < 860) FullSmVersion = 860;
299 if (Bits[NVPTX::SM87] && FullSmVersion < 870) FullSmVersion = 870;
300 if (Bits[NVPTX::SM89] && FullSmVersion < 890) FullSmVersion = 890;
301 if (Bits[NVPTX::SM90] && FullSmVersion < 900) FullSmVersion = 900;
302 if (Bits[NVPTX::SM90a] && FullSmVersion < 901) FullSmVersion = 901;
303}
304#endif // GET_SUBTARGETINFO_TARGET_DESC
305
306
307#ifdef GET_SUBTARGETINFO_HEADER
308#undef GET_SUBTARGETINFO_HEADER
309
310namespace llvm {
311class DFAPacketizer;
312namespace NVPTX_MC {
313unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
314} // end namespace NVPTX_MC
315
316struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {
317 explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
318public:
319 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
320 unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
321 DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
322};
323} // end namespace llvm
324
325#endif // GET_SUBTARGETINFO_HEADER
326
327
328#ifdef GET_SUBTARGETINFO_CTOR
329#undef GET_SUBTARGETINFO_CTOR
330
331#include "llvm/CodeGen/TargetSchedule.h"
332
333namespace llvm {
334extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];
335extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[];
336extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];
337extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];
338extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];
339NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
340 : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(NVPTXFeatureKV, 48), ArrayRef(NVPTXSubTypeKV, 21),
341 NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable,
342 nullptr, nullptr, nullptr) {}
343
344unsigned NVPTXGenSubtargetInfo
345::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
346 report_fatal_error("Expected a variant SchedClass");
347} // NVPTXGenSubtargetInfo::resolveSchedClass
348
349unsigned NVPTXGenSubtargetInfo
350::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
351 return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
352} // NVPTXGenSubtargetInfo::resolveVariantSchedClass
353
354} // end namespace llvm
355
356#endif // GET_SUBTARGETINFO_CTOR
357
358
359#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
360#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
361
362#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
363
364
365#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
366#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
367
368#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
369
370