| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the PPC target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | const unsigned MAX_SUBTARGET_PREDICATES = 41; |
| 11 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 12 | #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 | |
| 14 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 | mutable MatcherState State; |
| 16 | typedef ComplexRendererFns(PPCInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 | typedef void(PPCInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 19 | static PPCInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 | static PPCInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 | const uint8_t *getMatchTable() const override; |
| 25 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 26 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 27 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 28 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 29 | |
| 30 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 31 | , State(0), |
| 32 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 33 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_IMPL |
| 36 | // LLT Objects. |
| 37 | enum { |
| 38 | GILLT_s1, |
| 39 | GILLT_s32, |
| 40 | GILLT_s64, |
| 41 | GILLT_s128, |
| 42 | GILLT_v2s64, |
| 43 | GILLT_v4s32, |
| 44 | GILLT_v8s16, |
| 45 | GILLT_v16s8, |
| 46 | GILLT_v256s1, |
| 47 | GILLT_v512s1, |
| 48 | }; |
| 49 | const static size_t NumTypeObjects = 10; |
| 50 | const static LLT TypeObjects[] = { |
| 51 | LLT::scalar(1), |
| 52 | LLT::scalar(32), |
| 53 | LLT::scalar(64), |
| 54 | LLT::scalar(128), |
| 55 | LLT::vector(ElementCount::getFixed(2), 64), |
| 56 | LLT::vector(ElementCount::getFixed(4), 32), |
| 57 | LLT::vector(ElementCount::getFixed(8), 16), |
| 58 | LLT::vector(ElementCount::getFixed(16), 8), |
| 59 | LLT::vector(ElementCount::getFixed(256), 1), |
| 60 | LLT::vector(ElementCount::getFixed(512), 1), |
| 61 | }; |
| 62 | |
| 63 | // Bits for subtarget features that participate in instruction matching. |
| 64 | enum SubtargetFeatureBits : uint8_t { |
| 65 | Feature_In32BitModeBit = 1, |
| 66 | Feature_In64BitModeBit = 9, |
| 67 | Feature_HasOnlyMSYNCBit = 23, |
| 68 | Feature_HasSYNCBit = 22, |
| 69 | Feature_HasSPEBit = 8, |
| 70 | Feature_HasICBTBit = 21, |
| 71 | Feature_HasBPERMDBit = 10, |
| 72 | Feature_HasExtDivBit = 3, |
| 73 | Feature_IsISA2_06Bit = 11, |
| 74 | Feature_IsISA2_07Bit = 40, |
| 75 | Feature_IsISA3_0Bit = 2, |
| 76 | Feature_HasFPUBit = 0, |
| 77 | Feature_PCRelativeMemopsBit = 37, |
| 78 | Feature_IsNotISA3_1Bit = 39, |
| 79 | Feature_IsAIXBit = 24, |
| 80 | Feature_NotAIXBit = 25, |
| 81 | Feature_IsISAFutureBit = 20, |
| 82 | Feature_IsNotISAFutureBit = 18, |
| 83 | Feature_HasAltivecBit = 4, |
| 84 | Feature_HasP8AltivecBit = 5, |
| 85 | Feature_HasP8CryptoBit = 6, |
| 86 | Feature_HasP9AltivecBit = 7, |
| 87 | Feature_HasVSXBit = 12, |
| 88 | Feature_IsLittleEndianBit = 26, |
| 89 | Feature_IsBigEndianBit = 27, |
| 90 | Feature_IsPPC64Bit = 31, |
| 91 | Feature_HasOnlySwappingMemOpsBit = 29, |
| 92 | Feature_NoP8VectorBit = 30, |
| 93 | Feature_HasP8VectorBit = 13, |
| 94 | Feature_HasDirectMoveBit = 14, |
| 95 | Feature_NoP9VectorBit = 28, |
| 96 | Feature_HasP9VectorBit = 15, |
| 97 | Feature_NoP9AltivecBit = 32, |
| 98 | Feature_NoP10VectorBit = 33, |
| 99 | Feature_HasP10VectorBit = 36, |
| 100 | Feature_HasHTMBit = 34, |
| 101 | Feature_IsPPC32Bit = 38, |
| 102 | Feature_PrefixInstrsBit = 16, |
| 103 | Feature_IsISA3_1Bit = 17, |
| 104 | Feature_PairedVectorMemopsBit = 35, |
| 105 | Feature_MMABit = 19, |
| 106 | }; |
| 107 | |
| 108 | PredicateBitset PPCInstructionSelector:: |
| 109 | computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const { |
| 110 | PredicateBitset Features{}; |
| 111 | if (!Subtarget->isPPC64()) |
| 112 | Features.set(Feature_In32BitModeBit); |
| 113 | if (Subtarget->isPPC64()) |
| 114 | Features.set(Feature_In64BitModeBit); |
| 115 | if (Subtarget->hasOnlyMSYNC()) |
| 116 | Features.set(Feature_HasOnlyMSYNCBit); |
| 117 | if (!Subtarget->hasOnlyMSYNC()) |
| 118 | Features.set(Feature_HasSYNCBit); |
| 119 | if (Subtarget->hasSPE()) |
| 120 | Features.set(Feature_HasSPEBit); |
| 121 | if (Subtarget->hasICBT()) |
| 122 | Features.set(Feature_HasICBTBit); |
| 123 | if (Subtarget->hasBPERMD()) |
| 124 | Features.set(Feature_HasBPERMDBit); |
| 125 | if (Subtarget->hasExtDiv()) |
| 126 | Features.set(Feature_HasExtDivBit); |
| 127 | if (Subtarget->isISA2_06()) |
| 128 | Features.set(Feature_IsISA2_06Bit); |
| 129 | if (Subtarget->isISA2_07()) |
| 130 | Features.set(Feature_IsISA2_07Bit); |
| 131 | if (Subtarget->isISA3_0()) |
| 132 | Features.set(Feature_IsISA3_0Bit); |
| 133 | if (Subtarget->hasFPU()) |
| 134 | Features.set(Feature_HasFPUBit); |
| 135 | if (Subtarget->hasPCRelativeMemops()) |
| 136 | Features.set(Feature_PCRelativeMemopsBit); |
| 137 | if (!Subtarget->isISA3_1()) |
| 138 | Features.set(Feature_IsNotISA3_1Bit); |
| 139 | if (Subtarget->isAIXABI()) |
| 140 | Features.set(Feature_IsAIXBit); |
| 141 | if (!Subtarget->isAIXABI()) |
| 142 | Features.set(Feature_NotAIXBit); |
| 143 | if (Subtarget->isISAFuture()) |
| 144 | Features.set(Feature_IsISAFutureBit); |
| 145 | if (!Subtarget->isISAFuture()) |
| 146 | Features.set(Feature_IsNotISAFutureBit); |
| 147 | if (Subtarget->hasAltivec()) |
| 148 | Features.set(Feature_HasAltivecBit); |
| 149 | if (Subtarget->hasP8Altivec()) |
| 150 | Features.set(Feature_HasP8AltivecBit); |
| 151 | if (Subtarget->hasP8Crypto()) |
| 152 | Features.set(Feature_HasP8CryptoBit); |
| 153 | if (Subtarget->hasP9Altivec()) |
| 154 | Features.set(Feature_HasP9AltivecBit); |
| 155 | if (Subtarget->hasVSX()) |
| 156 | Features.set(Feature_HasVSXBit); |
| 157 | if (Subtarget->isLittleEndian()) |
| 158 | Features.set(Feature_IsLittleEndianBit); |
| 159 | if (!Subtarget->isLittleEndian()) |
| 160 | Features.set(Feature_IsBigEndianBit); |
| 161 | if (Subtarget->isPPC64()) |
| 162 | Features.set(Feature_IsPPC64Bit); |
| 163 | if (!Subtarget->hasP9Vector()) |
| 164 | Features.set(Feature_HasOnlySwappingMemOpsBit); |
| 165 | if (!Subtarget->hasP8Vector()) |
| 166 | Features.set(Feature_NoP8VectorBit); |
| 167 | if (Subtarget->hasP8Vector()) |
| 168 | Features.set(Feature_HasP8VectorBit); |
| 169 | if (Subtarget->hasDirectMove()) |
| 170 | Features.set(Feature_HasDirectMoveBit); |
| 171 | if (!Subtarget->hasP9Vector()) |
| 172 | Features.set(Feature_NoP9VectorBit); |
| 173 | if (Subtarget->hasP9Vector()) |
| 174 | Features.set(Feature_HasP9VectorBit); |
| 175 | if (!Subtarget->hasP9Altivec()) |
| 176 | Features.set(Feature_NoP9AltivecBit); |
| 177 | if (!Subtarget->hasP10Vector()) |
| 178 | Features.set(Feature_NoP10VectorBit); |
| 179 | if (Subtarget->hasP10Vector()) |
| 180 | Features.set(Feature_HasP10VectorBit); |
| 181 | if (Subtarget->hasHTM()) |
| 182 | Features.set(Feature_HasHTMBit); |
| 183 | if (!Subtarget->isPPC64()) |
| 184 | Features.set(Feature_IsPPC32Bit); |
| 185 | if (Subtarget->hasPrefixInstrs()) |
| 186 | Features.set(Feature_PrefixInstrsBit); |
| 187 | if (Subtarget->isISA3_1()) |
| 188 | Features.set(Feature_IsISA3_1Bit); |
| 189 | if (Subtarget->pairedVectorMemops()) |
| 190 | Features.set(Feature_PairedVectorMemopsBit); |
| 191 | if (Subtarget->hasMMA()) |
| 192 | Features.set(Feature_MMABit); |
| 193 | return Features; |
| 194 | } |
| 195 | |
| 196 | void PPCInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 197 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const PPCSubtarget *)&MF.getSubtarget(), &MF); |
| 198 | } |
| 199 | PredicateBitset PPCInstructionSelector:: |
| 200 | computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget, const MachineFunction *MF) const { |
| 201 | PredicateBitset Features{}; |
| 202 | return Features; |
| 203 | } |
| 204 | |
| 205 | // Feature bitsets. |
| 206 | enum { |
| 207 | GIFBS_Invalid, |
| 208 | GIFBS_HasAltivec, |
| 209 | GIFBS_HasBPERMD, |
| 210 | GIFBS_HasExtDiv, |
| 211 | GIFBS_HasFPU, |
| 212 | GIFBS_HasHTM, |
| 213 | GIFBS_HasOnlyMSYNC, |
| 214 | GIFBS_HasP8Altivec, |
| 215 | GIFBS_HasP8Crypto, |
| 216 | GIFBS_HasP9Altivec, |
| 217 | GIFBS_HasSPE, |
| 218 | GIFBS_HasSYNC, |
| 219 | GIFBS_HasVSX, |
| 220 | GIFBS_In32BitMode, |
| 221 | GIFBS_In64BitMode, |
| 222 | GIFBS_IsAIX, |
| 223 | GIFBS_IsISA3_0, |
| 224 | GIFBS_IsISA3_1, |
| 225 | GIFBS_IsNotISA3_1, |
| 226 | GIFBS_NotAIX, |
| 227 | GIFBS_HasDirectMove_HasVSX, |
| 228 | GIFBS_HasFPU_IsISA3_1, |
| 229 | GIFBS_HasP10Vector_PrefixInstrs, |
| 230 | GIFBS_HasP8Altivec_HasVSX, |
| 231 | GIFBS_HasP8Vector_HasVSX, |
| 232 | GIFBS_HasP9Vector_HasVSX, |
| 233 | GIFBS_HasVSX_IsISA3_1, |
| 234 | GIFBS_In64BitMode_IsISA3_0, |
| 235 | GIFBS_IsISAFuture_MMA, |
| 236 | GIFBS_IsNotISAFuture_MMA, |
| 237 | GIFBS_HasP8Altivec_HasVSX_IsBigEndian, |
| 238 | GIFBS_HasP8Altivec_HasVSX_IsLittleEndian, |
| 239 | GIFBS_IsISAFuture_MMA_PrefixInstrs, |
| 240 | GIFBS_IsNotISAFuture_MMA_PrefixInstrs, |
| 241 | GIFBS_HasDirectMove_HasVSX_IsISA3_0_IsLittleEndian, |
| 242 | GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector, |
| 243 | GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32, |
| 244 | GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsISA3_0_IsPPC64, |
| 245 | GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector, |
| 246 | }; |
| 247 | constexpr static PredicateBitset FeatureBitsets[] { |
| 248 | {}, // GIFBS_Invalid |
| 249 | {Feature_HasAltivecBit, }, |
| 250 | {Feature_HasBPERMDBit, }, |
| 251 | {Feature_HasExtDivBit, }, |
| 252 | {Feature_HasFPUBit, }, |
| 253 | {Feature_HasHTMBit, }, |
| 254 | {Feature_HasOnlyMSYNCBit, }, |
| 255 | {Feature_HasP8AltivecBit, }, |
| 256 | {Feature_HasP8CryptoBit, }, |
| 257 | {Feature_HasP9AltivecBit, }, |
| 258 | {Feature_HasSPEBit, }, |
| 259 | {Feature_HasSYNCBit, }, |
| 260 | {Feature_HasVSXBit, }, |
| 261 | {Feature_In32BitModeBit, }, |
| 262 | {Feature_In64BitModeBit, }, |
| 263 | {Feature_IsAIXBit, }, |
| 264 | {Feature_IsISA3_0Bit, }, |
| 265 | {Feature_IsISA3_1Bit, }, |
| 266 | {Feature_IsNotISA3_1Bit, }, |
| 267 | {Feature_NotAIXBit, }, |
| 268 | {Feature_HasDirectMoveBit, Feature_HasVSXBit, }, |
| 269 | {Feature_HasFPUBit, Feature_IsISA3_1Bit, }, |
| 270 | {Feature_HasP10VectorBit, Feature_PrefixInstrsBit, }, |
| 271 | {Feature_HasP8AltivecBit, Feature_HasVSXBit, }, |
| 272 | {Feature_HasP8VectorBit, Feature_HasVSXBit, }, |
| 273 | {Feature_HasP9VectorBit, Feature_HasVSXBit, }, |
| 274 | {Feature_HasVSXBit, Feature_IsISA3_1Bit, }, |
| 275 | {Feature_In64BitModeBit, Feature_IsISA3_0Bit, }, |
| 276 | {Feature_IsISAFutureBit, Feature_MMABit, }, |
| 277 | {Feature_IsNotISAFutureBit, Feature_MMABit, }, |
| 278 | {Feature_HasP8AltivecBit, Feature_HasVSXBit, Feature_IsBigEndianBit, }, |
| 279 | {Feature_HasP8AltivecBit, Feature_HasVSXBit, Feature_IsLittleEndianBit, }, |
| 280 | {Feature_IsISAFutureBit, Feature_MMABit, Feature_PrefixInstrsBit, }, |
| 281 | {Feature_IsNotISAFutureBit, Feature_MMABit, Feature_PrefixInstrsBit, }, |
| 282 | {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsISA3_0Bit, Feature_IsLittleEndianBit, }, |
| 283 | {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsLittleEndianBit, Feature_NoP9VectorBit, }, |
| 284 | {Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsISA3_1Bit, Feature_IsPPC32Bit, }, |
| 285 | {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsISA3_0Bit, Feature_IsPPC64Bit, }, |
| 286 | {Feature_HasDirectMoveBit, Feature_HasVSXBit, Feature_IsBigEndianBit, Feature_IsPPC64Bit, Feature_NoP9VectorBit, }, |
| 287 | }; |
| 288 | |
| 289 | // ComplexPattern predicates. |
| 290 | enum { |
| 291 | GICP_Invalid, |
| 292 | }; |
| 293 | // See constructor for table contents |
| 294 | |
| 295 | PPCInstructionSelector::ComplexMatcherMemFn |
| 296 | PPCInstructionSelector::ComplexPredicateFns[] = { |
| 297 | nullptr, // GICP_Invalid |
| 298 | }; |
| 299 | |
| 300 | // PatFrag predicates. |
| 301 | bool PPCInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 302 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 303 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 304 | const auto &Operands = State.RecordedOperands; |
| 305 | (void)Operands; |
| 306 | (void)MRI; |
| 307 | llvm_unreachable("Unknown predicate"); |
| 308 | return false; |
| 309 | } |
| 310 | // PatFrag predicates. |
| 311 | enum { |
| 312 | GICXXPred_I64_Predicate_Msk2Imm = GICXXPred_Invalid + 1, |
| 313 | GICXXPred_I64_Predicate_Msk4Imm, |
| 314 | GICXXPred_I64_Predicate_Msk8Imm, |
| 315 | GICXXPred_I64_Predicate_i32immNonAllOneNonZero, |
| 316 | GICXXPred_I64_Predicate_imm32SExt16, |
| 317 | GICXXPred_I64_Predicate_imm64SExt16, |
| 318 | GICXXPred_I64_Predicate_imm64ZExt32, |
| 319 | GICXXPred_I64_Predicate_immNonAllOneAnyExt8, |
| 320 | GICXXPred_I64_Predicate_immSExt5NonZero, |
| 321 | }; |
| 322 | bool PPCInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 323 | switch (PredicateID) { |
| 324 | case GICXXPred_I64_Predicate_Msk2Imm: { |
| 325 | return isUInt<2>(Imm); |
| 326 | } |
| 327 | case GICXXPred_I64_Predicate_Msk4Imm: { |
| 328 | return isUInt<4>(Imm); |
| 329 | } |
| 330 | case GICXXPred_I64_Predicate_Msk8Imm: { |
| 331 | return isUInt<8>(Imm); |
| 332 | } |
| 333 | case GICXXPred_I64_Predicate_i32immNonAllOneNonZero: { |
| 334 | return Imm && (Imm != -1); |
| 335 | } |
| 336 | case GICXXPred_I64_Predicate_imm32SExt16: { |
| 337 | |
| 338 | // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit |
| 339 | // sign extended field. Used by instructions like 'addi'. |
| 340 | return (int32_t)Imm == (short)Imm; |
| 341 | |
| 342 | llvm_unreachable("imm32SExt16 should have returned"); |
| 343 | } |
| 344 | case GICXXPred_I64_Predicate_imm64SExt16: { |
| 345 | |
| 346 | // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit |
| 347 | // sign extended field. Used by instructions like 'addi'. |
| 348 | return (int64_t)Imm == (short)Imm; |
| 349 | |
| 350 | llvm_unreachable("imm64SExt16 should have returned"); |
| 351 | } |
| 352 | case GICXXPred_I64_Predicate_imm64ZExt32: { |
| 353 | |
| 354 | // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit |
| 355 | // zero extended field. |
| 356 | return isUInt<32>(Imm); |
| 357 | |
| 358 | llvm_unreachable("imm64ZExt32 should have returned"); |
| 359 | } |
| 360 | case GICXXPred_I64_Predicate_immNonAllOneAnyExt8: { |
| 361 | |
| 362 | return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); |
| 363 | |
| 364 | } |
| 365 | case GICXXPred_I64_Predicate_immSExt5NonZero: { |
| 366 | return Imm && isInt<5>(Imm); |
| 367 | } |
| 368 | } |
| 369 | llvm_unreachable("Unknown predicate"); |
| 370 | return false; |
| 371 | } |
| 372 | // PatFrag predicates. |
| 373 | bool PPCInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 374 | llvm_unreachable("Unknown predicate"); |
| 375 | return false; |
| 376 | } |
| 377 | // PatFrag predicates. |
| 378 | bool PPCInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 379 | llvm_unreachable("Unknown predicate"); |
| 380 | return false; |
| 381 | } |
| 382 | bool PPCInstructionSelector::testSimplePredicate(unsigned) const { |
| 383 | llvm_unreachable("PPCInstructionSelector does not support simple predicates!"); |
| 384 | return false; |
| 385 | } |
| 386 | // Custom renderers. |
| 387 | enum { |
| 388 | GICR_Invalid, |
| 389 | }; |
| 390 | PPCInstructionSelector::CustomRendererFn |
| 391 | PPCInstructionSelector::CustomRenderers[] = { |
| 392 | nullptr, // GICR_Invalid |
| 393 | }; |
| 394 | |
| 395 | bool PPCInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 396 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 397 | MachineIRBuilder B(I); |
| 398 | State.MIs.clear(); |
| 399 | State.MIs.push_back(&I); |
| 400 | |
| 401 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 402 | return true; |
| 403 | } |
| 404 | |
| 405 | return false; |
| 406 | } |
| 407 | |
| 408 | bool PPCInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 409 | llvm_unreachable("PPCInstructionSelector does not support custom C++ actions!"); |
| 410 | } |
| 411 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 412 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8) |
| 413 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24) |
| 414 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56) |
| 415 | #else |
| 416 | #define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val) |
| 417 | #define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val) |
| 418 | #define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val) |
| 419 | #endif |
| 420 | const uint8_t *PPCInstructionSelector::getMatchTable() const { |
| 421 | constexpr static uint8_t MatchTable0[] = { |
| 422 | GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(51), GIMT_Encode2(274), /*)*//*default:*//*Label 82*/ GIMT_Encode4(97181), |
| 423 | /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(902), |
| 424 | /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(1219), |
| 425 | /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(1660), |
| 426 | /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(1942), |
| 427 | /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(2098), |
| 428 | /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(2254), |
| 429 | /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(2416), GIMT_Encode4(0), GIMT_Encode4(0), |
| 430 | /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(2578), |
| 431 | /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(3212), |
| 432 | /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(3846), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 433 | /*TargetOpcode::G_BUILD_VECTOR*//*Label 10*/ GIMT_Encode4(5350), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 434 | /*TargetOpcode::G_BITCAST*//*Label 11*/ GIMT_Encode4(6317), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 435 | /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 12*/ GIMT_Encode4(8594), |
| 436 | /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 13*/ GIMT_Encode4(8866), |
| 437 | /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 14*/ GIMT_Encode4(9113), |
| 438 | /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 15*/ GIMT_Encode4(9241), GIMT_Encode4(0), |
| 439 | /*TargetOpcode::G_READCYCLECOUNTER*//*Label 16*/ GIMT_Encode4(9369), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 440 | /*TargetOpcode::G_FENCE*//*Label 17*/ GIMT_Encode4(9389), GIMT_Encode4(0), |
| 441 | /*TargetOpcode::G_BRCOND*//*Label 18*/ GIMT_Encode4(9514), GIMT_Encode4(0), GIMT_Encode4(0), |
| 442 | /*TargetOpcode::G_INTRINSIC*//*Label 19*/ GIMT_Encode4(9577), |
| 443 | /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 20*/ GIMT_Encode4(35305), GIMT_Encode4(0), GIMT_Encode4(0), |
| 444 | /*TargetOpcode::G_ANYEXT*//*Label 21*/ GIMT_Encode4(37995), |
| 445 | /*TargetOpcode::G_TRUNC*//*Label 22*/ GIMT_Encode4(38181), |
| 446 | /*TargetOpcode::G_CONSTANT*//*Label 23*/ GIMT_Encode4(38367), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 447 | /*TargetOpcode::G_SEXT*//*Label 24*/ GIMT_Encode4(38519), GIMT_Encode4(0), |
| 448 | /*TargetOpcode::G_ZEXT*//*Label 25*/ GIMT_Encode4(38725), |
| 449 | /*TargetOpcode::G_SHL*//*Label 26*/ GIMT_Encode4(38911), |
| 450 | /*TargetOpcode::G_LSHR*//*Label 27*/ GIMT_Encode4(39261), |
| 451 | /*TargetOpcode::G_ASHR*//*Label 28*/ GIMT_Encode4(39611), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 452 | /*TargetOpcode::G_ROTL*//*Label 29*/ GIMT_Encode4(39975), |
| 453 | /*TargetOpcode::G_ICMP*//*Label 30*/ GIMT_Encode4(40283), |
| 454 | /*TargetOpcode::G_FCMP*//*Label 31*/ GIMT_Encode4(44285), GIMT_Encode4(0), GIMT_Encode4(0), |
| 455 | /*TargetOpcode::G_SELECT*//*Label 32*/ GIMT_Encode4(47860), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 456 | /*TargetOpcode::G_UMULH*//*Label 33*/ GIMT_Encode4(48957), |
| 457 | /*TargetOpcode::G_SMULH*//*Label 34*/ GIMT_Encode4(49087), |
| 458 | /*TargetOpcode::G_UADDSAT*//*Label 35*/ GIMT_Encode4(49217), |
| 459 | /*TargetOpcode::G_SADDSAT*//*Label 36*/ GIMT_Encode4(49319), |
| 460 | /*TargetOpcode::G_USUBSAT*//*Label 37*/ GIMT_Encode4(49421), |
| 461 | /*TargetOpcode::G_SSUBSAT*//*Label 38*/ GIMT_Encode4(49523), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 462 | /*TargetOpcode::G_FADD*//*Label 39*/ GIMT_Encode4(49625), |
| 463 | /*TargetOpcode::G_FSUB*//*Label 40*/ GIMT_Encode4(49920), |
| 464 | /*TargetOpcode::G_FMUL*//*Label 41*/ GIMT_Encode4(50215), |
| 465 | /*TargetOpcode::G_FMA*//*Label 42*/ GIMT_Encode4(50565), GIMT_Encode4(0), |
| 466 | /*TargetOpcode::G_FDIV*//*Label 43*/ GIMT_Encode4(51146), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 467 | /*TargetOpcode::G_FNEG*//*Label 44*/ GIMT_Encode4(51416), |
| 468 | /*TargetOpcode::G_FPEXT*//*Label 45*/ GIMT_Encode4(53806), |
| 469 | /*TargetOpcode::G_FPTRUNC*//*Label 46*/ GIMT_Encode4(53967), |
| 470 | /*TargetOpcode::G_FPTOSI*//*Label 47*/ GIMT_Encode4(54124), |
| 471 | /*TargetOpcode::G_FPTOUI*//*Label 48*/ GIMT_Encode4(54384), |
| 472 | /*TargetOpcode::G_SITOFP*//*Label 49*/ GIMT_Encode4(54644), |
| 473 | /*TargetOpcode::G_UITOFP*//*Label 50*/ GIMT_Encode4(54888), |
| 474 | /*TargetOpcode::G_FABS*//*Label 51*/ GIMT_Encode4(55132), |
| 475 | /*TargetOpcode::G_FCOPYSIGN*//*Label 52*/ GIMT_Encode4(55421), GIMT_Encode4(0), GIMT_Encode4(0), |
| 476 | /*TargetOpcode::G_FMINNUM*//*Label 53*/ GIMT_Encode4(55731), |
| 477 | /*TargetOpcode::G_FMAXNUM*//*Label 54*/ GIMT_Encode4(55811), |
| 478 | /*TargetOpcode::G_FMINNUM_IEEE*//*Label 55*/ GIMT_Encode4(55891), |
| 479 | /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 56*/ GIMT_Encode4(56030), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 480 | /*TargetOpcode::G_SMIN*//*Label 57*/ GIMT_Encode4(56169), |
| 481 | /*TargetOpcode::G_SMAX*//*Label 58*/ GIMT_Encode4(56343), |
| 482 | /*TargetOpcode::G_UMIN*//*Label 59*/ GIMT_Encode4(56517), |
| 483 | /*TargetOpcode::G_UMAX*//*Label 60*/ GIMT_Encode4(56691), GIMT_Encode4(0), |
| 484 | /*TargetOpcode::G_LROUND*//*Label 61*/ GIMT_Encode4(56865), |
| 485 | /*TargetOpcode::G_LLROUND*//*Label 62*/ GIMT_Encode4(57027), |
| 486 | /*TargetOpcode::G_BR*//*Label 63*/ GIMT_Encode4(57189), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 487 | /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 64*/ GIMT_Encode4(57205), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 488 | /*TargetOpcode::G_CTTZ*//*Label 65*/ GIMT_Encode4(57323), GIMT_Encode4(0), |
| 489 | /*TargetOpcode::G_CTLZ*//*Label 66*/ GIMT_Encode4(57501), GIMT_Encode4(0), |
| 490 | /*TargetOpcode::G_CTPOP*//*Label 67*/ GIMT_Encode4(57673), |
| 491 | /*TargetOpcode::G_BSWAP*//*Label 68*/ GIMT_Encode4(57845), |
| 492 | /*TargetOpcode::G_BITREVERSE*//*Label 69*/ GIMT_Encode4(58103), |
| 493 | /*TargetOpcode::G_FCEIL*//*Label 70*/ GIMT_Encode4(94109), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 494 | /*TargetOpcode::G_FSQRT*//*Label 71*/ GIMT_Encode4(94381), |
| 495 | /*TargetOpcode::G_FFLOOR*//*Label 72*/ GIMT_Encode4(94598), |
| 496 | /*TargetOpcode::G_FRINT*//*Label 73*/ GIMT_Encode4(94870), |
| 497 | /*TargetOpcode::G_FNEARBYINT*//*Label 74*/ GIMT_Encode4(95079), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 498 | /*TargetOpcode::G_STRICT_FADD*//*Label 75*/ GIMT_Encode4(95313), |
| 499 | /*TargetOpcode::G_STRICT_FSUB*//*Label 76*/ GIMT_Encode4(95583), |
| 500 | /*TargetOpcode::G_STRICT_FMUL*//*Label 77*/ GIMT_Encode4(95853), |
| 501 | /*TargetOpcode::G_STRICT_FDIV*//*Label 78*/ GIMT_Encode4(96123), GIMT_Encode4(0), |
| 502 | /*TargetOpcode::G_STRICT_FMA*//*Label 79*/ GIMT_Encode4(96393), |
| 503 | /*TargetOpcode::G_STRICT_FSQRT*//*Label 80*/ GIMT_Encode4(96951), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 504 | /*TargetOpcode::G_TRAP*//*Label 81*/ GIMT_Encode4(97168), |
| 505 | // Label 0: @902 |
| 506 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 91*/ GIMT_Encode4(1218), |
| 507 | /*GILLT_s1*//*Label 83*/ GIMT_Encode4(945), |
| 508 | /*GILLT_s32*//*Label 84*/ GIMT_Encode4(968), |
| 509 | /*GILLT_s64*//*Label 85*/ GIMT_Encode4(1028), |
| 510 | /*GILLT_s128*//*Label 86*/ GIMT_Encode4(1088), |
| 511 | /*GILLT_v2s64*//*Label 87*/ GIMT_Encode4(1114), |
| 512 | /*GILLT_v4s32*//*Label 88*/ GIMT_Encode4(1140), |
| 513 | /*GILLT_v8s16*//*Label 89*/ GIMT_Encode4(1166), |
| 514 | /*GILLT_v16s8*//*Label 90*/ GIMT_Encode4(1192), |
| 515 | // Label 83: @945 |
| 516 | GIM_Try, /*On fail goto*//*Label 92*/ GIMT_Encode4(967), // Rule ID 3616 // |
| 517 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 518 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 520 | // (add:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b) |
| 521 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR), |
| 522 | GIR_RootConstrainSelectedInstOperands, |
| 523 | // GIR_Coverage, 3616, |
| 524 | GIR_Done, |
| 525 | // Label 92: @967 |
| 526 | GIM_Reject, |
| 527 | // Label 84: @968 |
| 528 | GIM_Try, /*On fail goto*//*Label 93*/ GIMT_Encode4(1027), |
| 529 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 530 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 532 | GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1014), // Rule ID 104 // |
| 533 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 534 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 535 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 536 | // MIs[1] Operand 1 |
| 537 | // No operand predicates |
| 538 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 539 | // (add:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D) => (ADDI:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] }):$D) |
| 540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDI), |
| 541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 542 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 543 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D |
| 544 | GIR_RootConstrainSelectedInstOperands, |
| 545 | // GIR_Coverage, 104, |
| 546 | GIR_EraseRootFromParent_Done, |
| 547 | // Label 94: @1014 |
| 548 | GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1026), // Rule ID 196 // |
| 549 | // (add:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (ADD4:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 550 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ADD4), |
| 551 | GIR_RootConstrainSelectedInstOperands, |
| 552 | // GIR_Coverage, 196, |
| 553 | GIR_Done, |
| 554 | // Label 95: @1026 |
| 555 | GIM_Reject, |
| 556 | // Label 93: @1027 |
| 557 | GIM_Reject, |
| 558 | // Label 85: @1028 |
| 559 | GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1087), |
| 560 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 561 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 563 | GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1074), // Rule ID 656 // |
| 564 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 565 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 566 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 567 | // MIs[1] Operand 1 |
| 568 | // No operand predicates |
| 569 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 570 | // (add:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D) => (ADDI8:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] }):$D) |
| 571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDI8), |
| 572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 573 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 574 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D |
| 575 | GIR_RootConstrainSelectedInstOperands, |
| 576 | // GIR_Coverage, 656, |
| 577 | GIR_EraseRootFromParent_Done, |
| 578 | // Label 97: @1074 |
| 579 | GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1086), // Rule ID 652 // |
| 580 | // (add:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (ADD8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 581 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ADD8), |
| 582 | GIR_RootConstrainSelectedInstOperands, |
| 583 | // GIR_Coverage, 652, |
| 584 | GIR_Done, |
| 585 | // Label 98: @1086 |
| 586 | GIM_Reject, |
| 587 | // Label 96: @1087 |
| 588 | GIM_Reject, |
| 589 | // Label 86: @1088 |
| 590 | GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1113), // Rule ID 467 // |
| 591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 592 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 593 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 595 | // (add:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VADDUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 596 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUQM), |
| 597 | GIR_RootConstrainSelectedInstOperands, |
| 598 | // GIR_Coverage, 467, |
| 599 | GIR_Done, |
| 600 | // Label 99: @1113 |
| 601 | GIM_Reject, |
| 602 | // Label 87: @1114 |
| 603 | GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1139), // Rule ID 466 // |
| 604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 605 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 606 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 608 | // (add:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VADDUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 609 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUDM), |
| 610 | GIR_RootConstrainSelectedInstOperands, |
| 611 | // GIR_Coverage, 466, |
| 612 | GIR_Done, |
| 613 | // Label 100: @1139 |
| 614 | GIM_Reject, |
| 615 | // Label 88: @1140 |
| 616 | GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1165), // Rule ID 300 // |
| 617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 619 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 621 | // (add:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 622 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUWM), |
| 623 | GIR_RootConstrainSelectedInstOperands, |
| 624 | // GIR_Coverage, 300, |
| 625 | GIR_Done, |
| 626 | // Label 101: @1165 |
| 627 | GIM_Reject, |
| 628 | // Label 89: @1166 |
| 629 | GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1191), // Rule ID 299 // |
| 630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 631 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 634 | // (add:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 635 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUHM), |
| 636 | GIR_RootConstrainSelectedInstOperands, |
| 637 | // GIR_Coverage, 299, |
| 638 | GIR_Done, |
| 639 | // Label 102: @1191 |
| 640 | GIM_Reject, |
| 641 | // Label 90: @1192 |
| 642 | GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1217), // Rule ID 298 // |
| 643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 644 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 645 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 647 | // (add:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 648 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUBM), |
| 649 | GIR_RootConstrainSelectedInstOperands, |
| 650 | // GIR_Coverage, 298, |
| 651 | GIR_Done, |
| 652 | // Label 103: @1217 |
| 653 | GIM_Reject, |
| 654 | // Label 91: @1218 |
| 655 | GIM_Reject, |
| 656 | // Label 1: @1219 |
| 657 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 112*/ GIMT_Encode4(1659), |
| 658 | /*GILLT_s1*//*Label 104*/ GIMT_Encode4(1262), |
| 659 | /*GILLT_s32*//*Label 105*/ GIMT_Encode4(1285), |
| 660 | /*GILLT_s64*//*Label 106*/ GIMT_Encode4(1370), |
| 661 | /*GILLT_s128*//*Label 107*/ GIMT_Encode4(1455), |
| 662 | /*GILLT_v2s64*//*Label 108*/ GIMT_Encode4(1481), |
| 663 | /*GILLT_v4s32*//*Label 109*/ GIMT_Encode4(1544), |
| 664 | /*GILLT_v8s16*//*Label 110*/ GIMT_Encode4(1607), |
| 665 | /*GILLT_v16s8*//*Label 111*/ GIMT_Encode4(1633), |
| 666 | // Label 104: @1262 |
| 667 | GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1284), // Rule ID 3617 // |
| 668 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 669 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 671 | // (sub:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b) |
| 672 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR), |
| 673 | GIR_RootConstrainSelectedInstOperands, |
| 674 | // GIR_Coverage, 3617, |
| 675 | GIR_Done, |
| 676 | // Label 113: @1284 |
| 677 | GIM_Reject, |
| 678 | // Label 105: @1285 |
| 679 | GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(1369), |
| 680 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 681 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 683 | GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(1318), // Rule ID 208 // |
| 684 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 685 | // (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$RA) => (NEG:{ *:[i32] } i32:{ *:[i32] }:$RA) |
| 686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NEG), |
| 687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 688 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 689 | GIR_RootConstrainSelectedInstOperands, |
| 690 | // GIR_Coverage, 208, |
| 691 | GIR_EraseRootFromParent_Done, |
| 692 | // Label 115: @1318 |
| 693 | GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1352), // Rule ID 1200 // |
| 694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 695 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 696 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 697 | // MIs[1] Operand 1 |
| 698 | // No operand predicates |
| 699 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 700 | // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, i32:{ *:[i32] }:$in) => (SUBFIC:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm) |
| 701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBFIC), |
| 702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 703 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 704 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 705 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0, |
| 706 | GIR_RootConstrainSelectedInstOperands, |
| 707 | // GIR_Coverage, 1200, |
| 708 | GIR_EraseRootFromParent_Done, |
| 709 | // Label 116: @1352 |
| 710 | GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1368), // Rule ID 206 // |
| 711 | // (sub:{ *:[i32] } i32:{ *:[i32] }:$RB, i32:{ *:[i32] }:$RA) => (SUBF:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBF), |
| 713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 714 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 715 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 716 | GIR_RootConstrainSelectedInstOperands, |
| 717 | // GIR_Coverage, 206, |
| 718 | GIR_EraseRootFromParent_Done, |
| 719 | // Label 117: @1368 |
| 720 | GIM_Reject, |
| 721 | // Label 114: @1369 |
| 722 | GIM_Reject, |
| 723 | // Label 106: @1370 |
| 724 | GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(1454), |
| 725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 726 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 728 | GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(1403), // Rule ID 662 // |
| 729 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 730 | // (sub:{ *:[i64] } 0:{ *:[i64] }, i64:{ *:[i64] }:$RA) => (NEG8:{ *:[i64] } i64:{ *:[i64] }:$RA) |
| 731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NEG8), |
| 732 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 733 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 734 | GIR_RootConstrainSelectedInstOperands, |
| 735 | // GIR_Coverage, 662, |
| 736 | GIR_EraseRootFromParent_Done, |
| 737 | // Label 119: @1403 |
| 738 | GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(1437), // Rule ID 1522 // |
| 739 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 740 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 741 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 742 | // MIs[1] Operand 1 |
| 743 | // No operand predicates |
| 744 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 745 | // (sub:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, i64:{ *:[i64] }:$in) => (SUBFIC8:{ *:[i64] }:{ *:[i32] } ?:{ *:[i64] }:$in, (imm:{ *:[i64] }):$imm) |
| 746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBFIC8), |
| 747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 748 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 749 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 750 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0, |
| 751 | GIR_RootConstrainSelectedInstOperands, |
| 752 | // GIR_Coverage, 1522, |
| 753 | GIR_EraseRootFromParent_Done, |
| 754 | // Label 120: @1437 |
| 755 | GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(1453), // Rule ID 661 // |
| 756 | // (sub:{ *:[i64] } i64:{ *:[i64] }:$RB, i64:{ *:[i64] }:$RA) => (SUBF8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SUBF8), |
| 758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 759 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 760 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 761 | GIR_RootConstrainSelectedInstOperands, |
| 762 | // GIR_Coverage, 661, |
| 763 | GIR_EraseRootFromParent_Done, |
| 764 | // Label 121: @1453 |
| 765 | GIM_Reject, |
| 766 | // Label 118: @1454 |
| 767 | GIM_Reject, |
| 768 | // Label 107: @1455 |
| 769 | GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(1480), // Rule ID 472 // |
| 770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 771 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 772 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 774 | // (sub:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VSUBUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 775 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUQM), |
| 776 | GIR_RootConstrainSelectedInstOperands, |
| 777 | // GIR_Coverage, 472, |
| 778 | GIR_Done, |
| 779 | // Label 122: @1480 |
| 780 | GIM_Reject, |
| 781 | // Label 108: @1481 |
| 782 | GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(1543), |
| 783 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 786 | GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(1527), // Rule ID 539 // |
| 787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 789 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 790 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 791 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 792 | // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, v2i64:{ *:[v2i64] }:$VB) => (VNEGD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) |
| 793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNEGD), |
| 794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 795 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 796 | GIR_RootConstrainSelectedInstOperands, |
| 797 | // GIR_Coverage, 539, |
| 798 | GIR_EraseRootFromParent_Done, |
| 799 | // Label 124: @1527 |
| 800 | GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(1542), // Rule ID 471 // |
| 801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 802 | // (sub:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VSUBUDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 803 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUDM), |
| 804 | GIR_RootConstrainSelectedInstOperands, |
| 805 | // GIR_Coverage, 471, |
| 806 | GIR_Done, |
| 807 | // Label 125: @1542 |
| 808 | GIM_Reject, |
| 809 | // Label 123: @1543 |
| 810 | GIM_Reject, |
| 811 | // Label 109: @1544 |
| 812 | GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(1606), |
| 813 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 814 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 816 | GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(1590), // Rule ID 538 // |
| 817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 818 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 819 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 820 | GIM_CheckIsBuildVectorAllZeros, /*MI*/1, |
| 821 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 822 | // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, v4i32:{ *:[v4i32] }:$VB) => (VNEGW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) |
| 823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNEGW), |
| 824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 825 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 826 | GIR_RootConstrainSelectedInstOperands, |
| 827 | // GIR_Coverage, 538, |
| 828 | GIR_EraseRootFromParent_Done, |
| 829 | // Label 127: @1590 |
| 830 | GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(1605), // Rule ID 370 // |
| 831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 832 | // (sub:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 833 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUWM), |
| 834 | GIR_RootConstrainSelectedInstOperands, |
| 835 | // GIR_Coverage, 370, |
| 836 | GIR_Done, |
| 837 | // Label 128: @1605 |
| 838 | GIM_Reject, |
| 839 | // Label 126: @1606 |
| 840 | GIM_Reject, |
| 841 | // Label 110: @1607 |
| 842 | GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(1632), // Rule ID 369 // |
| 843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 844 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 845 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 847 | // (sub:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 848 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUHM), |
| 849 | GIR_RootConstrainSelectedInstOperands, |
| 850 | // GIR_Coverage, 369, |
| 851 | GIR_Done, |
| 852 | // Label 129: @1632 |
| 853 | GIM_Reject, |
| 854 | // Label 111: @1633 |
| 855 | GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(1658), // Rule ID 368 // |
| 856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 857 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 860 | // (sub:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBUBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 861 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUBM), |
| 862 | GIR_RootConstrainSelectedInstOperands, |
| 863 | // GIR_Coverage, 368, |
| 864 | GIR_Done, |
| 865 | // Label 130: @1658 |
| 866 | GIM_Reject, |
| 867 | // Label 112: @1659 |
| 868 | GIM_Reject, |
| 869 | // Label 2: @1660 |
| 870 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(7), /*)*//*default:*//*Label 137*/ GIMT_Encode4(1941), |
| 871 | /*GILLT_s1*//*Label 131*/ GIMT_Encode4(1699), |
| 872 | /*GILLT_s32*//*Label 132*/ GIMT_Encode4(1722), |
| 873 | /*GILLT_s64*//*Label 133*/ GIMT_Encode4(1782), GIMT_Encode4(0), |
| 874 | /*GILLT_v2s64*//*Label 134*/ GIMT_Encode4(1842), |
| 875 | /*GILLT_v4s32*//*Label 135*/ GIMT_Encode4(1868), |
| 876 | /*GILLT_v8s16*//*Label 136*/ GIMT_Encode4(1894), |
| 877 | // Label 131: @1699 |
| 878 | GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(1721), // Rule ID 3618 // |
| 879 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 882 | // (mul:{ *:[i1] } i1:{ *:[i1] }:$a, i1:{ *:[i1] }:$b) => (CRAND:{ *:[i1] } ?:{ *:[i1] }:$a, ?:{ *:[i1] }:$b) |
| 883 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRAND), |
| 884 | GIR_RootConstrainSelectedInstOperands, |
| 885 | // GIR_Coverage, 3618, |
| 886 | GIR_Done, |
| 887 | // Label 138: @1721 |
| 888 | GIM_Reject, |
| 889 | // Label 132: @1722 |
| 890 | GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(1781), |
| 891 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 894 | GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(1768), // Rule ID 108 // |
| 895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 897 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 898 | // MIs[1] Operand 1 |
| 899 | // No operand predicates |
| 900 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 901 | // (mul:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D) => (MULLI:{ *:[i32] } i32:{ *:[i32] }:$RA, (imm:{ *:[i32] }):$D) |
| 902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULLI), |
| 903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 904 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 905 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D |
| 906 | GIR_RootConstrainSelectedInstOperands, |
| 907 | // GIR_Coverage, 108, |
| 908 | GIR_EraseRootFromParent_Done, |
| 909 | // Label 140: @1768 |
| 910 | GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(1780), // Rule ID 205 // |
| 911 | // (mul:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULLW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 912 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULLW), |
| 913 | GIR_RootConstrainSelectedInstOperands, |
| 914 | // GIR_Coverage, 205, |
| 915 | GIR_Done, |
| 916 | // Label 141: @1780 |
| 917 | GIM_Reject, |
| 918 | // Label 139: @1781 |
| 919 | GIM_Reject, |
| 920 | // Label 133: @1782 |
| 921 | GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(1841), |
| 922 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 923 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 925 | GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(1828), // Rule ID 696 // |
| 926 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 927 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 928 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 929 | // MIs[1] Operand 1 |
| 930 | // No operand predicates |
| 931 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 932 | // (mul:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D) => (MULLI8:{ *:[i64] } i64:{ *:[i64] }:$RA, (imm:{ *:[i64] }):$D) |
| 933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULLI8), |
| 934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 935 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 936 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D |
| 937 | GIR_RootConstrainSelectedInstOperands, |
| 938 | // GIR_Coverage, 696, |
| 939 | GIR_EraseRootFromParent_Done, |
| 940 | // Label 143: @1828 |
| 941 | GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(1840), // Rule ID 695 // |
| 942 | // (mul:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULLD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 943 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULLD), |
| 944 | GIR_RootConstrainSelectedInstOperands, |
| 945 | // GIR_Coverage, 695, |
| 946 | GIR_Done, |
| 947 | // Label 144: @1840 |
| 948 | GIM_Reject, |
| 949 | // Label 142: @1841 |
| 950 | GIM_Reject, |
| 951 | // Label 134: @1842 |
| 952 | GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(1867), // Rule ID 1112 // |
| 953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 954 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 955 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 957 | // (mul:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 958 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULLD), |
| 959 | GIR_RootConstrainSelectedInstOperands, |
| 960 | // GIR_Coverage, 1112, |
| 961 | GIR_Done, |
| 962 | // Label 145: @1867 |
| 963 | GIM_Reject, |
| 964 | // Label 135: @1868 |
| 965 | GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(1893), // Rule ID 458 // |
| 966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 967 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 968 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 970 | // (mul:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULUWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 971 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULUWM), |
| 972 | GIR_RootConstrainSelectedInstOperands, |
| 973 | // GIR_Coverage, 458, |
| 974 | GIR_Done, |
| 975 | // Label 146: @1893 |
| 976 | GIM_Reject, |
| 977 | // Label 136: @1894 |
| 978 | GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(1940), // Rule ID 1278 // |
| 979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 981 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 983 | // (mul:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VMLADDUHM:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB, (V_SET0H:{ *:[v8i16] })) |
| 984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::V_SET0H), |
| 986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 987 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM), |
| 989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 990 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 991 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 993 | GIR_RootConstrainSelectedInstOperands, |
| 994 | // GIR_Coverage, 1278, |
| 995 | GIR_EraseRootFromParent_Done, |
| 996 | // Label 147: @1940 |
| 997 | GIM_Reject, |
| 998 | // Label 137: @1941 |
| 999 | GIM_Reject, |
| 1000 | // Label 3: @1942 |
| 1001 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 153*/ GIMT_Encode4(2097), |
| 1002 | /*GILLT_s32*//*Label 148*/ GIMT_Encode4(1973), |
| 1003 | /*GILLT_s64*//*Label 149*/ GIMT_Encode4(1996), |
| 1004 | /*GILLT_s128*//*Label 150*/ GIMT_Encode4(2019), |
| 1005 | /*GILLT_v2s64*//*Label 151*/ GIMT_Encode4(2045), |
| 1006 | /*GILLT_v4s32*//*Label 152*/ GIMT_Encode4(2071), |
| 1007 | // Label 148: @1973 |
| 1008 | GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(1995), // Rule ID 199 // |
| 1009 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1012 | // (sdiv:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (DIVW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 1013 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVW), |
| 1014 | GIR_RootConstrainSelectedInstOperands, |
| 1015 | // GIR_Coverage, 199, |
| 1016 | GIR_Done, |
| 1017 | // Label 154: @1995 |
| 1018 | GIM_Reject, |
| 1019 | // Label 149: @1996 |
| 1020 | GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2018), // Rule ID 687 // |
| 1021 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1022 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 1024 | // (sdiv:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (DIVD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 1025 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVD), |
| 1026 | GIR_RootConstrainSelectedInstOperands, |
| 1027 | // GIR_Coverage, 687, |
| 1028 | GIR_Done, |
| 1029 | // Label 155: @2018 |
| 1030 | GIM_Reject, |
| 1031 | // Label 150: @2019 |
| 1032 | GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(2044), // Rule ID 1136 // |
| 1033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1034 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 1035 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 1036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1037 | // (sdiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 1038 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSQ), |
| 1039 | GIR_RootConstrainSelectedInstOperands, |
| 1040 | // GIR_Coverage, 1136, |
| 1041 | GIR_Done, |
| 1042 | // Label 156: @2044 |
| 1043 | GIM_Reject, |
| 1044 | // Label 151: @2045 |
| 1045 | GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(2070), // Rule ID 1123 // |
| 1046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1047 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1048 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1050 | // (sdiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 1051 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSD), |
| 1052 | GIR_RootConstrainSelectedInstOperands, |
| 1053 | // GIR_Coverage, 1123, |
| 1054 | GIR_Done, |
| 1055 | // Label 157: @2070 |
| 1056 | GIM_Reject, |
| 1057 | // Label 152: @2071 |
| 1058 | GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(2096), // Rule ID 1121 // |
| 1059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1060 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1061 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1063 | // (sdiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1064 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVSW), |
| 1065 | GIR_RootConstrainSelectedInstOperands, |
| 1066 | // GIR_Coverage, 1121, |
| 1067 | GIR_Done, |
| 1068 | // Label 158: @2096 |
| 1069 | GIM_Reject, |
| 1070 | // Label 153: @2097 |
| 1071 | GIM_Reject, |
| 1072 | // Label 4: @2098 |
| 1073 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 164*/ GIMT_Encode4(2253), |
| 1074 | /*GILLT_s32*//*Label 159*/ GIMT_Encode4(2129), |
| 1075 | /*GILLT_s64*//*Label 160*/ GIMT_Encode4(2152), |
| 1076 | /*GILLT_s128*//*Label 161*/ GIMT_Encode4(2175), |
| 1077 | /*GILLT_v2s64*//*Label 162*/ GIMT_Encode4(2201), |
| 1078 | /*GILLT_v4s32*//*Label 163*/ GIMT_Encode4(2227), |
| 1079 | // Label 159: @2129 |
| 1080 | GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(2151), // Rule ID 200 // |
| 1081 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1082 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1084 | // (udiv:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (DIVWU:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 1085 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVWU), |
| 1086 | GIR_RootConstrainSelectedInstOperands, |
| 1087 | // GIR_Coverage, 200, |
| 1088 | GIR_Done, |
| 1089 | // Label 165: @2151 |
| 1090 | GIM_Reject, |
| 1091 | // Label 160: @2152 |
| 1092 | GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(2174), // Rule ID 688 // |
| 1093 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1094 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 1096 | // (udiv:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (DIVDU:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 1097 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::DIVDU), |
| 1098 | GIR_RootConstrainSelectedInstOperands, |
| 1099 | // GIR_Coverage, 688, |
| 1100 | GIR_Done, |
| 1101 | // Label 166: @2174 |
| 1102 | GIM_Reject, |
| 1103 | // Label 161: @2175 |
| 1104 | GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(2200), // Rule ID 1137 // |
| 1105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1106 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 1107 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 1108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1109 | // (udiv:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 1110 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUQ), |
| 1111 | GIR_RootConstrainSelectedInstOperands, |
| 1112 | // GIR_Coverage, 1137, |
| 1113 | GIR_Done, |
| 1114 | // Label 167: @2200 |
| 1115 | GIM_Reject, |
| 1116 | // Label 162: @2201 |
| 1117 | GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(2226), // Rule ID 1124 // |
| 1118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1119 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1120 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1122 | // (udiv:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 1123 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUD), |
| 1124 | GIR_RootConstrainSelectedInstOperands, |
| 1125 | // GIR_Coverage, 1124, |
| 1126 | GIR_Done, |
| 1127 | // Label 168: @2226 |
| 1128 | GIM_Reject, |
| 1129 | // Label 163: @2227 |
| 1130 | GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(2252), // Rule ID 1122 // |
| 1131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1132 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1135 | // (udiv:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1136 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VDIVUW), |
| 1137 | GIR_RootConstrainSelectedInstOperands, |
| 1138 | // GIR_Coverage, 1122, |
| 1139 | GIR_Done, |
| 1140 | // Label 169: @2252 |
| 1141 | GIM_Reject, |
| 1142 | // Label 164: @2253 |
| 1143 | GIM_Reject, |
| 1144 | // Label 5: @2254 |
| 1145 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 175*/ GIMT_Encode4(2415), |
| 1146 | /*GILLT_s32*//*Label 170*/ GIMT_Encode4(2285), |
| 1147 | /*GILLT_s64*//*Label 171*/ GIMT_Encode4(2311), |
| 1148 | /*GILLT_s128*//*Label 172*/ GIMT_Encode4(2337), |
| 1149 | /*GILLT_v2s64*//*Label 173*/ GIMT_Encode4(2363), |
| 1150 | /*GILLT_v4s32*//*Label 174*/ GIMT_Encode4(2389), |
| 1151 | // Label 170: @2285 |
| 1152 | GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(2310), // Rule ID 194 // |
| 1153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 1154 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1155 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1157 | // (srem:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MODSW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 1158 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODSW), |
| 1159 | GIR_RootConstrainSelectedInstOperands, |
| 1160 | // GIR_Coverage, 194, |
| 1161 | GIR_Done, |
| 1162 | // Label 176: @2310 |
| 1163 | GIM_Reject, |
| 1164 | // Label 171: @2311 |
| 1165 | GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(2336), // Rule ID 692 // |
| 1166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 1167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1168 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1169 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 1170 | // (srem:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MODSD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 1171 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODSD), |
| 1172 | GIR_RootConstrainSelectedInstOperands, |
| 1173 | // GIR_Coverage, 692, |
| 1174 | GIR_Done, |
| 1175 | // Label 177: @2336 |
| 1176 | GIM_Reject, |
| 1177 | // Label 172: @2337 |
| 1178 | GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(2362), // Rule ID 1146 // |
| 1179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1180 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 1181 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 1182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1183 | // (srem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VMODSQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 1184 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSQ), |
| 1185 | GIR_RootConstrainSelectedInstOperands, |
| 1186 | // GIR_Coverage, 1146, |
| 1187 | GIR_Done, |
| 1188 | // Label 178: @2362 |
| 1189 | GIM_Reject, |
| 1190 | // Label 173: @2363 |
| 1191 | GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(2388), // Rule ID 1119 // |
| 1192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1193 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1196 | // (srem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMODSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 1197 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSD), |
| 1198 | GIR_RootConstrainSelectedInstOperands, |
| 1199 | // GIR_Coverage, 1119, |
| 1200 | GIR_Done, |
| 1201 | // Label 179: @2388 |
| 1202 | GIM_Reject, |
| 1203 | // Label 174: @2389 |
| 1204 | GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(2414), // Rule ID 1117 // |
| 1205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1206 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1207 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1209 | // (srem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMODSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1210 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODSW), |
| 1211 | GIR_RootConstrainSelectedInstOperands, |
| 1212 | // GIR_Coverage, 1117, |
| 1213 | GIR_Done, |
| 1214 | // Label 180: @2414 |
| 1215 | GIM_Reject, |
| 1216 | // Label 175: @2415 |
| 1217 | GIM_Reject, |
| 1218 | // Label 6: @2416 |
| 1219 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 186*/ GIMT_Encode4(2577), |
| 1220 | /*GILLT_s32*//*Label 181*/ GIMT_Encode4(2447), |
| 1221 | /*GILLT_s64*//*Label 182*/ GIMT_Encode4(2473), |
| 1222 | /*GILLT_s128*//*Label 183*/ GIMT_Encode4(2499), |
| 1223 | /*GILLT_v2s64*//*Label 184*/ GIMT_Encode4(2525), |
| 1224 | /*GILLT_v4s32*//*Label 185*/ GIMT_Encode4(2551), |
| 1225 | // Label 181: @2447 |
| 1226 | GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(2472), // Rule ID 195 // |
| 1227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 1228 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1229 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1230 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1231 | // (urem:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MODUW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 1232 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODUW), |
| 1233 | GIR_RootConstrainSelectedInstOperands, |
| 1234 | // GIR_Coverage, 195, |
| 1235 | GIR_Done, |
| 1236 | // Label 187: @2472 |
| 1237 | GIM_Reject, |
| 1238 | // Label 182: @2473 |
| 1239 | GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(2498), // Rule ID 693 // |
| 1240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 1241 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1242 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 1244 | // (urem:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MODUD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 1245 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MODUD), |
| 1246 | GIR_RootConstrainSelectedInstOperands, |
| 1247 | // GIR_Coverage, 693, |
| 1248 | GIR_Done, |
| 1249 | // Label 188: @2498 |
| 1250 | GIM_Reject, |
| 1251 | // Label 183: @2499 |
| 1252 | GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(2524), // Rule ID 1147 // |
| 1253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 1255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 1256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1257 | // (urem:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VMODUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 1258 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUQ), |
| 1259 | GIR_RootConstrainSelectedInstOperands, |
| 1260 | // GIR_Coverage, 1147, |
| 1261 | GIR_Done, |
| 1262 | // Label 189: @2524 |
| 1263 | GIM_Reject, |
| 1264 | // Label 184: @2525 |
| 1265 | GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(2550), // Rule ID 1120 // |
| 1266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1267 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1268 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1269 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1270 | // (urem:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMODUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 1271 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUD), |
| 1272 | GIR_RootConstrainSelectedInstOperands, |
| 1273 | // GIR_Coverage, 1120, |
| 1274 | GIR_Done, |
| 1275 | // Label 190: @2550 |
| 1276 | GIM_Reject, |
| 1277 | // Label 185: @2551 |
| 1278 | GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(2576), // Rule ID 1118 // |
| 1279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 1280 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1281 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1283 | // (urem:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMODUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1284 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMODUW), |
| 1285 | GIR_RootConstrainSelectedInstOperands, |
| 1286 | // GIR_Coverage, 1118, |
| 1287 | GIR_Done, |
| 1288 | // Label 191: @2576 |
| 1289 | GIM_Reject, |
| 1290 | // Label 186: @2577 |
| 1291 | GIM_Reject, |
| 1292 | // Label 7: @2578 |
| 1293 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 196*/ GIMT_Encode4(3211), |
| 1294 | /*GILLT_s1*//*Label 192*/ GIMT_Encode4(2613), |
| 1295 | /*GILLT_s32*//*Label 193*/ GIMT_Encode4(2722), |
| 1296 | /*GILLT_s64*//*Label 194*/ GIMT_Encode4(2831), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1297 | /*GILLT_v4s32*//*Label 195*/ GIMT_Encode4(2940), |
| 1298 | // Label 192: @2613 |
| 1299 | GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(2721), |
| 1300 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 1301 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 1302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 1303 | GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(2668), // Rule ID 4864 // |
| 1304 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1305 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1306 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1307 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1308 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1309 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1310 | // (and:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), |
| 1312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1313 | GIR_RootToRootCopy, /*OpIdx*/2, // CRA |
| 1314 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB |
| 1315 | GIR_RootConstrainSelectedInstOperands, |
| 1316 | // GIR_Coverage, 4864, |
| 1317 | GIR_EraseRootFromParent_Done, |
| 1318 | // Label 198: @2668 |
| 1319 | GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(2708), // Rule ID 179 // |
| 1320 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1321 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1322 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1323 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1324 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1325 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1326 | // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRANDC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), |
| 1328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1329 | GIR_RootToRootCopy, /*OpIdx*/1, // CRA |
| 1330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB |
| 1331 | GIR_RootConstrainSelectedInstOperands, |
| 1332 | // GIR_Coverage, 179, |
| 1333 | GIR_EraseRootFromParent_Done, |
| 1334 | // Label 199: @2708 |
| 1335 | GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(2720), // Rule ID 172 // |
| 1336 | // (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1337 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRAND), |
| 1338 | GIR_RootConstrainSelectedInstOperands, |
| 1339 | // GIR_Coverage, 172, |
| 1340 | GIR_Done, |
| 1341 | // Label 200: @2720 |
| 1342 | GIM_Reject, |
| 1343 | // Label 197: @2721 |
| 1344 | GIM_Reject, |
| 1345 | // Label 193: @2722 |
| 1346 | GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(2830), |
| 1347 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1348 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1350 | GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(2777), // Rule ID 4858 // |
| 1351 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1352 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1353 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1354 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1355 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1356 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1357 | // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] }), i32:{ *:[i32] }:$RST) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC), |
| 1359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1360 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 1361 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1362 | GIR_RootConstrainSelectedInstOperands, |
| 1363 | // GIR_Coverage, 4858, |
| 1364 | GIR_EraseRootFromParent_Done, |
| 1365 | // Label 202: @2777 |
| 1366 | GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(2817), // Rule ID 120 // |
| 1367 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1368 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1369 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1370 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1371 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1372 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1373 | // (and:{ *:[i32] } i32:{ *:[i32] }:$RST, (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] })) => (ANDC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC), |
| 1375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1376 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 1377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1378 | GIR_RootConstrainSelectedInstOperands, |
| 1379 | // GIR_Coverage, 120, |
| 1380 | GIR_EraseRootFromParent_Done, |
| 1381 | // Label 203: @2817 |
| 1382 | GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(2829), // Rule ID 119 // |
| 1383 | // (and:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (AND:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1384 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 1385 | GIR_RootConstrainSelectedInstOperands, |
| 1386 | // GIR_Coverage, 119, |
| 1387 | GIR_Done, |
| 1388 | // Label 204: @2829 |
| 1389 | GIM_Reject, |
| 1390 | // Label 201: @2830 |
| 1391 | GIM_Reject, |
| 1392 | // Label 194: @2831 |
| 1393 | GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(2939), |
| 1394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 1397 | GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(2886), // Rule ID 4871 // |
| 1398 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1399 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1400 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1401 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1402 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1403 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1404 | // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] }), i64:{ *:[i64] }:$RST) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 1405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC8), |
| 1406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1407 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 1408 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1409 | GIR_RootConstrainSelectedInstOperands, |
| 1410 | // GIR_Coverage, 4871, |
| 1411 | GIR_EraseRootFromParent_Done, |
| 1412 | // Label 206: @2886 |
| 1413 | GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(2926), // Rule ID 640 // |
| 1414 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1415 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1416 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1417 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1418 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1419 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1420 | // (and:{ *:[i64] } i64:{ *:[i64] }:$RST, (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] })) => (ANDC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 1421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDC8), |
| 1422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1423 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 1424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1425 | GIR_RootConstrainSelectedInstOperands, |
| 1426 | // GIR_Coverage, 640, |
| 1427 | GIR_EraseRootFromParent_Done, |
| 1428 | // Label 207: @2926 |
| 1429 | GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(2938), // Rule ID 639 // |
| 1430 | // (and:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (AND8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 1431 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 1432 | GIR_RootConstrainSelectedInstOperands, |
| 1433 | // GIR_Coverage, 639, |
| 1434 | GIR_Done, |
| 1435 | // Label 208: @2938 |
| 1436 | GIM_Reject, |
| 1437 | // Label 205: @2939 |
| 1438 | GIM_Reject, |
| 1439 | // Label 195: @2940 |
| 1440 | GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(3210), |
| 1441 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1442 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1443 | GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(3006), // Rule ID 4879 // |
| 1444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 1445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 1446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1449 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1450 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1451 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1452 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1453 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1454 | // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 1455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLANDC), |
| 1456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 1457 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 1458 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 1459 | GIR_RootConstrainSelectedInstOperands, |
| 1460 | // GIR_Coverage, 4879, |
| 1461 | GIR_EraseRootFromParent_Done, |
| 1462 | // Label 210: @3006 |
| 1463 | GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(3061), // Rule ID 923 // |
| 1464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 1465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 1466 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1467 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1468 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1469 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1470 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1471 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1472 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1473 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1474 | // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 1475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLANDC), |
| 1476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 1477 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 1478 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 1479 | GIR_RootConstrainSelectedInstOperands, |
| 1480 | // GIR_Coverage, 923, |
| 1481 | GIR_EraseRootFromParent_Done, |
| 1482 | // Label 211: @3061 |
| 1483 | GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(3080), // Rule ID 922 // |
| 1484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 1485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 1486 | // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 1487 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLAND), |
| 1488 | GIR_RootConstrainSelectedInstOperands, |
| 1489 | // GIR_Coverage, 922, |
| 1490 | GIR_Done, |
| 1491 | // Label 212: @3080 |
| 1492 | GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(3135), // Rule ID 4867 // |
| 1493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 1494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1496 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1497 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1498 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1499 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1500 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1501 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1502 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1503 | // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VA) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC), |
| 1505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 1506 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 1507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB |
| 1508 | GIR_RootConstrainSelectedInstOperands, |
| 1509 | // GIR_Coverage, 4867, |
| 1510 | GIR_EraseRootFromParent_Done, |
| 1511 | // Label 213: @3135 |
| 1512 | GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(3190), // Rule ID 309 // |
| 1513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 1514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1516 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1517 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1518 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1519 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1520 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1521 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1522 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1523 | // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] })) => (VANDC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VANDC), |
| 1525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 1526 | GIR_RootToRootCopy, /*OpIdx*/1, // VA |
| 1527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB |
| 1528 | GIR_RootConstrainSelectedInstOperands, |
| 1529 | // GIR_Coverage, 309, |
| 1530 | GIR_EraseRootFromParent_Done, |
| 1531 | // Label 214: @3190 |
| 1532 | GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(3209), // Rule ID 308 // |
| 1533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 1534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1535 | // (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1536 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VAND), |
| 1537 | GIR_RootConstrainSelectedInstOperands, |
| 1538 | // GIR_Coverage, 308, |
| 1539 | GIR_Done, |
| 1540 | // Label 215: @3209 |
| 1541 | GIM_Reject, |
| 1542 | // Label 209: @3210 |
| 1543 | GIM_Reject, |
| 1544 | // Label 196: @3211 |
| 1545 | GIM_Reject, |
| 1546 | // Label 8: @3212 |
| 1547 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 220*/ GIMT_Encode4(3845), |
| 1548 | /*GILLT_s1*//*Label 216*/ GIMT_Encode4(3247), |
| 1549 | /*GILLT_s32*//*Label 217*/ GIMT_Encode4(3356), |
| 1550 | /*GILLT_s64*//*Label 218*/ GIMT_Encode4(3465), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1551 | /*GILLT_v4s32*//*Label 219*/ GIMT_Encode4(3574), |
| 1552 | // Label 216: @3247 |
| 1553 | GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(3355), |
| 1554 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 1555 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 1556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 1557 | GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(3302), // Rule ID 4865 // |
| 1558 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1559 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1560 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1561 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1562 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1563 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1564 | // (or:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRA) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), |
| 1566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1567 | GIR_RootToRootCopy, /*OpIdx*/2, // CRA |
| 1568 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB |
| 1569 | GIR_RootConstrainSelectedInstOperands, |
| 1570 | // GIR_Coverage, 4865, |
| 1571 | GIR_EraseRootFromParent_Done, |
| 1572 | // Label 222: @3302 |
| 1573 | GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(3342), // Rule ID 180 // |
| 1574 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1575 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1576 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1577 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1578 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1579 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1580 | // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, -1:{ *:[i1] })) => (CRORC:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), |
| 1582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1583 | GIR_RootToRootCopy, /*OpIdx*/1, // CRA |
| 1584 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRB |
| 1585 | GIR_RootConstrainSelectedInstOperands, |
| 1586 | // GIR_Coverage, 180, |
| 1587 | GIR_EraseRootFromParent_Done, |
| 1588 | // Label 223: @3342 |
| 1589 | GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(3354), // Rule ID 174 // |
| 1590 | // (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CROR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1591 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CROR), |
| 1592 | GIR_RootConstrainSelectedInstOperands, |
| 1593 | // GIR_Coverage, 174, |
| 1594 | GIR_Done, |
| 1595 | // Label 224: @3354 |
| 1596 | GIM_Reject, |
| 1597 | // Label 221: @3355 |
| 1598 | GIM_Reject, |
| 1599 | // Label 217: @3356 |
| 1600 | GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(3464), |
| 1601 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1602 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1604 | GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(3411), // Rule ID 4859 // |
| 1605 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1606 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1607 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1608 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1609 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1610 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1611 | // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] }), i32:{ *:[i32] }:$RST) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC), |
| 1613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1614 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 1615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1616 | GIR_RootConstrainSelectedInstOperands, |
| 1617 | // GIR_Coverage, 4859, |
| 1618 | GIR_EraseRootFromParent_Done, |
| 1619 | // Label 226: @3411 |
| 1620 | GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(3451), // Rule ID 123 // |
| 1621 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1622 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1623 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1624 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1625 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1626 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1627 | // (or:{ *:[i32] } i32:{ *:[i32] }:$RST, (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, -1:{ *:[i32] })) => (ORC:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC), |
| 1629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1630 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 1631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1632 | GIR_RootConstrainSelectedInstOperands, |
| 1633 | // GIR_Coverage, 123, |
| 1634 | GIR_EraseRootFromParent_Done, |
| 1635 | // Label 227: @3451 |
| 1636 | GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(3463), // Rule ID 121 // |
| 1637 | // (or:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (OR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1638 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 1639 | GIR_RootConstrainSelectedInstOperands, |
| 1640 | // GIR_Coverage, 121, |
| 1641 | GIR_Done, |
| 1642 | // Label 228: @3463 |
| 1643 | GIM_Reject, |
| 1644 | // Label 225: @3464 |
| 1645 | GIM_Reject, |
| 1646 | // Label 218: @3465 |
| 1647 | GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(3573), |
| 1648 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 1649 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 1650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 1651 | GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(3520), // Rule ID 4872 // |
| 1652 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1653 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1654 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1655 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1656 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1657 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1658 | // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] }), i64:{ *:[i64] }:$RST) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 1659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC8), |
| 1660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1661 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 1662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1663 | GIR_RootConstrainSelectedInstOperands, |
| 1664 | // GIR_Coverage, 4872, |
| 1665 | GIR_EraseRootFromParent_Done, |
| 1666 | // Label 230: @3520 |
| 1667 | GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(3560), // Rule ID 643 // |
| 1668 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1669 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1670 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 1671 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 1672 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1673 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1674 | // (or:{ *:[i64] } i64:{ *:[i64] }:$RST, (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, -1:{ *:[i64] })) => (ORC8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 1675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ORC8), |
| 1676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1677 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 1678 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 1679 | GIR_RootConstrainSelectedInstOperands, |
| 1680 | // GIR_Coverage, 643, |
| 1681 | GIR_EraseRootFromParent_Done, |
| 1682 | // Label 231: @3560 |
| 1683 | GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(3572), // Rule ID 641 // |
| 1684 | // (or:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (OR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 1685 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 1686 | GIR_RootConstrainSelectedInstOperands, |
| 1687 | // GIR_Coverage, 641, |
| 1688 | GIR_Done, |
| 1689 | // Label 232: @3572 |
| 1690 | GIM_Reject, |
| 1691 | // Label 229: @3573 |
| 1692 | GIM_Reject, |
| 1693 | // Label 219: @3574 |
| 1694 | GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(3844), |
| 1695 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1696 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1697 | GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(3640), // Rule ID 4882 // |
| 1698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 1699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 1700 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1701 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1702 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1703 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1704 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1705 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1706 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1707 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1708 | // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XA) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 1709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLORC), |
| 1710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 1711 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 1712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 1713 | GIR_RootConstrainSelectedInstOperands, |
| 1714 | // GIR_Coverage, 4882, |
| 1715 | GIR_EraseRootFromParent_Done, |
| 1716 | // Label 234: @3640 |
| 1717 | GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(3695), // Rule ID 936 // |
| 1718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 1719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 1720 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1721 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1722 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1723 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1724 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1725 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1726 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1727 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1728 | // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, immAllOnesV:{ *:[v4i32] })) => (XXLORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 1729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLORC), |
| 1730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 1731 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 1732 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 1733 | GIR_RootConstrainSelectedInstOperands, |
| 1734 | // GIR_Coverage, 936, |
| 1735 | GIR_EraseRootFromParent_Done, |
| 1736 | // Label 235: @3695 |
| 1737 | GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(3714), // Rule ID 925 // |
| 1738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 1739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 1740 | // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 1741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLOR), |
| 1742 | GIR_RootConstrainSelectedInstOperands, |
| 1743 | // GIR_Coverage, 925, |
| 1744 | GIR_Done, |
| 1745 | // Label 236: @3714 |
| 1746 | GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(3769), // Rule ID 4870 // |
| 1747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 1748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1749 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1750 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1751 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1752 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1753 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1754 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1755 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1756 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1757 | // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VA) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VORC), |
| 1759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 1760 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 1761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB |
| 1762 | GIR_RootConstrainSelectedInstOperands, |
| 1763 | // GIR_Coverage, 4870, |
| 1764 | GIR_EraseRootFromParent_Done, |
| 1765 | // Label 237: @3769 |
| 1766 | GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(3824), // Rule ID 486 // |
| 1767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 1768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1769 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1770 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1771 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1772 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1773 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 1774 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 1775 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 1776 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1777 | // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, immAllOnesV:{ *:[v4i32] })) => (VORC:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VORC), |
| 1779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 1780 | GIR_RootToRootCopy, /*OpIdx*/1, // VA |
| 1781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VB |
| 1782 | GIR_RootConstrainSelectedInstOperands, |
| 1783 | // GIR_Coverage, 486, |
| 1784 | GIR_EraseRootFromParent_Done, |
| 1785 | // Label 238: @3824 |
| 1786 | GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(3843), // Rule ID 383 // |
| 1787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 1788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 1789 | // (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 1790 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VOR), |
| 1791 | GIR_RootConstrainSelectedInstOperands, |
| 1792 | // GIR_Coverage, 383, |
| 1793 | GIR_Done, |
| 1794 | // Label 239: @3843 |
| 1795 | GIM_Reject, |
| 1796 | // Label 233: @3844 |
| 1797 | GIM_Reject, |
| 1798 | // Label 220: @3845 |
| 1799 | GIM_Reject, |
| 1800 | // Label 9: @3846 |
| 1801 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(6), /*)*//*default:*//*Label 244*/ GIMT_Encode4(5349), |
| 1802 | /*GILLT_s1*//*Label 240*/ GIMT_Encode4(3881), |
| 1803 | /*GILLT_s32*//*Label 241*/ GIMT_Encode4(4152), |
| 1804 | /*GILLT_s64*//*Label 242*/ GIMT_Encode4(4407), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1805 | /*GILLT_v4s32*//*Label 243*/ GIMT_Encode4(4662), |
| 1806 | // Label 240: @3881 |
| 1807 | GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(4151), |
| 1808 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 1809 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 1810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 1811 | GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(3938), // Rule ID 173 // |
| 1812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1813 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1815 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1816 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1817 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1818 | // (xor:{ *:[i1] } (and:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNAND:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNAND), |
| 1820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA |
| 1822 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB |
| 1823 | GIR_RootConstrainSelectedInstOperands, |
| 1824 | // GIR_Coverage, 173, |
| 1825 | GIR_EraseRootFromParent_Done, |
| 1826 | // Label 246: @3938 |
| 1827 | GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(3980), // Rule ID 176 // |
| 1828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 1830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1831 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1832 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1833 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1834 | // (xor:{ *:[i1] } (or:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CRNOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOR), |
| 1836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA |
| 1838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB |
| 1839 | GIR_RootConstrainSelectedInstOperands, |
| 1840 | // GIR_Coverage, 176, |
| 1841 | GIR_EraseRootFromParent_Done, |
| 1842 | // Label 247: @3980 |
| 1843 | GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(4020), // Rule ID 4862 // |
| 1844 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1845 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1846 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1847 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1848 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1849 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1850 | // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }), i1:{ *:[i1] }:$CRB) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), |
| 1852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1853 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA |
| 1854 | GIR_RootToRootCopy, /*OpIdx*/2, // CRB |
| 1855 | GIR_RootConstrainSelectedInstOperands, |
| 1856 | // GIR_Coverage, 4862, |
| 1857 | GIR_EraseRootFromParent_Done, |
| 1858 | // Label 248: @4020 |
| 1859 | GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(4062), // Rule ID 177 // |
| 1860 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1861 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1862 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1863 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1864 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1865 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1866 | // (xor:{ *:[i1] } (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB), -1:{ *:[i1] }) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), |
| 1868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1869 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA |
| 1870 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // CRB |
| 1871 | GIR_RootConstrainSelectedInstOperands, |
| 1872 | // GIR_Coverage, 177, |
| 1873 | GIR_EraseRootFromParent_Done, |
| 1874 | // Label 249: @4062 |
| 1875 | GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(4102), // Rule ID 4863 // |
| 1876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1878 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 1879 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 1880 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1881 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1882 | // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRB, (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] })) => (CREQV:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), |
| 1884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // CRA |
| 1886 | GIR_RootToRootCopy, /*OpIdx*/1, // CRB |
| 1887 | GIR_RootConstrainSelectedInstOperands, |
| 1888 | // GIR_Coverage, 4863, |
| 1889 | GIR_EraseRootFromParent_Done, |
| 1890 | // Label 250: @4102 |
| 1891 | GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(4120), // Rule ID 178 // |
| 1892 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1893 | // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } i1:{ *:[i1] }:$CRA) |
| 1894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 1895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1896 | GIR_RootToRootCopy, /*OpIdx*/1, // CRA |
| 1897 | GIR_RootConstrainSelectedInstOperands, |
| 1898 | // GIR_Coverage, 178, |
| 1899 | GIR_EraseRootFromParent_Done, |
| 1900 | // Label 251: @4120 |
| 1901 | GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(4138), // Rule ID 2887 // |
| 1902 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1903 | // (xor:{ *:[i1] } i1:{ *:[i1] }:$in, -1:{ *:[i1] }) => (CRNOT:{ *:[i1] } ?:{ *:[i1] }:$in) |
| 1904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 1905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 1906 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 1907 | GIR_RootConstrainSelectedInstOperands, |
| 1908 | // GIR_Coverage, 2887, |
| 1909 | GIR_EraseRootFromParent_Done, |
| 1910 | // Label 252: @4138 |
| 1911 | GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(4150), // Rule ID 175 // |
| 1912 | // (xor:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) => (CRXOR:{ *:[i1] } i1:{ *:[i1] }:$CRA, i1:{ *:[i1] }:$CRB) |
| 1913 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CRXOR), |
| 1914 | GIR_RootConstrainSelectedInstOperands, |
| 1915 | // GIR_Coverage, 175, |
| 1916 | GIR_Done, |
| 1917 | // Label 253: @4150 |
| 1918 | GIM_Reject, |
| 1919 | // Label 245: @4151 |
| 1920 | GIM_Reject, |
| 1921 | // Label 241: @4152 |
| 1922 | GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(4406), |
| 1923 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 1926 | GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4209), // Rule ID 118 // |
| 1927 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1928 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1929 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1930 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1931 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1932 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1933 | // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (NAND:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NAND), |
| 1935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 1937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 1938 | GIR_RootConstrainSelectedInstOperands, |
| 1939 | // GIR_Coverage, 118, |
| 1940 | GIR_EraseRootFromParent_Done, |
| 1941 | // Label 255: @4209 |
| 1942 | GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(4251), // Rule ID 122 // |
| 1943 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1944 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 1945 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1946 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1947 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1948 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1949 | // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (NOR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR), |
| 1951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 1953 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 1954 | GIR_RootConstrainSelectedInstOperands, |
| 1955 | // GIR_Coverage, 122, |
| 1956 | GIR_EraseRootFromParent_Done, |
| 1957 | // Label 256: @4251 |
| 1958 | GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(4291), // Rule ID 4860 // |
| 1959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1960 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1962 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1963 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1964 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1965 | // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, -1:{ *:[i32] }), i32:{ *:[i32] }:$RB) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV), |
| 1967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 1969 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 1970 | GIR_RootConstrainSelectedInstOperands, |
| 1971 | // GIR_Coverage, 4860, |
| 1972 | GIR_EraseRootFromParent_Done, |
| 1973 | // Label 257: @4291 |
| 1974 | GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(4333), // Rule ID 124 // |
| 1975 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1976 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1977 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1978 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1979 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 1980 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1981 | // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB), -1:{ *:[i32] }) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV), |
| 1983 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 1984 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 1985 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 1986 | GIR_RootConstrainSelectedInstOperands, |
| 1987 | // GIR_Coverage, 124, |
| 1988 | GIR_EraseRootFromParent_Done, |
| 1989 | // Label 258: @4333 |
| 1990 | GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(4373), // Rule ID 4861 // |
| 1991 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1992 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 1993 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1994 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1995 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 1996 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1997 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$RB, (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, -1:{ *:[i32] })) => (EQV:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 1998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV), |
| 1999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 2001 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 2002 | GIR_RootConstrainSelectedInstOperands, |
| 2003 | // GIR_Coverage, 4861, |
| 2004 | GIR_EraseRootFromParent_Done, |
| 2005 | // Label 259: @4373 |
| 2006 | GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(4393), // Rule ID 1196 // |
| 2007 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2008 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } ?:{ *:[i32] }:$in, ?:{ *:[i32] }:$in) |
| 2009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR), |
| 2010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2011 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 2012 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 2013 | GIR_RootConstrainSelectedInstOperands, |
| 2014 | // GIR_Coverage, 1196, |
| 2015 | GIR_EraseRootFromParent_Done, |
| 2016 | // Label 260: @4393 |
| 2017 | GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(4405), // Rule ID 125 // |
| 2018 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) => (XOR:{ *:[i32] } i32:{ *:[i32] }:$RST, i32:{ *:[i32] }:$RB) |
| 2019 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XOR), |
| 2020 | GIR_RootConstrainSelectedInstOperands, |
| 2021 | // GIR_Coverage, 125, |
| 2022 | GIR_Done, |
| 2023 | // Label 261: @4405 |
| 2024 | GIM_Reject, |
| 2025 | // Label 254: @4406 |
| 2026 | GIM_Reject, |
| 2027 | // Label 242: @4407 |
| 2028 | GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(4661), |
| 2029 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2030 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 2032 | GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(4464), // Rule ID 638 // |
| 2033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2037 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2038 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2039 | // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (NAND8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 2040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NAND8), |
| 2041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2042 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 2043 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 2044 | GIR_RootConstrainSelectedInstOperands, |
| 2045 | // GIR_Coverage, 638, |
| 2046 | GIR_EraseRootFromParent_Done, |
| 2047 | // Label 263: @4464 |
| 2048 | GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(4506), // Rule ID 642 // |
| 2049 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2050 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 2051 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2052 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2053 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2054 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2055 | // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (NOR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 2056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR8), |
| 2057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2058 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 2059 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 2060 | GIR_RootConstrainSelectedInstOperands, |
| 2061 | // GIR_Coverage, 642, |
| 2062 | GIR_EraseRootFromParent_Done, |
| 2063 | // Label 264: @4506 |
| 2064 | GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(4546), // Rule ID 4873 // |
| 2065 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2066 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2067 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2068 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2069 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 2070 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2071 | // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, -1:{ *:[i64] }), i64:{ *:[i64] }:$RB) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 2072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8), |
| 2073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2074 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 2075 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 2076 | GIR_RootConstrainSelectedInstOperands, |
| 2077 | // GIR_Coverage, 4873, |
| 2078 | GIR_EraseRootFromParent_Done, |
| 2079 | // Label 265: @4546 |
| 2080 | GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(4588), // Rule ID 644 // |
| 2081 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2082 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2083 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2084 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2086 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2087 | // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB), -1:{ *:[i64] }) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 2088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8), |
| 2089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 2091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 2092 | GIR_RootConstrainSelectedInstOperands, |
| 2093 | // GIR_Coverage, 644, |
| 2094 | GIR_EraseRootFromParent_Done, |
| 2095 | // Label 266: @4588 |
| 2096 | GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(4628), // Rule ID 4874 // |
| 2097 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2098 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2099 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2100 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2101 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 2102 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2103 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$RB, (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, -1:{ *:[i64] })) => (EQV8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 2104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EQV8), |
| 2105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2106 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RST |
| 2107 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 2108 | GIR_RootConstrainSelectedInstOperands, |
| 2109 | // GIR_Coverage, 4874, |
| 2110 | GIR_EraseRootFromParent_Done, |
| 2111 | // Label 267: @4628 |
| 2112 | GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(4648), // Rule ID 1508 // |
| 2113 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2114 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$in, -1:{ *:[i64] }) => (NOR8:{ *:[i64] } ?:{ *:[i64] }:$in, ?:{ *:[i64] }:$in) |
| 2115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOR8), |
| 2116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2117 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 2118 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 2119 | GIR_RootConstrainSelectedInstOperands, |
| 2120 | // GIR_Coverage, 1508, |
| 2121 | GIR_EraseRootFromParent_Done, |
| 2122 | // Label 268: @4648 |
| 2123 | GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(4660), // Rule ID 645 // |
| 2124 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (XOR8:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 2125 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XOR8), |
| 2126 | GIR_RootConstrainSelectedInstOperands, |
| 2127 | // GIR_Coverage, 645, |
| 2128 | GIR_Done, |
| 2129 | // Label 269: @4660 |
| 2130 | GIM_Reject, |
| 2131 | // Label 262: @4661 |
| 2132 | GIM_Reject, |
| 2133 | // Label 243: @4662 |
| 2134 | GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5348), |
| 2135 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2137 | GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(4730), // Rule ID 934 // |
| 2138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 2139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2141 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2143 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2144 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2145 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2146 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2147 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2148 | // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 2149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNAND), |
| 2150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 2152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 2153 | GIR_RootConstrainSelectedInstOperands, |
| 2154 | // GIR_Coverage, 934, |
| 2155 | GIR_EraseRootFromParent_Done, |
| 2156 | // Label 271: @4730 |
| 2157 | GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(4787), // Rule ID 924 // |
| 2158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2161 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 2162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2163 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2164 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2165 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2166 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2167 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2168 | // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 2169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNOR), |
| 2170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 2172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 2173 | GIR_RootConstrainSelectedInstOperands, |
| 2174 | // GIR_Coverage, 924, |
| 2175 | GIR_EraseRootFromParent_Done, |
| 2176 | // Label 272: @4787 |
| 2177 | GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(4842), // Rule ID 4880 // |
| 2178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 2179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2182 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2183 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2184 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2185 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2186 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2187 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2188 | // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$XB) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 2189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), |
| 2190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 2192 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 2193 | GIR_RootConstrainSelectedInstOperands, |
| 2194 | // GIR_Coverage, 4880, |
| 2195 | GIR_EraseRootFromParent_Done, |
| 2196 | // Label 273: @4842 |
| 2197 | GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(4899), // Rule ID 933 // |
| 2198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 2199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2200 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2201 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2202 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2203 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2204 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2205 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2206 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2207 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2208 | // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB), immAllOnesV:{ *:[v4i32] }) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 2209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), |
| 2210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 2212 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 2213 | GIR_RootConstrainSelectedInstOperands, |
| 2214 | // GIR_Coverage, 933, |
| 2215 | GIR_EraseRootFromParent_Done, |
| 2216 | // Label 274: @4899 |
| 2217 | GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(4954), // Rule ID 4881 // |
| 2218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 2219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2220 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2221 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2222 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2223 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2224 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2225 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2226 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2227 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2228 | // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, immAllOnesV:{ *:[v4i32] })) => (XXLEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 2229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), |
| 2230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2231 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 2232 | GIR_RootToRootCopy, /*OpIdx*/1, // XB |
| 2233 | GIR_RootConstrainSelectedInstOperands, |
| 2234 | // GIR_Coverage, 4881, |
| 2235 | GIR_EraseRootFromParent_Done, |
| 2236 | // Label 275: @4954 |
| 2237 | GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(4991), // Rule ID 1569 // |
| 2238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2240 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2241 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2242 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 2243 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2244 | // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$A, immAllOnesV:{ *:[v4i32] }) => (XXLNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$A) |
| 2245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLNOR), |
| 2246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2247 | GIR_RootToRootCopy, /*OpIdx*/1, // A |
| 2248 | GIR_RootToRootCopy, /*OpIdx*/1, // A |
| 2249 | GIR_RootConstrainSelectedInstOperands, |
| 2250 | // GIR_Coverage, 1569, |
| 2251 | GIR_EraseRootFromParent_Done, |
| 2252 | // Label 276: @4991 |
| 2253 | GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5010), // Rule ID 926 // |
| 2254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2256 | // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XXLXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 2257 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXLXOR), |
| 2258 | GIR_RootConstrainSelectedInstOperands, |
| 2259 | // GIR_Coverage, 926, |
| 2260 | GIR_Done, |
| 2261 | // Label 277: @5010 |
| 2262 | GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5067), // Rule ID 485 // |
| 2263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 2264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2265 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2266 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 2267 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2268 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2269 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2270 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2271 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2272 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2273 | // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VNAND:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 2274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNAND), |
| 2275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA |
| 2277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB |
| 2278 | GIR_RootConstrainSelectedInstOperands, |
| 2279 | // GIR_Coverage, 485, |
| 2280 | GIR_EraseRootFromParent_Done, |
| 2281 | // Label 278: @5067 |
| 2282 | GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5124), // Rule ID 382 // |
| 2283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 2287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2288 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2289 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2290 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2291 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2292 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2293 | // (xor:{ *:[v4i32] } (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 2294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR), |
| 2295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2296 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA |
| 2297 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB |
| 2298 | GIR_RootConstrainSelectedInstOperands, |
| 2299 | // GIR_Coverage, 382, |
| 2300 | GIR_EraseRootFromParent_Done, |
| 2301 | // Label 279: @5124 |
| 2302 | GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5179), // Rule ID 4868 // |
| 2303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 2304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2305 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2306 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2307 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2308 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2309 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2310 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2311 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2312 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2313 | // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, immAllOnesV:{ *:[v4i32] }), v4i32:{ *:[v4i32] }:$VB) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 2314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV), |
| 2315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA |
| 2317 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 2318 | GIR_RootConstrainSelectedInstOperands, |
| 2319 | // GIR_Coverage, 4868, |
| 2320 | GIR_EraseRootFromParent_Done, |
| 2321 | // Label 280: @5179 |
| 2322 | GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5236), // Rule ID 484 // |
| 2323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 2324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2326 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2327 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2328 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2329 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2330 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2331 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2332 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2333 | // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB), immAllOnesV:{ *:[v4i32] }) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 2334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV), |
| 2335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA |
| 2337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // VB |
| 2338 | GIR_RootConstrainSelectedInstOperands, |
| 2339 | // GIR_Coverage, 484, |
| 2340 | GIR_EraseRootFromParent_Done, |
| 2341 | // Label 281: @5236 |
| 2342 | GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(5291), // Rule ID 4869 // |
| 2343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 2344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2345 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2346 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 2347 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2348 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2349 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2350 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2351 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 2352 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2353 | // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB, (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, immAllOnesV:{ *:[v4i32] })) => (VEQV:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 2354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEQV), |
| 2355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2356 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // VA |
| 2357 | GIR_RootToRootCopy, /*OpIdx*/1, // VB |
| 2358 | GIR_RootConstrainSelectedInstOperands, |
| 2359 | // GIR_Coverage, 4869, |
| 2360 | GIR_EraseRootFromParent_Done, |
| 2361 | // Label 282: @5291 |
| 2362 | GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(5328), // Rule ID 1365 // |
| 2363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2365 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2366 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2367 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 2368 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2369 | // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, immAllOnesV:{ *:[v4i32] }) => (VNOR:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vA) |
| 2370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNOR), |
| 2371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2372 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 2373 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 2374 | GIR_RootConstrainSelectedInstOperands, |
| 2375 | // GIR_Coverage, 1365, |
| 2376 | GIR_EraseRootFromParent_Done, |
| 2377 | // Label 283: @5328 |
| 2378 | GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(5347), // Rule ID 384 // |
| 2379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2381 | // (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VXOR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 2382 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VXOR), |
| 2383 | GIR_RootConstrainSelectedInstOperands, |
| 2384 | // GIR_Coverage, 384, |
| 2385 | GIR_Done, |
| 2386 | // Label 284: @5347 |
| 2387 | GIM_Reject, |
| 2388 | // Label 270: @5348 |
| 2389 | GIM_Reject, |
| 2390 | // Label 244: @5349 |
| 2391 | GIM_Reject, |
| 2392 | // Label 10: @5350 |
| 2393 | GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(5650), |
| 2394 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 2395 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 2396 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2397 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2399 | GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(5493), // Rule ID 2111 // |
| 2400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector), |
| 2401 | // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$A, i64:{ *:[i64] }:$B) => (XXPERMDI:{ *:[v2i64] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$A), sub_64:{ *:[i32] }), (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$B), sub_64:{ *:[i32] }), 0:{ *:[i32] }) |
| 2402 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2403 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 2404 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 2405 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 2406 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), |
| 2407 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2408 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // B |
| 2409 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 2410 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2411 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2412 | GIR_AddImm8, /*InsnID*/3, /*Imm*/1, |
| 2413 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 2414 | GIR_AddImm8, /*InsnID*/3, /*Imm*/3, |
| 2415 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2416 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2417 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), |
| 2418 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2419 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 2420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 2421 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2422 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2423 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2424 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 2425 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 2426 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2427 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), |
| 2429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2431 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 2432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2433 | GIR_RootConstrainSelectedInstOperands, |
| 2434 | // GIR_Coverage, 2111, |
| 2435 | GIR_EraseRootFromParent_Done, |
| 2436 | // Label 286: @5493 |
| 2437 | GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(5615), // Rule ID 2114 // |
| 2438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector), |
| 2439 | // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$A, i64:{ *:[i64] }:$B) => (XXPERMDI:{ *:[v2i64] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$B), sub_64:{ *:[i32] }), (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] }) |
| 2440 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2441 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 2442 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 2443 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 2444 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), |
| 2445 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2446 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 2447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 2448 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2449 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2450 | GIR_AddImm8, /*InsnID*/3, /*Imm*/1, |
| 2451 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 2452 | GIR_AddImm8, /*InsnID*/3, /*Imm*/3, |
| 2453 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2454 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2455 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), |
| 2456 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2457 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // B |
| 2458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 2459 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2460 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2461 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2462 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 2463 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 2464 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2465 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), |
| 2467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2468 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2469 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 2470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2471 | GIR_RootConstrainSelectedInstOperands, |
| 2472 | // GIR_Coverage, 2114, |
| 2473 | GIR_EraseRootFromParent_Done, |
| 2474 | // Label 287: @5615 |
| 2475 | GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(5630), // Rule ID 2857 // |
| 2476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsISA3_0_IsPPC64), |
| 2477 | // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$rB, i64:{ *:[i64] }:$rA) => (MTVSRDD:{ *:[v2i64] } ?:{ *:[i64] }:$rB, ?:{ *:[i64] }:$rA) |
| 2478 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MTVSRDD), |
| 2479 | GIR_RootConstrainSelectedInstOperands, |
| 2480 | // GIR_Coverage, 2857, |
| 2481 | GIR_Done, |
| 2482 | // Label 288: @5630 |
| 2483 | GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(5649), // Rule ID 2861 // |
| 2484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsISA3_0_IsLittleEndian), |
| 2485 | // (build_vector:{ *:[v2i64] } i64:{ *:[i64] }:$rA, i64:{ *:[i64] }:$rB) => (MTVSRDD:{ *:[v2i64] } ?:{ *:[i64] }:$rB, ?:{ *:[i64] }:$rA) |
| 2486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRDD), |
| 2487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2488 | GIR_RootToRootCopy, /*OpIdx*/2, // rB |
| 2489 | GIR_RootToRootCopy, /*OpIdx*/1, // rA |
| 2490 | GIR_RootConstrainSelectedInstOperands, |
| 2491 | // GIR_Coverage, 2861, |
| 2492 | GIR_EraseRootFromParent_Done, |
| 2493 | // Label 289: @5649 |
| 2494 | GIM_Reject, |
| 2495 | // Label 285: @5650 |
| 2496 | GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(6175), |
| 2497 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 2498 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 2499 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 2500 | GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(5715), // Rule ID 2025 // |
| 2501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 2502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2503 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2504 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2505 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt5NonZero), |
| 2506 | // MIs[1] Operand 1 |
| 2507 | // No operand predicates |
| 2508 | // MIs[0] A |
| 2509 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2510 | // MIs[0] A |
| 2511 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2512 | // MIs[0] A |
| 2513 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2514 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2515 | // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_immSExt5NonZero>>:$A) => (VSPLTISW:{ *:[v4i32] } (imm:{ *:[i32] }):$A) |
| 2516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSPLTISW), |
| 2517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 2518 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A |
| 2519 | GIR_RootConstrainSelectedInstOperands, |
| 2520 | // GIR_Coverage, 2025, |
| 2521 | GIR_EraseRootFromParent_Done, |
| 2522 | // Label 291: @5715 |
| 2523 | GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(5766), // Rule ID 3358 // |
| 2524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), |
| 2525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2526 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2527 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2528 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32immNonAllOneNonZero), |
| 2529 | // MIs[1] Operand 1 |
| 2530 | // No operand predicates |
| 2531 | // MIs[0] A |
| 2532 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2533 | // MIs[0] A |
| 2534 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2535 | // MIs[0] A |
| 2536 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2537 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2538 | // (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A, (imm:{ *:[i32] })<<P:Predicate_i32immNonAllOneNonZero>>:$A) => (XXSPLTIW:{ *:[v4i32] } (imm:{ *:[i32] }):$A) |
| 2539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTIW), |
| 2540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2541 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // A |
| 2542 | GIR_RootConstrainSelectedInstOperands, |
| 2543 | // GIR_Coverage, 3358, |
| 2544 | GIR_EraseRootFromParent_Done, |
| 2545 | // Label 292: @5766 |
| 2546 | GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(5902), // Rule ID 1717 // |
| 2547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2548 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 2549 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 2550 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 2551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2552 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2553 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 2554 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2555 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 2556 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 2557 | // MIs[2] A |
| 2558 | GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 2559 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 2560 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 2561 | // MIs[3] A |
| 2562 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 2563 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/4, // MIs[4] |
| 2564 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 2565 | // MIs[4] A |
| 2566 | GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 2567 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 2568 | // (build_vector:{ *:[v4f32] } (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A), (fpround:{ *:[f32] } f64:{ *:[f64] }:$A)) => (XXSPLTW:{ *:[v4f32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (XSCVDPSP:{ *:[f64] } f64:{ *:[f64] }:$A), sub_64:{ *:[i32] }), 0:{ *:[i32] }) |
| 2569 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2570 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 2571 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSP), |
| 2572 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2573 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // A |
| 2574 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 2575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2577 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2578 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 2579 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 2580 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2581 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), |
| 2583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2586 | GIR_RootConstrainSelectedInstOperands, |
| 2587 | // GIR_Coverage, 1717, |
| 2588 | GIR_EraseRootFromParent_Done, |
| 2589 | // Label 293: @5902 |
| 2590 | GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(5960), // Rule ID 1718 // |
| 2591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2593 | // MIs[0] A |
| 2594 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2595 | // MIs[0] A |
| 2596 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2597 | // MIs[0] A |
| 2598 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2599 | // (build_vector:{ *:[v4f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$A) => (XXSPLTW:{ *:[v4f32] } (XSCVDPSPN:{ *:[v4f32] } ?:{ *:[f32] }:$A), 0:{ *:[i32] }) |
| 2600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSPN), |
| 2602 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2603 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 2604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), |
| 2606 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2607 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2609 | GIR_RootConstrainSelectedInstOperands, |
| 2610 | // GIR_Coverage, 1718, |
| 2611 | GIR_EraseRootFromParent_Done, |
| 2612 | // Label 294: @5960 |
| 2613 | GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(6049), // Rule ID 2113 // |
| 2614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsBigEndian_IsPPC64_NoP9Vector), |
| 2615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2616 | // MIs[0] A |
| 2617 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2618 | // MIs[0] A |
| 2619 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2620 | // MIs[0] A |
| 2621 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2622 | // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (XXSPLTW:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$A), sub_64:{ *:[i32] }), 1:{ *:[i32] }) |
| 2623 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2624 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 2625 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ), |
| 2626 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2627 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 2628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 2629 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2630 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2631 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2632 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 2633 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 2634 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2635 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), |
| 2637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2638 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 2640 | GIR_RootConstrainSelectedInstOperands, |
| 2641 | // GIR_Coverage, 2113, |
| 2642 | GIR_EraseRootFromParent_Done, |
| 2643 | // Label 295: @6049 |
| 2644 | GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(6138), // Rule ID 2116 // |
| 2645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX_IsLittleEndian_NoP9Vector), |
| 2646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2647 | // MIs[0] A |
| 2648 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2649 | // MIs[0] A |
| 2650 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2651 | // MIs[0] A |
| 2652 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2653 | // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (XXSPLTW:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[v4i32] } 1:{ *:[i64] }, (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$A), sub_64:{ *:[i32] }), 1:{ *:[i32] }) |
| 2654 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2655 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 2656 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ), |
| 2657 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2658 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 2659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 2660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), |
| 2661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2662 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 2663 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 2664 | GIR_AddImm8, /*InsnID*/1, /*Imm*/3, |
| 2665 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSPLTW), |
| 2668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2669 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 2671 | GIR_RootConstrainSelectedInstOperands, |
| 2672 | // GIR_Coverage, 2116, |
| 2673 | GIR_EraseRootFromParent_Done, |
| 2674 | // Label 296: @6138 |
| 2675 | GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(6174), // Rule ID 2247 // |
| 2676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 2677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2678 | // MIs[0] A |
| 2679 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2680 | // MIs[0] A |
| 2681 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2682 | // MIs[0] A |
| 2683 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2684 | // (build_vector:{ *:[v4i32] } i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A, i32:{ *:[i32] }:$A) => (MTVSRWS:{ *:[v4i32] } ?:{ *:[i32] }:$A) |
| 2685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRWS), |
| 2686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 2687 | GIR_RootToRootCopy, /*OpIdx*/1, // A |
| 2688 | GIR_RootConstrainSelectedInstOperands, |
| 2689 | // GIR_Coverage, 2247, |
| 2690 | GIR_EraseRootFromParent_Done, |
| 2691 | // Label 297: @6174 |
| 2692 | GIM_Reject, |
| 2693 | // Label 290: @6175 |
| 2694 | GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(6316), // Rule ID 2248 // |
| 2695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 2696 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/17, |
| 2697 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 2698 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 2699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2700 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2701 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2702 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immNonAllOneAnyExt8), |
| 2703 | // MIs[1] Operand 1 |
| 2704 | // No operand predicates |
| 2705 | // MIs[0] A |
| 2706 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2707 | // MIs[0] A |
| 2708 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2709 | // MIs[0] A |
| 2710 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2711 | // MIs[0] A |
| 2712 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2713 | // MIs[0] A |
| 2714 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2715 | // MIs[0] A |
| 2716 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2717 | // MIs[0] A |
| 2718 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2719 | // MIs[0] A |
| 2720 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2721 | // MIs[0] A |
| 2722 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2723 | // MIs[0] A |
| 2724 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2725 | // MIs[0] A |
| 2726 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2727 | // MIs[0] A |
| 2728 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2729 | // MIs[0] A |
| 2730 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2731 | // MIs[0] A |
| 2732 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2733 | // MIs[0] A |
| 2734 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2735 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2736 | // (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A, (imm:{ *:[i32] })<<P:Predicate_immNonAllOneAnyExt8>>:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXSPLTIB:{ *:[v4i32] } (imm:{ *:[i32] }):$A), VSRC:{ *:[i32] }) |
| 2737 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2738 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSPLTIB), |
| 2739 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2740 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // A |
| 2741 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 2744 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2745 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2746 | // GIR_Coverage, 2248, |
| 2747 | GIR_EraseRootFromParent_Done, |
| 2748 | // Label 298: @6316 |
| 2749 | GIM_Reject, |
| 2750 | // Label 11: @6317 |
| 2751 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 306*/ GIMT_Encode4(8593), |
| 2752 | /*GILLT_s32*//*Label 299*/ GIMT_Encode4(6356), |
| 2753 | /*GILLT_s64*//*Label 300*/ GIMT_Encode4(6429), |
| 2754 | /*GILLT_s128*//*Label 301*/ GIMT_Encode4(6477), |
| 2755 | /*GILLT_v2s64*//*Label 302*/ GIMT_Encode4(6881), |
| 2756 | /*GILLT_v4s32*//*Label 303*/ GIMT_Encode4(7443), |
| 2757 | /*GILLT_v8s16*//*Label 304*/ GIMT_Encode4(7994), |
| 2758 | /*GILLT_v16s8*//*Label 305*/ GIMT_Encode4(8322), |
| 2759 | // Label 299: @6356 |
| 2760 | GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(6428), // Rule ID 2011 // |
| 2761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 2762 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 2763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 2764 | // (bitconvert:{ *:[i32] } f32:{ *:[f32] }:$A) => (MFVSRWZ:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f64] } (XSCVDPSPN:{ *:[v4i32] } ?:{ *:[f32] }:$A), sub_64:{ *:[i32] })) |
| 2765 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 2766 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 2767 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSPN), |
| 2768 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2769 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 2770 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 2771 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2772 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2773 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_64), |
| 2774 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 2775 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ), |
| 2777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 2778 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2779 | GIR_RootConstrainSelectedInstOperands, |
| 2780 | // GIR_Coverage, 2011, |
| 2781 | GIR_EraseRootFromParent_Done, |
| 2782 | // Label 307: @6428 |
| 2783 | GIM_Reject, |
| 2784 | // Label 300: @6429 |
| 2785 | GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(6476), |
| 2786 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2787 | GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(6456), // Rule ID 2013 // |
| 2788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 2789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 2790 | // (bitconvert:{ *:[i64] } f64:{ *:[f64] }:$A) => (MFVSRD:{ *:[i64] } ?:{ *:[f64] }:$A) |
| 2791 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 2792 | GIR_RootConstrainSelectedInstOperands, |
| 2793 | // GIR_Coverage, 2013, |
| 2794 | GIR_Done, |
| 2795 | // Label 309: @6456 |
| 2796 | GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(6475), // Rule ID 2014 // |
| 2797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 2798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 2799 | // (bitconvert:{ *:[f64] } i64:{ *:[i64] }:$S) => (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$S) |
| 2800 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), |
| 2801 | GIR_RootConstrainSelectedInstOperands, |
| 2802 | // GIR_Coverage, 2014, |
| 2803 | GIR_Done, |
| 2804 | // Label 310: @6475 |
| 2805 | GIM_Reject, |
| 2806 | // Label 308: @6476 |
| 2807 | GIM_Reject, |
| 2808 | // Label 301: @6477 |
| 2809 | GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(6534), // Rule ID 1917 // |
| 2810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 2811 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2813 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2814 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2815 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 2816 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2817 | // (bitconvert:{ *:[v1i128] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) |
| 2818 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2819 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), |
| 2820 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2821 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 2824 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2825 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2826 | // GIR_Coverage, 1917, |
| 2827 | GIR_EraseRootFromParent_Done, |
| 2828 | // Label 311: @6534 |
| 2829 | GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(6560), // Rule ID 1604 // |
| 2830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2831 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2833 | // (bitconvert:{ *:[v1i128] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v1i128] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) |
| 2834 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2835 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2836 | // GIR_Coverage, 1604, |
| 2837 | GIR_Done, |
| 2838 | // Label 312: @6560 |
| 2839 | GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(6592), // Rule ID 1319 // |
| 2840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2841 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2843 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2844 | // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v1i128] }:$src |
| 2845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2846 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2847 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2848 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2849 | // GIR_Coverage, 1319, |
| 2850 | GIR_EraseRootFromParent_Done, |
| 2851 | // Label 313: @6592 |
| 2852 | GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6624), // Rule ID 1320 // |
| 2853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2854 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2856 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2857 | // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v1i128] }:$src |
| 2858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2859 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2860 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2861 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2862 | // GIR_Coverage, 1320, |
| 2863 | GIR_EraseRootFromParent_Done, |
| 2864 | // Label 314: @6624 |
| 2865 | GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6656), // Rule ID 1321 // |
| 2866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2867 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2870 | // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v1i128] }:$src |
| 2871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2872 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2873 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2874 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2875 | // GIR_Coverage, 1321, |
| 2876 | GIR_EraseRootFromParent_Done, |
| 2877 | // Label 315: @6656 |
| 2878 | GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6688), // Rule ID 1322 // |
| 2879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2880 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2882 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2883 | // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v1i128] }:$src |
| 2884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2885 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2886 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2887 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2888 | // GIR_Coverage, 1322, |
| 2889 | GIR_EraseRootFromParent_Done, |
| 2890 | // Label 316: @6688 |
| 2891 | GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6720), // Rule ID 1323 // |
| 2892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2893 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2895 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2896 | // (bitconvert:{ *:[v1i128] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v1i128] }:$src |
| 2897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2898 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2899 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2900 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2901 | // GIR_Coverage, 1323, |
| 2902 | GIR_EraseRootFromParent_Done, |
| 2903 | // Label 317: @6720 |
| 2904 | GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6752), // Rule ID 1324 // |
| 2905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2906 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2908 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2909 | // (bitconvert:{ *:[f128] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[f128] }:$src |
| 2910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2911 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2912 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2913 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2914 | // GIR_Coverage, 1324, |
| 2915 | GIR_EraseRootFromParent_Done, |
| 2916 | // Label 318: @6752 |
| 2917 | GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6784), // Rule ID 1325 // |
| 2918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2919 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2921 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2922 | // (bitconvert:{ *:[f128] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[f128] }:$src |
| 2923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2924 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2925 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2926 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2927 | // GIR_Coverage, 1325, |
| 2928 | GIR_EraseRootFromParent_Done, |
| 2929 | // Label 319: @6784 |
| 2930 | GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6816), // Rule ID 1326 // |
| 2931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2932 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2934 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2935 | // (bitconvert:{ *:[f128] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[f128] }:$src |
| 2936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2937 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2938 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2939 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2940 | // GIR_Coverage, 1326, |
| 2941 | GIR_EraseRootFromParent_Done, |
| 2942 | // Label 320: @6816 |
| 2943 | GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6848), // Rule ID 1327 // |
| 2944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2945 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2947 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2948 | // (bitconvert:{ *:[f128] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[f128] }:$src |
| 2949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2950 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2951 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2952 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2953 | // GIR_Coverage, 1327, |
| 2954 | GIR_EraseRootFromParent_Done, |
| 2955 | // Label 321: @6848 |
| 2956 | GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(6880), // Rule ID 1328 // |
| 2957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 2958 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 2961 | // (bitconvert:{ *:[f128] } VRRC:{ *:[v2f64] }:$src) => VRRC:{ *:[f128] }:$src |
| 2962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2963 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 2964 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 2965 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 2966 | // GIR_Coverage, 1328, |
| 2967 | GIR_EraseRootFromParent_Done, |
| 2968 | // Label 322: @6880 |
| 2969 | GIM_Reject, |
| 2970 | // Label 302: @6881 |
| 2971 | GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(6938), // Rule ID 1918 // |
| 2972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 2973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2975 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2976 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 2977 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 2978 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2979 | // (bitconvert:{ *:[v2i64] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) |
| 2980 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 2981 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), |
| 2982 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2983 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 2984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 2986 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 2987 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2988 | // GIR_Coverage, 1918, |
| 2989 | GIR_EraseRootFromParent_Done, |
| 2990 | // Label 323: @6938 |
| 2991 | GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(6964), // Rule ID 1585 // |
| 2992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 2993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 2995 | // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v4f32] }:$A, VSRC:{ *:[i32] }) |
| 2996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 2997 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 2998 | // GIR_Coverage, 1585, |
| 2999 | GIR_Done, |
| 3000 | // Label 324: @6964 |
| 3001 | GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(6990), // Rule ID 1586 // |
| 3002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3005 | // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v4i32] }:$A, VSRC:{ *:[i32] }) |
| 3006 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3007 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3008 | // GIR_Coverage, 1586, |
| 3009 | GIR_Done, |
| 3010 | // Label 325: @6990 |
| 3011 | GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(7016), // Rule ID 1587 // |
| 3012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3013 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3015 | // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }) |
| 3016 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3017 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3018 | // GIR_Coverage, 1587, |
| 3019 | GIR_Done, |
| 3020 | // Label 326: @7016 |
| 3021 | GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(7042), // Rule ID 1588 // |
| 3022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3023 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3025 | // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }) |
| 3026 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3027 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3028 | // GIR_Coverage, 1588, |
| 3029 | GIR_Done, |
| 3030 | // Label 327: @7042 |
| 3031 | GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(7068), // Rule ID 1593 // |
| 3032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3033 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3035 | // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v4f32] }:$A, VSRC:{ *:[i32] }) |
| 3036 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3037 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3038 | // GIR_Coverage, 1593, |
| 3039 | GIR_Done, |
| 3040 | // Label 328: @7068 |
| 3041 | GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(7094), // Rule ID 1594 // |
| 3042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3043 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3045 | // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v4i32] }:$A, VSRC:{ *:[i32] }) |
| 3046 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3047 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3048 | // GIR_Coverage, 1594, |
| 3049 | GIR_Done, |
| 3050 | // Label 329: @7094 |
| 3051 | GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(7120), // Rule ID 1595 // |
| 3052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3053 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3054 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3055 | // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }) |
| 3056 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3057 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3058 | // GIR_Coverage, 1595, |
| 3059 | GIR_Done, |
| 3060 | // Label 330: @7120 |
| 3061 | GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(7146), // Rule ID 1596 // |
| 3062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3063 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3065 | // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }) |
| 3066 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3067 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3068 | // GIR_Coverage, 1596, |
| 3069 | GIR_Done, |
| 3070 | // Label 331: @7146 |
| 3071 | GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(7172), // Rule ID 1601 // |
| 3072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3073 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3075 | // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) |
| 3076 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3077 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3078 | // GIR_Coverage, 1601, |
| 3079 | GIR_Done, |
| 3080 | // Label 332: @7172 |
| 3081 | GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(7198), // Rule ID 1602 // |
| 3082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3083 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3085 | // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) |
| 3086 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3087 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3088 | // GIR_Coverage, 1602, |
| 3089 | GIR_Done, |
| 3090 | // Label 333: @7198 |
| 3091 | GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(7224), // Rule ID 1603 // |
| 3092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3093 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3095 | // (bitconvert:{ *:[v2f64] } v1i128:{ *:[v1i128] }:$A) => (COPY_TO_REGCLASS:{ *:[v2f64] } ?:{ *:[v1i128] }:$A, VRRC:{ *:[i32] }) |
| 3096 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3097 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3098 | // GIR_Coverage, 1603, |
| 3099 | GIR_Done, |
| 3100 | // Label 334: @7224 |
| 3101 | GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(7250), // Rule ID 1605 // |
| 3102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3103 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3105 | // (bitconvert:{ *:[v2i64] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v2i64] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) |
| 3106 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3107 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3108 | // GIR_Coverage, 1605, |
| 3109 | GIR_Done, |
| 3110 | // Label 335: @7250 |
| 3111 | GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(7282), // Rule ID 1314 // |
| 3112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3113 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3115 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3116 | // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v2i64] }:$src |
| 3117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3118 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3119 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3120 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3121 | // GIR_Coverage, 1314, |
| 3122 | GIR_EraseRootFromParent_Done, |
| 3123 | // Label 336: @7282 |
| 3124 | GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(7314), // Rule ID 1315 // |
| 3125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3126 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3129 | // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v2i64] }:$src |
| 3130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3131 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3132 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3133 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3134 | // GIR_Coverage, 1315, |
| 3135 | GIR_EraseRootFromParent_Done, |
| 3136 | // Label 337: @7314 |
| 3137 | GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(7346), // Rule ID 1316 // |
| 3138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3139 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3141 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3142 | // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v2i64] }:$src |
| 3143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3144 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3145 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3146 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3147 | // GIR_Coverage, 1316, |
| 3148 | GIR_EraseRootFromParent_Done, |
| 3149 | // Label 338: @7346 |
| 3150 | GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7378), // Rule ID 1317 // |
| 3151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3152 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3154 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3155 | // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v2i64] }:$src |
| 3156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3157 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3158 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3159 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3160 | // GIR_Coverage, 1317, |
| 3161 | GIR_EraseRootFromParent_Done, |
| 3162 | // Label 339: @7378 |
| 3163 | GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7410), // Rule ID 1318 // |
| 3164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3167 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3168 | // (bitconvert:{ *:[v2i64] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v2i64] }:$src |
| 3169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3170 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3171 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3172 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3173 | // GIR_Coverage, 1318, |
| 3174 | GIR_EraseRootFromParent_Done, |
| 3175 | // Label 340: @7410 |
| 3176 | GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7442), // Rule ID 1333 // |
| 3177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3178 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3181 | // (bitconvert:{ *:[v2f64] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v2f64] }:$src |
| 3182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3183 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3184 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3185 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3186 | // GIR_Coverage, 1333, |
| 3187 | GIR_EraseRootFromParent_Done, |
| 3188 | // Label 341: @7442 |
| 3189 | GIM_Reject, |
| 3190 | // Label 303: @7443 |
| 3191 | GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7479), // Rule ID 935 // |
| 3192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 3193 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3195 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3196 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 3197 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 3198 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3199 | // (bitconvert:{ *:[v4i32] } immAllOnesV:{ *:[v16i8] }) => (XXLEQVOnes:{ *:[v4i32] }) |
| 3200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), |
| 3201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 3202 | GIR_RootConstrainSelectedInstOperands, |
| 3203 | // GIR_Coverage, 935, |
| 3204 | GIR_EraseRootFromParent_Done, |
| 3205 | // Label 342: @7479 |
| 3206 | GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7505), // Rule ID 1589 // |
| 3207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3208 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3210 | // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4f32] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) |
| 3211 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3212 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3213 | // GIR_Coverage, 1589, |
| 3214 | GIR_Done, |
| 3215 | // Label 343: @7505 |
| 3216 | GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7531), // Rule ID 1590 // |
| 3217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3218 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3220 | // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) |
| 3221 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3222 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3223 | // GIR_Coverage, 1590, |
| 3224 | GIR_Done, |
| 3225 | // Label 344: @7531 |
| 3226 | GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7557), // Rule ID 1597 // |
| 3227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3228 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3230 | // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4f32] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) |
| 3231 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3232 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3233 | // GIR_Coverage, 1597, |
| 3234 | GIR_Done, |
| 3235 | // Label 345: @7557 |
| 3236 | GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7583), // Rule ID 1598 // |
| 3237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3238 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3240 | // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) |
| 3241 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3242 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3243 | // GIR_Coverage, 1598, |
| 3244 | GIR_Done, |
| 3245 | // Label 346: @7583 |
| 3246 | GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7609), // Rule ID 1606 // |
| 3247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3250 | // (bitconvert:{ *:[v4i32] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) |
| 3251 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3252 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3253 | // GIR_Coverage, 1606, |
| 3254 | GIR_Done, |
| 3255 | // Label 347: @7609 |
| 3256 | GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(7641), // Rule ID 1304 // |
| 3257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3258 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3260 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3261 | // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4i32] }:$src |
| 3262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3263 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3264 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3265 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3266 | // GIR_Coverage, 1304, |
| 3267 | GIR_EraseRootFromParent_Done, |
| 3268 | // Label 348: @7641 |
| 3269 | GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(7673), // Rule ID 1305 // |
| 3270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3271 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3274 | // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4i32] }:$src |
| 3275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3276 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3277 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3278 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3279 | // GIR_Coverage, 1305, |
| 3280 | GIR_EraseRootFromParent_Done, |
| 3281 | // Label 349: @7673 |
| 3282 | GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(7705), // Rule ID 1306 // |
| 3283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3287 | // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v4i32] }:$src |
| 3288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3289 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3290 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3291 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3292 | // GIR_Coverage, 1306, |
| 3293 | GIR_EraseRootFromParent_Done, |
| 3294 | // Label 350: @7705 |
| 3295 | GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(7737), // Rule ID 1307 // |
| 3296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3297 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3299 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3300 | // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4i32] }:$src |
| 3301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3302 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3303 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3304 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3305 | // GIR_Coverage, 1307, |
| 3306 | GIR_EraseRootFromParent_Done, |
| 3307 | // Label 351: @7737 |
| 3308 | GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(7769), // Rule ID 1308 // |
| 3309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3310 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3312 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3313 | // (bitconvert:{ *:[v4i32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4i32] }:$src |
| 3314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3315 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3316 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3317 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3318 | // GIR_Coverage, 1308, |
| 3319 | GIR_EraseRootFromParent_Done, |
| 3320 | // Label 352: @7769 |
| 3321 | GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(7801), // Rule ID 1309 // |
| 3322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3323 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3326 | // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v4f32] }:$src |
| 3327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3328 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3329 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3330 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3331 | // GIR_Coverage, 1309, |
| 3332 | GIR_EraseRootFromParent_Done, |
| 3333 | // Label 353: @7801 |
| 3334 | GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(7833), // Rule ID 1310 // |
| 3335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3338 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3339 | // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v4f32] }:$src |
| 3340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3341 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3342 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3343 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3344 | // GIR_Coverage, 1310, |
| 3345 | GIR_EraseRootFromParent_Done, |
| 3346 | // Label 354: @7833 |
| 3347 | GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(7865), // Rule ID 1311 // |
| 3348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3349 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3351 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3352 | // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v4f32] }:$src |
| 3353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3354 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3355 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3356 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3357 | // GIR_Coverage, 1311, |
| 3358 | GIR_EraseRootFromParent_Done, |
| 3359 | // Label 355: @7865 |
| 3360 | GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(7897), // Rule ID 1312 // |
| 3361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3362 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3364 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3365 | // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v4f32] }:$src |
| 3366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3367 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3368 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3369 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3370 | // GIR_Coverage, 1312, |
| 3371 | GIR_EraseRootFromParent_Done, |
| 3372 | // Label 356: @7897 |
| 3373 | GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(7929), // Rule ID 1313 // |
| 3374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3375 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3377 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3378 | // (bitconvert:{ *:[v4f32] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v4f32] }:$src |
| 3379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3380 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3381 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3382 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3383 | // GIR_Coverage, 1313, |
| 3384 | GIR_EraseRootFromParent_Done, |
| 3385 | // Label 357: @7929 |
| 3386 | GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(7961), // Rule ID 1331 // |
| 3387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3388 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3390 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3391 | // (bitconvert:{ *:[v4i32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4i32] }:$src |
| 3392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3393 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3394 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3395 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3396 | // GIR_Coverage, 1331, |
| 3397 | GIR_EraseRootFromParent_Done, |
| 3398 | // Label 358: @7961 |
| 3399 | GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(7993), // Rule ID 1332 // |
| 3400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3401 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3403 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3404 | // (bitconvert:{ *:[v4f32] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v4f32] }:$src |
| 3405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3406 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3407 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3408 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3409 | // GIR_Coverage, 1332, |
| 3410 | GIR_EraseRootFromParent_Done, |
| 3411 | // Label 359: @7993 |
| 3412 | GIM_Reject, |
| 3413 | // Label 304: @7994 |
| 3414 | GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(8051), // Rule ID 1919 // |
| 3415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 3416 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3418 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3419 | GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 3420 | GIM_CheckIsBuildVectorAllOnes, /*MI*/1, |
| 3421 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3422 | // (bitconvert:{ *:[v8i16] } immAllOnesV:{ *:[v16i8] }) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXLEQVOnes:{ *:[v4i32] }), VSRC:{ *:[i32] }) |
| 3423 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3424 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLEQVOnes), |
| 3425 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3429 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3430 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 3431 | // GIR_Coverage, 1919, |
| 3432 | GIR_EraseRootFromParent_Done, |
| 3433 | // Label 360: @8051 |
| 3434 | GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(8077), // Rule ID 1591 // |
| 3435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3436 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3438 | // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) |
| 3439 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3440 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3441 | // GIR_Coverage, 1591, |
| 3442 | GIR_Done, |
| 3443 | // Label 361: @8077 |
| 3444 | GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(8103), // Rule ID 1599 // |
| 3445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3448 | // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) |
| 3449 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3450 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3451 | // GIR_Coverage, 1599, |
| 3452 | GIR_Done, |
| 3453 | // Label 362: @8103 |
| 3454 | GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(8129), // Rule ID 1607 // |
| 3455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3456 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3458 | // (bitconvert:{ *:[v8i16] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) |
| 3459 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3460 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3461 | // GIR_Coverage, 1607, |
| 3462 | GIR_Done, |
| 3463 | // Label 363: @8129 |
| 3464 | GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(8161), // Rule ID 1299 // |
| 3465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3466 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3468 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3469 | // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v16i8] }:$src) => VRRC:{ *:[v8i16] }:$src |
| 3470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3471 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3472 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3473 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3474 | // GIR_Coverage, 1299, |
| 3475 | GIR_EraseRootFromParent_Done, |
| 3476 | // Label 364: @8161 |
| 3477 | GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(8193), // Rule ID 1300 // |
| 3478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3479 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3481 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3482 | // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v8i16] }:$src |
| 3483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3484 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3485 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3486 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3487 | // GIR_Coverage, 1300, |
| 3488 | GIR_EraseRootFromParent_Done, |
| 3489 | // Label 365: @8193 |
| 3490 | GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(8225), // Rule ID 1301 // |
| 3491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3492 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3494 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3495 | // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v8i16] }:$src |
| 3496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3497 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3498 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3499 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3500 | // GIR_Coverage, 1301, |
| 3501 | GIR_EraseRootFromParent_Done, |
| 3502 | // Label 366: @8225 |
| 3503 | GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8257), // Rule ID 1302 // |
| 3504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3505 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3507 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3508 | // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v8i16] }:$src |
| 3509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3510 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3511 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3512 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3513 | // GIR_Coverage, 1302, |
| 3514 | GIR_EraseRootFromParent_Done, |
| 3515 | // Label 367: @8257 |
| 3516 | GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8289), // Rule ID 1303 // |
| 3517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3520 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3521 | // (bitconvert:{ *:[v8i16] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v8i16] }:$src |
| 3522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3523 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3524 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3525 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3526 | // GIR_Coverage, 1303, |
| 3527 | GIR_EraseRootFromParent_Done, |
| 3528 | // Label 368: @8289 |
| 3529 | GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8321), // Rule ID 1330 // |
| 3530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3531 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3533 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3534 | // (bitconvert:{ *:[v8i16] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v8i16] }:$src |
| 3535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3536 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3537 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3538 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3539 | // GIR_Coverage, 1330, |
| 3540 | GIR_EraseRootFromParent_Done, |
| 3541 | // Label 369: @8321 |
| 3542 | GIM_Reject, |
| 3543 | // Label 305: @8322 |
| 3544 | GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8348), // Rule ID 1592 // |
| 3545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3546 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3548 | // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[v2f64] }:$A, VRRC:{ *:[i32] }) |
| 3549 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3550 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3551 | // GIR_Coverage, 1592, |
| 3552 | GIR_Done, |
| 3553 | // Label 370: @8348 |
| 3554 | GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8374), // Rule ID 1600 // |
| 3555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3556 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3558 | // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[v2i64] }:$A, VRRC:{ *:[i32] }) |
| 3559 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3560 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3561 | // GIR_Coverage, 1600, |
| 3562 | GIR_Done, |
| 3563 | // Label 371: @8374 |
| 3564 | GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(8400), // Rule ID 1608 // |
| 3565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3566 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3568 | // (bitconvert:{ *:[v16i8] } f128:{ *:[f128] }:$A) => (COPY_TO_REGCLASS:{ *:[v16i8] } ?:{ *:[f128] }:$A, VRRC:{ *:[i32] }) |
| 3569 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3570 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3571 | // GIR_Coverage, 1608, |
| 3572 | GIR_Done, |
| 3573 | // Label 372: @8400 |
| 3574 | GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(8432), // Rule ID 1294 // |
| 3575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3576 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3579 | // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v8i16] }:$src) => VRRC:{ *:[v16i8] }:$src |
| 3580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3581 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3582 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3583 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3584 | // GIR_Coverage, 1294, |
| 3585 | GIR_EraseRootFromParent_Done, |
| 3586 | // Label 373: @8432 |
| 3587 | GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(8464), // Rule ID 1295 // |
| 3588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3589 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3591 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3592 | // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4i32] }:$src) => VRRC:{ *:[v16i8] }:$src |
| 3593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3594 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3595 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3596 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3597 | // GIR_Coverage, 1295, |
| 3598 | GIR_EraseRootFromParent_Done, |
| 3599 | // Label 374: @8464 |
| 3600 | GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(8496), // Rule ID 1296 // |
| 3601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3602 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3604 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3605 | // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v4f32] }:$src) => VRRC:{ *:[v16i8] }:$src |
| 3606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3607 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3608 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3609 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3610 | // GIR_Coverage, 1296, |
| 3611 | GIR_EraseRootFromParent_Done, |
| 3612 | // Label 375: @8496 |
| 3613 | GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(8528), // Rule ID 1297 // |
| 3614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3615 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3617 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3618 | // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v2i64] }:$src) => VRRC:{ *:[v16i8] }:$src |
| 3619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3620 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3621 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3622 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3623 | // GIR_Coverage, 1297, |
| 3624 | GIR_EraseRootFromParent_Done, |
| 3625 | // Label 376: @8528 |
| 3626 | GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(8560), // Rule ID 1298 // |
| 3627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3628 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3630 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3631 | // (bitconvert:{ *:[v16i8] } VRRC:{ *:[v1i128] }:$src) => VRRC:{ *:[v16i8] }:$src |
| 3632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3633 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3634 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3635 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3636 | // GIR_Coverage, 1298, |
| 3637 | GIR_EraseRootFromParent_Done, |
| 3638 | // Label 377: @8560 |
| 3639 | GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(8592), // Rule ID 1329 // |
| 3640 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3641 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3643 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3644 | // (bitconvert:{ *:[v16i8] } VRRC:{ *:[f128] }:$src) => VRRC:{ *:[v16i8] }:$src |
| 3645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3646 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 3647 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 3648 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 3649 | // GIR_Coverage, 1329, |
| 3650 | GIR_EraseRootFromParent_Done, |
| 3651 | // Label 378: @8592 |
| 3652 | GIM_Reject, |
| 3653 | // Label 306: @8593 |
| 3654 | GIM_Reject, |
| 3655 | // Label 12: @8594 |
| 3656 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 384*/ GIMT_Encode4(8865), |
| 3657 | /*GILLT_s32*//*Label 379*/ GIMT_Encode4(8625), |
| 3658 | /*GILLT_s64*//*Label 380*/ GIMT_Encode4(8715), |
| 3659 | /*GILLT_s128*//*Label 381*/ GIMT_Encode4(8763), |
| 3660 | /*GILLT_v2s64*//*Label 382*/ GIMT_Encode4(8794), |
| 3661 | /*GILLT_v4s32*//*Label 383*/ GIMT_Encode4(8817), |
| 3662 | // Label 379: @8625 |
| 3663 | GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(8714), |
| 3664 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 3665 | GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(8694), // Rule ID 1695 // |
| 3666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 3668 | // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIZ:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 3669 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3670 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 3671 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3672 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3673 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 3674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIZ), |
| 3676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3677 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 3678 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3681 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3682 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 3683 | // GIR_Coverage, 1695, |
| 3684 | GIR_EraseRootFromParent_Done, |
| 3685 | // Label 386: @8694 |
| 3686 | GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(8713), // Rule ID 147 // |
| 3687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 3688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 3689 | // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIZS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 3690 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIZS), |
| 3691 | GIR_RootConstrainSelectedInstOperands, |
| 3692 | // GIR_Coverage, 147, |
| 3693 | GIR_Done, |
| 3694 | // Label 387: @8713 |
| 3695 | GIM_Reject, |
| 3696 | // Label 385: @8714 |
| 3697 | GIM_Reject, |
| 3698 | // Label 380: @8715 |
| 3699 | GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(8762), |
| 3700 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 3701 | GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(8742), // Rule ID 905 // |
| 3702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 3704 | // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIZ:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 3705 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIZ), |
| 3706 | GIR_RootConstrainSelectedInstOperands, |
| 3707 | // GIR_Coverage, 905, |
| 3708 | GIR_Done, |
| 3709 | // Label 389: @8742 |
| 3710 | GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(8761), // Rule ID 145 // |
| 3711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 3712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 3713 | // (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIZD:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 3714 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIZD), |
| 3715 | GIR_RootConstrainSelectedInstOperands, |
| 3716 | // GIR_Coverage, 145, |
| 3717 | GIR_Done, |
| 3718 | // Label 390: @8761 |
| 3719 | GIM_Reject, |
| 3720 | // Label 388: @8762 |
| 3721 | GIM_Reject, |
| 3722 | // Label 381: @8763 |
| 3723 | GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(8793), // Rule ID 2144 // |
| 3724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 3725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3727 | // (ftrunc:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 1:{ *:[i32] }) |
| 3728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), |
| 3729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 3730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 3731 | GIR_RootToRootCopy, /*OpIdx*/1, // vB |
| 3732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 3733 | GIR_RootConstrainSelectedInstOperands, |
| 3734 | // GIR_Coverage, 2144, |
| 3735 | GIR_EraseRootFromParent_Done, |
| 3736 | // Label 391: @8793 |
| 3737 | GIM_Reject, |
| 3738 | // Label 382: @8794 |
| 3739 | GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(8816), // Rule ID 913 // |
| 3740 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3741 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3743 | // (ftrunc:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIZ:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 3744 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIZ), |
| 3745 | GIR_RootConstrainSelectedInstOperands, |
| 3746 | // GIR_Coverage, 913, |
| 3747 | GIR_Done, |
| 3748 | // Label 392: @8816 |
| 3749 | GIM_Reject, |
| 3750 | // Label 383: @8817 |
| 3751 | GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(8864), |
| 3752 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3753 | GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(8844), // Rule ID 921 // |
| 3754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3756 | // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 3757 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIZ), |
| 3758 | GIR_RootConstrainSelectedInstOperands, |
| 3759 | // GIR_Coverage, 921, |
| 3760 | GIR_Done, |
| 3761 | // Label 394: @8844 |
| 3762 | GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(8863), // Rule ID 1404 // |
| 3763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 3764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3765 | // (ftrunc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIZ:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA) |
| 3766 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIZ), |
| 3767 | GIR_RootConstrainSelectedInstOperands, |
| 3768 | // GIR_Coverage, 1404, |
| 3769 | GIR_Done, |
| 3770 | // Label 395: @8863 |
| 3771 | GIM_Reject, |
| 3772 | // Label 393: @8864 |
| 3773 | GIM_Reject, |
| 3774 | // Label 384: @8865 |
| 3775 | GIM_Reject, |
| 3776 | // Label 13: @8866 |
| 3777 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 401*/ GIMT_Encode4(9112), |
| 3778 | /*GILLT_s32*//*Label 396*/ GIMT_Encode4(8897), |
| 3779 | /*GILLT_s64*//*Label 397*/ GIMT_Encode4(8987), |
| 3780 | /*GILLT_s128*//*Label 398*/ GIMT_Encode4(9035), |
| 3781 | /*GILLT_v2s64*//*Label 399*/ GIMT_Encode4(9066), |
| 3782 | /*GILLT_v4s32*//*Label 400*/ GIMT_Encode4(9089), |
| 3783 | // Label 396: @8897 |
| 3784 | GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(8986), |
| 3785 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 3786 | GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(8966), // Rule ID 1689 // |
| 3787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 3789 | // (fround:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 3790 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3791 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 3792 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3793 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3794 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 3795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3796 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), |
| 3797 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3798 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 3799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3802 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3803 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 3804 | // GIR_Coverage, 1689, |
| 3805 | GIR_EraseRootFromParent_Done, |
| 3806 | // Label 403: @8966 |
| 3807 | GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(8985), // Rule ID 139 // |
| 3808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 3809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 3810 | // (fround:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRINS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 3811 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRINS), |
| 3812 | GIR_RootConstrainSelectedInstOperands, |
| 3813 | // GIR_Coverage, 139, |
| 3814 | GIR_Done, |
| 3815 | // Label 404: @8985 |
| 3816 | GIM_Reject, |
| 3817 | // Label 402: @8986 |
| 3818 | GIM_Reject, |
| 3819 | // Label 397: @8987 |
| 3820 | GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(9034), |
| 3821 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 3822 | GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(9014), // Rule ID 899 // |
| 3823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 3825 | // (fround:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPI:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 3826 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), |
| 3827 | GIR_RootConstrainSelectedInstOperands, |
| 3828 | // GIR_Coverage, 899, |
| 3829 | GIR_Done, |
| 3830 | // Label 406: @9014 |
| 3831 | GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(9033), // Rule ID 137 // |
| 3832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 3833 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 3834 | // (fround:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIND:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 3835 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIND), |
| 3836 | GIR_RootConstrainSelectedInstOperands, |
| 3837 | // GIR_Coverage, 137, |
| 3838 | GIR_Done, |
| 3839 | // Label 407: @9033 |
| 3840 | GIM_Reject, |
| 3841 | // Label 405: @9034 |
| 3842 | GIM_Reject, |
| 3843 | // Label 398: @9035 |
| 3844 | GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(9065), // Rule ID 2142 // |
| 3845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 3846 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 3847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 3848 | // (fround:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 0:{ *:[i32] }) |
| 3849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), |
| 3850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 3851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3852 | GIR_RootToRootCopy, /*OpIdx*/1, // vB |
| 3853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3854 | GIR_RootConstrainSelectedInstOperands, |
| 3855 | // GIR_Coverage, 2142, |
| 3856 | GIR_EraseRootFromParent_Done, |
| 3857 | // Label 408: @9065 |
| 3858 | GIM_Reject, |
| 3859 | // Label 399: @9066 |
| 3860 | GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(9088), // Rule ID 907 // |
| 3861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3862 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3864 | // (fround:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPI:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 3865 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPI), |
| 3866 | GIR_RootConstrainSelectedInstOperands, |
| 3867 | // GIR_Coverage, 907, |
| 3868 | GIR_Done, |
| 3869 | // Label 409: @9088 |
| 3870 | GIM_Reject, |
| 3871 | // Label 400: @9089 |
| 3872 | GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(9111), // Rule ID 915 // |
| 3873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 3874 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 3876 | // (fround:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPI:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 3877 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPI), |
| 3878 | GIR_RootConstrainSelectedInstOperands, |
| 3879 | // GIR_Coverage, 915, |
| 3880 | GIR_Done, |
| 3881 | // Label 410: @9111 |
| 3882 | GIM_Reject, |
| 3883 | // Label 401: @9112 |
| 3884 | GIM_Reject, |
| 3885 | // Label 14: @9113 |
| 3886 | GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(9240), |
| 3887 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 3888 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 414*/ GIMT_Encode4(9239), |
| 3889 | /*GILLT_s32*//*Label 412*/ GIMT_Encode4(9140), |
| 3890 | /*GILLT_s64*//*Label 413*/ GIMT_Encode4(9198), |
| 3891 | // Label 412: @9140 |
| 3892 | GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(9197), // Rule ID 2016 // |
| 3893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 3894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 3895 | // (lrint:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, F8RC:{ *:[i32] }))) |
| 3896 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3897 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 3898 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3899 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3900 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 3901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 3903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3904 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 3905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 3907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 3908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3909 | GIR_RootConstrainSelectedInstOperands, |
| 3910 | // GIR_Coverage, 2016, |
| 3911 | GIR_EraseRootFromParent_Done, |
| 3912 | // Label 415: @9197 |
| 3913 | GIM_Reject, |
| 3914 | // Label 413: @9198 |
| 3915 | GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(9238), // Rule ID 2015 // |
| 3916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 3917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 3918 | // (lrint:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } ?:{ *:[f64] }:$S)) |
| 3919 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3920 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 3921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3922 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 3923 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 3925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 3926 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3927 | GIR_RootConstrainSelectedInstOperands, |
| 3928 | // GIR_Coverage, 2015, |
| 3929 | GIR_EraseRootFromParent_Done, |
| 3930 | // Label 416: @9238 |
| 3931 | GIM_Reject, |
| 3932 | // Label 414: @9239 |
| 3933 | GIM_Reject, |
| 3934 | // Label 411: @9240 |
| 3935 | GIM_Reject, |
| 3936 | // Label 15: @9241 |
| 3937 | GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(9368), |
| 3938 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 3939 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 420*/ GIMT_Encode4(9367), |
| 3940 | /*GILLT_s32*//*Label 418*/ GIMT_Encode4(9268), |
| 3941 | /*GILLT_s64*//*Label 419*/ GIMT_Encode4(9326), |
| 3942 | // Label 418: @9268 |
| 3943 | GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(9325), // Rule ID 2018 // |
| 3944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 3945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 3946 | // (llrint:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, F8RC:{ *:[i32] }))) |
| 3947 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3948 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 3949 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3950 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3951 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 3952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3953 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 3954 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3955 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 3956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 3958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 3959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3960 | GIR_RootConstrainSelectedInstOperands, |
| 3961 | // GIR_Coverage, 2018, |
| 3962 | GIR_EraseRootFromParent_Done, |
| 3963 | // Label 421: @9325 |
| 3964 | GIM_Reject, |
| 3965 | // Label 419: @9326 |
| 3966 | GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(9366), // Rule ID 2017 // |
| 3967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 3968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 3969 | // (llrint:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } ?:{ *:[f64] }:$S)) |
| 3970 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3971 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 3972 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3973 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 3974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 3976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 3977 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3978 | GIR_RootConstrainSelectedInstOperands, |
| 3979 | // GIR_Coverage, 2017, |
| 3980 | GIR_EraseRootFromParent_Done, |
| 3981 | // Label 422: @9366 |
| 3982 | GIM_Reject, |
| 3983 | // Label 420: @9367 |
| 3984 | GIM_Reject, |
| 3985 | // Label 417: @9368 |
| 3986 | GIM_Reject, |
| 3987 | // Label 16: @9369 |
| 3988 | GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(9388), // Rule ID 632 // |
| 3989 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 3990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 3991 | // (readcyclecounter:{ *:[i64] }) => (MFTB8:{ *:[i64] }) |
| 3992 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MFTB8), |
| 3993 | GIR_RootConstrainSelectedInstOperands, |
| 3994 | // GIR_Coverage, 632, |
| 3995 | GIR_Done, |
| 3996 | // Label 423: @9388 |
| 3997 | GIM_Reject, |
| 3998 | // Label 17: @9389 |
| 3999 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 426*/ GIMT_Encode4(9464), |
| 4000 | /*GILLT_s32*//*Label 424*/ GIMT_Encode4(9408), |
| 4001 | /*GILLT_s64*//*Label 425*/ GIMT_Encode4(9436), |
| 4002 | // Label 424: @9408 |
| 4003 | GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(9435), // Rule ID 1254 // |
| 4004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 4005 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7, |
| 4006 | // MIs[0] Operand 1 |
| 4007 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 4008 | // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (SYNC 0:{ *:[i32] }) |
| 4009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 4010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4011 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 4012 | GIR_RootConstrainSelectedInstOperands, |
| 4013 | // GIR_Coverage, 1254, |
| 4014 | GIR_EraseRootFromParent_Done, |
| 4015 | // Label 427: @9435 |
| 4016 | GIM_Reject, |
| 4017 | // Label 425: @9436 |
| 4018 | GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(9463), // Rule ID 1253 // |
| 4019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 4020 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 7, |
| 4021 | // MIs[0] Operand 1 |
| 4022 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 4023 | // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (SYNC 0:{ *:[i32] }) |
| 4024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 4025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4026 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 4027 | GIR_RootConstrainSelectedInstOperands, |
| 4028 | // GIR_Coverage, 1253, |
| 4029 | GIR_EraseRootFromParent_Done, |
| 4030 | // Label 428: @9463 |
| 4031 | GIM_Reject, |
| 4032 | // Label 426: @9464 |
| 4033 | GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(9513), |
| 4034 | GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 4035 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 4036 | GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(9495), // Rule ID 1255 // |
| 4037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 4038 | // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (SYNC 1:{ *:[i32] }) |
| 4039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 4040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 4041 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 4042 | GIR_RootConstrainSelectedInstOperands, |
| 4043 | // GIR_Coverage, 1255, |
| 4044 | GIR_EraseRootFromParent_Done, |
| 4045 | // Label 430: @9495 |
| 4046 | GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(9512), // Rule ID 1256 // |
| 4047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC), |
| 4048 | // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] })) => (MSYNC) |
| 4049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC), |
| 4050 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 4051 | GIR_RootConstrainSelectedInstOperands, |
| 4052 | // GIR_Coverage, 1256, |
| 4053 | GIR_EraseRootFromParent_Done, |
| 4054 | // Label 431: @9512 |
| 4055 | GIM_Reject, |
| 4056 | // Label 429: @9513 |
| 4057 | GIM_Reject, |
| 4058 | // Label 18: @9514 |
| 4059 | GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(9576), |
| 4060 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 4061 | GIM_CheckIsMBB, /*MI*/0, /*Op*/1, |
| 4062 | GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(9563), // Rule ID 17 // |
| 4063 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 4064 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4065 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 4066 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 4067 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4068 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4069 | // (brcond (xor:{ *:[i1] } i1:{ *:[i1] }:$BI, -1:{ *:[i1] }), (bb:{ *:[Other] }):$BD) => (BCn i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) |
| 4070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCn), |
| 4071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // BI |
| 4072 | GIR_RootToRootCopy, /*OpIdx*/1, // BD |
| 4073 | GIR_RootConstrainSelectedInstOperands, |
| 4074 | // GIR_Coverage, 17, |
| 4075 | GIR_EraseRootFromParent_Done, |
| 4076 | // Label 433: @9563 |
| 4077 | GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(9575), // Rule ID 16 // |
| 4078 | // (brcond i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) => (BC i1:{ *:[i1] }:$BI, (bb:{ *:[Other] }):$BD) |
| 4079 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BC), |
| 4080 | GIR_RootConstrainSelectedInstOperands, |
| 4081 | // GIR_Coverage, 16, |
| 4082 | GIR_Done, |
| 4083 | // Label 434: @9575 |
| 4084 | GIM_Reject, |
| 4085 | // Label 432: @9576 |
| 4086 | GIM_Reject, |
| 4087 | // Label 19: @9577 |
| 4088 | GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(9698), |
| 4089 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 4090 | GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(9612), // Rule ID 1155 // |
| 4091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 4092 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxsetaccz), |
| 4093 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 4094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 4095 | // (intrinsic_wo_chain:{ *:[v512i1] } 9994:{ *:[iPTR] }) => (XXSETACCZ:{ *:[v512i1] }) |
| 4096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSETACCZ), |
| 4097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 4098 | GIR_RootConstrainSelectedInstOperands, |
| 4099 | // GIR_Coverage, 1155, |
| 4100 | GIR_EraseRootFromParent_Done, |
| 4101 | // Label 436: @9612 |
| 4102 | GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(9639), // Rule ID 1156 // |
| 4103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 4104 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxsetaccz), |
| 4105 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 4106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 4107 | // (intrinsic_wo_chain:{ *:[v512i1] } 9994:{ *:[iPTR] }) => (XXSETACCZW:{ *:[v512i1] }) |
| 4108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSETACCZW), |
| 4109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 4110 | GIR_RootConstrainSelectedInstOperands, |
| 4111 | // GIR_Coverage, 1156, |
| 4112 | GIR_EraseRootFromParent_Done, |
| 4113 | // Label 437: @9639 |
| 4114 | GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(9663), // Rule ID 4847 // |
| 4115 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfmsr), |
| 4116 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4118 | // (intrinsic_wo_chain:{ *:[i32] } 9926:{ *:[iPTR] }) => (MFMSR:{ *:[i32] }) |
| 4119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFMSR), |
| 4120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 4121 | GIR_RootConstrainSelectedInstOperands, |
| 4122 | // GIR_Coverage, 4847, |
| 4123 | GIR_EraseRootFromParent_Done, |
| 4124 | // Label 438: @9663 |
| 4125 | GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(9697), // Rule ID 4848 // |
| 4126 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mftbu), |
| 4127 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4129 | // (intrinsic_wo_chain:{ *:[i32] } 9928:{ *:[iPTR] }) => (MFTB:{ *:[i32] } 269:{ *:[i32] }) |
| 4130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFTB), |
| 4131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 4132 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(269), |
| 4133 | GIR_RootConstrainSelectedInstOperands, |
| 4134 | // GIR_Coverage, 4848, |
| 4135 | GIR_EraseRootFromParent_Done, |
| 4136 | // Label 439: @9697 |
| 4137 | GIM_Reject, |
| 4138 | // Label 435: @9698 |
| 4139 | GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(13211), |
| 4140 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 4141 | GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(9742), // Rule ID 1737 // |
| 4142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4143 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrte), |
| 4144 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4145 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 4147 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 4148 | // (intrinsic_wo_chain:{ *:[f64] } 9901:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XB) => (XSRSQRTEDP:{ *:[f64] } ?:{ *:[f64] }:$XB) |
| 4149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSQRTEDP), |
| 4150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4151 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4152 | GIR_RootConstrainSelectedInstOperands, |
| 4153 | // GIR_Coverage, 1737, |
| 4154 | GIR_EraseRootFromParent_Done, |
| 4155 | // Label 441: @9742 |
| 4156 | GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(9778), // Rule ID 1928 // |
| 4157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 4158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrtes), |
| 4159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 4162 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 4163 | // (intrinsic_wo_chain:{ *:[f32] } 9902:{ *:[iPTR] }, vssrc:{ *:[f32] }:$XB) => (XSRSQRTESP:{ *:[f32] } ?:{ *:[f32] }:$XB) |
| 4164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSQRTESP), |
| 4165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4166 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4167 | GIR_RootConstrainSelectedInstOperands, |
| 4168 | // GIR_Coverage, 1928, |
| 4169 | GIR_EraseRootFromParent_Done, |
| 4170 | // Label 442: @9778 |
| 4171 | GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(9810), // Rule ID 866 // |
| 4172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4173 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpsp), |
| 4174 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4175 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4177 | // (intrinsic_wo_chain:{ *:[v4f32] } 10087:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSP:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$XB) |
| 4178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSP), |
| 4179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4180 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4181 | GIR_RootConstrainSelectedInstOperands, |
| 4182 | // GIR_Coverage, 866, |
| 4183 | GIR_EraseRootFromParent_Done, |
| 4184 | // Label 443: @9810 |
| 4185 | GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(9842), // Rule ID 869 // |
| 4186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4187 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpsxws), |
| 4188 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4189 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4191 | // (intrinsic_wo_chain:{ *:[v4i32] } 10088:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB) |
| 4192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSXWS), |
| 4193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4194 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4195 | GIR_RootConstrainSelectedInstOperands, |
| 4196 | // GIR_Coverage, 869, |
| 4197 | GIR_EraseRootFromParent_Done, |
| 4198 | // Label 444: @9842 |
| 4199 | GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(9874), // Rule ID 872 // |
| 4200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4201 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvdpuxws), |
| 4202 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4203 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4205 | // (intrinsic_wo_chain:{ *:[v4i32] } 10089:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXWS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$XB) |
| 4206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVDPUXWS), |
| 4207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4208 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4209 | GIR_RootConstrainSelectedInstOperands, |
| 4210 | // GIR_Coverage, 872, |
| 4211 | GIR_EraseRootFromParent_Done, |
| 4212 | // Label 445: @9874 |
| 4213 | GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(9906), // Rule ID 873 // |
| 4214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4215 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspdp), |
| 4216 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4217 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4219 | // (intrinsic_wo_chain:{ *:[v2f64] } 10092:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPDP:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$XB) |
| 4220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPDP), |
| 4221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4222 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4223 | GIR_RootConstrainSelectedInstOperands, |
| 4224 | // GIR_Coverage, 873, |
| 4225 | GIR_EraseRootFromParent_Done, |
| 4226 | // Label 446: @9906 |
| 4227 | GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(9938), // Rule ID 874 // |
| 4228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4229 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspsxds), |
| 4230 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4233 | // (intrinsic_wo_chain:{ *:[v2i64] } 10094:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB) |
| 4234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPSXDS), |
| 4235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4236 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4237 | GIR_RootConstrainSelectedInstOperands, |
| 4238 | // GIR_Coverage, 874, |
| 4239 | GIR_EraseRootFromParent_Done, |
| 4240 | // Label 447: @9938 |
| 4241 | GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(9970), // Rule ID 877 // |
| 4242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4243 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspuxds), |
| 4244 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4245 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4247 | // (intrinsic_wo_chain:{ *:[v2i64] } 10095:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXDS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$XB) |
| 4248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPUXDS), |
| 4249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4250 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4251 | GIR_RootConstrainSelectedInstOperands, |
| 4252 | // GIR_Coverage, 877, |
| 4253 | GIR_EraseRootFromParent_Done, |
| 4254 | // Label 448: @9970 |
| 4255 | GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(10002), // Rule ID 882 // |
| 4256 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4257 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsxdsp), |
| 4258 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4259 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4261 | // (intrinsic_wo_chain:{ *:[v4f32] } 10096:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB) |
| 4262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSXDSP), |
| 4263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4264 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4265 | GIR_RootConstrainSelectedInstOperands, |
| 4266 | // GIR_Coverage, 882, |
| 4267 | GIR_EraseRootFromParent_Done, |
| 4268 | // Label 449: @10002 |
| 4269 | GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(10034), // Rule ID 887 // |
| 4270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4271 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvuxdsp), |
| 4272 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4273 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4275 | // (intrinsic_wo_chain:{ *:[v4f32] } 10098:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDSP:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$XB) |
| 4276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVUXDSP), |
| 4277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4278 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4279 | GIR_RootConstrainSelectedInstOperands, |
| 4280 | // GIR_Coverage, 887, |
| 4281 | GIR_EraseRootFromParent_Done, |
| 4282 | // Label 450: @10034 |
| 4283 | GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(10066), // Rule ID 890 // |
| 4284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4285 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsxwdp), |
| 4286 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4287 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4289 | // (intrinsic_wo_chain:{ *:[v2f64] } 10097:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB) |
| 4290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSXWDP), |
| 4291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4292 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4293 | GIR_RootConstrainSelectedInstOperands, |
| 4294 | // GIR_Coverage, 890, |
| 4295 | GIR_EraseRootFromParent_Done, |
| 4296 | // Label 451: @10066 |
| 4297 | GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(10098), // Rule ID 891 // |
| 4298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4299 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvuxwdp), |
| 4300 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4301 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4303 | // (intrinsic_wo_chain:{ *:[v2f64] } 10099:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWDP:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$XB) |
| 4304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVUXWDP), |
| 4305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4306 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4307 | GIR_RootConstrainSelectedInstOperands, |
| 4308 | // GIR_Coverage, 891, |
| 4309 | GIR_EraseRootFromParent_Done, |
| 4310 | // Label 452: @10098 |
| 4311 | GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(10130), // Rule ID 999 // |
| 4312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4313 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_sqrtf128_round_to_odd), |
| 4314 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 4315 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 4316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4317 | // (intrinsic_wo_chain:{ *:[f128] } 10023:{ *:[iPTR] }, f128:{ *:[f128] }:$RB) => (XSSQRTQPO:{ *:[f128] } f128:{ *:[f128] }:$RB) |
| 4318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQPO), |
| 4319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 4320 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 4321 | GIR_RootConstrainSelectedInstOperands, |
| 4322 | // GIR_Coverage, 999, |
| 4323 | GIR_EraseRootFromParent_Done, |
| 4324 | // Label 453: @10130 |
| 4325 | GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(10162), // Rule ID 1006 // |
| 4326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4327 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_truncf128_round_to_odd), |
| 4328 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4329 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 4330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VFRCRegClassID), |
| 4331 | // (intrinsic_wo_chain:{ *:[f64] } 10050:{ *:[iPTR] }, f128:{ *:[f128] }:$RB) => (XSCVQPDPO:{ *:[f64] } f128:{ *:[f128] }:$RB) |
| 4332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDPO), |
| 4333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 4334 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 4335 | GIR_RootConstrainSelectedInstOperands, |
| 4336 | // GIR_Coverage, 1006, |
| 4337 | GIR_EraseRootFromParent_Done, |
| 4338 | // Label 454: @10162 |
| 4339 | GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(10194), // Rule ID 1015 // |
| 4340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4341 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvsphp), |
| 4342 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4343 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4345 | // (intrinsic_wo_chain:{ *:[v4f32] } 10093:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVCVSPHP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 4346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVSPHP), |
| 4347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4348 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4349 | GIR_RootConstrainSelectedInstOperands, |
| 4350 | // GIR_Coverage, 1015, |
| 4351 | GIR_EraseRootFromParent_Done, |
| 4352 | // Label 455: @10194 |
| 4353 | GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(10226), // Rule ID 1019 // |
| 4354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4355 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxexpdp), |
| 4356 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4357 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4359 | // (intrinsic_wo_chain:{ *:[v2i64] } 10121:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXEXPDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) |
| 4360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXEXPDP), |
| 4361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4362 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4363 | GIR_RootConstrainSelectedInstOperands, |
| 4364 | // GIR_Coverage, 1019, |
| 4365 | GIR_EraseRootFromParent_Done, |
| 4366 | // Label 456: @10226 |
| 4367 | GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(10258), // Rule ID 1020 // |
| 4368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4369 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxexpsp), |
| 4370 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4371 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4373 | // (intrinsic_wo_chain:{ *:[v4i32] } 10122:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXEXPSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) |
| 4374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXEXPSP), |
| 4375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4376 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4377 | GIR_RootConstrainSelectedInstOperands, |
| 4378 | // GIR_Coverage, 1020, |
| 4379 | GIR_EraseRootFromParent_Done, |
| 4380 | // Label 457: @10258 |
| 4381 | GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(10290), // Rule ID 1021 // |
| 4382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4383 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxsigdp), |
| 4384 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4385 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4387 | // (intrinsic_wo_chain:{ *:[v2i64] } 10123:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB) => (XVXSIGDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) |
| 4388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXSIGDP), |
| 4389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4390 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4391 | GIR_RootConstrainSelectedInstOperands, |
| 4392 | // GIR_Coverage, 1021, |
| 4393 | GIR_EraseRootFromParent_Done, |
| 4394 | // Label 458: @10290 |
| 4395 | GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(10322), // Rule ID 1022 // |
| 4396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4397 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvxsigsp), |
| 4398 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4399 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4401 | // (intrinsic_wo_chain:{ *:[v4i32] } 10124:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB) => (XVXSIGSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) |
| 4402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVXSIGSP), |
| 4403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4404 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 4405 | GIR_RootConstrainSelectedInstOperands, |
| 4406 | // GIR_Coverage, 1022, |
| 4407 | GIR_EraseRootFromParent_Done, |
| 4408 | // Label 459: @10322 |
| 4409 | GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(10377), // Rule ID 1645 // |
| 4410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4411 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtsqrtdp), |
| 4412 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4413 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4415 | // (intrinsic_wo_chain:{ *:[i32] } 10117:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTSQRTDP:{ *:[i32] } ?:{ *:[v2f64] }:$A), GPRC:{ *:[i32] }) |
| 4416 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 4417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTSQRTDP), |
| 4418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4419 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 4420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 4423 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4424 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 4425 | // GIR_Coverage, 1645, |
| 4426 | GIR_EraseRootFromParent_Done, |
| 4427 | // Label 460: @10377 |
| 4428 | GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(10432), // Rule ID 1646 // |
| 4429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4430 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtsqrtsp), |
| 4431 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4434 | // (intrinsic_wo_chain:{ *:[i32] } 10118:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTSQRTSP:{ *:[i32] } ?:{ *:[v4f32] }:$A), GPRC:{ *:[i32] }) |
| 4435 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 4436 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTSQRTSP), |
| 4437 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4438 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 4439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 4442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4443 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 4444 | // GIR_Coverage, 1646, |
| 4445 | GIR_EraseRootFromParent_Done, |
| 4446 | // Label 461: @10432 |
| 4447 | GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(10464), // Rule ID 1647 // |
| 4448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4449 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvresp), |
| 4450 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4451 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4453 | // (intrinsic_wo_chain:{ *:[v4f32] } 10110:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (XVRESP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A) |
| 4454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRESP), |
| 4455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4456 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4457 | GIR_RootConstrainSelectedInstOperands, |
| 4458 | // GIR_Coverage, 1647, |
| 4459 | GIR_EraseRootFromParent_Done, |
| 4460 | // Label 462: @10464 |
| 4461 | GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(10496), // Rule ID 1648 // |
| 4462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4463 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvredp), |
| 4464 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4465 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4467 | // (intrinsic_wo_chain:{ *:[v2f64] } 10109:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (XVREDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A) |
| 4468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVREDP), |
| 4469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4470 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4471 | GIR_RootConstrainSelectedInstOperands, |
| 4472 | // GIR_Coverage, 1648, |
| 4473 | GIR_EraseRootFromParent_Done, |
| 4474 | // Label 463: @10496 |
| 4475 | GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(10528), // Rule ID 1649 // |
| 4476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4477 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvrsqrtesp), |
| 4478 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4479 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4481 | // (intrinsic_wo_chain:{ *:[v4f32] } 10113:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A) => (XVRSQRTESP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A) |
| 4482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRSQRTESP), |
| 4483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4484 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4485 | GIR_RootConstrainSelectedInstOperands, |
| 4486 | // GIR_Coverage, 1649, |
| 4487 | GIR_EraseRootFromParent_Done, |
| 4488 | // Label 464: @10528 |
| 4489 | GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(10560), // Rule ID 1650 // |
| 4490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4491 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvrsqrtedp), |
| 4492 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4493 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4495 | // (intrinsic_wo_chain:{ *:[v2f64] } 10112:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A) => (XVRSQRTEDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A) |
| 4496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVRSQRTEDP), |
| 4497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4498 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4499 | GIR_RootConstrainSelectedInstOperands, |
| 4500 | // GIR_Coverage, 1650, |
| 4501 | GIR_EraseRootFromParent_Done, |
| 4502 | // Label 465: @10560 |
| 4503 | GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(10592), // Rule ID 1736 // |
| 4504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4505 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fre), |
| 4506 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4507 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 4509 | // (intrinsic_wo_chain:{ *:[f64] } 9899:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSREDP:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 4510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSREDP), |
| 4511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4512 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4513 | GIR_RootConstrainSelectedInstOperands, |
| 4514 | // GIR_Coverage, 1736, |
| 4515 | GIR_EraseRootFromParent_Done, |
| 4516 | // Label 466: @10592 |
| 4517 | GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(10624), // Rule ID 1738 // |
| 4518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4519 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabs), |
| 4520 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4521 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 4523 | // (intrinsic_wo_chain:{ *:[f64] } 9894:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSNABSDP:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 4524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDP), |
| 4525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4526 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4527 | GIR_RootConstrainSelectedInstOperands, |
| 4528 | // GIR_Coverage, 1738, |
| 4529 | GIR_EraseRootFromParent_Done, |
| 4530 | // Label 467: @10624 |
| 4531 | GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(10656), // Rule ID 1739 // |
| 4532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 4533 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabss), |
| 4534 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4535 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 4537 | // (intrinsic_wo_chain:{ *:[f32] } 9895:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (XSNABSDPs:{ *:[f32] } ?:{ *:[f32] }:$A) |
| 4538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDPs), |
| 4539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4540 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4541 | GIR_RootConstrainSelectedInstOperands, |
| 4542 | // GIR_Coverage, 1739, |
| 4543 | GIR_EraseRootFromParent_Done, |
| 4544 | // Label 468: @10656 |
| 4545 | GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(10688), // Rule ID 1923 // |
| 4546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 4547 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fres), |
| 4548 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4549 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 4551 | // (intrinsic_wo_chain:{ *:[f32] } 9900:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (XSRESP:{ *:[f32] } ?:{ *:[f32] }:$A) |
| 4552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRESP), |
| 4553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4554 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 4555 | GIR_RootConstrainSelectedInstOperands, |
| 4556 | // GIR_Coverage, 1923, |
| 4557 | GIR_EraseRootFromParent_Done, |
| 4558 | // Label 469: @10688 |
| 4559 | GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(10769), // Rule ID 1924 // |
| 4560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 4561 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_extract_exp), |
| 4562 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4563 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 4565 | // (intrinsic_wo_chain:{ *:[i32] } 9879:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (EXTRACT_SUBREG:{ *:[i32] } (XSXEXPDP:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f64] }:$A, VSFRC:{ *:[i32] })), sub_32:{ *:[i32] }) |
| 4566 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 4567 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 4568 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4569 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4570 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 4571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4572 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSXEXPDP), |
| 4573 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4574 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 4575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 4578 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 4579 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 4580 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 4581 | // GIR_Coverage, 1924, |
| 4582 | GIR_EraseRootFromParent_Done, |
| 4583 | // Label 470: @10769 |
| 4584 | GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(10820), // Rule ID 1925 // |
| 4585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 4586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_extract_sig), |
| 4587 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 4590 | // (intrinsic_wo_chain:{ *:[i64] } 9880:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSXSIGDP:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f64] }:$A, VSFRC:{ *:[i32] })) |
| 4591 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 4592 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4593 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4594 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 4595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSXSIGDP), |
| 4597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 4598 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4599 | GIR_RootConstrainSelectedInstOperands, |
| 4600 | // GIR_Coverage, 1925, |
| 4601 | GIR_EraseRootFromParent_Done, |
| 4602 | // Label 471: @10820 |
| 4603 | GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(10871), // Rule ID 2138 // |
| 4604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4605 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvhpsp), |
| 4606 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4607 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 4609 | // (intrinsic_wo_chain:{ *:[v4f32] } 10090:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$A) => (XVCVHPSP:{ *:[v4f32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] })) |
| 4610 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4611 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4612 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4613 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 4614 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCVHPSP), |
| 4616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 4617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4618 | GIR_RootConstrainSelectedInstOperands, |
| 4619 | // GIR_Coverage, 2138, |
| 4620 | GIR_EraseRootFromParent_Done, |
| 4621 | // Label 472: @10871 |
| 4622 | GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(10951), // Rule ID 2152 // |
| 4623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 4624 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_scalar_extract_expq), |
| 4625 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4626 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 4627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 4628 | // (intrinsic_wo_chain:{ *:[i64] } 10014:{ *:[iPTR] }, f128:{ *:[f128] }:$vA) => (MFVSRD:{ *:[i64] } (EXTRACT_SUBREG:{ *:[f64] } (XSXEXPQP:{ *:[v2i64] } ?:{ *:[f128] }:$vA), sub_64:{ *:[i32] })) |
| 4629 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 4630 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64, |
| 4631 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSXEXPQP), |
| 4632 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4633 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vA |
| 4634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4635 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4636 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4637 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_64), |
| 4638 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::VFRCRegClassID), |
| 4639 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::VRRCRegClassID), |
| 4640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 4641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 4642 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4643 | GIR_RootConstrainSelectedInstOperands, |
| 4644 | // GIR_Coverage, 2152, |
| 4645 | GIR_EraseRootFromParent_Done, |
| 4646 | // Label 473: @10951 |
| 4647 | GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(10994), // Rule ID 1085 // |
| 4648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 4649 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrbm), |
| 4650 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 4651 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4653 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4654 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4655 | // MIs[1] Operand 1 |
| 4656 | // No operand predicates |
| 4657 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4658 | // (intrinsic_wo_chain:{ *:[v16i8] } 9548:{ *:[iPTR] }, (imm:{ *:[i64] }):$D) => (MTVSRBMI:{ *:[v16i8] } (imm:{ *:[i64] }):$D) |
| 4659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRBMI), |
| 4660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 4661 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // D |
| 4662 | GIR_RootConstrainSelectedInstOperands, |
| 4663 | // GIR_Coverage, 1085, |
| 4664 | GIR_EraseRootFromParent_Done, |
| 4665 | // Label 474: @10994 |
| 4666 | GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(11027), // Rule ID 4805 // |
| 4667 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrte), |
| 4668 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 4669 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 4671 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 4672 | // (intrinsic_wo_chain:{ *:[f64] } 9901:{ *:[iPTR] }, f8rc:{ *:[f64] }:$frB) => (FRSQRTE:{ *:[f64] } ?:{ *:[f64] }:$frB) |
| 4673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRSQRTE), |
| 4674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 4675 | GIR_RootToRootCopy, /*OpIdx*/2, // frB |
| 4676 | GIR_RootConstrainSelectedInstOperands, |
| 4677 | // GIR_Coverage, 4805, |
| 4678 | GIR_EraseRootFromParent_Done, |
| 4679 | // Label 475: @11027 |
| 4680 | GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(11060), // Rule ID 4806 // |
| 4681 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_frsqrtes), |
| 4682 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4683 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 4685 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 4686 | // (intrinsic_wo_chain:{ *:[f32] } 9902:{ *:[iPTR] }, f4rc:{ *:[f32] }:$frB) => (FRSQRTES:{ *:[f32] } ?:{ *:[f32] }:$frB) |
| 4687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRSQRTES), |
| 4688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 4689 | GIR_RootToRootCopy, /*OpIdx*/2, // frB |
| 4690 | GIR_RootConstrainSelectedInstOperands, |
| 4691 | // GIR_Coverage, 4806, |
| 4692 | GIR_EraseRootFromParent_Done, |
| 4693 | // Label 476: @11060 |
| 4694 | GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(11089), // Rule ID 73 // |
| 4695 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_popcntb), |
| 4696 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4697 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4699 | // (intrinsic_wo_chain:{ *:[i32] } 10009:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (POPCNTB:{ *:[i32] } i32:{ *:[i32] }:$RST) |
| 4700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::POPCNTB), |
| 4701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 4702 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 4703 | GIR_RootConstrainSelectedInstOperands, |
| 4704 | // GIR_Coverage, 73, |
| 4705 | GIR_EraseRootFromParent_Done, |
| 4706 | // Label 477: @11089 |
| 4707 | GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(11121), // Rule ID 318 // |
| 4708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4709 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexptefp), |
| 4710 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4711 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4713 | // (intrinsic_wo_chain:{ *:[v4f32] } 9655:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VEXPTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPTEFP), |
| 4715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4716 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4717 | GIR_RootConstrainSelectedInstOperands, |
| 4718 | // GIR_Coverage, 318, |
| 4719 | GIR_EraseRootFromParent_Done, |
| 4720 | // Label 478: @11121 |
| 4721 | GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(11153), // Rule ID 319 // |
| 4722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4723 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vlogefp), |
| 4724 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4725 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4727 | // (intrinsic_wo_chain:{ *:[v4f32] } 9693:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VLOGEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VLOGEFP), |
| 4729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4730 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4731 | GIR_RootConstrainSelectedInstOperands, |
| 4732 | // GIR_Coverage, 319, |
| 4733 | GIR_EraseRootFromParent_Done, |
| 4734 | // Label 479: @11153 |
| 4735 | GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(11185), // Rule ID 360 // |
| 4736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4737 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrefp), |
| 4738 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4739 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4741 | // (intrinsic_wo_chain:{ *:[v4f32] } 9761:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VREFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VREFP), |
| 4743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4744 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4745 | GIR_RootConstrainSelectedInstOperands, |
| 4746 | // GIR_Coverage, 360, |
| 4747 | GIR_EraseRootFromParent_Done, |
| 4748 | // Label 480: @11185 |
| 4749 | GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(11217), // Rule ID 361 // |
| 4750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4751 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfim), |
| 4752 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4753 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4755 | // (intrinsic_wo_chain:{ *:[v4f32] } 9762:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIM), |
| 4757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4758 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4759 | GIR_RootConstrainSelectedInstOperands, |
| 4760 | // GIR_Coverage, 361, |
| 4761 | GIR_EraseRootFromParent_Done, |
| 4762 | // Label 481: @11217 |
| 4763 | GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(11249), // Rule ID 362 // |
| 4764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4765 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfin), |
| 4766 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4767 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4769 | // (intrinsic_wo_chain:{ *:[v4f32] } 9763:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIN:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIN), |
| 4771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4772 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4773 | GIR_RootConstrainSelectedInstOperands, |
| 4774 | // GIR_Coverage, 362, |
| 4775 | GIR_EraseRootFromParent_Done, |
| 4776 | // Label 482: @11249 |
| 4777 | GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(11281), // Rule ID 363 // |
| 4778 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4779 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfip), |
| 4780 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4781 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4783 | // (intrinsic_wo_chain:{ *:[v4f32] } 9764:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIP), |
| 4785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4786 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4787 | GIR_RootConstrainSelectedInstOperands, |
| 4788 | // GIR_Coverage, 363, |
| 4789 | GIR_EraseRootFromParent_Done, |
| 4790 | // Label 483: @11281 |
| 4791 | GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(11313), // Rule ID 364 // |
| 4792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4793 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrfiz), |
| 4794 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4795 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4797 | // (intrinsic_wo_chain:{ *:[v4f32] } 9765:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRFIZ:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRFIZ), |
| 4799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4800 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4801 | GIR_RootConstrainSelectedInstOperands, |
| 4802 | // GIR_Coverage, 364, |
| 4803 | GIR_EraseRootFromParent_Done, |
| 4804 | // Label 484: @11313 |
| 4805 | GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(11345), // Rule ID 365 // |
| 4806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4807 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrsqrtefp), |
| 4808 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4809 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4811 | // (intrinsic_wo_chain:{ *:[v4f32] } 9776:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB) => (VRSQRTEFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VB) |
| 4812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRSQRTEFP), |
| 4813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4814 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4815 | GIR_RootConstrainSelectedInstOperands, |
| 4816 | // GIR_Coverage, 365, |
| 4817 | GIR_EraseRootFromParent_Done, |
| 4818 | // Label 485: @11345 |
| 4819 | GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(11377), // Rule ID 416 // |
| 4820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4821 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhpx), |
| 4822 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4823 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4825 | // (intrinsic_wo_chain:{ *:[v4i32] } 9818:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKHPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) |
| 4826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHPX), |
| 4827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4828 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4829 | GIR_RootConstrainSelectedInstOperands, |
| 4830 | // GIR_Coverage, 416, |
| 4831 | GIR_EraseRootFromParent_Done, |
| 4832 | // Label 486: @11377 |
| 4833 | GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(11409), // Rule ID 417 // |
| 4834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4835 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsb), |
| 4836 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 4837 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4839 | // (intrinsic_wo_chain:{ *:[v8i16] } 9819:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VUPKHSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VB) |
| 4840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSB), |
| 4841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4842 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4843 | GIR_RootConstrainSelectedInstOperands, |
| 4844 | // GIR_Coverage, 417, |
| 4845 | GIR_EraseRootFromParent_Done, |
| 4846 | // Label 487: @11409 |
| 4847 | GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(11441), // Rule ID 418 // |
| 4848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4849 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsh), |
| 4850 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4851 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4853 | // (intrinsic_wo_chain:{ *:[v4i32] } 9820:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKHSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) |
| 4854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSH), |
| 4855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4856 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4857 | GIR_RootConstrainSelectedInstOperands, |
| 4858 | // GIR_Coverage, 418, |
| 4859 | GIR_EraseRootFromParent_Done, |
| 4860 | // Label 488: @11441 |
| 4861 | GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(11473), // Rule ID 419 // |
| 4862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4863 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklpx), |
| 4864 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4865 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4867 | // (intrinsic_wo_chain:{ *:[v4i32] } 9822:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKLPX:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) |
| 4868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLPX), |
| 4869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4870 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4871 | GIR_RootConstrainSelectedInstOperands, |
| 4872 | // GIR_Coverage, 419, |
| 4873 | GIR_EraseRootFromParent_Done, |
| 4874 | // Label 489: @11473 |
| 4875 | GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(11505), // Rule ID 420 // |
| 4876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4877 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsb), |
| 4878 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 4879 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4881 | // (intrinsic_wo_chain:{ *:[v8i16] } 9823:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VUPKLSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VB) |
| 4882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSB), |
| 4883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4884 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4885 | GIR_RootConstrainSelectedInstOperands, |
| 4886 | // GIR_Coverage, 420, |
| 4887 | GIR_EraseRootFromParent_Done, |
| 4888 | // Label 490: @11505 |
| 4889 | GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(11537), // Rule ID 421 // |
| 4890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 4891 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsh), |
| 4892 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4893 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4895 | // (intrinsic_wo_chain:{ *:[v4i32] } 9824:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VUPKLSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) |
| 4896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSH), |
| 4897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4898 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4899 | GIR_RootConstrainSelectedInstOperands, |
| 4900 | // GIR_Coverage, 421, |
| 4901 | GIR_EraseRootFromParent_Done, |
| 4902 | // Label 491: @11537 |
| 4903 | GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(11569), // Rule ID 501 // |
| 4904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 4905 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupkhsw), |
| 4906 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4907 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4909 | // (intrinsic_wo_chain:{ *:[v2i64] } 9821:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VUPKHSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB) |
| 4910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKHSW), |
| 4911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4912 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4913 | GIR_RootConstrainSelectedInstOperands, |
| 4914 | // GIR_Coverage, 501, |
| 4915 | GIR_EraseRootFromParent_Done, |
| 4916 | // Label 492: @11569 |
| 4917 | GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(11601), // Rule ID 502 // |
| 4918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 4919 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vupklsw), |
| 4920 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4921 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4923 | // (intrinsic_wo_chain:{ *:[v2i64] } 9825:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VUPKLSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB) |
| 4924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VUPKLSW), |
| 4925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4926 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4927 | GIR_RootConstrainSelectedInstOperands, |
| 4928 | // GIR_Coverage, 502, |
| 4929 | GIR_EraseRootFromParent_Done, |
| 4930 | // Label 493: @11601 |
| 4931 | GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(11633), // Rule ID 503 // |
| 4932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 4933 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vgbbd), |
| 4934 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 4935 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4937 | // (intrinsic_wo_chain:{ *:[v16i8] } 9675:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VGBBD:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 4938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VGBBD), |
| 4939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4940 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4941 | GIR_RootConstrainSelectedInstOperands, |
| 4942 | // GIR_Coverage, 503, |
| 4943 | GIR_EraseRootFromParent_Done, |
| 4944 | // Label 494: @11633 |
| 4945 | GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(11665), // Rule ID 511 // |
| 4946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 4947 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vsbox), |
| 4948 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4949 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4951 | // (intrinsic_wo_chain:{ *:[v2i64] } 9530:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA) => (VSBOX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA) |
| 4952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSBOX), |
| 4953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4954 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 4955 | GIR_RootConstrainSelectedInstOperands, |
| 4956 | // GIR_Coverage, 511, |
| 4957 | GIR_EraseRootFromParent_Done, |
| 4958 | // Label 495: @11665 |
| 4959 | GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(11697), // Rule ID 527 // |
| 4960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 4961 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclzlsbb), |
| 4962 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4963 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4965 | // (intrinsic_wo_chain:{ *:[i32] } 9585:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VCLZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB) |
| 4966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLZLSBB), |
| 4967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4968 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4969 | GIR_RootConstrainSelectedInstOperands, |
| 4970 | // GIR_Coverage, 527, |
| 4971 | GIR_EraseRootFromParent_Done, |
| 4972 | // Label 496: @11697 |
| 4973 | GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(11729), // Rule ID 528 // |
| 4974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 4975 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctzlsbb), |
| 4976 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 4977 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 4979 | // (intrinsic_wo_chain:{ *:[i32] } 9643:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VCTZLSBB:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB) |
| 4980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTZLSBB), |
| 4981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4982 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4983 | GIR_RootConstrainSelectedInstOperands, |
| 4984 | // GIR_Coverage, 528, |
| 4985 | GIR_EraseRootFromParent_Done, |
| 4986 | // Label 497: @11729 |
| 4987 | GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(11761), // Rule ID 533 // |
| 4988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 4989 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsb2w), |
| 4990 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4991 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 4992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 4993 | // (intrinsic_wo_chain:{ *:[v4i32] } 9670:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTSB2W:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VB) |
| 4994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2W), |
| 4995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 4996 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 4997 | GIR_RootConstrainSelectedInstOperands, |
| 4998 | // GIR_Coverage, 533, |
| 4999 | GIR_EraseRootFromParent_Done, |
| 5000 | // Label 498: @11761 |
| 5001 | GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(11793), // Rule ID 534 // |
| 5002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5003 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsh2w), |
| 5004 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5005 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5007 | // (intrinsic_wo_chain:{ *:[v4i32] } 9673:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTSH2W:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VB) |
| 5008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2W), |
| 5009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5010 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5011 | GIR_RootConstrainSelectedInstOperands, |
| 5012 | // GIR_Coverage, 534, |
| 5013 | GIR_EraseRootFromParent_Done, |
| 5014 | // Label 499: @11793 |
| 5015 | GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(11825), // Rule ID 535 // |
| 5016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5017 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsb2d), |
| 5018 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5019 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5021 | // (intrinsic_wo_chain:{ *:[v2i64] } 9669:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTSB2D:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$VB) |
| 5022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSB2D), |
| 5023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5024 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5025 | GIR_RootConstrainSelectedInstOperands, |
| 5026 | // GIR_Coverage, 535, |
| 5027 | GIR_EraseRootFromParent_Done, |
| 5028 | // Label 500: @11825 |
| 5029 | GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(11857), // Rule ID 536 // |
| 5030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5031 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsh2d), |
| 5032 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5033 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5035 | // (intrinsic_wo_chain:{ *:[v2i64] } 9672:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTSH2D:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$VB) |
| 5036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSH2D), |
| 5037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5038 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5039 | GIR_RootConstrainSelectedInstOperands, |
| 5040 | // GIR_Coverage, 536, |
| 5041 | GIR_EraseRootFromParent_Done, |
| 5042 | // Label 501: @11857 |
| 5043 | GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(11889), // Rule ID 537 // |
| 5044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5045 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsw2d), |
| 5046 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5047 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5048 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5049 | // (intrinsic_wo_chain:{ *:[v2i64] } 9674:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXTSW2D:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VB) |
| 5050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSW2D), |
| 5051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5052 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5053 | GIR_RootConstrainSelectedInstOperands, |
| 5054 | // GIR_Coverage, 537, |
| 5055 | GIR_EraseRootFromParent_Done, |
| 5056 | // Label 502: @11889 |
| 5057 | GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(11921), // Rule ID 540 // |
| 5058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5059 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybw), |
| 5060 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5061 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5063 | // (intrinsic_wo_chain:{ *:[v4i32] } 9760:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VPRTYBW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) |
| 5064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBW), |
| 5065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5066 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5067 | GIR_RootConstrainSelectedInstOperands, |
| 5068 | // GIR_Coverage, 540, |
| 5069 | GIR_EraseRootFromParent_Done, |
| 5070 | // Label 503: @11921 |
| 5071 | GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(11953), // Rule ID 541 // |
| 5072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5073 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybd), |
| 5074 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5075 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5077 | // (intrinsic_wo_chain:{ *:[v2i64] } 9758:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VPRTYBD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) |
| 5078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBD), |
| 5079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5080 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5081 | GIR_RootConstrainSelectedInstOperands, |
| 5082 | // GIR_Coverage, 541, |
| 5083 | GIR_EraseRootFromParent_Done, |
| 5084 | // Label 504: @11953 |
| 5085 | GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(11985), // Rule ID 542 // |
| 5086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 5087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vprtybq), |
| 5088 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5089 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5091 | // (intrinsic_wo_chain:{ *:[v1i128] } 9759:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VPRTYBQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VB) |
| 5092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPRTYBQ), |
| 5093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5094 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5095 | GIR_RootConstrainSelectedInstOperands, |
| 5096 | // GIR_Coverage, 542, |
| 5097 | GIR_EraseRootFromParent_Done, |
| 5098 | // Label 505: @11985 |
| 5099 | GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(12014), // Rule ID 686 // |
| 5100 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_popcntb), |
| 5101 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5102 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 5104 | // (intrinsic_wo_chain:{ *:[i64] } 10009:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (POPCNTB8:{ *:[i64] } i64:{ *:[i64] }:$RST) |
| 5105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::POPCNTB8), |
| 5106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 5107 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 5108 | GIR_RootConstrainSelectedInstOperands, |
| 5109 | // GIR_Coverage, 686, |
| 5110 | GIR_EraseRootFromParent_Done, |
| 5111 | // Label 506: @12014 |
| 5112 | GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(12046), // Rule ID 1050 // |
| 5113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5114 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstribr), |
| 5115 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5116 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5118 | // (intrinsic_wo_chain:{ *:[v16i8] } 9797:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VSTRIBR:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 5119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIBR), |
| 5120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] |
| 5121 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5122 | GIR_RootConstrainSelectedInstOperands, |
| 5123 | // GIR_Coverage, 1050, |
| 5124 | GIR_EraseRootFromParent_Done, |
| 5125 | // Label 507: @12046 |
| 5126 | GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(12078), // Rule ID 1051 // |
| 5127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5128 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstribl), |
| 5129 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5130 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5132 | // (intrinsic_wo_chain:{ *:[v16i8] } 9795:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VSTRIBL:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 5133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIBL), |
| 5134 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] |
| 5135 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5136 | GIR_RootConstrainSelectedInstOperands, |
| 5137 | // GIR_Coverage, 1051, |
| 5138 | GIR_EraseRootFromParent_Done, |
| 5139 | // Label 508: @12078 |
| 5140 | GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(12110), // Rule ID 1052 // |
| 5141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5142 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstrihr), |
| 5143 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5146 | // (intrinsic_wo_chain:{ *:[v8i16] } 9801:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VSTRIHR:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) |
| 5147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIHR), |
| 5148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] |
| 5149 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5150 | GIR_RootConstrainSelectedInstOperands, |
| 5151 | // GIR_Coverage, 1052, |
| 5152 | GIR_EraseRootFromParent_Done, |
| 5153 | // Label 509: @12110 |
| 5154 | GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(12142), // Rule ID 1053 // |
| 5155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5156 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vstrihl), |
| 5157 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5158 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5160 | // (intrinsic_wo_chain:{ *:[v8i16] } 9799:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VSTRIHL:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) |
| 5161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSTRIHL), |
| 5162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VT] |
| 5163 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5164 | GIR_RootConstrainSelectedInstOperands, |
| 5165 | // GIR_Coverage, 1053, |
| 5166 | GIR_EraseRootFromParent_Done, |
| 5167 | // Label 510: @12142 |
| 5168 | GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(12174), // Rule ID 1070 // |
| 5169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5170 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractbm), |
| 5171 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5172 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 5174 | // (intrinsic_wo_chain:{ *:[i32] } 9664:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXTRACTBM:{ *:[i32] } v16i8:{ *:[v16i8] }:$VB) |
| 5175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTBM), |
| 5176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5177 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5178 | GIR_RootConstrainSelectedInstOperands, |
| 5179 | // GIR_Coverage, 1070, |
| 5180 | GIR_EraseRootFromParent_Done, |
| 5181 | // Label 511: @12174 |
| 5182 | GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(12206), // Rule ID 1071 // |
| 5183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5184 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextracthm), |
| 5185 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 5188 | // (intrinsic_wo_chain:{ *:[i32] } 9666:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXTRACTHM:{ *:[i32] } v8i16:{ *:[v8i16] }:$VB) |
| 5189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTHM), |
| 5190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5191 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5192 | GIR_RootConstrainSelectedInstOperands, |
| 5193 | // GIR_Coverage, 1071, |
| 5194 | GIR_EraseRootFromParent_Done, |
| 5195 | // Label 512: @12206 |
| 5196 | GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(12238), // Rule ID 1072 // |
| 5197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5198 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractwm), |
| 5199 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5200 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 5202 | // (intrinsic_wo_chain:{ *:[i32] } 9668:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXTRACTWM:{ *:[i32] } v4i32:{ *:[v4i32] }:$VB) |
| 5203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTWM), |
| 5204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5205 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5206 | GIR_RootConstrainSelectedInstOperands, |
| 5207 | // GIR_Coverage, 1072, |
| 5208 | GIR_EraseRootFromParent_Done, |
| 5209 | // Label 513: @12238 |
| 5210 | GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(12270), // Rule ID 1073 // |
| 5211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5212 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractdm), |
| 5213 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5214 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 5216 | // (intrinsic_wo_chain:{ *:[i32] } 9665:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXTRACTDM:{ *:[i32] } v2i64:{ *:[v2i64] }:$VB) |
| 5217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTDM), |
| 5218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5219 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5220 | GIR_RootConstrainSelectedInstOperands, |
| 5221 | // GIR_Coverage, 1073, |
| 5222 | GIR_EraseRootFromParent_Done, |
| 5223 | // Label 514: @12270 |
| 5224 | GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(12302), // Rule ID 1074 // |
| 5225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5226 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextractqm), |
| 5227 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5228 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 5230 | // (intrinsic_wo_chain:{ *:[i32] } 9667:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VEXTRACTQM:{ *:[i32] } v1i128:{ *:[v1i128] }:$VB) |
| 5231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTRACTQM), |
| 5232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5233 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5234 | GIR_RootConstrainSelectedInstOperands, |
| 5235 | // GIR_Coverage, 1074, |
| 5236 | GIR_EraseRootFromParent_Done, |
| 5237 | // Label 515: @12302 |
| 5238 | GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(12334), // Rule ID 1075 // |
| 5239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5240 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandbm), |
| 5241 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5242 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5244 | // (intrinsic_wo_chain:{ *:[v16i8] } 9650:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB) => (VEXPANDBM:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 5245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDBM), |
| 5246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5247 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5248 | GIR_RootConstrainSelectedInstOperands, |
| 5249 | // GIR_Coverage, 1075, |
| 5250 | GIR_EraseRootFromParent_Done, |
| 5251 | // Label 516: @12334 |
| 5252 | GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(12366), // Rule ID 1076 // |
| 5253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5254 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandhm), |
| 5255 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5256 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5257 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5258 | // (intrinsic_wo_chain:{ *:[v8i16] } 9652:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB) => (VEXPANDHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) |
| 5259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDHM), |
| 5260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5261 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5262 | GIR_RootConstrainSelectedInstOperands, |
| 5263 | // GIR_Coverage, 1076, |
| 5264 | GIR_EraseRootFromParent_Done, |
| 5265 | // Label 517: @12366 |
| 5266 | GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(12398), // Rule ID 1077 // |
| 5267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5268 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandwm), |
| 5269 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5270 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5272 | // (intrinsic_wo_chain:{ *:[v4i32] } 9654:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (VEXPANDWM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) |
| 5273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDWM), |
| 5274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5275 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5276 | GIR_RootConstrainSelectedInstOperands, |
| 5277 | // GIR_Coverage, 1077, |
| 5278 | GIR_EraseRootFromParent_Done, |
| 5279 | // Label 518: @12398 |
| 5280 | GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(12430), // Rule ID 1078 // |
| 5281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpanddm), |
| 5283 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5286 | // (intrinsic_wo_chain:{ *:[v2i64] } 9651:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXPANDDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) |
| 5287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDDM), |
| 5288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5289 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5290 | GIR_RootConstrainSelectedInstOperands, |
| 5291 | // GIR_Coverage, 1078, |
| 5292 | GIR_EraseRootFromParent_Done, |
| 5293 | // Label 519: @12430 |
| 5294 | GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(12462), // Rule ID 1079 // |
| 5295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5296 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vexpandqm), |
| 5297 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5300 | // (intrinsic_wo_chain:{ *:[v1i128] } 9653:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB) => (VEXPANDQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VB) |
| 5301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXPANDQM), |
| 5302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5303 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5304 | GIR_RootConstrainSelectedInstOperands, |
| 5305 | // GIR_Coverage, 1079, |
| 5306 | GIR_EraseRootFromParent_Done, |
| 5307 | // Label 520: @12462 |
| 5308 | GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(12494), // Rule ID 1080 // |
| 5309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5310 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrbm), |
| 5311 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5314 | // (intrinsic_wo_chain:{ *:[v16i8] } 9548:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRBM:{ *:[v16i8] } i64:{ *:[i64] }:$VB) |
| 5315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRBM), |
| 5316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5317 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5318 | GIR_RootConstrainSelectedInstOperands, |
| 5319 | // GIR_Coverage, 1080, |
| 5320 | GIR_EraseRootFromParent_Done, |
| 5321 | // Label 521: @12494 |
| 5322 | GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(12526), // Rule ID 1081 // |
| 5323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5324 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrhm), |
| 5325 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5326 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5328 | // (intrinsic_wo_chain:{ *:[v8i16] } 9550:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRHM:{ *:[v8i16] } i64:{ *:[i64] }:$VB) |
| 5329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRHM), |
| 5330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5331 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5332 | GIR_RootConstrainSelectedInstOperands, |
| 5333 | // GIR_Coverage, 1081, |
| 5334 | GIR_EraseRootFromParent_Done, |
| 5335 | // Label 522: @12526 |
| 5336 | GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(12558), // Rule ID 1082 // |
| 5337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5338 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrwm), |
| 5339 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5340 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5342 | // (intrinsic_wo_chain:{ *:[v4i32] } 9552:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRWM:{ *:[v4i32] } i64:{ *:[i64] }:$VB) |
| 5343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRWM), |
| 5344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5345 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5346 | GIR_RootConstrainSelectedInstOperands, |
| 5347 | // GIR_Coverage, 1082, |
| 5348 | GIR_EraseRootFromParent_Done, |
| 5349 | // Label 523: @12558 |
| 5350 | GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(12590), // Rule ID 1083 // |
| 5351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5352 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrdm), |
| 5353 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5356 | // (intrinsic_wo_chain:{ *:[v2i64] } 9549:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRDM:{ *:[v2i64] } i64:{ *:[i64] }:$VB) |
| 5357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRDM), |
| 5358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5359 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5360 | GIR_RootConstrainSelectedInstOperands, |
| 5361 | // GIR_Coverage, 1083, |
| 5362 | GIR_EraseRootFromParent_Done, |
| 5363 | // Label 524: @12590 |
| 5364 | GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(12622), // Rule ID 1084 // |
| 5365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mtvsrqm), |
| 5367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5370 | // (intrinsic_wo_chain:{ *:[v1i128] } 9551:{ *:[iPTR] }, i64:{ *:[i64] }:$VB) => (MTVSRQM:{ *:[v1i128] } i64:{ *:[i64] }:$VB) |
| 5371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSRQM), |
| 5372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5373 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5374 | GIR_RootConstrainSelectedInstOperands, |
| 5375 | // GIR_Coverage, 1084, |
| 5376 | GIR_EraseRootFromParent_Done, |
| 5377 | // Label 525: @12622 |
| 5378 | GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(12654), // Rule ID 1148 // |
| 5379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 5380 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextsd2q), |
| 5381 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5382 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5384 | // (intrinsic_wo_chain:{ *:[v1i128] } 9671:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB) => (VEXTSD2Q:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VB) |
| 5385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTSD2Q), |
| 5386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 5387 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 5388 | GIR_RootConstrainSelectedInstOperands, |
| 5389 | // GIR_Coverage, 1148, |
| 5390 | GIR_EraseRootFromParent_Done, |
| 5391 | // Label 526: @12654 |
| 5392 | GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(12686), // Rule ID 1153 // |
| 5393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 5394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxmfacc), |
| 5395 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 5396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 5397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 5398 | // (intrinsic_wo_chain:{ *:[v512i1] } 9992:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$AT) => (XXMFACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$AT) |
| 5399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXMFACC), |
| 5400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[ATo] |
| 5401 | GIR_RootToRootCopy, /*OpIdx*/2, // AT |
| 5402 | GIR_RootConstrainSelectedInstOperands, |
| 5403 | // GIR_Coverage, 1153, |
| 5404 | GIR_EraseRootFromParent_Done, |
| 5405 | // Label 527: @12686 |
| 5406 | GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(12718), // Rule ID 1154 // |
| 5407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 5408 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xxmtacc), |
| 5409 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 5410 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 5411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 5412 | // (intrinsic_wo_chain:{ *:[v512i1] } 9993:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi) => (XXMTACC:{ *:[v512i1] } v512i1:{ *:[v512i1] }:$ATi) |
| 5413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXMTACC), |
| 5414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 5415 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 5416 | GIR_RootConstrainSelectedInstOperands, |
| 5417 | // GIR_Coverage, 1154, |
| 5418 | GIR_EraseRootFromParent_Done, |
| 5419 | // Label 528: @12718 |
| 5420 | GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(12747), // Rule ID 1269 // |
| 5421 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fre), |
| 5422 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5423 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 5425 | // (intrinsic_wo_chain:{ *:[f64] } 9899:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FRE:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRE), |
| 5427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5428 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5429 | GIR_RootConstrainSelectedInstOperands, |
| 5430 | // GIR_Coverage, 1269, |
| 5431 | GIR_EraseRootFromParent_Done, |
| 5432 | // Label 529: @12747 |
| 5433 | GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(12776), // Rule ID 1270 // |
| 5434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fres), |
| 5435 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 5438 | // (intrinsic_wo_chain:{ *:[f32] } 9900:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (FRES:{ *:[f32] } ?:{ *:[f32] }:$A) |
| 5439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FRES), |
| 5440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5441 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5442 | GIR_RootConstrainSelectedInstOperands, |
| 5443 | // GIR_Coverage, 1270, |
| 5444 | GIR_EraseRootFromParent_Done, |
| 5445 | // Label 530: @12776 |
| 5446 | GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(12805), // Rule ID 1271 // |
| 5447 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabs), |
| 5448 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5449 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 5451 | // (intrinsic_wo_chain:{ *:[f64] } 9894:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FNABSD:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSD), |
| 5453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5454 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5455 | GIR_RootConstrainSelectedInstOperands, |
| 5456 | // GIR_Coverage, 1271, |
| 5457 | GIR_EraseRootFromParent_Done, |
| 5458 | // Label 531: @12805 |
| 5459 | GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(12834), // Rule ID 1272 // |
| 5460 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnabss), |
| 5461 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 5462 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 5464 | // (intrinsic_wo_chain:{ *:[f32] } 9895:{ *:[iPTR] }, f32:{ *:[f32] }:$A) => (FNABSS:{ *:[f32] } ?:{ *:[f32] }:$A) |
| 5465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSS), |
| 5466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5467 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5468 | GIR_RootConstrainSelectedInstOperands, |
| 5469 | // GIR_Coverage, 1272, |
| 5470 | GIR_EraseRootFromParent_Done, |
| 5471 | // Label 532: @12834 |
| 5472 | GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(12906), // Rule ID 3340 // |
| 5473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), |
| 5474 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvspbf16), |
| 5475 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5476 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5478 | // (intrinsic_wo_chain:{ *:[v16i8] } 10091:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XVCVSPBF16:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 5479 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5480 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 5481 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5482 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5483 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 5484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVCVSPBF16), |
| 5486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5487 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5488 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5491 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5492 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 5493 | // GIR_Coverage, 3340, |
| 5494 | GIR_EraseRootFromParent_Done, |
| 5495 | // Label 533: @12906 |
| 5496 | GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(12978), // Rule ID 3341 // |
| 5497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), |
| 5498 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcvbf16spn), |
| 5499 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5500 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5502 | // (intrinsic_wo_chain:{ *:[v16i8] } 10086:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XVCVBF16SPN:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 5503 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5504 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 5505 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5506 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5507 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 5508 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5509 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVCVBF16SPN), |
| 5510 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5511 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5515 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5516 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 5517 | // GIR_Coverage, 3341, |
| 5518 | GIR_EraseRootFromParent_Done, |
| 5519 | // Label 534: @12978 |
| 5520 | GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(13007), // Rule ID 4839 // |
| 5521 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fcfid), |
| 5522 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5525 | // (intrinsic_wo_chain:{ *:[f64] } 9881:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVSXDDP:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSXDDP), |
| 5527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5528 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5529 | GIR_RootConstrainSelectedInstOperands, |
| 5530 | // GIR_Coverage, 4839, |
| 5531 | GIR_EraseRootFromParent_Done, |
| 5532 | // Label 535: @13007 |
| 5533 | GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(13036), // Rule ID 4840 // |
| 5534 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fcfud), |
| 5535 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5538 | // (intrinsic_wo_chain:{ *:[f64] } 9882:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVUXDDP:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUXDDP), |
| 5540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5541 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5542 | GIR_RootConstrainSelectedInstOperands, |
| 5543 | // GIR_Coverage, 4840, |
| 5544 | GIR_EraseRootFromParent_Done, |
| 5545 | // Label 536: @13036 |
| 5546 | GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(13065), // Rule ID 4841 // |
| 5547 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctid), |
| 5548 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5549 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 5551 | // (intrinsic_wo_chain:{ *:[f64] } 9883:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FCTID:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 5553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5554 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5555 | GIR_RootConstrainSelectedInstOperands, |
| 5556 | // GIR_Coverage, 4841, |
| 5557 | GIR_EraseRootFromParent_Done, |
| 5558 | // Label 537: @13065 |
| 5559 | GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(13094), // Rule ID 4842 // |
| 5560 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctidz), |
| 5561 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5562 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5564 | // (intrinsic_wo_chain:{ *:[f64] } 9884:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPSXDS:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSXDS), |
| 5566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5567 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5568 | GIR_RootConstrainSelectedInstOperands, |
| 5569 | // GIR_Coverage, 4842, |
| 5570 | GIR_EraseRootFromParent_Done, |
| 5571 | // Label 538: @13094 |
| 5572 | GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(13123), // Rule ID 4843 // |
| 5573 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctiw), |
| 5574 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 5577 | // (intrinsic_wo_chain:{ *:[f64] } 9885:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (FCTIW:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCTIW), |
| 5579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5580 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5581 | GIR_RootConstrainSelectedInstOperands, |
| 5582 | // GIR_Coverage, 4843, |
| 5583 | GIR_EraseRootFromParent_Done, |
| 5584 | // Label 539: @13123 |
| 5585 | GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(13152), // Rule ID 4844 // |
| 5586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctiwz), |
| 5587 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5590 | // (intrinsic_wo_chain:{ *:[f64] } 9886:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPSXWS:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPSXWS), |
| 5592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5593 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5594 | GIR_RootConstrainSelectedInstOperands, |
| 5595 | // GIR_Coverage, 4844, |
| 5596 | GIR_EraseRootFromParent_Done, |
| 5597 | // Label 540: @13152 |
| 5598 | GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(13181), // Rule ID 4845 // |
| 5599 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctudz), |
| 5600 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5601 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5603 | // (intrinsic_wo_chain:{ *:[f64] } 9887:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPUXDS:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPUXDS), |
| 5605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5606 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5607 | GIR_RootConstrainSelectedInstOperands, |
| 5608 | // GIR_Coverage, 4845, |
| 5609 | GIR_EraseRootFromParent_Done, |
| 5610 | // Label 541: @13181 |
| 5611 | GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(13210), // Rule ID 4846 // |
| 5612 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fctuwz), |
| 5613 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5614 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5616 | // (intrinsic_wo_chain:{ *:[f64] } 9888:{ *:[iPTR] }, f64:{ *:[f64] }:$A) => (XSCVDPUXWS:{ *:[f64] } ?:{ *:[f64] }:$A) |
| 5617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPUXWS), |
| 5618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5619 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5620 | GIR_RootConstrainSelectedInstOperands, |
| 5621 | // GIR_Coverage, 4846, |
| 5622 | GIR_EraseRootFromParent_Done, |
| 5623 | // Label 542: @13210 |
| 5624 | GIM_Reject, |
| 5625 | // Label 440: @13211 |
| 5626 | GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(21409), |
| 5627 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 5628 | GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(13290), // Rule ID 2154 // |
| 5629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5630 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxextractuw), |
| 5631 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 5634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5635 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5636 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 5637 | // MIs[1] Operand 1 |
| 5638 | // No operand predicates |
| 5639 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5640 | // (intrinsic_wo_chain:{ *:[v2i64] } 10130:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$A, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXEXTRACTUW:{ *:[f64] } ?:{ *:[v2i64] }:$A, (imm:{ *:[i32] }):$IMM), VSRC:{ *:[i32] }) |
| 5641 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 5642 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXEXTRACTUW), |
| 5643 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5644 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 5645 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM |
| 5646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 5649 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5650 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 5651 | // GIR_Coverage, 2154, |
| 5652 | GIR_EraseRootFromParent_Done, |
| 5653 | // Label 544: @13290 |
| 5654 | GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(13327), // Rule ID 1023 // |
| 5655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5656 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtstdcsp), |
| 5657 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5660 | // MIs[0] DCMX |
| 5661 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5662 | // (intrinsic_wo_chain:{ *:[v4i32] } 10120:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCSP:{ *:[v4i32] } (timm:{ *:[i32] }):$DCMX, v4f32:{ *:[v4f32] }:$XB) |
| 5663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVTSTDCSP), |
| 5664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5665 | GIR_RootToRootCopy, /*OpIdx*/3, // DCMX |
| 5666 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 5667 | GIR_RootConstrainSelectedInstOperands, |
| 5668 | // GIR_Coverage, 1023, |
| 5669 | GIR_EraseRootFromParent_Done, |
| 5670 | // Label 545: @13327 |
| 5671 | GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(13364), // Rule ID 1024 // |
| 5672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5673 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtstdcdp), |
| 5674 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5675 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5677 | // MIs[0] DCMX |
| 5678 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5679 | // (intrinsic_wo_chain:{ *:[v2i64] } 10119:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XB, (timm:{ *:[i32] }):$DCMX) => (XVTSTDCDP:{ *:[v2i64] } (timm:{ *:[i32] }):$DCMX, v2f64:{ *:[v2f64] }:$XB) |
| 5680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVTSTDCDP), |
| 5681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5682 | GIR_RootToRootCopy, /*OpIdx*/3, // DCMX |
| 5683 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 5684 | GIR_RootConstrainSelectedInstOperands, |
| 5685 | // GIR_Coverage, 1024, |
| 5686 | GIR_EraseRootFromParent_Done, |
| 5687 | // Label 546: @13364 |
| 5688 | GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(13409), // Rule ID 892 // |
| 5689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5690 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xsmaxdp), |
| 5691 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5692 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5693 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 5694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5696 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5697 | // (intrinsic_wo_chain:{ *:[f64] } 10072:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMAXDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) |
| 5698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP), |
| 5699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5700 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5701 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5702 | GIR_RootConstrainSelectedInstOperands, |
| 5703 | // GIR_Coverage, 892, |
| 5704 | GIR_EraseRootFromParent_Done, |
| 5705 | // Label 547: @13409 |
| 5706 | GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(13454), // Rule ID 893 // |
| 5707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5708 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xsmindp), |
| 5709 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 5710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 5712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5713 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5714 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 5715 | // (intrinsic_wo_chain:{ *:[f64] } 10073:{ *:[iPTR] }, vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) => (XSMINDP:{ *:[f64] } vsfrc:{ *:[f64] }:$XA, vsfrc:{ *:[f64] }:$XB) |
| 5716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMINDP), |
| 5717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5718 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5719 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5720 | GIR_RootConstrainSelectedInstOperands, |
| 5721 | // GIR_Coverage, 893, |
| 5722 | GIR_EraseRootFromParent_Done, |
| 5723 | // Label 548: @13454 |
| 5724 | GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(13499), // Rule ID 894 // |
| 5725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5726 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmaxdp), |
| 5727 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5728 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5729 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 5730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5731 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5732 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5733 | // (intrinsic_wo_chain:{ *:[v2f64] } 10104:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMAXDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) |
| 5734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMAXDP), |
| 5735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5736 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5737 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5738 | GIR_RootConstrainSelectedInstOperands, |
| 5739 | // GIR_Coverage, 894, |
| 5740 | GIR_EraseRootFromParent_Done, |
| 5741 | // Label 549: @13499 |
| 5742 | GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(13544), // Rule ID 895 // |
| 5743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5744 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmindp), |
| 5745 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5746 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5747 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 5748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5749 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5750 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5751 | // (intrinsic_wo_chain:{ *:[v2f64] } 10106:{ *:[iPTR] }, vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) => (XVMINDP:{ *:[v2f64] } vsrc:{ *:[v2f64] }:$XA, vsrc:{ *:[v2f64] }:$XB) |
| 5752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMINDP), |
| 5753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5754 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5755 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5756 | GIR_RootConstrainSelectedInstOperands, |
| 5757 | // GIR_Coverage, 895, |
| 5758 | GIR_EraseRootFromParent_Done, |
| 5759 | // Label 550: @13544 |
| 5760 | GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(13589), // Rule ID 896 // |
| 5761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5762 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvmaxsp), |
| 5763 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5765 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5767 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5768 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5769 | // (intrinsic_wo_chain:{ *:[v4f32] } 10105:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMAXSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) |
| 5770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMAXSP), |
| 5771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5772 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5773 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5774 | GIR_RootConstrainSelectedInstOperands, |
| 5775 | // GIR_Coverage, 896, |
| 5776 | GIR_EraseRootFromParent_Done, |
| 5777 | // Label 551: @13589 |
| 5778 | GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(13634), // Rule ID 897 // |
| 5779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5780 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvminsp), |
| 5781 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5783 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5785 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5786 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5787 | // (intrinsic_wo_chain:{ *:[v4f32] } 10107:{ *:[iPTR] }, vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) => (XVMINSP:{ *:[v4f32] } vsrc:{ *:[v4f32] }:$XA, vsrc:{ *:[v4f32] }:$XB) |
| 5788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMINSP), |
| 5789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5790 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5791 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5792 | GIR_RootConstrainSelectedInstOperands, |
| 5793 | // GIR_Coverage, 897, |
| 5794 | GIR_EraseRootFromParent_Done, |
| 5795 | // Label 552: @13634 |
| 5796 | GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(13671), // Rule ID 821 // |
| 5797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5798 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpeqdp), |
| 5799 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 5802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5803 | // (intrinsic_wo_chain:{ *:[v2i64] } 10074:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPEQDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 5804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPEQDP), |
| 5805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5806 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5807 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5808 | GIR_RootConstrainSelectedInstOperands, |
| 5809 | // GIR_Coverage, 821, |
| 5810 | GIR_EraseRootFromParent_Done, |
| 5811 | // Label 553: @13671 |
| 5812 | GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(13708), // Rule ID 823 // |
| 5813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5814 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpeqsp), |
| 5815 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5817 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5819 | // (intrinsic_wo_chain:{ *:[v4i32] } 10076:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPEQSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 5820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPEQSP), |
| 5821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5822 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5823 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5824 | GIR_RootConstrainSelectedInstOperands, |
| 5825 | // GIR_Coverage, 823, |
| 5826 | GIR_EraseRootFromParent_Done, |
| 5827 | // Label 554: @13708 |
| 5828 | GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(13745), // Rule ID 825 // |
| 5829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5830 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgedp), |
| 5831 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5832 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5833 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 5834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5835 | // (intrinsic_wo_chain:{ *:[v2i64] } 10078:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGEDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 5836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGEDP), |
| 5837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5838 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5839 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5840 | GIR_RootConstrainSelectedInstOperands, |
| 5841 | // GIR_Coverage, 825, |
| 5842 | GIR_EraseRootFromParent_Done, |
| 5843 | // Label 555: @13745 |
| 5844 | GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(13782), // Rule ID 827 // |
| 5845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5846 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgesp), |
| 5847 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5848 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5849 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5851 | // (intrinsic_wo_chain:{ *:[v4i32] } 10080:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGESP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 5852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGESP), |
| 5853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5854 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5855 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5856 | GIR_RootConstrainSelectedInstOperands, |
| 5857 | // GIR_Coverage, 827, |
| 5858 | GIR_EraseRootFromParent_Done, |
| 5859 | // Label 556: @13782 |
| 5860 | GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(13819), // Rule ID 829 // |
| 5861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5862 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgtdp), |
| 5863 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5865 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 5866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5867 | // (intrinsic_wo_chain:{ *:[v2i64] } 10082:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVCMPGTDP:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 5868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGTDP), |
| 5869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5870 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5871 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5872 | GIR_RootConstrainSelectedInstOperands, |
| 5873 | // GIR_Coverage, 829, |
| 5874 | GIR_EraseRootFromParent_Done, |
| 5875 | // Label 557: @13819 |
| 5876 | GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(13856), // Rule ID 831 // |
| 5877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvcmpgtsp), |
| 5879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5883 | // (intrinsic_wo_chain:{ *:[v4i32] } 10084:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVCMPGTSP:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 5884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCMPGTSP), |
| 5885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5886 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5887 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5888 | GIR_RootConstrainSelectedInstOperands, |
| 5889 | // GIR_Coverage, 831, |
| 5890 | GIR_EraseRootFromParent_Done, |
| 5891 | // Label 558: @13856 |
| 5892 | GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(13893), // Rule ID 995 // |
| 5893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5894 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addf128_round_to_odd), |
| 5895 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5897 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 5898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5899 | // (intrinsic_wo_chain:{ *:[f128] } 9519:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 5900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSADDQPO), |
| 5901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5902 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 5903 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 5904 | GIR_RootConstrainSelectedInstOperands, |
| 5905 | // GIR_Coverage, 995, |
| 5906 | GIR_EraseRootFromParent_Done, |
| 5907 | // Label 559: @13893 |
| 5908 | GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(13930), // Rule ID 996 // |
| 5909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5910 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulf128_round_to_odd), |
| 5911 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5913 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 5914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5915 | // (intrinsic_wo_chain:{ *:[f128] } 10001:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 5916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMULQPO), |
| 5917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5918 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 5919 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 5920 | GIR_RootConstrainSelectedInstOperands, |
| 5921 | // GIR_Coverage, 996, |
| 5922 | GIR_EraseRootFromParent_Done, |
| 5923 | // Label 560: @13930 |
| 5924 | GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(13967), // Rule ID 997 // |
| 5925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5926 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_subf128_round_to_odd), |
| 5927 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5928 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5929 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 5930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5931 | // (intrinsic_wo_chain:{ *:[f128] } 10032:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 5932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSSUBQPO), |
| 5933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5934 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 5935 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 5936 | GIR_RootConstrainSelectedInstOperands, |
| 5937 | // GIR_Coverage, 997, |
| 5938 | GIR_EraseRootFromParent_Done, |
| 5939 | // Label 561: @13967 |
| 5940 | GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(14004), // Rule ID 998 // |
| 5941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5942 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divf128_round_to_odd), |
| 5943 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 5944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 5945 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 5946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 5947 | // (intrinsic_wo_chain:{ *:[f128] } 9875:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQPO:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 5948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSDIVQPO), |
| 5949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 5950 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 5951 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 5952 | GIR_RootConstrainSelectedInstOperands, |
| 5953 | // GIR_Coverage, 998, |
| 5954 | GIR_EraseRootFromParent_Done, |
| 5955 | // Label 562: @14004 |
| 5956 | GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(14041), // Rule ID 1017 // |
| 5957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5958 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xviexpdp), |
| 5959 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 5962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5963 | // (intrinsic_wo_chain:{ *:[v2f64] } 10102:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) => (XVIEXPDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB) |
| 5964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVIEXPDP), |
| 5965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5966 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5967 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5968 | GIR_RootConstrainSelectedInstOperands, |
| 5969 | // GIR_Coverage, 1017, |
| 5970 | GIR_EraseRootFromParent_Done, |
| 5971 | // Label 563: @14041 |
| 5972 | GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(14078), // Rule ID 1018 // |
| 5973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 5974 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xviexpsp), |
| 5975 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5979 | // (intrinsic_wo_chain:{ *:[v4f32] } 10103:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) => (XVIEXPSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XA, v4i32:{ *:[v4i32] }:$XB) |
| 5980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVIEXPSP), |
| 5981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5982 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 5983 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 5984 | GIR_RootConstrainSelectedInstOperands, |
| 5985 | // GIR_Coverage, 1018, |
| 5986 | GIR_EraseRootFromParent_Done, |
| 5987 | // Label 564: @14078 |
| 5988 | GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(14115), // Rule ID 1641 // |
| 5989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 5990 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvdivsp), |
| 5991 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5992 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5993 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 5994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 5995 | // (intrinsic_wo_chain:{ *:[v4f32] } 10101:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B) => (XVDIVSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B) |
| 5996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP), |
| 5997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 5998 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 5999 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 6000 | GIR_RootConstrainSelectedInstOperands, |
| 6001 | // GIR_Coverage, 1641, |
| 6002 | GIR_EraseRootFromParent_Done, |
| 6003 | // Label 565: @14115 |
| 6004 | GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(14152), // Rule ID 1642 // |
| 6005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 6006 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvdivdp), |
| 6007 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6009 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 6011 | // (intrinsic_wo_chain:{ *:[v2f64] } 10100:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A, v2f64:{ *:[v2f64] }:$B) => (XVDIVDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$A, ?:{ *:[v2f64] }:$B) |
| 6012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP), |
| 6013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 6014 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 6015 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 6016 | GIR_RootConstrainSelectedInstOperands, |
| 6017 | // GIR_Coverage, 1642, |
| 6018 | GIR_EraseRootFromParent_Done, |
| 6019 | // Label 566: @14152 |
| 6020 | GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(14214), // Rule ID 1643 // |
| 6021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 6022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtdivdp), |
| 6023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6027 | // (intrinsic_wo_chain:{ *:[i32] } 10114:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$A, v2f64:{ *:[v2f64] }:$B) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTDIVDP:{ *:[i32] } ?:{ *:[v2f64] }:$A, ?:{ *:[v2f64] }:$B), GPRC:{ *:[i32] }) |
| 6028 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6029 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTDIVDP), |
| 6030 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6031 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 6032 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B |
| 6033 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6036 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6037 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 6038 | // GIR_Coverage, 1643, |
| 6039 | GIR_EraseRootFromParent_Done, |
| 6040 | // Label 567: @14214 |
| 6041 | GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(14276), // Rule ID 1644 // |
| 6042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 6043 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtdivsp), |
| 6044 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6045 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6046 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6048 | // (intrinsic_wo_chain:{ *:[i32] } 10115:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B) => (COPY_TO_REGCLASS:{ *:[i32] } (XVTDIVSP:{ *:[i32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B), GPRC:{ *:[i32] }) |
| 6049 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6050 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTDIVSP), |
| 6051 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6052 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 6053 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B |
| 6054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6057 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6058 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 6059 | // GIR_Coverage, 1644, |
| 6060 | GIR_EraseRootFromParent_Done, |
| 6061 | // Label 568: @14276 |
| 6062 | GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(14313), // Rule ID 1888 // |
| 6063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 6064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxleqv), |
| 6065 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6066 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6067 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 6069 | // (intrinsic_wo_chain:{ *:[v4i32] } 10136:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B) => (XXLEQV:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B) |
| 6070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXLEQV), |
| 6071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 6072 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 6073 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 6074 | GIR_RootConstrainSelectedInstOperands, |
| 6075 | // GIR_Coverage, 1888, |
| 6076 | GIR_EraseRootFromParent_Done, |
| 6077 | // Label 569: @14313 |
| 6078 | GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(14392), // Rule ID 1926 // |
| 6079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 6080 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_insert_exp), |
| 6081 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6082 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6083 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 6085 | // (intrinsic_wo_chain:{ *:[f64] } 9910:{ *:[iPTR] }, f64:{ *:[f64] }:$A, i64:{ *:[i64] }:$B) => (COPY_TO_REGCLASS:{ *:[f64] } (XSIEXPDP:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[i64] } ?:{ *:[f64] }:$A, G8RC:{ *:[i32] }), ?:{ *:[i64] }:$B), F8RC:{ *:[i32] }) |
| 6086 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6087 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 6088 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6089 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6090 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 6091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6092 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSIEXPDP), |
| 6093 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6094 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6095 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // B |
| 6096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6098 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6099 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6100 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID), |
| 6101 | // GIR_Coverage, 1926, |
| 6102 | GIR_EraseRootFromParent_Done, |
| 6103 | // Label 570: @14392 |
| 6104 | GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(14448), // Rule ID 2151 // |
| 6105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 6106 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_scalar_insert_exp_qp), |
| 6107 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 6108 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 6109 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6111 | // (intrinsic_wo_chain:{ *:[f128] } 10015:{ *:[iPTR] }, f128:{ *:[f128] }:$vA, i64:{ *:[i64] }:$vB) => (XSIEXPQP:{ *:[f128] } ?:{ *:[f128] }:$vA, (MTVSRD:{ *:[f64] } ?:{ *:[i64] }:$vB)) |
| 6112 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 6113 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRD), |
| 6114 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6115 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vB |
| 6116 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSIEXPQP), |
| 6118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 6119 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 6120 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6121 | GIR_RootConstrainSelectedInstOperands, |
| 6122 | // GIR_Coverage, 2151, |
| 6123 | GIR_EraseRootFromParent_Done, |
| 6124 | // Label 571: @14448 |
| 6125 | GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(14536), // Rule ID 3330 // |
| 6126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6127 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtlsbb), |
| 6128 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6129 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6130 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 6132 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 6133 | // (intrinsic_wo_chain:{ *:[i32] } 10116:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XB, 1:{ *:[i32] }) => (EXTRACT_SUBREG:{ *:[i32] } (XVTLSBB:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })), sub_lt:{ *:[i32] }) |
| 6134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6135 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 6136 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6137 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6138 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XB |
| 6139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTLSBB), |
| 6141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6142 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6146 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 6147 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 6148 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 6149 | // GIR_Coverage, 3330, |
| 6150 | GIR_EraseRootFromParent_Done, |
| 6151 | // Label 572: @14536 |
| 6152 | GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(14624), // Rule ID 3331 // |
| 6153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6154 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xvtlsbb), |
| 6155 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6157 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 6159 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 6160 | // (intrinsic_wo_chain:{ *:[i32] } 10116:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XB, 0:{ *:[i32] }) => (EXTRACT_SUBREG:{ *:[i32] } (XVTLSBB:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })), sub_eq:{ *:[i32] }) |
| 6161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6162 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 6163 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6164 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6165 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // XB |
| 6166 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6167 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XVTLSBB), |
| 6168 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6169 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6173 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 6174 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 6175 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 6176 | // GIR_Coverage, 3331, |
| 6177 | GIR_EraseRootFromParent_Done, |
| 6178 | // Label 573: @14624 |
| 6179 | GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(14667), // Rule ID 314 // |
| 6180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6181 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfsx), |
| 6182 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6183 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6185 | // MIs[0] Operand 3 |
| 6186 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 6187 | // (intrinsic_wo_chain:{ *:[v4f32] } 9579:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, 0:{ *:[i32] }) => (VCFSX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$VB) |
| 6188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFSX_0), |
| 6189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6190 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6191 | GIR_RootConstrainSelectedInstOperands, |
| 6192 | // GIR_Coverage, 314, |
| 6193 | GIR_EraseRootFromParent_Done, |
| 6194 | // Label 574: @14667 |
| 6195 | GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(14710), // Rule ID 315 // |
| 6196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6197 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctuxs), |
| 6198 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6199 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6201 | // MIs[0] Operand 3 |
| 6202 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 6203 | // (intrinsic_wo_chain:{ *:[v4i32] } 9641:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, 0:{ *:[i32] }) => (VCTUXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$VB) |
| 6204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTUXS_0), |
| 6205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6206 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6207 | GIR_RootConstrainSelectedInstOperands, |
| 6208 | // GIR_Coverage, 315, |
| 6209 | GIR_EraseRootFromParent_Done, |
| 6210 | // Label 575: @14710 |
| 6211 | GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(14753), // Rule ID 316 // |
| 6212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfux), |
| 6214 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6215 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6217 | // MIs[0] Operand 3 |
| 6218 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 6219 | // (intrinsic_wo_chain:{ *:[v4f32] } 9581:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, 0:{ *:[i32] }) => (VCFUX_0:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$VB) |
| 6220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUX_0), |
| 6221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6222 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6223 | GIR_RootConstrainSelectedInstOperands, |
| 6224 | // GIR_Coverage, 316, |
| 6225 | GIR_EraseRootFromParent_Done, |
| 6226 | // Label 576: @14753 |
| 6227 | GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(14796), // Rule ID 317 // |
| 6228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6229 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctsxs), |
| 6230 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6233 | // MIs[0] Operand 3 |
| 6234 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 6235 | // (intrinsic_wo_chain:{ *:[v4i32] } 9640:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, 0:{ *:[i32] }) => (VCTSXS_0:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$VB) |
| 6236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTSXS_0), |
| 6237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6238 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6239 | GIR_RootConstrainSelectedInstOperands, |
| 6240 | // GIR_Coverage, 317, |
| 6241 | GIR_EraseRootFromParent_Done, |
| 6242 | // Label 577: @14796 |
| 6243 | GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(14867), // Rule ID 3326 // |
| 6244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6245 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvbm), |
| 6246 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6247 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6248 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6250 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6251 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6252 | // MIs[1] Operand 1 |
| 6253 | // No operand predicates |
| 6254 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6255 | // (intrinsic_wo_chain:{ *:[v16i8] } 10131:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXGENPCVBM:{ *:[v4i32] } ?:{ *:[v16i8] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) |
| 6256 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6257 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVBM), |
| 6258 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6259 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 6260 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM |
| 6261 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6264 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6265 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 6266 | // GIR_Coverage, 3326, |
| 6267 | GIR_EraseRootFromParent_Done, |
| 6268 | // Label 578: @14867 |
| 6269 | GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(14938), // Rule ID 3327 // |
| 6270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6271 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvhm), |
| 6272 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6273 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6274 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6276 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6277 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6278 | // MIs[1] Operand 1 |
| 6279 | // No operand predicates |
| 6280 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6281 | // (intrinsic_wo_chain:{ *:[v8i16] } 10133:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXGENPCVHM:{ *:[v4i32] } ?:{ *:[v8i16] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) |
| 6282 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6283 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVHM), |
| 6284 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6285 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 6286 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM |
| 6287 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6290 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6291 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 6292 | // GIR_Coverage, 3327, |
| 6293 | GIR_EraseRootFromParent_Done, |
| 6294 | // Label 579: @14938 |
| 6295 | GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(15009), // Rule ID 3328 // |
| 6296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6297 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvwm), |
| 6298 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6299 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6300 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6302 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6303 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6304 | // MIs[1] Operand 1 |
| 6305 | // No operand predicates |
| 6306 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6307 | // (intrinsic_wo_chain:{ *:[v4i32] } 10134:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v4i32] } (XXGENPCVWM:{ *:[v4i32] } ?:{ *:[v4i32] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) |
| 6308 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6309 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVWM), |
| 6310 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6311 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 6312 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM |
| 6313 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6316 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6317 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 6318 | // GIR_Coverage, 3328, |
| 6319 | GIR_EraseRootFromParent_Done, |
| 6320 | // Label 580: @15009 |
| 6321 | GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(15080), // Rule ID 3329 // |
| 6322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6323 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxgenpcvdm), |
| 6324 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6325 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6326 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6328 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6329 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6330 | // MIs[1] Operand 1 |
| 6331 | // No operand predicates |
| 6332 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6333 | // (intrinsic_wo_chain:{ *:[v2i64] } 10132:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VRB, (imm:{ *:[i32] }):$IMM) => (COPY_TO_REGCLASS:{ *:[v2i64] } (XXGENPCVDM:{ *:[v4i32] } ?:{ *:[v2i64] }:$VRB, (imm:{ *:[i32] }):$IMM), VRRC:{ *:[i32] }) |
| 6334 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6335 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXGENPCVDM), |
| 6336 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6337 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 6338 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // IMM |
| 6339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6342 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6343 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 6344 | // GIR_Coverage, 3329, |
| 6345 | GIR_EraseRootFromParent_Done, |
| 6346 | // Label 581: @15080 |
| 6347 | GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(15117), // Rule ID 310 // |
| 6348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6349 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfsx), |
| 6350 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6351 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6353 | // MIs[0] VA |
| 6354 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6355 | // (intrinsic_wo_chain:{ *:[v4f32] } 9579:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCFSX:{ *:[v4f32] } (timm:{ *:[i32] }):$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFSX), |
| 6357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6358 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 6359 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6360 | GIR_RootConstrainSelectedInstOperands, |
| 6361 | // GIR_Coverage, 310, |
| 6362 | GIR_EraseRootFromParent_Done, |
| 6363 | // Label 582: @15117 |
| 6364 | GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(15154), // Rule ID 311 // |
| 6365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfux), |
| 6367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6370 | // MIs[0] VA |
| 6371 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6372 | // (intrinsic_wo_chain:{ *:[v4f32] } 9581:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCFUX:{ *:[v4f32] } (timm:{ *:[i32] }):$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6373 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUX), |
| 6374 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6375 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 6376 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6377 | GIR_RootConstrainSelectedInstOperands, |
| 6378 | // GIR_Coverage, 311, |
| 6379 | GIR_EraseRootFromParent_Done, |
| 6380 | // Label 583: @15154 |
| 6381 | GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(15191), // Rule ID 312 // |
| 6382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6383 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctsxs), |
| 6384 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6385 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6387 | // MIs[0] VA |
| 6388 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6389 | // (intrinsic_wo_chain:{ *:[v4i32] } 9640:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCTSXS:{ *:[v4i32] } (timm:{ *:[i32] }):$VA, v4f32:{ *:[v4f32] }:$VB) |
| 6390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTSXS), |
| 6391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6392 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 6393 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6394 | GIR_RootConstrainSelectedInstOperands, |
| 6395 | // GIR_Coverage, 312, |
| 6396 | GIR_EraseRootFromParent_Done, |
| 6397 | // Label 584: @15191 |
| 6398 | GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(15228), // Rule ID 313 // |
| 6399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6400 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctuxs), |
| 6401 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6402 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6404 | // MIs[0] VA |
| 6405 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6406 | // (intrinsic_wo_chain:{ *:[v4i32] } 9641:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VB, (timm:{ *:[i32] }):$VA) => (VCTUXS:{ *:[v4i32] } (timm:{ *:[i32] }):$VA, v4f32:{ *:[v4f32] }:$VB) |
| 6407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTUXS), |
| 6408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6409 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 6410 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6411 | GIR_RootConstrainSelectedInstOperands, |
| 6412 | // GIR_Coverage, 313, |
| 6413 | GIR_EraseRootFromParent_Done, |
| 6414 | // Label 585: @15228 |
| 6415 | GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(15265), // Rule ID 1086 // |
| 6416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6417 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbb), |
| 6418 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6419 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6421 | // MIs[0] MP |
| 6422 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6423 | // (intrinsic_wo_chain:{ *:[i64] } 9636:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBB:{ *:[i64] } v16i8:{ *:[v16i8] }:$VB, (timm:{ *:[i32] }):$MP) |
| 6424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBB), |
| 6425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] |
| 6426 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6427 | GIR_RootToRootCopy, /*OpIdx*/3, // MP |
| 6428 | GIR_RootConstrainSelectedInstOperands, |
| 6429 | // GIR_Coverage, 1086, |
| 6430 | GIR_EraseRootFromParent_Done, |
| 6431 | // Label 586: @15265 |
| 6432 | GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(15302), // Rule ID 1087 // |
| 6433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbh), |
| 6435 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6438 | // MIs[0] MP |
| 6439 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6440 | // (intrinsic_wo_chain:{ *:[i64] } 9638:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBH:{ *:[i64] } v8i16:{ *:[v8i16] }:$VB, (timm:{ *:[i32] }):$MP) |
| 6441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBH), |
| 6442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] |
| 6443 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6444 | GIR_RootToRootCopy, /*OpIdx*/3, // MP |
| 6445 | GIR_RootConstrainSelectedInstOperands, |
| 6446 | // GIR_Coverage, 1087, |
| 6447 | GIR_EraseRootFromParent_Done, |
| 6448 | // Label 587: @15302 |
| 6449 | GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(15339), // Rule ID 1088 // |
| 6450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6451 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbw), |
| 6452 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6453 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6455 | // MIs[0] MP |
| 6456 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6457 | // (intrinsic_wo_chain:{ *:[i64] } 9639:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBW:{ *:[i64] } v4i32:{ *:[v4i32] }:$VB, (timm:{ *:[i32] }):$MP) |
| 6458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBW), |
| 6459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] |
| 6460 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6461 | GIR_RootToRootCopy, /*OpIdx*/3, // MP |
| 6462 | GIR_RootConstrainSelectedInstOperands, |
| 6463 | // GIR_Coverage, 1088, |
| 6464 | GIR_EraseRootFromParent_Done, |
| 6465 | // Label 588: @15339 |
| 6466 | GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(15376), // Rule ID 1089 // |
| 6467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6468 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcntmbd), |
| 6469 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6472 | // MIs[0] MP |
| 6473 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6474 | // (intrinsic_wo_chain:{ *:[i64] } 9637:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VB, (timm:{ *:[i32] }):$MP) => (VCNTMBD:{ *:[i64] } v2i64:{ *:[v2i64] }:$VB, (timm:{ *:[i32] }):$MP) |
| 6475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCNTMBD), |
| 6476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] |
| 6477 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6478 | GIR_RootToRootCopy, /*OpIdx*/3, // MP |
| 6479 | GIR_RootConstrainSelectedInstOperands, |
| 6480 | // GIR_Coverage, 1089, |
| 6481 | GIR_EraseRootFromParent_Done, |
| 6482 | // Label 589: @15376 |
| 6483 | GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(15413), // Rule ID 1103 // |
| 6484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 6485 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vgnb), |
| 6486 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6487 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 6488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6489 | // MIs[0] N |
| 6490 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 6491 | // (intrinsic_wo_chain:{ *:[i64] } 9676:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VB, (timm:{ *:[i32] }):$N) => (VGNB:{ *:[i64] } v1i128:{ *:[v1i128] }:$VB, (timm:{ *:[i32] }):$N) |
| 6492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VGNB), |
| 6493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RD] |
| 6494 | GIR_RootToRootCopy, /*OpIdx*/2, // VB |
| 6495 | GIR_RootToRootCopy, /*OpIdx*/3, // N |
| 6496 | GIR_RootConstrainSelectedInstOperands, |
| 6497 | // GIR_Coverage, 1103, |
| 6498 | GIR_EraseRootFromParent_Done, |
| 6499 | // Label 590: @15413 |
| 6500 | GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(15458), // Rule ID 201 // |
| 6501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), |
| 6502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divwe), |
| 6503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6507 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6508 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6509 | // (intrinsic_wo_chain:{ *:[i32] } 9876:{ *:[iPTR] }, gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) => (DIVWE:{ *:[i32] } gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) |
| 6510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVWE), |
| 6511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6512 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 6513 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 6514 | GIR_RootConstrainSelectedInstOperands, |
| 6515 | // GIR_Coverage, 201, |
| 6516 | GIR_EraseRootFromParent_Done, |
| 6517 | // Label 591: @15458 |
| 6518 | GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(15503), // Rule ID 202 // |
| 6519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), |
| 6520 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divweu), |
| 6521 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6522 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6523 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6525 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6526 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6527 | // (intrinsic_wo_chain:{ *:[i32] } 9877:{ *:[iPTR] }, gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) => (DIVWEU:{ *:[i32] } gprc:{ *:[i32] }:$RA, gprc:{ *:[i32] }:$RB) |
| 6528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVWEU), |
| 6529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6530 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 6531 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 6532 | GIR_RootConstrainSelectedInstOperands, |
| 6533 | // GIR_Coverage, 202, |
| 6534 | GIR_EraseRootFromParent_Done, |
| 6535 | // Label 592: @15503 |
| 6536 | GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(15548), // Rule ID 683 // |
| 6537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasBPERMD), |
| 6538 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bpermd), |
| 6539 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6541 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6543 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6544 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6545 | // (intrinsic_wo_chain:{ *:[i64] } 9839:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RST, g8rc:{ *:[i64] }:$RB) => (BPERMD:{ *:[i64] } g8rc:{ *:[i64] }:$RST, g8rc:{ *:[i64] }:$RB) |
| 6546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BPERMD), |
| 6547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 6548 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 6549 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 6550 | GIR_RootConstrainSelectedInstOperands, |
| 6551 | // GIR_Coverage, 683, |
| 6552 | GIR_EraseRootFromParent_Done, |
| 6553 | // Label 593: @15548 |
| 6554 | GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(15593), // Rule ID 689 // |
| 6555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), |
| 6556 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divde), |
| 6557 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6558 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6559 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6561 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6562 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6563 | // (intrinsic_wo_chain:{ *:[i64] } 9873:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) => (DIVDE:{ *:[i64] } g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) |
| 6564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVDE), |
| 6565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6566 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 6567 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 6568 | GIR_RootConstrainSelectedInstOperands, |
| 6569 | // GIR_Coverage, 689, |
| 6570 | GIR_EraseRootFromParent_Done, |
| 6571 | // Label 594: @15593 |
| 6572 | GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(15638), // Rule ID 694 // |
| 6573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExtDiv), |
| 6574 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_divdeu), |
| 6575 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6577 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6579 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6580 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6581 | // (intrinsic_wo_chain:{ *:[i64] } 9874:{ *:[iPTR] }, g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) => (DIVDEU:{ *:[i64] } g8rc:{ *:[i64] }:$RA, g8rc:{ *:[i64] }:$RB) |
| 6582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DIVDEU), |
| 6583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6584 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 6585 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 6586 | GIR_RootConstrainSelectedInstOperands, |
| 6587 | // GIR_Coverage, 694, |
| 6588 | GIR_EraseRootFromParent_Done, |
| 6589 | // Label 595: @15638 |
| 6590 | GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(15704), // Rule ID 1547 // |
| 6591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), |
| 6592 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpeqb), |
| 6593 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6595 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6597 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6598 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6599 | // (intrinsic_wo_chain:{ *:[i64] } 9843:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (SETB8:{ *:[i64] } (CMPEQB:{ *:[i32] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)) |
| 6600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPEQB), |
| 6602 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6603 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 6604 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 6605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETB8), |
| 6607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6608 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6609 | GIR_RootConstrainSelectedInstOperands, |
| 6610 | // GIR_Coverage, 1547, |
| 6611 | GIR_EraseRootFromParent_Done, |
| 6612 | // Label 596: @15704 |
| 6613 | GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(15770), // Rule ID 1548 // |
| 6614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), |
| 6615 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setb), |
| 6616 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6617 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6618 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6620 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6621 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6622 | // (intrinsic_wo_chain:{ *:[i64] } 10020:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (SETB8:{ *:[i64] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b)) |
| 6623 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 6624 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 6625 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6626 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 6627 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 6628 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETB8), |
| 6630 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6631 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6632 | GIR_RootConstrainSelectedInstOperands, |
| 6633 | // GIR_Coverage, 1548, |
| 6634 | GIR_EraseRootFromParent_Done, |
| 6635 | // Label 597: @15770 |
| 6636 | GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(15815), // Rule ID 1552 // |
| 6637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode), |
| 6638 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhd), |
| 6639 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6641 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6643 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6644 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6645 | // (intrinsic_wo_chain:{ *:[i64] } 10002:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (MULHD:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b) |
| 6646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHD), |
| 6647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6648 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 6649 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 6650 | GIR_RootConstrainSelectedInstOperands, |
| 6651 | // GIR_Coverage, 1552, |
| 6652 | GIR_EraseRootFromParent_Done, |
| 6653 | // Label 598: @15815 |
| 6654 | GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(15860), // Rule ID 1553 // |
| 6655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode), |
| 6656 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhdu), |
| 6657 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6659 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6661 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6662 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6663 | // (intrinsic_wo_chain:{ *:[i64] } 10003:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (MULHDU:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b) |
| 6664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHDU), |
| 6665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6666 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 6667 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 6668 | GIR_RootConstrainSelectedInstOperands, |
| 6669 | // GIR_Coverage, 1553, |
| 6670 | GIR_EraseRootFromParent_Done, |
| 6671 | // Label 599: @15860 |
| 6672 | GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(15902), // Rule ID 1556 // |
| 6673 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpb), |
| 6674 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 6675 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6676 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 6677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6678 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6679 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 6680 | // (intrinsic_wo_chain:{ *:[i64] } 9842:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b) => (CMPB8:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b) |
| 6681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CMPB8), |
| 6682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 6683 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 6684 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 6685 | GIR_RootConstrainSelectedInstOperands, |
| 6686 | // GIR_Coverage, 1556, |
| 6687 | GIR_EraseRootFromParent_Done, |
| 6688 | // Label 600: @15902 |
| 6689 | GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(15944), // Rule ID 4825 // |
| 6690 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhw), |
| 6691 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6692 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6693 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6695 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6696 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6697 | // (intrinsic_wo_chain:{ *:[i32] } 10004:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (MULHW:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b) |
| 6698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHW), |
| 6699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6700 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 6701 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 6702 | GIR_RootConstrainSelectedInstOperands, |
| 6703 | // GIR_Coverage, 4825, |
| 6704 | GIR_EraseRootFromParent_Done, |
| 6705 | // Label 601: @15944 |
| 6706 | GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(15986), // Rule ID 4826 // |
| 6707 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mulhwu), |
| 6708 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6709 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6710 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6712 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6713 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6714 | // (intrinsic_wo_chain:{ *:[i32] } 10005:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (MULHWU:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b) |
| 6715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MULHWU), |
| 6716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 6717 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 6718 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 6719 | GIR_RootConstrainSelectedInstOperands, |
| 6720 | // GIR_Coverage, 4826, |
| 6721 | GIR_EraseRootFromParent_Done, |
| 6722 | // Label 602: @15986 |
| 6723 | GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(16028), // Rule ID 4827 // |
| 6724 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cmpb), |
| 6725 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6726 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6727 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 6728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6729 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6730 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 6731 | // (intrinsic_wo_chain:{ *:[i32] } 9842:{ *:[iPTR] }, gprc:{ *:[i32] }:$a, gprc:{ *:[i32] }:$b) => (CMPB:{ *:[i32] } ?:{ *:[i32] }:$a, ?:{ *:[i32] }:$b) |
| 6732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CMPB), |
| 6733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 6734 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 6735 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 6736 | GIR_RootConstrainSelectedInstOperands, |
| 6737 | // GIR_Coverage, 4827, |
| 6738 | GIR_EraseRootFromParent_Done, |
| 6739 | // Label 603: @16028 |
| 6740 | GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(16065), // Rule ID 301 // |
| 6741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6742 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddcuw), |
| 6743 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6747 | // (intrinsic_wo_chain:{ *:[v4i32] } 9562:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDCUW), |
| 6749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6750 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6751 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6752 | GIR_RootConstrainSelectedInstOperands, |
| 6753 | // GIR_Coverage, 301, |
| 6754 | GIR_EraseRootFromParent_Done, |
| 6755 | // Label 604: @16065 |
| 6756 | GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(16102), // Rule ID 302 // |
| 6757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6758 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddsbs), |
| 6759 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6761 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6763 | // (intrinsic_wo_chain:{ *:[v16i8] } 9565:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 6764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSBS), |
| 6765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6766 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6767 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6768 | GIR_RootConstrainSelectedInstOperands, |
| 6769 | // GIR_Coverage, 302, |
| 6770 | GIR_EraseRootFromParent_Done, |
| 6771 | // Label 605: @16102 |
| 6772 | GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(16139), // Rule ID 303 // |
| 6773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6774 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddshs), |
| 6775 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6779 | // (intrinsic_wo_chain:{ *:[v8i16] } 9566:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 6780 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSHS), |
| 6781 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6782 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6783 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6784 | GIR_RootConstrainSelectedInstOperands, |
| 6785 | // GIR_Coverage, 303, |
| 6786 | GIR_EraseRootFromParent_Done, |
| 6787 | // Label 606: @16139 |
| 6788 | GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(16176), // Rule ID 304 // |
| 6789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6790 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddsws), |
| 6791 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6792 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6793 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6795 | // (intrinsic_wo_chain:{ *:[v4i32] } 9567:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDSWS), |
| 6797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6798 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6799 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6800 | GIR_RootConstrainSelectedInstOperands, |
| 6801 | // GIR_Coverage, 304, |
| 6802 | GIR_EraseRootFromParent_Done, |
| 6803 | // Label 607: @16176 |
| 6804 | GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(16213), // Rule ID 305 // |
| 6805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6806 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddubs), |
| 6807 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6808 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6809 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6811 | // (intrinsic_wo_chain:{ *:[v16i8] } 9568:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VADDUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 6812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUBS), |
| 6813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6814 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6815 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6816 | GIR_RootConstrainSelectedInstOperands, |
| 6817 | // GIR_Coverage, 305, |
| 6818 | GIR_EraseRootFromParent_Done, |
| 6819 | // Label 608: @16213 |
| 6820 | GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(16250), // Rule ID 306 // |
| 6821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6822 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vadduhs), |
| 6823 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6825 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6827 | // (intrinsic_wo_chain:{ *:[v8i16] } 9569:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VADDUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 6828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUHS), |
| 6829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6830 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6831 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6832 | GIR_RootConstrainSelectedInstOperands, |
| 6833 | // GIR_Coverage, 306, |
| 6834 | GIR_EraseRootFromParent_Done, |
| 6835 | // Label 609: @16250 |
| 6836 | GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(16287), // Rule ID 307 // |
| 6837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6838 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vadduws), |
| 6839 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6840 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6841 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6843 | // (intrinsic_wo_chain:{ *:[v4i32] } 9570:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VADDUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDUWS), |
| 6845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6846 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6847 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6848 | GIR_RootConstrainSelectedInstOperands, |
| 6849 | // GIR_Coverage, 307, |
| 6850 | GIR_EraseRootFromParent_Done, |
| 6851 | // Label 610: @16287 |
| 6852 | GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(16324), // Rule ID 320 // |
| 6853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6854 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsb), |
| 6855 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6859 | // (intrinsic_wo_chain:{ *:[v16i8] } 9571:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VAVGSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 6860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSB), |
| 6861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6862 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6863 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6864 | GIR_RootConstrainSelectedInstOperands, |
| 6865 | // GIR_Coverage, 320, |
| 6866 | GIR_EraseRootFromParent_Done, |
| 6867 | // Label 611: @16324 |
| 6868 | GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(16361), // Rule ID 321 // |
| 6869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6870 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsh), |
| 6871 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6873 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6875 | // (intrinsic_wo_chain:{ *:[v8i16] } 9572:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VAVGSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 6876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSH), |
| 6877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6878 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6879 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6880 | GIR_RootConstrainSelectedInstOperands, |
| 6881 | // GIR_Coverage, 321, |
| 6882 | GIR_EraseRootFromParent_Done, |
| 6883 | // Label 612: @16361 |
| 6884 | GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(16398), // Rule ID 322 // |
| 6885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6886 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgsw), |
| 6887 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6888 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6889 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6891 | // (intrinsic_wo_chain:{ *:[v4i32] } 9573:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAVGSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGSW), |
| 6893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6894 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6895 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6896 | GIR_RootConstrainSelectedInstOperands, |
| 6897 | // GIR_Coverage, 322, |
| 6898 | GIR_EraseRootFromParent_Done, |
| 6899 | // Label 613: @16398 |
| 6900 | GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(16435), // Rule ID 323 // |
| 6901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavgub), |
| 6903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6907 | // (intrinsic_wo_chain:{ *:[v16i8] } 9574:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VAVGUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 6908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUB), |
| 6909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6910 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6911 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6912 | GIR_RootConstrainSelectedInstOperands, |
| 6913 | // GIR_Coverage, 323, |
| 6914 | GIR_EraseRootFromParent_Done, |
| 6915 | // Label 614: @16435 |
| 6916 | GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(16472), // Rule ID 324 // |
| 6917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6918 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavguh), |
| 6919 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6921 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6923 | // (intrinsic_wo_chain:{ *:[v8i16] } 9575:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VAVGUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 6924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUH), |
| 6925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6926 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6927 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6928 | GIR_RootConstrainSelectedInstOperands, |
| 6929 | // GIR_Coverage, 324, |
| 6930 | GIR_EraseRootFromParent_Done, |
| 6931 | // Label 615: @16472 |
| 6932 | GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(16509), // Rule ID 325 // |
| 6933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6934 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vavguw), |
| 6935 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6936 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6937 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6939 | // (intrinsic_wo_chain:{ *:[v4i32] } 9576:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VAVGUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 6940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VAVGUW), |
| 6941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6942 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6943 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6944 | GIR_RootConstrainSelectedInstOperands, |
| 6945 | // GIR_Coverage, 325, |
| 6946 | GIR_EraseRootFromParent_Done, |
| 6947 | // Label 616: @16509 |
| 6948 | GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(16546), // Rule ID 326 // |
| 6949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6950 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxfp), |
| 6951 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6952 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6953 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6955 | // (intrinsic_wo_chain:{ *:[v4f32] } 9695:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VMAXFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) |
| 6956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXFP), |
| 6957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6958 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6959 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6960 | GIR_RootConstrainSelectedInstOperands, |
| 6961 | // GIR_Coverage, 326, |
| 6962 | GIR_EraseRootFromParent_Done, |
| 6963 | // Label 617: @16546 |
| 6964 | GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(16583), // Rule ID 327 // |
| 6965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6966 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsb), |
| 6967 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6968 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6969 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6971 | // (intrinsic_wo_chain:{ *:[v16i8] } 9696:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMAXSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 6972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSB), |
| 6973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6974 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6975 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6976 | GIR_RootConstrainSelectedInstOperands, |
| 6977 | // GIR_Coverage, 327, |
| 6978 | GIR_EraseRootFromParent_Done, |
| 6979 | // Label 618: @16583 |
| 6980 | GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(16620), // Rule ID 328 // |
| 6981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6982 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsh), |
| 6983 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6984 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6985 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 6987 | // (intrinsic_wo_chain:{ *:[v8i16] } 9698:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMAXSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 6988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSH), |
| 6989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 6990 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 6991 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 6992 | GIR_RootConstrainSelectedInstOperands, |
| 6993 | // GIR_Coverage, 328, |
| 6994 | GIR_EraseRootFromParent_Done, |
| 6995 | // Label 619: @16620 |
| 6996 | GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(16657), // Rule ID 329 // |
| 6997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 6998 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsw), |
| 6999 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7003 | // (intrinsic_wo_chain:{ *:[v4i32] } 9699:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMAXSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSW), |
| 7005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7006 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7007 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7008 | GIR_RootConstrainSelectedInstOperands, |
| 7009 | // GIR_Coverage, 329, |
| 7010 | GIR_EraseRootFromParent_Done, |
| 7011 | // Label 620: @16657 |
| 7012 | GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(16694), // Rule ID 330 // |
| 7013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7014 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxub), |
| 7015 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7017 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7019 | // (intrinsic_wo_chain:{ *:[v16i8] } 9700:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMAXUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUB), |
| 7021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7022 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7023 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7024 | GIR_RootConstrainSelectedInstOperands, |
| 7025 | // GIR_Coverage, 330, |
| 7026 | GIR_EraseRootFromParent_Done, |
| 7027 | // Label 621: @16694 |
| 7028 | GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(16731), // Rule ID 331 // |
| 7029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7030 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxuh), |
| 7031 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7032 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7033 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7035 | // (intrinsic_wo_chain:{ *:[v8i16] } 9702:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMAXUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUH), |
| 7037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7038 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7039 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7040 | GIR_RootConstrainSelectedInstOperands, |
| 7041 | // GIR_Coverage, 331, |
| 7042 | GIR_EraseRootFromParent_Done, |
| 7043 | // Label 622: @16731 |
| 7044 | GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(16768), // Rule ID 332 // |
| 7045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7046 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxuw), |
| 7047 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7048 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7049 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7051 | // (intrinsic_wo_chain:{ *:[v4i32] } 9703:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMAXUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUW), |
| 7053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7054 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7055 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7056 | GIR_RootConstrainSelectedInstOperands, |
| 7057 | // GIR_Coverage, 332, |
| 7058 | GIR_EraseRootFromParent_Done, |
| 7059 | // Label 623: @16768 |
| 7060 | GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(16805), // Rule ID 333 // |
| 7061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7062 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminfp), |
| 7063 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7064 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7065 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7067 | // (intrinsic_wo_chain:{ *:[v4f32] } 9706:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VMINFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) |
| 7068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINFP), |
| 7069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7070 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7071 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7072 | GIR_RootConstrainSelectedInstOperands, |
| 7073 | // GIR_Coverage, 333, |
| 7074 | GIR_EraseRootFromParent_Done, |
| 7075 | // Label 624: @16805 |
| 7076 | GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(16842), // Rule ID 334 // |
| 7077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7078 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsb), |
| 7079 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7080 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7081 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7083 | // (intrinsic_wo_chain:{ *:[v16i8] } 9707:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMINSB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSB), |
| 7085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7086 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7087 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7088 | GIR_RootConstrainSelectedInstOperands, |
| 7089 | // GIR_Coverage, 334, |
| 7090 | GIR_EraseRootFromParent_Done, |
| 7091 | // Label 625: @16842 |
| 7092 | GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(16879), // Rule ID 335 // |
| 7093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7094 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsh), |
| 7095 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7097 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7099 | // (intrinsic_wo_chain:{ *:[v8i16] } 9709:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMINSH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSH), |
| 7101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7102 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7103 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7104 | GIR_RootConstrainSelectedInstOperands, |
| 7105 | // GIR_Coverage, 335, |
| 7106 | GIR_EraseRootFromParent_Done, |
| 7107 | // Label 626: @16879 |
| 7108 | GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(16916), // Rule ID 336 // |
| 7109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7110 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsw), |
| 7111 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7112 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7113 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7115 | // (intrinsic_wo_chain:{ *:[v4i32] } 9710:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSW), |
| 7117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7118 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7119 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7120 | GIR_RootConstrainSelectedInstOperands, |
| 7121 | // GIR_Coverage, 336, |
| 7122 | GIR_EraseRootFromParent_Done, |
| 7123 | // Label 627: @16916 |
| 7124 | GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(16953), // Rule ID 337 // |
| 7125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7126 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminub), |
| 7127 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7129 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7131 | // (intrinsic_wo_chain:{ *:[v16i8] } 9711:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMINUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUB), |
| 7133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7134 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7135 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7136 | GIR_RootConstrainSelectedInstOperands, |
| 7137 | // GIR_Coverage, 337, |
| 7138 | GIR_EraseRootFromParent_Done, |
| 7139 | // Label 628: @16953 |
| 7140 | GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(16990), // Rule ID 338 // |
| 7141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7142 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminuh), |
| 7143 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7145 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7147 | // (intrinsic_wo_chain:{ *:[v8i16] } 9713:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMINUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUH), |
| 7149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7150 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7151 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7152 | GIR_RootConstrainSelectedInstOperands, |
| 7153 | // GIR_Coverage, 338, |
| 7154 | GIR_EraseRootFromParent_Done, |
| 7155 | // Label 629: @16990 |
| 7156 | GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(17027), // Rule ID 339 // |
| 7157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminuw), |
| 7159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7163 | // (intrinsic_wo_chain:{ *:[v4i32] } 9714:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMINUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUW), |
| 7165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7166 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7167 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7168 | GIR_RootConstrainSelectedInstOperands, |
| 7169 | // GIR_Coverage, 339, |
| 7170 | GIR_EraseRootFromParent_Done, |
| 7171 | // Label 630: @17027 |
| 7172 | GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(17064), // Rule ID 352 // |
| 7173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7174 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesb), |
| 7175 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7177 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7179 | // (intrinsic_wo_chain:{ *:[v8i16] } 9724:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULESB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESB), |
| 7181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7182 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7183 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7184 | GIR_RootConstrainSelectedInstOperands, |
| 7185 | // GIR_Coverage, 352, |
| 7186 | GIR_EraseRootFromParent_Done, |
| 7187 | // Label 631: @17064 |
| 7188 | GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(17101), // Rule ID 353 // |
| 7189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7190 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesh), |
| 7191 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7192 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7193 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7195 | // (intrinsic_wo_chain:{ *:[v4i32] } 9726:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULESH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESH), |
| 7197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7198 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7199 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7200 | GIR_RootConstrainSelectedInstOperands, |
| 7201 | // GIR_Coverage, 353, |
| 7202 | GIR_EraseRootFromParent_Done, |
| 7203 | // Label 632: @17101 |
| 7204 | GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(17138), // Rule ID 354 // |
| 7205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7206 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleub), |
| 7207 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7208 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7209 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7211 | // (intrinsic_wo_chain:{ *:[v8i16] } 9728:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULEUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUB), |
| 7213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7214 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7215 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7216 | GIR_RootConstrainSelectedInstOperands, |
| 7217 | // GIR_Coverage, 354, |
| 7218 | GIR_EraseRootFromParent_Done, |
| 7219 | // Label 633: @17138 |
| 7220 | GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(17175), // Rule ID 355 // |
| 7221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7222 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleuh), |
| 7223 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7224 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7225 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7227 | // (intrinsic_wo_chain:{ *:[v4i32] } 9730:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULEUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUH), |
| 7229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7230 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7231 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7232 | GIR_RootConstrainSelectedInstOperands, |
| 7233 | // GIR_Coverage, 355, |
| 7234 | GIR_EraseRootFromParent_Done, |
| 7235 | // Label 634: @17175 |
| 7236 | GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(17212), // Rule ID 356 // |
| 7237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7238 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosb), |
| 7239 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7241 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7243 | // (intrinsic_wo_chain:{ *:[v8i16] } 9736:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULOSB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSB), |
| 7245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7246 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7247 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7248 | GIR_RootConstrainSelectedInstOperands, |
| 7249 | // GIR_Coverage, 356, |
| 7250 | GIR_EraseRootFromParent_Done, |
| 7251 | // Label 635: @17212 |
| 7252 | GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(17249), // Rule ID 357 // |
| 7253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7254 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosh), |
| 7255 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7256 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7257 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7259 | // (intrinsic_wo_chain:{ *:[v4i32] } 9738:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULOSH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSH), |
| 7261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7262 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7263 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7264 | GIR_RootConstrainSelectedInstOperands, |
| 7265 | // GIR_Coverage, 357, |
| 7266 | GIR_EraseRootFromParent_Done, |
| 7267 | // Label 636: @17249 |
| 7268 | GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(17286), // Rule ID 358 // |
| 7269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7270 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuloub), |
| 7271 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7272 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7273 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7275 | // (intrinsic_wo_chain:{ *:[v8i16] } 9740:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VMULOUB:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUB), |
| 7277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7278 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7279 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7280 | GIR_RootConstrainSelectedInstOperands, |
| 7281 | // GIR_Coverage, 358, |
| 7282 | GIR_EraseRootFromParent_Done, |
| 7283 | // Label 637: @17286 |
| 7284 | GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(17323), // Rule ID 359 // |
| 7285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7286 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulouh), |
| 7287 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7288 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7289 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7291 | // (intrinsic_wo_chain:{ *:[v4i32] } 9742:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VMULOUH:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUH), |
| 7293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7294 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7295 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7296 | GIR_RootConstrainSelectedInstOperands, |
| 7297 | // GIR_Coverage, 359, |
| 7298 | GIR_EraseRootFromParent_Done, |
| 7299 | // Label 638: @17323 |
| 7300 | GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(17360), // Rule ID 366 // |
| 7301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7302 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubcuw), |
| 7303 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7305 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7307 | // (intrinsic_wo_chain:{ *:[v4i32] } 9804:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBCUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBCUW), |
| 7309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7310 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7311 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7312 | GIR_RootConstrainSelectedInstOperands, |
| 7313 | // GIR_Coverage, 366, |
| 7314 | GIR_EraseRootFromParent_Done, |
| 7315 | // Label 639: @17360 |
| 7316 | GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(17397), // Rule ID 371 // |
| 7317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7318 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubsbs), |
| 7319 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7320 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7321 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7323 | // (intrinsic_wo_chain:{ *:[v16i8] } 9807:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBSBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSBS), |
| 7325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7326 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7327 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7328 | GIR_RootConstrainSelectedInstOperands, |
| 7329 | // GIR_Coverage, 371, |
| 7330 | GIR_EraseRootFromParent_Done, |
| 7331 | // Label 640: @17397 |
| 7332 | GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(17434), // Rule ID 372 // |
| 7333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7334 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubshs), |
| 7335 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7336 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7337 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7339 | // (intrinsic_wo_chain:{ *:[v8i16] } 9808:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSHS), |
| 7341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7342 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7343 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7344 | GIR_RootConstrainSelectedInstOperands, |
| 7345 | // GIR_Coverage, 372, |
| 7346 | GIR_EraseRootFromParent_Done, |
| 7347 | // Label 641: @17434 |
| 7348 | GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(17471), // Rule ID 373 // |
| 7349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7350 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubsws), |
| 7351 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7353 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7355 | // (intrinsic_wo_chain:{ *:[v4i32] } 9809:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBSWS), |
| 7357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7358 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7359 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7360 | GIR_RootConstrainSelectedInstOperands, |
| 7361 | // GIR_Coverage, 373, |
| 7362 | GIR_EraseRootFromParent_Done, |
| 7363 | // Label 642: @17471 |
| 7364 | GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(17508), // Rule ID 374 // |
| 7365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsububs), |
| 7367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7369 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7371 | // (intrinsic_wo_chain:{ *:[v16i8] } 9810:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSUBUBS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUBS), |
| 7373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7374 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7375 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7376 | GIR_RootConstrainSelectedInstOperands, |
| 7377 | // GIR_Coverage, 374, |
| 7378 | GIR_EraseRootFromParent_Done, |
| 7379 | // Label 643: @17508 |
| 7380 | GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(17545), // Rule ID 375 // |
| 7381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7382 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubuhs), |
| 7383 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7384 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7385 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7387 | // (intrinsic_wo_chain:{ *:[v8i16] } 9811:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSUBUHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUHS), |
| 7389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7390 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7391 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7392 | GIR_RootConstrainSelectedInstOperands, |
| 7393 | // GIR_Coverage, 375, |
| 7394 | GIR_EraseRootFromParent_Done, |
| 7395 | // Label 644: @17545 |
| 7396 | GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(17582), // Rule ID 376 // |
| 7397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7398 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubuws), |
| 7399 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7400 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7401 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7403 | // (intrinsic_wo_chain:{ *:[v4i32] } 9812:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUBUWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBUWS), |
| 7405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7406 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7407 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7408 | GIR_RootConstrainSelectedInstOperands, |
| 7409 | // GIR_Coverage, 376, |
| 7410 | GIR_EraseRootFromParent_Done, |
| 7411 | // Label 645: @17582 |
| 7412 | GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(17619), // Rule ID 385 // |
| 7413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7414 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlb), |
| 7415 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7417 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7419 | // (intrinsic_wo_chain:{ *:[v16i8] } 9766:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLB), |
| 7421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7422 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7423 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7424 | GIR_RootConstrainSelectedInstOperands, |
| 7425 | // GIR_Coverage, 385, |
| 7426 | GIR_EraseRootFromParent_Done, |
| 7427 | // Label 646: @17619 |
| 7428 | GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(17656), // Rule ID 386 // |
| 7429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7430 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlh), |
| 7431 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7433 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7435 | // (intrinsic_wo_chain:{ *:[v8i16] } 9770:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLH), |
| 7437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7438 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7439 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7440 | GIR_RootConstrainSelectedInstOperands, |
| 7441 | // GIR_Coverage, 386, |
| 7442 | GIR_EraseRootFromParent_Done, |
| 7443 | // Label 647: @17656 |
| 7444 | GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(17693), // Rule ID 387 // |
| 7445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7446 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlw), |
| 7447 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7448 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7449 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7451 | // (intrinsic_wo_chain:{ *:[v4i32] } 9773:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLW), |
| 7453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7454 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7455 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7456 | GIR_RootConstrainSelectedInstOperands, |
| 7457 | // GIR_Coverage, 387, |
| 7458 | GIR_EraseRootFromParent_Done, |
| 7459 | // Label 648: @17693 |
| 7460 | GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(17730), // Rule ID 388 // |
| 7461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7462 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsl), |
| 7463 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7464 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7465 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7467 | // (intrinsic_wo_chain:{ *:[v4i32] } 9778:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSL), |
| 7469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7470 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7471 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7472 | GIR_RootConstrainSelectedInstOperands, |
| 7473 | // GIR_Coverage, 388, |
| 7474 | GIR_EraseRootFromParent_Done, |
| 7475 | // Label 649: @17730 |
| 7476 | GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(17767), // Rule ID 389 // |
| 7477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7478 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslo), |
| 7479 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7481 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7483 | // (intrinsic_wo_chain:{ *:[v4i32] } 9782:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSLO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLO), |
| 7485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7486 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7487 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7488 | GIR_RootConstrainSelectedInstOperands, |
| 7489 | // GIR_Coverage, 389, |
| 7490 | GIR_EraseRootFromParent_Done, |
| 7491 | // Label 650: @17767 |
| 7492 | GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(17804), // Rule ID 390 // |
| 7493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7494 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslb), |
| 7495 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7497 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7499 | // (intrinsic_wo_chain:{ *:[v16i8] } 9779:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLB), |
| 7501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7502 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7503 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7504 | GIR_RootConstrainSelectedInstOperands, |
| 7505 | // GIR_Coverage, 390, |
| 7506 | GIR_EraseRootFromParent_Done, |
| 7507 | // Label 651: @17804 |
| 7508 | GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(17841), // Rule ID 391 // |
| 7509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7510 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslh), |
| 7511 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7512 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7513 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7515 | // (intrinsic_wo_chain:{ *:[v8i16] } 9781:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLH), |
| 7517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7518 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7519 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7520 | GIR_RootConstrainSelectedInstOperands, |
| 7521 | // GIR_Coverage, 391, |
| 7522 | GIR_EraseRootFromParent_Done, |
| 7523 | // Label 652: @17841 |
| 7524 | GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(17878), // Rule ID 392 // |
| 7525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7526 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslw), |
| 7527 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7528 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7529 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7531 | // (intrinsic_wo_chain:{ *:[v4i32] } 9784:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLW), |
| 7533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7534 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7535 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7536 | GIR_RootConstrainSelectedInstOperands, |
| 7537 | // GIR_Coverage, 392, |
| 7538 | GIR_EraseRootFromParent_Done, |
| 7539 | // Label 653: @17878 |
| 7540 | GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(17915), // Rule ID 396 // |
| 7541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7542 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsr), |
| 7543 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7544 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7545 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7547 | // (intrinsic_wo_chain:{ *:[v4i32] } 9785:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSR:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSR), |
| 7549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7550 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7551 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7552 | GIR_RootConstrainSelectedInstOperands, |
| 7553 | // GIR_Coverage, 396, |
| 7554 | GIR_EraseRootFromParent_Done, |
| 7555 | // Label 654: @17915 |
| 7556 | GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(17952), // Rule ID 397 // |
| 7557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7558 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsro), |
| 7559 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7561 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7563 | // (intrinsic_wo_chain:{ *:[v4i32] } 9792:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRO), |
| 7565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7566 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7567 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7568 | GIR_RootConstrainSelectedInstOperands, |
| 7569 | // GIR_Coverage, 397, |
| 7570 | GIR_EraseRootFromParent_Done, |
| 7571 | // Label 655: @17952 |
| 7572 | GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(17989), // Rule ID 398 // |
| 7573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7574 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrab), |
| 7575 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7577 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7579 | // (intrinsic_wo_chain:{ *:[v16i8] } 9786:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRAB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAB), |
| 7581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7582 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7583 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7584 | GIR_RootConstrainSelectedInstOperands, |
| 7585 | // GIR_Coverage, 398, |
| 7586 | GIR_EraseRootFromParent_Done, |
| 7587 | // Label 656: @17989 |
| 7588 | GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(18026), // Rule ID 399 // |
| 7589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7590 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrah), |
| 7591 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7592 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7593 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7595 | // (intrinsic_wo_chain:{ *:[v8i16] } 9787:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSRAH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAH), |
| 7597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7598 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7599 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7600 | GIR_RootConstrainSelectedInstOperands, |
| 7601 | // GIR_Coverage, 399, |
| 7602 | GIR_EraseRootFromParent_Done, |
| 7603 | // Label 657: @18026 |
| 7604 | GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(18063), // Rule ID 400 // |
| 7605 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7606 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsraw), |
| 7607 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7608 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7609 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7611 | // (intrinsic_wo_chain:{ *:[v4i32] } 9788:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAW), |
| 7613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7614 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7615 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7616 | GIR_RootConstrainSelectedInstOperands, |
| 7617 | // GIR_Coverage, 400, |
| 7618 | GIR_EraseRootFromParent_Done, |
| 7619 | // Label 658: @18063 |
| 7620 | GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(18100), // Rule ID 401 // |
| 7621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrb), |
| 7623 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7627 | // (intrinsic_wo_chain:{ *:[v16i8] } 9789:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRB), |
| 7629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7630 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7631 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7632 | GIR_RootConstrainSelectedInstOperands, |
| 7633 | // GIR_Coverage, 401, |
| 7634 | GIR_EraseRootFromParent_Done, |
| 7635 | // Label 659: @18100 |
| 7636 | GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(18137), // Rule ID 402 // |
| 7637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7638 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrh), |
| 7639 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7641 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7643 | // (intrinsic_wo_chain:{ *:[v8i16] } 9791:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VSRH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRH), |
| 7645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7646 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7647 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7648 | GIR_RootConstrainSelectedInstOperands, |
| 7649 | // GIR_Coverage, 402, |
| 7650 | GIR_EraseRootFromParent_Done, |
| 7651 | // Label 660: @18137 |
| 7652 | GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(18174), // Rule ID 403 // |
| 7653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7654 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrw), |
| 7655 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7659 | // (intrinsic_wo_chain:{ *:[v4i32] } 9794:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRW), |
| 7661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7662 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7663 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7664 | GIR_RootConstrainSelectedInstOperands, |
| 7665 | // GIR_Coverage, 403, |
| 7666 | GIR_EraseRootFromParent_Done, |
| 7667 | // Label 661: @18174 |
| 7668 | GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(18211), // Rule ID 407 // |
| 7669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 7670 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkpx), |
| 7671 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7673 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7675 | // (intrinsic_wo_chain:{ *:[v8i16] } 9748:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKPX:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKPX), |
| 7677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7678 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7679 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7680 | GIR_RootConstrainSelectedInstOperands, |
| 7681 | // GIR_Coverage, 407, |
| 7682 | GIR_EraseRootFromParent_Done, |
| 7683 | // Label 662: @18211 |
| 7684 | GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(18248), // Rule ID 454 // |
| 7685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7686 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesw), |
| 7687 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7688 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7689 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7691 | // (intrinsic_wo_chain:{ *:[v2i64] } 9727:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULESW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESW), |
| 7693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7694 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7695 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7696 | GIR_RootConstrainSelectedInstOperands, |
| 7697 | // GIR_Coverage, 454, |
| 7698 | GIR_EraseRootFromParent_Done, |
| 7699 | // Label 663: @18248 |
| 7700 | GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(18285), // Rule ID 455 // |
| 7701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7702 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleuw), |
| 7703 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7704 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7705 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7707 | // (intrinsic_wo_chain:{ *:[v2i64] } 9731:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULEUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUW), |
| 7709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7710 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7711 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7712 | GIR_RootConstrainSelectedInstOperands, |
| 7713 | // GIR_Coverage, 455, |
| 7714 | GIR_EraseRootFromParent_Done, |
| 7715 | // Label 664: @18285 |
| 7716 | GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(18322), // Rule ID 456 // |
| 7717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7718 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosw), |
| 7719 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7720 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7721 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7723 | // (intrinsic_wo_chain:{ *:[v2i64] } 9739:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULOSW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSW), |
| 7725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7726 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7727 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7728 | GIR_RootConstrainSelectedInstOperands, |
| 7729 | // GIR_Coverage, 456, |
| 7730 | GIR_EraseRootFromParent_Done, |
| 7731 | // Label 665: @18322 |
| 7732 | GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(18359), // Rule ID 457 // |
| 7733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7734 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulouw), |
| 7735 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7739 | // (intrinsic_wo_chain:{ *:[v2i64] } 9743:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULOUW:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUW), |
| 7741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7742 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7743 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7744 | GIR_RootConstrainSelectedInstOperands, |
| 7745 | // GIR_Coverage, 457, |
| 7746 | GIR_EraseRootFromParent_Done, |
| 7747 | // Label 666: @18359 |
| 7748 | GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(18396), // Rule ID 459 // |
| 7749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7750 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxsd), |
| 7751 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7753 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7755 | // (intrinsic_wo_chain:{ *:[v2i64] } 9697:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMAXSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSD), |
| 7757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7758 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7759 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7760 | GIR_RootConstrainSelectedInstOperands, |
| 7761 | // GIR_Coverage, 459, |
| 7762 | GIR_EraseRootFromParent_Done, |
| 7763 | // Label 667: @18396 |
| 7764 | GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(18433), // Rule ID 460 // |
| 7765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7766 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaxud), |
| 7767 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7768 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7769 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7771 | // (intrinsic_wo_chain:{ *:[v2i64] } 9701:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMAXUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUD), |
| 7773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7774 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7775 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7776 | GIR_RootConstrainSelectedInstOperands, |
| 7777 | // GIR_Coverage, 460, |
| 7778 | GIR_EraseRootFromParent_Done, |
| 7779 | // Label 668: @18433 |
| 7780 | GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(18470), // Rule ID 461 // |
| 7781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminsd), |
| 7783 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7787 | // (intrinsic_wo_chain:{ *:[v2i64] } 9708:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSD), |
| 7789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7790 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7791 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7792 | GIR_RootConstrainSelectedInstOperands, |
| 7793 | // GIR_Coverage, 461, |
| 7794 | GIR_EraseRootFromParent_Done, |
| 7795 | // Label 669: @18470 |
| 7796 | GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(18507), // Rule ID 462 // |
| 7797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7798 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vminud), |
| 7799 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7803 | // (intrinsic_wo_chain:{ *:[v2i64] } 9712:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMINUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUD), |
| 7805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7806 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7807 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7808 | GIR_RootConstrainSelectedInstOperands, |
| 7809 | // GIR_Coverage, 462, |
| 7810 | GIR_EraseRootFromParent_Done, |
| 7811 | // Label 670: @18507 |
| 7812 | GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(18544), // Rule ID 465 // |
| 7813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7814 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrld), |
| 7815 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7817 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7819 | // (intrinsic_wo_chain:{ *:[v2i64] } 9767:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLD), |
| 7821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7822 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7823 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7824 | GIR_RootConstrainSelectedInstOperands, |
| 7825 | // GIR_Coverage, 465, |
| 7826 | GIR_EraseRootFromParent_Done, |
| 7827 | // Label 671: @18544 |
| 7828 | GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(18581), // Rule ID 469 // |
| 7829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7830 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddcuq), |
| 7831 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 7832 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 7833 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 7834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7835 | // (intrinsic_wo_chain:{ *:[v1i128] } 9561:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VADDCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 7836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDCUQ), |
| 7837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7838 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7839 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7840 | GIR_RootConstrainSelectedInstOperands, |
| 7841 | // GIR_Coverage, 469, |
| 7842 | GIR_EraseRootFromParent_Done, |
| 7843 | // Label 672: @18581 |
| 7844 | GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(18618), // Rule ID 474 // |
| 7845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7846 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubcuq), |
| 7847 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 7848 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 7849 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 7850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7851 | // (intrinsic_wo_chain:{ *:[v1i128] } 9803:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VSUBCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 7852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBCUQ), |
| 7853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7854 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7855 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7856 | GIR_RootConstrainSelectedInstOperands, |
| 7857 | // GIR_Coverage, 474, |
| 7858 | GIR_EraseRootFromParent_Done, |
| 7859 | // Label 673: @18618 |
| 7860 | GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(18655), // Rule ID 493 // |
| 7861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7862 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumb), |
| 7863 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7865 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7867 | // (intrinsic_wo_chain:{ *:[v16i8] } 9526:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VPMSUMB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMB), |
| 7869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7870 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7871 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7872 | GIR_RootConstrainSelectedInstOperands, |
| 7873 | // GIR_Coverage, 493, |
| 7874 | GIR_EraseRootFromParent_Done, |
| 7875 | // Label 674: @18655 |
| 7876 | GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(18692), // Rule ID 494 // |
| 7877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumh), |
| 7879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7883 | // (intrinsic_wo_chain:{ *:[v8i16] } 9528:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPMSUMH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 7884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMH), |
| 7885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7886 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7887 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7888 | GIR_RootConstrainSelectedInstOperands, |
| 7889 | // GIR_Coverage, 494, |
| 7890 | GIR_EraseRootFromParent_Done, |
| 7891 | // Label 675: @18692 |
| 7892 | GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(18729), // Rule ID 495 // |
| 7893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7894 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumw), |
| 7895 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7897 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7899 | // (intrinsic_wo_chain:{ *:[v4i32] } 9529:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPMSUMW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 7900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMW), |
| 7901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7902 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7903 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7904 | GIR_RootConstrainSelectedInstOperands, |
| 7905 | // GIR_Coverage, 495, |
| 7906 | GIR_EraseRootFromParent_Done, |
| 7907 | // Label 676: @18729 |
| 7908 | GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(18766), // Rule ID 496 // |
| 7909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7910 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpmsumd), |
| 7911 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7913 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7915 | // (intrinsic_wo_chain:{ *:[v2i64] } 9527:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPMSUMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPMSUMD), |
| 7917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7918 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7919 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7920 | GIR_RootConstrainSelectedInstOperands, |
| 7921 | // GIR_Coverage, 496, |
| 7922 | GIR_EraseRootFromParent_Done, |
| 7923 | // Label 677: @18766 |
| 7924 | GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(18803), // Rule ID 504 // |
| 7925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 7926 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vbpermq), |
| 7927 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7928 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7929 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7931 | // (intrinsic_wo_chain:{ *:[v2i64] } 9578:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VBPERMQ:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 7932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VBPERMQ), |
| 7933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7934 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7935 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7936 | GIR_RootConstrainSelectedInstOperands, |
| 7937 | // GIR_Coverage, 504, |
| 7938 | GIR_EraseRootFromParent_Done, |
| 7939 | // Label 678: @18803 |
| 7940 | GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(18840), // Rule ID 507 // |
| 7941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 7942 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vcipher), |
| 7943 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7944 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7945 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7947 | // (intrinsic_wo_chain:{ *:[v2i64] } 9520:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCIPHER), |
| 7949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7950 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7951 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7952 | GIR_RootConstrainSelectedInstOperands, |
| 7953 | // GIR_Coverage, 507, |
| 7954 | GIR_EraseRootFromParent_Done, |
| 7955 | // Label 679: @18840 |
| 7956 | GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(18877), // Rule ID 508 // |
| 7957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 7958 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vcipherlast), |
| 7959 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7963 | // (intrinsic_wo_chain:{ *:[v2i64] } 9521:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCIPHERLAST), |
| 7965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7966 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7967 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7968 | GIR_RootConstrainSelectedInstOperands, |
| 7969 | // GIR_Coverage, 508, |
| 7970 | GIR_EraseRootFromParent_Done, |
| 7971 | // Label 680: @18877 |
| 7972 | GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(18914), // Rule ID 509 // |
| 7973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 7974 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vncipher), |
| 7975 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7976 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7977 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7979 | // (intrinsic_wo_chain:{ *:[v2i64] } 9522:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VNCIPHER:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNCIPHER), |
| 7981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7982 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7983 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 7984 | GIR_RootConstrainSelectedInstOperands, |
| 7985 | // GIR_Coverage, 509, |
| 7986 | GIR_EraseRootFromParent_Done, |
| 7987 | // Label 681: @18914 |
| 7988 | GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(18951), // Rule ID 510 // |
| 7989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 7990 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vncipherlast), |
| 7991 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7992 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7993 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 7995 | // (intrinsic_wo_chain:{ *:[v2i64] } 9523:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VNCIPHERLAST:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 7996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNCIPHERLAST), |
| 7997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 7998 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 7999 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8000 | GIR_RootConstrainSelectedInstOperands, |
| 8001 | // GIR_Coverage, 510, |
| 8002 | GIR_EraseRootFromParent_Done, |
| 8003 | // Label 682: @18951 |
| 8004 | GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(18988), // Rule ID 543 // |
| 8005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8006 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vbpermd), |
| 8007 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8009 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8011 | // (intrinsic_wo_chain:{ *:[v2i64] } 9577:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VBPERMD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 8012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VBPERMD), |
| 8013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8014 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8015 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8016 | GIR_RootConstrainSelectedInstOperands, |
| 8017 | // GIR_Coverage, 543, |
| 8018 | GIR_EraseRootFromParent_Done, |
| 8019 | // Label 683: @18988 |
| 8020 | GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(19025), // Rule ID 544 // |
| 8021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlwnm), |
| 8023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8027 | // (intrinsic_wo_chain:{ *:[v4i32] } 9775:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VRLWNM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 8028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLWNM), |
| 8029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8030 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8031 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8032 | GIR_RootConstrainSelectedInstOperands, |
| 8033 | // GIR_Coverage, 544, |
| 8034 | GIR_EraseRootFromParent_Done, |
| 8035 | // Label 684: @19025 |
| 8036 | GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(19062), // Rule ID 546 // |
| 8037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8038 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrldnm), |
| 8039 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8041 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8043 | // (intrinsic_wo_chain:{ *:[v2i64] } 9769:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VRLDNM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLDNM), |
| 8045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8046 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8047 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8048 | GIR_RootConstrainSelectedInstOperands, |
| 8049 | // GIR_Coverage, 546, |
| 8050 | GIR_EraseRootFromParent_Done, |
| 8051 | // Label 685: @19062 |
| 8052 | GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(19099), // Rule ID 548 // |
| 8053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8054 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vslv), |
| 8055 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8056 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8057 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8059 | // (intrinsic_wo_chain:{ *:[v16i8] } 9783:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSLV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 8060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLV), |
| 8061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8062 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8063 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8064 | GIR_RootConstrainSelectedInstOperands, |
| 8065 | // GIR_Coverage, 548, |
| 8066 | GIR_EraseRootFromParent_Done, |
| 8067 | // Label 686: @19099 |
| 8068 | GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(19136), // Rule ID 549 // |
| 8069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8070 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrv), |
| 8071 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8072 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8073 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8075 | // (intrinsic_wo_chain:{ *:[v16i8] } 9793:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VSRV:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 8076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRV), |
| 8077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8078 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8079 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8080 | GIR_RootConstrainSelectedInstOperands, |
| 8081 | // GIR_Coverage, 549, |
| 8082 | GIR_EraseRootFromParent_Done, |
| 8083 | // Label 687: @19136 |
| 8084 | GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(19173), // Rule ID 550 // |
| 8085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8086 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsdub), |
| 8087 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8088 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8089 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8091 | // (intrinsic_wo_chain:{ *:[v16i8] } 9558:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VABSDUB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 8092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUB), |
| 8093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8094 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8095 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8096 | GIR_RootConstrainSelectedInstOperands, |
| 8097 | // GIR_Coverage, 550, |
| 8098 | GIR_EraseRootFromParent_Done, |
| 8099 | // Label 688: @19173 |
| 8100 | GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(19210), // Rule ID 551 // |
| 8101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsduh), |
| 8103 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8107 | // (intrinsic_wo_chain:{ *:[v8i16] } 9559:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VABSDUH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 8108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUH), |
| 8109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8110 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8111 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8112 | GIR_RootConstrainSelectedInstOperands, |
| 8113 | // GIR_Coverage, 551, |
| 8114 | GIR_EraseRootFromParent_Done, |
| 8115 | // Label 689: @19210 |
| 8116 | GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(19247), // Rule ID 552 // |
| 8117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 8118 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vabsduw), |
| 8119 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8120 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8121 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8123 | // (intrinsic_wo_chain:{ *:[v4i32] } 9560:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VABSDUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 8124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VABSDUW), |
| 8125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8126 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8127 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8128 | GIR_RootConstrainSelectedInstOperands, |
| 8129 | // GIR_Coverage, 552, |
| 8130 | GIR_EraseRootFromParent_Done, |
| 8131 | // Label 690: @19247 |
| 8132 | GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(19284), // Rule ID 1098 // |
| 8133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8134 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpdepd), |
| 8135 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8136 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8137 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8139 | // (intrinsic_wo_chain:{ *:[v2i64] } 9745:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPDEPD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPDEPD), |
| 8141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8142 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8143 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8144 | GIR_RootConstrainSelectedInstOperands, |
| 8145 | // GIR_Coverage, 1098, |
| 8146 | GIR_EraseRootFromParent_Done, |
| 8147 | // Label 691: @19284 |
| 8148 | GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(19321), // Rule ID 1099 // |
| 8149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8150 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpextd), |
| 8151 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8152 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8153 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8154 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8155 | // (intrinsic_wo_chain:{ *:[v2i64] } 9747:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPEXTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPEXTD), |
| 8157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8158 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8159 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8160 | GIR_RootConstrainSelectedInstOperands, |
| 8161 | // GIR_Coverage, 1099, |
| 8162 | GIR_EraseRootFromParent_Done, |
| 8163 | // Label 692: @19321 |
| 8164 | GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(19358), // Rule ID 1100 // |
| 8165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8166 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_pdepd), |
| 8167 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 8168 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8169 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 8170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 8171 | // (intrinsic_wo_chain:{ *:[i64] } 10007:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (PDEPD:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 8172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PDEPD), |
| 8173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 8174 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 8175 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 8176 | GIR_RootConstrainSelectedInstOperands, |
| 8177 | // GIR_Coverage, 1100, |
| 8178 | GIR_EraseRootFromParent_Done, |
| 8179 | // Label 693: @19358 |
| 8180 | GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(19395), // Rule ID 1101 // |
| 8181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8182 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_pextd), |
| 8183 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 8184 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8185 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 8186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 8187 | // (intrinsic_wo_chain:{ *:[i64] } 10008:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (PEXTD:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 8188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PEXTD), |
| 8189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 8190 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 8191 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 8192 | GIR_RootConstrainSelectedInstOperands, |
| 8193 | // GIR_Coverage, 1101, |
| 8194 | GIR_EraseRootFromParent_Done, |
| 8195 | // Label 694: @19395 |
| 8196 | GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(19432), // Rule ID 1102 // |
| 8197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8198 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vcfuged), |
| 8199 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8200 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8201 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8203 | // (intrinsic_wo_chain:{ *:[v2i64] } 9580:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCFUGED:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCFUGED), |
| 8205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8206 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8207 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8208 | GIR_RootConstrainSelectedInstOperands, |
| 8209 | // GIR_Coverage, 1102, |
| 8210 | GIR_EraseRootFromParent_Done, |
| 8211 | // Label 695: @19432 |
| 8212 | GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(19469), // Rule ID 1104 // |
| 8213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8214 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cfuged), |
| 8215 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 8216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8217 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 8218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 8219 | // (intrinsic_wo_chain:{ *:[i64] } 9841:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CFUGED:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 8220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CFUGED), |
| 8221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 8222 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 8223 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 8224 | GIR_RootConstrainSelectedInstOperands, |
| 8225 | // GIR_Coverage, 1104, |
| 8226 | GIR_EraseRootFromParent_Done, |
| 8227 | // Label 696: @19469 |
| 8228 | GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(19506), // Rule ID 1106 // |
| 8229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8230 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclzdm), |
| 8231 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8233 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8235 | // (intrinsic_wo_chain:{ *:[v2i64] } 9584:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCLZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLZDM), |
| 8237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8238 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8239 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8240 | GIR_RootConstrainSelectedInstOperands, |
| 8241 | // GIR_Coverage, 1106, |
| 8242 | GIR_EraseRootFromParent_Done, |
| 8243 | // Label 697: @19506 |
| 8244 | GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(19543), // Rule ID 1107 // |
| 8245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8246 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vctzdm), |
| 8247 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8248 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8249 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8251 | // (intrinsic_wo_chain:{ *:[v2i64] } 9642:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VCTZDM:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCTZDM), |
| 8253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8254 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8255 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8256 | GIR_RootConstrainSelectedInstOperands, |
| 8257 | // GIR_Coverage, 1107, |
| 8258 | GIR_EraseRootFromParent_Done, |
| 8259 | // Label 698: @19543 |
| 8260 | GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(19580), // Rule ID 1108 // |
| 8261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8262 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cntlzdm), |
| 8263 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 8264 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8265 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 8266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 8267 | // (intrinsic_wo_chain:{ *:[i64] } 9846:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CNTLZDM:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 8268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CNTLZDM), |
| 8269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 8270 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 8271 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 8272 | GIR_RootConstrainSelectedInstOperands, |
| 8273 | // GIR_Coverage, 1108, |
| 8274 | GIR_EraseRootFromParent_Done, |
| 8275 | // Label 699: @19580 |
| 8276 | GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(19617), // Rule ID 1109 // |
| 8277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8278 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_cnttzdm), |
| 8279 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 8280 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8281 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 8282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 8283 | // (intrinsic_wo_chain:{ *:[i64] } 9847:{ *:[iPTR] }, i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) => (CNTTZDM:{ *:[i64] } i64:{ *:[i64] }:$RST, i64:{ *:[i64] }:$RB) |
| 8284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CNTTZDM), |
| 8285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 8286 | GIR_RootToRootCopy, /*OpIdx*/2, // RST |
| 8287 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 8288 | GIR_RootConstrainSelectedInstOperands, |
| 8289 | // GIR_Coverage, 1109, |
| 8290 | GIR_EraseRootFromParent_Done, |
| 8291 | // Label 700: @19617 |
| 8292 | GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(19654), // Rule ID 1110 // |
| 8293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8294 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclrlb), |
| 8295 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8296 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8297 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 8298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8299 | // (intrinsic_wo_chain:{ *:[v16i8] } 9582:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) => (VCLRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) |
| 8300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLRLB), |
| 8301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8302 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8303 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8304 | GIR_RootConstrainSelectedInstOperands, |
| 8305 | // GIR_Coverage, 1110, |
| 8306 | GIR_EraseRootFromParent_Done, |
| 8307 | // Label 701: @19654 |
| 8308 | GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(19691), // Rule ID 1111 // |
| 8309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8310 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vclrrb), |
| 8311 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8313 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 8314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8315 | // (intrinsic_wo_chain:{ *:[v16i8] } 9583:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) => (VCLRRB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VA, i32:{ *:[i32] }:$VB) |
| 8316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VCLRRB), |
| 8317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8318 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8319 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8320 | GIR_RootConstrainSelectedInstOperands, |
| 8321 | // GIR_Coverage, 1111, |
| 8322 | GIR_EraseRootFromParent_Done, |
| 8323 | // Label 702: @19691 |
| 8324 | GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(19728), // Rule ID 1125 // |
| 8325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8326 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesw), |
| 8327 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8328 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8329 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8331 | // (intrinsic_wo_chain:{ *:[v4i32] } 9646:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVESW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 8332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESW), |
| 8333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8334 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8335 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8336 | GIR_RootConstrainSelectedInstOperands, |
| 8337 | // GIR_Coverage, 1125, |
| 8338 | GIR_EraseRootFromParent_Done, |
| 8339 | // Label 703: @19728 |
| 8340 | GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(19765), // Rule ID 1126 // |
| 8341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8342 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveuw), |
| 8343 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8344 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8345 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8347 | // (intrinsic_wo_chain:{ *:[v4i32] } 9649:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VDIVEUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 8348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUW), |
| 8349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8350 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8351 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8352 | GIR_RootConstrainSelectedInstOperands, |
| 8353 | // GIR_Coverage, 1126, |
| 8354 | GIR_EraseRootFromParent_Done, |
| 8355 | // Label 704: @19765 |
| 8356 | GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(19802), // Rule ID 1127 // |
| 8357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8358 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesd), |
| 8359 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8361 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8363 | // (intrinsic_wo_chain:{ *:[v2i64] } 9644:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVESD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESD), |
| 8365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8366 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8367 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8368 | GIR_RootConstrainSelectedInstOperands, |
| 8369 | // GIR_Coverage, 1127, |
| 8370 | GIR_EraseRootFromParent_Done, |
| 8371 | // Label 705: @19802 |
| 8372 | GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(19839), // Rule ID 1128 // |
| 8373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8374 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveud), |
| 8375 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8376 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8377 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8379 | // (intrinsic_wo_chain:{ *:[v2i64] } 9647:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VDIVEUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUD), |
| 8381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8382 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8383 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8384 | GIR_RootConstrainSelectedInstOperands, |
| 8385 | // GIR_Coverage, 1128, |
| 8386 | GIR_EraseRootFromParent_Done, |
| 8387 | // Label 706: @19839 |
| 8388 | GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(19876), // Rule ID 1131 // |
| 8389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8390 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulesd), |
| 8391 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8393 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8395 | // (intrinsic_wo_chain:{ *:[v1i128] } 9725:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULESD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULESD), |
| 8397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8398 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8399 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8400 | GIR_RootConstrainSelectedInstOperands, |
| 8401 | // GIR_Coverage, 1131, |
| 8402 | GIR_EraseRootFromParent_Done, |
| 8403 | // Label 707: @19876 |
| 8404 | GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(19913), // Rule ID 1132 // |
| 8405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8406 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuleud), |
| 8407 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8408 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8409 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8411 | // (intrinsic_wo_chain:{ *:[v1i128] } 9729:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULEUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULEUD), |
| 8413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8414 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8415 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8416 | GIR_RootConstrainSelectedInstOperands, |
| 8417 | // GIR_Coverage, 1132, |
| 8418 | GIR_EraseRootFromParent_Done, |
| 8419 | // Label 708: @19913 |
| 8420 | GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(19950), // Rule ID 1133 // |
| 8421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8422 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulosd), |
| 8423 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8424 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8425 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8427 | // (intrinsic_wo_chain:{ *:[v1i128] } 9737:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULOSD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOSD), |
| 8429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8430 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8431 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8432 | GIR_RootConstrainSelectedInstOperands, |
| 8433 | // GIR_Coverage, 1133, |
| 8434 | GIR_EraseRootFromParent_Done, |
| 8435 | // Label 709: @19950 |
| 8436 | GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(19987), // Rule ID 1134 // |
| 8437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8438 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmuloud), |
| 8439 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8441 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8443 | // (intrinsic_wo_chain:{ *:[v1i128] } 9741:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULOUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 8444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULOUD), |
| 8445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8446 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8447 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8448 | GIR_RootConstrainSelectedInstOperands, |
| 8449 | // GIR_Coverage, 1134, |
| 8450 | GIR_EraseRootFromParent_Done, |
| 8451 | // Label 710: @19987 |
| 8452 | GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(20024), // Rule ID 1138 // |
| 8453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8454 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdivesq), |
| 8455 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 8457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 8458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8459 | // (intrinsic_wo_chain:{ *:[v1i128] } 9645:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVESQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 8460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVESQ), |
| 8461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8462 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8463 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8464 | GIR_RootConstrainSelectedInstOperands, |
| 8465 | // GIR_Coverage, 1138, |
| 8466 | GIR_EraseRootFromParent_Done, |
| 8467 | // Label 711: @20024 |
| 8468 | GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(20061), // Rule ID 1139 // |
| 8469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8470 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vdiveuq), |
| 8471 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 8473 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 8474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8475 | // (intrinsic_wo_chain:{ *:[v1i128] } 9648:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VDIVEUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 8476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VDIVEUQ), |
| 8477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8478 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8479 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8480 | GIR_RootConstrainSelectedInstOperands, |
| 8481 | // GIR_Coverage, 1139, |
| 8482 | GIR_EraseRootFromParent_Done, |
| 8483 | // Label 712: @20061 |
| 8484 | GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(20098), // Rule ID 1149 // |
| 8485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8486 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlqnm), |
| 8487 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8488 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 8489 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 8490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8491 | // (intrinsic_wo_chain:{ *:[v1i128] } 9772:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) => (VRLQNM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB) |
| 8492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLQNM), |
| 8493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8494 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 8495 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 8496 | GIR_RootConstrainSelectedInstOperands, |
| 8497 | // GIR_Coverage, 1149, |
| 8498 | GIR_EraseRootFromParent_Done, |
| 8499 | // Label 713: @20098 |
| 8500 | GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(20135), // Rule ID 3322 // |
| 8501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhsw), |
| 8503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8507 | // (intrinsic_wo_chain:{ *:[v4i32] } 9733:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 8508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHSW), |
| 8509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8510 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 8511 | GIR_RootToRootCopy, /*OpIdx*/3, // vB |
| 8512 | GIR_RootConstrainSelectedInstOperands, |
| 8513 | // GIR_Coverage, 3322, |
| 8514 | GIR_EraseRootFromParent_Done, |
| 8515 | // Label 714: @20135 |
| 8516 | GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(20172), // Rule ID 3323 // |
| 8517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8518 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhuw), |
| 8519 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8523 | // (intrinsic_wo_chain:{ *:[v4i32] } 9735:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VMULHUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 8524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHUW), |
| 8525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8526 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 8527 | GIR_RootToRootCopy, /*OpIdx*/3, // vB |
| 8528 | GIR_RootConstrainSelectedInstOperands, |
| 8529 | // GIR_Coverage, 3323, |
| 8530 | GIR_EraseRootFromParent_Done, |
| 8531 | // Label 715: @20172 |
| 8532 | GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(20209), // Rule ID 3324 // |
| 8533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8534 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhsd), |
| 8535 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8536 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8537 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8539 | // (intrinsic_wo_chain:{ *:[v2i64] } 9732:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHSD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) |
| 8540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHSD), |
| 8541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8542 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 8543 | GIR_RootToRootCopy, /*OpIdx*/3, // vB |
| 8544 | GIR_RootConstrainSelectedInstOperands, |
| 8545 | // GIR_Coverage, 3324, |
| 8546 | GIR_EraseRootFromParent_Done, |
| 8547 | // Label 716: @20209 |
| 8548 | GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(20246), // Rule ID 3325 // |
| 8549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 8550 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmulhud), |
| 8551 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8552 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8553 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8555 | // (intrinsic_wo_chain:{ *:[v2i64] } 9734:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VMULHUD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) |
| 8556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMULHUD), |
| 8557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 8558 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 8559 | GIR_RootToRootCopy, /*OpIdx*/3, // vB |
| 8560 | GIR_RootConstrainSelectedInstOperands, |
| 8561 | // GIR_Coverage, 3325, |
| 8562 | GIR_EraseRootFromParent_Done, |
| 8563 | // Label 717: @20246 |
| 8564 | GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(20321), // Rule ID 3490 // |
| 8565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8566 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8), |
| 8567 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8569 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8571 | // (intrinsic_wo_chain:{ *:[v512i1] } 9987:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8572 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8573 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8574 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8575 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8576 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8577 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8578 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8579 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8580 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8), |
| 8583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8585 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8586 | GIR_RootConstrainSelectedInstOperands, |
| 8587 | // GIR_Coverage, 3490, |
| 8588 | GIR_EraseRootFromParent_Done, |
| 8589 | // Label 718: @20321 |
| 8590 | GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(20396), // Rule ID 3492 // |
| 8591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8592 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4), |
| 8593 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8595 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8597 | // (intrinsic_wo_chain:{ *:[v512i1] } 9989:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8598 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8599 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8600 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8601 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8602 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8603 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8604 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8605 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8606 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4), |
| 8609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8610 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8612 | GIR_RootConstrainSelectedInstOperands, |
| 8613 | // GIR_Coverage, 3492, |
| 8614 | GIR_EraseRootFromParent_Done, |
| 8615 | // Label 719: @20396 |
| 8616 | GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(20471), // Rule ID 3494 // |
| 8617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8618 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2s), |
| 8619 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8620 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8621 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8623 | // (intrinsic_wo_chain:{ *:[v512i1] } 9985:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2S:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8624 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8625 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8626 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8627 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8628 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8629 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8630 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8631 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8632 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2S), |
| 8635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8638 | GIR_RootConstrainSelectedInstOperands, |
| 8639 | // GIR_Coverage, 3494, |
| 8640 | GIR_EraseRootFromParent_Done, |
| 8641 | // Label 720: @20471 |
| 8642 | GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(20546), // Rule ID 3496 // |
| 8643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8644 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8), |
| 8645 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8646 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8647 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8649 | // (intrinsic_wo_chain:{ *:[v512i1] } 9987:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8651 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8652 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8653 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8654 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8656 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8657 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8658 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8W), |
| 8661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8664 | GIR_RootConstrainSelectedInstOperands, |
| 8665 | // GIR_Coverage, 3496, |
| 8666 | GIR_EraseRootFromParent_Done, |
| 8667 | // Label 721: @20546 |
| 8668 | GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(20621), // Rule ID 3498 // |
| 8669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8670 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4), |
| 8671 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8673 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8675 | // (intrinsic_wo_chain:{ *:[v512i1] } 9989:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8676 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8677 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8678 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8679 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8680 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8681 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8682 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8683 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8684 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8685 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4W), |
| 8687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8688 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8689 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8690 | GIR_RootConstrainSelectedInstOperands, |
| 8691 | // GIR_Coverage, 3498, |
| 8692 | GIR_EraseRootFromParent_Done, |
| 8693 | // Label 722: @20621 |
| 8694 | GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(20696), // Rule ID 3500 // |
| 8695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8696 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2s), |
| 8697 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8698 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8699 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8701 | // (intrinsic_wo_chain:{ *:[v512i1] } 9985:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8702 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8703 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8704 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8705 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8706 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8710 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SW), |
| 8713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8714 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8715 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8716 | GIR_RootConstrainSelectedInstOperands, |
| 8717 | // GIR_Coverage, 3500, |
| 8718 | GIR_EraseRootFromParent_Done, |
| 8719 | // Label 723: @20696 |
| 8720 | GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(20771), // Rule ID 3502 // |
| 8721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8722 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2), |
| 8723 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8724 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8725 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8727 | // (intrinsic_wo_chain:{ *:[v512i1] } 9968:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8729 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8730 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8731 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8732 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8736 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2), |
| 8739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8740 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8742 | GIR_RootConstrainSelectedInstOperands, |
| 8743 | // GIR_Coverage, 3502, |
| 8744 | GIR_EraseRootFromParent_Done, |
| 8745 | // Label 724: @20771 |
| 8746 | GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(20846), // Rule ID 3507 // |
| 8747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8748 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2), |
| 8749 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8750 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8751 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8753 | // (intrinsic_wo_chain:{ *:[v512i1] } 9968:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8754 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8755 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8756 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8757 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8758 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8760 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8761 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8762 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2W), |
| 8765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8768 | GIR_RootConstrainSelectedInstOperands, |
| 8769 | // GIR_Coverage, 3507, |
| 8770 | GIR_EraseRootFromParent_Done, |
| 8771 | // Label 725: @20846 |
| 8772 | GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(20921), // Rule ID 3512 // |
| 8773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8774 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32ger), |
| 8775 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8779 | // (intrinsic_wo_chain:{ *:[v512i1] } 9973:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GER:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8780 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8781 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8782 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8783 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8784 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8785 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8786 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8787 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8788 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GER), |
| 8791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8792 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8793 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8794 | GIR_RootConstrainSelectedInstOperands, |
| 8795 | // GIR_Coverage, 3512, |
| 8796 | GIR_EraseRootFromParent_Done, |
| 8797 | // Label 726: @20921 |
| 8798 | GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(20977), // Rule ID 3517 // |
| 8799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8800 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64ger), |
| 8801 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8802 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, |
| 8803 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8805 | // (intrinsic_wo_chain:{ *:[v512i1] } 9978:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GER:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8809 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GER), |
| 8812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8813 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 8814 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8815 | GIR_RootConstrainSelectedInstOperands, |
| 8816 | // GIR_Coverage, 3517, |
| 8817 | GIR_EraseRootFromParent_Done, |
| 8818 | // Label 727: @20977 |
| 8819 | GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(21052), // Rule ID 3522 // |
| 8820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8821 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2), |
| 8822 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8823 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8824 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8826 | // (intrinsic_wo_chain:{ *:[v512i1] } 9963:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8827 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8828 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8829 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8830 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8831 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8834 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8835 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2), |
| 8838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8839 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8840 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8841 | GIR_RootConstrainSelectedInstOperands, |
| 8842 | // GIR_Coverage, 3522, |
| 8843 | GIR_EraseRootFromParent_Done, |
| 8844 | // Label 728: @21052 |
| 8845 | GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(21127), // Rule ID 3527 // |
| 8846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 8847 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2), |
| 8848 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8849 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8850 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 8852 | // (intrinsic_wo_chain:{ *:[v512i1] } 9983:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8853 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8854 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8855 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8856 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8857 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8859 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8860 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8861 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2), |
| 8864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8865 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8866 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8867 | GIR_RootConstrainSelectedInstOperands, |
| 8868 | // GIR_Coverage, 3527, |
| 8869 | GIR_EraseRootFromParent_Done, |
| 8870 | // Label 729: @21127 |
| 8871 | GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(21202), // Rule ID 3530 // |
| 8872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8873 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32ger), |
| 8874 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8875 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8876 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8878 | // (intrinsic_wo_chain:{ *:[v512i1] } 9973:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8880 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8881 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8882 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8883 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8885 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8886 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8887 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERW), |
| 8890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8891 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8892 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8893 | GIR_RootConstrainSelectedInstOperands, |
| 8894 | // GIR_Coverage, 3530, |
| 8895 | GIR_EraseRootFromParent_Done, |
| 8896 | // Label 730: @21202 |
| 8897 | GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(21258), // Rule ID 3535 // |
| 8898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8899 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64ger), |
| 8900 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8901 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, |
| 8902 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8904 | // (intrinsic_wo_chain:{ *:[v512i1] } 9978:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERW:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8905 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8906 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8907 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8908 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8909 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERW), |
| 8911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8912 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 8913 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8914 | GIR_RootConstrainSelectedInstOperands, |
| 8915 | // GIR_Coverage, 3535, |
| 8916 | GIR_EraseRootFromParent_Done, |
| 8917 | // Label 731: @21258 |
| 8918 | GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(21333), // Rule ID 3540 // |
| 8919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8920 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2), |
| 8921 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8923 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8925 | // (intrinsic_wo_chain:{ *:[v512i1] } 9963:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8926 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8927 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8928 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8929 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8930 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8933 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8934 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8935 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2W), |
| 8937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8938 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8940 | GIR_RootConstrainSelectedInstOperands, |
| 8941 | // GIR_Coverage, 3540, |
| 8942 | GIR_EraseRootFromParent_Done, |
| 8943 | // Label 732: @21333 |
| 8944 | GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(21408), // Rule ID 3545 // |
| 8945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 8946 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2), |
| 8947 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 8948 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8949 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 8951 | // (intrinsic_wo_chain:{ *:[v512i1] } 9983:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 8952 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 8953 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 8954 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8955 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8956 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 8957 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8958 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8959 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8960 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 8961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2W), |
| 8963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 8964 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8965 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8966 | GIR_RootConstrainSelectedInstOperands, |
| 8967 | // GIR_Coverage, 3545, |
| 8968 | GIR_EraseRootFromParent_Done, |
| 8969 | // Label 733: @21408 |
| 8970 | GIM_Reject, |
| 8971 | // Label 543: @21409 |
| 8972 | GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(27845), |
| 8973 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 8974 | GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(21475), // Rule ID 1001 // |
| 8975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 8976 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd), |
| 8977 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 8978 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 8979 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 8980 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 8981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 8982 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 8983 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 8984 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 8985 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8986 | // (intrinsic_wo_chain:{ *:[f128] } 9891:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 8987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQPO), |
| 8988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 8989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi |
| 8990 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 8991 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 8992 | GIR_RootConstrainSelectedInstOperands, |
| 8993 | // GIR_Coverage, 1001, |
| 8994 | GIR_EraseRootFromParent_Done, |
| 8995 | // Label 735: @21475 |
| 8996 | GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(21528), // Rule ID 2153 // |
| 8997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 8998 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxinsertw), |
| 8999 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9002 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 9004 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 9005 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9006 | // MIs[1] Operand 1 |
| 9007 | // No operand predicates |
| 9008 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9009 | // (intrinsic_wo_chain:{ *:[v4i32] } 10135:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v2i64:{ *:[v2i64] }:$B, (imm:{ *:[i32] }):$IMM) => (XXINSERTW:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v2i64] }:$B, (imm:{ *:[i32] }):$IMM) |
| 9010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXINSERTW), |
| 9011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 9012 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 9013 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 9014 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // IMM |
| 9015 | GIR_RootConstrainSelectedInstOperands, |
| 9016 | // GIR_Coverage, 2153, |
| 9017 | GIR_EraseRootFromParent_Done, |
| 9018 | // Label 736: @21528 |
| 9019 | GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(21570), // Rule ID 1000 // |
| 9020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 9021 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd), |
| 9022 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 9023 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 9024 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 9025 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 9026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9027 | // (intrinsic_wo_chain:{ *:[f128] } 9891:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 9028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQPO), |
| 9029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 9030 | GIR_RootToRootCopy, /*OpIdx*/4, // RSTi |
| 9031 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9032 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9033 | GIR_RootConstrainSelectedInstOperands, |
| 9034 | // GIR_Coverage, 1000, |
| 9035 | GIR_EraseRootFromParent_Done, |
| 9036 | // Label 737: @21570 |
| 9037 | GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(21612), // Rule ID 1734 // |
| 9038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 9039 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsub), |
| 9040 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 9041 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9042 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9043 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 9045 | // (intrinsic_wo_chain:{ *:[f64] } 9892:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (XSMSUBMDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) |
| 9046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBMDP), |
| 9047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 9048 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 9049 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 9050 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 9051 | GIR_RootConstrainSelectedInstOperands, |
| 9052 | // GIR_Coverage, 1734, |
| 9053 | GIR_EraseRootFromParent_Done, |
| 9054 | // Label 738: @21612 |
| 9055 | GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(21654), // Rule ID 1735 // |
| 9056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 9057 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadd), |
| 9058 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 9059 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9060 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9061 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 9063 | // (intrinsic_wo_chain:{ *:[f64] } 9896:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (XSNMADDMDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) |
| 9064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDMDP), |
| 9065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 9066 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 9067 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 9068 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 9069 | GIR_RootConstrainSelectedInstOperands, |
| 9070 | // GIR_Coverage, 1735, |
| 9071 | GIR_EraseRootFromParent_Done, |
| 9072 | // Label 739: @21654 |
| 9073 | GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(21696), // Rule ID 1921 // |
| 9074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 9075 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsubs), |
| 9076 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 9077 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9078 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9079 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 9081 | // (intrinsic_wo_chain:{ *:[f32] } 9893:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (XSMSUBMSP:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) |
| 9082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBMSP), |
| 9083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 9084 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 9085 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 9086 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 9087 | GIR_RootConstrainSelectedInstOperands, |
| 9088 | // GIR_Coverage, 1921, |
| 9089 | GIR_EraseRootFromParent_Done, |
| 9090 | // Label 740: @21696 |
| 9091 | GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(21738), // Rule ID 1922 // |
| 9092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 9093 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadds), |
| 9094 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 9095 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9096 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9097 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 9099 | // (intrinsic_wo_chain:{ *:[f32] } 9897:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (XSNMADDMSP:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) |
| 9100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDMSP), |
| 9101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 9102 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 9103 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 9104 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 9105 | GIR_RootConstrainSelectedInstOperands, |
| 9106 | // GIR_Coverage, 1922, |
| 9107 | GIR_EraseRootFromParent_Done, |
| 9108 | // Label 741: @21738 |
| 9109 | GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(21780), // Rule ID 505 // |
| 9110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 9111 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vshasigmaw), |
| 9112 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9113 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9115 | // MIs[0] ST |
| 9116 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 9117 | // MIs[0] SIX |
| 9118 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9119 | // (intrinsic_wo_chain:{ *:[v4i32] } 9532:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) |
| 9120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSHASIGMAW), |
| 9121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9122 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 9123 | GIR_RootToRootCopy, /*OpIdx*/3, // ST |
| 9124 | GIR_RootToRootCopy, /*OpIdx*/4, // SIX |
| 9125 | GIR_RootConstrainSelectedInstOperands, |
| 9126 | // GIR_Coverage, 505, |
| 9127 | GIR_EraseRootFromParent_Done, |
| 9128 | // Label 742: @21780 |
| 9129 | GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(21822), // Rule ID 506 // |
| 9130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Crypto), |
| 9131 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vshasigmad), |
| 9132 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9133 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9135 | // MIs[0] ST |
| 9136 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 9137 | // MIs[0] SIX |
| 9138 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9139 | // (intrinsic_wo_chain:{ *:[v2i64] } 9531:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) => (VSHASIGMAD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, (timm:{ *:[i32] }):$ST, (timm:{ *:[i32] }):$SIX) |
| 9140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSHASIGMAD), |
| 9141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9142 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 9143 | GIR_RootToRootCopy, /*OpIdx*/3, // ST |
| 9144 | GIR_RootToRootCopy, /*OpIdx*/4, // SIX |
| 9145 | GIR_RootConstrainSelectedInstOperands, |
| 9146 | // GIR_Coverage, 506, |
| 9147 | GIR_EraseRootFromParent_Done, |
| 9148 | // Label 743: @21822 |
| 9149 | GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(21864), // Rule ID 1048 // |
| 9150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9151 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsldbi), |
| 9152 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9153 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9154 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9156 | // MIs[0] SD |
| 9157 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9158 | // (intrinsic_wo_chain:{ *:[v16i8] } 9780:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) => (VSLDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) |
| 9159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLDBI), |
| 9160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 9161 | GIR_RootToRootCopy, /*OpIdx*/2, // VRA |
| 9162 | GIR_RootToRootCopy, /*OpIdx*/3, // VRB |
| 9163 | GIR_RootToRootCopy, /*OpIdx*/4, // SD |
| 9164 | GIR_RootConstrainSelectedInstOperands, |
| 9165 | // GIR_Coverage, 1048, |
| 9166 | GIR_EraseRootFromParent_Done, |
| 9167 | // Label 744: @21864 |
| 9168 | GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(21906), // Rule ID 1049 // |
| 9169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9170 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsrdbi), |
| 9171 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9172 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9173 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9175 | // MIs[0] SD |
| 9176 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9177 | // (intrinsic_wo_chain:{ *:[v16i8] } 9790:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) => (VSRDBI:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VRA, v16i8:{ *:[v16i8] }:$VRB, (timm:{ *:[i32] }):$SD) |
| 9178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRDBI), |
| 9179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 9180 | GIR_RootToRootCopy, /*OpIdx*/2, // VRA |
| 9181 | GIR_RootToRootCopy, /*OpIdx*/3, // VRB |
| 9182 | GIR_RootToRootCopy, /*OpIdx*/4, // SD |
| 9183 | GIR_RootConstrainSelectedInstOperands, |
| 9184 | // GIR_Coverage, 1049, |
| 9185 | GIR_EraseRootFromParent_Done, |
| 9186 | // Label 745: @21906 |
| 9187 | GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(21948), // Rule ID 1054 // |
| 9188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9189 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsw), |
| 9190 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9191 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9192 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9193 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9194 | // MIs[0] VA |
| 9195 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9196 | // (intrinsic_wo_chain:{ *:[v4i32] } 9688:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VB, (timm:{ *:[i32] }):$VA) => (VINSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, (timm:{ *:[i32] }):$VA, i32:{ *:[i32] }:$VB) |
| 9197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSW), |
| 9198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9199 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9200 | GIR_RootToRootCopy, /*OpIdx*/4, // VA |
| 9201 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 9202 | GIR_RootConstrainSelectedInstOperands, |
| 9203 | // GIR_Coverage, 1054, |
| 9204 | GIR_EraseRootFromParent_Done, |
| 9205 | // Label 746: @21948 |
| 9206 | GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(21990), // Rule ID 1055 // |
| 9207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsd), |
| 9209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9213 | // MIs[0] VA |
| 9214 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9215 | // (intrinsic_wo_chain:{ *:[v2i64] } 9681:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VB, (timm:{ *:[i32] }):$VA) => (VINSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, (timm:{ *:[i32] }):$VA, i64:{ *:[i64] }:$VB) |
| 9216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSD), |
| 9217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9218 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9219 | GIR_RootToRootCopy, /*OpIdx*/4, // VA |
| 9220 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 9221 | GIR_RootConstrainSelectedInstOperands, |
| 9222 | // GIR_Coverage, 1055, |
| 9223 | GIR_EraseRootFromParent_Done, |
| 9224 | // Label 747: @21990 |
| 9225 | GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(22035), // Rule ID 1433 // |
| 9226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 9227 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bcdadd), |
| 9228 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9229 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9230 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9232 | // MIs[0] PS |
| 9233 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9234 | // (intrinsic_wo_chain:{ *:[v16i8] } 9835:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$PS) => (BCDADD_rec:{ *:[v16i8] }:{ *:[i32] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB, ?:{ *:[i32] }:$PS) |
| 9235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDADD_rec), |
| 9236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9237 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 9238 | GIR_RootToRootCopy, /*OpIdx*/3, // vB |
| 9239 | GIR_RootToRootCopy, /*OpIdx*/4, // PS |
| 9240 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0, |
| 9241 | GIR_RootConstrainSelectedInstOperands, |
| 9242 | // GIR_Coverage, 1433, |
| 9243 | GIR_EraseRootFromParent_Done, |
| 9244 | // Label 748: @22035 |
| 9245 | GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(22080), // Rule ID 1434 // |
| 9246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 9247 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_bcdsub), |
| 9248 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9249 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9250 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9252 | // MIs[0] PS |
| 9253 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9254 | // (intrinsic_wo_chain:{ *:[v16i8] } 9837:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, (timm:{ *:[i32] }):$PS) => (BCDSUB_rec:{ *:[v16i8] }:{ *:[i32] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB, ?:{ *:[i32] }:$PS) |
| 9255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::BCDSUB_rec), |
| 9256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9257 | GIR_RootToRootCopy, /*OpIdx*/2, // vA |
| 9258 | GIR_RootToRootCopy, /*OpIdx*/3, // vB |
| 9259 | GIR_RootToRootCopy, /*OpIdx*/4, // PS |
| 9260 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR6*/0, |
| 9261 | GIR_RootConstrainSelectedInstOperands, |
| 9262 | // GIR_Coverage, 1434, |
| 9263 | GIR_EraseRootFromParent_Done, |
| 9264 | // Label 749: @22080 |
| 9265 | GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(22134), // Rule ID 1549 // |
| 9266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), |
| 9267 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddhd), |
| 9268 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 9269 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9270 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9271 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9273 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9274 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9275 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9276 | // (intrinsic_wo_chain:{ *:[i64] } 9919:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDHD:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c) |
| 9277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDHD), |
| 9278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9279 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 9280 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 9281 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 9282 | GIR_RootConstrainSelectedInstOperands, |
| 9283 | // GIR_Coverage, 1549, |
| 9284 | GIR_EraseRootFromParent_Done, |
| 9285 | // Label 750: @22134 |
| 9286 | GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(22188), // Rule ID 1550 // |
| 9287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), |
| 9288 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddhdu), |
| 9289 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 9290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9292 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9294 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9295 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9296 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9297 | // (intrinsic_wo_chain:{ *:[i64] } 9920:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDHDU:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c) |
| 9298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDHDU), |
| 9299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9300 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 9301 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 9302 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 9303 | GIR_RootConstrainSelectedInstOperands, |
| 9304 | // GIR_Coverage, 1550, |
| 9305 | GIR_EraseRootFromParent_Done, |
| 9306 | // Label 751: @22188 |
| 9307 | GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(22242), // Rule ID 1551 // |
| 9308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode_IsISA3_0), |
| 9309 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_maddld), |
| 9310 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 9311 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9312 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9313 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9314 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9315 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9316 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9317 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 9318 | // (intrinsic_wo_chain:{ *:[i64] } 9921:{ *:[iPTR] }, g8rc:{ *:[i64] }:$a, g8rc:{ *:[i64] }:$b, g8rc:{ *:[i64] }:$c) => (MADDLD8:{ *:[i64] } ?:{ *:[i64] }:$a, ?:{ *:[i64] }:$b, ?:{ *:[i64] }:$c) |
| 9319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MADDLD8), |
| 9320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9321 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 9322 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 9323 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 9324 | GIR_RootConstrainSelectedInstOperands, |
| 9325 | // GIR_Coverage, 1551, |
| 9326 | GIR_EraseRootFromParent_Done, |
| 9327 | // Label 752: @22242 |
| 9328 | GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(22293), // Rule ID 4804 // |
| 9329 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fsel), |
| 9330 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 9331 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9332 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9333 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 9335 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 9336 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 9337 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 9338 | // (intrinsic_wo_chain:{ *:[f64] } 9903:{ *:[iPTR] }, f8rc:{ *:[f64] }:$FRA, f8rc:{ *:[f64] }:$FRC, f8rc:{ *:[f64] }:$FRB) => (FSELD:{ *:[f64] } ?:{ *:[f64] }:$FRA, ?:{ *:[f64] }:$FRC, ?:{ *:[f64] }:$FRB) |
| 9339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FSELD), |
| 9340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 9341 | GIR_RootToRootCopy, /*OpIdx*/2, // FRA |
| 9342 | GIR_RootToRootCopy, /*OpIdx*/3, // FRC |
| 9343 | GIR_RootToRootCopy, /*OpIdx*/4, // FRB |
| 9344 | GIR_RootConstrainSelectedInstOperands, |
| 9345 | // GIR_Coverage, 4804, |
| 9346 | GIR_EraseRootFromParent_Done, |
| 9347 | // Label 753: @22293 |
| 9348 | GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(22335), // Rule ID 293 // |
| 9349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9350 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmladduhm), |
| 9351 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9353 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9354 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 9355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9356 | // (intrinsic_wo_chain:{ *:[v8i16] } 9715:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMLADDUHM:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) |
| 9357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMLADDUHM), |
| 9358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9359 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9360 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9361 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9362 | GIR_RootConstrainSelectedInstOperands, |
| 9363 | // GIR_Coverage, 293, |
| 9364 | GIR_EraseRootFromParent_Done, |
| 9365 | // Label 754: @22335 |
| 9366 | GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(22377), // Rule ID 294 // |
| 9367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vperm), |
| 9369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9372 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 9373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9374 | // (intrinsic_wo_chain:{ *:[v4i32] } 9746:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v16i8:{ *:[v16i8] }:$RC) => (VPERM:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v16i8:{ *:[v16i8] }:$RC) |
| 9375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERM), |
| 9376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9377 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9378 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9379 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9380 | GIR_RootConstrainSelectedInstOperands, |
| 9381 | // GIR_Coverage, 294, |
| 9382 | GIR_EraseRootFromParent_Done, |
| 9383 | // Label 755: @22377 |
| 9384 | GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(22419), // Rule ID 295 // |
| 9385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9386 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsel), |
| 9387 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9388 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9389 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9390 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9392 | // (intrinsic_wo_chain:{ *:[v4i32] } 9777:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VSEL:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 9393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 9394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9395 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9396 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9397 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9398 | GIR_RootConstrainSelectedInstOperands, |
| 9399 | // GIR_Coverage, 295, |
| 9400 | GIR_EraseRootFromParent_Done, |
| 9401 | // Label 756: @22419 |
| 9402 | GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(22461), // Rule ID 346 // |
| 9403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9404 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsummbm), |
| 9405 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9406 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9407 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9408 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9410 | // (intrinsic_wo_chain:{ *:[v4i32] } 9717:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMMBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 9411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMMBM), |
| 9412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9413 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9414 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9415 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9416 | GIR_RootConstrainSelectedInstOperands, |
| 9417 | // GIR_Coverage, 346, |
| 9418 | GIR_EraseRootFromParent_Done, |
| 9419 | // Label 757: @22461 |
| 9420 | GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(22503), // Rule ID 347 // |
| 9421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9422 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumshm), |
| 9423 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9424 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9425 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9426 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9428 | // (intrinsic_wo_chain:{ *:[v4i32] } 9718:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMSHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 9429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMSHM), |
| 9430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9431 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9432 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9433 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9434 | GIR_RootConstrainSelectedInstOperands, |
| 9435 | // GIR_Coverage, 347, |
| 9436 | GIR_EraseRootFromParent_Done, |
| 9437 | // Label 758: @22503 |
| 9438 | GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(22545), // Rule ID 348 // |
| 9439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9440 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumubm), |
| 9441 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9442 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9443 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9444 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9446 | // (intrinsic_wo_chain:{ *:[v4i32] } 9720:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUBM:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 9447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUBM), |
| 9448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9449 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9450 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9451 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9452 | GIR_RootConstrainSelectedInstOperands, |
| 9453 | // GIR_Coverage, 348, |
| 9454 | GIR_EraseRootFromParent_Done, |
| 9455 | // Label 759: @22545 |
| 9456 | GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(22587), // Rule ID 349 // |
| 9457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 9458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumuhm), |
| 9459 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9462 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9464 | // (intrinsic_wo_chain:{ *:[v4i32] } 9722:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUHM:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 9465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUHM), |
| 9466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9467 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9468 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9469 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9470 | GIR_RootConstrainSelectedInstOperands, |
| 9471 | // GIR_Coverage, 349, |
| 9472 | GIR_EraseRootFromParent_Done, |
| 9473 | // Label 760: @22587 |
| 9474 | GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(22629), // Rule ID 468 // |
| 9475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 9476 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddeuqm), |
| 9477 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 9478 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 9479 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 9480 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 9481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9482 | // (intrinsic_wo_chain:{ *:[v1i128] } 9564:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VADDEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) |
| 9483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDEUQM), |
| 9484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9485 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9486 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9487 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9488 | GIR_RootConstrainSelectedInstOperands, |
| 9489 | // GIR_Coverage, 468, |
| 9490 | GIR_EraseRootFromParent_Done, |
| 9491 | // Label 761: @22629 |
| 9492 | GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(22671), // Rule ID 470 // |
| 9493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 9494 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vaddecuq), |
| 9495 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 9496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 9497 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 9498 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 9499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9500 | // (intrinsic_wo_chain:{ *:[v1i128] } 9563:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VADDECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) |
| 9501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VADDECUQ), |
| 9502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9503 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9504 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9505 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9506 | GIR_RootConstrainSelectedInstOperands, |
| 9507 | // GIR_Coverage, 470, |
| 9508 | GIR_EraseRootFromParent_Done, |
| 9509 | // Label 762: @22671 |
| 9510 | GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(22713), // Rule ID 473 // |
| 9511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 9512 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubeuqm), |
| 9513 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 9514 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 9515 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 9516 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 9517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9518 | // (intrinsic_wo_chain:{ *:[v1i128] } 9806:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VSUBEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) |
| 9519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBEUQM), |
| 9520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9521 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9522 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9523 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9524 | GIR_RootConstrainSelectedInstOperands, |
| 9525 | // GIR_Coverage, 473, |
| 9526 | GIR_EraseRootFromParent_Done, |
| 9527 | // Label 763: @22713 |
| 9528 | GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(22755), // Rule ID 475 // |
| 9529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 9530 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsubecuq), |
| 9531 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 9532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 9533 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 9534 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 9535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9536 | // (intrinsic_wo_chain:{ *:[v1i128] } 9805:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VSUBECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$RA, v1i128:{ *:[v1i128] }:$RB, v1i128:{ *:[v1i128] }:$RC) |
| 9537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUBECUQ), |
| 9538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9539 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9540 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9541 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9542 | GIR_RootConstrainSelectedInstOperands, |
| 9543 | // GIR_Coverage, 475, |
| 9544 | GIR_EraseRootFromParent_Done, |
| 9545 | // Label 764: @22755 |
| 9546 | GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(22797), // Rule ID 512 // |
| 9547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 9548 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumudm), |
| 9549 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 9550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9551 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9552 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 9553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9554 | // (intrinsic_wo_chain:{ *:[v1i128] } 9721:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VMSUMUDM:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) |
| 9555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUDM), |
| 9556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9557 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9558 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9559 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9560 | GIR_RootConstrainSelectedInstOperands, |
| 9561 | // GIR_Coverage, 512, |
| 9562 | GIR_EraseRootFromParent_Done, |
| 9563 | // Label 765: @22797 |
| 9564 | GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(22839), // Rule ID 545 // |
| 9565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 9566 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlwmi), |
| 9567 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9569 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9570 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9572 | // (intrinsic_wo_chain:{ *:[v4i32] } 9774:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB, v4i32:{ *:[v4i32] }:$VDi) => (VRLWMI:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB, v4i32:{ *:[v4i32] }:$VDi) |
| 9573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLWMI), |
| 9574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9575 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 9576 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 9577 | GIR_RootToRootCopy, /*OpIdx*/4, // VDi |
| 9578 | GIR_RootConstrainSelectedInstOperands, |
| 9579 | // GIR_Coverage, 545, |
| 9580 | GIR_EraseRootFromParent_Done, |
| 9581 | // Label 766: @22839 |
| 9582 | GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(22881), // Rule ID 547 // |
| 9583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 9584 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrldmi), |
| 9585 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9586 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9587 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9588 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 9589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9590 | // (intrinsic_wo_chain:{ *:[v2i64] } 9768:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB, v2i64:{ *:[v2i64] }:$VDi) => (VRLDMI:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB, v2i64:{ *:[v2i64] }:$VDi) |
| 9591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLDMI), |
| 9592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9593 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 9594 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 9595 | GIR_RootToRootCopy, /*OpIdx*/4, // VDi |
| 9596 | GIR_RootConstrainSelectedInstOperands, |
| 9597 | // GIR_Coverage, 547, |
| 9598 | GIR_EraseRootFromParent_Done, |
| 9599 | // Label 767: @22881 |
| 9600 | GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(22923), // Rule ID 1056 // |
| 9601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9602 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbvlx), |
| 9603 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9606 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 9607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9608 | // (intrinsic_wo_chain:{ *:[v16i8] } 9679:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VINSBVLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 9609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBVLX), |
| 9610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9611 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9612 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9613 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9614 | GIR_RootConstrainSelectedInstOperands, |
| 9615 | // GIR_Coverage, 1056, |
| 9616 | GIR_EraseRootFromParent_Done, |
| 9617 | // Label 768: @22923 |
| 9618 | GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(22965), // Rule ID 1057 // |
| 9619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9620 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbvrx), |
| 9621 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9622 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9623 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9624 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 9625 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9626 | // (intrinsic_wo_chain:{ *:[v16i8] } 9680:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) => (VINSBVRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, v16i8:{ *:[v16i8] }:$VB) |
| 9627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBVRX), |
| 9628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9629 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9630 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9631 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9632 | GIR_RootConstrainSelectedInstOperands, |
| 9633 | // GIR_Coverage, 1057, |
| 9634 | GIR_EraseRootFromParent_Done, |
| 9635 | // Label 769: @22965 |
| 9636 | GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(23007), // Rule ID 1058 // |
| 9637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9638 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshvlx), |
| 9639 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9640 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9641 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9642 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 9643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9644 | // (intrinsic_wo_chain:{ *:[v8i16] } 9686:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VINSHVLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 9645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHVLX), |
| 9646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9647 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9648 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9649 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9650 | GIR_RootConstrainSelectedInstOperands, |
| 9651 | // GIR_Coverage, 1058, |
| 9652 | GIR_EraseRootFromParent_Done, |
| 9653 | // Label 770: @23007 |
| 9654 | GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(23049), // Rule ID 1059 // |
| 9655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9656 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshvrx), |
| 9657 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9659 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9660 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 9661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9662 | // (intrinsic_wo_chain:{ *:[v8i16] } 9687:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VINSHVRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 9663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHVRX), |
| 9664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9665 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9666 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9667 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9668 | GIR_RootConstrainSelectedInstOperands, |
| 9669 | // GIR_Coverage, 1059, |
| 9670 | GIR_EraseRootFromParent_Done, |
| 9671 | // Label 771: @23049 |
| 9672 | GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(23091), // Rule ID 1060 // |
| 9673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9674 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswvlx), |
| 9675 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9676 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9677 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9678 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9680 | // (intrinsic_wo_chain:{ *:[v4i32] } 9691:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VINSWVLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 9681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWVLX), |
| 9682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9683 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9684 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9685 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9686 | GIR_RootConstrainSelectedInstOperands, |
| 9687 | // GIR_Coverage, 1060, |
| 9688 | GIR_EraseRootFromParent_Done, |
| 9689 | // Label 772: @23091 |
| 9690 | GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(23133), // Rule ID 1061 // |
| 9691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9692 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswvrx), |
| 9693 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9694 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9695 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9696 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 9697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9698 | // (intrinsic_wo_chain:{ *:[v4i32] } 9692:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VINSWVRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 9699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWVRX), |
| 9700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9701 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9702 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9703 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9704 | GIR_RootConstrainSelectedInstOperands, |
| 9705 | // GIR_Coverage, 1061, |
| 9706 | GIR_EraseRootFromParent_Done, |
| 9707 | // Label 773: @23133 |
| 9708 | GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(23175), // Rule ID 1062 // |
| 9709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsblx), |
| 9711 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9712 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9713 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9714 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9716 | // (intrinsic_wo_chain:{ *:[v16i8] } 9677:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSBLX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) |
| 9717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBLX), |
| 9718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9719 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9720 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9721 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9722 | GIR_RootConstrainSelectedInstOperands, |
| 9723 | // GIR_Coverage, 1062, |
| 9724 | GIR_EraseRootFromParent_Done, |
| 9725 | // Label 774: @23175 |
| 9726 | GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(23217), // Rule ID 1063 // |
| 9727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsbrx), |
| 9729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9731 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9732 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9734 | // (intrinsic_wo_chain:{ *:[v16i8] } 9678:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSBRX:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) |
| 9735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBRX), |
| 9736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9737 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9738 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9739 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9740 | GIR_RootConstrainSelectedInstOperands, |
| 9741 | // GIR_Coverage, 1063, |
| 9742 | GIR_EraseRootFromParent_Done, |
| 9743 | // Label 775: @23217 |
| 9744 | GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(23259), // Rule ID 1064 // |
| 9745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9746 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshlx), |
| 9747 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9748 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9749 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9750 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9752 | // (intrinsic_wo_chain:{ *:[v8i16] } 9684:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSHLX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) |
| 9753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHLX), |
| 9754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9755 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9756 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9757 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9758 | GIR_RootConstrainSelectedInstOperands, |
| 9759 | // GIR_Coverage, 1064, |
| 9760 | GIR_EraseRootFromParent_Done, |
| 9761 | // Label 776: @23259 |
| 9762 | GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(23301), // Rule ID 1065 // |
| 9763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9764 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinshrx), |
| 9765 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9766 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9767 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9768 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9770 | // (intrinsic_wo_chain:{ *:[v8i16] } 9685:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSHRX:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) |
| 9771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHRX), |
| 9772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9773 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9774 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9775 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9776 | GIR_RootConstrainSelectedInstOperands, |
| 9777 | // GIR_Coverage, 1065, |
| 9778 | GIR_EraseRootFromParent_Done, |
| 9779 | // Label 777: @23301 |
| 9780 | GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(23343), // Rule ID 1066 // |
| 9781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswlx), |
| 9783 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9786 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9788 | // (intrinsic_wo_chain:{ *:[v4i32] } 9689:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSWLX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) |
| 9789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWLX), |
| 9790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9791 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9792 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9793 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9794 | GIR_RootConstrainSelectedInstOperands, |
| 9795 | // GIR_Coverage, 1066, |
| 9796 | GIR_EraseRootFromParent_Done, |
| 9797 | // Label 778: @23343 |
| 9798 | GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(23385), // Rule ID 1067 // |
| 9799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9800 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinswrx), |
| 9801 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9802 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9803 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 9804 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9805 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9806 | // (intrinsic_wo_chain:{ *:[v4i32] } 9690:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) => (VINSWRX:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VDi, i32:{ *:[i32] }:$VA, i32:{ *:[i32] }:$VB) |
| 9807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSWRX), |
| 9808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9809 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9810 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9811 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9812 | GIR_RootConstrainSelectedInstOperands, |
| 9813 | // GIR_Coverage, 1067, |
| 9814 | GIR_EraseRootFromParent_Done, |
| 9815 | // Label 779: @23385 |
| 9816 | GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(23427), // Rule ID 1068 // |
| 9817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9818 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsdlx), |
| 9819 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9820 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9821 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9822 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9824 | // (intrinsic_wo_chain:{ *:[v2i64] } 9682:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) => (VINSDLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) |
| 9825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSDLX), |
| 9826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9827 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9828 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9829 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9830 | GIR_RootConstrainSelectedInstOperands, |
| 9831 | // GIR_Coverage, 1068, |
| 9832 | GIR_EraseRootFromParent_Done, |
| 9833 | // Label 780: @23427 |
| 9834 | GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(23469), // Rule ID 1069 // |
| 9835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9836 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vinsdrx), |
| 9837 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9838 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9839 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 9840 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 9841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9842 | // (intrinsic_wo_chain:{ *:[v2i64] } 9683:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) => (VINSDRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VDi, i64:{ *:[i64] }:$VA, i64:{ *:[i64] }:$VB) |
| 9843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSDRX), |
| 9844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 9845 | GIR_RootToRootCopy, /*OpIdx*/2, // VDi |
| 9846 | GIR_RootToRootCopy, /*OpIdx*/3, // VA |
| 9847 | GIR_RootToRootCopy, /*OpIdx*/4, // VB |
| 9848 | GIR_RootConstrainSelectedInstOperands, |
| 9849 | // GIR_Coverage, 1069, |
| 9850 | GIR_EraseRootFromParent_Done, |
| 9851 | // Label 781: @23469 |
| 9852 | GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(23511), // Rule ID 1090 // |
| 9853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9854 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextdubvlx), |
| 9855 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9858 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9860 | // (intrinsic_wo_chain:{ *:[v2i64] } 9658:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUBVLX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) |
| 9861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUBVLX), |
| 9862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9863 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9864 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9865 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9866 | GIR_RootConstrainSelectedInstOperands, |
| 9867 | // GIR_Coverage, 1090, |
| 9868 | GIR_EraseRootFromParent_Done, |
| 9869 | // Label 782: @23511 |
| 9870 | GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(23553), // Rule ID 1091 // |
| 9871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9872 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextdubvrx), |
| 9873 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9876 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9878 | // (intrinsic_wo_chain:{ *:[v2i64] } 9659:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUBVRX:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$RA, v16i8:{ *:[v16i8] }:$RB, i32:{ *:[i32] }:$RC) |
| 9879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUBVRX), |
| 9880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9881 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9882 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9883 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9884 | GIR_RootConstrainSelectedInstOperands, |
| 9885 | // GIR_Coverage, 1091, |
| 9886 | GIR_EraseRootFromParent_Done, |
| 9887 | // Label 783: @23553 |
| 9888 | GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(23595), // Rule ID 1092 // |
| 9889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9890 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduhvlx), |
| 9891 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9892 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9893 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9894 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9895 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9896 | // (intrinsic_wo_chain:{ *:[v2i64] } 9660:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUHVLX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) |
| 9897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUHVLX), |
| 9898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9899 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9900 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9901 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9902 | GIR_RootConstrainSelectedInstOperands, |
| 9903 | // GIR_Coverage, 1092, |
| 9904 | GIR_EraseRootFromParent_Done, |
| 9905 | // Label 784: @23595 |
| 9906 | GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(23637), // Rule ID 1093 // |
| 9907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduhvrx), |
| 9909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9912 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9914 | // (intrinsic_wo_chain:{ *:[v2i64] } 9661:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUHVRX:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, i32:{ *:[i32] }:$RC) |
| 9915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUHVRX), |
| 9916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9917 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9918 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9919 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9920 | GIR_RootConstrainSelectedInstOperands, |
| 9921 | // GIR_Coverage, 1093, |
| 9922 | GIR_EraseRootFromParent_Done, |
| 9923 | // Label 785: @23637 |
| 9924 | GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(23679), // Rule ID 1094 // |
| 9925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9926 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduwvlx), |
| 9927 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9928 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9929 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9930 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9932 | // (intrinsic_wo_chain:{ *:[v2i64] } 9662:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUWVLX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) |
| 9933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUWVLX), |
| 9934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9935 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9936 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9937 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9938 | GIR_RootConstrainSelectedInstOperands, |
| 9939 | // GIR_Coverage, 1094, |
| 9940 | GIR_EraseRootFromParent_Done, |
| 9941 | // Label 786: @23679 |
| 9942 | GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(23721), // Rule ID 1095 // |
| 9943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9944 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextduwvrx), |
| 9945 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9946 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9947 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9948 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9950 | // (intrinsic_wo_chain:{ *:[v2i64] } 9663:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDUWVRX:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$RA, v4i32:{ *:[v4i32] }:$RB, i32:{ *:[i32] }:$RC) |
| 9951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDUWVRX), |
| 9952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9953 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9954 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9955 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9956 | GIR_RootConstrainSelectedInstOperands, |
| 9957 | // GIR_Coverage, 1095, |
| 9958 | GIR_EraseRootFromParent_Done, |
| 9959 | // Label 787: @23721 |
| 9960 | GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(23763), // Rule ID 1096 // |
| 9961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextddvlx), |
| 9963 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9965 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9966 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9968 | // (intrinsic_wo_chain:{ *:[v2i64] } 9656:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDDVLX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) |
| 9969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDDVLX), |
| 9970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9971 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9972 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9973 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9974 | GIR_RootConstrainSelectedInstOperands, |
| 9975 | // GIR_Coverage, 1096, |
| 9976 | GIR_EraseRootFromParent_Done, |
| 9977 | // Label 788: @23763 |
| 9978 | GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(23805), // Rule ID 1097 // |
| 9979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9980 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vextddvrx), |
| 9981 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9982 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9983 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9984 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 9985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 9986 | // (intrinsic_wo_chain:{ *:[v2i64] } 9657:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) => (VEXTDDVRX:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, i32:{ *:[i32] }:$RC) |
| 9987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VEXTDDVRX), |
| 9988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 9989 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 9990 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 9991 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 9992 | GIR_RootConstrainSelectedInstOperands, |
| 9993 | // GIR_Coverage, 1097, |
| 9994 | GIR_EraseRootFromParent_Done, |
| 9995 | // Label 789: @23805 |
| 9996 | GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(23847), // Rule ID 1135 // |
| 9997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 9998 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumcud), |
| 9999 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 10000 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 10002 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 10003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10004 | // (intrinsic_wo_chain:{ *:[v1i128] } 9716:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) => (VMSUMCUD:{ *:[v1i128] } v2i64:{ *:[v2i64] }:$RA, v2i64:{ *:[v2i64] }:$RB, v1i128:{ *:[v1i128] }:$RC) |
| 10005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMCUD), |
| 10006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 10007 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 10008 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 10009 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 10010 | GIR_RootConstrainSelectedInstOperands, |
| 10011 | // GIR_Coverage, 1135, |
| 10012 | GIR_EraseRootFromParent_Done, |
| 10013 | // Label 790: @23847 |
| 10014 | GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(23889), // Rule ID 1150 // |
| 10015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 10016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vrlqmi), |
| 10017 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s128, |
| 10018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 10019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 10020 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s128, |
| 10021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10022 | // (intrinsic_wo_chain:{ *:[v1i128] } 9771:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB, v1i128:{ *:[v1i128] }:$VDi) => (VRLQMI:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VA, v1i128:{ *:[v1i128] }:$VB, v1i128:{ *:[v1i128] }:$VDi) |
| 10023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VRLQMI), |
| 10024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 10025 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 10026 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 10027 | GIR_RootToRootCopy, /*OpIdx*/4, // VDi |
| 10028 | GIR_RootConstrainSelectedInstOperands, |
| 10029 | // GIR_Coverage, 1150, |
| 10030 | GIR_EraseRootFromParent_Done, |
| 10031 | // Label 791: @23889 |
| 10032 | GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(23928), // Rule ID 1265 // |
| 10033 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsub), |
| 10034 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 10035 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 10036 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 10037 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 10038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 10039 | // (intrinsic_wo_chain:{ *:[f64] } 9892:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (FMSUB:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) |
| 10040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB), |
| 10041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 10042 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10043 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10044 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10045 | GIR_RootConstrainSelectedInstOperands, |
| 10046 | // GIR_Coverage, 1265, |
| 10047 | GIR_EraseRootFromParent_Done, |
| 10048 | // Label 792: @23928 |
| 10049 | GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(23967), // Rule ID 1266 // |
| 10050 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmsubs), |
| 10051 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 10052 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 10053 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 10054 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 10055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 10056 | // (intrinsic_wo_chain:{ *:[f32] } 9893:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (FMSUBS:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) |
| 10057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS), |
| 10058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 10059 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10060 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10061 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10062 | GIR_RootConstrainSelectedInstOperands, |
| 10063 | // GIR_Coverage, 1266, |
| 10064 | GIR_EraseRootFromParent_Done, |
| 10065 | // Label 793: @23967 |
| 10066 | GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(24006), // Rule ID 1267 // |
| 10067 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadd), |
| 10068 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 10069 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 10070 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 10071 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 10072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 10073 | // (intrinsic_wo_chain:{ *:[f64] } 9896:{ *:[iPTR] }, f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B, f64:{ *:[f64] }:$C) => (FNMADD:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B, ?:{ *:[f64] }:$C) |
| 10074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD), |
| 10075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 10076 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10077 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10078 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10079 | GIR_RootConstrainSelectedInstOperands, |
| 10080 | // GIR_Coverage, 1267, |
| 10081 | GIR_EraseRootFromParent_Done, |
| 10082 | // Label 794: @24006 |
| 10083 | GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(24045), // Rule ID 1268 // |
| 10084 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fnmadds), |
| 10085 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 10086 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 10087 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 10088 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 10089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 10090 | // (intrinsic_wo_chain:{ *:[f32] } 9897:{ *:[iPTR] }, f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B, f32:{ *:[f32] }:$C) => (FNMADDS:{ *:[f32] } ?:{ *:[f32] }:$A, ?:{ *:[f32] }:$B, ?:{ *:[f32] }:$C) |
| 10091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS), |
| 10092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 10093 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10094 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10095 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10096 | GIR_RootConstrainSelectedInstOperands, |
| 10097 | // GIR_Coverage, 1268, |
| 10098 | GIR_EraseRootFromParent_Done, |
| 10099 | // Label 795: @24045 |
| 10100 | GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(24087), // Rule ID 1370 // |
| 10101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 10102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmaddfp), |
| 10103 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10106 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10108 | // (intrinsic_wo_chain:{ *:[v4f32] } 9694:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B, v4f32:{ *:[v4f32] }:$C) => (VMADDFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B, ?:{ *:[v4f32] }:$C) |
| 10109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMADDFP), |
| 10110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 10111 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10112 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10113 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10114 | GIR_RootConstrainSelectedInstOperands, |
| 10115 | // GIR_Coverage, 1370, |
| 10116 | GIR_EraseRootFromParent_Done, |
| 10117 | // Label 796: @24087 |
| 10118 | GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(24129), // Rule ID 1371 // |
| 10119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 10120 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vnmsubfp), |
| 10121 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10122 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10123 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10124 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10126 | // (intrinsic_wo_chain:{ *:[v4f32] } 9744:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$A, v4f32:{ *:[v4f32] }:$B, v4f32:{ *:[v4f32] }:$C) => (VNMSUBFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$A, ?:{ *:[v4f32] }:$B, ?:{ *:[v4f32] }:$C) |
| 10127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNMSUBFP), |
| 10128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 10129 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10130 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10131 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10132 | GIR_RootConstrainSelectedInstOperands, |
| 10133 | // GIR_Coverage, 1371, |
| 10134 | GIR_EraseRootFromParent_Done, |
| 10135 | // Label 797: @24129 |
| 10136 | GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(24228), // Rule ID 1566 // |
| 10137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX_IsLittleEndian), |
| 10138 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor), |
| 10139 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 10140 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10141 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10142 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10144 | // (intrinsic_wo_chain:{ *:[v16i8] } 9524:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, (XXLNOR:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$c, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$c, VSRC:{ *:[i32] }))) |
| 10145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10146 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10147 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 10148 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10149 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10150 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // c |
| 10151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 10152 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10153 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10154 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // c |
| 10155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10156 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXLNOR), |
| 10157 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10158 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10159 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 10160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR), |
| 10162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 10163 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 10164 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 10165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10166 | GIR_RootConstrainSelectedInstOperands, |
| 10167 | // GIR_Coverage, 1566, |
| 10168 | GIR_EraseRootFromParent_Done, |
| 10169 | // Label 798: @24228 |
| 10170 | GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(24270), // Rule ID 1567 // |
| 10171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX_IsBigEndian), |
| 10172 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor), |
| 10173 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 10174 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10175 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10176 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10178 | // (intrinsic_wo_chain:{ *:[v16i8] } 9524:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, ?:{ *:[v16i8] }:$c) |
| 10179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR), |
| 10180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 10181 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 10182 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 10183 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 10184 | GIR_RootConstrainSelectedInstOperands, |
| 10185 | // GIR_Coverage, 1567, |
| 10186 | GIR_EraseRootFromParent_Done, |
| 10187 | // Label 799: @24270 |
| 10188 | GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(24312), // Rule ID 1568 // |
| 10189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec_HasVSX), |
| 10190 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_crypto_vpermxor_be), |
| 10191 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 10192 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10193 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10194 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 10196 | // (intrinsic_wo_chain:{ *:[v16i8] } 9525:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$a, v16i8:{ *:[v16i8] }:$b, v16i8:{ *:[v16i8] }:$c) => (VPERMXOR:{ *:[v16i8] } ?:{ *:[v16i8] }:$a, ?:{ *:[v16i8] }:$b, ?:{ *:[v16i8] }:$c) |
| 10197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPERMXOR), |
| 10198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 10199 | GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 10200 | GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 10201 | GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 10202 | GIR_RootConstrainSelectedInstOperands, |
| 10203 | // GIR_Coverage, 1568, |
| 10204 | GIR_EraseRootFromParent_Done, |
| 10205 | // Label 800: @24312 |
| 10206 | GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(24432), // Rule ID 3408 // |
| 10207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), |
| 10208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvb), |
| 10209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 10210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10212 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 10214 | // (intrinsic_wo_chain:{ *:[v16i8] } 10125:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$A, v16i8:{ *:[v16i8] }:$B, v16i8:{ *:[v16i8] }:$C) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXBLENDVB:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$C, VSRC:{ *:[i32] })), VSRC:{ *:[i32] }) |
| 10215 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10216 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10217 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 10218 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, |
| 10219 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10220 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10221 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C |
| 10222 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 10223 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10224 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10225 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B |
| 10226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 10227 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10228 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10229 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 10230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVB), |
| 10232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10233 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10234 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 10235 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 10236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10239 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10240 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 10241 | // GIR_Coverage, 3408, |
| 10242 | GIR_EraseRootFromParent_Done, |
| 10243 | // Label 801: @24432 |
| 10244 | GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(24552), // Rule ID 3409 // |
| 10245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), |
| 10246 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvh), |
| 10247 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10248 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10249 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10250 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 10252 | // (intrinsic_wo_chain:{ *:[v8i16] } 10127:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$A, v8i16:{ *:[v8i16] }:$B, v8i16:{ *:[v8i16] }:$C) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXBLENDVH:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$C, VSRC:{ *:[i32] })), VSRC:{ *:[i32] }) |
| 10253 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10254 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10255 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 10256 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, |
| 10257 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10258 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10259 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C |
| 10260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 10261 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10262 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10263 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B |
| 10264 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 10265 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10266 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10267 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 10268 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10269 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVH), |
| 10270 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10271 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10272 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 10273 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 10274 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10277 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10278 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 10279 | // GIR_Coverage, 3409, |
| 10280 | GIR_EraseRootFromParent_Done, |
| 10281 | // Label 802: @24552 |
| 10282 | GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(24594), // Rule ID 3410 // |
| 10283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), |
| 10284 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvw), |
| 10285 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10286 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10287 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10288 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10289 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 10290 | // (intrinsic_wo_chain:{ *:[v4i32] } 10128:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$A, v4i32:{ *:[v4i32] }:$B, v4i32:{ *:[v4i32] }:$C) => (XXBLENDVW:{ *:[v4i32] } ?:{ *:[v4i32] }:$A, ?:{ *:[v4i32] }:$B, ?:{ *:[v4i32] }:$C) |
| 10291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVW), |
| 10292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 10293 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10294 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10295 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10296 | GIR_RootConstrainSelectedInstOperands, |
| 10297 | // GIR_Coverage, 3410, |
| 10298 | GIR_EraseRootFromParent_Done, |
| 10299 | // Label 803: @24594 |
| 10300 | GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(24636), // Rule ID 3411 // |
| 10301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), |
| 10302 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxblendvd), |
| 10303 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10305 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 10306 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 10307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 10308 | // (intrinsic_wo_chain:{ *:[v2i64] } 10126:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$A, v2i64:{ *:[v2i64] }:$B, v2i64:{ *:[v2i64] }:$C) => (XXBLENDVD:{ *:[v2i64] } ?:{ *:[v2i64] }:$A, ?:{ *:[v2i64] }:$B, ?:{ *:[v2i64] }:$C) |
| 10309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXBLENDVD), |
| 10310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 10311 | GIR_RootToRootCopy, /*OpIdx*/2, // A |
| 10312 | GIR_RootToRootCopy, /*OpIdx*/3, // B |
| 10313 | GIR_RootToRootCopy, /*OpIdx*/4, // C |
| 10314 | GIR_RootConstrainSelectedInstOperands, |
| 10315 | // GIR_Coverage, 3411, |
| 10316 | GIR_EraseRootFromParent_Done, |
| 10317 | // Label 804: @24636 |
| 10318 | GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(24716), // Rule ID 3491 // |
| 10319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10320 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8pp), |
| 10321 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10322 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10323 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10324 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10326 | // (intrinsic_wo_chain:{ *:[v512i1] } 9988:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10327 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10328 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10329 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10330 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10331 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10335 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10336 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8PP), |
| 10338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10339 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10340 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10342 | GIR_RootConstrainSelectedInstOperands, |
| 10343 | // GIR_Coverage, 3491, |
| 10344 | GIR_EraseRootFromParent_Done, |
| 10345 | // Label 805: @24716 |
| 10346 | GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(24796), // Rule ID 3493 // |
| 10347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10348 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4pp), |
| 10349 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10350 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10351 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10352 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10354 | // (intrinsic_wo_chain:{ *:[v512i1] } 9990:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10355 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10356 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10357 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10358 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10359 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10361 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10362 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10363 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4PP), |
| 10366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10367 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10368 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10369 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10370 | GIR_RootConstrainSelectedInstOperands, |
| 10371 | // GIR_Coverage, 3493, |
| 10372 | GIR_EraseRootFromParent_Done, |
| 10373 | // Label 806: @24796 |
| 10374 | GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(24876), // Rule ID 3495 // |
| 10375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10376 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2spp), |
| 10377 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10378 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10379 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10380 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10382 | // (intrinsic_wo_chain:{ *:[v512i1] } 9986:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10383 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10384 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10385 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10386 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10387 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10391 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10392 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SPP), |
| 10394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10395 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10396 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10397 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10398 | GIR_RootConstrainSelectedInstOperands, |
| 10399 | // GIR_Coverage, 3495, |
| 10400 | GIR_EraseRootFromParent_Done, |
| 10401 | // Label 807: @24876 |
| 10402 | GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(24956), // Rule ID 3497 // |
| 10403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10404 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi4ger8pp), |
| 10405 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10406 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10407 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10408 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10410 | // (intrinsic_wo_chain:{ *:[v512i1] } 9988:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI4GER8WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10411 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10412 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10413 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10414 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10415 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10419 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI4GER8WPP), |
| 10422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10423 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10424 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10425 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10426 | GIR_RootConstrainSelectedInstOperands, |
| 10427 | // GIR_Coverage, 3497, |
| 10428 | GIR_EraseRootFromParent_Done, |
| 10429 | // Label 808: @24956 |
| 10430 | GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(25036), // Rule ID 3499 // |
| 10431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10432 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4pp), |
| 10433 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10434 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10435 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10436 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10438 | // (intrinsic_wo_chain:{ *:[v512i1] } 9990:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10439 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10440 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10441 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10442 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10443 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10445 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10446 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10447 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10448 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4WPP), |
| 10450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10451 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10452 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10453 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10454 | GIR_RootConstrainSelectedInstOperands, |
| 10455 | // GIR_Coverage, 3499, |
| 10456 | GIR_EraseRootFromParent_Done, |
| 10457 | // Label 809: @25036 |
| 10458 | GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(25116), // Rule ID 3501 // |
| 10459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10460 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2spp), |
| 10461 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10462 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10463 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10464 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10466 | // (intrinsic_wo_chain:{ *:[v512i1] } 9986:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2SWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10467 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10468 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10469 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10470 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10471 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10472 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10475 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2SWPP), |
| 10478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10479 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10480 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10481 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10482 | GIR_RootConstrainSelectedInstOperands, |
| 10483 | // GIR_Coverage, 3501, |
| 10484 | GIR_EraseRootFromParent_Done, |
| 10485 | // Label 810: @25116 |
| 10486 | GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(25196), // Rule ID 3503 // |
| 10487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pp), |
| 10489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10492 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10494 | // (intrinsic_wo_chain:{ *:[v512i1] } 9972:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10496 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10497 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10498 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10499 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10500 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10501 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10502 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10503 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2PP), |
| 10506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10507 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10508 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10509 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10510 | GIR_RootConstrainSelectedInstOperands, |
| 10511 | // GIR_Coverage, 3503, |
| 10512 | GIR_EraseRootFromParent_Done, |
| 10513 | // Label 811: @25196 |
| 10514 | GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(25276), // Rule ID 3504 // |
| 10515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10516 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pn), |
| 10517 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10518 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10519 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10520 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10522 | // (intrinsic_wo_chain:{ *:[v512i1] } 9971:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10523 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10524 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10525 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10526 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10527 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10531 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2PN), |
| 10534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10535 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10536 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10537 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10538 | GIR_RootConstrainSelectedInstOperands, |
| 10539 | // GIR_Coverage, 3504, |
| 10540 | GIR_EraseRootFromParent_Done, |
| 10541 | // Label 812: @25276 |
| 10542 | GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(25356), // Rule ID 3505 // |
| 10543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10544 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2np), |
| 10545 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10546 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10547 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10548 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10550 | // (intrinsic_wo_chain:{ *:[v512i1] } 9970:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10551 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10552 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10553 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10554 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10555 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10557 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10559 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2NP), |
| 10562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10563 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10564 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10565 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10566 | GIR_RootConstrainSelectedInstOperands, |
| 10567 | // GIR_Coverage, 3505, |
| 10568 | GIR_EraseRootFromParent_Done, |
| 10569 | // Label 813: @25356 |
| 10570 | GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(25436), // Rule ID 3506 // |
| 10571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10572 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2nn), |
| 10573 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10574 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10575 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10576 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10578 | // (intrinsic_wo_chain:{ *:[v512i1] } 9969:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10579 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10580 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10581 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10582 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10583 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10584 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10585 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10586 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10587 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10588 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2NN), |
| 10590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10591 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10592 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10593 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10594 | GIR_RootConstrainSelectedInstOperands, |
| 10595 | // GIR_Coverage, 3506, |
| 10596 | GIR_EraseRootFromParent_Done, |
| 10597 | // Label 814: @25436 |
| 10598 | GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(25516), // Rule ID 3508 // |
| 10599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10600 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pp), |
| 10601 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10602 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10603 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10604 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10606 | // (intrinsic_wo_chain:{ *:[v512i1] } 9972:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10607 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10608 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10609 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10610 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10611 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10612 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10615 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WPP), |
| 10618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10619 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10621 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10622 | GIR_RootConstrainSelectedInstOperands, |
| 10623 | // GIR_Coverage, 3508, |
| 10624 | GIR_EraseRootFromParent_Done, |
| 10625 | // Label 815: @25516 |
| 10626 | GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(25596), // Rule ID 3509 // |
| 10627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2pn), |
| 10629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10631 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10632 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10634 | // (intrinsic_wo_chain:{ *:[v512i1] } 9971:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10635 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10636 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10637 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10638 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10639 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10640 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10643 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10644 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WPN), |
| 10646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10647 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10648 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10649 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10650 | GIR_RootConstrainSelectedInstOperands, |
| 10651 | // GIR_Coverage, 3509, |
| 10652 | GIR_EraseRootFromParent_Done, |
| 10653 | // Label 816: @25596 |
| 10654 | GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(25676), // Rule ID 3510 // |
| 10655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10656 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2np), |
| 10657 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10658 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10659 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10660 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10662 | // (intrinsic_wo_chain:{ *:[v512i1] } 9970:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10663 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10664 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10665 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10666 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10667 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10668 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10670 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10671 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10672 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WNP), |
| 10674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10675 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10676 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10677 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10678 | GIR_RootConstrainSelectedInstOperands, |
| 10679 | // GIR_Coverage, 3510, |
| 10680 | GIR_EraseRootFromParent_Done, |
| 10681 | // Label 817: @25676 |
| 10682 | GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(25756), // Rule ID 3511 // |
| 10683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 10684 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf16ger2nn), |
| 10685 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10686 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10687 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10688 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 10690 | // (intrinsic_wo_chain:{ *:[v512i1] } 9969:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10691 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10692 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10693 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10694 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10695 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10696 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10697 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10699 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF16GER2WNN), |
| 10702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10703 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10704 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10705 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10706 | GIR_RootConstrainSelectedInstOperands, |
| 10707 | // GIR_Coverage, 3511, |
| 10708 | GIR_EraseRootFromParent_Done, |
| 10709 | // Label 818: @25756 |
| 10710 | GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(25836), // Rule ID 3513 // |
| 10711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10712 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpp), |
| 10713 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10714 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10715 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10716 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10717 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10718 | // (intrinsic_wo_chain:{ *:[v512i1] } 9977:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10719 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10720 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10721 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10722 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10723 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10725 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10726 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10727 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10728 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERPP), |
| 10730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10731 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10732 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10733 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10734 | GIR_RootConstrainSelectedInstOperands, |
| 10735 | // GIR_Coverage, 3513, |
| 10736 | GIR_EraseRootFromParent_Done, |
| 10737 | // Label 819: @25836 |
| 10738 | GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(25916), // Rule ID 3514 // |
| 10739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10740 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpn), |
| 10741 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10743 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10744 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10746 | // (intrinsic_wo_chain:{ *:[v512i1] } 9976:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10747 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10748 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10749 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10750 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10751 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10752 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10753 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10754 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10755 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10756 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERPN), |
| 10758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10759 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10760 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10761 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10762 | GIR_RootConstrainSelectedInstOperands, |
| 10763 | // GIR_Coverage, 3514, |
| 10764 | GIR_EraseRootFromParent_Done, |
| 10765 | // Label 820: @25916 |
| 10766 | GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(25996), // Rule ID 3515 // |
| 10767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10768 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernp), |
| 10769 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10771 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10772 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10774 | // (intrinsic_wo_chain:{ *:[v512i1] } 9975:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10775 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10776 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10777 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10778 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10779 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10780 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10781 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10782 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10783 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10784 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERNP), |
| 10786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10787 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10788 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10789 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10790 | GIR_RootConstrainSelectedInstOperands, |
| 10791 | // GIR_Coverage, 3515, |
| 10792 | GIR_EraseRootFromParent_Done, |
| 10793 | // Label 821: @25996 |
| 10794 | GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(26076), // Rule ID 3516 // |
| 10795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10796 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernn), |
| 10797 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10798 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10799 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10800 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10802 | // (intrinsic_wo_chain:{ *:[v512i1] } 9974:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10803 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10804 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10805 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10806 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10807 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10808 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10809 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10810 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10811 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10812 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERNN), |
| 10814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10815 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10816 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10817 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10818 | GIR_RootConstrainSelectedInstOperands, |
| 10819 | // GIR_Coverage, 3516, |
| 10820 | GIR_EraseRootFromParent_Done, |
| 10821 | // Label 822: @26076 |
| 10822 | GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(26137), // Rule ID 3518 // |
| 10823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10824 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpp), |
| 10825 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10827 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 10828 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10830 | // (intrinsic_wo_chain:{ *:[v512i1] } 9982:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10831 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10832 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10833 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10834 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10835 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERPP), |
| 10837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10838 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10839 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 10840 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10841 | GIR_RootConstrainSelectedInstOperands, |
| 10842 | // GIR_Coverage, 3518, |
| 10843 | GIR_EraseRootFromParent_Done, |
| 10844 | // Label 823: @26137 |
| 10845 | GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(26198), // Rule ID 3519 // |
| 10846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10847 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpn), |
| 10848 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10849 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10850 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 10851 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10853 | // (intrinsic_wo_chain:{ *:[v512i1] } 9981:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10857 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERPN), |
| 10860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10861 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10862 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 10863 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10864 | GIR_RootConstrainSelectedInstOperands, |
| 10865 | // GIR_Coverage, 3519, |
| 10866 | GIR_EraseRootFromParent_Done, |
| 10867 | // Label 824: @26198 |
| 10868 | GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(26259), // Rule ID 3520 // |
| 10869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10870 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernp), |
| 10871 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10873 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 10874 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10876 | // (intrinsic_wo_chain:{ *:[v512i1] } 9980:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10877 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10878 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10879 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10880 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10881 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNP), |
| 10883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10884 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10885 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 10886 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10887 | GIR_RootConstrainSelectedInstOperands, |
| 10888 | // GIR_Coverage, 3520, |
| 10889 | GIR_EraseRootFromParent_Done, |
| 10890 | // Label 825: @26259 |
| 10891 | GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(26320), // Rule ID 3521 // |
| 10892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10893 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernn), |
| 10894 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10895 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10896 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 10897 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10899 | // (intrinsic_wo_chain:{ *:[v512i1] } 9979:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10901 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10902 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10903 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10904 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNN), |
| 10906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10907 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10908 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 10909 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10910 | GIR_RootConstrainSelectedInstOperands, |
| 10911 | // GIR_Coverage, 3521, |
| 10912 | GIR_EraseRootFromParent_Done, |
| 10913 | // Label 826: @26320 |
| 10914 | GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(26400), // Rule ID 3523 // |
| 10915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10916 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pp), |
| 10917 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10919 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10920 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10922 | // (intrinsic_wo_chain:{ *:[v512i1] } 9967:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10923 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10924 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10925 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10926 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10927 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10928 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10929 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10930 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10931 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2PP), |
| 10934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10935 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10936 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10938 | GIR_RootConstrainSelectedInstOperands, |
| 10939 | // GIR_Coverage, 3523, |
| 10940 | GIR_EraseRootFromParent_Done, |
| 10941 | // Label 827: @26400 |
| 10942 | GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(26480), // Rule ID 3524 // |
| 10943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10944 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pn), |
| 10945 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10946 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10947 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10948 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10950 | // (intrinsic_wo_chain:{ *:[v512i1] } 9966:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10952 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10953 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10954 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10955 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10957 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10958 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10959 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2PN), |
| 10962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10963 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10964 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10965 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10966 | GIR_RootConstrainSelectedInstOperands, |
| 10967 | // GIR_Coverage, 3524, |
| 10968 | GIR_EraseRootFromParent_Done, |
| 10969 | // Label 828: @26480 |
| 10970 | GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(26560), // Rule ID 3525 // |
| 10971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 10972 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2np), |
| 10973 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 10974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 10975 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10976 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 10978 | // (intrinsic_wo_chain:{ *:[v512i1] } 9965:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 10979 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10980 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10981 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10982 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10983 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 10984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10987 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 10988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2NP), |
| 10990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 10991 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 10992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10993 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 10994 | GIR_RootConstrainSelectedInstOperands, |
| 10995 | // GIR_Coverage, 3525, |
| 10996 | GIR_EraseRootFromParent_Done, |
| 10997 | // Label 829: @26560 |
| 10998 | GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(26640), // Rule ID 3526 // |
| 10999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 11000 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2nn), |
| 11001 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11002 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11003 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11004 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11006 | // (intrinsic_wo_chain:{ *:[v512i1] } 9964:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11007 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11008 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11009 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11010 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11011 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11012 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11015 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2NN), |
| 11018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11019 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11020 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11021 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11022 | GIR_RootConstrainSelectedInstOperands, |
| 11023 | // GIR_Coverage, 3526, |
| 11024 | GIR_EraseRootFromParent_Done, |
| 11025 | // Label 830: @26640 |
| 11026 | GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(26720), // Rule ID 3528 // |
| 11027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 11028 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2pp), |
| 11029 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11030 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11031 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11032 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11034 | // (intrinsic_wo_chain:{ *:[v512i1] } 9984:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11035 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11036 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11037 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11038 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11039 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11041 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11042 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11043 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11044 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2PP), |
| 11046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11047 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11048 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11049 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11050 | GIR_RootConstrainSelectedInstOperands, |
| 11051 | // GIR_Coverage, 3528, |
| 11052 | GIR_EraseRootFromParent_Done, |
| 11053 | // Label 831: @26720 |
| 11054 | GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(26800), // Rule ID 3529 // |
| 11055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA), |
| 11056 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4spp), |
| 11057 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11060 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11062 | // (intrinsic_wo_chain:{ *:[v512i1] } 9991:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11063 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11064 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11065 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11066 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11067 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11068 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11069 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11070 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11071 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4SPP), |
| 11074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11075 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11076 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11077 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11078 | GIR_RootConstrainSelectedInstOperands, |
| 11079 | // GIR_Coverage, 3529, |
| 11080 | GIR_EraseRootFromParent_Done, |
| 11081 | // Label 832: @26800 |
| 11082 | GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(26880), // Rule ID 3531 // |
| 11083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11084 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpp), |
| 11085 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11086 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11087 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11088 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11090 | // (intrinsic_wo_chain:{ *:[v512i1] } 9977:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11091 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11092 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11093 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11094 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11095 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11097 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11098 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11099 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWPP), |
| 11102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11103 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11104 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11105 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11106 | GIR_RootConstrainSelectedInstOperands, |
| 11107 | // GIR_Coverage, 3531, |
| 11108 | GIR_EraseRootFromParent_Done, |
| 11109 | // Label 833: @26880 |
| 11110 | GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(26960), // Rule ID 3532 // |
| 11111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11112 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gerpn), |
| 11113 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11114 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11115 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11116 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11118 | // (intrinsic_wo_chain:{ *:[v512i1] } 9976:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11119 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11120 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11121 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11122 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11123 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11124 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11127 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11128 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWPN), |
| 11130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11131 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11132 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11133 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11134 | GIR_RootConstrainSelectedInstOperands, |
| 11135 | // GIR_Coverage, 3532, |
| 11136 | GIR_EraseRootFromParent_Done, |
| 11137 | // Label 834: @26960 |
| 11138 | GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(27040), // Rule ID 3533 // |
| 11139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11140 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernp), |
| 11141 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11142 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11143 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11144 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11146 | // (intrinsic_wo_chain:{ *:[v512i1] } 9975:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11147 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11148 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11149 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11150 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11151 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11153 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11154 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11155 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWNP), |
| 11158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11159 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11160 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11161 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11162 | GIR_RootConstrainSelectedInstOperands, |
| 11163 | // GIR_Coverage, 3533, |
| 11164 | GIR_EraseRootFromParent_Done, |
| 11165 | // Label 835: @27040 |
| 11166 | GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(27120), // Rule ID 3534 // |
| 11167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11168 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf32gernn), |
| 11169 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11170 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11171 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11172 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11174 | // (intrinsic_wo_chain:{ *:[v512i1] } 9974:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF32GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11175 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11176 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11177 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11178 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11179 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11180 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11181 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11182 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11183 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11184 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF32GERWNN), |
| 11186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11187 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11188 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11189 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11190 | GIR_RootConstrainSelectedInstOperands, |
| 11191 | // GIR_Coverage, 3534, |
| 11192 | GIR_EraseRootFromParent_Done, |
| 11193 | // Label 836: @27120 |
| 11194 | GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(27181), // Rule ID 3536 // |
| 11195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11196 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpp), |
| 11197 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11199 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 11200 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11202 | // (intrinsic_wo_chain:{ *:[v512i1] } 9982:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11203 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11204 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11205 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11206 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWPP), |
| 11209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11210 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11211 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 11212 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11213 | GIR_RootConstrainSelectedInstOperands, |
| 11214 | // GIR_Coverage, 3536, |
| 11215 | GIR_EraseRootFromParent_Done, |
| 11216 | // Label 837: @27181 |
| 11217 | GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(27242), // Rule ID 3537 // |
| 11218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11219 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gerpn), |
| 11220 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11221 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11222 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 11223 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11225 | // (intrinsic_wo_chain:{ *:[v512i1] } 9981:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11229 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWPN), |
| 11232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11233 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11234 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 11235 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11236 | GIR_RootConstrainSelectedInstOperands, |
| 11237 | // GIR_Coverage, 3537, |
| 11238 | GIR_EraseRootFromParent_Done, |
| 11239 | // Label 838: @27242 |
| 11240 | GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(27303), // Rule ID 3538 // |
| 11241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11242 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernp), |
| 11243 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11244 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11245 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 11246 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11248 | // (intrinsic_wo_chain:{ *:[v512i1] } 9980:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11249 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11250 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11251 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11252 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERNP), |
| 11255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11256 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11257 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 11258 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11259 | GIR_RootConstrainSelectedInstOperands, |
| 11260 | // GIR_Coverage, 3538, |
| 11261 | GIR_EraseRootFromParent_Done, |
| 11262 | // Label 839: @27303 |
| 11263 | GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(27364), // Rule ID 3539 // |
| 11264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11265 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvf64gernn), |
| 11266 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11267 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11268 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 11269 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11271 | // (intrinsic_wo_chain:{ *:[v512i1] } 9979:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVF64GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11273 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11274 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11275 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVF64GERWNN), |
| 11278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11279 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11280 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 11281 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11282 | GIR_RootConstrainSelectedInstOperands, |
| 11283 | // GIR_Coverage, 3539, |
| 11284 | GIR_EraseRootFromParent_Done, |
| 11285 | // Label 840: @27364 |
| 11286 | GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(27444), // Rule ID 3541 // |
| 11287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11288 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pp), |
| 11289 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11292 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11294 | // (intrinsic_wo_chain:{ *:[v512i1] } 9967:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11295 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11296 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11297 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11298 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11299 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11300 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11301 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11302 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11303 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WPP), |
| 11306 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11307 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11308 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11310 | GIR_RootConstrainSelectedInstOperands, |
| 11311 | // GIR_Coverage, 3541, |
| 11312 | GIR_EraseRootFromParent_Done, |
| 11313 | // Label 841: @27444 |
| 11314 | GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(27524), // Rule ID 3542 // |
| 11315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11316 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2pn), |
| 11317 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11318 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11319 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11320 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11322 | // (intrinsic_wo_chain:{ *:[v512i1] } 9966:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11323 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11324 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11325 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11326 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11327 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11329 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11330 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11331 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WPN), |
| 11334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11335 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11336 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11338 | GIR_RootConstrainSelectedInstOperands, |
| 11339 | // GIR_Coverage, 3542, |
| 11340 | GIR_EraseRootFromParent_Done, |
| 11341 | // Label 842: @27524 |
| 11342 | GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(27604), // Rule ID 3543 // |
| 11343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11344 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2np), |
| 11345 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11346 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11347 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11348 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11350 | // (intrinsic_wo_chain:{ *:[v512i1] } 9965:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11351 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11352 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11353 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11354 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11355 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11356 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11359 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WNP), |
| 11362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11363 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11364 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11365 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11366 | GIR_RootConstrainSelectedInstOperands, |
| 11367 | // GIR_Coverage, 3543, |
| 11368 | GIR_EraseRootFromParent_Done, |
| 11369 | // Label 843: @27604 |
| 11370 | GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(27684), // Rule ID 3544 // |
| 11371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11372 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvbf16ger2nn), |
| 11373 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11374 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11375 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11376 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11378 | // (intrinsic_wo_chain:{ *:[v512i1] } 9964:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVBF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11379 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11380 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11381 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11382 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11383 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11387 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVBF16GER2WNN), |
| 11390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11391 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11392 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11394 | GIR_RootConstrainSelectedInstOperands, |
| 11395 | // GIR_Coverage, 3544, |
| 11396 | GIR_EraseRootFromParent_Done, |
| 11397 | // Label 844: @27684 |
| 11398 | GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(27764), // Rule ID 3546 // |
| 11399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11400 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi16ger2pp), |
| 11401 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11402 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11403 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11404 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11406 | // (intrinsic_wo_chain:{ *:[v512i1] } 9984:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11407 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11408 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11409 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11410 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11411 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11412 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11413 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11414 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11415 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI16GER2WPP), |
| 11418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11419 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11420 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11421 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11422 | GIR_RootConstrainSelectedInstOperands, |
| 11423 | // GIR_Coverage, 3546, |
| 11424 | GIR_EraseRootFromParent_Done, |
| 11425 | // Label 845: @27764 |
| 11426 | GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(27844), // Rule ID 3547 // |
| 11427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA), |
| 11428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_xvi8ger4spp), |
| 11429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 11431 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11432 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11434 | // (intrinsic_wo_chain:{ *:[v512i1] } 9991:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB) => (XVI8GER4WSPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] })) |
| 11435 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11436 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11437 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11438 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11439 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 11440 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11441 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11442 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11443 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 11444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVI8GER4WSPP), |
| 11446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11447 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 11448 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11449 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11450 | GIR_RootConstrainSelectedInstOperands, |
| 11451 | // GIR_Coverage, 3547, |
| 11452 | GIR_EraseRootFromParent_Done, |
| 11453 | // Label 846: @27844 |
| 11454 | GIM_Reject, |
| 11455 | // Label 734: @27845 |
| 11456 | GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(28442), |
| 11457 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 11458 | GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(27966), // Rule ID 3559 // |
| 11459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11460 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32ger), |
| 11461 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11462 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11463 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11464 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11465 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11467 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11468 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11469 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11470 | // MIs[1] Operand 1 |
| 11471 | // No operand predicates |
| 11472 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11473 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11474 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11475 | // MIs[2] Operand 1 |
| 11476 | // No operand predicates |
| 11477 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11478 | // (intrinsic_wo_chain:{ *:[v512i1] } 9944:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GER:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 11479 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11480 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11481 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11482 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11483 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11485 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11486 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11487 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11488 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GER), |
| 11490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11491 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11492 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11493 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11494 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11495 | GIR_RootConstrainSelectedInstOperands, |
| 11496 | // GIR_Coverage, 3559, |
| 11497 | GIR_EraseRootFromParent_Done, |
| 11498 | // Label 848: @27966 |
| 11499 | GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(28060), // Rule ID 3564 // |
| 11500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11501 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64ger), |
| 11502 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11503 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, |
| 11504 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11505 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11506 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11510 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11511 | // MIs[1] Operand 1 |
| 11512 | // No operand predicates |
| 11513 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11514 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11515 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 11516 | // MIs[2] Operand 1 |
| 11517 | // No operand predicates |
| 11518 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11519 | // (intrinsic_wo_chain:{ *:[v512i1] } 9949:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GER:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 11520 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11521 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11522 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11523 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GER), |
| 11526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11527 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 11528 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11529 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11530 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11531 | GIR_RootConstrainSelectedInstOperands, |
| 11532 | // GIR_Coverage, 3564, |
| 11533 | GIR_EraseRootFromParent_Done, |
| 11534 | // Label 849: @28060 |
| 11535 | GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(28173), // Rule ID 3588 // |
| 11536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 11537 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32ger), |
| 11538 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11539 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11540 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11541 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11542 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11544 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11545 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11546 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11547 | // MIs[1] Operand 1 |
| 11548 | // No operand predicates |
| 11549 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11550 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11551 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11552 | // MIs[2] Operand 1 |
| 11553 | // No operand predicates |
| 11554 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11555 | // (intrinsic_wo_chain:{ *:[v512i1] } 9944:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 11556 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11557 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11558 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11559 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11560 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11562 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11563 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11564 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERW), |
| 11567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11568 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11569 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11570 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11571 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11572 | GIR_RootConstrainSelectedInstOperands, |
| 11573 | // GIR_Coverage, 3588, |
| 11574 | GIR_EraseRootFromParent_Done, |
| 11575 | // Label 850: @28173 |
| 11576 | GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(28267), // Rule ID 3593 // |
| 11577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 11578 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64ger), |
| 11579 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11580 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v256s1, |
| 11581 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11582 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11583 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11585 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11586 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11587 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11588 | // MIs[1] Operand 1 |
| 11589 | // No operand predicates |
| 11590 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11591 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11592 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 11593 | // MIs[2] Operand 1 |
| 11594 | // No operand predicates |
| 11595 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 11596 | // (intrinsic_wo_chain:{ *:[v512i1] } 9949:{ *:[iPTR] }, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERW:{ *:[v512i1] } ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 11597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11600 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERW), |
| 11603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11604 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 11605 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11606 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11607 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11608 | GIR_RootConstrainSelectedInstOperands, |
| 11609 | // GIR_Coverage, 3593, |
| 11610 | GIR_EraseRootFromParent_Done, |
| 11611 | // Label 851: @28267 |
| 11612 | GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(28314), // Rule ID 1105 // |
| 11613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 11614 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxeval), |
| 11615 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64, |
| 11616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 11617 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 11618 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 11619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 11620 | // MIs[0] IMM |
| 11621 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 11622 | // (intrinsic_wo_chain:{ *:[v2i64] } 10129:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) => (XXEVAL:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XA, v2i64:{ *:[v2i64] }:$XB, v2i64:{ *:[v2i64] }:$XC, (timm:{ *:[i32] }):$IMM) |
| 11623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXEVAL), |
| 11624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 11625 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 11626 | GIR_RootToRootCopy, /*OpIdx*/3, // XB |
| 11627 | GIR_RootToRootCopy, /*OpIdx*/4, // XC |
| 11628 | GIR_RootToRootCopy, /*OpIdx*/5, // IMM |
| 11629 | GIR_RootConstrainSelectedInstOperands, |
| 11630 | // GIR_Coverage, 1105, |
| 11631 | GIR_EraseRootFromParent_Done, |
| 11632 | // Label 852: @28314 |
| 11633 | GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(28441), // Rule ID 3407 // |
| 11634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP10Vector_PrefixInstrs), |
| 11635 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_vsx_xxpermx), |
| 11636 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 11637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11638 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11639 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 11640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 11641 | // MIs[0] D |
| 11642 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 11643 | // (intrinsic_wo_chain:{ *:[v16i8] } 10137:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$A, v16i8:{ *:[v16i8] }:$B, v16i8:{ *:[v16i8] }:$C, (timm:{ *:[i32] }):$D) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXPERMX:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$A, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$B, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$C, VSRC:{ *:[i32] }), ?:{ *:[i32] }:$D), VSRC:{ *:[i32] }) |
| 11644 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11645 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11646 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 11647 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, |
| 11648 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11649 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11650 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/4, // C |
| 11651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 11652 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11653 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11654 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // B |
| 11655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 11656 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11657 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11658 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // A |
| 11659 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMX), |
| 11661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11662 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 11663 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 11664 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 11665 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // D |
| 11666 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 11669 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11670 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSRCRegClassID), |
| 11671 | // GIR_Coverage, 3407, |
| 11672 | GIR_EraseRootFromParent_Done, |
| 11673 | // Label 853: @28441 |
| 11674 | GIM_Reject, |
| 11675 | // Label 847: @28442 |
| 11676 | GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(31759), |
| 11677 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 11678 | GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(28581), // Rule ID 3548 // |
| 11679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11680 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8), |
| 11681 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11682 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11683 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11684 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11685 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11686 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11688 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11689 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11690 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11691 | // MIs[1] Operand 1 |
| 11692 | // No operand predicates |
| 11693 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11694 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11695 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11696 | // MIs[2] Operand 1 |
| 11697 | // No operand predicates |
| 11698 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11699 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11700 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), |
| 11701 | // MIs[3] Operand 1 |
| 11702 | // No operand predicates |
| 11703 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11704 | // (intrinsic_wo_chain:{ *:[v512i1] } 9958:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) |
| 11705 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11706 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11707 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11708 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11709 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11711 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11713 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11714 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8), |
| 11716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11717 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11718 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11719 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11720 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11721 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 11722 | GIR_RootConstrainSelectedInstOperands, |
| 11723 | // GIR_Coverage, 3548, |
| 11724 | GIR_EraseRootFromParent_Done, |
| 11725 | // Label 855: @28581 |
| 11726 | GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(28712), // Rule ID 3550 // |
| 11727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4), |
| 11729 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11730 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11731 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11732 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11733 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11734 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11736 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11737 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11738 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11739 | // MIs[1] Operand 1 |
| 11740 | // No operand predicates |
| 11741 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11742 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11743 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11744 | // MIs[2] Operand 1 |
| 11745 | // No operand predicates |
| 11746 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11747 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11748 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11749 | // MIs[3] Operand 1 |
| 11750 | // No operand predicates |
| 11751 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11752 | // (intrinsic_wo_chain:{ *:[v512i1] } 9960:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) |
| 11753 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11754 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11755 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11756 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11757 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11759 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11760 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11761 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4), |
| 11764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11765 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11767 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11768 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11769 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 11770 | GIR_RootConstrainSelectedInstOperands, |
| 11771 | // GIR_Coverage, 3550, |
| 11772 | GIR_EraseRootFromParent_Done, |
| 11773 | // Label 856: @28712 |
| 11774 | GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(28843), // Rule ID 3552 // |
| 11775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11776 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2s), |
| 11777 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11778 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11779 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11780 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11781 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11782 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11784 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11785 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11786 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11787 | // MIs[1] Operand 1 |
| 11788 | // No operand predicates |
| 11789 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11790 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11791 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11792 | // MIs[2] Operand 1 |
| 11793 | // No operand predicates |
| 11794 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11795 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11796 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 11797 | // MIs[3] Operand 1 |
| 11798 | // No operand predicates |
| 11799 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11800 | // (intrinsic_wo_chain:{ *:[v512i1] } 9956:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2S:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 11801 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11802 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11803 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11804 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11805 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11806 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11809 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11810 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2S), |
| 11812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11813 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11814 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11815 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11816 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11817 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 11818 | GIR_RootConstrainSelectedInstOperands, |
| 11819 | // GIR_Coverage, 3552, |
| 11820 | GIR_EraseRootFromParent_Done, |
| 11821 | // Label 857: @28843 |
| 11822 | GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(28974), // Rule ID 3554 // |
| 11823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11824 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2), |
| 11825 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11827 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11828 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11829 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11830 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11832 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11833 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11834 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11835 | // MIs[1] Operand 1 |
| 11836 | // No operand predicates |
| 11837 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11838 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11839 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11840 | // MIs[2] Operand 1 |
| 11841 | // No operand predicates |
| 11842 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11843 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11844 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 11845 | // MIs[3] Operand 1 |
| 11846 | // No operand predicates |
| 11847 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11848 | // (intrinsic_wo_chain:{ *:[v512i1] } 9939:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 11849 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11850 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11851 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11852 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11853 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11854 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11857 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11858 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2), |
| 11860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11861 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11862 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11863 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11864 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11865 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 11866 | GIR_RootConstrainSelectedInstOperands, |
| 11867 | // GIR_Coverage, 3554, |
| 11868 | GIR_EraseRootFromParent_Done, |
| 11869 | // Label 858: @28974 |
| 11870 | GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(29105), // Rule ID 3569 // |
| 11871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11872 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2), |
| 11873 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11876 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11877 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11878 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11880 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11881 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11882 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11883 | // MIs[1] Operand 1 |
| 11884 | // No operand predicates |
| 11885 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11886 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11887 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11888 | // MIs[2] Operand 1 |
| 11889 | // No operand predicates |
| 11890 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11891 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11892 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 11893 | // MIs[3] Operand 1 |
| 11894 | // No operand predicates |
| 11895 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11896 | // (intrinsic_wo_chain:{ *:[v512i1] } 9934:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 11897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11898 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11899 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11900 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11901 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11902 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11903 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11904 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11905 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2), |
| 11908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11909 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11910 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11911 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11912 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11913 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 11914 | GIR_RootConstrainSelectedInstOperands, |
| 11915 | // GIR_Coverage, 3569, |
| 11916 | GIR_EraseRootFromParent_Done, |
| 11917 | // Label 859: @29105 |
| 11918 | GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(29236), // Rule ID 3574 // |
| 11919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 11920 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2), |
| 11921 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11923 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11924 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11925 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11926 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 11928 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11929 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11930 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11931 | // MIs[1] Operand 1 |
| 11932 | // No operand predicates |
| 11933 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11934 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11935 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11936 | // MIs[2] Operand 1 |
| 11937 | // No operand predicates |
| 11938 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11939 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11940 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 11941 | // MIs[3] Operand 1 |
| 11942 | // No operand predicates |
| 11943 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11944 | // (intrinsic_wo_chain:{ *:[v512i1] } 9954:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 11945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11946 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11947 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11948 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11949 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11951 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11952 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11953 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 11954 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 11955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2), |
| 11956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 11957 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11958 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 11959 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 11960 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 11961 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 11962 | GIR_RootConstrainSelectedInstOperands, |
| 11963 | // GIR_Coverage, 3574, |
| 11964 | GIR_EraseRootFromParent_Done, |
| 11965 | // Label 860: @29236 |
| 11966 | GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(29367), // Rule ID 3577 // |
| 11967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 11968 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8), |
| 11969 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 11970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 11971 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 11972 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 11973 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 11974 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 11975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 11976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 11977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11978 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11979 | // MIs[1] Operand 1 |
| 11980 | // No operand predicates |
| 11981 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 11982 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11983 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 11984 | // MIs[2] Operand 1 |
| 11985 | // No operand predicates |
| 11986 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 11987 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 11988 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), |
| 11989 | // MIs[3] Operand 1 |
| 11990 | // No operand predicates |
| 11991 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 11992 | // (intrinsic_wo_chain:{ *:[v512i1] } 9958:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) |
| 11993 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11994 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 11995 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11996 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 11997 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 11998 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 11999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 12002 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8W), |
| 12004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12005 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12006 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12007 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12008 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12009 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12010 | GIR_RootConstrainSelectedInstOperands, |
| 12011 | // GIR_Coverage, 3577, |
| 12012 | GIR_EraseRootFromParent_Done, |
| 12013 | // Label 861: @29367 |
| 12014 | GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(29498), // Rule ID 3579 // |
| 12015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12016 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4), |
| 12017 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12018 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12019 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12020 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 12021 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12022 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 12025 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12026 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12027 | // MIs[1] Operand 1 |
| 12028 | // No operand predicates |
| 12029 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 12030 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12031 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12032 | // MIs[2] Operand 1 |
| 12033 | // No operand predicates |
| 12034 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 12035 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12036 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12037 | // MIs[3] Operand 1 |
| 12038 | // No operand predicates |
| 12039 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12040 | // (intrinsic_wo_chain:{ *:[v512i1] } 9960:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) |
| 12041 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12042 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12043 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12044 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12045 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 12046 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12049 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 12050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4W), |
| 12052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12053 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12054 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12055 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12056 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12057 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12058 | GIR_RootConstrainSelectedInstOperands, |
| 12059 | // GIR_Coverage, 3579, |
| 12060 | GIR_EraseRootFromParent_Done, |
| 12061 | // Label 862: @29498 |
| 12062 | GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(29629), // Rule ID 3581 // |
| 12063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2s), |
| 12065 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12066 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12067 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12068 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 12069 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12070 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12072 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 12073 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12074 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12075 | // MIs[1] Operand 1 |
| 12076 | // No operand predicates |
| 12077 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 12078 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12079 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12080 | // MIs[2] Operand 1 |
| 12081 | // No operand predicates |
| 12082 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 12083 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12084 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12085 | // MIs[3] Operand 1 |
| 12086 | // No operand predicates |
| 12087 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12088 | // (intrinsic_wo_chain:{ *:[v512i1] } 9956:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SW:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 12089 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12090 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12091 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12092 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12093 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 12094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12097 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 12098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SW), |
| 12100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12101 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12102 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12103 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12104 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12105 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12106 | GIR_RootConstrainSelectedInstOperands, |
| 12107 | // GIR_Coverage, 3581, |
| 12108 | GIR_EraseRootFromParent_Done, |
| 12109 | // Label 863: @29629 |
| 12110 | GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(29760), // Rule ID 3583 // |
| 12111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12112 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2), |
| 12113 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12114 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12115 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12116 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 12117 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12118 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12120 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 12121 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12122 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12123 | // MIs[1] Operand 1 |
| 12124 | // No operand predicates |
| 12125 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 12126 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12127 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12128 | // MIs[2] Operand 1 |
| 12129 | // No operand predicates |
| 12130 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 12131 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12132 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12133 | // MIs[3] Operand 1 |
| 12134 | // No operand predicates |
| 12135 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12136 | // (intrinsic_wo_chain:{ *:[v512i1] } 9939:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 12137 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12138 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12139 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12140 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12141 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 12142 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12143 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12144 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12145 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 12146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2W), |
| 12148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12149 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12150 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12151 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12152 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12153 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12154 | GIR_RootConstrainSelectedInstOperands, |
| 12155 | // GIR_Coverage, 3583, |
| 12156 | GIR_EraseRootFromParent_Done, |
| 12157 | // Label 864: @29760 |
| 12158 | GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(29891), // Rule ID 3598 // |
| 12159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12160 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2), |
| 12161 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12162 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12163 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12164 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 12165 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12166 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 12169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12170 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12171 | // MIs[1] Operand 1 |
| 12172 | // No operand predicates |
| 12173 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 12174 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12175 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12176 | // MIs[2] Operand 1 |
| 12177 | // No operand predicates |
| 12178 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 12179 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12180 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12181 | // MIs[3] Operand 1 |
| 12182 | // No operand predicates |
| 12183 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12184 | // (intrinsic_wo_chain:{ *:[v512i1] } 9934:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 12185 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12186 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12187 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12188 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12189 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 12190 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12191 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12192 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12193 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 12194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2W), |
| 12196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12199 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12200 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12201 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12202 | GIR_RootConstrainSelectedInstOperands, |
| 12203 | // GIR_Coverage, 3598, |
| 12204 | GIR_EraseRootFromParent_Done, |
| 12205 | // Label 865: @29891 |
| 12206 | GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(30022), // Rule ID 3603 // |
| 12207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2), |
| 12209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 12211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12212 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 12213 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12214 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12216 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 12217 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12218 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12219 | // MIs[1] Operand 1 |
| 12220 | // No operand predicates |
| 12221 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2] |
| 12222 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12223 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12224 | // MIs[2] Operand 1 |
| 12225 | // No operand predicates |
| 12226 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/6, // MIs[3] |
| 12227 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12228 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12229 | // MIs[3] Operand 1 |
| 12230 | // No operand predicates |
| 12231 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12232 | // (intrinsic_wo_chain:{ *:[v512i1] } 9954:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2W:{ *:[v512i1] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 12233 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12234 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12235 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12236 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12237 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // XB |
| 12238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12239 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12240 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12241 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // XA |
| 12242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2W), |
| 12244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12247 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12248 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12249 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12250 | GIR_RootConstrainSelectedInstOperands, |
| 12251 | // GIR_Coverage, 3603, |
| 12252 | GIR_EraseRootFromParent_Done, |
| 12253 | // Label 866: @30022 |
| 12254 | GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(30140), // Rule ID 3560 // |
| 12255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12256 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpp), |
| 12257 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12258 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12259 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12260 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12261 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12262 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12264 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12265 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12266 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12267 | // MIs[1] Operand 1 |
| 12268 | // No operand predicates |
| 12269 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12270 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12271 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12272 | // MIs[2] Operand 1 |
| 12273 | // No operand predicates |
| 12274 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12275 | // (intrinsic_wo_chain:{ *:[v512i1] } 9948:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12276 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12277 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12278 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12279 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12280 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12282 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12283 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12284 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12285 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERPP), |
| 12287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12288 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12289 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12290 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12291 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12292 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12293 | GIR_RootConstrainSelectedInstOperands, |
| 12294 | // GIR_Coverage, 3560, |
| 12295 | GIR_EraseRootFromParent_Done, |
| 12296 | // Label 867: @30140 |
| 12297 | GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(30258), // Rule ID 3561 // |
| 12298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12299 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpn), |
| 12300 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12301 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12302 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12303 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12304 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12305 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12307 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12308 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12309 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12310 | // MIs[1] Operand 1 |
| 12311 | // No operand predicates |
| 12312 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12313 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12314 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12315 | // MIs[2] Operand 1 |
| 12316 | // No operand predicates |
| 12317 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12318 | // (intrinsic_wo_chain:{ *:[v512i1] } 9947:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12319 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12320 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12321 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12322 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12323 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12325 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12326 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12327 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERPN), |
| 12330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12331 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12332 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12333 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12334 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12335 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12336 | GIR_RootConstrainSelectedInstOperands, |
| 12337 | // GIR_Coverage, 3561, |
| 12338 | GIR_EraseRootFromParent_Done, |
| 12339 | // Label 868: @30258 |
| 12340 | GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(30376), // Rule ID 3562 // |
| 12341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12342 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernp), |
| 12343 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12344 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12345 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12346 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12347 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12348 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12350 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12351 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12352 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12353 | // MIs[1] Operand 1 |
| 12354 | // No operand predicates |
| 12355 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12356 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12357 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12358 | // MIs[2] Operand 1 |
| 12359 | // No operand predicates |
| 12360 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12361 | // (intrinsic_wo_chain:{ *:[v512i1] } 9946:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12363 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12364 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12365 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12366 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12367 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12368 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12369 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12370 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERNP), |
| 12373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12374 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12375 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12376 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12377 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12378 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12379 | GIR_RootConstrainSelectedInstOperands, |
| 12380 | // GIR_Coverage, 3562, |
| 12381 | GIR_EraseRootFromParent_Done, |
| 12382 | // Label 869: @30376 |
| 12383 | GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(30494), // Rule ID 3563 // |
| 12384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12385 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernn), |
| 12386 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12387 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12388 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12389 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12390 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12391 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12393 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12394 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12395 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12396 | // MIs[1] Operand 1 |
| 12397 | // No operand predicates |
| 12398 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12399 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12400 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12401 | // MIs[2] Operand 1 |
| 12402 | // No operand predicates |
| 12403 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12404 | // (intrinsic_wo_chain:{ *:[v512i1] } 9945:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12405 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12406 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12407 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12408 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12409 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12410 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12413 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12414 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERNN), |
| 12416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12417 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12418 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12419 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12420 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12421 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12422 | GIR_RootConstrainSelectedInstOperands, |
| 12423 | // GIR_Coverage, 3563, |
| 12424 | GIR_EraseRootFromParent_Done, |
| 12425 | // Label 870: @30494 |
| 12426 | GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(30593), // Rule ID 3565 // |
| 12427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12428 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpp), |
| 12429 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12431 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12432 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12433 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12434 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12436 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12437 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12438 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12439 | // MIs[1] Operand 1 |
| 12440 | // No operand predicates |
| 12441 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12442 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12443 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12444 | // MIs[2] Operand 1 |
| 12445 | // No operand predicates |
| 12446 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12447 | // (intrinsic_wo_chain:{ *:[v512i1] } 9953:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12448 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12449 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12450 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12451 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12452 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERPP), |
| 12454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12455 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12456 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12457 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12458 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12459 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12460 | GIR_RootConstrainSelectedInstOperands, |
| 12461 | // GIR_Coverage, 3565, |
| 12462 | GIR_EraseRootFromParent_Done, |
| 12463 | // Label 871: @30593 |
| 12464 | GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(30692), // Rule ID 3566 // |
| 12465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpn), |
| 12467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12468 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12469 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12470 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12471 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12472 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12474 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12475 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12476 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12477 | // MIs[1] Operand 1 |
| 12478 | // No operand predicates |
| 12479 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12480 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12481 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12482 | // MIs[2] Operand 1 |
| 12483 | // No operand predicates |
| 12484 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12485 | // (intrinsic_wo_chain:{ *:[v512i1] } 9952:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12486 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12487 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12488 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12489 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERPN), |
| 12492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12493 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12494 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12495 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12496 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12497 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12498 | GIR_RootConstrainSelectedInstOperands, |
| 12499 | // GIR_Coverage, 3566, |
| 12500 | GIR_EraseRootFromParent_Done, |
| 12501 | // Label 872: @30692 |
| 12502 | GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(30791), // Rule ID 3567 // |
| 12503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12504 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernp), |
| 12505 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12506 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12507 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12508 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12509 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12510 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12511 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12512 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12513 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12514 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12515 | // MIs[1] Operand 1 |
| 12516 | // No operand predicates |
| 12517 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12518 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12519 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12520 | // MIs[2] Operand 1 |
| 12521 | // No operand predicates |
| 12522 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12523 | // (intrinsic_wo_chain:{ *:[v512i1] } 9951:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12524 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12525 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12526 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12527 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERNP), |
| 12530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12531 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12532 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12534 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12535 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12536 | GIR_RootConstrainSelectedInstOperands, |
| 12537 | // GIR_Coverage, 3567, |
| 12538 | GIR_EraseRootFromParent_Done, |
| 12539 | // Label 873: @30791 |
| 12540 | GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(30890), // Rule ID 3568 // |
| 12541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12542 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernn), |
| 12543 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12544 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12545 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12546 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12547 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12548 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12550 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12551 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12552 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12553 | // MIs[1] Operand 1 |
| 12554 | // No operand predicates |
| 12555 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12556 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12557 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12558 | // MIs[2] Operand 1 |
| 12559 | // No operand predicates |
| 12560 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12561 | // (intrinsic_wo_chain:{ *:[v512i1] } 9950:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12562 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12563 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12564 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12565 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERNN), |
| 12568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12569 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12570 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12571 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12572 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12573 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12574 | GIR_RootConstrainSelectedInstOperands, |
| 12575 | // GIR_Coverage, 3568, |
| 12576 | GIR_EraseRootFromParent_Done, |
| 12577 | // Label 874: @30890 |
| 12578 | GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(31008), // Rule ID 3589 // |
| 12579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12580 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpp), |
| 12581 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12582 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12583 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12584 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12585 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12586 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12588 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12589 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12590 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12591 | // MIs[1] Operand 1 |
| 12592 | // No operand predicates |
| 12593 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12594 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12595 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12596 | // MIs[2] Operand 1 |
| 12597 | // No operand predicates |
| 12598 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12599 | // (intrinsic_wo_chain:{ *:[v512i1] } 9948:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12601 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12602 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12603 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12604 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12605 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12606 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12607 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12608 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12609 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWPP), |
| 12611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12612 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12613 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12614 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12615 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12616 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12617 | GIR_RootConstrainSelectedInstOperands, |
| 12618 | // GIR_Coverage, 3589, |
| 12619 | GIR_EraseRootFromParent_Done, |
| 12620 | // Label 875: @31008 |
| 12621 | GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(31126), // Rule ID 3590 // |
| 12622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12623 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gerpn), |
| 12624 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12625 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12626 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12627 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12628 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12629 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12631 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12632 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12633 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12634 | // MIs[1] Operand 1 |
| 12635 | // No operand predicates |
| 12636 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12637 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12638 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12639 | // MIs[2] Operand 1 |
| 12640 | // No operand predicates |
| 12641 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12642 | // (intrinsic_wo_chain:{ *:[v512i1] } 9947:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12643 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12644 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12645 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12646 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12647 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12648 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12649 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12651 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12652 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWPN), |
| 12654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12655 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12656 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12657 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12658 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12659 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12660 | GIR_RootConstrainSelectedInstOperands, |
| 12661 | // GIR_Coverage, 3590, |
| 12662 | GIR_EraseRootFromParent_Done, |
| 12663 | // Label 876: @31126 |
| 12664 | GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(31244), // Rule ID 3591 // |
| 12665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12666 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernp), |
| 12667 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12668 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12669 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12670 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12671 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12672 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12674 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12675 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12676 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12677 | // MIs[1] Operand 1 |
| 12678 | // No operand predicates |
| 12679 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12680 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12681 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12682 | // MIs[2] Operand 1 |
| 12683 | // No operand predicates |
| 12684 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12685 | // (intrinsic_wo_chain:{ *:[v512i1] } 9946:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12687 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12688 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12689 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12690 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12692 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12693 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12694 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWNP), |
| 12697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12698 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12699 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12700 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12701 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12702 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12703 | GIR_RootConstrainSelectedInstOperands, |
| 12704 | // GIR_Coverage, 3591, |
| 12705 | GIR_EraseRootFromParent_Done, |
| 12706 | // Label 877: @31244 |
| 12707 | GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(31362), // Rule ID 3592 // |
| 12708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12709 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf32gernn), |
| 12710 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12711 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12712 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12713 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12714 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12715 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12717 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12718 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12719 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12720 | // MIs[1] Operand 1 |
| 12721 | // No operand predicates |
| 12722 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12723 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12724 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12725 | // MIs[2] Operand 1 |
| 12726 | // No operand predicates |
| 12727 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12728 | // (intrinsic_wo_chain:{ *:[v512i1] } 9945:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) => (PMXVF32GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK) |
| 12729 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12730 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12731 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12732 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12733 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12735 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12736 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12737 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12738 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF32GERWNN), |
| 12740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12741 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12742 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12743 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12744 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12745 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12746 | GIR_RootConstrainSelectedInstOperands, |
| 12747 | // GIR_Coverage, 3592, |
| 12748 | GIR_EraseRootFromParent_Done, |
| 12749 | // Label 878: @31362 |
| 12750 | GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(31461), // Rule ID 3594 // |
| 12751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12752 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpp), |
| 12753 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12754 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12755 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12756 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12757 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12758 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12760 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12761 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12762 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12763 | // MIs[1] Operand 1 |
| 12764 | // No operand predicates |
| 12765 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12766 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12767 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12768 | // MIs[2] Operand 1 |
| 12769 | // No operand predicates |
| 12770 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12771 | // (intrinsic_wo_chain:{ *:[v512i1] } 9953:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12774 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12775 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWPP), |
| 12778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12779 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12780 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12781 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12782 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12783 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12784 | GIR_RootConstrainSelectedInstOperands, |
| 12785 | // GIR_Coverage, 3594, |
| 12786 | GIR_EraseRootFromParent_Done, |
| 12787 | // Label 879: @31461 |
| 12788 | GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(31560), // Rule ID 3595 // |
| 12789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12790 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gerpn), |
| 12791 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12792 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12793 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12794 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12795 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12796 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12800 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12801 | // MIs[1] Operand 1 |
| 12802 | // No operand predicates |
| 12803 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12804 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12805 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12806 | // MIs[2] Operand 1 |
| 12807 | // No operand predicates |
| 12808 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12809 | // (intrinsic_wo_chain:{ *:[v512i1] } 9952:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12810 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12811 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12812 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12813 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12814 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWPN), |
| 12816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12817 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12818 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12819 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12820 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12821 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12822 | GIR_RootConstrainSelectedInstOperands, |
| 12823 | // GIR_Coverage, 3595, |
| 12824 | GIR_EraseRootFromParent_Done, |
| 12825 | // Label 880: @31560 |
| 12826 | GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(31659), // Rule ID 3596 // |
| 12827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12828 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernp), |
| 12829 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12830 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12831 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12832 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12833 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12834 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12837 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12838 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12839 | // MIs[1] Operand 1 |
| 12840 | // No operand predicates |
| 12841 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12842 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12843 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12844 | // MIs[2] Operand 1 |
| 12845 | // No operand predicates |
| 12846 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12847 | // (intrinsic_wo_chain:{ *:[v512i1] } 9951:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12851 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12852 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWNP), |
| 12854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12855 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12856 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12857 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12858 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12859 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12860 | GIR_RootConstrainSelectedInstOperands, |
| 12861 | // GIR_Coverage, 3596, |
| 12862 | GIR_EraseRootFromParent_Done, |
| 12863 | // Label 881: @31659 |
| 12864 | GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(31758), // Rule ID 3597 // |
| 12865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 12866 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf64gernn), |
| 12867 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12868 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12869 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v256s1, |
| 12870 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12871 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12872 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 12874 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12875 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12876 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12877 | // MIs[1] Operand 1 |
| 12878 | // No operand predicates |
| 12879 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12880 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12881 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 12882 | // MIs[2] Operand 1 |
| 12883 | // No operand predicates |
| 12884 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 12885 | // (intrinsic_wo_chain:{ *:[v512i1] } 9950:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v256i1:{ *:[v256i1] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) => (PMXVF64GERWNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, ?:{ *:[v256i1] }:$XA, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$YMSK) |
| 12886 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12887 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12888 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12889 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF64GERWNN), |
| 12892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12893 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12894 | GIR_RootToRootCopy, /*OpIdx*/3, // XA |
| 12895 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12896 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12897 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12898 | GIR_RootConstrainSelectedInstOperands, |
| 12899 | // GIR_Coverage, 3597, |
| 12900 | GIR_EraseRootFromParent_Done, |
| 12901 | // Label 882: @31758 |
| 12902 | GIM_Reject, |
| 12903 | // Label 854: @31759 |
| 12904 | GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(35304), |
| 12905 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 12906 | GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(31903), // Rule ID 3549 // |
| 12907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8pp), |
| 12909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12912 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12913 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12914 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12915 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 12916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12917 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12918 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12919 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12920 | // MIs[1] Operand 1 |
| 12921 | // No operand predicates |
| 12922 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12923 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12924 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12925 | // MIs[2] Operand 1 |
| 12926 | // No operand predicates |
| 12927 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 12928 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12929 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), |
| 12930 | // MIs[3] Operand 1 |
| 12931 | // No operand predicates |
| 12932 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12933 | // (intrinsic_wo_chain:{ *:[v512i1] } 9959:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) |
| 12934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12935 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12936 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12937 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12938 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12940 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12941 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12942 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8PP), |
| 12945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12946 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12947 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12948 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12949 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 12950 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 12951 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 12952 | GIR_RootConstrainSelectedInstOperands, |
| 12953 | // GIR_Coverage, 3549, |
| 12954 | GIR_EraseRootFromParent_Done, |
| 12955 | // Label 884: @31903 |
| 12956 | GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(32039), // Rule ID 3551 // |
| 12957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 12958 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4pp), |
| 12959 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 12960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 12961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 12962 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 12963 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 12964 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 12965 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 12966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 12967 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 12968 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12969 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12970 | // MIs[1] Operand 1 |
| 12971 | // No operand predicates |
| 12972 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 12973 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12974 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12975 | // MIs[2] Operand 1 |
| 12976 | // No operand predicates |
| 12977 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 12978 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 12979 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 12980 | // MIs[3] Operand 1 |
| 12981 | // No operand predicates |
| 12982 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 12983 | // (intrinsic_wo_chain:{ *:[v512i1] } 9961:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) |
| 12984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12985 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 12986 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12987 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12988 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 12989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12990 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12991 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 12992 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 12993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4PP), |
| 12995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 12996 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 12997 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12998 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 12999 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13000 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13001 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13002 | GIR_RootConstrainSelectedInstOperands, |
| 13003 | // GIR_Coverage, 3551, |
| 13004 | GIR_EraseRootFromParent_Done, |
| 13005 | // Label 885: @32039 |
| 13006 | GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(32175), // Rule ID 3553 // |
| 13007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13008 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2spp), |
| 13009 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13012 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13013 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13014 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13015 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13017 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13018 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13019 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13020 | // MIs[1] Operand 1 |
| 13021 | // No operand predicates |
| 13022 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13023 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13024 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13025 | // MIs[2] Operand 1 |
| 13026 | // No operand predicates |
| 13027 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13028 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13029 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13030 | // MIs[3] Operand 1 |
| 13031 | // No operand predicates |
| 13032 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13033 | // (intrinsic_wo_chain:{ *:[v512i1] } 9957:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13035 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13036 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13037 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13038 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13040 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13041 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13042 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SPP), |
| 13045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13046 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13048 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13049 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13050 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13051 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13052 | GIR_RootConstrainSelectedInstOperands, |
| 13053 | // GIR_Coverage, 3553, |
| 13054 | GIR_EraseRootFromParent_Done, |
| 13055 | // Label 886: @32175 |
| 13056 | GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(32311), // Rule ID 3555 // |
| 13057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pp), |
| 13059 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13062 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13063 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13064 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13065 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13067 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13068 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13069 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13070 | // MIs[1] Operand 1 |
| 13071 | // No operand predicates |
| 13072 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13073 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13074 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13075 | // MIs[2] Operand 1 |
| 13076 | // No operand predicates |
| 13077 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13078 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13079 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13080 | // MIs[3] Operand 1 |
| 13081 | // No operand predicates |
| 13082 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13083 | // (intrinsic_wo_chain:{ *:[v512i1] } 9943:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13085 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13086 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13087 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13088 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13090 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13091 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13092 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13093 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2PP), |
| 13095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13096 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13097 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13098 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13099 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13100 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13101 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13102 | GIR_RootConstrainSelectedInstOperands, |
| 13103 | // GIR_Coverage, 3555, |
| 13104 | GIR_EraseRootFromParent_Done, |
| 13105 | // Label 887: @32311 |
| 13106 | GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(32447), // Rule ID 3556 // |
| 13107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pn), |
| 13109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13111 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13112 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13113 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13114 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13115 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13117 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13118 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13119 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13120 | // MIs[1] Operand 1 |
| 13121 | // No operand predicates |
| 13122 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13123 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13124 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13125 | // MIs[2] Operand 1 |
| 13126 | // No operand predicates |
| 13127 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13128 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13129 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13130 | // MIs[3] Operand 1 |
| 13131 | // No operand predicates |
| 13132 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13133 | // (intrinsic_wo_chain:{ *:[v512i1] } 9942:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13135 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13136 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13137 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13138 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13142 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2PN), |
| 13145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13146 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13147 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13148 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13149 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13150 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13151 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13152 | GIR_RootConstrainSelectedInstOperands, |
| 13153 | // GIR_Coverage, 3556, |
| 13154 | GIR_EraseRootFromParent_Done, |
| 13155 | // Label 888: @32447 |
| 13156 | GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(32583), // Rule ID 3557 // |
| 13157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2np), |
| 13159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13162 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13163 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13164 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13165 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13167 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13168 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13169 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13170 | // MIs[1] Operand 1 |
| 13171 | // No operand predicates |
| 13172 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13173 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13174 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13175 | // MIs[2] Operand 1 |
| 13176 | // No operand predicates |
| 13177 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13178 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13179 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13180 | // MIs[3] Operand 1 |
| 13181 | // No operand predicates |
| 13182 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13183 | // (intrinsic_wo_chain:{ *:[v512i1] } 9941:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13184 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13185 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13186 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13187 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13188 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13189 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13190 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13191 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13192 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2NP), |
| 13195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13196 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13199 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13200 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13201 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13202 | GIR_RootConstrainSelectedInstOperands, |
| 13203 | // GIR_Coverage, 3557, |
| 13204 | GIR_EraseRootFromParent_Done, |
| 13205 | // Label 889: @32583 |
| 13206 | GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(32719), // Rule ID 3558 // |
| 13207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13208 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2nn), |
| 13209 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13210 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13211 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13212 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13213 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13214 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13215 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13217 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13218 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13219 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13220 | // MIs[1] Operand 1 |
| 13221 | // No operand predicates |
| 13222 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13223 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13224 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13225 | // MIs[2] Operand 1 |
| 13226 | // No operand predicates |
| 13227 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13228 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13229 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13230 | // MIs[3] Operand 1 |
| 13231 | // No operand predicates |
| 13232 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13233 | // (intrinsic_wo_chain:{ *:[v512i1] } 9940:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13234 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13235 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13236 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13237 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13238 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13240 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13241 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13242 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13243 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2NN), |
| 13245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13246 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13247 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13248 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13249 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13250 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13251 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13252 | GIR_RootConstrainSelectedInstOperands, |
| 13253 | // GIR_Coverage, 3558, |
| 13254 | GIR_EraseRootFromParent_Done, |
| 13255 | // Label 890: @32719 |
| 13256 | GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(32855), // Rule ID 3570 // |
| 13257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13258 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pp), |
| 13259 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13261 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13262 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13263 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13264 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13265 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13267 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13268 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13269 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13270 | // MIs[1] Operand 1 |
| 13271 | // No operand predicates |
| 13272 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13273 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13274 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13275 | // MIs[2] Operand 1 |
| 13276 | // No operand predicates |
| 13277 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13278 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13279 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13280 | // MIs[3] Operand 1 |
| 13281 | // No operand predicates |
| 13282 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13283 | // (intrinsic_wo_chain:{ *:[v512i1] } 9938:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13284 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13285 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13286 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13287 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13288 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13290 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13291 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13292 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2PP), |
| 13295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13296 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13298 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13299 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13300 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13301 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13302 | GIR_RootConstrainSelectedInstOperands, |
| 13303 | // GIR_Coverage, 3570, |
| 13304 | GIR_EraseRootFromParent_Done, |
| 13305 | // Label 891: @32855 |
| 13306 | GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(32991), // Rule ID 3571 // |
| 13307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13308 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pn), |
| 13309 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13310 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13311 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13312 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13313 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13314 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13315 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13318 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13319 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13320 | // MIs[1] Operand 1 |
| 13321 | // No operand predicates |
| 13322 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13323 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13324 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13325 | // MIs[2] Operand 1 |
| 13326 | // No operand predicates |
| 13327 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13328 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13329 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13330 | // MIs[3] Operand 1 |
| 13331 | // No operand predicates |
| 13332 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13333 | // (intrinsic_wo_chain:{ *:[v512i1] } 9937:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2PN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13334 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13335 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13336 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13337 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13338 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13339 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13340 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13341 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13342 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2PN), |
| 13345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13346 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13347 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13348 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13349 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13350 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13351 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13352 | GIR_RootConstrainSelectedInstOperands, |
| 13353 | // GIR_Coverage, 3571, |
| 13354 | GIR_EraseRootFromParent_Done, |
| 13355 | // Label 892: @32991 |
| 13356 | GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(33127), // Rule ID 3572 // |
| 13357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13358 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2np), |
| 13359 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13361 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13362 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13363 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13364 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13365 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13367 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13368 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13369 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13370 | // MIs[1] Operand 1 |
| 13371 | // No operand predicates |
| 13372 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13373 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13374 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13375 | // MIs[2] Operand 1 |
| 13376 | // No operand predicates |
| 13377 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13378 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13379 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13380 | // MIs[3] Operand 1 |
| 13381 | // No operand predicates |
| 13382 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13383 | // (intrinsic_wo_chain:{ *:[v512i1] } 9936:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2NP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13385 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13386 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13387 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13388 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13389 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13390 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13391 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13392 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13393 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2NP), |
| 13395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13396 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13397 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13398 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13399 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13400 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13401 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13402 | GIR_RootConstrainSelectedInstOperands, |
| 13403 | // GIR_Coverage, 3572, |
| 13404 | GIR_EraseRootFromParent_Done, |
| 13405 | // Label 893: @33127 |
| 13406 | GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(33263), // Rule ID 3573 // |
| 13407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13408 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2nn), |
| 13409 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13410 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13411 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13412 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13413 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13414 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13415 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13417 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13418 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13419 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13420 | // MIs[1] Operand 1 |
| 13421 | // No operand predicates |
| 13422 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13423 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13424 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13425 | // MIs[2] Operand 1 |
| 13426 | // No operand predicates |
| 13427 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13428 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13429 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13430 | // MIs[3] Operand 1 |
| 13431 | // No operand predicates |
| 13432 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13433 | // (intrinsic_wo_chain:{ *:[v512i1] } 9935:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2NN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13434 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13435 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13436 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13437 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13438 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13439 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13441 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13442 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13443 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2NN), |
| 13445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13446 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13447 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13448 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13449 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13450 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13451 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13452 | GIR_RootConstrainSelectedInstOperands, |
| 13453 | // GIR_Coverage, 3573, |
| 13454 | GIR_EraseRootFromParent_Done, |
| 13455 | // Label 894: @33263 |
| 13456 | GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(33399), // Rule ID 3575 // |
| 13457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4spp), |
| 13459 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13462 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13463 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13464 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13465 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13467 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13468 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13469 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13470 | // MIs[1] Operand 1 |
| 13471 | // No operand predicates |
| 13472 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13473 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13474 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13475 | // MIs[2] Operand 1 |
| 13476 | // No operand predicates |
| 13477 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13478 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13479 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13480 | // MIs[3] Operand 1 |
| 13481 | // No operand predicates |
| 13482 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13483 | // (intrinsic_wo_chain:{ *:[v512i1] } 9962:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI8GER4SPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13484 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13485 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13486 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13487 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13488 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13489 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13490 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13491 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13492 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13493 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4SPP), |
| 13495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13496 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13497 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13498 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13499 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13500 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13501 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13502 | GIR_RootConstrainSelectedInstOperands, |
| 13503 | // GIR_Coverage, 3575, |
| 13504 | GIR_EraseRootFromParent_Done, |
| 13505 | // Label 895: @33399 |
| 13506 | GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(33535), // Rule ID 3576 // |
| 13507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISAFuture_MMA_PrefixInstrs), |
| 13508 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2pp), |
| 13509 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13510 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13511 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13512 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13513 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13514 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13515 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 13517 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13518 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13519 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13520 | // MIs[1] Operand 1 |
| 13521 | // No operand predicates |
| 13522 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13523 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13524 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13525 | // MIs[2] Operand 1 |
| 13526 | // No operand predicates |
| 13527 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13528 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13529 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13530 | // MIs[3] Operand 1 |
| 13531 | // No operand predicates |
| 13532 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13533 | // (intrinsic_wo_chain:{ *:[v512i1] } 9955:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2PP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13534 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13535 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13536 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13537 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13538 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13539 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13540 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13541 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13542 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13543 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2PP), |
| 13545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13546 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13548 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13549 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13550 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13551 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13552 | GIR_RootConstrainSelectedInstOperands, |
| 13553 | // GIR_Coverage, 3576, |
| 13554 | GIR_EraseRootFromParent_Done, |
| 13555 | // Label 896: @33535 |
| 13556 | GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(33671), // Rule ID 3578 // |
| 13557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13558 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi4ger8pp), |
| 13559 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13561 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13562 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13563 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13564 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13565 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13568 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13569 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13570 | // MIs[1] Operand 1 |
| 13571 | // No operand predicates |
| 13572 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13573 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13574 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13575 | // MIs[2] Operand 1 |
| 13576 | // No operand predicates |
| 13577 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13578 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13579 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk8Imm), |
| 13580 | // MIs[3] Operand 1 |
| 13581 | // No operand predicates |
| 13582 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13583 | // (intrinsic_wo_chain:{ *:[v512i1] } 9959:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) => (PMXVI4GER8WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk8Imm>>:$PMSK) |
| 13584 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13585 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13586 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13587 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13588 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13589 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13590 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13591 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13592 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI4GER8WPP), |
| 13595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13596 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13597 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13598 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13599 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13600 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13601 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13602 | GIR_RootConstrainSelectedInstOperands, |
| 13603 | // GIR_Coverage, 3578, |
| 13604 | GIR_EraseRootFromParent_Done, |
| 13605 | // Label 897: @33671 |
| 13606 | GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(33807), // Rule ID 3580 // |
| 13607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13608 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4pp), |
| 13609 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13611 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13612 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13613 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13614 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13615 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13617 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13618 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13619 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13620 | // MIs[1] Operand 1 |
| 13621 | // No operand predicates |
| 13622 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13623 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13624 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13625 | // MIs[2] Operand 1 |
| 13626 | // No operand predicates |
| 13627 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13628 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13629 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13630 | // MIs[3] Operand 1 |
| 13631 | // No operand predicates |
| 13632 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13633 | // (intrinsic_wo_chain:{ *:[v512i1] } 9961:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) => (PMXVI8GER4WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$PMSK) |
| 13634 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13635 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13636 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13637 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13638 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13639 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13640 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13641 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13642 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13643 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4WPP), |
| 13645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13646 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13647 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13648 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13649 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13650 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13651 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13652 | GIR_RootConstrainSelectedInstOperands, |
| 13653 | // GIR_Coverage, 3580, |
| 13654 | GIR_EraseRootFromParent_Done, |
| 13655 | // Label 898: @33807 |
| 13656 | GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(33943), // Rule ID 3582 // |
| 13657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13658 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2spp), |
| 13659 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13662 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13663 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13664 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13665 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13667 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13668 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13669 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13670 | // MIs[1] Operand 1 |
| 13671 | // No operand predicates |
| 13672 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13673 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13674 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13675 | // MIs[2] Operand 1 |
| 13676 | // No operand predicates |
| 13677 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13678 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13679 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13680 | // MIs[3] Operand 1 |
| 13681 | // No operand predicates |
| 13682 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13683 | // (intrinsic_wo_chain:{ *:[v512i1] } 9957:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2SWPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13684 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13685 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13686 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13687 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13688 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13689 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13690 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13691 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13692 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13693 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2SWPP), |
| 13695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13696 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13697 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13698 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13699 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13700 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13701 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13702 | GIR_RootConstrainSelectedInstOperands, |
| 13703 | // GIR_Coverage, 3582, |
| 13704 | GIR_EraseRootFromParent_Done, |
| 13705 | // Label 899: @33943 |
| 13706 | GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(34079), // Rule ID 3584 // |
| 13707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13708 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pp), |
| 13709 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13710 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13712 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13713 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13714 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13715 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13717 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13718 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13719 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13720 | // MIs[1] Operand 1 |
| 13721 | // No operand predicates |
| 13722 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13723 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13724 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13725 | // MIs[2] Operand 1 |
| 13726 | // No operand predicates |
| 13727 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13728 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13729 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13730 | // MIs[3] Operand 1 |
| 13731 | // No operand predicates |
| 13732 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13733 | // (intrinsic_wo_chain:{ *:[v512i1] } 9943:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13734 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13735 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13736 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13737 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13738 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13740 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13741 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13742 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WPP), |
| 13745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13746 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13747 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13748 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13749 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13750 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13751 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13752 | GIR_RootConstrainSelectedInstOperands, |
| 13753 | // GIR_Coverage, 3584, |
| 13754 | GIR_EraseRootFromParent_Done, |
| 13755 | // Label 900: @34079 |
| 13756 | GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(34215), // Rule ID 3585 // |
| 13757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13758 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2pn), |
| 13759 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13761 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13762 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13763 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13764 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13765 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13768 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13769 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13770 | // MIs[1] Operand 1 |
| 13771 | // No operand predicates |
| 13772 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13773 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13774 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13775 | // MIs[2] Operand 1 |
| 13776 | // No operand predicates |
| 13777 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13778 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13779 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13780 | // MIs[3] Operand 1 |
| 13781 | // No operand predicates |
| 13782 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13783 | // (intrinsic_wo_chain:{ *:[v512i1] } 9942:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13785 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13786 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13787 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13788 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13790 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13791 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13792 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WPN), |
| 13795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13796 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13797 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13798 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13799 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13800 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13801 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13802 | GIR_RootConstrainSelectedInstOperands, |
| 13803 | // GIR_Coverage, 3585, |
| 13804 | GIR_EraseRootFromParent_Done, |
| 13805 | // Label 901: @34215 |
| 13806 | GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(34351), // Rule ID 3586 // |
| 13807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13808 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2np), |
| 13809 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13810 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13811 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13812 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13813 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13814 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13815 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13817 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13818 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13819 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13820 | // MIs[1] Operand 1 |
| 13821 | // No operand predicates |
| 13822 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13823 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13824 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13825 | // MIs[2] Operand 1 |
| 13826 | // No operand predicates |
| 13827 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13828 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13829 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13830 | // MIs[3] Operand 1 |
| 13831 | // No operand predicates |
| 13832 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13833 | // (intrinsic_wo_chain:{ *:[v512i1] } 9941:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13834 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13835 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13836 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13837 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13838 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13842 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WNP), |
| 13845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13846 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13847 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13848 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13849 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13850 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13851 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13852 | GIR_RootConstrainSelectedInstOperands, |
| 13853 | // GIR_Coverage, 3586, |
| 13854 | GIR_EraseRootFromParent_Done, |
| 13855 | // Label 902: @34351 |
| 13856 | GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(34487), // Rule ID 3587 // |
| 13857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13858 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvf16ger2nn), |
| 13859 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13860 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13861 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13862 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13863 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13864 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13865 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13867 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13868 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13869 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13870 | // MIs[1] Operand 1 |
| 13871 | // No operand predicates |
| 13872 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13873 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13874 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13875 | // MIs[2] Operand 1 |
| 13876 | // No operand predicates |
| 13877 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13878 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13879 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13880 | // MIs[3] Operand 1 |
| 13881 | // No operand predicates |
| 13882 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13883 | // (intrinsic_wo_chain:{ *:[v512i1] } 9940:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13884 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13885 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13886 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13887 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13888 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13890 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13891 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13892 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13893 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVF16GER2WNN), |
| 13895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13896 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13897 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13898 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13899 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13900 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13901 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13902 | GIR_RootConstrainSelectedInstOperands, |
| 13903 | // GIR_Coverage, 3587, |
| 13904 | GIR_EraseRootFromParent_Done, |
| 13905 | // Label 903: @34487 |
| 13906 | GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(34623), // Rule ID 3599 // |
| 13907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pp), |
| 13909 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13910 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13911 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13912 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13913 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13914 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13915 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13917 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13918 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13919 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13920 | // MIs[1] Operand 1 |
| 13921 | // No operand predicates |
| 13922 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13923 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13924 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13925 | // MIs[2] Operand 1 |
| 13926 | // No operand predicates |
| 13927 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13928 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13929 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13930 | // MIs[3] Operand 1 |
| 13931 | // No operand predicates |
| 13932 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13933 | // (intrinsic_wo_chain:{ *:[v512i1] } 9938:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13934 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13935 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13936 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13937 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13938 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13939 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13940 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13941 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13942 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WPP), |
| 13945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13946 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13947 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13948 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13949 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 13950 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 13951 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 13952 | GIR_RootConstrainSelectedInstOperands, |
| 13953 | // GIR_Coverage, 3599, |
| 13954 | GIR_EraseRootFromParent_Done, |
| 13955 | // Label 904: @34623 |
| 13956 | GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(34759), // Rule ID 3600 // |
| 13957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 13958 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2pn), |
| 13959 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 13960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 13961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 13962 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 13963 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 13964 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 13965 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 13966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 13967 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 13968 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13969 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13970 | // MIs[1] Operand 1 |
| 13971 | // No operand predicates |
| 13972 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 13973 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13974 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 13975 | // MIs[2] Operand 1 |
| 13976 | // No operand predicates |
| 13977 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 13978 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 13979 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 13980 | // MIs[3] Operand 1 |
| 13981 | // No operand predicates |
| 13982 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 13983 | // (intrinsic_wo_chain:{ *:[v512i1] } 9937:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WPN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 13984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13985 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 13986 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13987 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13988 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 13989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13990 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13991 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 13992 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 13993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WPN), |
| 13995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 13996 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 13997 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13998 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 13999 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 14000 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 14001 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 14002 | GIR_RootConstrainSelectedInstOperands, |
| 14003 | // GIR_Coverage, 3600, |
| 14004 | GIR_EraseRootFromParent_Done, |
| 14005 | // Label 905: @34759 |
| 14006 | GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(34895), // Rule ID 3601 // |
| 14007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 14008 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2np), |
| 14009 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 14010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 14011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 14012 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 14013 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 14014 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 14015 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 14016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 14017 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 14018 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14019 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14020 | // MIs[1] Operand 1 |
| 14021 | // No operand predicates |
| 14022 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 14023 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14024 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14025 | // MIs[2] Operand 1 |
| 14026 | // No operand predicates |
| 14027 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 14028 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14029 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 14030 | // MIs[3] Operand 1 |
| 14031 | // No operand predicates |
| 14032 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 14033 | // (intrinsic_wo_chain:{ *:[v512i1] } 9936:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WNP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 14034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14035 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 14036 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14037 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14038 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 14039 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 14040 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14041 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14042 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 14043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WNP), |
| 14045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 14046 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 14047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14048 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 14049 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 14050 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 14051 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 14052 | GIR_RootConstrainSelectedInstOperands, |
| 14053 | // GIR_Coverage, 3601, |
| 14054 | GIR_EraseRootFromParent_Done, |
| 14055 | // Label 906: @34895 |
| 14056 | GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(35031), // Rule ID 3602 // |
| 14057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 14058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvbf16ger2nn), |
| 14059 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 14060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 14061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 14062 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 14063 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 14064 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 14065 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 14066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 14067 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 14068 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14069 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14070 | // MIs[1] Operand 1 |
| 14071 | // No operand predicates |
| 14072 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 14073 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14074 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14075 | // MIs[2] Operand 1 |
| 14076 | // No operand predicates |
| 14077 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 14078 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14079 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 14080 | // MIs[3] Operand 1 |
| 14081 | // No operand predicates |
| 14082 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 14083 | // (intrinsic_wo_chain:{ *:[v512i1] } 9935:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVBF16GER2WNN:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 14084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14085 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 14086 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14087 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14088 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 14089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 14090 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14091 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14092 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 14093 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVBF16GER2WNN), |
| 14095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 14096 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 14097 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14098 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 14099 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 14100 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 14101 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 14102 | GIR_RootConstrainSelectedInstOperands, |
| 14103 | // GIR_Coverage, 3602, |
| 14104 | GIR_EraseRootFromParent_Done, |
| 14105 | // Label 907: @35031 |
| 14106 | GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(35167), // Rule ID 3604 // |
| 14107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 14108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi8ger4spp), |
| 14109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 14110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 14111 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 14112 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 14113 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 14114 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 14115 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 14116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::WACCRCRegClassID), |
| 14117 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 14118 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14119 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14120 | // MIs[1] Operand 1 |
| 14121 | // No operand predicates |
| 14122 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 14123 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14124 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14125 | // MIs[2] Operand 1 |
| 14126 | // No operand predicates |
| 14127 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 14128 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14129 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 14130 | // MIs[3] Operand 1 |
| 14131 | // No operand predicates |
| 14132 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 14133 | // (intrinsic_wo_chain:{ *:[v512i1] } 9962:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI8GER4WSPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 14134 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14135 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 14136 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14137 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14138 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 14139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 14140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14142 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 14143 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI8GER4WSPP), |
| 14145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 14146 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 14147 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14148 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 14149 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 14150 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 14151 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 14152 | GIR_RootConstrainSelectedInstOperands, |
| 14153 | // GIR_Coverage, 3604, |
| 14154 | GIR_EraseRootFromParent_Done, |
| 14155 | // Label 908: @35167 |
| 14156 | GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(35303), // Rule ID 3605 // |
| 14157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISAFuture_MMA_PrefixInstrs), |
| 14158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mma_pmxvi16ger2pp), |
| 14159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v512s1, |
| 14160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v512s1, |
| 14161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 14162 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 14163 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 14164 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 14165 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 14166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::ACCRCRegClassID), |
| 14167 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/5, // MIs[1] |
| 14168 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14169 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14170 | // MIs[1] Operand 1 |
| 14171 | // No operand predicates |
| 14172 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/6, // MIs[2] |
| 14173 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14174 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk4Imm), |
| 14175 | // MIs[2] Operand 1 |
| 14176 | // No operand predicates |
| 14177 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/7, // MIs[3] |
| 14178 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14179 | GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_Msk2Imm), |
| 14180 | // MIs[3] Operand 1 |
| 14181 | // No operand predicates |
| 14182 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 14183 | // (intrinsic_wo_chain:{ *:[v512i1] } 9955:{ *:[iPTR] }, v512i1:{ *:[v512i1] }:$ATi, v16i8:{ *:[v16i8] }:$XA, v16i8:{ *:[v16i8] }:$XB, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) => (PMXVI16GER2WPP:{ *:[v512i1] } ?:{ *:[v512i1] }:$ATi, (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XA, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$XB, VSRC:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$XMSK, (imm:{ *:[i32] })<<P:Predicate_Msk4Imm>>:$YMSK, (imm:{ *:[i32] })<<P:Predicate_Msk2Imm>>:$PMSK) |
| 14184 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14185 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 14186 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14187 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14188 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // XB |
| 14189 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 14190 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14191 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14192 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // XA |
| 14193 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PMXVI16GER2WPP), |
| 14195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[AT] |
| 14196 | GIR_RootToRootCopy, /*OpIdx*/2, // ATi |
| 14197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 14199 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // XMSK |
| 14200 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // YMSK |
| 14201 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // PMSK |
| 14202 | GIR_RootConstrainSelectedInstOperands, |
| 14203 | // GIR_Coverage, 3605, |
| 14204 | GIR_EraseRootFromParent_Done, |
| 14205 | // Label 909: @35303 |
| 14206 | GIM_Reject, |
| 14207 | // Label 883: @35304 |
| 14208 | GIM_Reject, |
| 14209 | // Label 20: @35305 |
| 14210 | GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(35644), |
| 14211 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 14212 | GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(35332), // Rule ID 103 // |
| 14213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_eieio), |
| 14214 | // (intrinsic_void 9878:{ *:[iPTR] }) => (PseudoEIEIO) |
| 14215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PseudoEIEIO), |
| 14216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14217 | GIR_RootConstrainSelectedInstOperands, |
| 14218 | // GIR_Coverage, 103, |
| 14219 | GIR_EraseRootFromParent_Done, |
| 14220 | // Label 911: @35332 |
| 14221 | GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(35357), // Rule ID 1184 // |
| 14222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 14223 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_sync), |
| 14224 | // (intrinsic_void 10033:{ *:[iPTR] }) => (SYNC 0:{ *:[i32] }) |
| 14225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 14226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14228 | GIR_RootConstrainSelectedInstOperands, |
| 14229 | // GIR_Coverage, 1184, |
| 14230 | GIR_EraseRootFromParent_Done, |
| 14231 | // Label 912: @35357 |
| 14232 | GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(35382), // Rule ID 1185 // |
| 14233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 14234 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_sync), |
| 14235 | // (intrinsic_void 9913:{ *:[iPTR] }) => (SYNC 0:{ *:[i32] }) |
| 14236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 14237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14239 | GIR_RootConstrainSelectedInstOperands, |
| 14240 | // GIR_Coverage, 1185, |
| 14241 | GIR_EraseRootFromParent_Done, |
| 14242 | // Label 913: @35382 |
| 14243 | GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(35407), // Rule ID 1186 // |
| 14244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 14245 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_lwsync), |
| 14246 | // (intrinsic_void 9918:{ *:[iPTR] }) => (SYNC 1:{ *:[i32] }) |
| 14247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 14248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 14249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14250 | GIR_RootConstrainSelectedInstOperands, |
| 14251 | // GIR_Coverage, 1186, |
| 14252 | GIR_EraseRootFromParent_Done, |
| 14253 | // Label 914: @35407 |
| 14254 | GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(35432), // Rule ID 1187 // |
| 14255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSYNC), |
| 14256 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_lwsync), |
| 14257 | // (intrinsic_void 9912:{ *:[iPTR] }) => (SYNC 1:{ *:[i32] }) |
| 14258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SYNC), |
| 14259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 14260 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14261 | GIR_RootConstrainSelectedInstOperands, |
| 14262 | // GIR_Coverage, 1187, |
| 14263 | GIR_EraseRootFromParent_Done, |
| 14264 | // Label 915: @35432 |
| 14265 | GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(35454), // Rule ID 1188 // |
| 14266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC), |
| 14267 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_sync), |
| 14268 | // (intrinsic_void 10033:{ *:[iPTR] }) => (MSYNC) |
| 14269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC), |
| 14270 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14271 | GIR_RootConstrainSelectedInstOperands, |
| 14272 | // GIR_Coverage, 1188, |
| 14273 | GIR_EraseRootFromParent_Done, |
| 14274 | // Label 916: @35454 |
| 14275 | GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(35476), // Rule ID 1189 // |
| 14276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC), |
| 14277 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_sync), |
| 14278 | // (intrinsic_void 9913:{ *:[iPTR] }) => (MSYNC) |
| 14279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC), |
| 14280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14281 | GIR_RootConstrainSelectedInstOperands, |
| 14282 | // GIR_Coverage, 1189, |
| 14283 | GIR_EraseRootFromParent_Done, |
| 14284 | // Label 917: @35476 |
| 14285 | GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(35498), // Rule ID 1190 // |
| 14286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC), |
| 14287 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_lwsync), |
| 14288 | // (intrinsic_void 9918:{ *:[iPTR] }) => (MSYNC) |
| 14289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC), |
| 14290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14291 | GIR_RootConstrainSelectedInstOperands, |
| 14292 | // GIR_Coverage, 1190, |
| 14293 | GIR_EraseRootFromParent_Done, |
| 14294 | // Label 918: @35498 |
| 14295 | GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(35520), // Rule ID 1191 // |
| 14296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasOnlyMSYNC), |
| 14297 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_lwsync), |
| 14298 | // (intrinsic_void 9912:{ *:[iPTR] }) => (MSYNC) |
| 14299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MSYNC), |
| 14300 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14301 | GIR_RootConstrainSelectedInstOperands, |
| 14302 | // GIR_Coverage, 1191, |
| 14303 | GIR_EraseRootFromParent_Done, |
| 14304 | // Label 919: @35520 |
| 14305 | GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(35539), // Rule ID 1192 // |
| 14306 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_eieio), |
| 14307 | // (intrinsic_void 9878:{ *:[iPTR] }) => (PseudoEIEIO) |
| 14308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PseudoEIEIO), |
| 14309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14310 | GIR_RootConstrainSelectedInstOperands, |
| 14311 | // GIR_Coverage, 1192, |
| 14312 | GIR_EraseRootFromParent_Done, |
| 14313 | // Label 920: @35539 |
| 14314 | GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(35558), // Rule ID 1193 // |
| 14315 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_iospace_eieio), |
| 14316 | // (intrinsic_void 9911:{ *:[iPTR] }) => (PseudoEIEIO) |
| 14317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PseudoEIEIO), |
| 14318 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14319 | GIR_RootConstrainSelectedInstOperands, |
| 14320 | // GIR_Coverage, 1193, |
| 14321 | GIR_EraseRootFromParent_Done, |
| 14322 | // Label 921: @35558 |
| 14323 | GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(35580), // Rule ID 1219 // |
| 14324 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_fence), |
| 14325 | // (intrinsic_void 9889:{ *:[iPTR] }) => (FENCE) |
| 14326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FENCE), |
| 14327 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0, |
| 14328 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14329 | GIR_RootConstrainSelectedInstOperands, |
| 14330 | // GIR_Coverage, 1219, |
| 14331 | GIR_EraseRootFromParent_Done, |
| 14332 | // Label 922: @35580 |
| 14333 | GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(35602), // Rule ID 1273 // |
| 14334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsAIX), |
| 14335 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dssall), |
| 14336 | // (intrinsic_void 9534:{ *:[iPTR] }) => (NOP) |
| 14337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::NOP), |
| 14338 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14339 | GIR_RootConstrainSelectedInstOperands, |
| 14340 | // GIR_Coverage, 1273, |
| 14341 | GIR_EraseRootFromParent_Done, |
| 14342 | // Label 923: @35602 |
| 14343 | GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(35624), // Rule ID 1274 // |
| 14344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotAIX), |
| 14345 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dssall), |
| 14346 | // (intrinsic_void 9534:{ *:[iPTR] }) => (DSSALL) |
| 14347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSSALL), |
| 14348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14349 | GIR_RootConstrainSelectedInstOperands, |
| 14350 | // GIR_Coverage, 1274, |
| 14351 | GIR_EraseRootFromParent_Done, |
| 14352 | // Label 924: @35624 |
| 14353 | GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(35643), // Rule ID 4807 // |
| 14354 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_isync), |
| 14355 | // (intrinsic_void 9914:{ *:[iPTR] }) => (ISYNC) |
| 14356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ISYNC), |
| 14357 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14358 | GIR_RootConstrainSelectedInstOperands, |
| 14359 | // GIR_Coverage, 4807, |
| 14360 | GIR_EraseRootFromParent_Done, |
| 14361 | // Label 925: @35643 |
| 14362 | GIM_Reject, |
| 14363 | // Label 910: @35644 |
| 14364 | GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(36406), |
| 14365 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 14366 | GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(35691), // Rule ID 266 // |
| 14367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dss), |
| 14369 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 14371 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14372 | // MIs[1] Operand 1 |
| 14373 | // No operand predicates |
| 14374 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14375 | // (intrinsic_void 9533:{ *:[iPTR] }, (imm:{ *:[i32] }):$STRM) => (DSS (imm:{ *:[i32] }):$STRM) |
| 14376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSS), |
| 14377 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14378 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14379 | GIR_RootConstrainSelectedInstOperands, |
| 14380 | // GIR_Coverage, 266, |
| 14381 | GIR_EraseRootFromParent_Done, |
| 14382 | // Label 927: @35691 |
| 14383 | GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(35717), // Rule ID 190 // |
| 14384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 14385 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsb0), |
| 14386 | // MIs[0] FM |
| 14387 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 14388 | // (intrinsic_void 9995:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM) => (MTFSB0 (timm:{ *:[i32] }):$FM) |
| 14389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSB0), |
| 14390 | GIR_RootToRootCopy, /*OpIdx*/1, // FM |
| 14391 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0, |
| 14392 | GIR_RootConstrainSelectedInstOperands, |
| 14393 | // GIR_Coverage, 190, |
| 14394 | GIR_EraseRootFromParent_Done, |
| 14395 | // Label 928: @35717 |
| 14396 | GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(35743), // Rule ID 191 // |
| 14397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 14398 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsb1), |
| 14399 | // MIs[0] FM |
| 14400 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 14401 | // (intrinsic_void 9996:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM) => (MTFSB1 (timm:{ *:[i32] }):$FM) |
| 14402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSB1), |
| 14403 | GIR_RootToRootCopy, /*OpIdx*/1, // FM |
| 14404 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0, |
| 14405 | GIR_RootConstrainSelectedInstOperands, |
| 14406 | // GIR_Coverage, 191, |
| 14407 | GIR_EraseRootFromParent_Done, |
| 14408 | // Label 929: @35743 |
| 14409 | GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(35770), // Rule ID 275 // |
| 14410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14411 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_mfvscr), |
| 14412 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 14413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 14414 | // (intrinsic_w_chain:{ *:[v8i16] } 9546:{ *:[iPTR] }) => (MFVSCR:{ *:[v8i16] }) |
| 14415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSCR), |
| 14416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 14417 | GIR_RootConstrainSelectedInstOperands, |
| 14418 | // GIR_Coverage, 275, |
| 14419 | GIR_EraseRootFromParent_Done, |
| 14420 | // Label 930: @35770 |
| 14421 | GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(35794), // Rule ID 1220 // |
| 14422 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_readflm), |
| 14423 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 14425 | // (intrinsic_w_chain:{ *:[f64] } 10010:{ *:[iPTR] }) => (MFFS:{ *:[f64] }) |
| 14426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFFS), |
| 14427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14428 | GIR_RootConstrainSelectedInstOperands, |
| 14429 | // GIR_Coverage, 1220, |
| 14430 | GIR_EraseRootFromParent_Done, |
| 14431 | // Label 931: @35794 |
| 14432 | GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(35822), // Rule ID 1221 // |
| 14433 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mffsl), |
| 14434 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 14436 | // (intrinsic_w_chain:{ *:[f64] } 9925:{ *:[iPTR] }) => (MFFSL:{ *:[f64] }) |
| 14437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFFSL), |
| 14438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14439 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14440 | GIR_RootConstrainSelectedInstOperands, |
| 14441 | // GIR_Coverage, 1221, |
| 14442 | GIR_EraseRootFromParent_Done, |
| 14443 | // Label 932: @35822 |
| 14444 | GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(35886), // Rule ID 1557 // |
| 14445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 14446 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_darn32), |
| 14447 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14449 | // (intrinsic_w_chain:{ *:[i32] } 9855:{ *:[iPTR] }) => (EXTRACT_SUBREG:{ *:[i32] } (DARN:{ *:[i64] } 0:{ *:[i32] }), sub_32:{ *:[i32] }) |
| 14450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 14451 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::DARN), |
| 14452 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14453 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 14454 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14455 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 14458 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 14459 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 14460 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 14461 | // GIR_Coverage, 1557, |
| 14462 | GIR_EraseRootFromParent_Done, |
| 14463 | // Label 933: @35886 |
| 14464 | GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(35920), // Rule ID 1558 // |
| 14465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 14466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_darn), |
| 14467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14469 | // (intrinsic_w_chain:{ *:[i64] } 9854:{ *:[iPTR] }) => (DARN:{ *:[i64] } 1:{ *:[i32] }) |
| 14470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DARN), |
| 14471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 14472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 14473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14474 | GIR_RootConstrainSelectedInstOperands, |
| 14475 | // GIR_Coverage, 1558, |
| 14476 | GIR_EraseRootFromParent_Done, |
| 14477 | // Label 934: @35920 |
| 14478 | GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(35954), // Rule ID 1559 // |
| 14479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 14480 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_darnraw), |
| 14481 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14483 | // (intrinsic_w_chain:{ *:[i64] } 9856:{ *:[iPTR] }) => (DARN:{ *:[i64] } 2:{ *:[i32] }) |
| 14484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DARN), |
| 14485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 14486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 14487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14488 | GIR_RootConstrainSelectedInstOperands, |
| 14489 | // GIR_Coverage, 1559, |
| 14490 | GIR_EraseRootFromParent_Done, |
| 14491 | // Label 935: @35954 |
| 14492 | GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(35985), // Rule ID 2871 // |
| 14493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14494 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_tcheck), |
| 14495 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 14497 | // (intrinsic_w_chain:{ *:[i32] } 10040:{ *:[iPTR] }) => (TCHECK_RET:{ *:[i32] }) |
| 14498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::TCHECK_RET), |
| 14499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out] |
| 14500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14501 | GIR_RootConstrainSelectedInstOperands, |
| 14502 | // GIR_Coverage, 2871, |
| 14503 | GIR_EraseRootFromParent_Done, |
| 14504 | // Label 936: @35985 |
| 14505 | GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(36026), // Rule ID 2875 // |
| 14506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14507 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_texasr), |
| 14508 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14510 | // (intrinsic_w_chain:{ *:[i64] } 9905:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 130:{ *:[i32] }) |
| 14511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8), |
| 14512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14513 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(130), |
| 14514 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14515 | GIR_RootConstrainSelectedInstOperands, |
| 14516 | // GIR_Coverage, 2875, |
| 14517 | GIR_EraseRootFromParent_Done, |
| 14518 | // Label 937: @36026 |
| 14519 | GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(36067), // Rule ID 2876 // |
| 14520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14521 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_texasru), |
| 14522 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14524 | // (intrinsic_w_chain:{ *:[i64] } 9906:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 131:{ *:[i32] }) |
| 14525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8), |
| 14526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14527 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(131), |
| 14528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14529 | GIR_RootConstrainSelectedInstOperands, |
| 14530 | // GIR_Coverage, 2876, |
| 14531 | GIR_EraseRootFromParent_Done, |
| 14532 | // Label 938: @36067 |
| 14533 | GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(36108), // Rule ID 2877 // |
| 14534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14535 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_tfhar), |
| 14536 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14538 | // (intrinsic_w_chain:{ *:[i64] } 9907:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 128:{ *:[i32] }) |
| 14539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8), |
| 14540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14541 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128), |
| 14542 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14543 | GIR_RootConstrainSelectedInstOperands, |
| 14544 | // GIR_Coverage, 2877, |
| 14545 | GIR_EraseRootFromParent_Done, |
| 14546 | // Label 939: @36108 |
| 14547 | GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(36149), // Rule ID 2878 // |
| 14548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14549 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_get_tfiar), |
| 14550 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14552 | // (intrinsic_w_chain:{ *:[i64] } 9908:{ *:[iPTR] }) => (MFSPR8:{ *:[i64] } 129:{ *:[i32] }) |
| 14553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8), |
| 14554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14555 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(129), |
| 14556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14557 | GIR_RootConstrainSelectedInstOperands, |
| 14558 | // GIR_Coverage, 2878, |
| 14559 | GIR_EraseRootFromParent_Done, |
| 14560 | // Label 940: @36149 |
| 14561 | GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(36180), // Rule ID 4851 // |
| 14562 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtmsr), |
| 14563 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14564 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 14565 | // (intrinsic_void 9999:{ *:[iPTR] }, gprc:{ *:[i32] }:$RS) => (MTMSR ?:{ *:[i32] }:$RS, 0:{ *:[i32] }) |
| 14566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTMSR), |
| 14567 | GIR_RootToRootCopy, /*OpIdx*/1, // RS |
| 14568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14570 | GIR_RootConstrainSelectedInstOperands, |
| 14571 | // GIR_Coverage, 4851, |
| 14572 | GIR_EraseRootFromParent_Done, |
| 14573 | // Label 941: @36180 |
| 14574 | GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(36207), // Rule ID 186 // |
| 14575 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::set_loop_iterations), |
| 14576 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14577 | // (intrinsic_void 313:{ *:[iPTR] }, i32:{ *:[i32] }:$RST) => (MTCTRloop:{ *:[i32] } i32:{ *:[i32] }:$RST) |
| 14578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTCTRloop), |
| 14579 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 14580 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CTR*/0, |
| 14581 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14582 | GIR_RootConstrainSelectedInstOperands, |
| 14583 | // GIR_Coverage, 186, |
| 14584 | GIR_EraseRootFromParent_Done, |
| 14585 | // Label 942: @36207 |
| 14586 | GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(36230), // Rule ID 276 // |
| 14587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14588 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_mtvscr), |
| 14589 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14590 | // (intrinsic_void 9547:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VB) => (MTVSCR v4i32:{ *:[v4i32] }:$VB) |
| 14591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTVSCR), |
| 14592 | GIR_RootToRootCopy, /*OpIdx*/1, // VB |
| 14593 | GIR_RootConstrainSelectedInstOperands, |
| 14594 | // GIR_Coverage, 276, |
| 14595 | GIR_EraseRootFromParent_Done, |
| 14596 | // Label 943: @36230 |
| 14597 | GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(36257), // Rule ID 630 // |
| 14598 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::set_loop_iterations), |
| 14599 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14600 | // (intrinsic_void 313:{ *:[iPTR] }, i64:{ *:[i64] }:$RST) => (MTCTR8loop:{ *:[i64] } i64:{ *:[i64] }:$RST) |
| 14601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTCTR8loop), |
| 14602 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 14603 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CTR8*/0, |
| 14604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14605 | GIR_RootConstrainSelectedInstOperands, |
| 14606 | // GIR_Coverage, 630, |
| 14607 | GIR_EraseRootFromParent_Done, |
| 14608 | // Label 944: @36257 |
| 14609 | GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(36294), // Rule ID 2879 // |
| 14610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14611 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_texasr), |
| 14612 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14613 | // (intrinsic_void 10016:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 130:{ *:[i32] }, ?:{ *:[i64] }:$V) |
| 14614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8), |
| 14615 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(130), |
| 14616 | GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 14617 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14618 | GIR_RootConstrainSelectedInstOperands, |
| 14619 | // GIR_Coverage, 2879, |
| 14620 | GIR_EraseRootFromParent_Done, |
| 14621 | // Label 945: @36294 |
| 14622 | GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(36331), // Rule ID 2880 // |
| 14623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14624 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_texasru), |
| 14625 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14626 | // (intrinsic_void 10017:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 131:{ *:[i32] }, ?:{ *:[i64] }:$V) |
| 14627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8), |
| 14628 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(131), |
| 14629 | GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 14630 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14631 | GIR_RootConstrainSelectedInstOperands, |
| 14632 | // GIR_Coverage, 2880, |
| 14633 | GIR_EraseRootFromParent_Done, |
| 14634 | // Label 946: @36331 |
| 14635 | GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(36368), // Rule ID 2881 // |
| 14636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14637 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_tfhar), |
| 14638 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14639 | // (intrinsic_void 10018:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 128:{ *:[i32] }, ?:{ *:[i64] }:$V) |
| 14640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8), |
| 14641 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128), |
| 14642 | GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 14643 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14644 | GIR_RootConstrainSelectedInstOperands, |
| 14645 | // GIR_Coverage, 2881, |
| 14646 | GIR_EraseRootFromParent_Done, |
| 14647 | // Label 947: @36368 |
| 14648 | GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(36405), // Rule ID 2882 // |
| 14649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasHTM), |
| 14650 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_set_tfiar), |
| 14651 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14652 | // (intrinsic_void 10019:{ *:[iPTR] }, i64:{ *:[i64] }:$V) => (MTSPR8 129:{ *:[i32] }, ?:{ *:[i64] }:$V) |
| 14653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8), |
| 14654 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(129), |
| 14655 | GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 14656 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14657 | GIR_RootConstrainSelectedInstOperands, |
| 14658 | // GIR_Coverage, 2882, |
| 14659 | GIR_EraseRootFromParent_Done, |
| 14660 | // Label 948: @36405 |
| 14661 | GIM_Reject, |
| 14662 | // Label 926: @36406 |
| 14663 | GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(36851), |
| 14664 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 14665 | GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(36445), // Rule ID 1161 // |
| 14666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 14667 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsfi), |
| 14668 | // MIs[0] BF |
| 14669 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 14670 | // MIs[0] U |
| 14671 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 14672 | // (intrinsic_void 9998:{ *:[iPTR] }, (timm:{ *:[i32] }):$BF, (timm:{ *:[i32] }):$U) => (MTFSFIb (timm:{ *:[i32] }):$BF, (timm:{ *:[i32] }):$U) |
| 14673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSFIb), |
| 14674 | GIR_RootToRootCopy, /*OpIdx*/1, // BF |
| 14675 | GIR_RootToRootCopy, /*OpIdx*/2, // U |
| 14676 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0, |
| 14677 | GIR_RootConstrainSelectedInstOperands, |
| 14678 | // GIR_Coverage, 1161, |
| 14679 | GIR_EraseRootFromParent_Done, |
| 14680 | // Label 950: @36445 |
| 14681 | GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(36490), // Rule ID 12 // |
| 14682 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setrnd), |
| 14683 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14684 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 14686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14688 | // MIs[1] Operand 1 |
| 14689 | // No operand predicates |
| 14690 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14691 | // (intrinsic_w_chain:{ *:[f64] } 10022:{ *:[iPTR] }, (imm:{ *:[i32] }):$RND) => (SETRNDi:{ *:[f64] } (imm:{ *:[i32] }):$RND) |
| 14692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETRNDi), |
| 14693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 14694 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // RND |
| 14695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14696 | GIR_RootConstrainSelectedInstOperands, |
| 14697 | // GIR_Coverage, 12, |
| 14698 | GIR_EraseRootFromParent_Done, |
| 14699 | // Label 951: @36490 |
| 14700 | GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(36535), // Rule ID 187 // |
| 14701 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::loop_decrement), |
| 14702 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 14703 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 14705 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14706 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14707 | // MIs[1] Operand 1 |
| 14708 | // No operand predicates |
| 14709 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14710 | // (intrinsic_w_chain:{ *:[i1] } 215:{ *:[iPTR] }, (imm:{ *:[i32] }):$stride) => (DecreaseCTRloop:{ *:[i1] }:{ *:[i32] } (imm:{ *:[i32] }):$stride) |
| 14711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DecreaseCTRloop), |
| 14712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rT] |
| 14713 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // stride |
| 14714 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14715 | GIR_RootConstrainSelectedInstOperands, |
| 14716 | // GIR_Coverage, 187, |
| 14717 | GIR_EraseRootFromParent_Done, |
| 14718 | // Label 952: @36535 |
| 14719 | GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(36580), // Rule ID 631 // |
| 14720 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::loop_decrement), |
| 14721 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 14722 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 14723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 14724 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14725 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14726 | // MIs[1] Operand 1 |
| 14727 | // No operand predicates |
| 14728 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14729 | // (intrinsic_w_chain:{ *:[i1] } 215:{ *:[iPTR] }, (imm:{ *:[i64] }):$stride) => (DecreaseCTR8loop:{ *:[i1] }:{ *:[i64] } (imm:{ *:[i64] }):$stride) |
| 14730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DecreaseCTR8loop), |
| 14731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rT] |
| 14732 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // stride |
| 14733 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14734 | GIR_RootConstrainSelectedInstOperands, |
| 14735 | // GIR_Coverage, 631, |
| 14736 | GIR_EraseRootFromParent_Done, |
| 14737 | // Label 953: @36580 |
| 14738 | GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(36613), // Rule ID 1162 // |
| 14739 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fixed_addr_ld), |
| 14740 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 14742 | // MIs[0] imm |
| 14743 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 14744 | // (intrinsic_w_chain:{ *:[i32] } 9890:{ *:[iPTR] }, (timm:{ *:[i32] }):$imm) => (PPCLdFixedAddr:{ *:[i32] } (timm:{ *:[i32] }):$imm) |
| 14745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::PPCLdFixedAddr), |
| 14746 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rT] |
| 14747 | GIR_RootToRootCopy, /*OpIdx*/2, // imm |
| 14748 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14749 | GIR_RootConstrainSelectedInstOperands, |
| 14750 | // GIR_Coverage, 1162, |
| 14751 | GIR_EraseRootFromParent_Done, |
| 14752 | // Label 954: @36613 |
| 14753 | GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(36646), // Rule ID 1562 // |
| 14754 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfspr), |
| 14755 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14757 | // MIs[0] SPR |
| 14758 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 14759 | // (intrinsic_w_chain:{ *:[i64] } 9927:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR) => (MFSPR8:{ *:[i64] } ?:{ *:[i32] }:$SPR) |
| 14760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR8), |
| 14761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14762 | GIR_RootToRootCopy, /*OpIdx*/2, // SPR |
| 14763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14764 | GIR_RootConstrainSelectedInstOperands, |
| 14765 | // GIR_Coverage, 1562, |
| 14766 | GIR_EraseRootFromParent_Done, |
| 14767 | // Label 955: @36646 |
| 14768 | GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(36679), // Rule ID 4849 // |
| 14769 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_mfspr), |
| 14770 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 14772 | // MIs[0] SPR |
| 14773 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 14774 | // (intrinsic_w_chain:{ *:[i32] } 9927:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR) => (MFSPR:{ *:[i32] } ?:{ *:[i32] }:$SPR) |
| 14775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFSPR), |
| 14776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 14777 | GIR_RootToRootCopy, /*OpIdx*/2, // SPR |
| 14778 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14779 | GIR_RootConstrainSelectedInstOperands, |
| 14780 | // GIR_Coverage, 4849, |
| 14781 | GIR_EraseRootFromParent_Done, |
| 14782 | // Label 956: @36679 |
| 14783 | GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(36712), // Rule ID 1563 // |
| 14784 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtspr), |
| 14785 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 14786 | // MIs[0] SPR |
| 14787 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 14788 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 14789 | // (intrinsic_void 10000:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR, g8rc:{ *:[i64] }:$RT) => (MTSPR8 ?:{ *:[i32] }:$SPR, ?:{ *:[i64] }:$RT) |
| 14790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR8), |
| 14791 | GIR_RootToRootCopy, /*OpIdx*/1, // SPR |
| 14792 | GIR_RootToRootCopy, /*OpIdx*/2, // RT |
| 14793 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14794 | GIR_RootConstrainSelectedInstOperands, |
| 14795 | // GIR_Coverage, 1563, |
| 14796 | GIR_EraseRootFromParent_Done, |
| 14797 | // Label 957: @36712 |
| 14798 | GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(36745), // Rule ID 4850 // |
| 14799 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtspr), |
| 14800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14801 | // MIs[0] SPR |
| 14802 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 14803 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 14804 | // (intrinsic_void 10000:{ *:[iPTR] }, (timm:{ *:[i32] }):$SPR, gprc:{ *:[i32] }:$RT) => (MTSPR ?:{ *:[i32] }:$SPR, ?:{ *:[i32] }:$RT) |
| 14805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTSPR), |
| 14806 | GIR_RootToRootCopy, /*OpIdx*/1, // SPR |
| 14807 | GIR_RootToRootCopy, /*OpIdx*/2, // RT |
| 14808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14809 | GIR_RootConstrainSelectedInstOperands, |
| 14810 | // GIR_Coverage, 4850, |
| 14811 | GIR_EraseRootFromParent_Done, |
| 14812 | // Label 958: @36745 |
| 14813 | GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(36776), // Rule ID 192 // |
| 14814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 14815 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_mtfsf), |
| 14816 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 14817 | // MIs[0] FM |
| 14818 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 14819 | // (intrinsic_void 9997:{ *:[iPTR] }, (timm:{ *:[i32] }):$FM, f64:{ *:[f64] }:$RT) => (MTFSFb (timm:{ *:[i32] }):$FM, f64:{ *:[f64] }:$RT) |
| 14820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MTFSFb), |
| 14821 | GIR_RootToRootCopy, /*OpIdx*/1, // FM |
| 14822 | GIR_RootToRootCopy, /*OpIdx*/2, // RT |
| 14823 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::RM*/0, |
| 14824 | GIR_RootConstrainSelectedInstOperands, |
| 14825 | // GIR_Coverage, 192, |
| 14826 | GIR_EraseRootFromParent_Done, |
| 14827 | // Label 959: @36776 |
| 14828 | GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(36813), // Rule ID 13 // |
| 14829 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setrnd), |
| 14830 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14831 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 14833 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 14834 | // (intrinsic_w_chain:{ *:[f64] } 10022:{ *:[iPTR] }, gprc:{ *:[i32] }:$in) => (SETRND:{ *:[f64] } gprc:{ *:[i32] }:$in) |
| 14835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETRND), |
| 14836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 14837 | GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 14838 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14839 | GIR_RootConstrainSelectedInstOperands, |
| 14840 | // GIR_Coverage, 13, |
| 14841 | GIR_EraseRootFromParent_Done, |
| 14842 | // Label 960: @36813 |
| 14843 | GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(36850), // Rule ID 14 // |
| 14844 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_setflm), |
| 14845 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14846 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 14847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 14848 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 14849 | // (intrinsic_w_chain:{ *:[f64] } 10021:{ *:[iPTR] }, f8rc:{ *:[f64] }:$FLM) => (SETFLM:{ *:[f64] } f8rc:{ *:[f64] }:$FLM) |
| 14850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SETFLM), |
| 14851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 14852 | GIR_RootToRootCopy, /*OpIdx*/2, // FLM |
| 14853 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14854 | GIR_RootConstrainSelectedInstOperands, |
| 14855 | // GIR_Coverage, 14, |
| 14856 | GIR_EraseRootFromParent_Done, |
| 14857 | // Label 961: @36850 |
| 14858 | GIM_Reject, |
| 14859 | // Label 949: @36851 |
| 14860 | GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(37778), |
| 14861 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 14862 | GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(36909), // Rule ID 267 // |
| 14863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14864 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dst), |
| 14865 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14866 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14867 | // MIs[0] RA |
| 14868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14869 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14870 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14871 | // MIs[1] Operand 1 |
| 14872 | // No operand predicates |
| 14873 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14874 | // (intrinsic_void 9535:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DST (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 14875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DST), |
| 14876 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14877 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 14878 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 14879 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14880 | GIR_RootConstrainSelectedInstOperands, |
| 14881 | // GIR_Coverage, 267, |
| 14882 | GIR_EraseRootFromParent_Done, |
| 14883 | // Label 963: @36909 |
| 14884 | GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(36959), // Rule ID 268 // |
| 14885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14886 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstt), |
| 14887 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14888 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14889 | // MIs[0] RA |
| 14890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14891 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14892 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14893 | // MIs[1] Operand 1 |
| 14894 | // No operand predicates |
| 14895 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14896 | // (intrinsic_void 9538:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTT (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 14897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTT), |
| 14898 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14899 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 14900 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 14901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14902 | GIR_RootConstrainSelectedInstOperands, |
| 14903 | // GIR_Coverage, 268, |
| 14904 | GIR_EraseRootFromParent_Done, |
| 14905 | // Label 964: @36959 |
| 14906 | GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(37009), // Rule ID 269 // |
| 14907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14908 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstst), |
| 14909 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14910 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14911 | // MIs[0] RA |
| 14912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14913 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14914 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14915 | // MIs[1] Operand 1 |
| 14916 | // No operand predicates |
| 14917 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14918 | // (intrinsic_void 9536:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTST (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 14919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTST), |
| 14920 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14921 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 14922 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 14923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14924 | GIR_RootConstrainSelectedInstOperands, |
| 14925 | // GIR_Coverage, 269, |
| 14926 | GIR_EraseRootFromParent_Done, |
| 14927 | // Label 965: @37009 |
| 14928 | GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(37059), // Rule ID 270 // |
| 14929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14930 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dststt), |
| 14931 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14932 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14933 | // MIs[0] RA |
| 14934 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14935 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14936 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14937 | // MIs[1] Operand 1 |
| 14938 | // No operand predicates |
| 14939 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14940 | // (intrinsic_void 9537:{ *:[iPTR] }, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTSTT (imm:{ *:[i32] }):$STRM, i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 14941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTSTT), |
| 14942 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14943 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 14944 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 14945 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14946 | GIR_RootConstrainSelectedInstOperands, |
| 14947 | // GIR_Coverage, 270, |
| 14948 | GIR_EraseRootFromParent_Done, |
| 14949 | // Label 966: @37059 |
| 14950 | GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(37109), // Rule ID 271 // |
| 14951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14952 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dst), |
| 14953 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14954 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14955 | // MIs[0] RA |
| 14956 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 14957 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14958 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14959 | // MIs[1] Operand 1 |
| 14960 | // No operand predicates |
| 14961 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14962 | // (intrinsic_void 9535:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DST64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB) |
| 14963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DST64), |
| 14964 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14965 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 14966 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 14967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14968 | GIR_RootConstrainSelectedInstOperands, |
| 14969 | // GIR_Coverage, 271, |
| 14970 | GIR_EraseRootFromParent_Done, |
| 14971 | // Label 967: @37109 |
| 14972 | GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(37159), // Rule ID 272 // |
| 14973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14974 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstt), |
| 14975 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14976 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14977 | // MIs[0] RA |
| 14978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 14979 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 14980 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 14981 | // MIs[1] Operand 1 |
| 14982 | // No operand predicates |
| 14983 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 14984 | // (intrinsic_void 9538:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTT64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB) |
| 14985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTT64), |
| 14986 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 14987 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 14988 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 14989 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 14990 | GIR_RootConstrainSelectedInstOperands, |
| 14991 | // GIR_Coverage, 272, |
| 14992 | GIR_EraseRootFromParent_Done, |
| 14993 | // Label 968: @37159 |
| 14994 | GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(37209), // Rule ID 273 // |
| 14995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 14996 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dstst), |
| 14997 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14998 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 14999 | // MIs[0] RA |
| 15000 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15001 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15002 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15003 | // MIs[1] Operand 1 |
| 15004 | // No operand predicates |
| 15005 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15006 | // (intrinsic_void 9536:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTST64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB) |
| 15007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTST64), |
| 15008 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 15009 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 15010 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 15011 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 15012 | GIR_RootConstrainSelectedInstOperands, |
| 15013 | // GIR_Coverage, 273, |
| 15014 | GIR_EraseRootFromParent_Done, |
| 15015 | // Label 969: @37209 |
| 15016 | GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(37259), // Rule ID 274 // |
| 15017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15018 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::ppc_altivec_dststt), |
| 15019 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15020 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 15021 | // MIs[0] RA |
| 15022 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15023 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 15024 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 15025 | // MIs[1] Operand 1 |
| 15026 | // No operand predicates |
| 15027 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15028 | // (intrinsic_void 9537:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB, (imm:{ *:[i32] }):$STRM) => (DSTSTT64 (imm:{ *:[i32] }):$STRM, i64:{ *:[i64] }:$RA, i32:{ *:[i32] }:$RB) |
| 15029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::DSTSTT64), |
| 15030 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // STRM |
| 15031 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 15032 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 15033 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 15034 | GIR_RootConstrainSelectedInstOperands, |
| 15035 | // GIR_Coverage, 274, |
| 15036 | GIR_EraseRootFromParent_Done, |
| 15037 | // Label 970: @37259 |
| 15038 | GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(37296), // Rule ID 377 // |
| 15039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15040 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsumsws), |
| 15041 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15042 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15043 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15045 | // (intrinsic_w_chain:{ *:[v4i32] } 9817:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUMSWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUMSWS), |
| 15047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15048 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15049 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15050 | GIR_RootConstrainSelectedInstOperands, |
| 15051 | // GIR_Coverage, 377, |
| 15052 | GIR_EraseRootFromParent_Done, |
| 15053 | // Label 971: @37296 |
| 15054 | GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(37333), // Rule ID 378 // |
| 15055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15056 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum2sws), |
| 15057 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15061 | // (intrinsic_w_chain:{ *:[v4i32] } 9813:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM2SWS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM2SWS), |
| 15063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15064 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15065 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15066 | GIR_RootConstrainSelectedInstOperands, |
| 15067 | // GIR_Coverage, 378, |
| 15068 | GIR_EraseRootFromParent_Done, |
| 15069 | // Label 972: @37333 |
| 15070 | GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(37370), // Rule ID 379 // |
| 15071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15072 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum4sbs), |
| 15073 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15074 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15075 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15077 | // (intrinsic_w_chain:{ *:[v4i32] } 9814:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM4SBS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM4SBS), |
| 15079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15080 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15081 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15082 | GIR_RootConstrainSelectedInstOperands, |
| 15083 | // GIR_Coverage, 379, |
| 15084 | GIR_EraseRootFromParent_Done, |
| 15085 | // Label 973: @37370 |
| 15086 | GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(37407), // Rule ID 380 // |
| 15087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15088 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum4shs), |
| 15089 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15091 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15093 | // (intrinsic_w_chain:{ *:[v4i32] } 9815:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM4SHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM4SHS), |
| 15095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15096 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15097 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15098 | GIR_RootConstrainSelectedInstOperands, |
| 15099 | // GIR_Coverage, 380, |
| 15100 | GIR_EraseRootFromParent_Done, |
| 15101 | // Label 974: @37407 |
| 15102 | GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(37444), // Rule ID 381 // |
| 15103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15104 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vsum4ubs), |
| 15105 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15106 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15107 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15109 | // (intrinsic_w_chain:{ *:[v4i32] } 9816:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VSUM4UBS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSUM4UBS), |
| 15111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15112 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15113 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15114 | GIR_RootConstrainSelectedInstOperands, |
| 15115 | // GIR_Coverage, 381, |
| 15116 | GIR_EraseRootFromParent_Done, |
| 15117 | // Label 975: @37444 |
| 15118 | GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(37481), // Rule ID 408 // |
| 15119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15120 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkshss), |
| 15121 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15122 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15123 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15125 | // (intrinsic_w_chain:{ *:[v16i8] } 9751:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPKSHSS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 15126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSHSS), |
| 15127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15128 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15129 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15130 | GIR_RootConstrainSelectedInstOperands, |
| 15131 | // GIR_Coverage, 408, |
| 15132 | GIR_EraseRootFromParent_Done, |
| 15133 | // Label 976: @37481 |
| 15134 | GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(37518), // Rule ID 409 // |
| 15135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15136 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkshus), |
| 15137 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15138 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15139 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15141 | // (intrinsic_w_chain:{ *:[v16i8] } 9752:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPKSHUS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 15142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSHUS), |
| 15143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15144 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15145 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15146 | GIR_RootConstrainSelectedInstOperands, |
| 15147 | // GIR_Coverage, 409, |
| 15148 | GIR_EraseRootFromParent_Done, |
| 15149 | // Label 977: @37518 |
| 15150 | GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(37555), // Rule ID 410 // |
| 15151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15152 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkswss), |
| 15153 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15154 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15155 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15157 | // (intrinsic_w_chain:{ *:[v8i16] } 9753:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKSWSS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSWSS), |
| 15159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15160 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15161 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15162 | GIR_RootConstrainSelectedInstOperands, |
| 15163 | // GIR_Coverage, 410, |
| 15164 | GIR_EraseRootFromParent_Done, |
| 15165 | // Label 978: @37555 |
| 15166 | GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(37592), // Rule ID 411 // |
| 15167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15168 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkswus), |
| 15169 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15170 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15171 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15173 | // (intrinsic_w_chain:{ *:[v8i16] } 9754:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKSWUS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSWUS), |
| 15175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15176 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15177 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15178 | GIR_RootConstrainSelectedInstOperands, |
| 15179 | // GIR_Coverage, 411, |
| 15180 | GIR_EraseRootFromParent_Done, |
| 15181 | // Label 979: @37592 |
| 15182 | GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(37629), // Rule ID 412 // |
| 15183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15184 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkuhus), |
| 15185 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15187 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15189 | // (intrinsic_w_chain:{ *:[v16i8] } 9756:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) => (VPKUHUS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$VA, v8i16:{ *:[v8i16] }:$VB) |
| 15190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKUHUS), |
| 15191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15192 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15193 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15194 | GIR_RootConstrainSelectedInstOperands, |
| 15195 | // GIR_Coverage, 412, |
| 15196 | GIR_EraseRootFromParent_Done, |
| 15197 | // Label 980: @37629 |
| 15198 | GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(37666), // Rule ID 413 // |
| 15199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15200 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkuwus), |
| 15201 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15202 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15203 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 15204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15205 | // (intrinsic_w_chain:{ *:[v8i16] } 9757:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VPKUWUS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 15206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKUWUS), |
| 15207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15208 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15209 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15210 | GIR_RootConstrainSelectedInstOperands, |
| 15211 | // GIR_Coverage, 413, |
| 15212 | GIR_EraseRootFromParent_Done, |
| 15213 | // Label 981: @37666 |
| 15214 | GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(37703), // Rule ID 497 // |
| 15215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 15216 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpksdss), |
| 15217 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15218 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15219 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 15220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15221 | // (intrinsic_w_chain:{ *:[v4i32] } 9749:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPKSDSS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 15222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSDSS), |
| 15223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15224 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15225 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15226 | GIR_RootConstrainSelectedInstOperands, |
| 15227 | // GIR_Coverage, 497, |
| 15228 | GIR_EraseRootFromParent_Done, |
| 15229 | // Label 982: @37703 |
| 15230 | GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(37740), // Rule ID 498 // |
| 15231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 15232 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpksdus), |
| 15233 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15235 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 15236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15237 | // (intrinsic_w_chain:{ *:[v4i32] } 9750:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPKSDUS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 15238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKSDUS), |
| 15239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15240 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15241 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15242 | GIR_RootConstrainSelectedInstOperands, |
| 15243 | // GIR_Coverage, 498, |
| 15244 | GIR_EraseRootFromParent_Done, |
| 15245 | // Label 983: @37740 |
| 15246 | GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(37777), // Rule ID 499 // |
| 15247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 15248 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vpkudus), |
| 15249 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15250 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15251 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 15252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15253 | // (intrinsic_w_chain:{ *:[v4i32] } 9755:{ *:[iPTR] }, v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VPKUDUS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 15254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VPKUDUS), |
| 15255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15256 | GIR_RootToRootCopy, /*OpIdx*/2, // VA |
| 15257 | GIR_RootToRootCopy, /*OpIdx*/3, // VB |
| 15258 | GIR_RootConstrainSelectedInstOperands, |
| 15259 | // GIR_Coverage, 499, |
| 15260 | GIR_EraseRootFromParent_Done, |
| 15261 | // Label 984: @37777 |
| 15262 | GIM_Reject, |
| 15263 | // Label 962: @37778 |
| 15264 | GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(37994), |
| 15265 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 15266 | GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(37825), // Rule ID 756 // |
| 15267 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_addex), |
| 15268 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 15269 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 15270 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 15271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15272 | // MIs[0] CY |
| 15273 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 15274 | // (intrinsic_w_chain:{ *:[i64] } 9518:{ *:[iPTR] }, i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB, (timm:{ *:[i32] }):$CY) => (ADDEX8:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB, (timm:{ *:[i32] }):$CY) |
| 15275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ADDEX8), |
| 15276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 15277 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 15278 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 15279 | GIR_RootToRootCopy, /*OpIdx*/4, // CY |
| 15280 | GIR_RootConstrainSelectedInstOperands, |
| 15281 | // GIR_Coverage, 756, |
| 15282 | GIR_EraseRootFromParent_Done, |
| 15283 | // Label 986: @37825 |
| 15284 | GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(37867), // Rule ID 291 // |
| 15285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15286 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmhaddshs), |
| 15287 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15288 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15289 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15290 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 15291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15292 | // (intrinsic_w_chain:{ *:[v8i16] } 9704:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMHADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) |
| 15293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMHADDSHS), |
| 15294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 15295 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 15296 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 15297 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 15298 | GIR_RootConstrainSelectedInstOperands, |
| 15299 | // GIR_Coverage, 291, |
| 15300 | GIR_EraseRootFromParent_Done, |
| 15301 | // Label 987: @37867 |
| 15302 | GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(37909), // Rule ID 292 // |
| 15303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15304 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmhraddshs), |
| 15305 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15306 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15307 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15308 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 15309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15310 | // (intrinsic_w_chain:{ *:[v8i16] } 9705:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) => (VMHRADDSHS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v8i16:{ *:[v8i16] }:$RC) |
| 15311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMHRADDSHS), |
| 15312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 15313 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 15314 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 15315 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 15316 | GIR_RootConstrainSelectedInstOperands, |
| 15317 | // GIR_Coverage, 292, |
| 15318 | GIR_EraseRootFromParent_Done, |
| 15319 | // Label 988: @37909 |
| 15320 | GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(37951), // Rule ID 350 // |
| 15321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15322 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumshs), |
| 15323 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15325 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15326 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 15327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15328 | // (intrinsic_w_chain:{ *:[v4i32] } 9719:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMSHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 15329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMSHS), |
| 15330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 15331 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 15332 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 15333 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 15334 | GIR_RootConstrainSelectedInstOperands, |
| 15335 | // GIR_Coverage, 350, |
| 15336 | GIR_EraseRootFromParent_Done, |
| 15337 | // Label 989: @37951 |
| 15338 | GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(37993), // Rule ID 351 // |
| 15339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15340 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_altivec_vmsumuhs), |
| 15341 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15343 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 15344 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 15345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15346 | // (intrinsic_w_chain:{ *:[v4i32] } 9723:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) => (VMSUMUHS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$RA, v8i16:{ *:[v8i16] }:$RB, v4i32:{ *:[v4i32] }:$RC) |
| 15347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMSUMUHS), |
| 15348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 15349 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 15350 | GIR_RootToRootCopy, /*OpIdx*/3, // RB |
| 15351 | GIR_RootToRootCopy, /*OpIdx*/4, // RC |
| 15352 | GIR_RootConstrainSelectedInstOperands, |
| 15353 | // GIR_Coverage, 351, |
| 15354 | GIR_EraseRootFromParent_Done, |
| 15355 | // Label 990: @37993 |
| 15356 | GIM_Reject, |
| 15357 | // Label 985: @37994 |
| 15358 | GIM_Reject, |
| 15359 | // Label 21: @37995 |
| 15360 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 993*/ GIMT_Encode4(38180), |
| 15361 | /*GILLT_s32*//*Label 991*/ GIMT_Encode4(38014), |
| 15362 | /*GILLT_s64*//*Label 992*/ GIMT_Encode4(38097), |
| 15363 | // Label 991: @38014 |
| 15364 | GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(38096), |
| 15365 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 15367 | GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(38041), // Rule ID 2968 // |
| 15368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 15369 | // (anyext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SETBC:{ *:[i32] } ?:{ *:[i1] }:$in) |
| 15370 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC), |
| 15371 | GIR_RootConstrainSelectedInstOperands, |
| 15372 | // GIR_Coverage, 2968, |
| 15373 | GIR_Done, |
| 15374 | // Label 995: @38041 |
| 15375 | GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(38095), // Rule ID 3624 // |
| 15376 | // (anyext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } ?:{ *:[i1] }:$in, (LI:{ *:[i32] } 1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] })) |
| 15377 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15378 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 15379 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15380 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15381 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 15382 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15383 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15384 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15385 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 15386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4), |
| 15388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15389 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 15390 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15391 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15392 | GIR_RootConstrainSelectedInstOperands, |
| 15393 | // GIR_Coverage, 3624, |
| 15394 | GIR_EraseRootFromParent_Done, |
| 15395 | // Label 996: @38095 |
| 15396 | GIM_Reject, |
| 15397 | // Label 994: @38096 |
| 15398 | GIM_Reject, |
| 15399 | // Label 992: @38097 |
| 15400 | GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(38179), |
| 15401 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15403 | GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(38124), // Rule ID 2969 // |
| 15404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 15405 | // (anyext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SETBC8:{ *:[i64] } ?:{ *:[i1] }:$in) |
| 15406 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC8), |
| 15407 | GIR_RootConstrainSelectedInstOperands, |
| 15408 | // GIR_Coverage, 2969, |
| 15409 | GIR_Done, |
| 15410 | // Label 998: @38124 |
| 15411 | GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(38178), // Rule ID 3625 // |
| 15412 | // (anyext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } ?:{ *:[i1] }:$in, (LI8:{ *:[i64] } 1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] })) |
| 15413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 15414 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 15415 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15416 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15417 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 15418 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15421 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 15422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8), |
| 15424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15425 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 15426 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15427 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15428 | GIR_RootConstrainSelectedInstOperands, |
| 15429 | // GIR_Coverage, 3625, |
| 15430 | GIR_EraseRootFromParent_Done, |
| 15431 | // Label 999: @38178 |
| 15432 | GIM_Reject, |
| 15433 | // Label 997: @38179 |
| 15434 | GIM_Reject, |
| 15435 | // Label 993: @38180 |
| 15436 | GIM_Reject, |
| 15437 | // Label 22: @38181 |
| 15438 | GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(38366), |
| 15439 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 15440 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1003*/ GIMT_Encode4(38300), |
| 15441 | /*GILLT_s32*//*Label 1001*/ GIMT_Encode4(38208), |
| 15442 | /*GILLT_s64*//*Label 1002*/ GIMT_Encode4(38254), |
| 15443 | // Label 1001: @38208 |
| 15444 | GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(38253), // Rule ID 1157 // |
| 15445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 15446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 15449 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 15450 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15451 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15452 | // (trunc:{ *:[i1] } (xor:{ *:[i32] } i32:{ *:[i32] }:$in, -1:{ *:[i32] })) => (ANDI_rec_1_EQ_BIT:{ *:[i1] }:{ *:[i32] } i32:{ *:[i32] }:$in) |
| 15453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_EQ_BIT), |
| 15454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15455 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in |
| 15456 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0, |
| 15457 | GIR_RootConstrainSelectedInstOperands, |
| 15458 | // GIR_Coverage, 1157, |
| 15459 | GIR_EraseRootFromParent_Done, |
| 15460 | // Label 1004: @38253 |
| 15461 | GIM_Reject, |
| 15462 | // Label 1002: @38254 |
| 15463 | GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(38299), // Rule ID 1159 // |
| 15464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 15465 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 15466 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 15467 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15468 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 15469 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 15470 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 15471 | // (trunc:{ *:[i1] } (xor:{ *:[i64] } i64:{ *:[i64] }:$in, -1:{ *:[i64] })) => (ANDI_rec_1_EQ_BIT8:{ *:[i1] }:{ *:[i32] } i64:{ *:[i64] }:$in) |
| 15472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_EQ_BIT8), |
| 15473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15474 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // in |
| 15475 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CR0*/0, |
| 15476 | GIR_RootConstrainSelectedInstOperands, |
| 15477 | // GIR_Coverage, 1159, |
| 15478 | GIR_EraseRootFromParent_Done, |
| 15479 | // Label 1005: @38299 |
| 15480 | GIM_Reject, |
| 15481 | // Label 1003: @38300 |
| 15482 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1008*/ GIMT_Encode4(38365), |
| 15483 | /*GILLT_s32*//*Label 1006*/ GIMT_Encode4(38319), |
| 15484 | /*GILLT_s64*//*Label 1007*/ GIMT_Encode4(38342), |
| 15485 | // Label 1006: @38319 |
| 15486 | GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(38341), // Rule ID 1158 // |
| 15487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 15488 | // (trunc:{ *:[i1] } i32:{ *:[i32] }:$in) => (ANDI_rec_1_GT_BIT:{ *:[i1] }:{ *:[i32] } i32:{ *:[i32] }:$in) |
| 15489 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_GT_BIT), |
| 15490 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CR0), GIMT_Encode2(RegState::Dead), |
| 15491 | GIR_RootConstrainSelectedInstOperands, |
| 15492 | // GIR_Coverage, 1158, |
| 15493 | GIR_Done, |
| 15494 | // Label 1009: @38341 |
| 15495 | GIM_Reject, |
| 15496 | // Label 1007: @38342 |
| 15497 | GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(38364), // Rule ID 1160 // |
| 15498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 15499 | // (trunc:{ *:[i1] } i64:{ *:[i64] }:$in) => (ANDI_rec_1_GT_BIT8:{ *:[i1] }:{ *:[i32] } i64:{ *:[i64] }:$in) |
| 15500 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::ANDI_rec_1_GT_BIT8), |
| 15501 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CR0), GIMT_Encode2(RegState::Dead), |
| 15502 | GIR_RootConstrainSelectedInstOperands, |
| 15503 | // GIR_Coverage, 1160, |
| 15504 | GIR_Done, |
| 15505 | // Label 1010: @38364 |
| 15506 | GIM_Reject, |
| 15507 | // Label 1008: @38365 |
| 15508 | GIM_Reject, |
| 15509 | // Label 1000: @38366 |
| 15510 | GIM_Reject, |
| 15511 | // Label 23: @38367 |
| 15512 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 1014*/ GIMT_Encode4(38518), |
| 15513 | /*GILLT_s1*//*Label 1011*/ GIMT_Encode4(38390), |
| 15514 | /*GILLT_s32*//*Label 1012*/ GIMT_Encode4(38470), |
| 15515 | /*GILLT_s64*//*Label 1013*/ GIMT_Encode4(38494), |
| 15516 | // Label 1011: @38390 |
| 15517 | GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(38469), |
| 15518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 15519 | GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(38422), // Rule ID 181 // |
| 15520 | // MIs[0] Operand 1 |
| 15521 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1), |
| 15522 | // 1:{ *:[i1] } => (CRSET:{ *:[i1] }) |
| 15523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRSET), |
| 15524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 15525 | GIR_RootConstrainSelectedInstOperands, |
| 15526 | // GIR_Coverage, 181, |
| 15527 | GIR_EraseRootFromParent_Done, |
| 15528 | // Label 1016: @38422 |
| 15529 | GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(38445), // Rule ID 182 // |
| 15530 | // MIs[0] Operand 1 |
| 15531 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0), |
| 15532 | // 0:{ *:[i1] } => (CRUNSET:{ *:[i1] }) |
| 15533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRUNSET), |
| 15534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 15535 | GIR_RootConstrainSelectedInstOperands, |
| 15536 | // GIR_Coverage, 182, |
| 15537 | GIR_EraseRootFromParent_Done, |
| 15538 | // Label 1017: @38445 |
| 15539 | GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(38468), // Rule ID 3619 // |
| 15540 | // MIs[0] Operand 1 |
| 15541 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(-1), |
| 15542 | // -1:{ *:[i1] } => (CRSET:{ *:[i1] }) |
| 15543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRSET), |
| 15544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 15545 | GIR_RootConstrainSelectedInstOperands, |
| 15546 | // GIR_Coverage, 3619, |
| 15547 | GIR_EraseRootFromParent_Done, |
| 15548 | // Label 1018: @38468 |
| 15549 | GIM_Reject, |
| 15550 | // Label 1015: @38469 |
| 15551 | GIM_Reject, |
| 15552 | // Label 1012: @38470 |
| 15553 | GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(38493), // Rule ID 110 // |
| 15554 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 15555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 15556 | // MIs[0] Operand 1 |
| 15557 | // No operand predicates |
| 15558 | // (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$D => (LI:{ *:[i32] } (imm:{ *:[i32] }):$D) |
| 15559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 15561 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // D |
| 15562 | GIR_RootConstrainSelectedInstOperands, |
| 15563 | // GIR_Coverage, 110, |
| 15564 | GIR_EraseRootFromParent_Done, |
| 15565 | // Label 1019: @38493 |
| 15566 | GIM_Reject, |
| 15567 | // Label 1013: @38494 |
| 15568 | GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(38517), // Rule ID 636 // |
| 15569 | GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 15570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15571 | // MIs[0] Operand 1 |
| 15572 | // No operand predicates |
| 15573 | // (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$D => (LI8:{ *:[i64] } (imm:{ *:[i64] }):$D) |
| 15574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 15576 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // D |
| 15577 | GIR_RootConstrainSelectedInstOperands, |
| 15578 | // GIR_Coverage, 636, |
| 15579 | GIR_EraseRootFromParent_Done, |
| 15580 | // Label 1020: @38517 |
| 15581 | GIM_Reject, |
| 15582 | // Label 1014: @38518 |
| 15583 | GIM_Reject, |
| 15584 | // Label 24: @38519 |
| 15585 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1023*/ GIMT_Encode4(38724), |
| 15586 | /*GILLT_s32*//*Label 1021*/ GIMT_Encode4(38538), |
| 15587 | /*GILLT_s64*//*Label 1022*/ GIMT_Encode4(38621), |
| 15588 | // Label 1021: @38538 |
| 15589 | GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(38620), |
| 15590 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 15592 | GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(38565), // Rule ID 2966 // |
| 15593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 15594 | // (sext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SETNBC:{ *:[i32] } ?:{ *:[i1] }:$in) |
| 15595 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETNBC), |
| 15596 | GIR_RootConstrainSelectedInstOperands, |
| 15597 | // GIR_Coverage, 2966, |
| 15598 | GIR_Done, |
| 15599 | // Label 1025: @38565 |
| 15600 | GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(38619), // Rule ID 3621 // |
| 15601 | // (sext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } ?:{ *:[i1] }:$in, (LI:{ *:[i32] } -1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] })) |
| 15602 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15603 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 15604 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15605 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15606 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 15607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15610 | GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1), |
| 15611 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4), |
| 15613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15614 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 15615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15617 | GIR_RootConstrainSelectedInstOperands, |
| 15618 | // GIR_Coverage, 3621, |
| 15619 | GIR_EraseRootFromParent_Done, |
| 15620 | // Label 1026: @38619 |
| 15621 | GIM_Reject, |
| 15622 | // Label 1024: @38620 |
| 15623 | GIM_Reject, |
| 15624 | // Label 1022: @38621 |
| 15625 | GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(38640), // Rule ID 677 // |
| 15626 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 15627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15628 | // (sext:{ *:[i64] } i32:{ *:[i32] }:$RST) => (EXTSW_32_64:{ *:[i64] } i32:{ *:[i32] }:$RST) |
| 15629 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EXTSW_32_64), |
| 15630 | GIR_RootConstrainSelectedInstOperands, |
| 15631 | // GIR_Coverage, 677, |
| 15632 | GIR_Done, |
| 15633 | // Label 1027: @38640 |
| 15634 | GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(38662), // Rule ID 2967 // |
| 15635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 15636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15638 | // (sext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SETNBC8:{ *:[i64] } ?:{ *:[i1] }:$in) |
| 15639 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETNBC8), |
| 15640 | GIR_RootConstrainSelectedInstOperands, |
| 15641 | // GIR_Coverage, 2967, |
| 15642 | GIR_Done, |
| 15643 | // Label 1028: @38662 |
| 15644 | GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(38723), // Rule ID 3623 // |
| 15645 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15647 | // (sext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } ?:{ *:[i1] }:$in, (LI8:{ *:[i64] } -1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] })) |
| 15648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 15649 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 15650 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15651 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15652 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 15653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15656 | GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1), |
| 15657 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8), |
| 15659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15660 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 15661 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15663 | GIR_RootConstrainSelectedInstOperands, |
| 15664 | // GIR_Coverage, 3623, |
| 15665 | GIR_EraseRootFromParent_Done, |
| 15666 | // Label 1029: @38723 |
| 15667 | GIM_Reject, |
| 15668 | // Label 1023: @38724 |
| 15669 | GIM_Reject, |
| 15670 | // Label 25: @38725 |
| 15671 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1032*/ GIMT_Encode4(38910), |
| 15672 | /*GILLT_s32*//*Label 1030*/ GIMT_Encode4(38744), |
| 15673 | /*GILLT_s64*//*Label 1031*/ GIMT_Encode4(38827), |
| 15674 | // Label 1030: @38744 |
| 15675 | GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(38826), |
| 15676 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 15678 | GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(38771), // Rule ID 2964 // |
| 15679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 15680 | // (zext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SETBC:{ *:[i32] } ?:{ *:[i1] }:$in) |
| 15681 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC), |
| 15682 | GIR_RootConstrainSelectedInstOperands, |
| 15683 | // GIR_Coverage, 2964, |
| 15684 | GIR_Done, |
| 15685 | // Label 1034: @38771 |
| 15686 | GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(38825), // Rule ID 3620 // |
| 15687 | // (zext:{ *:[i32] } i1:{ *:[i1] }:$in) => (SELECT_I4:{ *:[i32] } ?:{ *:[i1] }:$in, (LI:{ *:[i32] } 1:{ *:[i32] }), (LI:{ *:[i32] } 0:{ *:[i32] })) |
| 15688 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15689 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 15690 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15691 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15692 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 15693 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15694 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI), |
| 15695 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15696 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 15697 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4), |
| 15699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15700 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 15701 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15702 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15703 | GIR_RootConstrainSelectedInstOperands, |
| 15704 | // GIR_Coverage, 3620, |
| 15705 | GIR_EraseRootFromParent_Done, |
| 15706 | // Label 1035: @38825 |
| 15707 | GIM_Reject, |
| 15708 | // Label 1033: @38826 |
| 15709 | GIM_Reject, |
| 15710 | // Label 1031: @38827 |
| 15711 | GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(38909), |
| 15712 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 15713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15714 | GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(38854), // Rule ID 2965 // |
| 15715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 15716 | // (zext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SETBC8:{ *:[i64] } ?:{ *:[i1] }:$in) |
| 15717 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SETBC8), |
| 15718 | GIR_RootConstrainSelectedInstOperands, |
| 15719 | // GIR_Coverage, 2965, |
| 15720 | GIR_Done, |
| 15721 | // Label 1037: @38854 |
| 15722 | GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(38908), // Rule ID 3622 // |
| 15723 | // (zext:{ *:[i64] } i1:{ *:[i1] }:$in) => (SELECT_I8:{ *:[i64] } ?:{ *:[i1] }:$in, (LI8:{ *:[i64] } 1:{ *:[i64] }), (LI8:{ *:[i64] } 0:{ *:[i64] })) |
| 15724 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 15725 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 15726 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15727 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15728 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 15729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15730 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::LI8), |
| 15731 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15732 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 15733 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8), |
| 15735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 15736 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 15737 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15738 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15739 | GIR_RootConstrainSelectedInstOperands, |
| 15740 | // GIR_Coverage, 3622, |
| 15741 | GIR_EraseRootFromParent_Done, |
| 15742 | // Label 1038: @38908 |
| 15743 | GIM_Reject, |
| 15744 | // Label 1036: @38909 |
| 15745 | GIM_Reject, |
| 15746 | // Label 1032: @38910 |
| 15747 | GIM_Reject, |
| 15748 | // Label 26: @38911 |
| 15749 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1046*/ GIMT_Encode4(39260), |
| 15750 | /*GILLT_s32*//*Label 1039*/ GIMT_Encode4(38950), |
| 15751 | /*GILLT_s64*//*Label 1040*/ GIMT_Encode4(38973), |
| 15752 | /*GILLT_s128*//*Label 1041*/ GIMT_Encode4(38996), |
| 15753 | /*GILLT_v2s64*//*Label 1042*/ GIMT_Encode4(39156), |
| 15754 | /*GILLT_v4s32*//*Label 1043*/ GIMT_Encode4(39182), |
| 15755 | /*GILLT_v8s16*//*Label 1044*/ GIMT_Encode4(39208), |
| 15756 | /*GILLT_v16s8*//*Label 1045*/ GIMT_Encode4(39234), |
| 15757 | // Label 1039: @38950 |
| 15758 | GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(38972), // Rule ID 1240 // |
| 15759 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 15760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 15762 | // (shl:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (SLW:{ *:[i32] } ?:{ *:[i32] }:$rS, ?:{ *:[i32] }:$rB) |
| 15763 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SLW), |
| 15764 | GIR_RootConstrainSelectedInstOperands, |
| 15765 | // GIR_Coverage, 1240, |
| 15766 | GIR_Done, |
| 15767 | // Label 1047: @38972 |
| 15768 | GIM_Reject, |
| 15769 | // Label 1040: @38973 |
| 15770 | GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(38995), // Rule ID 1521 // |
| 15771 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 15772 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15774 | // (shl:{ *:[i64] } i64:{ *:[i64] }:$rS, i32:{ *:[i32] }:$rB) => (SLD:{ *:[i64] } ?:{ *:[i64] }:$rS, ?:{ *:[i32] }:$rB) |
| 15775 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SLD), |
| 15776 | GIR_RootConstrainSelectedInstOperands, |
| 15777 | // GIR_Coverage, 1521, |
| 15778 | GIR_Done, |
| 15779 | // Label 1048: @38995 |
| 15780 | GIM_Reject, |
| 15781 | // Label 1041: @38996 |
| 15782 | GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(39155), |
| 15783 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 15784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 15785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15786 | GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(39090), // Rule ID 3352 // |
| 15787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), |
| 15788 | // (shl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, v1i128:{ *:[v1i128] }:$VRB) => (VSLQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, (XXPERMDI:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), 2:{ *:[i32] })) |
| 15789 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15790 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 15791 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 15792 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15793 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15794 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 15795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 15796 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15797 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15798 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 15799 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15800 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), |
| 15801 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15802 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 15803 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 15804 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 15805 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSLQ), |
| 15807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15808 | GIR_RootToRootCopy, /*OpIdx*/1, // VRA |
| 15809 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15810 | GIR_RootConstrainSelectedInstOperands, |
| 15811 | // GIR_Coverage, 3352, |
| 15812 | GIR_EraseRootFromParent_Done, |
| 15813 | // Label 1050: @39090 |
| 15814 | GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(39154), // Rule ID 1379 // |
| 15815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15816 | // (shl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VSL:{ *:[v1i128] } (VSLO:{ *:[v16i8] } ?:{ *:[v1i128] }:$vA, ?:{ *:[v1i128] }:$vB), (VSPLTB:{ *:[v16i8] } 15:{ *:[i32] }, ?:{ *:[v1i128] }:$vB)) |
| 15817 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 15818 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 15819 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::VSPLTB), |
| 15820 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15821 | GIR_AddImm8, /*InsnID*/2, /*Imm*/15, |
| 15822 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 15823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15824 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::VSLO), |
| 15825 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15826 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vA |
| 15827 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 15828 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSL), |
| 15830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15831 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15832 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15833 | GIR_RootConstrainSelectedInstOperands, |
| 15834 | // GIR_Coverage, 1379, |
| 15835 | GIR_EraseRootFromParent_Done, |
| 15836 | // Label 1051: @39154 |
| 15837 | GIM_Reject, |
| 15838 | // Label 1049: @39155 |
| 15839 | GIM_Reject, |
| 15840 | // Label 1042: @39156 |
| 15841 | GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(39181), // Rule ID 1427 // |
| 15842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 15843 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 15844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15846 | // (shl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSLD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) |
| 15847 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLD), |
| 15848 | GIR_RootConstrainSelectedInstOperands, |
| 15849 | // GIR_Coverage, 1427, |
| 15850 | GIR_Done, |
| 15851 | // Label 1052: @39181 |
| 15852 | GIM_Reject, |
| 15853 | // Label 1043: @39182 |
| 15854 | GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(39207), // Rule ID 1378 // |
| 15855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15856 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 15857 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15859 | // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSLW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 15860 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLW), |
| 15861 | GIR_RootConstrainSelectedInstOperands, |
| 15862 | // GIR_Coverage, 1378, |
| 15863 | GIR_Done, |
| 15864 | // Label 1053: @39207 |
| 15865 | GIM_Reject, |
| 15866 | // Label 1044: @39208 |
| 15867 | GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(39233), // Rule ID 1377 // |
| 15868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15869 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15870 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15872 | // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSLH:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 15873 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLH), |
| 15874 | GIR_RootConstrainSelectedInstOperands, |
| 15875 | // GIR_Coverage, 1377, |
| 15876 | GIR_Done, |
| 15877 | // Label 1054: @39233 |
| 15878 | GIM_Reject, |
| 15879 | // Label 1045: @39234 |
| 15880 | GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(39259), // Rule ID 1376 // |
| 15881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15882 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 15883 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15885 | // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSLB:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 15886 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSLB), |
| 15887 | GIR_RootConstrainSelectedInstOperands, |
| 15888 | // GIR_Coverage, 1376, |
| 15889 | GIR_Done, |
| 15890 | // Label 1055: @39259 |
| 15891 | GIM_Reject, |
| 15892 | // Label 1046: @39260 |
| 15893 | GIM_Reject, |
| 15894 | // Label 27: @39261 |
| 15895 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1063*/ GIMT_Encode4(39610), |
| 15896 | /*GILLT_s32*//*Label 1056*/ GIMT_Encode4(39300), |
| 15897 | /*GILLT_s64*//*Label 1057*/ GIMT_Encode4(39323), |
| 15898 | /*GILLT_s128*//*Label 1058*/ GIMT_Encode4(39346), |
| 15899 | /*GILLT_v2s64*//*Label 1059*/ GIMT_Encode4(39506), |
| 15900 | /*GILLT_v4s32*//*Label 1060*/ GIMT_Encode4(39532), |
| 15901 | /*GILLT_v8s16*//*Label 1061*/ GIMT_Encode4(39558), |
| 15902 | /*GILLT_v16s8*//*Label 1062*/ GIMT_Encode4(39584), |
| 15903 | // Label 1056: @39300 |
| 15904 | GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(39322), // Rule ID 1239 // |
| 15905 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 15906 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 15908 | // (srl:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (SRW:{ *:[i32] } ?:{ *:[i32] }:$rS, ?:{ *:[i32] }:$rB) |
| 15909 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRW), |
| 15910 | GIR_RootConstrainSelectedInstOperands, |
| 15911 | // GIR_Coverage, 1239, |
| 15912 | GIR_Done, |
| 15913 | // Label 1064: @39322 |
| 15914 | GIM_Reject, |
| 15915 | // Label 1057: @39323 |
| 15916 | GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(39345), // Rule ID 1520 // |
| 15917 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 15918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 15920 | // (srl:{ *:[i64] } i64:{ *:[i64] }:$rS, i32:{ *:[i32] }:$rB) => (SRD:{ *:[i64] } ?:{ *:[i64] }:$rS, ?:{ *:[i32] }:$rB) |
| 15921 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRD), |
| 15922 | GIR_RootConstrainSelectedInstOperands, |
| 15923 | // GIR_Coverage, 1520, |
| 15924 | GIR_Done, |
| 15925 | // Label 1065: @39345 |
| 15926 | GIM_Reject, |
| 15927 | // Label 1058: @39346 |
| 15928 | GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(39505), |
| 15929 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 15930 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 15931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15932 | GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(39440), // Rule ID 3354 // |
| 15933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), |
| 15934 | // (srl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, v1i128:{ *:[v1i128] }:$VRB) => (VSRQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, (XXPERMDI:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), 2:{ *:[i32] })) |
| 15935 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15936 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 15937 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 15938 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15939 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15940 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 15941 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 15942 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 15943 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15944 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 15945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15946 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), |
| 15947 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15948 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 15949 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 15950 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 15951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRQ), |
| 15953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15954 | GIR_RootToRootCopy, /*OpIdx*/1, // VRA |
| 15955 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15956 | GIR_RootConstrainSelectedInstOperands, |
| 15957 | // GIR_Coverage, 3354, |
| 15958 | GIR_EraseRootFromParent_Done, |
| 15959 | // Label 1067: @39440 |
| 15960 | GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(39504), // Rule ID 1387 // |
| 15961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 15962 | // (srl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VSR:{ *:[v1i128] } (VSRO:{ *:[v16i8] } ?:{ *:[v1i128] }:$vA, ?:{ *:[v1i128] }:$vB), (VSPLTB:{ *:[v16i8] } 15:{ *:[i32] }, ?:{ *:[v1i128] }:$vB)) |
| 15963 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 15964 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 15965 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::VSPLTB), |
| 15966 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15967 | GIR_AddImm8, /*InsnID*/2, /*Imm*/15, |
| 15968 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 15969 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15970 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::VSRO), |
| 15971 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 15972 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vA |
| 15973 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 15974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSR), |
| 15976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 15977 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15978 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 15979 | GIR_RootConstrainSelectedInstOperands, |
| 15980 | // GIR_Coverage, 1387, |
| 15981 | GIR_EraseRootFromParent_Done, |
| 15982 | // Label 1068: @39504 |
| 15983 | GIM_Reject, |
| 15984 | // Label 1066: @39505 |
| 15985 | GIM_Reject, |
| 15986 | // Label 1059: @39506 |
| 15987 | GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(39531), // Rule ID 1429 // |
| 15988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 15989 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 15990 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 15992 | // (srl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSRD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) |
| 15993 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRD), |
| 15994 | GIR_RootConstrainSelectedInstOperands, |
| 15995 | // GIR_Coverage, 1429, |
| 15996 | GIR_Done, |
| 15997 | // Label 1069: @39531 |
| 15998 | GIM_Reject, |
| 15999 | // Label 1060: @39532 |
| 16000 | GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(39557), // Rule ID 1386 // |
| 16001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16002 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16003 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16005 | // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 16006 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRW), |
| 16007 | GIR_RootConstrainSelectedInstOperands, |
| 16008 | // GIR_Coverage, 1386, |
| 16009 | GIR_Done, |
| 16010 | // Label 1070: @39557 |
| 16011 | GIM_Reject, |
| 16012 | // Label 1061: @39558 |
| 16013 | GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(39583), // Rule ID 1385 // |
| 16014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16018 | // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSRH:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 16019 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRH), |
| 16020 | GIR_RootConstrainSelectedInstOperands, |
| 16021 | // GIR_Coverage, 1385, |
| 16022 | GIR_Done, |
| 16023 | // Label 1071: @39583 |
| 16024 | GIM_Reject, |
| 16025 | // Label 1062: @39584 |
| 16026 | GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(39609), // Rule ID 1384 // |
| 16027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 16029 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 16030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16031 | // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRB:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 16032 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRB), |
| 16033 | GIR_RootConstrainSelectedInstOperands, |
| 16034 | // GIR_Coverage, 1384, |
| 16035 | GIR_Done, |
| 16036 | // Label 1072: @39609 |
| 16037 | GIM_Reject, |
| 16038 | // Label 1063: @39610 |
| 16039 | GIM_Reject, |
| 16040 | // Label 28: @39611 |
| 16041 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1080*/ GIMT_Encode4(39974), |
| 16042 | /*GILLT_s32*//*Label 1073*/ GIMT_Encode4(39650), |
| 16043 | /*GILLT_s64*//*Label 1074*/ GIMT_Encode4(39715), |
| 16044 | /*GILLT_s128*//*Label 1075*/ GIMT_Encode4(39780), |
| 16045 | /*GILLT_v2s64*//*Label 1076*/ GIMT_Encode4(39870), |
| 16046 | /*GILLT_v4s32*//*Label 1077*/ GIMT_Encode4(39896), |
| 16047 | /*GILLT_v8s16*//*Label 1078*/ GIMT_Encode4(39922), |
| 16048 | /*GILLT_v16s8*//*Label 1079*/ GIMT_Encode4(39948), |
| 16049 | // Label 1073: @39650 |
| 16050 | GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(39714), |
| 16051 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 16052 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 16054 | GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(39695), // Rule ID 129 // |
| 16055 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16056 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16057 | // MIs[1] Operand 1 |
| 16058 | // No operand predicates |
| 16059 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16060 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$RST, (imm:{ *:[i32] }):$RB) => (SRAWI:{ *:[i32] }:{ *:[i32] } i32:{ *:[i32] }:$RST, (imm:{ *:[i32] }):$RB) |
| 16061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SRAWI), |
| 16062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 16063 | GIR_RootToRootCopy, /*OpIdx*/1, // RST |
| 16064 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // RB |
| 16065 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0, |
| 16066 | GIR_RootConstrainSelectedInstOperands, |
| 16067 | // GIR_Coverage, 129, |
| 16068 | GIR_EraseRootFromParent_Done, |
| 16069 | // Label 1082: @39695 |
| 16070 | GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(39713), // Rule ID 1238 // |
| 16071 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$rS, i32:{ *:[i32] }:$rB) => (SRAW:{ *:[i32] }:{ *:[i32] } ?:{ *:[i32] }:$rS, ?:{ *:[i32] }:$rB) |
| 16072 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRAW), |
| 16073 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CARRY), GIMT_Encode2(RegState::Dead), |
| 16074 | GIR_RootConstrainSelectedInstOperands, |
| 16075 | // GIR_Coverage, 1238, |
| 16076 | GIR_Done, |
| 16077 | // Label 1083: @39713 |
| 16078 | GIM_Reject, |
| 16079 | // Label 1081: @39714 |
| 16080 | GIM_Reject, |
| 16081 | // Label 1074: @39715 |
| 16082 | GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(39779), |
| 16083 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 16084 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 16086 | GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(39760), // Rule ID 678 // |
| 16087 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16088 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16089 | // MIs[1] Operand 1 |
| 16090 | // No operand predicates |
| 16091 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16092 | // (sra:{ *:[i64] } i64:{ *:[i64] }:$RS, (imm:{ *:[i32] }):$SH) => (SRADI:{ *:[i64] }:{ *:[i32] } i64:{ *:[i64] }:$RS, (imm:{ *:[i32] }):$SH) |
| 16093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::SRADI), |
| 16094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 16095 | GIR_RootToRootCopy, /*OpIdx*/1, // RS |
| 16096 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SH |
| 16097 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for PPC::CARRY*/0, |
| 16098 | GIR_RootConstrainSelectedInstOperands, |
| 16099 | // GIR_Coverage, 678, |
| 16100 | GIR_EraseRootFromParent_Done, |
| 16101 | // Label 1085: @39760 |
| 16102 | GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(39778), // Rule ID 1519 // |
| 16103 | // (sra:{ *:[i64] } i64:{ *:[i64] }:$rS, i32:{ *:[i32] }:$rB) => (SRAD:{ *:[i64] }:{ *:[i32] } ?:{ *:[i64] }:$rS, ?:{ *:[i32] }:$rB) |
| 16104 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SRAD), |
| 16105 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(PPC::CARRY), GIMT_Encode2(RegState::Dead), |
| 16106 | GIR_RootConstrainSelectedInstOperands, |
| 16107 | // GIR_Coverage, 1519, |
| 16108 | GIR_Done, |
| 16109 | // Label 1086: @39778 |
| 16110 | GIM_Reject, |
| 16111 | // Label 1084: @39779 |
| 16112 | GIM_Reject, |
| 16113 | // Label 1075: @39780 |
| 16114 | GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(39869), // Rule ID 3356 // |
| 16115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsISA3_1), |
| 16116 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 16117 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 16118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16119 | // (sra:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, v1i128:{ *:[v1i128] }:$VRB) => (VSRAQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$VRA, (XXPERMDI:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$VRB, VSRC:{ *:[i32] }), 2:{ *:[i32] })) |
| 16120 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16121 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 16122 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 16123 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16124 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16125 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 16126 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 16127 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16128 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16129 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // VRB |
| 16130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16131 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXPERMDI), |
| 16132 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16133 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 16134 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 16135 | GIR_AddImm8, /*InsnID*/1, /*Imm*/2, |
| 16136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSRAQ), |
| 16138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 16139 | GIR_RootToRootCopy, /*OpIdx*/1, // VRA |
| 16140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16141 | GIR_RootConstrainSelectedInstOperands, |
| 16142 | // GIR_Coverage, 3356, |
| 16143 | GIR_EraseRootFromParent_Done, |
| 16144 | // Label 1087: @39869 |
| 16145 | GIM_Reject, |
| 16146 | // Label 1076: @39870 |
| 16147 | GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(39895), // Rule ID 1431 // |
| 16148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 16149 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16152 | // (sra:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VSRAD:{ *:[v2i64] } ?:{ *:[v2i64] }:$vA, ?:{ *:[v2i64] }:$vB) |
| 16153 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAD), |
| 16154 | GIR_RootConstrainSelectedInstOperands, |
| 16155 | // GIR_Coverage, 1431, |
| 16156 | GIR_Done, |
| 16157 | // Label 1088: @39895 |
| 16158 | GIM_Reject, |
| 16159 | // Label 1077: @39896 |
| 16160 | GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(39921), // Rule ID 1394 // |
| 16161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16162 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16163 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16165 | // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSRAW:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 16166 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAW), |
| 16167 | GIR_RootConstrainSelectedInstOperands, |
| 16168 | // GIR_Coverage, 1394, |
| 16169 | GIR_Done, |
| 16170 | // Label 1089: @39921 |
| 16171 | GIM_Reject, |
| 16172 | // Label 1078: @39922 |
| 16173 | GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(39947), // Rule ID 1393 // |
| 16174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16175 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16178 | // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSRAH:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 16179 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAH), |
| 16180 | GIR_RootConstrainSelectedInstOperands, |
| 16181 | // GIR_Coverage, 1393, |
| 16182 | GIR_Done, |
| 16183 | // Label 1090: @39947 |
| 16184 | GIM_Reject, |
| 16185 | // Label 1079: @39948 |
| 16186 | GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(39973), // Rule ID 1392 // |
| 16187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16188 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 16189 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 16190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16191 | // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSRAB:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 16192 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSRAB), |
| 16193 | GIR_RootConstrainSelectedInstOperands, |
| 16194 | // GIR_Coverage, 1392, |
| 16195 | GIR_Done, |
| 16196 | // Label 1091: @39973 |
| 16197 | GIM_Reject, |
| 16198 | // Label 1080: @39974 |
| 16199 | GIM_Reject, |
| 16200 | // Label 29: @39975 |
| 16201 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1099*/ GIMT_Encode4(40282), |
| 16202 | /*GILLT_s32*//*Label 1092*/ GIMT_Encode4(40014), |
| 16203 | /*GILLT_s64*//*Label 1093*/ GIMT_Encode4(40086), |
| 16204 | /*GILLT_s128*//*Label 1094*/ GIMT_Encode4(40152), |
| 16205 | /*GILLT_v2s64*//*Label 1095*/ GIMT_Encode4(40178), |
| 16206 | /*GILLT_v4s32*//*Label 1096*/ GIMT_Encode4(40204), |
| 16207 | /*GILLT_v8s16*//*Label 1097*/ GIMT_Encode4(40230), |
| 16208 | /*GILLT_v16s8*//*Label 1098*/ GIMT_Encode4(40256), |
| 16209 | // Label 1092: @40014 |
| 16210 | GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(40085), |
| 16211 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 16212 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 16214 | GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(40062), // Rule ID 1204 // |
| 16215 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16216 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16217 | // MIs[1] Operand 1 |
| 16218 | // No operand predicates |
| 16219 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16220 | // (rotl:{ *:[i32] } i32:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm) => (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$in, (imm:{ *:[i32] }):$imm, 0:{ *:[i32] }, 31:{ *:[i32] }) |
| 16221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 16222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 16223 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 16224 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/31, |
| 16227 | GIR_RootConstrainSelectedInstOperands, |
| 16228 | // GIR_Coverage, 1204, |
| 16229 | GIR_EraseRootFromParent_Done, |
| 16230 | // Label 1101: @40062 |
| 16231 | GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(40084), // Rule ID 1203 // |
| 16232 | // (rotl:{ *:[i32] } i32:{ *:[i32] }:$in, i32:{ *:[i32] }:$sh) => (RLWNM:{ *:[i32] } ?:{ *:[i32] }:$in, ?:{ *:[i32] }:$sh, 0:{ *:[i32] }, 31:{ *:[i32] }) |
| 16233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWNM), |
| 16234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 16235 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 16236 | GIR_RootToRootCopy, /*OpIdx*/2, // sh |
| 16237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/31, |
| 16239 | GIR_RootConstrainSelectedInstOperands, |
| 16240 | // GIR_Coverage, 1203, |
| 16241 | GIR_EraseRootFromParent_Done, |
| 16242 | // Label 1102: @40084 |
| 16243 | GIM_Reject, |
| 16244 | // Label 1100: @40085 |
| 16245 | GIM_Reject, |
| 16246 | // Label 1093: @40086 |
| 16247 | GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(40151), |
| 16248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 16249 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 16251 | GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(40131), // Rule ID 1526 // |
| 16252 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16253 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16254 | // MIs[1] Operand 1 |
| 16255 | // No operand predicates |
| 16256 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16257 | // (rotl:{ *:[i64] } i64:{ *:[i64] }:$in, (imm:{ *:[i32] }):$imm) => (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$in, (imm:{ *:[i32] }):$imm, 0:{ *:[i32] }) |
| 16258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 16259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 16260 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 16261 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 16262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16263 | GIR_RootConstrainSelectedInstOperands, |
| 16264 | // GIR_Coverage, 1526, |
| 16265 | GIR_EraseRootFromParent_Done, |
| 16266 | // Label 1104: @40131 |
| 16267 | GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(40150), // Rule ID 1525 // |
| 16268 | // (rotl:{ *:[i64] } i64:{ *:[i64] }:$in, i32:{ *:[i32] }:$sh) => (RLDCL:{ *:[i64] } ?:{ *:[i64] }:$in, ?:{ *:[i32] }:$sh, 0:{ *:[i32] }) |
| 16269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDCL), |
| 16270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 16271 | GIR_RootToRootCopy, /*OpIdx*/1, // in |
| 16272 | GIR_RootToRootCopy, /*OpIdx*/2, // sh |
| 16273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16274 | GIR_RootConstrainSelectedInstOperands, |
| 16275 | // GIR_Coverage, 1525, |
| 16276 | GIR_EraseRootFromParent_Done, |
| 16277 | // Label 1105: @40150 |
| 16278 | GIM_Reject, |
| 16279 | // Label 1103: @40151 |
| 16280 | GIM_Reject, |
| 16281 | // Label 1094: @40152 |
| 16282 | GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(40177), // Rule ID 3338 // |
| 16283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 16285 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 16286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16287 | // (rotl:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) => (VRLQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB) |
| 16288 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLQ), |
| 16289 | GIR_RootConstrainSelectedInstOperands, |
| 16290 | // GIR_Coverage, 3338, |
| 16291 | GIR_Done, |
| 16292 | // Label 1106: @40177 |
| 16293 | GIM_Reject, |
| 16294 | // Label 1095: @40178 |
| 16295 | GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(40203), // Rule ID 1426 // |
| 16296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 16297 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 16298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 16299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16300 | // (rotl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) => (VRLD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB) |
| 16301 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLD), |
| 16302 | GIR_RootConstrainSelectedInstOperands, |
| 16303 | // GIR_Coverage, 1426, |
| 16304 | GIR_Done, |
| 16305 | // Label 1107: @40203 |
| 16306 | GIM_Reject, |
| 16307 | // Label 1096: @40204 |
| 16308 | GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(40229), // Rule ID 1277 // |
| 16309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16310 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16311 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16313 | // (rotl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VRLW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) |
| 16314 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLW), |
| 16315 | GIR_RootConstrainSelectedInstOperands, |
| 16316 | // GIR_Coverage, 1277, |
| 16317 | GIR_Done, |
| 16318 | // Label 1108: @40229 |
| 16319 | GIM_Reject, |
| 16320 | // Label 1097: @40230 |
| 16321 | GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(40255), // Rule ID 1276 // |
| 16322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16323 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16326 | // (rotl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VRLH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) |
| 16327 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLH), |
| 16328 | GIR_RootConstrainSelectedInstOperands, |
| 16329 | // GIR_Coverage, 1276, |
| 16330 | GIR_Done, |
| 16331 | // Label 1109: @40255 |
| 16332 | GIM_Reject, |
| 16333 | // Label 1098: @40256 |
| 16334 | GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(40281), // Rule ID 1275 // |
| 16335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 16336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 16337 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 16338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 16339 | // (rotl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VRLB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) |
| 16340 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRLB), |
| 16341 | GIR_RootConstrainSelectedInstOperands, |
| 16342 | // GIR_Coverage, 1275, |
| 16343 | GIR_Done, |
| 16344 | // Label 1110: @40281 |
| 16345 | GIM_Reject, |
| 16346 | // Label 1099: @40282 |
| 16347 | GIM_Reject, |
| 16348 | // Label 30: @40283 |
| 16349 | GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(44284), |
| 16350 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 16351 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1114*/ GIMT_Encode4(40860), |
| 16352 | /*GILLT_s32*//*Label 1112*/ GIMT_Encode4(40310), |
| 16353 | /*GILLT_s64*//*Label 1113*/ GIMT_Encode4(40585), |
| 16354 | // Label 1112: @40310 |
| 16355 | GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(40584), |
| 16356 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16358 | GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(40409), // Rule ID 3010 // |
| 16359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16360 | // MIs[0] Operand 1 |
| 16361 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 16362 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16363 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16364 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16365 | // MIs[1] Operand 1 |
| 16366 | // No operand predicates |
| 16367 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16368 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] })) |
| 16369 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16370 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16371 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16372 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16373 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16374 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16376 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16377 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16378 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 16379 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16380 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16383 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16384 | GIR_RootConstrainSelectedInstOperands, |
| 16385 | // GIR_Coverage, 3010, |
| 16386 | GIR_EraseRootFromParent_Done, |
| 16387 | // Label 1116: @40409 |
| 16388 | GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(40496), // Rule ID 3026 // |
| 16389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16390 | // MIs[0] Operand 1 |
| 16391 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 16392 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16393 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16394 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16395 | // MIs[1] Operand 1 |
| 16396 | // No operand predicates |
| 16397 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16398 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] })) |
| 16399 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16400 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16401 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16402 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16403 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16404 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16405 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16406 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16407 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16408 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 16409 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16410 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16413 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16414 | GIR_RootConstrainSelectedInstOperands, |
| 16415 | // GIR_Coverage, 3026, |
| 16416 | GIR_EraseRootFromParent_Done, |
| 16417 | // Label 1117: @40496 |
| 16418 | GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(40583), // Rule ID 3034 // |
| 16419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16420 | // MIs[0] Operand 1 |
| 16421 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 16422 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16423 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16424 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16425 | // MIs[1] Operand 1 |
| 16426 | // No operand predicates |
| 16427 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16428 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] })) |
| 16429 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16430 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16431 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16432 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16433 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16434 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16436 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16437 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16438 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 16439 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16440 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16443 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16444 | GIR_RootConstrainSelectedInstOperands, |
| 16445 | // GIR_Coverage, 3034, |
| 16446 | GIR_EraseRootFromParent_Done, |
| 16447 | // Label 1118: @40583 |
| 16448 | GIM_Reject, |
| 16449 | // Label 1115: @40584 |
| 16450 | GIM_Reject, |
| 16451 | // Label 1113: @40585 |
| 16452 | GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(40859), |
| 16453 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 16454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16455 | GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(40684), // Rule ID 3106 // |
| 16456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16457 | // MIs[0] Operand 1 |
| 16458 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 16459 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16460 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16461 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16462 | // MIs[1] Operand 1 |
| 16463 | // No operand predicates |
| 16464 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16465 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] })) |
| 16466 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16467 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16468 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16469 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16470 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16471 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16472 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16473 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16474 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16475 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 16476 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16477 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16480 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16481 | GIR_RootConstrainSelectedInstOperands, |
| 16482 | // GIR_Coverage, 3106, |
| 16483 | GIR_EraseRootFromParent_Done, |
| 16484 | // Label 1120: @40684 |
| 16485 | GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(40771), // Rule ID 3122 // |
| 16486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16487 | // MIs[0] Operand 1 |
| 16488 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 16489 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16490 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16491 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16492 | // MIs[1] Operand 1 |
| 16493 | // No operand predicates |
| 16494 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16495 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] })) |
| 16496 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16497 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16498 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16499 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16500 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16501 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16504 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16505 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 16506 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16507 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16511 | GIR_RootConstrainSelectedInstOperands, |
| 16512 | // GIR_Coverage, 3122, |
| 16513 | GIR_EraseRootFromParent_Done, |
| 16514 | // Label 1121: @40771 |
| 16515 | GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(40858), // Rule ID 3130 // |
| 16516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 16517 | // MIs[0] Operand 1 |
| 16518 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 16519 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16520 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16521 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16522 | // MIs[1] Operand 1 |
| 16523 | // No operand predicates |
| 16524 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16525 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] })) |
| 16526 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16527 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16528 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16529 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16530 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16531 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16533 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16534 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16535 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 16536 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16537 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16540 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16541 | GIR_RootConstrainSelectedInstOperands, |
| 16542 | // GIR_Coverage, 3130, |
| 16543 | GIR_EraseRootFromParent_Done, |
| 16544 | // Label 1122: @40858 |
| 16545 | GIM_Reject, |
| 16546 | // Label 1119: @40859 |
| 16547 | GIM_Reject, |
| 16548 | // Label 1114: @40860 |
| 16549 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1125*/ GIMT_Encode4(41315), |
| 16550 | /*GILLT_s32*//*Label 1123*/ GIMT_Encode4(40879), |
| 16551 | /*GILLT_s64*//*Label 1124*/ GIMT_Encode4(41097), |
| 16552 | // Label 1123: @40879 |
| 16553 | GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(41096), |
| 16554 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 16556 | GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(40959), // Rule ID 3741 // |
| 16557 | // MIs[0] Operand 1 |
| 16558 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 16559 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16560 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16561 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16562 | // MIs[1] Operand 1 |
| 16563 | // No operand predicates |
| 16564 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16565 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] }) |
| 16566 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16567 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16568 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16569 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16570 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 16571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16574 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 16575 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16576 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16577 | // GIR_Coverage, 3741, |
| 16578 | GIR_EraseRootFromParent_Done, |
| 16579 | // Label 1127: @40959 |
| 16580 | GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(41027), // Rule ID 3743 // |
| 16581 | // MIs[0] Operand 1 |
| 16582 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 16583 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16584 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16585 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16586 | // MIs[1] Operand 1 |
| 16587 | // No operand predicates |
| 16588 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16589 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] }) |
| 16590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16593 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16594 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 16595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16598 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 16599 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16600 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16601 | // GIR_Coverage, 3743, |
| 16602 | GIR_EraseRootFromParent_Done, |
| 16603 | // Label 1128: @41027 |
| 16604 | GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(41095), // Rule ID 3744 // |
| 16605 | // MIs[0] Operand 1 |
| 16606 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 16607 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16608 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16609 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16610 | // MIs[1] Operand 1 |
| 16611 | // No operand predicates |
| 16612 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16613 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] }) |
| 16614 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16615 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16616 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16617 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16618 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 16619 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16622 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 16623 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16624 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16625 | // GIR_Coverage, 3744, |
| 16626 | GIR_EraseRootFromParent_Done, |
| 16627 | // Label 1129: @41095 |
| 16628 | GIM_Reject, |
| 16629 | // Label 1126: @41096 |
| 16630 | GIM_Reject, |
| 16631 | // Label 1124: @41097 |
| 16632 | GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(41314), |
| 16633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 16634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 16635 | GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(41177), // Rule ID 3753 // |
| 16636 | // MIs[0] Operand 1 |
| 16637 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 16638 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16639 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16640 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16641 | // MIs[1] Operand 1 |
| 16642 | // No operand predicates |
| 16643 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16644 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] }) |
| 16645 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16646 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16647 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16648 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16649 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 16650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16653 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 16654 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16655 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16656 | // GIR_Coverage, 3753, |
| 16657 | GIR_EraseRootFromParent_Done, |
| 16658 | // Label 1131: @41177 |
| 16659 | GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(41245), // Rule ID 3755 // |
| 16660 | // MIs[0] Operand 1 |
| 16661 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 16662 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16663 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16664 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16665 | // MIs[1] Operand 1 |
| 16666 | // No operand predicates |
| 16667 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16668 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] }) |
| 16669 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16670 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16671 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16672 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16673 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 16674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16677 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 16678 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16679 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16680 | // GIR_Coverage, 3755, |
| 16681 | GIR_EraseRootFromParent_Done, |
| 16682 | // Label 1132: @41245 |
| 16683 | GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(41313), // Rule ID 3756 // |
| 16684 | // MIs[0] Operand 1 |
| 16685 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 16686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16688 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16689 | // MIs[1] Operand 1 |
| 16690 | // No operand predicates |
| 16691 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16692 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] }) |
| 16693 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16694 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16695 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16696 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16697 | GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm |
| 16698 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16701 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 16702 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16703 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16704 | // GIR_Coverage, 3756, |
| 16705 | GIR_EraseRootFromParent_Done, |
| 16706 | // Label 1133: @41313 |
| 16707 | GIM_Reject, |
| 16708 | // Label 1130: @41314 |
| 16709 | GIM_Reject, |
| 16710 | // Label 1125: @41315 |
| 16711 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1136*/ GIMT_Encode4(41884), |
| 16712 | /*GILLT_s32*//*Label 1134*/ GIMT_Encode4(41334), |
| 16713 | /*GILLT_s64*//*Label 1135*/ GIMT_Encode4(41609), |
| 16714 | // Label 1134: @41334 |
| 16715 | GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(41608), |
| 16716 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16717 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16718 | GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(41433), // Rule ID 3764 // |
| 16719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 16720 | // MIs[0] Operand 1 |
| 16721 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 16722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16723 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16724 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16725 | // MIs[1] Operand 1 |
| 16726 | // No operand predicates |
| 16727 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16728 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_lt:{ *:[i32] })) |
| 16729 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16730 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16731 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16732 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16733 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16734 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16736 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16737 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16738 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 16739 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16740 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16743 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16744 | GIR_RootConstrainSelectedInstOperands, |
| 16745 | // GIR_Coverage, 3764, |
| 16746 | GIR_EraseRootFromParent_Done, |
| 16747 | // Label 1138: @41433 |
| 16748 | GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(41520), // Rule ID 3780 // |
| 16749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 16750 | // MIs[0] Operand 1 |
| 16751 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 16752 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16753 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16754 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16755 | // MIs[1] Operand 1 |
| 16756 | // No operand predicates |
| 16757 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16758 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_gt:{ *:[i32] })) |
| 16759 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16760 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16761 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16762 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16763 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16764 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16765 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16766 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16767 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16768 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 16769 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16770 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16773 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16774 | GIR_RootConstrainSelectedInstOperands, |
| 16775 | // GIR_Coverage, 3780, |
| 16776 | GIR_EraseRootFromParent_Done, |
| 16777 | // Label 1139: @41520 |
| 16778 | GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(41607), // Rule ID 3788 // |
| 16779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 16780 | // MIs[0] Operand 1 |
| 16781 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 16782 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16783 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16784 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32SExt16), |
| 16785 | // MIs[1] Operand 1 |
| 16786 | // No operand predicates |
| 16787 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16788 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPWI:{ *:[i32] } ?:{ *:[i32] }:$s1, (imm:{ *:[i32] }):$imm), sub_eq:{ *:[i32] })) |
| 16789 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16790 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16791 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPWI), |
| 16792 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16793 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16794 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16796 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16797 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16798 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 16799 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16800 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16803 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16804 | GIR_RootConstrainSelectedInstOperands, |
| 16805 | // GIR_Coverage, 3788, |
| 16806 | GIR_EraseRootFromParent_Done, |
| 16807 | // Label 1140: @41607 |
| 16808 | GIM_Reject, |
| 16809 | // Label 1137: @41608 |
| 16810 | GIM_Reject, |
| 16811 | // Label 1135: @41609 |
| 16812 | GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(41883), |
| 16813 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 16814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16815 | GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(41708), // Rule ID 3860 // |
| 16816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 16817 | // MIs[0] Operand 1 |
| 16818 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 16819 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16820 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16821 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16822 | // MIs[1] Operand 1 |
| 16823 | // No operand predicates |
| 16824 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16825 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_lt:{ *:[i32] })) |
| 16826 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16827 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16828 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16829 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16830 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16831 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16834 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16835 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 16836 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16837 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16840 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16841 | GIR_RootConstrainSelectedInstOperands, |
| 16842 | // GIR_Coverage, 3860, |
| 16843 | GIR_EraseRootFromParent_Done, |
| 16844 | // Label 1142: @41708 |
| 16845 | GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(41795), // Rule ID 3876 // |
| 16846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 16847 | // MIs[0] Operand 1 |
| 16848 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 16849 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16850 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16851 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16852 | // MIs[1] Operand 1 |
| 16853 | // No operand predicates |
| 16854 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16855 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_gt:{ *:[i32] })) |
| 16856 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16857 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16858 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16859 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16860 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16861 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16864 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16865 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 16866 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16867 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16870 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16871 | GIR_RootConstrainSelectedInstOperands, |
| 16872 | // GIR_Coverage, 3876, |
| 16873 | GIR_EraseRootFromParent_Done, |
| 16874 | // Label 1143: @41795 |
| 16875 | GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(41882), // Rule ID 3884 // |
| 16876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 16877 | // MIs[0] Operand 1 |
| 16878 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 16879 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16880 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16881 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64SExt16), |
| 16882 | // MIs[1] Operand 1 |
| 16883 | // No operand predicates |
| 16884 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16885 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, (imm:{ *:[i64] })<<P:Predicate_imm64SExt16>>:$imm, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPDI:{ *:[i32] } ?:{ *:[i64] }:$s1, (imm:{ *:[i64] }):$imm), sub_eq:{ *:[i32] })) |
| 16886 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 16887 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16888 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPDI), |
| 16889 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16890 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 16891 | GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/1, // imm |
| 16892 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16893 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16894 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 16895 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 16896 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16897 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 16898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 16899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16900 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16901 | GIR_RootConstrainSelectedInstOperands, |
| 16902 | // GIR_Coverage, 3884, |
| 16903 | GIR_EraseRootFromParent_Done, |
| 16904 | // Label 1144: @41882 |
| 16905 | GIM_Reject, |
| 16906 | // Label 1141: @41883 |
| 16907 | GIM_Reject, |
| 16908 | // Label 1136: @41884 |
| 16909 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 1148*/ GIMT_Encode4(42899), |
| 16910 | /*GILLT_s1*//*Label 1145*/ GIMT_Encode4(41907), |
| 16911 | /*GILLT_s32*//*Label 1146*/ GIMT_Encode4(42131), |
| 16912 | /*GILLT_s64*//*Label 1147*/ GIMT_Encode4(42515), |
| 16913 | // Label 1145: @41907 |
| 16914 | GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(42130), |
| 16915 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s1, |
| 16916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 16917 | GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(41940), // Rule ID 3626 // |
| 16918 | // MIs[0] Operand 1 |
| 16919 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 16920 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETLT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2) |
| 16921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), |
| 16922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16923 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16924 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16925 | GIR_RootConstrainSelectedInstOperands, |
| 16926 | // GIR_Coverage, 3626, |
| 16927 | GIR_EraseRootFromParent_Done, |
| 16928 | // Label 1150: @41940 |
| 16929 | GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(41961), // Rule ID 3627 // |
| 16930 | // MIs[0] Operand 1 |
| 16931 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 16932 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETULT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1) |
| 16933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), |
| 16934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16935 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16936 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16937 | GIR_RootConstrainSelectedInstOperands, |
| 16938 | // GIR_Coverage, 3627, |
| 16939 | GIR_EraseRootFromParent_Done, |
| 16940 | // Label 1151: @41961 |
| 16941 | GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(41982), // Rule ID 3628 // |
| 16942 | // MIs[0] Operand 1 |
| 16943 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 16944 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETLE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2) |
| 16945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), |
| 16946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16947 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16948 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16949 | GIR_RootConstrainSelectedInstOperands, |
| 16950 | // GIR_Coverage, 3628, |
| 16951 | GIR_EraseRootFromParent_Done, |
| 16952 | // Label 1152: @41982 |
| 16953 | GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(42003), // Rule ID 3629 // |
| 16954 | // MIs[0] Operand 1 |
| 16955 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 16956 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETULE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1) |
| 16957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), |
| 16958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16959 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16960 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16961 | GIR_RootConstrainSelectedInstOperands, |
| 16962 | // GIR_Coverage, 3629, |
| 16963 | GIR_EraseRootFromParent_Done, |
| 16964 | // Label 1153: @42003 |
| 16965 | GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(42024), // Rule ID 3630 // |
| 16966 | // MIs[0] Operand 1 |
| 16967 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 16968 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETEQ:{ *:[Other] }) => (CREQV:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2) |
| 16969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CREQV), |
| 16970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16971 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16972 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16973 | GIR_RootConstrainSelectedInstOperands, |
| 16974 | // GIR_Coverage, 3630, |
| 16975 | GIR_EraseRootFromParent_Done, |
| 16976 | // Label 1154: @42024 |
| 16977 | GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(42045), // Rule ID 3631 // |
| 16978 | // MIs[0] Operand 1 |
| 16979 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 16980 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETGE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1) |
| 16981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), |
| 16982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16983 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16984 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16985 | GIR_RootConstrainSelectedInstOperands, |
| 16986 | // GIR_Coverage, 3631, |
| 16987 | GIR_EraseRootFromParent_Done, |
| 16988 | // Label 1155: @42045 |
| 16989 | GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(42066), // Rule ID 3632 // |
| 16990 | // MIs[0] Operand 1 |
| 16991 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 16992 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETUGE:{ *:[Other] }) => (CRORC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2) |
| 16993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRORC), |
| 16994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 16995 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 16996 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 16997 | GIR_RootConstrainSelectedInstOperands, |
| 16998 | // GIR_Coverage, 3632, |
| 16999 | GIR_EraseRootFromParent_Done, |
| 17000 | // Label 1156: @42066 |
| 17001 | GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(42087), // Rule ID 3633 // |
| 17002 | // MIs[0] Operand 1 |
| 17003 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 17004 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETGT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s2, ?:{ *:[i1] }:$s1) |
| 17005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), |
| 17006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17007 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 17008 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 17009 | GIR_RootConstrainSelectedInstOperands, |
| 17010 | // GIR_Coverage, 3633, |
| 17011 | GIR_EraseRootFromParent_Done, |
| 17012 | // Label 1157: @42087 |
| 17013 | GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(42108), // Rule ID 3634 // |
| 17014 | // MIs[0] Operand 1 |
| 17015 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 17016 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETUGT:{ *:[Other] }) => (CRANDC:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2) |
| 17017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRANDC), |
| 17018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17019 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 17020 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 17021 | GIR_RootConstrainSelectedInstOperands, |
| 17022 | // GIR_Coverage, 3634, |
| 17023 | GIR_EraseRootFromParent_Done, |
| 17024 | // Label 1158: @42108 |
| 17025 | GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(42129), // Rule ID 3635 // |
| 17026 | // MIs[0] Operand 1 |
| 17027 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 17028 | // (setcc:{ *:[i1] } i1:{ *:[i1] }:$s1, i1:{ *:[i1] }:$s2, SETNE:{ *:[Other] }) => (CRXOR:{ *:[i1] } ?:{ *:[i1] }:$s1, ?:{ *:[i1] }:$s2) |
| 17029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRXOR), |
| 17030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17031 | GIR_RootToRootCopy, /*OpIdx*/2, // s1 |
| 17032 | GIR_RootToRootCopy, /*OpIdx*/3, // s2 |
| 17033 | GIR_RootConstrainSelectedInstOperands, |
| 17034 | // GIR_Coverage, 3635, |
| 17035 | GIR_EraseRootFromParent_Done, |
| 17036 | // Label 1159: @42129 |
| 17037 | GIM_Reject, |
| 17038 | // Label 1149: @42130 |
| 17039 | GIM_Reject, |
| 17040 | // Label 1146: @42131 |
| 17041 | GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(42514), |
| 17042 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17044 | GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(42217), // Rule ID 2956 // |
| 17045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17046 | // MIs[0] Operand 1 |
| 17047 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 17048 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })) |
| 17049 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17050 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17051 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW), |
| 17052 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17053 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17054 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17056 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17057 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17058 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17059 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17060 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17063 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17064 | GIR_RootConstrainSelectedInstOperands, |
| 17065 | // GIR_Coverage, 2956, |
| 17066 | GIR_EraseRootFromParent_Done, |
| 17067 | // Label 1161: @42217 |
| 17068 | GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(42291), // Rule ID 2970 // |
| 17069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17070 | // MIs[0] Operand 1 |
| 17071 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 17072 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })) |
| 17073 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17074 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17075 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17076 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17077 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17078 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17080 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17081 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17082 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17083 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17084 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17087 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17088 | GIR_RootConstrainSelectedInstOperands, |
| 17089 | // GIR_Coverage, 2970, |
| 17090 | GIR_EraseRootFromParent_Done, |
| 17091 | // Label 1162: @42291 |
| 17092 | GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(42365), // Rule ID 2978 // |
| 17093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17094 | // MIs[0] Operand 1 |
| 17095 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 17096 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })) |
| 17097 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17098 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17099 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW), |
| 17100 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17101 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17102 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17104 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17105 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17106 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17107 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17108 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17111 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17112 | GIR_RootConstrainSelectedInstOperands, |
| 17113 | // GIR_Coverage, 2978, |
| 17114 | GIR_EraseRootFromParent_Done, |
| 17115 | // Label 1163: @42365 |
| 17116 | GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(42439), // Rule ID 2986 // |
| 17117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17118 | // MIs[0] Operand 1 |
| 17119 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 17120 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })) |
| 17121 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17122 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17123 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17124 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17125 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17126 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17130 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17131 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17132 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17134 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17135 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17136 | GIR_RootConstrainSelectedInstOperands, |
| 17137 | // GIR_Coverage, 2986, |
| 17138 | GIR_EraseRootFromParent_Done, |
| 17139 | // Label 1164: @42439 |
| 17140 | GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(42513), // Rule ID 2994 // |
| 17141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17142 | // MIs[0] Operand 1 |
| 17143 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 17144 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] })) |
| 17145 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17146 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17147 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17148 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17149 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17150 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17152 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17153 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17154 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17155 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17156 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17159 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17160 | GIR_RootConstrainSelectedInstOperands, |
| 17161 | // GIR_Coverage, 2994, |
| 17162 | GIR_EraseRootFromParent_Done, |
| 17163 | // Label 1165: @42513 |
| 17164 | GIM_Reject, |
| 17165 | // Label 1160: @42514 |
| 17166 | GIM_Reject, |
| 17167 | // Label 1147: @42515 |
| 17168 | GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(42898), |
| 17169 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 17170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17171 | GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(42601), // Rule ID 3058 // |
| 17172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17173 | // MIs[0] Operand 1 |
| 17174 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 17175 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })) |
| 17176 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17177 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17178 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD), |
| 17179 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17180 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17181 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17182 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17183 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17184 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17185 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17186 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17187 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17190 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17191 | GIR_RootConstrainSelectedInstOperands, |
| 17192 | // GIR_Coverage, 3058, |
| 17193 | GIR_EraseRootFromParent_Done, |
| 17194 | // Label 1167: @42601 |
| 17195 | GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(42675), // Rule ID 3066 // |
| 17196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17197 | // MIs[0] Operand 1 |
| 17198 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 17199 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })) |
| 17200 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17201 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17202 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17203 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17204 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17205 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17206 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17207 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17208 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17209 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17210 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17211 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17214 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17215 | GIR_RootConstrainSelectedInstOperands, |
| 17216 | // GIR_Coverage, 3066, |
| 17217 | GIR_EraseRootFromParent_Done, |
| 17218 | // Label 1168: @42675 |
| 17219 | GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(42749), // Rule ID 3074 // |
| 17220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17221 | // MIs[0] Operand 1 |
| 17222 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 17223 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })) |
| 17224 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17225 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17226 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD), |
| 17227 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17228 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17229 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17233 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17234 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17235 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17239 | GIR_RootConstrainSelectedInstOperands, |
| 17240 | // GIR_Coverage, 3074, |
| 17241 | GIR_EraseRootFromParent_Done, |
| 17242 | // Label 1169: @42749 |
| 17243 | GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(42823), // Rule ID 3082 // |
| 17244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17245 | // MIs[0] Operand 1 |
| 17246 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 17247 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })) |
| 17248 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17249 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17250 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17251 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17252 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17253 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17254 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17255 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17256 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17257 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17258 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17259 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17262 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17263 | GIR_RootConstrainSelectedInstOperands, |
| 17264 | // GIR_Coverage, 3082, |
| 17265 | GIR_EraseRootFromParent_Done, |
| 17266 | // Label 1170: @42823 |
| 17267 | GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(42897), // Rule ID 3090 // |
| 17268 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 17269 | // MIs[0] Operand 1 |
| 17270 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 17271 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] })) |
| 17272 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17273 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17274 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17275 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17276 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17277 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17278 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17281 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17282 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17283 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17286 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17287 | GIR_RootConstrainSelectedInstOperands, |
| 17288 | // GIR_Coverage, 3090, |
| 17289 | GIR_EraseRootFromParent_Done, |
| 17290 | // Label 1171: @42897 |
| 17291 | GIM_Reject, |
| 17292 | // Label 1166: @42898 |
| 17293 | GIM_Reject, |
| 17294 | // Label 1148: @42899 |
| 17295 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1174*/ GIMT_Encode4(43496), |
| 17296 | /*GILLT_s32*//*Label 1172*/ GIMT_Encode4(42918), |
| 17297 | /*GILLT_s64*//*Label 1173*/ GIMT_Encode4(43207), |
| 17298 | // Label 1172: @42918 |
| 17299 | GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(43206), |
| 17300 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 17302 | GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(42985), // Rule ID 3747 // |
| 17303 | // MIs[0] Operand 1 |
| 17304 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 17305 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }) |
| 17306 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17307 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW), |
| 17308 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17309 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17310 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17311 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17314 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17315 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17316 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17317 | // GIR_Coverage, 3747, |
| 17318 | GIR_EraseRootFromParent_Done, |
| 17319 | // Label 1176: @42985 |
| 17320 | GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(43040), // Rule ID 3748 // |
| 17321 | // MIs[0] Operand 1 |
| 17322 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 17323 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] }) |
| 17324 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17325 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17326 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17327 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17328 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17332 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17333 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17334 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17335 | // GIR_Coverage, 3748, |
| 17336 | GIR_EraseRootFromParent_Done, |
| 17337 | // Label 1177: @43040 |
| 17338 | GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(43095), // Rule ID 3749 // |
| 17339 | // MIs[0] Operand 1 |
| 17340 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 17341 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }) |
| 17342 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17343 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLW), |
| 17344 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17345 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17346 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17350 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17351 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17352 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17353 | // GIR_Coverage, 3749, |
| 17354 | GIR_EraseRootFromParent_Done, |
| 17355 | // Label 1178: @43095 |
| 17356 | GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(43150), // Rule ID 3750 // |
| 17357 | // MIs[0] Operand 1 |
| 17358 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 17359 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] }) |
| 17360 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17361 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17362 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17363 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17364 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17368 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17369 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17370 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17371 | // GIR_Coverage, 3750, |
| 17372 | GIR_EraseRootFromParent_Done, |
| 17373 | // Label 1179: @43150 |
| 17374 | GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(43205), // Rule ID 3751 // |
| 17375 | // MIs[0] Operand 1 |
| 17376 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 17377 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] }) |
| 17378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17379 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17380 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17381 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17382 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17386 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17387 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17388 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17389 | // GIR_Coverage, 3751, |
| 17390 | GIR_EraseRootFromParent_Done, |
| 17391 | // Label 1180: @43205 |
| 17392 | GIM_Reject, |
| 17393 | // Label 1175: @43206 |
| 17394 | GIM_Reject, |
| 17395 | // Label 1173: @43207 |
| 17396 | GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(43495), |
| 17397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 17398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 17399 | GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(43274), // Rule ID 3759 // |
| 17400 | // MIs[0] Operand 1 |
| 17401 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 17402 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }) |
| 17403 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17404 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD), |
| 17405 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17406 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17407 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17411 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17412 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17413 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17414 | // GIR_Coverage, 3759, |
| 17415 | GIR_EraseRootFromParent_Done, |
| 17416 | // Label 1182: @43274 |
| 17417 | GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(43329), // Rule ID 3760 // |
| 17418 | // MIs[0] Operand 1 |
| 17419 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 17420 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] }) |
| 17421 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17422 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17423 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17424 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17425 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17426 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17429 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17430 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17431 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17432 | // GIR_Coverage, 3760, |
| 17433 | GIR_EraseRootFromParent_Done, |
| 17434 | // Label 1183: @43329 |
| 17435 | GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(43384), // Rule ID 3761 // |
| 17436 | // MIs[0] Operand 1 |
| 17437 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 17438 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }) |
| 17439 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPLD), |
| 17441 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17442 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17443 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17444 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17447 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17448 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17449 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17450 | // GIR_Coverage, 3761, |
| 17451 | GIR_EraseRootFromParent_Done, |
| 17452 | // Label 1184: @43384 |
| 17453 | GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(43439), // Rule ID 3762 // |
| 17454 | // MIs[0] Operand 1 |
| 17455 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 17456 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] }) |
| 17457 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17458 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17459 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17460 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17461 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17465 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17466 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17467 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17468 | // GIR_Coverage, 3762, |
| 17469 | GIR_EraseRootFromParent_Done, |
| 17470 | // Label 1185: @43439 |
| 17471 | GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(43494), // Rule ID 3763 // |
| 17472 | // MIs[0] Operand 1 |
| 17473 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 17474 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] }) |
| 17475 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17476 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17477 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17478 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17479 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 17483 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17484 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17485 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17486 | // GIR_Coverage, 3763, |
| 17487 | GIR_EraseRootFromParent_Done, |
| 17488 | // Label 1186: @43494 |
| 17489 | GIM_Reject, |
| 17490 | // Label 1181: @43495 |
| 17491 | GIM_Reject, |
| 17492 | // Label 1174: @43496 |
| 17493 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1189*/ GIMT_Encode4(44283), |
| 17494 | /*GILLT_s32*//*Label 1187*/ GIMT_Encode4(43515), |
| 17495 | /*GILLT_s64*//*Label 1188*/ GIMT_Encode4(43899), |
| 17496 | // Label 1187: @43515 |
| 17497 | GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(43898), |
| 17498 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17500 | GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(43601), // Rule ID 3812 // |
| 17501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17502 | // MIs[0] Operand 1 |
| 17503 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 17504 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })) |
| 17505 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17506 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17507 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW), |
| 17508 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17509 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17510 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17512 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17513 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17514 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17515 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17516 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17519 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17520 | GIR_RootConstrainSelectedInstOperands, |
| 17521 | // GIR_Coverage, 3812, |
| 17522 | GIR_EraseRootFromParent_Done, |
| 17523 | // Label 1191: @43601 |
| 17524 | GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(43675), // Rule ID 3820 // |
| 17525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17526 | // MIs[0] Operand 1 |
| 17527 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 17528 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_lt:{ *:[i32] })) |
| 17529 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17530 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17531 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17532 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17533 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17534 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17536 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17537 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17538 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17539 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17540 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17543 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17544 | GIR_RootConstrainSelectedInstOperands, |
| 17545 | // GIR_Coverage, 3820, |
| 17546 | GIR_EraseRootFromParent_Done, |
| 17547 | // Label 1192: @43675 |
| 17548 | GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(43749), // Rule ID 3828 // |
| 17549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17550 | // MIs[0] Operand 1 |
| 17551 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 17552 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })) |
| 17553 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17554 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17555 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLW), |
| 17556 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17557 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17558 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17559 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17560 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17561 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17562 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17563 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17564 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17567 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17568 | GIR_RootConstrainSelectedInstOperands, |
| 17569 | // GIR_Coverage, 3828, |
| 17570 | GIR_EraseRootFromParent_Done, |
| 17571 | // Label 1193: @43749 |
| 17572 | GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(43823), // Rule ID 3836 // |
| 17573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17574 | // MIs[0] Operand 1 |
| 17575 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 17576 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_gt:{ *:[i32] })) |
| 17577 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17578 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17579 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17580 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17581 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17582 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17584 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17585 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17586 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17587 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17588 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17591 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17592 | GIR_RootConstrainSelectedInstOperands, |
| 17593 | // GIR_Coverage, 3836, |
| 17594 | GIR_EraseRootFromParent_Done, |
| 17595 | // Label 1194: @43823 |
| 17596 | GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(43897), // Rule ID 3844 // |
| 17597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17598 | // MIs[0] Operand 1 |
| 17599 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 17600 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$s1, i32:{ *:[i32] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPW:{ *:[i32] } ?:{ *:[i32] }:$s1, ?:{ *:[i32] }:$s2), sub_eq:{ *:[i32] })) |
| 17601 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17602 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17603 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPW), |
| 17604 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17605 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17606 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17610 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17611 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17612 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17616 | GIR_RootConstrainSelectedInstOperands, |
| 17617 | // GIR_Coverage, 3844, |
| 17618 | GIR_EraseRootFromParent_Done, |
| 17619 | // Label 1195: @43897 |
| 17620 | GIM_Reject, |
| 17621 | // Label 1190: @43898 |
| 17622 | GIM_Reject, |
| 17623 | // Label 1188: @43899 |
| 17624 | GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(44282), |
| 17625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 17626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17627 | GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(43985), // Rule ID 3908 // |
| 17628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17629 | // MIs[0] Operand 1 |
| 17630 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 17631 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })) |
| 17632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17633 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17634 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD), |
| 17635 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17636 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17637 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17638 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17641 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17642 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17643 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17647 | GIR_RootConstrainSelectedInstOperands, |
| 17648 | // GIR_Coverage, 3908, |
| 17649 | GIR_EraseRootFromParent_Done, |
| 17650 | // Label 1197: @43985 |
| 17651 | GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(44059), // Rule ID 3916 // |
| 17652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17653 | // MIs[0] Operand 1 |
| 17654 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 17655 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_lt:{ *:[i32] })) |
| 17656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17657 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17658 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17659 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17660 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17661 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17662 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17663 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17664 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17665 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17667 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17671 | GIR_RootConstrainSelectedInstOperands, |
| 17672 | // GIR_Coverage, 3916, |
| 17673 | GIR_EraseRootFromParent_Done, |
| 17674 | // Label 1198: @44059 |
| 17675 | GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(44133), // Rule ID 3924 // |
| 17676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17677 | // MIs[0] Operand 1 |
| 17678 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 17679 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPLD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })) |
| 17680 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17681 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17682 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPLD), |
| 17683 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17684 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17685 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17687 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17689 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17690 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17691 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17694 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17695 | GIR_RootConstrainSelectedInstOperands, |
| 17696 | // GIR_Coverage, 3924, |
| 17697 | GIR_EraseRootFromParent_Done, |
| 17698 | // Label 1199: @44133 |
| 17699 | GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(44207), // Rule ID 3932 // |
| 17700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17701 | // MIs[0] Operand 1 |
| 17702 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 17703 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETLE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_gt:{ *:[i32] })) |
| 17704 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17705 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17706 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17707 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17708 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17709 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17711 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17712 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17713 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17714 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17715 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17718 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17719 | GIR_RootConstrainSelectedInstOperands, |
| 17720 | // GIR_Coverage, 3932, |
| 17721 | GIR_EraseRootFromParent_Done, |
| 17722 | // Label 1200: @44207 |
| 17723 | GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(44281), // Rule ID 3940 // |
| 17724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotISA3_1), |
| 17725 | // MIs[0] Operand 1 |
| 17726 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 17727 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$s1, i64:{ *:[i64] }:$s2, SETNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (CMPD:{ *:[i32] } ?:{ *:[i64] }:$s1, ?:{ *:[i64] }:$s2), sub_eq:{ *:[i32] })) |
| 17728 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17729 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17730 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CMPD), |
| 17731 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17732 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17733 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17735 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17736 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17737 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17738 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17739 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17742 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17743 | GIR_RootConstrainSelectedInstOperands, |
| 17744 | // GIR_Coverage, 3940, |
| 17745 | GIR_EraseRootFromParent_Done, |
| 17746 | // Label 1201: @44281 |
| 17747 | GIM_Reject, |
| 17748 | // Label 1196: @44282 |
| 17749 | GIM_Reject, |
| 17750 | // Label 1189: @44283 |
| 17751 | GIM_Reject, |
| 17752 | // Label 1111: @44284 |
| 17753 | GIM_Reject, |
| 17754 | // Label 31: @44285 |
| 17755 | GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(47859), |
| 17756 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 17757 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 1206*/ GIMT_Encode4(45246), |
| 17758 | /*GILLT_s32*//*Label 1203*/ GIMT_Encode4(44316), |
| 17759 | /*GILLT_s64*//*Label 1204*/ GIMT_Encode4(44626), |
| 17760 | /*GILLT_s128*//*Label 1205*/ GIMT_Encode4(44936), |
| 17761 | // Label 1203: @44316 |
| 17762 | GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(44625), |
| 17763 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17765 | GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(44402), // Rule ID 3154 // |
| 17766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17767 | // MIs[0] Operand 1 |
| 17768 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 17769 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] })) |
| 17770 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17771 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17772 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 17773 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17774 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17775 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17777 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17778 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17779 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17780 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17781 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17784 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17785 | GIR_RootConstrainSelectedInstOperands, |
| 17786 | // GIR_Coverage, 3154, |
| 17787 | GIR_EraseRootFromParent_Done, |
| 17788 | // Label 1208: @44402 |
| 17789 | GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(44476), // Rule ID 3170 // |
| 17790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17791 | // MIs[0] Operand 1 |
| 17792 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 17793 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })) |
| 17794 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17795 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17796 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 17797 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17798 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17799 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17800 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17801 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17802 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17803 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17804 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17805 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17808 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17809 | GIR_RootConstrainSelectedInstOperands, |
| 17810 | // GIR_Coverage, 3170, |
| 17811 | GIR_EraseRootFromParent_Done, |
| 17812 | // Label 1209: @44476 |
| 17813 | GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(44550), // Rule ID 3186 // |
| 17814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17815 | // MIs[0] Operand 1 |
| 17816 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 17817 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] })) |
| 17818 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17819 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17820 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 17821 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17822 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17823 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17824 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17825 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17826 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17827 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17828 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17829 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17832 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17833 | GIR_RootConstrainSelectedInstOperands, |
| 17834 | // GIR_Coverage, 3186, |
| 17835 | GIR_EraseRootFromParent_Done, |
| 17836 | // Label 1210: @44550 |
| 17837 | GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(44624), // Rule ID 3202 // |
| 17838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17839 | // MIs[0] Operand 1 |
| 17840 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 17841 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] })) |
| 17842 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17843 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17844 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 17845 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17846 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17847 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17848 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17851 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 17852 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17853 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17856 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17857 | GIR_RootConstrainSelectedInstOperands, |
| 17858 | // GIR_Coverage, 3202, |
| 17859 | GIR_EraseRootFromParent_Done, |
| 17860 | // Label 1211: @44624 |
| 17861 | GIM_Reject, |
| 17862 | // Label 1207: @44625 |
| 17863 | GIM_Reject, |
| 17864 | // Label 1204: @44626 |
| 17865 | GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(44935), |
| 17866 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 17867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17868 | GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(44712), // Rule ID 3210 // |
| 17869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17870 | // MIs[0] Operand 1 |
| 17871 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 17872 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] })) |
| 17873 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17874 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17875 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 17876 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17877 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17878 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17881 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17882 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17883 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17884 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17887 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17888 | GIR_RootConstrainSelectedInstOperands, |
| 17889 | // GIR_Coverage, 3210, |
| 17890 | GIR_EraseRootFromParent_Done, |
| 17891 | // Label 1213: @44712 |
| 17892 | GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(44786), // Rule ID 3226 // |
| 17893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17894 | // MIs[0] Operand 1 |
| 17895 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 17896 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })) |
| 17897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17898 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17899 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 17900 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17901 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17902 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17906 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 17907 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17908 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17912 | GIR_RootConstrainSelectedInstOperands, |
| 17913 | // GIR_Coverage, 3226, |
| 17914 | GIR_EraseRootFromParent_Done, |
| 17915 | // Label 1214: @44786 |
| 17916 | GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(44860), // Rule ID 3242 // |
| 17917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17918 | // MIs[0] Operand 1 |
| 17919 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 17920 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] })) |
| 17921 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17922 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17923 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 17924 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17925 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17926 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17928 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17929 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17930 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 17931 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17932 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17935 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17936 | GIR_RootConstrainSelectedInstOperands, |
| 17937 | // GIR_Coverage, 3242, |
| 17938 | GIR_EraseRootFromParent_Done, |
| 17939 | // Label 1215: @44860 |
| 17940 | GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(44934), // Rule ID 3258 // |
| 17941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17942 | // MIs[0] Operand 1 |
| 17943 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 17944 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] })) |
| 17945 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17946 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17947 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 17948 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17949 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17950 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17953 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17954 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 17955 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17956 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17960 | GIR_RootConstrainSelectedInstOperands, |
| 17961 | // GIR_Coverage, 3258, |
| 17962 | GIR_EraseRootFromParent_Done, |
| 17963 | // Label 1216: @44934 |
| 17964 | GIM_Reject, |
| 17965 | // Label 1212: @44935 |
| 17966 | GIM_Reject, |
| 17967 | // Label 1205: @44936 |
| 17968 | GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(45245), |
| 17969 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 17970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17971 | GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(45022), // Rule ID 3266 // |
| 17972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17973 | // MIs[0] Operand 1 |
| 17974 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 17975 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] })) |
| 17976 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 17977 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 17978 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 17979 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17980 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 17981 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 17982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 17983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 17984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 17985 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 17986 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 17987 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 17988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 17989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 17990 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17991 | GIR_RootConstrainSelectedInstOperands, |
| 17992 | // GIR_Coverage, 3266, |
| 17993 | GIR_EraseRootFromParent_Done, |
| 17994 | // Label 1218: @45022 |
| 17995 | GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(45096), // Rule ID 3282 // |
| 17996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 17997 | // MIs[0] Operand 1 |
| 17998 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 17999 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] })) |
| 18000 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18001 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18002 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18003 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18004 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18005 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18006 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18007 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18008 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18009 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18010 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18011 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18014 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18015 | GIR_RootConstrainSelectedInstOperands, |
| 18016 | // GIR_Coverage, 3282, |
| 18017 | GIR_EraseRootFromParent_Done, |
| 18018 | // Label 1219: @45096 |
| 18019 | GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(45170), // Rule ID 3298 // |
| 18020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 18021 | // MIs[0] Operand 1 |
| 18022 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 18023 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] })) |
| 18024 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18025 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18026 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18027 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18028 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18029 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18030 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18031 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18032 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18033 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18034 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18035 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18038 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18039 | GIR_RootConstrainSelectedInstOperands, |
| 18040 | // GIR_Coverage, 3298, |
| 18041 | GIR_EraseRootFromParent_Done, |
| 18042 | // Label 1220: @45170 |
| 18043 | GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(45244), // Rule ID 3314 // |
| 18044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU_IsISA3_1), |
| 18045 | // MIs[0] Operand 1 |
| 18046 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 18047 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] })) |
| 18048 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18049 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18050 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18051 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18052 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18053 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18057 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18058 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18059 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18063 | GIR_RootConstrainSelectedInstOperands, |
| 18064 | // GIR_Coverage, 3314, |
| 18065 | GIR_EraseRootFromParent_Done, |
| 18066 | // Label 1221: @45244 |
| 18067 | GIM_Reject, |
| 18068 | // Label 1217: @45245 |
| 18069 | GIM_Reject, |
| 18070 | // Label 1206: @45246 |
| 18071 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 1225*/ GIMT_Encode4(46979), |
| 18072 | /*GILLT_s32*//*Label 1222*/ GIMT_Encode4(45269), |
| 18073 | /*GILLT_s64*//*Label 1223*/ GIMT_Encode4(45839), |
| 18074 | /*GILLT_s128*//*Label 1224*/ GIMT_Encode4(46409), |
| 18075 | // Label 1222: @45269 |
| 18076 | GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(45838), |
| 18077 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18078 | GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(45339), // Rule ID 3949 // |
| 18079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18081 | // MIs[0] Operand 1 |
| 18082 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 18083 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] }) |
| 18084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18085 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18086 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18087 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18088 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18092 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 18093 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18094 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18095 | // GIR_Coverage, 3949, |
| 18096 | GIR_EraseRootFromParent_Done, |
| 18097 | // Label 1227: @45339 |
| 18098 | GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(45401), // Rule ID 3953 // |
| 18099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18101 | // MIs[0] Operand 1 |
| 18102 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 18103 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }) |
| 18104 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18105 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18106 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18107 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18108 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18112 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18113 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18114 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18115 | // GIR_Coverage, 3953, |
| 18116 | GIR_EraseRootFromParent_Done, |
| 18117 | // Label 1228: @45401 |
| 18118 | GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(45463), // Rule ID 3957 // |
| 18119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18121 | // MIs[0] Operand 1 |
| 18122 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 18123 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] }) |
| 18124 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18125 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18126 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18127 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18128 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18129 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18132 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18133 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18134 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18135 | // GIR_Coverage, 3957, |
| 18136 | GIR_EraseRootFromParent_Done, |
| 18137 | // Label 1229: @45463 |
| 18138 | GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(45525), // Rule ID 3961 // |
| 18139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18141 | // MIs[0] Operand 1 |
| 18142 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 18143 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] }) |
| 18144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18145 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18146 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18147 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18148 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18149 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18152 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18153 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18154 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18155 | // GIR_Coverage, 3961, |
| 18156 | GIR_EraseRootFromParent_Done, |
| 18157 | // Label 1230: @45525 |
| 18158 | GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(45603), // Rule ID 3963 // |
| 18159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18161 | // MIs[0] Operand 1 |
| 18162 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 18163 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_lt:{ *:[i32] })) |
| 18164 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18165 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18166 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18167 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18168 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18169 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18170 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18171 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18172 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18173 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 18174 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18175 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18179 | GIR_RootConstrainSelectedInstOperands, |
| 18180 | // GIR_Coverage, 3963, |
| 18181 | GIR_EraseRootFromParent_Done, |
| 18182 | // Label 1231: @45603 |
| 18183 | GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(45681), // Rule ID 3995 // |
| 18184 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18186 | // MIs[0] Operand 1 |
| 18187 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 18188 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })) |
| 18189 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18190 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18191 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18192 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18193 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18194 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18196 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18197 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18198 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18199 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18200 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18203 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18204 | GIR_RootConstrainSelectedInstOperands, |
| 18205 | // GIR_Coverage, 3995, |
| 18206 | GIR_EraseRootFromParent_Done, |
| 18207 | // Label 1232: @45681 |
| 18208 | GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(45759), // Rule ID 4027 // |
| 18209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18211 | // MIs[0] Operand 1 |
| 18212 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 18213 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_eq:{ *:[i32] })) |
| 18214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18215 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18216 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18217 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18218 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18219 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18220 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18221 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18222 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18223 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18224 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18225 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18228 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18229 | GIR_RootConstrainSelectedInstOperands, |
| 18230 | // GIR_Coverage, 4027, |
| 18231 | GIR_EraseRootFromParent_Done, |
| 18232 | // Label 1233: @45759 |
| 18233 | GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(45837), // Rule ID 4059 // |
| 18234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18236 | // MIs[0] Operand 1 |
| 18237 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 18238 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUS:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_un:{ *:[i32] })) |
| 18239 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18240 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18241 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUS), |
| 18242 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18243 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18244 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18246 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18247 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18248 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18249 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18250 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18253 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18254 | GIR_RootConstrainSelectedInstOperands, |
| 18255 | // GIR_Coverage, 4059, |
| 18256 | GIR_EraseRootFromParent_Done, |
| 18257 | // Label 1234: @45837 |
| 18258 | GIM_Reject, |
| 18259 | // Label 1226: @45838 |
| 18260 | GIM_Reject, |
| 18261 | // Label 1223: @45839 |
| 18262 | GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(46408), |
| 18263 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 18264 | GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(45925), // Rule ID 4075 // |
| 18265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18267 | // MIs[0] Operand 1 |
| 18268 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 18269 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] })) |
| 18270 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18271 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18272 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18273 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18274 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18275 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18277 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18278 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18279 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 18280 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18281 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18285 | GIR_RootConstrainSelectedInstOperands, |
| 18286 | // GIR_Coverage, 4075, |
| 18287 | GIR_EraseRootFromParent_Done, |
| 18288 | // Label 1236: @45925 |
| 18289 | GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(46003), // Rule ID 4107 // |
| 18290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18292 | // MIs[0] Operand 1 |
| 18293 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 18294 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })) |
| 18295 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18296 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18297 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18298 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18299 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18300 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18302 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18303 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18304 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18305 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18306 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18310 | GIR_RootConstrainSelectedInstOperands, |
| 18311 | // GIR_Coverage, 4107, |
| 18312 | GIR_EraseRootFromParent_Done, |
| 18313 | // Label 1237: @46003 |
| 18314 | GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(46081), // Rule ID 4139 // |
| 18315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18317 | // MIs[0] Operand 1 |
| 18318 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 18319 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] })) |
| 18320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18321 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18322 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18323 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18324 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18325 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18326 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18329 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18330 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18331 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18334 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18335 | GIR_RootConstrainSelectedInstOperands, |
| 18336 | // GIR_Coverage, 4139, |
| 18337 | GIR_EraseRootFromParent_Done, |
| 18338 | // Label 1238: @46081 |
| 18339 | GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(46159), // Rule ID 4171 // |
| 18340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18342 | // MIs[0] Operand 1 |
| 18343 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 18344 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] })) |
| 18345 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18346 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18347 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18348 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18349 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18350 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18351 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18352 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18353 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18354 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18355 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18356 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18359 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18360 | GIR_RootConstrainSelectedInstOperands, |
| 18361 | // GIR_Coverage, 4171, |
| 18362 | GIR_EraseRootFromParent_Done, |
| 18363 | // Label 1239: @46159 |
| 18364 | GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(46221), // Rule ID 4187 // |
| 18365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18367 | // MIs[0] Operand 1 |
| 18368 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 18369 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_lt:{ *:[i32] }) |
| 18370 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18371 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18372 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18373 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18374 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18378 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 18379 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18380 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18381 | // GIR_Coverage, 4187, |
| 18382 | GIR_EraseRootFromParent_Done, |
| 18383 | // Label 1240: @46221 |
| 18384 | GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(46283), // Rule ID 4191 // |
| 18385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18387 | // MIs[0] Operand 1 |
| 18388 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 18389 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }) |
| 18390 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18391 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18392 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18393 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18394 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18395 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18398 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18399 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18400 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18401 | // GIR_Coverage, 4191, |
| 18402 | GIR_EraseRootFromParent_Done, |
| 18403 | // Label 1241: @46283 |
| 18404 | GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(46345), // Rule ID 4195 // |
| 18405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18407 | // MIs[0] Operand 1 |
| 18408 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 18409 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_eq:{ *:[i32] }) |
| 18410 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18411 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18412 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18413 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18414 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18415 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18418 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18419 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18420 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18421 | // GIR_Coverage, 4195, |
| 18422 | GIR_EraseRootFromParent_Done, |
| 18423 | // Label 1242: @46345 |
| 18424 | GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(46407), // Rule ID 4199 // |
| 18425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18427 | // MIs[0] Operand 1 |
| 18428 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 18429 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (FCMPUD:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_un:{ *:[i32] }) |
| 18430 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18431 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCMPUD), |
| 18432 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18433 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18434 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18438 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18439 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18440 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18441 | // GIR_Coverage, 4199, |
| 18442 | GIR_EraseRootFromParent_Done, |
| 18443 | // Label 1243: @46407 |
| 18444 | GIM_Reject, |
| 18445 | // Label 1235: @46408 |
| 18446 | GIM_Reject, |
| 18447 | // Label 1224: @46409 |
| 18448 | GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(46978), |
| 18449 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 18450 | GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(46495), // Rule ID 4201 // |
| 18451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18453 | // MIs[0] Operand 1 |
| 18454 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 18455 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] })) |
| 18456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18457 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18458 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18459 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18460 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18461 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18464 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18465 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 18466 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18467 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18470 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18471 | GIR_RootConstrainSelectedInstOperands, |
| 18472 | // GIR_Coverage, 4201, |
| 18473 | GIR_EraseRootFromParent_Done, |
| 18474 | // Label 1245: @46495 |
| 18475 | GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(46573), // Rule ID 4233 // |
| 18476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18478 | // MIs[0] Operand 1 |
| 18479 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 18480 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] })) |
| 18481 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18482 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18483 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18484 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18485 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18486 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18488 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18489 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18490 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18491 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18492 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18495 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18496 | GIR_RootConstrainSelectedInstOperands, |
| 18497 | // GIR_Coverage, 4233, |
| 18498 | GIR_EraseRootFromParent_Done, |
| 18499 | // Label 1246: @46573 |
| 18500 | GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(46651), // Rule ID 4265 // |
| 18501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18503 | // MIs[0] Operand 1 |
| 18504 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 18505 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] })) |
| 18506 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18507 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18508 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18509 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18510 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18511 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18515 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18516 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18517 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18520 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18521 | GIR_RootConstrainSelectedInstOperands, |
| 18522 | // GIR_Coverage, 4265, |
| 18523 | GIR_EraseRootFromParent_Done, |
| 18524 | // Label 1247: @46651 |
| 18525 | GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(46729), // Rule ID 4297 // |
| 18526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18528 | // MIs[0] Operand 1 |
| 18529 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 18530 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETO:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] })) |
| 18531 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18532 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18533 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18534 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18535 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18536 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18537 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18538 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18539 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18540 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18541 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18542 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18545 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18546 | GIR_RootConstrainSelectedInstOperands, |
| 18547 | // GIR_Coverage, 4297, |
| 18548 | GIR_EraseRootFromParent_Done, |
| 18549 | // Label 1248: @46729 |
| 18550 | GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(46791), // Rule ID 4313 // |
| 18551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18553 | // MIs[0] Operand 1 |
| 18554 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 18555 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_lt:{ *:[i32] }) |
| 18556 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18557 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18559 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18560 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18561 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18564 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_lt), |
| 18565 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18566 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18567 | // GIR_Coverage, 4313, |
| 18568 | GIR_EraseRootFromParent_Done, |
| 18569 | // Label 1249: @46791 |
| 18570 | GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(46853), // Rule ID 4317 // |
| 18571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18573 | // MIs[0] Operand 1 |
| 18574 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 18575 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_gt:{ *:[i32] }) |
| 18576 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18579 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18580 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18584 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18585 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18586 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18587 | // GIR_Coverage, 4317, |
| 18588 | GIR_EraseRootFromParent_Done, |
| 18589 | // Label 1250: @46853 |
| 18590 | GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(46915), // Rule ID 4321 // |
| 18591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18593 | // MIs[0] Operand 1 |
| 18594 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 18595 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_eq:{ *:[i32] }) |
| 18596 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18597 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18598 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18599 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18600 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18601 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18604 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_eq), |
| 18605 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18606 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18607 | // GIR_Coverage, 4321, |
| 18608 | GIR_EraseRootFromParent_Done, |
| 18609 | // Label 1251: @46915 |
| 18610 | GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(46977), // Rule ID 4325 // |
| 18611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18613 | // MIs[0] Operand 1 |
| 18614 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 18615 | // (setcc:{ *:[i1] } f128:{ *:[f128] }:$s1, f128:{ *:[f128] }:$s2, SETUO:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (XSCMPUQP:{ *:[i32] } ?:{ *:[f128] }:$s1, ?:{ *:[f128] }:$s2), sub_un:{ *:[i32] }) |
| 18616 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18617 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCMPUQP), |
| 18618 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18619 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18620 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18624 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_un), |
| 18625 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18626 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18627 | // GIR_Coverage, 4325, |
| 18628 | GIR_EraseRootFromParent_Done, |
| 18629 | // Label 1252: @46977 |
| 18630 | GIM_Reject, |
| 18631 | // Label 1244: @46978 |
| 18632 | GIM_Reject, |
| 18633 | // Label 1225: @46979 |
| 18634 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1255*/ GIMT_Encode4(47858), |
| 18635 | /*GILLT_s32*//*Label 1253*/ GIMT_Encode4(46998), |
| 18636 | /*GILLT_s64*//*Label 1254*/ GIMT_Encode4(47428), |
| 18637 | // Label 1253: @46998 |
| 18638 | GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(47427), |
| 18639 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18640 | GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(47068), // Rule ID 4516 // |
| 18641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18643 | // MIs[0] Operand 1 |
| 18644 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 18645 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }) |
| 18646 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18647 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT), |
| 18648 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18649 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18650 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18651 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18654 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18655 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18656 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18657 | // GIR_Coverage, 4516, |
| 18658 | GIR_EraseRootFromParent_Done, |
| 18659 | // Label 1257: @47068 |
| 18660 | GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(47130), // Rule ID 4520 // |
| 18661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18663 | // MIs[0] Operand 1 |
| 18664 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 18665 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }) |
| 18666 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18667 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT), |
| 18668 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18669 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18670 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18671 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18674 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18675 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18676 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18677 | // GIR_Coverage, 4520, |
| 18678 | GIR_EraseRootFromParent_Done, |
| 18679 | // Label 1258: @47130 |
| 18680 | GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(47192), // Rule ID 4524 // |
| 18681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18683 | // MIs[0] Operand 1 |
| 18684 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 18685 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] }) |
| 18686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18687 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ), |
| 18688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18689 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18690 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18694 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18695 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18696 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18697 | // GIR_Coverage, 4524, |
| 18698 | GIR_EraseRootFromParent_Done, |
| 18699 | // Label 1259: @47192 |
| 18700 | GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(47270), // Rule ID 4528 // |
| 18701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18703 | // MIs[0] Operand 1 |
| 18704 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 18705 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPLT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })) |
| 18706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18707 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18708 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPLT), |
| 18709 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18710 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18711 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18713 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18714 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18715 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18716 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18717 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18721 | GIR_RootConstrainSelectedInstOperands, |
| 18722 | // GIR_Coverage, 4528, |
| 18723 | GIR_EraseRootFromParent_Done, |
| 18724 | // Label 1260: @47270 |
| 18725 | GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(47348), // Rule ID 4560 // |
| 18726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18728 | // MIs[0] Operand 1 |
| 18729 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 18730 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPGT:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })) |
| 18731 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18732 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18733 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPGT), |
| 18734 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18735 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18736 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18738 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18739 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18740 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18741 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18742 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18745 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18746 | GIR_RootConstrainSelectedInstOperands, |
| 18747 | // GIR_Coverage, 4560, |
| 18748 | GIR_EraseRootFromParent_Done, |
| 18749 | // Label 1261: @47348 |
| 18750 | GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(47426), // Rule ID 4592 // |
| 18751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18753 | // MIs[0] Operand 1 |
| 18754 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 18755 | // (setcc:{ *:[i1] } f32:{ *:[f32] }:$s1, f32:{ *:[f32] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFSCMPEQ:{ *:[i32] } ?:{ *:[f32] }:$s1, ?:{ *:[f32] }:$s2), sub_gt:{ *:[i32] })) |
| 18756 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18757 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18758 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFSCMPEQ), |
| 18759 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18760 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18761 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18762 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18763 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18764 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18765 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18766 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18767 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18771 | GIR_RootConstrainSelectedInstOperands, |
| 18772 | // GIR_Coverage, 4592, |
| 18773 | GIR_EraseRootFromParent_Done, |
| 18774 | // Label 1262: @47426 |
| 18775 | GIM_Reject, |
| 18776 | // Label 1256: @47427 |
| 18777 | GIM_Reject, |
| 18778 | // Label 1254: @47428 |
| 18779 | GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(47857), |
| 18780 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 18781 | GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(47498), // Rule ID 4624 // |
| 18782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18784 | // MIs[0] Operand 1 |
| 18785 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 18786 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOLT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }) |
| 18787 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18788 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT), |
| 18789 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18790 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18791 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18792 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18795 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18796 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18797 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18798 | // GIR_Coverage, 4624, |
| 18799 | GIR_EraseRootFromParent_Done, |
| 18800 | // Label 1264: @47498 |
| 18801 | GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(47560), // Rule ID 4628 // |
| 18802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18804 | // MIs[0] Operand 1 |
| 18805 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 18806 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOGT:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }) |
| 18807 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18808 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT), |
| 18809 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18810 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18811 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18812 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18815 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18816 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18817 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18818 | // GIR_Coverage, 4628, |
| 18819 | GIR_EraseRootFromParent_Done, |
| 18820 | // Label 1265: @47560 |
| 18821 | GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(47622), // Rule ID 4632 // |
| 18822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRRCRegClassID), |
| 18824 | // MIs[0] Operand 1 |
| 18825 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 18826 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETOEQ:{ *:[Other] }) => (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] }) |
| 18827 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18828 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ), |
| 18829 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18830 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18831 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 18835 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18836 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18837 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18838 | // GIR_Coverage, 4632, |
| 18839 | GIR_EraseRootFromParent_Done, |
| 18840 | // Label 1266: @47622 |
| 18841 | GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(47700), // Rule ID 4636 // |
| 18842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18844 | // MIs[0] Operand 1 |
| 18845 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 18846 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUGE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPLT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })) |
| 18847 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18848 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18849 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPLT), |
| 18850 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18851 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18852 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18854 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18855 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18856 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18857 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18858 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18861 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18862 | GIR_RootConstrainSelectedInstOperands, |
| 18863 | // GIR_Coverage, 4636, |
| 18864 | GIR_EraseRootFromParent_Done, |
| 18865 | // Label 1267: @47700 |
| 18866 | GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(47778), // Rule ID 4668 // |
| 18867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18869 | // MIs[0] Operand 1 |
| 18870 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 18871 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETULE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPGT:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })) |
| 18872 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18873 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18874 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPGT), |
| 18875 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18876 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18877 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18878 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18879 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18880 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18881 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18882 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18883 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18886 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18887 | GIR_RootConstrainSelectedInstOperands, |
| 18888 | // GIR_Coverage, 4668, |
| 18889 | GIR_EraseRootFromParent_Done, |
| 18890 | // Label 1268: @47778 |
| 18891 | GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(47856), // Rule ID 4700 // |
| 18892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18894 | // MIs[0] Operand 1 |
| 18895 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 18896 | // (setcc:{ *:[i1] } f64:{ *:[f64] }:$s1, f64:{ *:[f64] }:$s2, SETUNE:{ *:[Other] }) => (CRNOT:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i1] } (EFDCMPEQ:{ *:[i32] } ?:{ *:[f64] }:$s1, ?:{ *:[f64] }:$s2), sub_gt:{ *:[i32] })) |
| 18897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18898 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 18899 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::EFDCMPEQ), |
| 18900 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18901 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // s1 |
| 18902 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // s2 |
| 18903 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 18905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18906 | GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_gt), |
| 18907 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18908 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(PPC::CRRCRegClassID), |
| 18909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18912 | GIR_RootConstrainSelectedInstOperands, |
| 18913 | // GIR_Coverage, 4700, |
| 18914 | GIR_EraseRootFromParent_Done, |
| 18915 | // Label 1269: @47856 |
| 18916 | GIM_Reject, |
| 18917 | // Label 1263: @47857 |
| 18918 | GIM_Reject, |
| 18919 | // Label 1255: @47858 |
| 18920 | GIM_Reject, |
| 18921 | // Label 1202: @47859 |
| 18922 | GIM_Reject, |
| 18923 | // Label 32: @47860 |
| 18924 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 1278*/ GIMT_Encode4(48956), |
| 18925 | /*GILLT_s1*//*Label 1270*/ GIMT_Encode4(47903), |
| 18926 | /*GILLT_s32*//*Label 1271*/ GIMT_Encode4(47996), |
| 18927 | /*GILLT_s64*//*Label 1272*/ GIMT_Encode4(48085), |
| 18928 | /*GILLT_s128*//*Label 1273*/ GIMT_Encode4(48174), |
| 18929 | /*GILLT_v2s64*//*Label 1274*/ GIMT_Encode4(48349), |
| 18930 | /*GILLT_v4s32*//*Label 1275*/ GIMT_Encode4(48514), |
| 18931 | /*GILLT_v8s16*//*Label 1276*/ GIMT_Encode4(48676), |
| 18932 | /*GILLT_v16s8*//*Label 1277*/ GIMT_Encode4(48816), |
| 18933 | // Label 1270: @47903 |
| 18934 | GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(47995), // Rule ID 4731 // |
| 18935 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 18936 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 18937 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s1, |
| 18938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::CRBITRCRegClassID), |
| 18939 | // (select:{ *:[i1] } i1:{ *:[i1] }:$cond, i1:{ *:[i1] }:$tval, i1:{ *:[i1] }:$fval) => (CROR:{ *:[i1] } (CRAND:{ *:[i1] } ?:{ *:[i1] }:$cond, ?:{ *:[i1] }:$tval), (CRAND:{ *:[i1] } (CRNOT:{ *:[i1] } ?:{ *:[i1] }:$cond), ?:{ *:[i1] }:$fval)) |
| 18940 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 18941 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 18942 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 18943 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::CRNOT), |
| 18944 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18945 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 18946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 18947 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::CRAND), |
| 18948 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18949 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 18950 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // fval |
| 18951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 18952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::CRAND), |
| 18953 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 18954 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 18955 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // tval |
| 18956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::CROR), |
| 18958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[CRD] |
| 18959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 18960 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 18961 | GIR_RootConstrainSelectedInstOperands, |
| 18962 | // GIR_Coverage, 4731, |
| 18963 | GIR_EraseRootFromParent_Done, |
| 18964 | // Label 1279: @47995 |
| 18965 | GIM_Reject, |
| 18966 | // Label 1271: @47996 |
| 18967 | GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(48084), |
| 18968 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 18969 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18970 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18971 | GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(48029), // Rule ID 1045 // |
| 18972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 18973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 18974 | // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_VSSRC:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) |
| 18975 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VSSRC), |
| 18976 | GIR_RootConstrainSelectedInstOperands, |
| 18977 | // GIR_Coverage, 1045, |
| 18978 | GIR_Done, |
| 18979 | // Label 1281: @48029 |
| 18980 | GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(48045), // Rule ID 5 // |
| 18981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 18982 | // (select:{ *:[i32] } i1:{ *:[i1] }:$cond, i32:{ *:[i32] }:$T, i32:{ *:[i32] }:$F) => (SELECT_I4:{ *:[i32] } i1:{ *:[i1] }:$cond, i32:{ *:[i32] }:$T, i32:{ *:[i32] }:$F) |
| 18983 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_I4), |
| 18984 | GIR_RootConstrainSelectedInstOperands, |
| 18985 | // GIR_Coverage, 5, |
| 18986 | GIR_Done, |
| 18987 | // Label 1282: @48045 |
| 18988 | GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(48064), // Rule ID 7 // |
| 18989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 18990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 18991 | // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_F4:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) |
| 18992 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_F4), |
| 18993 | GIR_RootConstrainSelectedInstOperands, |
| 18994 | // GIR_Coverage, 7, |
| 18995 | GIR_Done, |
| 18996 | // Label 1283: @48064 |
| 18997 | GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(48083), // Rule ID 603 // |
| 18998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 18999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 19000 | // (select:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) => (SELECT_SPE4:{ *:[f32] } i1:{ *:[i1] }:$cond, f32:{ *:[f32] }:$T, f32:{ *:[f32] }:$F) |
| 19001 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_SPE4), |
| 19002 | GIR_RootConstrainSelectedInstOperands, |
| 19003 | // GIR_Coverage, 603, |
| 19004 | GIR_Done, |
| 19005 | // Label 1284: @48083 |
| 19006 | GIM_Reject, |
| 19007 | // Label 1280: @48084 |
| 19008 | GIM_Reject, |
| 19009 | // Label 1272: @48085 |
| 19010 | GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(48173), |
| 19011 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 19012 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19013 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 19014 | GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(48118), // Rule ID 1044 // |
| 19015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 19017 | // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_VSFRC:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) |
| 19018 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VSFRC), |
| 19019 | GIR_RootConstrainSelectedInstOperands, |
| 19020 | // GIR_Coverage, 1044, |
| 19021 | GIR_Done, |
| 19022 | // Label 1286: @48118 |
| 19023 | GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(48134), // Rule ID 6 // |
| 19024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 19025 | // (select:{ *:[i64] } i1:{ *:[i1] }:$cond, i64:{ *:[i64] }:$T, i64:{ *:[i64] }:$F) => (SELECT_I8:{ *:[i64] } i1:{ *:[i1] }:$cond, i64:{ *:[i64] }:$T, i64:{ *:[i64] }:$F) |
| 19026 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_I8), |
| 19027 | GIR_RootConstrainSelectedInstOperands, |
| 19028 | // GIR_Coverage, 6, |
| 19029 | GIR_Done, |
| 19030 | // Label 1287: @48134 |
| 19031 | GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(48153), // Rule ID 8 // |
| 19032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 19034 | // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_F8:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) |
| 19035 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_F8), |
| 19036 | GIR_RootConstrainSelectedInstOperands, |
| 19037 | // GIR_Coverage, 8, |
| 19038 | GIR_Done, |
| 19039 | // Label 1288: @48153 |
| 19040 | GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(48172), // Rule ID 604 // |
| 19041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 19042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 19043 | // (select:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) => (SELECT_SPE:{ *:[f64] } i1:{ *:[i1] }:$cond, f64:{ *:[f64] }:$T, f64:{ *:[f64] }:$F) |
| 19044 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_SPE), |
| 19045 | GIR_RootConstrainSelectedInstOperands, |
| 19046 | // GIR_Coverage, 604, |
| 19047 | GIR_Done, |
| 19048 | // Label 1289: @48172 |
| 19049 | GIM_Reject, |
| 19050 | // Label 1285: @48173 |
| 19051 | GIM_Reject, |
| 19052 | // Label 1273: @48174 |
| 19053 | GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(48286), // Rule ID 1657 // |
| 19054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 19056 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 19057 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 19058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19059 | // (vselect:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXSEL:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$vC, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$vB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$vA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 19060 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 19061 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 19062 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 19063 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, |
| 19064 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19065 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19066 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // vA |
| 19067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 19068 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19069 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19070 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 19071 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 19072 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19073 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19074 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // vC |
| 19075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19076 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19077 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19078 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 19079 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 19080 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 19081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 19084 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19085 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 19086 | // GIR_Coverage, 1657, |
| 19087 | GIR_EraseRootFromParent_Done, |
| 19088 | // Label 1290: @48286 |
| 19089 | GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(48314), // Rule ID 9 // |
| 19090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19091 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 19092 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 19093 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 19094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19095 | // (select:{ *:[f128] } i1:{ *:[i1] }:$cond, f128:{ *:[f128] }:$T, f128:{ *:[f128] }:$F) => (SELECT_F16:{ *:[f128] } i1:{ *:[i1] }:$cond, f128:{ *:[f128] }:$T, f128:{ *:[f128] }:$F) |
| 19096 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_F16), |
| 19097 | GIR_RootConstrainSelectedInstOperands, |
| 19098 | // GIR_Coverage, 9, |
| 19099 | GIR_Done, |
| 19100 | // Label 1291: @48314 |
| 19101 | GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(48348), // Rule ID 1412 // |
| 19102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19103 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 19104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 19105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 19106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19107 | // (vselect:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:[v1i128] }:$vC) => (VSEL:{ *:[v1i128] } ?:{ *:[v1i128] }:$vC, ?:{ *:[v1i128] }:$vB, ?:{ *:[v1i128] }:$vA) |
| 19108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19110 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19111 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19112 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19113 | GIR_RootConstrainSelectedInstOperands, |
| 19114 | // GIR_Coverage, 1412, |
| 19115 | GIR_EraseRootFromParent_Done, |
| 19116 | // Label 1292: @48348 |
| 19117 | GIM_Reject, |
| 19118 | // Label 1274: @48349 |
| 19119 | GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(48377), // Rule ID 1043 // |
| 19120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19121 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 19122 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19123 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19125 | // (select:{ *:[v2f64] } i1:{ *:[i1] }:$cond, v2f64:{ *:[v2f64] }:$T, v2f64:{ *:[v2f64] }:$F) => (SELECT_VSRC:{ *:[v2f64] } i1:{ *:[i1] }:$cond, v2f64:{ *:[v2f64] }:$T, v2f64:{ *:[v2f64] }:$F) |
| 19126 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VSRC), |
| 19127 | GIR_RootConstrainSelectedInstOperands, |
| 19128 | // GIR_Coverage, 1043, |
| 19129 | GIR_Done, |
| 19130 | // Label 1293: @48377 |
| 19131 | GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(48411), // Rule ID 1654 // |
| 19132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19133 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19134 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19135 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19137 | // (vselect:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v2i64:{ *:[v2i64] }:$vC) => (XXSEL:{ *:[v2i64] } ?:{ *:[v2i64] }:$vC, ?:{ *:[v2i64] }:$vB, ?:{ *:[v2i64] }:$vA) |
| 19138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 19140 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19141 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19142 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19143 | GIR_RootConstrainSelectedInstOperands, |
| 19144 | // GIR_Coverage, 1654, |
| 19145 | GIR_EraseRootFromParent_Done, |
| 19146 | // Label 1294: @48411 |
| 19147 | GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(48445), // Rule ID 1656 // |
| 19148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19149 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19151 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19153 | // (vselect:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$vA, v2f64:{ *:[v2f64] }:$vB, v2f64:{ *:[v2f64] }:$vC) => (XXSEL:{ *:[v2f64] } ?:{ *:[v2f64] }:$vC, ?:{ *:[v2f64] }:$vB, ?:{ *:[v2i64] }:$vA) |
| 19154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 19156 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19157 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19158 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19159 | GIR_RootConstrainSelectedInstOperands, |
| 19160 | // GIR_Coverage, 1656, |
| 19161 | GIR_EraseRootFromParent_Done, |
| 19162 | // Label 1295: @48445 |
| 19163 | GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(48479), // Rule ID 1409 // |
| 19164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19165 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19166 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19167 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19169 | // (vselect:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$vA, v2i64:{ *:[v2i64] }:$vB, v2i64:{ *:[v2i64] }:$vC) => (VSEL:{ *:[v2i64] } ?:{ *:[v2i64] }:$vC, ?:{ *:[v2i64] }:$vB, ?:{ *:[v2i64] }:$vA) |
| 19170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19172 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19173 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19174 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19175 | GIR_RootConstrainSelectedInstOperands, |
| 19176 | // GIR_Coverage, 1409, |
| 19177 | GIR_EraseRootFromParent_Done, |
| 19178 | // Label 1296: @48479 |
| 19179 | GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(48513), // Rule ID 1411 // |
| 19180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19181 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19182 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19183 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19185 | // (vselect:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$vA, v2f64:{ *:[v2f64] }:$vB, v2f64:{ *:[v2f64] }:$vC) => (VSEL:{ *:[v2f64] } ?:{ *:[v2f64] }:$vC, ?:{ *:[v2f64] }:$vB, ?:{ *:[v2i64] }:$vA) |
| 19186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19188 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19189 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19190 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19191 | GIR_RootConstrainSelectedInstOperands, |
| 19192 | // GIR_Coverage, 1411, |
| 19193 | GIR_EraseRootFromParent_Done, |
| 19194 | // Label 1297: @48513 |
| 19195 | GIM_Reject, |
| 19196 | // Label 1275: @48514 |
| 19197 | GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(48548), // Rule ID 1653 // |
| 19198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19199 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19200 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19201 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19203 | // (vselect:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (XXSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vC, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vA) |
| 19204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 19206 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19207 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19208 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19209 | GIR_RootConstrainSelectedInstOperands, |
| 19210 | // GIR_Coverage, 1653, |
| 19211 | GIR_EraseRootFromParent_Done, |
| 19212 | // Label 1298: @48548 |
| 19213 | GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(48582), // Rule ID 1655 // |
| 19214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19215 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19217 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19219 | // (vselect:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA, v4f32:{ *:[v4f32] }:$vB, v4f32:{ *:[v4f32] }:$vC) => (XXSEL:{ *:[v4f32] } ?:{ *:[v4f32] }:$vC, ?:{ *:[v4f32] }:$vB, ?:{ *:[v4i32] }:$vA) |
| 19220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 19222 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19223 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19224 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19225 | GIR_RootConstrainSelectedInstOperands, |
| 19226 | // GIR_Coverage, 1655, |
| 19227 | GIR_EraseRootFromParent_Done, |
| 19228 | // Label 1299: @48582 |
| 19229 | GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(48607), // Rule ID 10 // |
| 19230 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 19231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19232 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19233 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19234 | // (select:{ *:[v4i32] } i1:{ *:[i1] }:$cond, v4i32:{ *:[v4i32] }:$T, v4i32:{ *:[v4i32] }:$F) => (SELECT_VRRC:{ *:[v4i32] } i1:{ *:[i1] }:$cond, v4i32:{ *:[v4i32] }:$T, v4i32:{ *:[v4i32] }:$F) |
| 19235 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::SELECT_VRRC), |
| 19236 | GIR_RootConstrainSelectedInstOperands, |
| 19237 | // GIR_Coverage, 10, |
| 19238 | GIR_Done, |
| 19239 | // Label 1300: @48607 |
| 19240 | GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(48641), // Rule ID 1408 // |
| 19241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19242 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19243 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19244 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19246 | // (vselect:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB, v4i32:{ *:[v4i32] }:$vC) => (VSEL:{ *:[v4i32] } ?:{ *:[v4i32] }:$vC, ?:{ *:[v4i32] }:$vB, ?:{ *:[v4i32] }:$vA) |
| 19247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19249 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19250 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19251 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19252 | GIR_RootConstrainSelectedInstOperands, |
| 19253 | // GIR_Coverage, 1408, |
| 19254 | GIR_EraseRootFromParent_Done, |
| 19255 | // Label 1301: @48641 |
| 19256 | GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(48675), // Rule ID 1410 // |
| 19257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19258 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19259 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19260 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19262 | // (vselect:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA, v4f32:{ *:[v4f32] }:$vB, v4f32:{ *:[v4f32] }:$vC) => (VSEL:{ *:[v4f32] } ?:{ *:[v4f32] }:$vC, ?:{ *:[v4f32] }:$vB, ?:{ *:[v4i32] }:$vA) |
| 19263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19265 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19266 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19267 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19268 | GIR_RootConstrainSelectedInstOperands, |
| 19269 | // GIR_Coverage, 1410, |
| 19270 | GIR_EraseRootFromParent_Done, |
| 19271 | // Label 1302: @48675 |
| 19272 | GIM_Reject, |
| 19273 | // Label 1276: @48676 |
| 19274 | GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(48815), |
| 19275 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19276 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19277 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19279 | GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(48793), // Rule ID 1652 // |
| 19280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19281 | // (vselect:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXSEL:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$vC, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$vB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$vA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 19282 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 19283 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 19284 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 19285 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, |
| 19286 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19287 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19288 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // vA |
| 19289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 19290 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19291 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19292 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 19293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 19294 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19295 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19296 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // vC |
| 19297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19299 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19300 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 19301 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 19302 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 19303 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 19306 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19307 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 19308 | // GIR_Coverage, 1652, |
| 19309 | GIR_EraseRootFromParent_Done, |
| 19310 | // Label 1304: @48793 |
| 19311 | GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(48814), // Rule ID 1407 // |
| 19312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19313 | // (vselect:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB, v8i16:{ *:[v8i16] }:$vC) => (VSEL:{ *:[v8i16] } ?:{ *:[v8i16] }:$vC, ?:{ *:[v8i16] }:$vB, ?:{ *:[v8i16] }:$vA) |
| 19314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19316 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19317 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19318 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19319 | GIR_RootConstrainSelectedInstOperands, |
| 19320 | // GIR_Coverage, 1407, |
| 19321 | GIR_EraseRootFromParent_Done, |
| 19322 | // Label 1305: @48814 |
| 19323 | GIM_Reject, |
| 19324 | // Label 1303: @48815 |
| 19325 | GIM_Reject, |
| 19326 | // Label 1277: @48816 |
| 19327 | GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(48955), |
| 19328 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19329 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19330 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19332 | GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(48933), // Rule ID 1651 // |
| 19333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19334 | // (vselect:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v16i8:{ *:[v16i8] }:$vC) => (COPY_TO_REGCLASS:{ *:[v16i8] } (XXSEL:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$vC, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$vB, VSRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$vA, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 19335 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 19336 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 19337 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 19338 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32, |
| 19339 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19340 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19341 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // vA |
| 19342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 19343 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19344 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19345 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // vB |
| 19346 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 19347 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19348 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19349 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // vC |
| 19350 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19351 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXSEL), |
| 19352 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 19353 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 19354 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 19355 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 19356 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 19358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 19359 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 19360 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 19361 | // GIR_Coverage, 1651, |
| 19362 | GIR_EraseRootFromParent_Done, |
| 19363 | // Label 1307: @48933 |
| 19364 | GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(48954), // Rule ID 1406 // |
| 19365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19366 | // (vselect:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB, v16i8:{ *:[v16i8] }:$vC) => (VSEL:{ *:[v16i8] } ?:{ *:[v16i8] }:$vC, ?:{ *:[v16i8] }:$vB, ?:{ *:[v16i8] }:$vA) |
| 19367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VSEL), |
| 19368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 19369 | GIR_RootToRootCopy, /*OpIdx*/3, // vC |
| 19370 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 19371 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 19372 | GIR_RootConstrainSelectedInstOperands, |
| 19373 | // GIR_Coverage, 1406, |
| 19374 | GIR_EraseRootFromParent_Done, |
| 19375 | // Label 1308: @48954 |
| 19376 | GIM_Reject, |
| 19377 | // Label 1306: @48955 |
| 19378 | GIM_Reject, |
| 19379 | // Label 1278: @48956 |
| 19380 | GIM_Reject, |
| 19381 | // Label 33: @48957 |
| 19382 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1313*/ GIMT_Encode4(49086), |
| 19383 | /*GILLT_s32*//*Label 1309*/ GIMT_Encode4(48988), |
| 19384 | /*GILLT_s64*//*Label 1310*/ GIMT_Encode4(49011), GIMT_Encode4(0), |
| 19385 | /*GILLT_v2s64*//*Label 1311*/ GIMT_Encode4(49034), |
| 19386 | /*GILLT_v4s32*//*Label 1312*/ GIMT_Encode4(49060), |
| 19387 | // Label 1309: @48988 |
| 19388 | GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(49010), // Rule ID 204 // |
| 19389 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 19390 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 19392 | // (mulhu:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULHWU:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 19393 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHWU), |
| 19394 | GIR_RootConstrainSelectedInstOperands, |
| 19395 | // GIR_Coverage, 204, |
| 19396 | GIR_Done, |
| 19397 | // Label 1314: @49010 |
| 19398 | GIM_Reject, |
| 19399 | // Label 1310: @49011 |
| 19400 | GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(49033), // Rule ID 670 // |
| 19401 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 19402 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 19404 | // (mulhu:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULHDU:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 19405 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHDU), |
| 19406 | GIR_RootConstrainSelectedInstOperands, |
| 19407 | // GIR_Coverage, 670, |
| 19408 | GIR_Done, |
| 19409 | // Label 1315: @49033 |
| 19410 | GIM_Reject, |
| 19411 | // Label 1311: @49034 |
| 19412 | GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(49059), // Rule ID 1116 // |
| 19413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 19414 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19415 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19417 | // (mulhu:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULHUD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 19418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHUD), |
| 19419 | GIR_RootConstrainSelectedInstOperands, |
| 19420 | // GIR_Coverage, 1116, |
| 19421 | GIR_Done, |
| 19422 | // Label 1316: @49059 |
| 19423 | GIM_Reject, |
| 19424 | // Label 1312: @49060 |
| 19425 | GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(49085), // Rule ID 1114 // |
| 19426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 19427 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19428 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19430 | // (mulhu:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULHUW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 19431 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHUW), |
| 19432 | GIR_RootConstrainSelectedInstOperands, |
| 19433 | // GIR_Coverage, 1114, |
| 19434 | GIR_Done, |
| 19435 | // Label 1317: @49085 |
| 19436 | GIM_Reject, |
| 19437 | // Label 1313: @49086 |
| 19438 | GIM_Reject, |
| 19439 | // Label 34: @49087 |
| 19440 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1322*/ GIMT_Encode4(49216), |
| 19441 | /*GILLT_s32*//*Label 1318*/ GIMT_Encode4(49118), |
| 19442 | /*GILLT_s64*//*Label 1319*/ GIMT_Encode4(49141), GIMT_Encode4(0), |
| 19443 | /*GILLT_v2s64*//*Label 1320*/ GIMT_Encode4(49164), |
| 19444 | /*GILLT_v4s32*//*Label 1321*/ GIMT_Encode4(49190), |
| 19445 | // Label 1318: @49118 |
| 19446 | GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(49140), // Rule ID 203 // |
| 19447 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 19448 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 19450 | // (mulhs:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) => (MULHW:{ *:[i32] } i32:{ *:[i32] }:$RA, i32:{ *:[i32] }:$RB) |
| 19451 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHW), |
| 19452 | GIR_RootConstrainSelectedInstOperands, |
| 19453 | // GIR_Coverage, 203, |
| 19454 | GIR_Done, |
| 19455 | // Label 1323: @49140 |
| 19456 | GIM_Reject, |
| 19457 | // Label 1319: @49141 |
| 19458 | GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(49163), // Rule ID 669 // |
| 19459 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 19460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 19462 | // (mulhs:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) => (MULHD:{ *:[i64] } i64:{ *:[i64] }:$RA, i64:{ *:[i64] }:$RB) |
| 19463 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::MULHD), |
| 19464 | GIR_RootConstrainSelectedInstOperands, |
| 19465 | // GIR_Coverage, 669, |
| 19466 | GIR_Done, |
| 19467 | // Label 1324: @49163 |
| 19468 | GIM_Reject, |
| 19469 | // Label 1320: @49164 |
| 19470 | GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(49189), // Rule ID 1115 // |
| 19471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 19472 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19473 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19475 | // (mulhs:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) => (VMULHSD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VA, v2i64:{ *:[v2i64] }:$VB) |
| 19476 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHSD), |
| 19477 | GIR_RootConstrainSelectedInstOperands, |
| 19478 | // GIR_Coverage, 1115, |
| 19479 | GIR_Done, |
| 19480 | // Label 1325: @49189 |
| 19481 | GIM_Reject, |
| 19482 | // Label 1321: @49190 |
| 19483 | GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(49215), // Rule ID 1113 // |
| 19484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 19485 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19488 | // (mulhs:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) => (VMULHSW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VA, v4i32:{ *:[v4i32] }:$VB) |
| 19489 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMULHSW), |
| 19490 | GIR_RootConstrainSelectedInstOperands, |
| 19491 | // GIR_Coverage, 1113, |
| 19492 | GIR_Done, |
| 19493 | // Label 1326: @49215 |
| 19494 | GIM_Reject, |
| 19495 | // Label 1322: @49216 |
| 19496 | GIM_Reject, |
| 19497 | // Label 35: @49217 |
| 19498 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 1330*/ GIMT_Encode4(49318), |
| 19499 | /*GILLT_v4s32*//*Label 1327*/ GIMT_Encode4(49240), |
| 19500 | /*GILLT_v8s16*//*Label 1328*/ GIMT_Encode4(49266), |
| 19501 | /*GILLT_v16s8*//*Label 1329*/ GIMT_Encode4(49292), |
| 19502 | // Label 1327: @49240 |
| 19503 | GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(49265), // Rule ID 1285 // |
| 19504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19505 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19506 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19508 | // (uaddsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDUWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 19509 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUWS), |
| 19510 | GIR_RootConstrainSelectedInstOperands, |
| 19511 | // GIR_Coverage, 1285, |
| 19512 | GIR_Done, |
| 19513 | // Label 1331: @49265 |
| 19514 | GIM_Reject, |
| 19515 | // Label 1328: @49266 |
| 19516 | GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(49291), // Rule ID 1283 // |
| 19517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19519 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19521 | // (uaddsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDUHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 19522 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUHS), |
| 19523 | GIR_RootConstrainSelectedInstOperands, |
| 19524 | // GIR_Coverage, 1283, |
| 19525 | GIR_Done, |
| 19526 | // Label 1332: @49291 |
| 19527 | GIM_Reject, |
| 19528 | // Label 1329: @49292 |
| 19529 | GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(49317), // Rule ID 1281 // |
| 19530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19531 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19534 | // (uaddsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDUBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 19535 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDUBS), |
| 19536 | GIR_RootConstrainSelectedInstOperands, |
| 19537 | // GIR_Coverage, 1281, |
| 19538 | GIR_Done, |
| 19539 | // Label 1333: @49317 |
| 19540 | GIM_Reject, |
| 19541 | // Label 1330: @49318 |
| 19542 | GIM_Reject, |
| 19543 | // Label 36: @49319 |
| 19544 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 1337*/ GIMT_Encode4(49420), |
| 19545 | /*GILLT_v4s32*//*Label 1334*/ GIMT_Encode4(49342), |
| 19546 | /*GILLT_v8s16*//*Label 1335*/ GIMT_Encode4(49368), |
| 19547 | /*GILLT_v16s8*//*Label 1336*/ GIMT_Encode4(49394), |
| 19548 | // Label 1334: @49342 |
| 19549 | GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(49367), // Rule ID 1284 // |
| 19550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19551 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19552 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19554 | // (saddsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VADDSWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 19555 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDSWS), |
| 19556 | GIR_RootConstrainSelectedInstOperands, |
| 19557 | // GIR_Coverage, 1284, |
| 19558 | GIR_Done, |
| 19559 | // Label 1338: @49367 |
| 19560 | GIM_Reject, |
| 19561 | // Label 1335: @49368 |
| 19562 | GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(49393), // Rule ID 1282 // |
| 19563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19564 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19565 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19567 | // (saddsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VADDSHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 19568 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDSHS), |
| 19569 | GIR_RootConstrainSelectedInstOperands, |
| 19570 | // GIR_Coverage, 1282, |
| 19571 | GIR_Done, |
| 19572 | // Label 1339: @49393 |
| 19573 | GIM_Reject, |
| 19574 | // Label 1336: @49394 |
| 19575 | GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(49419), // Rule ID 1280 // |
| 19576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19577 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19578 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19580 | // (saddsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VADDSBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 19581 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDSBS), |
| 19582 | GIR_RootConstrainSelectedInstOperands, |
| 19583 | // GIR_Coverage, 1280, |
| 19584 | GIR_Done, |
| 19585 | // Label 1340: @49419 |
| 19586 | GIM_Reject, |
| 19587 | // Label 1337: @49420 |
| 19588 | GIM_Reject, |
| 19589 | // Label 37: @49421 |
| 19590 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 1344*/ GIMT_Encode4(49522), |
| 19591 | /*GILLT_v4s32*//*Label 1341*/ GIMT_Encode4(49444), |
| 19592 | /*GILLT_v8s16*//*Label 1342*/ GIMT_Encode4(49470), |
| 19593 | /*GILLT_v16s8*//*Label 1343*/ GIMT_Encode4(49496), |
| 19594 | // Label 1341: @49444 |
| 19595 | GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(49469), // Rule ID 1291 // |
| 19596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19597 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19598 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19600 | // (usubsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBUWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 19601 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUWS), |
| 19602 | GIR_RootConstrainSelectedInstOperands, |
| 19603 | // GIR_Coverage, 1291, |
| 19604 | GIR_Done, |
| 19605 | // Label 1345: @49469 |
| 19606 | GIM_Reject, |
| 19607 | // Label 1342: @49470 |
| 19608 | GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(49495), // Rule ID 1289 // |
| 19609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19610 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19611 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19613 | // (usubsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBUHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 19614 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUHS), |
| 19615 | GIR_RootConstrainSelectedInstOperands, |
| 19616 | // GIR_Coverage, 1289, |
| 19617 | GIR_Done, |
| 19618 | // Label 1346: @49495 |
| 19619 | GIM_Reject, |
| 19620 | // Label 1343: @49496 |
| 19621 | GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(49521), // Rule ID 1287 // |
| 19622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19623 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19625 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19626 | // (usubsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBUBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 19627 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBUBS), |
| 19628 | GIR_RootConstrainSelectedInstOperands, |
| 19629 | // GIR_Coverage, 1287, |
| 19630 | GIR_Done, |
| 19631 | // Label 1347: @49521 |
| 19632 | GIM_Reject, |
| 19633 | // Label 1344: @49522 |
| 19634 | GIM_Reject, |
| 19635 | // Label 38: @49523 |
| 19636 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(8), /*)*//*default:*//*Label 1351*/ GIMT_Encode4(49624), |
| 19637 | /*GILLT_v4s32*//*Label 1348*/ GIMT_Encode4(49546), |
| 19638 | /*GILLT_v8s16*//*Label 1349*/ GIMT_Encode4(49572), |
| 19639 | /*GILLT_v16s8*//*Label 1350*/ GIMT_Encode4(49598), |
| 19640 | // Label 1348: @49546 |
| 19641 | GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(49571), // Rule ID 1290 // |
| 19642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19643 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19644 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19646 | // (ssubsat:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$vA, v4i32:{ *:[v4i32] }:$vB) => (VSUBSWS:{ *:[v4i32] } ?:{ *:[v4i32] }:$vA, ?:{ *:[v4i32] }:$vB) |
| 19647 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBSWS), |
| 19648 | GIR_RootConstrainSelectedInstOperands, |
| 19649 | // GIR_Coverage, 1290, |
| 19650 | GIR_Done, |
| 19651 | // Label 1352: @49571 |
| 19652 | GIM_Reject, |
| 19653 | // Label 1349: @49572 |
| 19654 | GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(49597), // Rule ID 1288 // |
| 19655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19656 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 19657 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19659 | // (ssubsat:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vA, v8i16:{ *:[v8i16] }:$vB) => (VSUBSHS:{ *:[v8i16] } ?:{ *:[v8i16] }:$vA, ?:{ *:[v8i16] }:$vB) |
| 19660 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBSHS), |
| 19661 | GIR_RootConstrainSelectedInstOperands, |
| 19662 | // GIR_Coverage, 1288, |
| 19663 | GIR_Done, |
| 19664 | // Label 1353: @49597 |
| 19665 | GIM_Reject, |
| 19666 | // Label 1350: @49598 |
| 19667 | GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(49623), // Rule ID 1286 // |
| 19668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 19670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19672 | // (ssubsat:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vA, v16i8:{ *:[v16i8] }:$vB) => (VSUBSBS:{ *:[v16i8] } ?:{ *:[v16i8] }:$vA, ?:{ *:[v16i8] }:$vB) |
| 19673 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBSBS), |
| 19674 | GIR_RootConstrainSelectedInstOperands, |
| 19675 | // GIR_Coverage, 1286, |
| 19676 | GIR_Done, |
| 19677 | // Label 1354: @49623 |
| 19678 | GIM_Reject, |
| 19679 | // Label 1351: @49624 |
| 19680 | GIM_Reject, |
| 19681 | // Label 39: @49625 |
| 19682 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1360*/ GIMT_Encode4(49919), |
| 19683 | /*GILLT_s32*//*Label 1355*/ GIMT_Encode4(49656), |
| 19684 | /*GILLT_s64*//*Label 1356*/ GIMT_Encode4(49730), |
| 19685 | /*GILLT_s128*//*Label 1357*/ GIMT_Encode4(49808), |
| 19686 | /*GILLT_v2s64*//*Label 1358*/ GIMT_Encode4(49834), |
| 19687 | /*GILLT_v4s32*//*Label 1359*/ GIMT_Encode4(49864), |
| 19688 | // Label 1355: @49656 |
| 19689 | GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(49729), |
| 19690 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 19691 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19692 | GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(49686), // Rule ID 943 // |
| 19693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 19694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 19695 | // (fadd:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSADDSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 19696 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDSP), |
| 19697 | GIR_RootConstrainSelectedInstOperands, |
| 19698 | // GIR_Coverage, 943, |
| 19699 | GIR_Done, |
| 19700 | // Label 1362: @49686 |
| 19701 | GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(49709), // Rule ID 236 // |
| 19702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 19704 | // (fadd:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) |
| 19705 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADDS), |
| 19706 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19707 | GIR_RootConstrainSelectedInstOperands, |
| 19708 | // GIR_Coverage, 236, |
| 19709 | GIR_Done, |
| 19710 | // Label 1363: @49709 |
| 19711 | GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(49728), // Rule ID 576 // |
| 19712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 19713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 19714 | // (fadd:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSADD:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 19715 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSADD), |
| 19716 | GIR_RootConstrainSelectedInstOperands, |
| 19717 | // GIR_Coverage, 576, |
| 19718 | GIR_Done, |
| 19719 | // Label 1364: @49728 |
| 19720 | GIM_Reject, |
| 19721 | // Label 1361: @49729 |
| 19722 | GIM_Reject, |
| 19723 | // Label 1356: @49730 |
| 19724 | GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(49807), |
| 19725 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 19726 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19727 | GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(49764), // Rule ID 760 // |
| 19728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 19730 | // (fadd:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSADDDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 19731 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDDP), |
| 19732 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19733 | GIR_RootConstrainSelectedInstOperands, |
| 19734 | // GIR_Coverage, 760, |
| 19735 | GIR_Done, |
| 19736 | // Label 1366: @49764 |
| 19737 | GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(49787), // Rule ID 234 // |
| 19738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 19740 | // (fadd:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) |
| 19741 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADD), |
| 19742 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19743 | GIR_RootConstrainSelectedInstOperands, |
| 19744 | // GIR_Coverage, 234, |
| 19745 | GIR_Done, |
| 19746 | // Label 1367: @49787 |
| 19747 | GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(49806), // Rule ID 555 // |
| 19748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 19749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 19750 | // (fadd:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDADD:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 19751 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDADD), |
| 19752 | GIR_RootConstrainSelectedInstOperands, |
| 19753 | // GIR_Coverage, 555, |
| 19754 | GIR_Done, |
| 19755 | // Label 1368: @49806 |
| 19756 | GIM_Reject, |
| 19757 | // Label 1365: @49807 |
| 19758 | GIM_Reject, |
| 19759 | // Label 1357: @49808 |
| 19760 | GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(49833), // Rule ID 978 // |
| 19761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 19762 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 19763 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 19764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19765 | // (fadd:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 19766 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDQP), |
| 19767 | GIR_RootConstrainSelectedInstOperands, |
| 19768 | // GIR_Coverage, 978, |
| 19769 | GIR_Done, |
| 19770 | // Label 1369: @49833 |
| 19771 | GIM_Reject, |
| 19772 | // Label 1358: @49834 |
| 19773 | GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(49863), // Rule ID 764 // |
| 19774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19775 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19776 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19777 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19778 | // (fadd:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVADDDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 19779 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDDP), |
| 19780 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19781 | GIR_RootConstrainSelectedInstOperands, |
| 19782 | // GIR_Coverage, 764, |
| 19783 | GIR_Done, |
| 19784 | // Label 1370: @49863 |
| 19785 | GIM_Reject, |
| 19786 | // Label 1359: @49864 |
| 19787 | GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(49918), |
| 19788 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19789 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19790 | GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(49898), // Rule ID 766 // |
| 19791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19793 | // (fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVADDSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 19794 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDSP), |
| 19795 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19796 | GIR_RootConstrainSelectedInstOperands, |
| 19797 | // GIR_Coverage, 766, |
| 19798 | GIR_Done, |
| 19799 | // Label 1372: @49898 |
| 19800 | GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(49917), // Rule ID 297 // |
| 19801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19803 | // (fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VADDFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) |
| 19804 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VADDFP), |
| 19805 | GIR_RootConstrainSelectedInstOperands, |
| 19806 | // GIR_Coverage, 297, |
| 19807 | GIR_Done, |
| 19808 | // Label 1373: @49917 |
| 19809 | GIM_Reject, |
| 19810 | // Label 1371: @49918 |
| 19811 | GIM_Reject, |
| 19812 | // Label 1360: @49919 |
| 19813 | GIM_Reject, |
| 19814 | // Label 40: @49920 |
| 19815 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1379*/ GIMT_Encode4(50214), |
| 19816 | /*GILLT_s32*//*Label 1374*/ GIMT_Encode4(49951), |
| 19817 | /*GILLT_s64*//*Label 1375*/ GIMT_Encode4(50025), |
| 19818 | /*GILLT_s128*//*Label 1376*/ GIMT_Encode4(50103), |
| 19819 | /*GILLT_v2s64*//*Label 1377*/ GIMT_Encode4(50129), |
| 19820 | /*GILLT_v4s32*//*Label 1378*/ GIMT_Encode4(50159), |
| 19821 | // Label 1374: @49951 |
| 19822 | GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(50024), |
| 19823 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 19824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19825 | GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(49981), // Rule ID 947 // |
| 19826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 19827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 19828 | // (fsub:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSSUBSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 19829 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBSP), |
| 19830 | GIR_RootConstrainSelectedInstOperands, |
| 19831 | // GIR_Coverage, 947, |
| 19832 | GIR_Done, |
| 19833 | // Label 1381: @49981 |
| 19834 | GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(50004), // Rule ID 248 // |
| 19835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 19837 | // (fsub:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) |
| 19838 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUBS), |
| 19839 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19840 | GIR_RootConstrainSelectedInstOperands, |
| 19841 | // GIR_Coverage, 248, |
| 19842 | GIR_Done, |
| 19843 | // Label 1382: @50004 |
| 19844 | GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(50023), // Rule ID 594 // |
| 19845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 19846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 19847 | // (fsub:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSSUB:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 19848 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSSUB), |
| 19849 | GIR_RootConstrainSelectedInstOperands, |
| 19850 | // GIR_Coverage, 594, |
| 19851 | GIR_Done, |
| 19852 | // Label 1383: @50023 |
| 19853 | GIM_Reject, |
| 19854 | // Label 1380: @50024 |
| 19855 | GIM_Reject, |
| 19856 | // Label 1375: @50025 |
| 19857 | GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(50102), |
| 19858 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 19859 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19860 | GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(50059), // Rule ID 772 // |
| 19861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 19863 | // (fsub:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSSUBDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 19864 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBDP), |
| 19865 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19866 | GIR_RootConstrainSelectedInstOperands, |
| 19867 | // GIR_Coverage, 772, |
| 19868 | GIR_Done, |
| 19869 | // Label 1385: @50059 |
| 19870 | GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(50082), // Rule ID 246 // |
| 19871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 19873 | // (fsub:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) |
| 19874 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUB), |
| 19875 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19876 | GIR_RootConstrainSelectedInstOperands, |
| 19877 | // GIR_Coverage, 246, |
| 19878 | GIR_Done, |
| 19879 | // Label 1386: @50082 |
| 19880 | GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(50101), // Rule ID 573 // |
| 19881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 19882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 19883 | // (fsub:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDSUB:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 19884 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDSUB), |
| 19885 | GIR_RootConstrainSelectedInstOperands, |
| 19886 | // GIR_Coverage, 573, |
| 19887 | GIR_Done, |
| 19888 | // Label 1387: @50101 |
| 19889 | GIM_Reject, |
| 19890 | // Label 1384: @50102 |
| 19891 | GIM_Reject, |
| 19892 | // Label 1376: @50103 |
| 19893 | GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(50128), // Rule ID 982 // |
| 19894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 19895 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 19896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 19897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19898 | // (fsub:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 19899 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBQP), |
| 19900 | GIR_RootConstrainSelectedInstOperands, |
| 19901 | // GIR_Coverage, 982, |
| 19902 | GIR_Done, |
| 19903 | // Label 1388: @50128 |
| 19904 | GIM_Reject, |
| 19905 | // Label 1377: @50129 |
| 19906 | GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(50158), // Rule ID 774 // |
| 19907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 19909 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19911 | // (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVSUBDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 19912 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBDP), |
| 19913 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19914 | GIR_RootConstrainSelectedInstOperands, |
| 19915 | // GIR_Coverage, 774, |
| 19916 | GIR_Done, |
| 19917 | // Label 1389: @50158 |
| 19918 | GIM_Reject, |
| 19919 | // Label 1378: @50159 |
| 19920 | GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(50213), |
| 19921 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 19922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19923 | GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(50193), // Rule ID 776 // |
| 19924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 19926 | // (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVSUBSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 19927 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBSP), |
| 19928 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19929 | GIR_RootConstrainSelectedInstOperands, |
| 19930 | // GIR_Coverage, 776, |
| 19931 | GIR_Done, |
| 19932 | // Label 1391: @50193 |
| 19933 | GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(50212), // Rule ID 367 // |
| 19934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 19935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 19936 | // (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) => (VSUBFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$VA, v4f32:{ *:[v4f32] }:$VB) |
| 19937 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VSUBFP), |
| 19938 | GIR_RootConstrainSelectedInstOperands, |
| 19939 | // GIR_Coverage, 367, |
| 19940 | GIR_Done, |
| 19941 | // Label 1392: @50212 |
| 19942 | GIM_Reject, |
| 19943 | // Label 1390: @50213 |
| 19944 | GIM_Reject, |
| 19945 | // Label 1379: @50214 |
| 19946 | GIM_Reject, |
| 19947 | // Label 41: @50215 |
| 19948 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1398*/ GIMT_Encode4(50564), |
| 19949 | /*GILLT_s32*//*Label 1393*/ GIMT_Encode4(50246), |
| 19950 | /*GILLT_s64*//*Label 1394*/ GIMT_Encode4(50320), |
| 19951 | /*GILLT_s128*//*Label 1395*/ GIMT_Encode4(50398), |
| 19952 | /*GILLT_v2s64*//*Label 1396*/ GIMT_Encode4(50424), |
| 19953 | /*GILLT_v4s32*//*Label 1397*/ GIMT_Encode4(50454), |
| 19954 | // Label 1393: @50246 |
| 19955 | GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(50319), |
| 19956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 19957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19958 | GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(50276), // Rule ID 945 // |
| 19959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 19960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 19961 | // (fmul:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSMULSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 19962 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULSP), |
| 19963 | GIR_RootConstrainSelectedInstOperands, |
| 19964 | // GIR_Coverage, 945, |
| 19965 | GIR_Done, |
| 19966 | // Label 1400: @50276 |
| 19967 | GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(50299), // Rule ID 244 // |
| 19968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 19969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 19970 | // (fmul:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) => (FMULS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) |
| 19971 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMULS), |
| 19972 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19973 | GIR_RootConstrainSelectedInstOperands, |
| 19974 | // GIR_Coverage, 244, |
| 19975 | GIR_Done, |
| 19976 | // Label 1401: @50299 |
| 19977 | GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(50318), // Rule ID 590 // |
| 19978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 19979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 19980 | // (fmul:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSMUL:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 19981 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSMUL), |
| 19982 | GIR_RootConstrainSelectedInstOperands, |
| 19983 | // GIR_Coverage, 590, |
| 19984 | GIR_Done, |
| 19985 | // Label 1402: @50318 |
| 19986 | GIM_Reject, |
| 19987 | // Label 1399: @50319 |
| 19988 | GIM_Reject, |
| 19989 | // Label 1394: @50320 |
| 19990 | GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(50397), |
| 19991 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 19992 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19993 | GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(50354), // Rule ID 762 // |
| 19994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 19995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 19996 | // (fmul:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSMULDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 19997 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULDP), |
| 19998 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 19999 | GIR_RootConstrainSelectedInstOperands, |
| 20000 | // GIR_Coverage, 762, |
| 20001 | GIR_Done, |
| 20002 | // Label 1404: @50354 |
| 20003 | GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(50377), // Rule ID 242 // |
| 20004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20006 | // (fmul:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) => (FMUL:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) |
| 20007 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMUL), |
| 20008 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20009 | GIR_RootConstrainSelectedInstOperands, |
| 20010 | // GIR_Coverage, 242, |
| 20011 | GIR_Done, |
| 20012 | // Label 1405: @50377 |
| 20013 | GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(50396), // Rule ID 569 // |
| 20014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 20016 | // (fmul:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDMUL:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 20017 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDMUL), |
| 20018 | GIR_RootConstrainSelectedInstOperands, |
| 20019 | // GIR_Coverage, 569, |
| 20020 | GIR_Done, |
| 20021 | // Label 1406: @50396 |
| 20022 | GIM_Reject, |
| 20023 | // Label 1403: @50397 |
| 20024 | GIM_Reject, |
| 20025 | // Label 1395: @50398 |
| 20026 | GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(50423), // Rule ID 980 // |
| 20027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 20028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 20029 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 20030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 20031 | // (fmul:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 20032 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULQP), |
| 20033 | GIR_RootConstrainSelectedInstOperands, |
| 20034 | // GIR_Coverage, 980, |
| 20035 | GIR_Done, |
| 20036 | // Label 1407: @50423 |
| 20037 | GIM_Reject, |
| 20038 | // Label 1396: @50424 |
| 20039 | GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(50453), // Rule ID 768 // |
| 20040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20041 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 20042 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20044 | // (fmul:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVMULDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 20045 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULDP), |
| 20046 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20047 | GIR_RootConstrainSelectedInstOperands, |
| 20048 | // GIR_Coverage, 768, |
| 20049 | GIR_Done, |
| 20050 | // Label 1408: @50453 |
| 20051 | GIM_Reject, |
| 20052 | // Label 1397: @50454 |
| 20053 | GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(50563), |
| 20054 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20055 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20056 | GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(50488), // Rule ID 770 // |
| 20057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20059 | // (fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVMULSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 20060 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULSP), |
| 20061 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20062 | GIR_RootConstrainSelectedInstOperands, |
| 20063 | // GIR_Coverage, 770, |
| 20064 | GIR_Done, |
| 20065 | // Label 1410: @50488 |
| 20066 | GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(50562), // Rule ID 1368 // |
| 20067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 20068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 20069 | // (fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA, v4f32:{ *:[v4f32] }:$vB) => (VMADDFP:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA, ?:{ *:[v4f32] }:$vB, (VSLW:{ *:[v4i32] } (V_SETALLONES:{ *:[v4i32] }), (V_SETALLONES:{ *:[v4i32] }))) |
| 20070 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 20071 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 20072 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 20073 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::V_SETALLONES), |
| 20074 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20075 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 20076 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::V_SETALLONES), |
| 20077 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20078 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 20079 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::VSLW), |
| 20080 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20081 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 20082 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 20083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMADDFP), |
| 20085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 20086 | GIR_RootToRootCopy, /*OpIdx*/1, // vA |
| 20087 | GIR_RootToRootCopy, /*OpIdx*/2, // vB |
| 20088 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20089 | GIR_RootConstrainSelectedInstOperands, |
| 20090 | // GIR_Coverage, 1368, |
| 20091 | GIR_EraseRootFromParent_Done, |
| 20092 | // Label 1411: @50562 |
| 20093 | GIM_Reject, |
| 20094 | // Label 1409: @50563 |
| 20095 | GIM_Reject, |
| 20096 | // Label 1398: @50564 |
| 20097 | GIM_Reject, |
| 20098 | // Label 42: @50565 |
| 20099 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1417*/ GIMT_Encode4(51145), |
| 20100 | /*GILLT_s32*//*Label 1412*/ GIMT_Encode4(50596), |
| 20101 | /*GILLT_s64*//*Label 1413*/ GIMT_Encode4(50742), |
| 20102 | /*GILLT_s128*//*Label 1414*/ GIMT_Encode4(50888), |
| 20103 | /*GILLT_v2s64*//*Label 1415*/ GIMT_Encode4(50966), |
| 20104 | /*GILLT_v4s32*//*Label 1416*/ GIMT_Encode4(51044), |
| 20105 | // Label 1412: @50596 |
| 20106 | GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(50741), |
| 20107 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 20108 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20109 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 20110 | GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(50651), // Rule ID 959 // |
| 20111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20113 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20114 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20115 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20116 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20117 | // (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi)) => (XSMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBASP), |
| 20119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 20121 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20122 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20123 | GIR_RootConstrainSelectedInstOperands, |
| 20124 | // GIR_Coverage, 959, |
| 20125 | GIR_EraseRootFromParent_Done, |
| 20126 | // Label 1419: @50651 |
| 20127 | GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(50676), // Rule ID 957 // |
| 20128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20130 | // (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi) => (XSMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDASP), |
| 20132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20133 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 20134 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20135 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20136 | GIR_RootConstrainSelectedInstOperands, |
| 20137 | // GIR_Coverage, 957, |
| 20138 | GIR_EraseRootFromParent_Done, |
| 20139 | // Label 1420: @50676 |
| 20140 | GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(50717), // Rule ID 222 // |
| 20141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20143 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20144 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20145 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20146 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20147 | // (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB)) => (FMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 20148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS), |
| 20149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20150 | GIR_RootToRootCopy, /*OpIdx*/1, // FRA |
| 20151 | GIR_RootToRootCopy, /*OpIdx*/2, // FRC |
| 20152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB |
| 20153 | GIR_RootConstrainSelectedInstOperands, |
| 20154 | // GIR_Coverage, 222, |
| 20155 | GIR_EraseRootFromParent_Done, |
| 20156 | // Label 1421: @50717 |
| 20157 | GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(50740), // Rule ID 218 // |
| 20158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20160 | // (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) => (FMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 20161 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADDS), |
| 20162 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20163 | GIR_RootConstrainSelectedInstOperands, |
| 20164 | // GIR_Coverage, 218, |
| 20165 | GIR_Done, |
| 20166 | // Label 1422: @50740 |
| 20167 | GIM_Reject, |
| 20168 | // Label 1418: @50741 |
| 20169 | GIM_Reject, |
| 20170 | // Label 1413: @50742 |
| 20171 | GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(50887), |
| 20172 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 20173 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20174 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 20175 | GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(50797), // Rule ID 780 // |
| 20176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20178 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20179 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20180 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20181 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20182 | // (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi)) => (XSMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBADP), |
| 20184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 20186 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20187 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20188 | GIR_RootConstrainSelectedInstOperands, |
| 20189 | // GIR_Coverage, 780, |
| 20190 | GIR_EraseRootFromParent_Done, |
| 20191 | // Label 1424: @50797 |
| 20192 | GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(50822), // Rule ID 778 // |
| 20193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20195 | // (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi) => (XSMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDADP), |
| 20197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20198 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 20199 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20200 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20201 | GIR_RootConstrainSelectedInstOperands, |
| 20202 | // GIR_Coverage, 778, |
| 20203 | GIR_EraseRootFromParent_Done, |
| 20204 | // Label 1425: @50822 |
| 20205 | GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(50863), // Rule ID 220 // |
| 20206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20208 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20209 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20210 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20211 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20212 | // (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB)) => (FMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 20213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB), |
| 20214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20215 | GIR_RootToRootCopy, /*OpIdx*/1, // FRA |
| 20216 | GIR_RootToRootCopy, /*OpIdx*/2, // FRC |
| 20217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB |
| 20218 | GIR_RootConstrainSelectedInstOperands, |
| 20219 | // GIR_Coverage, 220, |
| 20220 | GIR_EraseRootFromParent_Done, |
| 20221 | // Label 1426: @50863 |
| 20222 | GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(50886), // Rule ID 216 // |
| 20223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20225 | // (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) => (FMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 20226 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADD), |
| 20227 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20228 | GIR_RootConstrainSelectedInstOperands, |
| 20229 | // GIR_Coverage, 216, |
| 20230 | GIR_Done, |
| 20231 | // Label 1427: @50886 |
| 20232 | GIM_Reject, |
| 20233 | // Label 1423: @50887 |
| 20234 | GIM_Reject, |
| 20235 | // Label 1414: @50888 |
| 20236 | GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(50965), |
| 20237 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 20238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 20239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 20240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 20241 | GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(50943), // Rule ID 990 // |
| 20242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 20243 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20244 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20245 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 20246 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20247 | // (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 20248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQP), |
| 20249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 20250 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi |
| 20251 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 20252 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 20253 | GIR_RootConstrainSelectedInstOperands, |
| 20254 | // GIR_Coverage, 990, |
| 20255 | GIR_EraseRootFromParent_Done, |
| 20256 | // Label 1429: @50943 |
| 20257 | GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(50964), // Rule ID 988 // |
| 20258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 20259 | // (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 20260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQP), |
| 20261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 20262 | GIR_RootToRootCopy, /*OpIdx*/3, // RSTi |
| 20263 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 20264 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 20265 | GIR_RootConstrainSelectedInstOperands, |
| 20266 | // GIR_Coverage, 988, |
| 20267 | GIR_EraseRootFromParent_Done, |
| 20268 | // Label 1430: @50964 |
| 20269 | GIM_Reject, |
| 20270 | // Label 1428: @50965 |
| 20271 | GIM_Reject, |
| 20272 | // Label 1415: @50966 |
| 20273 | GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(51043), |
| 20274 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 20275 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20276 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20278 | GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(51021), // Rule ID 790 // |
| 20279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20281 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20282 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 20283 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20284 | // (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi)) => (XVMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 20285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBADP), |
| 20286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20287 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 20288 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20289 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20290 | GIR_RootConstrainSelectedInstOperands, |
| 20291 | // GIR_Coverage, 790, |
| 20292 | GIR_EraseRootFromParent_Done, |
| 20293 | // Label 1432: @51021 |
| 20294 | GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(51042), // Rule ID 786 // |
| 20295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20296 | // (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi) => (XVMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 20297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDADP), |
| 20298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20299 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 20300 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20301 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20302 | GIR_RootConstrainSelectedInstOperands, |
| 20303 | // GIR_Coverage, 786, |
| 20304 | GIR_EraseRootFromParent_Done, |
| 20305 | // Label 1433: @51042 |
| 20306 | GIM_Reject, |
| 20307 | // Label 1431: @51043 |
| 20308 | GIM_Reject, |
| 20309 | // Label 1416: @51044 |
| 20310 | GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(51144), |
| 20311 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20312 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20313 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20314 | GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(51099), // Rule ID 792 // |
| 20315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20317 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 20318 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20319 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20320 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20321 | // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi)) => (XVMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 20322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBASP), |
| 20323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20324 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 20325 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20326 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20327 | GIR_RootConstrainSelectedInstOperands, |
| 20328 | // GIR_Coverage, 792, |
| 20329 | GIR_EraseRootFromParent_Done, |
| 20330 | // Label 1435: @51099 |
| 20331 | GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(51124), // Rule ID 788 // |
| 20332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20334 | // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi) => (XVMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 20335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDASP), |
| 20336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20337 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 20338 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 20339 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 20340 | GIR_RootConstrainSelectedInstOperands, |
| 20341 | // GIR_Coverage, 788, |
| 20342 | GIR_EraseRootFromParent_Done, |
| 20343 | // Label 1436: @51124 |
| 20344 | GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(51143), // Rule ID 289 // |
| 20345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 20346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 20347 | // (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, v4f32:{ *:[v4f32] }:$RB) => (VMADDFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, v4f32:{ *:[v4f32] }:$RB) |
| 20348 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMADDFP), |
| 20349 | GIR_RootConstrainSelectedInstOperands, |
| 20350 | // GIR_Coverage, 289, |
| 20351 | GIR_Done, |
| 20352 | // Label 1437: @51143 |
| 20353 | GIM_Reject, |
| 20354 | // Label 1434: @51144 |
| 20355 | GIM_Reject, |
| 20356 | // Label 1417: @51145 |
| 20357 | GIM_Reject, |
| 20358 | // Label 43: @51146 |
| 20359 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1443*/ GIMT_Encode4(51415), |
| 20360 | /*GILLT_s32*//*Label 1438*/ GIMT_Encode4(51177), |
| 20361 | /*GILLT_s64*//*Label 1439*/ GIMT_Encode4(51251), |
| 20362 | /*GILLT_s128*//*Label 1440*/ GIMT_Encode4(51329), |
| 20363 | /*GILLT_v2s64*//*Label 1441*/ GIMT_Encode4(51355), |
| 20364 | /*GILLT_v4s32*//*Label 1442*/ GIMT_Encode4(51385), |
| 20365 | // Label 1438: @51177 |
| 20366 | GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(51250), |
| 20367 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 20368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 20369 | GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(51207), // Rule ID 949 // |
| 20370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20372 | // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSDIVSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20373 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVSP), |
| 20374 | GIR_RootConstrainSelectedInstOperands, |
| 20375 | // GIR_Coverage, 949, |
| 20376 | GIR_Done, |
| 20377 | // Label 1445: @51207 |
| 20378 | GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(51230), // Rule ID 240 // |
| 20379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20381 | // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) |
| 20382 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIVS), |
| 20383 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20384 | GIR_RootConstrainSelectedInstOperands, |
| 20385 | // GIR_Coverage, 240, |
| 20386 | GIR_Done, |
| 20387 | // Label 1446: @51230 |
| 20388 | GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(51249), // Rule ID 588 // |
| 20389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 20391 | // (fdiv:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSDIV:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 20392 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSDIV), |
| 20393 | GIR_RootConstrainSelectedInstOperands, |
| 20394 | // GIR_Coverage, 588, |
| 20395 | GIR_Done, |
| 20396 | // Label 1447: @51249 |
| 20397 | GIM_Reject, |
| 20398 | // Label 1444: @51250 |
| 20399 | GIM_Reject, |
| 20400 | // Label 1439: @51251 |
| 20401 | GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(51328), |
| 20402 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 20403 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20404 | GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(51285), // Rule ID 801 // |
| 20405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20407 | // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSDIVDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20408 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVDP), |
| 20409 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20410 | GIR_RootConstrainSelectedInstOperands, |
| 20411 | // GIR_Coverage, 801, |
| 20412 | GIR_Done, |
| 20413 | // Label 1449: @51285 |
| 20414 | GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(51308), // Rule ID 238 // |
| 20415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20417 | // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FDIV:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) |
| 20418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIV), |
| 20419 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20420 | GIR_RootConstrainSelectedInstOperands, |
| 20421 | // GIR_Coverage, 238, |
| 20422 | GIR_Done, |
| 20423 | // Label 1450: @51308 |
| 20424 | GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(51327), // Rule ID 567 // |
| 20425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 20427 | // (fdiv:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDDIV:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 20428 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDDIV), |
| 20429 | GIR_RootConstrainSelectedInstOperands, |
| 20430 | // GIR_Coverage, 567, |
| 20431 | GIR_Done, |
| 20432 | // Label 1451: @51327 |
| 20433 | GIM_Reject, |
| 20434 | // Label 1448: @51328 |
| 20435 | GIM_Reject, |
| 20436 | // Label 1440: @51329 |
| 20437 | GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(51354), // Rule ID 984 // |
| 20438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 20439 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 20440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 20441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 20442 | // (fdiv:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 20443 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVQP), |
| 20444 | GIR_RootConstrainSelectedInstOperands, |
| 20445 | // GIR_Coverage, 984, |
| 20446 | GIR_Done, |
| 20447 | // Label 1452: @51354 |
| 20448 | GIM_Reject, |
| 20449 | // Label 1441: @51355 |
| 20450 | GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(51384), // Rule ID 810 // |
| 20451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20452 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 20453 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20455 | // (fdiv:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVDIVDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 20456 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP), |
| 20457 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20458 | GIR_RootConstrainSelectedInstOperands, |
| 20459 | // GIR_Coverage, 810, |
| 20460 | GIR_Done, |
| 20461 | // Label 1453: @51384 |
| 20462 | GIM_Reject, |
| 20463 | // Label 1442: @51385 |
| 20464 | GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(51414), // Rule ID 812 // |
| 20465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20466 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 20467 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 20469 | // (fdiv:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVDIVSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 20470 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP), |
| 20471 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20472 | GIR_RootConstrainSelectedInstOperands, |
| 20473 | // GIR_Coverage, 812, |
| 20474 | GIR_Done, |
| 20475 | // Label 1454: @51414 |
| 20476 | GIM_Reject, |
| 20477 | // Label 1443: @51415 |
| 20478 | GIM_Reject, |
| 20479 | // Label 44: @51416 |
| 20480 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1460*/ GIMT_Encode4(53805), |
| 20481 | /*GILLT_s32*//*Label 1455*/ GIMT_Encode4(51447), |
| 20482 | /*GILLT_s64*//*Label 1456*/ GIMT_Encode4(52139), |
| 20483 | /*GILLT_s128*//*Label 1457*/ GIMT_Encode4(52793), |
| 20484 | /*GILLT_v2s64*//*Label 1458*/ GIMT_Encode4(53201), |
| 20485 | /*GILLT_v4s32*//*Label 1459*/ GIMT_Encode4(53487), |
| 20486 | // Label 1455: @51447 |
| 20487 | GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(52138), |
| 20488 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 20489 | GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(51520), // Rule ID 963 // |
| 20490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20492 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20493 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20494 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20495 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20496 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20497 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20498 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20499 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20500 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20501 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi))) => (XSNMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBASP), |
| 20503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20504 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 20505 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20506 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20507 | GIR_RootConstrainSelectedInstOperands, |
| 20508 | // GIR_Coverage, 963, |
| 20509 | GIR_EraseRootFromParent_Done, |
| 20510 | // Label 1462: @51520 |
| 20511 | GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(51585), // Rule ID 962 // |
| 20512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20513 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20514 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20515 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20516 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20517 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20518 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20519 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20520 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20521 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20522 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20523 | // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi))) => (XSNMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBASP), |
| 20525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 20527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20528 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20529 | GIR_RootConstrainSelectedInstOperands, |
| 20530 | // GIR_Coverage, 962, |
| 20531 | GIR_EraseRootFromParent_Done, |
| 20532 | // Label 1463: @51585 |
| 20533 | GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(51638), // Rule ID 961 // |
| 20534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20536 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20537 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20538 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20539 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20540 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20541 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20542 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi)) => (XSNMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDASP), |
| 20544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 20546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20547 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20548 | GIR_RootConstrainSelectedInstOperands, |
| 20549 | // GIR_Coverage, 961, |
| 20550 | GIR_EraseRootFromParent_Done, |
| 20551 | // Label 1464: @51638 |
| 20552 | GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(51691), // Rule ID 960 // |
| 20553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20555 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20556 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20557 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20558 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20559 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20560 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20561 | // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi)) => (XSNMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 20562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDASP), |
| 20563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 20565 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20567 | GIR_RootConstrainSelectedInstOperands, |
| 20568 | // GIR_Coverage, 960, |
| 20569 | GIR_EraseRootFromParent_Done, |
| 20570 | // Label 1465: @51691 |
| 20571 | GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(51728), // Rule ID 835 // |
| 20572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20574 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20575 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 20576 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20577 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20578 | // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$XB)) => (XSNABSDPs:{ *:[f32] } f32:{ *:[f32] }:$XB) |
| 20579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDPs), |
| 20580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20581 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 20582 | GIR_RootConstrainSelectedInstOperands, |
| 20583 | // GIR_Coverage, 835, |
| 20584 | GIR_EraseRootFromParent_Done, |
| 20585 | // Label 1466: @51728 |
| 20586 | GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(51789), // Rule ID 1908 // |
| 20587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 20588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20589 | // (fneg:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSNEGDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 20590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 20591 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 20592 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 20593 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20594 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 20595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 20596 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSNEGDP), |
| 20597 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 20598 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 20599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 20601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 20602 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 20603 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 20604 | // GIR_Coverage, 1908, |
| 20605 | GIR_EraseRootFromParent_Done, |
| 20606 | // Label 1467: @51789 |
| 20607 | GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(51854), // Rule ID 230 // |
| 20608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20610 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20611 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20612 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20613 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20614 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20615 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20616 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20617 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20618 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20619 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB))) => (FNMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 20620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUBS), |
| 20621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20622 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20624 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB |
| 20625 | GIR_RootConstrainSelectedInstOperands, |
| 20626 | // GIR_Coverage, 230, |
| 20627 | GIR_EraseRootFromParent_Done, |
| 20628 | // Label 1468: @51854 |
| 20629 | GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(51919), // Rule ID 229 // |
| 20630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20632 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20633 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20634 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20635 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20636 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20637 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20638 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20639 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 20640 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20641 | // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB))) => (FNMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 20642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUBS), |
| 20643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20644 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20645 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20646 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB |
| 20647 | GIR_RootConstrainSelectedInstOperands, |
| 20648 | // GIR_Coverage, 229, |
| 20649 | GIR_EraseRootFromParent_Done, |
| 20650 | // Label 1469: @51919 |
| 20651 | GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(51972), // Rule ID 226 // |
| 20652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20654 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20655 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20656 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20657 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20658 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20659 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20660 | // (fneg:{ *:[f32] } (fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)) => (FNMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 20661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS), |
| 20662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20664 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20665 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB |
| 20666 | GIR_RootConstrainSelectedInstOperands, |
| 20667 | // GIR_Coverage, 226, |
| 20668 | GIR_EraseRootFromParent_Done, |
| 20669 | // Label 1470: @51972 |
| 20670 | GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(52025), // Rule ID 225 // |
| 20671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20674 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20676 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20677 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20678 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20679 | // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB)) => (FNMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 20680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADDS), |
| 20681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB |
| 20685 | GIR_RootConstrainSelectedInstOperands, |
| 20686 | // GIR_Coverage, 225, |
| 20687 | GIR_EraseRootFromParent_Done, |
| 20688 | // Label 1471: @52025 |
| 20689 | GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(52062), // Rule ID 162 // |
| 20690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20692 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20693 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 20694 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20695 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20696 | // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$RB)) => (FNABSS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 20697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSS), |
| 20698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 20699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 20700 | GIR_RootConstrainSelectedInstOperands, |
| 20701 | // GIR_Coverage, 162, |
| 20702 | GIR_EraseRootFromParent_Done, |
| 20703 | // Label 1472: @52062 |
| 20704 | GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(52099), // Rule ID 591 // |
| 20705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 20707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20708 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 20709 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 20710 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20711 | // (fneg:{ *:[f32] } (fabs:{ *:[f32] } f32:{ *:[f32] }:$RA)) => (EFSNABS:{ *:[f32] } f32:{ *:[f32] }:$RA) |
| 20712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EFSNABS), |
| 20713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 20714 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 20715 | GIR_RootConstrainSelectedInstOperands, |
| 20716 | // GIR_Coverage, 591, |
| 20717 | GIR_EraseRootFromParent_Done, |
| 20718 | // Label 1473: @52099 |
| 20719 | GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(52118), // Rule ID 164 // |
| 20720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 20722 | // (fneg:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FNEGS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 20723 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FNEGS), |
| 20724 | GIR_RootConstrainSelectedInstOperands, |
| 20725 | // GIR_Coverage, 164, |
| 20726 | GIR_Done, |
| 20727 | // Label 1474: @52118 |
| 20728 | GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(52137), // Rule ID 592 // |
| 20729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 20731 | // (fneg:{ *:[f32] } f32:{ *:[f32] }:$RA) => (EFSNEG:{ *:[f32] } f32:{ *:[f32] }:$RA) |
| 20732 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSNEG), |
| 20733 | GIR_RootConstrainSelectedInstOperands, |
| 20734 | // GIR_Coverage, 592, |
| 20735 | GIR_Done, |
| 20736 | // Label 1475: @52137 |
| 20737 | GIM_Reject, |
| 20738 | // Label 1461: @52138 |
| 20739 | GIM_Reject, |
| 20740 | // Label 1456: @52139 |
| 20741 | GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(52792), |
| 20742 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 20743 | GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(52212), // Rule ID 784 // |
| 20744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20746 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20747 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20748 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20749 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20750 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20751 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20752 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20753 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20754 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20755 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi))) => (XSNMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBADP), |
| 20757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20758 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 20759 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20760 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20761 | GIR_RootConstrainSelectedInstOperands, |
| 20762 | // GIR_Coverage, 784, |
| 20763 | GIR_EraseRootFromParent_Done, |
| 20764 | // Label 1477: @52212 |
| 20765 | GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(52277), // Rule ID 783 // |
| 20766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20768 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20769 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20770 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20771 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20772 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20773 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20774 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20775 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20776 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20777 | // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi))) => (XSNMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBADP), |
| 20779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 20781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20783 | GIR_RootConstrainSelectedInstOperands, |
| 20784 | // GIR_Coverage, 783, |
| 20785 | GIR_EraseRootFromParent_Done, |
| 20786 | // Label 1478: @52277 |
| 20787 | GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(52330), // Rule ID 782 // |
| 20788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20790 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20791 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20792 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20793 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20794 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20795 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20796 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi)) => (XSNMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDADP), |
| 20798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20799 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 20800 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20802 | GIR_RootConstrainSelectedInstOperands, |
| 20803 | // GIR_Coverage, 782, |
| 20804 | GIR_EraseRootFromParent_Done, |
| 20805 | // Label 1479: @52330 |
| 20806 | GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(52383), // Rule ID 781 // |
| 20807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20809 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20810 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20811 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20812 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20813 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20814 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20815 | // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi)) => (XSNMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 20816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDADP), |
| 20817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 20819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 20820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 20821 | GIR_RootConstrainSelectedInstOperands, |
| 20822 | // GIR_Coverage, 781, |
| 20823 | GIR_EraseRootFromParent_Done, |
| 20824 | // Label 1480: @52383 |
| 20825 | GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(52420), // Rule ID 834 // |
| 20826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 20830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20831 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20832 | // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$XB)) => (XSNABSDP:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 20833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSDP), |
| 20834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 20835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 20836 | GIR_RootConstrainSelectedInstOperands, |
| 20837 | // GIR_Coverage, 834, |
| 20838 | GIR_EraseRootFromParent_Done, |
| 20839 | // Label 1481: @52420 |
| 20840 | GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(52443), // Rule ID 836 // |
| 20841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 20842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 20843 | // (fneg:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSNEGDP:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 20844 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSNEGDP), |
| 20845 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 20846 | GIR_RootConstrainSelectedInstOperands, |
| 20847 | // GIR_Coverage, 836, |
| 20848 | GIR_Done, |
| 20849 | // Label 1482: @52443 |
| 20850 | GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(52508), // Rule ID 228 // |
| 20851 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20853 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20854 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20855 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20856 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20857 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20858 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20859 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20860 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20861 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20862 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB))) => (FNMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 20863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUB), |
| 20864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20866 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB |
| 20868 | GIR_RootConstrainSelectedInstOperands, |
| 20869 | // GIR_Coverage, 228, |
| 20870 | GIR_EraseRootFromParent_Done, |
| 20871 | // Label 1483: @52508 |
| 20872 | GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(52573), // Rule ID 227 // |
| 20873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20875 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20876 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20877 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20878 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20879 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20880 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 20881 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20882 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 20883 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 20884 | // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB))) => (FNMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 20885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMSUB), |
| 20886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20887 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20889 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // FRB |
| 20890 | GIR_RootConstrainSelectedInstOperands, |
| 20891 | // GIR_Coverage, 227, |
| 20892 | GIR_EraseRootFromParent_Done, |
| 20893 | // Label 1484: @52573 |
| 20894 | GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(52626), // Rule ID 224 // |
| 20895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20897 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20898 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 20899 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20900 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20901 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20902 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20903 | // (fneg:{ *:[f64] } (fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)) => (FNMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 20904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD), |
| 20905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20906 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20907 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20908 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB |
| 20909 | GIR_RootConstrainSelectedInstOperands, |
| 20910 | // GIR_Coverage, 224, |
| 20911 | GIR_EraseRootFromParent_Done, |
| 20912 | // Label 1485: @52626 |
| 20913 | GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(52679), // Rule ID 223 // |
| 20914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20916 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20917 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 20918 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20919 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20920 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20921 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20922 | // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB)) => (FNMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 20923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNMADD), |
| 20924 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 20925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRA |
| 20926 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // FRC |
| 20927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // FRB |
| 20928 | GIR_RootConstrainSelectedInstOperands, |
| 20929 | // GIR_Coverage, 223, |
| 20930 | GIR_EraseRootFromParent_Done, |
| 20931 | // Label 1486: @52679 |
| 20932 | GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(52716), // Rule ID 163 // |
| 20933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20935 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20936 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 20937 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20938 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20939 | // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$RB)) => (FNABSD:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 20940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FNABSD), |
| 20941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 20942 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 20943 | GIR_RootConstrainSelectedInstOperands, |
| 20944 | // GIR_Coverage, 163, |
| 20945 | GIR_EraseRootFromParent_Done, |
| 20946 | // Label 1487: @52716 |
| 20947 | GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(52753), // Rule ID 570 // |
| 20948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 20950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20951 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 20952 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 20953 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 20954 | // (fneg:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$RA)) => (EFDNABS:{ *:[f64] } f64:{ *:[f64] }:$RA) |
| 20955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::EFDNABS), |
| 20956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 20957 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 20958 | GIR_RootConstrainSelectedInstOperands, |
| 20959 | // GIR_Coverage, 570, |
| 20960 | GIR_EraseRootFromParent_Done, |
| 20961 | // Label 1488: @52753 |
| 20962 | GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(52772), // Rule ID 165 // |
| 20963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 20964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 20965 | // (fneg:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FNEGD:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 20966 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FNEGD), |
| 20967 | GIR_RootConstrainSelectedInstOperands, |
| 20968 | // GIR_Coverage, 165, |
| 20969 | GIR_Done, |
| 20970 | // Label 1489: @52772 |
| 20971 | GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(52791), // Rule ID 571 // |
| 20972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 20973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 20974 | // (fneg:{ *:[f64] } f64:{ *:[f64] }:$RA) => (EFDNEG:{ *:[f64] } f64:{ *:[f64] }:$RA) |
| 20975 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDNEG), |
| 20976 | GIR_RootConstrainSelectedInstOperands, |
| 20977 | // GIR_Coverage, 571, |
| 20978 | GIR_Done, |
| 20979 | // Label 1490: @52791 |
| 20980 | GIM_Reject, |
| 20981 | // Label 1476: @52792 |
| 20982 | GIM_Reject, |
| 20983 | // Label 1457: @52793 |
| 20984 | GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(53200), |
| 20985 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 20986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 20987 | GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(52874), // Rule ID 1003 // |
| 20988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 20989 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20990 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 20991 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, |
| 20992 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd), |
| 20993 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, |
| 20994 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, |
| 20995 | GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_s128, |
| 20996 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/4, // MIs[2] |
| 20997 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 20998 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128, |
| 20999 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21000 | // (fneg:{ *:[f128] } (intrinsic_wo_chain:{ *:[f128] } 9891:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi))) => (XSNMSUBQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 21001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBQPO), |
| 21002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21003 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RSTi |
| 21004 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RA |
| 21005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RB |
| 21006 | GIR_RootConstrainSelectedInstOperands, |
| 21007 | // GIR_Coverage, 1003, |
| 21008 | GIR_EraseRootFromParent_Done, |
| 21009 | // Label 1492: @52874 |
| 21010 | GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(52931), // Rule ID 1002 // |
| 21011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21012 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21013 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 21014 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, |
| 21015 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::ppc_fmaf128_round_to_odd), |
| 21016 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, |
| 21017 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, |
| 21018 | GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_s128, |
| 21019 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21020 | // (fneg:{ *:[f128] } (intrinsic_wo_chain:{ *:[f128] } 9891:{ *:[iPTR] }, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi)) => (XSNMADDQPO:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 21021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDQPO), |
| 21022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // RSTi |
| 21024 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RA |
| 21025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RB |
| 21026 | GIR_RootConstrainSelectedInstOperands, |
| 21027 | // GIR_Coverage, 1002, |
| 21028 | GIR_EraseRootFromParent_Done, |
| 21029 | // Label 1493: @52931 |
| 21030 | GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(52992), // Rule ID 994 // |
| 21031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21032 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21033 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21034 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 21035 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, |
| 21036 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, |
| 21037 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21038 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21039 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128, |
| 21040 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21041 | // (fneg:{ *:[f128] } (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi))) => (XSNMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 21042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBQP), |
| 21043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21044 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RSTi |
| 21045 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 21046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 21047 | GIR_RootConstrainSelectedInstOperands, |
| 21048 | // GIR_Coverage, 994, |
| 21049 | GIR_EraseRootFromParent_Done, |
| 21050 | // Label 1494: @52992 |
| 21051 | GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(53053), // Rule ID 993 // |
| 21052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21053 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21054 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 21055 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 21056 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, |
| 21057 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, |
| 21058 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21059 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21060 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s128, |
| 21061 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21062 | // (fneg:{ *:[f128] } (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi))) => (XSNMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 21063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMSUBQP), |
| 21064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21065 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RSTi |
| 21066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 21067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 21068 | GIR_RootConstrainSelectedInstOperands, |
| 21069 | // GIR_Coverage, 993, |
| 21070 | GIR_EraseRootFromParent_Done, |
| 21071 | // Label 1495: @53053 |
| 21072 | GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(53102), // Rule ID 992 // |
| 21073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21074 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21075 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21076 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 21077 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, |
| 21078 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, |
| 21079 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21080 | // (fneg:{ *:[f128] } (fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi)) => (XSNMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 21081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDQP), |
| 21082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RSTi |
| 21084 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 21085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 21086 | GIR_RootConstrainSelectedInstOperands, |
| 21087 | // GIR_Coverage, 992, |
| 21088 | GIR_EraseRootFromParent_Done, |
| 21089 | // Label 1496: @53102 |
| 21090 | GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(53151), // Rule ID 991 // |
| 21091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21092 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21093 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 21094 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 21095 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s128, |
| 21096 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s128, |
| 21097 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21098 | // (fneg:{ *:[f128] } (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi)) => (XSNMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 21099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNMADDQP), |
| 21100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // RSTi |
| 21102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 21103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RB |
| 21104 | GIR_RootConstrainSelectedInstOperands, |
| 21105 | // GIR_Coverage, 991, |
| 21106 | GIR_EraseRootFromParent_Done, |
| 21107 | // Label 1497: @53151 |
| 21108 | GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(53184), // Rule ID 975 // |
| 21109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21110 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21111 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 21112 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 21113 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21114 | // (fneg:{ *:[f128] } (fabs:{ *:[f128] } f128:{ *:[f128] }:$RB)) => (XSNABSQP:{ *:[f128] } f128:{ *:[f128] }:$RB) |
| 21115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSNABSQP), |
| 21116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RB |
| 21118 | GIR_RootConstrainSelectedInstOperands, |
| 21119 | // GIR_Coverage, 975, |
| 21120 | GIR_EraseRootFromParent_Done, |
| 21121 | // Label 1498: @53184 |
| 21122 | GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(53199), // Rule ID 976 // |
| 21123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21124 | // (fneg:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSNEGQP:{ *:[f128] } f128:{ *:[f128] }:$RB) |
| 21125 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSNEGQP), |
| 21126 | GIR_RootConstrainSelectedInstOperands, |
| 21127 | // GIR_Coverage, 976, |
| 21128 | GIR_Done, |
| 21129 | // Label 1499: @53199 |
| 21130 | GIM_Reject, |
| 21131 | // Label 1491: @53200 |
| 21132 | GIM_Reject, |
| 21133 | // Label 1458: @53201 |
| 21134 | GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(53486), |
| 21135 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21137 | GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(53274), // Rule ID 797 // |
| 21138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21140 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21141 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21142 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21143 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21144 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21145 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21146 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21147 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21148 | // (fneg:{ *:[v2f64] } (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi))) => (XVNMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 21149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBADP), |
| 21150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21151 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 21152 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21153 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21154 | GIR_RootConstrainSelectedInstOperands, |
| 21155 | // GIR_Coverage, 797, |
| 21156 | GIR_EraseRootFromParent_Done, |
| 21157 | // Label 1501: @53274 |
| 21158 | GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(53335), // Rule ID 796 // |
| 21159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21161 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 21162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21163 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21164 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21165 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21166 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21167 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21168 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21169 | // (fneg:{ *:[v2f64] } (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi))) => (XVNMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 21170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBADP), |
| 21171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21172 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 21173 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21175 | GIR_RootConstrainSelectedInstOperands, |
| 21176 | // GIR_Coverage, 796, |
| 21177 | GIR_EraseRootFromParent_Done, |
| 21178 | // Label 1502: @53335 |
| 21179 | GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(53384), // Rule ID 794 // |
| 21180 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21181 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21182 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21184 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21185 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21186 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21187 | // (fneg:{ *:[v2f64] } (fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi)) => (XVNMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 21188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMADDADP), |
| 21189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21190 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 21191 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21192 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21193 | GIR_RootConstrainSelectedInstOperands, |
| 21194 | // GIR_Coverage, 794, |
| 21195 | GIR_EraseRootFromParent_Done, |
| 21196 | // Label 1503: @53384 |
| 21197 | GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(53433), // Rule ID 793 // |
| 21198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 21201 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21202 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21203 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21204 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21205 | // (fneg:{ *:[v2f64] } (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi)) => (XVNMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 21206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMADDADP), |
| 21207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 21209 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21210 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21211 | GIR_RootConstrainSelectedInstOperands, |
| 21212 | // GIR_Coverage, 793, |
| 21213 | GIR_EraseRootFromParent_Done, |
| 21214 | // Label 1504: @53433 |
| 21215 | GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(53466), // Rule ID 842 // |
| 21216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21217 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21218 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 21219 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21220 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21221 | // (fneg:{ *:[v2f64] } (fabs:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB)) => (XVNABSDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 21222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNABSDP), |
| 21223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 21225 | GIR_RootConstrainSelectedInstOperands, |
| 21226 | // GIR_Coverage, 842, |
| 21227 | GIR_EraseRootFromParent_Done, |
| 21228 | // Label 1505: @53466 |
| 21229 | GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(53485), // Rule ID 844 // |
| 21230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21231 | // (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVNEGDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 21232 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVNEGDP), |
| 21233 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21234 | GIR_RootConstrainSelectedInstOperands, |
| 21235 | // GIR_Coverage, 844, |
| 21236 | GIR_Done, |
| 21237 | // Label 1506: @53485 |
| 21238 | GIM_Reject, |
| 21239 | // Label 1500: @53486 |
| 21240 | GIM_Reject, |
| 21241 | // Label 1459: @53487 |
| 21242 | GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(53804), |
| 21243 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21244 | GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(53560), // Rule ID 799 // |
| 21245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21247 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21248 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21249 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21250 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21251 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21252 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21253 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21254 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21255 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21256 | // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi))) => (XVNMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 21257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBASP), |
| 21258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21259 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 21260 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21261 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21262 | GIR_RootConstrainSelectedInstOperands, |
| 21263 | // GIR_Coverage, 799, |
| 21264 | GIR_EraseRootFromParent_Done, |
| 21265 | // Label 1508: @53560 |
| 21266 | GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(53625), // Rule ID 798 // |
| 21267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21269 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21270 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 21271 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21272 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21273 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21274 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21275 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21276 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21277 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21278 | // (fneg:{ *:[v4f32] } (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi))) => (XVNMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 21279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMSUBASP), |
| 21280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21281 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // XTi |
| 21282 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21284 | GIR_RootConstrainSelectedInstOperands, |
| 21285 | // GIR_Coverage, 798, |
| 21286 | GIR_EraseRootFromParent_Done, |
| 21287 | // Label 1509: @53625 |
| 21288 | GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(53678), // Rule ID 795 // |
| 21289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21291 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21292 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21293 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21294 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21295 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21296 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21297 | // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi)) => (XVNMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 21298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNMADDASP), |
| 21299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21300 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // XTi |
| 21301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XA |
| 21302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // XB |
| 21303 | GIR_RootConstrainSelectedInstOperands, |
| 21304 | // GIR_Coverage, 795, |
| 21305 | GIR_EraseRootFromParent_Done, |
| 21306 | // Label 1510: @53678 |
| 21307 | GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(53715), // Rule ID 843 // |
| 21308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21310 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21311 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 21312 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21313 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 21314 | // (fneg:{ *:[v4f32] } (fabs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB)) => (XVNABSSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 21315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVNABSSP), |
| 21316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21317 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XB |
| 21318 | GIR_RootConstrainSelectedInstOperands, |
| 21319 | // GIR_Coverage, 843, |
| 21320 | GIR_EraseRootFromParent_Done, |
| 21321 | // Label 1511: @53715 |
| 21322 | GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(53738), // Rule ID 845 // |
| 21323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21325 | // (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVNEGSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 21326 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVNEGSP), |
| 21327 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21328 | GIR_RootConstrainSelectedInstOperands, |
| 21329 | // GIR_Coverage, 845, |
| 21330 | GIR_Done, |
| 21331 | // Label 1512: @53738 |
| 21332 | GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(53803), // Rule ID 290 // |
| 21333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 21334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21335 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21336 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 21337 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21338 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21339 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21340 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2] |
| 21341 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 21342 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21343 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 21344 | // (fneg:{ *:[v4f32] } (fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RB))) => (VNMSUBFP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$RA, v4f32:{ *:[v4f32] }:$RC, v4f32:{ *:[v4f32] }:$RB) |
| 21345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VNMSUBFP), |
| 21346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RT] |
| 21347 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RA |
| 21348 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RC |
| 21349 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RB |
| 21350 | GIR_RootConstrainSelectedInstOperands, |
| 21351 | // GIR_Coverage, 290, |
| 21352 | GIR_EraseRootFromParent_Done, |
| 21353 | // Label 1513: @53803 |
| 21354 | GIM_Reject, |
| 21355 | // Label 1507: @53804 |
| 21356 | GIM_Reject, |
| 21357 | // Label 1460: @53805 |
| 21358 | GIM_Reject, |
| 21359 | // Label 45: @53806 |
| 21360 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 1516*/ GIMT_Encode4(53966), |
| 21361 | /*GILLT_s64*//*Label 1514*/ GIMT_Encode4(53825), |
| 21362 | /*GILLT_s128*//*Label 1515*/ GIMT_Encode4(53900), |
| 21363 | // Label 1514: @53825 |
| 21364 | GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(53899), |
| 21365 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21366 | GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(53856), // Rule ID 1892 // |
| 21367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 21368 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 21369 | // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$src, VSFRC:{ *:[i32] }) |
| 21370 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21371 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSFRCRegClassID), |
| 21372 | // GIR_Coverage, 1892, |
| 21373 | GIR_Done, |
| 21374 | // Label 1518: @53856 |
| 21375 | GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(53875), // Rule ID 557 // |
| 21376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 21378 | // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$RB) => (EFDCFS:{ *:[f64] } f32:{ *:[f32] }:$RB) |
| 21379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCFS), |
| 21380 | GIR_RootConstrainSelectedInstOperands, |
| 21381 | // GIR_Coverage, 557, |
| 21382 | GIR_Done, |
| 21383 | // Label 1519: @53875 |
| 21384 | GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(53898), // Rule ID 1252 // |
| 21385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 21386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 21387 | // (fpextend:{ *:[f64] } f32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$src, F8RC:{ *:[i32] }) |
| 21388 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21389 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::F8RCRegClassID), |
| 21390 | // GIR_Coverage, 1252, |
| 21391 | GIR_Done, |
| 21392 | // Label 1520: @53898 |
| 21393 | GIM_Reject, |
| 21394 | // Label 1517: @53899 |
| 21395 | GIM_Reject, |
| 21396 | // Label 1515: @53900 |
| 21397 | GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(53922), // Rule ID 1005 // |
| 21398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21399 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21401 | // (fpextend:{ *:[f128] } f64:{ *:[f64] }:$RB) => (XSCVDPQP:{ *:[f128] } f64:{ *:[f64] }:$RB) |
| 21402 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSCVDPQP), |
| 21403 | GIR_RootConstrainSelectedInstOperands, |
| 21404 | // GIR_Coverage, 1005, |
| 21405 | GIR_Done, |
| 21406 | // Label 1521: @53922 |
| 21407 | GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(53965), // Rule ID 2242 // |
| 21408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21409 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21411 | // (fpextend:{ *:[f128] } f32:{ *:[f32] }:$src) => (XSCVDPQP:{ *:[f128] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$src, VFRC:{ *:[i32] })) |
| 21412 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21413 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21414 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21415 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21416 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVDPQP), |
| 21418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21419 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21420 | GIR_RootConstrainSelectedInstOperands, |
| 21421 | // GIR_Coverage, 2242, |
| 21422 | GIR_EraseRootFromParent_Done, |
| 21423 | // Label 1522: @53965 |
| 21424 | GIM_Reject, |
| 21425 | // Label 1516: @53966 |
| 21426 | GIM_Reject, |
| 21427 | // Label 46: @53967 |
| 21428 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1525*/ GIMT_Encode4(54123), |
| 21429 | /*GILLT_s32*//*Label 1523*/ GIMT_Encode4(53986), |
| 21430 | /*GILLT_s64*//*Label 1524*/ GIMT_Encode4(54100), |
| 21431 | // Label 1523: @53986 |
| 21432 | GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(54008), // Rule ID 952 // |
| 21433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 21434 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 21436 | // (fpround:{ *:[f32] } f64:{ *:[f64] }:$XB) => (XSRSP:{ *:[f32] } f64:{ *:[f64] }:$XB) |
| 21437 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRSP), |
| 21438 | GIR_RootConstrainSelectedInstOperands, |
| 21439 | // GIR_Coverage, 952, |
| 21440 | GIR_Done, |
| 21441 | // Label 1526: @54008 |
| 21442 | GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(54051), // Rule ID 2240 // |
| 21443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21444 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 21445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 21446 | // (fpround:{ *:[f32] } f128:{ *:[f128] }:$src) => (XSRSP:{ *:[f32] } (XSCVQPDPO:{ *:[f64] } ?:{ *:[f128] }:$src)) |
| 21447 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21448 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDPO), |
| 21449 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21450 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21451 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRSP), |
| 21453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 21454 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21455 | GIR_RootConstrainSelectedInstOperands, |
| 21456 | // GIR_Coverage, 2240, |
| 21457 | GIR_EraseRootFromParent_Done, |
| 21458 | // Label 1527: @54051 |
| 21459 | GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(54077), // Rule ID 155 // |
| 21460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 21461 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 21463 | // (fpround:{ *:[f32] } f64:{ *:[f64] }:$RB) => (FRSP:{ *:[f32] } f64:{ *:[f64] }:$RB) |
| 21464 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRSP), |
| 21465 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21466 | GIR_RootConstrainSelectedInstOperands, |
| 21467 | // GIR_Coverage, 155, |
| 21468 | GIR_Done, |
| 21469 | // Label 1528: @54077 |
| 21470 | GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(54099), // Rule ID 578 // |
| 21471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21472 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21474 | // (fpround:{ *:[f32] } f64:{ *:[f64] }:$RB) => (EFSCFD:{ *:[f32] } f64:{ *:[f64] }:$RB) |
| 21475 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCFD), |
| 21476 | GIR_RootConstrainSelectedInstOperands, |
| 21477 | // GIR_Coverage, 578, |
| 21478 | GIR_Done, |
| 21479 | // Label 1529: @54099 |
| 21480 | GIM_Reject, |
| 21481 | // Label 1524: @54100 |
| 21482 | GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(54122), // Rule ID 2238 // |
| 21483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21484 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 21485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VFRCRegClassID), |
| 21486 | // (fpround:{ *:[f64] } f128:{ *:[f128] }:$src) => (XSCVQPDP:{ *:[f64] } ?:{ *:[f128] }:$src) |
| 21487 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSCVQPDP), |
| 21488 | GIR_RootConstrainSelectedInstOperands, |
| 21489 | // GIR_Coverage, 2238, |
| 21490 | GIR_Done, |
| 21491 | // Label 1530: @54122 |
| 21492 | GIM_Reject, |
| 21493 | // Label 1525: @54123 |
| 21494 | GIM_Reject, |
| 21495 | // Label 47: @54124 |
| 21496 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1535*/ GIMT_Encode4(54383), |
| 21497 | /*GILLT_s32*//*Label 1531*/ GIMT_Encode4(54155), |
| 21498 | /*GILLT_s64*//*Label 1532*/ GIMT_Encode4(54260), GIMT_Encode4(0), |
| 21499 | /*GILLT_v2s64*//*Label 1533*/ GIMT_Encode4(54304), |
| 21500 | /*GILLT_v4s32*//*Label 1534*/ GIMT_Encode4(54331), |
| 21501 | // Label 1531: @54155 |
| 21502 | GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(54215), // Rule ID 2228 // |
| 21503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 21505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21506 | // (fp_to_sint:{ *:[i32] } f128:{ *:[f128] }:$src) => (MFVSRWZ:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[f64] } (XSCVQPSWZ:{ *:[f128] } ?:{ *:[f128] }:$src), VFRC:{ *:[i32] })) |
| 21507 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21508 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 21509 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVQPSWZ), |
| 21510 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21511 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21512 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21513 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21514 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21515 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21516 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ), |
| 21518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 21519 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21520 | GIR_RootConstrainSelectedInstOperands, |
| 21521 | // GIR_Coverage, 2228, |
| 21522 | GIR_EraseRootFromParent_Done, |
| 21523 | // Label 1536: @54215 |
| 21524 | GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(54237), // Rule ID 563 // |
| 21525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21526 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21528 | // (fp_to_sint:{ *:[i32] } f64:{ *:[f64] }:$RB) => (EFDCTSIZ:{ *:[i32] } f64:{ *:[f64] }:$RB) |
| 21529 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCTSIZ), |
| 21530 | GIR_RootConstrainSelectedInstOperands, |
| 21531 | // GIR_Coverage, 563, |
| 21532 | GIR_Done, |
| 21533 | // Label 1537: @54237 |
| 21534 | GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(54259), // Rule ID 584 // |
| 21535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21536 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21538 | // (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$RB) => (EFSCTSIZ:{ *:[i32] } f32:{ *:[f32] }:$RB) |
| 21539 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCTSIZ), |
| 21540 | GIR_RootConstrainSelectedInstOperands, |
| 21541 | // GIR_Coverage, 584, |
| 21542 | GIR_Done, |
| 21543 | // Label 1538: @54259 |
| 21544 | GIM_Reject, |
| 21545 | // Label 1532: @54260 |
| 21546 | GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(54303), // Rule ID 2224 // |
| 21547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21548 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 21549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 21550 | // (fp_to_sint:{ *:[i64] } f128:{ *:[f128] }:$src) => (MFVRD:{ *:[i64] } (XSCVQPSDZ:{ *:[v4i32] } ?:{ *:[f128] }:$src)) |
| 21551 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21552 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVQPSDZ), |
| 21553 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21554 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVRD), |
| 21557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 21558 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21559 | GIR_RootConstrainSelectedInstOperands, |
| 21560 | // GIR_Coverage, 2224, |
| 21561 | GIR_EraseRootFromParent_Done, |
| 21562 | // Label 1539: @54303 |
| 21563 | GIM_Reject, |
| 21564 | // Label 1533: @54304 |
| 21565 | GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(54330), // Rule ID 868 // |
| 21566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21567 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21568 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21569 | // (fp_to_sint:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) => (XVCVDPSXDS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) |
| 21570 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVDPSXDS), |
| 21571 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21572 | GIR_RootConstrainSelectedInstOperands, |
| 21573 | // GIR_Coverage, 868, |
| 21574 | GIR_Done, |
| 21575 | // Label 1540: @54330 |
| 21576 | GIM_Reject, |
| 21577 | // Label 1534: @54331 |
| 21578 | GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(54382), |
| 21579 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21580 | GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(54362), // Rule ID 876 // |
| 21581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21583 | // (fp_to_sint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) => (XVCVSPSXWS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) |
| 21584 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSPSXWS), |
| 21585 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21586 | GIR_RootConstrainSelectedInstOperands, |
| 21587 | // GIR_Coverage, 876, |
| 21588 | GIR_Done, |
| 21589 | // Label 1542: @54362 |
| 21590 | GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(54381), // Rule ID 1398 // |
| 21591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 21592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21593 | // (fp_to_sint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$vA) => (VCTSXS_0:{ *:[v4i32] } ?:{ *:[v4f32] }:$vA) |
| 21594 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTSXS_0), |
| 21595 | GIR_RootConstrainSelectedInstOperands, |
| 21596 | // GIR_Coverage, 1398, |
| 21597 | GIR_Done, |
| 21598 | // Label 1543: @54381 |
| 21599 | GIM_Reject, |
| 21600 | // Label 1541: @54382 |
| 21601 | GIM_Reject, |
| 21602 | // Label 1535: @54383 |
| 21603 | GIM_Reject, |
| 21604 | // Label 48: @54384 |
| 21605 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1548*/ GIMT_Encode4(54643), |
| 21606 | /*GILLT_s32*//*Label 1544*/ GIMT_Encode4(54415), |
| 21607 | /*GILLT_s64*//*Label 1545*/ GIMT_Encode4(54520), GIMT_Encode4(0), |
| 21608 | /*GILLT_v2s64*//*Label 1546*/ GIMT_Encode4(54564), |
| 21609 | /*GILLT_v4s32*//*Label 1547*/ GIMT_Encode4(54591), |
| 21610 | // Label 1544: @54415 |
| 21611 | GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(54475), // Rule ID 2230 // |
| 21612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21613 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 21614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21615 | // (fp_to_uint:{ *:[i32] } f128:{ *:[f128] }:$src) => (MFVSRWZ:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[f64] } (XSCVQPUWZ:{ *:[f128] } ?:{ *:[f128] }:$src), VFRC:{ *:[i32] })) |
| 21616 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21617 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 21618 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSCVQPUWZ), |
| 21619 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21620 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21622 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21623 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21624 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRWZ), |
| 21627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 21628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21629 | GIR_RootConstrainSelectedInstOperands, |
| 21630 | // GIR_Coverage, 2230, |
| 21631 | GIR_EraseRootFromParent_Done, |
| 21632 | // Label 1549: @54475 |
| 21633 | GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(54497), // Rule ID 565 // |
| 21634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21635 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21637 | // (fp_to_uint:{ *:[i32] } f64:{ *:[f64] }:$RB) => (EFDCTUIZ:{ *:[i32] } f64:{ *:[f64] }:$RB) |
| 21638 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCTUIZ), |
| 21639 | GIR_RootConstrainSelectedInstOperands, |
| 21640 | // GIR_Coverage, 565, |
| 21641 | GIR_Done, |
| 21642 | // Label 1550: @54497 |
| 21643 | GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(54519), // Rule ID 586 // |
| 21644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21645 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21647 | // (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$RB) => (EFSCTUIZ:{ *:[i32] } f32:{ *:[f32] }:$RB) |
| 21648 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCTUIZ), |
| 21649 | GIR_RootConstrainSelectedInstOperands, |
| 21650 | // GIR_Coverage, 586, |
| 21651 | GIR_Done, |
| 21652 | // Label 1551: @54519 |
| 21653 | GIM_Reject, |
| 21654 | // Label 1545: @54520 |
| 21655 | GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(54563), // Rule ID 2226 // |
| 21656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21657 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 21658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 21659 | // (fp_to_uint:{ *:[i64] } f128:{ *:[f128] }:$src) => (MFVRD:{ *:[i64] } (XSCVQPUDZ:{ *:[v4i32] } ?:{ *:[f128] }:$src)) |
| 21660 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 21661 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSCVQPUDZ), |
| 21662 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21663 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21664 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVRD), |
| 21666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 21667 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21668 | GIR_RootConstrainSelectedInstOperands, |
| 21669 | // GIR_Coverage, 2226, |
| 21670 | GIR_EraseRootFromParent_Done, |
| 21671 | // Label 1552: @54563 |
| 21672 | GIM_Reject, |
| 21673 | // Label 1546: @54564 |
| 21674 | GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(54590), // Rule ID 871 // |
| 21675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21676 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21678 | // (fp_to_uint:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) => (XVCVDPUXDS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$XB) |
| 21679 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVDPUXDS), |
| 21680 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21681 | GIR_RootConstrainSelectedInstOperands, |
| 21682 | // GIR_Coverage, 871, |
| 21683 | GIR_Done, |
| 21684 | // Label 1553: @54590 |
| 21685 | GIM_Reject, |
| 21686 | // Label 1547: @54591 |
| 21687 | GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(54642), |
| 21688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21689 | GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(54622), // Rule ID 879 // |
| 21690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21692 | // (fp_to_uint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) => (XVCVSPUXWS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$XB) |
| 21693 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSPUXWS), |
| 21694 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21695 | GIR_RootConstrainSelectedInstOperands, |
| 21696 | // GIR_Coverage, 879, |
| 21697 | GIR_Done, |
| 21698 | // Label 1555: @54622 |
| 21699 | GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(54641), // Rule ID 1399 // |
| 21700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 21701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21702 | // (fp_to_uint:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$vA) => (VCTUXS_0:{ *:[v4i32] } ?:{ *:[v4f32] }:$vA) |
| 21703 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTUXS_0), |
| 21704 | GIR_RootConstrainSelectedInstOperands, |
| 21705 | // GIR_Coverage, 1399, |
| 21706 | GIR_Done, |
| 21707 | // Label 1556: @54641 |
| 21708 | GIM_Reject, |
| 21709 | // Label 1554: @54642 |
| 21710 | GIM_Reject, |
| 21711 | // Label 1548: @54643 |
| 21712 | GIM_Reject, |
| 21713 | // Label 49: @54644 |
| 21714 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1562*/ GIMT_Encode4(54887), |
| 21715 | /*GILLT_s32*//*Label 1557*/ GIMT_Encode4(54675), |
| 21716 | /*GILLT_s64*//*Label 1558*/ GIMT_Encode4(54698), |
| 21717 | /*GILLT_s128*//*Label 1559*/ GIMT_Encode4(54721), |
| 21718 | /*GILLT_v2s64*//*Label 1560*/ GIMT_Encode4(54808), |
| 21719 | /*GILLT_v4s32*//*Label 1561*/ GIMT_Encode4(54835), |
| 21720 | // Label 1557: @54675 |
| 21721 | GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(54697), // Rule ID 580 // |
| 21722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21723 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21725 | // (sint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$RB) => (EFSCFSI:{ *:[f32] } i32:{ *:[i32] }:$RB) |
| 21726 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCFSI), |
| 21727 | GIR_RootConstrainSelectedInstOperands, |
| 21728 | // GIR_Coverage, 580, |
| 21729 | GIR_Done, |
| 21730 | // Label 1563: @54697 |
| 21731 | GIM_Reject, |
| 21732 | // Label 1558: @54698 |
| 21733 | GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(54720), // Rule ID 559 // |
| 21734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21735 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 21737 | // (sint_to_fp:{ *:[f64] } i32:{ *:[i32] }:$RB) => (EFDCFSI:{ *:[f64] } i32:{ *:[i32] }:$RB) |
| 21738 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCFSI), |
| 21739 | GIR_RootConstrainSelectedInstOperands, |
| 21740 | // GIR_Coverage, 559, |
| 21741 | GIR_Done, |
| 21742 | // Label 1564: @54720 |
| 21743 | GIM_Reject, |
| 21744 | // Label 1559: @54721 |
| 21745 | GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(54764), // Rule ID 2121 // |
| 21746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21747 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21749 | // (sint_to_fp:{ *:[f128] } i64:{ *:[i64] }:$src) => (XSCVSDQP:{ *:[f128] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[i64] }:$src, VFRC:{ *:[i32] })) |
| 21750 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21751 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21752 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21753 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21754 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSDQP), |
| 21756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21757 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21758 | GIR_RootConstrainSelectedInstOperands, |
| 21759 | // GIR_Coverage, 2121, |
| 21760 | GIR_EraseRootFromParent_Done, |
| 21761 | // Label 1565: @54764 |
| 21762 | GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(54807), // Rule ID 2131 // |
| 21763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21764 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21766 | // (sint_to_fp:{ *:[f128] } i32:{ *:[i32] }:$src) => (XSCVSDQP:{ *:[f128] } (MTVSRWA:{ *:[f64] } ?:{ *:[i32] }:$src)) |
| 21767 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21768 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRWA), |
| 21769 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21770 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21771 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVSDQP), |
| 21773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21774 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21775 | GIR_RootConstrainSelectedInstOperands, |
| 21776 | // GIR_Coverage, 2131, |
| 21777 | GIR_EraseRootFromParent_Done, |
| 21778 | // Label 1566: @54807 |
| 21779 | GIM_Reject, |
| 21780 | // Label 1560: @54808 |
| 21781 | GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(54834), // Rule ID 881 // |
| 21782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21783 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21785 | // (sint_to_fp:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) => (XVCVSXDDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) |
| 21786 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSXDDP), |
| 21787 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21788 | GIR_RootConstrainSelectedInstOperands, |
| 21789 | // GIR_Coverage, 881, |
| 21790 | GIR_Done, |
| 21791 | // Label 1567: @54834 |
| 21792 | GIM_Reject, |
| 21793 | // Label 1561: @54835 |
| 21794 | GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(54886), |
| 21795 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21796 | GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(54866), // Rule ID 884 // |
| 21797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21799 | // (sint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) => (XVCVSXWSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) |
| 21800 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVSXWSP), |
| 21801 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21802 | GIR_RootConstrainSelectedInstOperands, |
| 21803 | // GIR_Coverage, 884, |
| 21804 | GIR_Done, |
| 21805 | // Label 1569: @54866 |
| 21806 | GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(54885), // Rule ID 1400 // |
| 21807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 21808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21809 | // (sint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA) => (VCFSX_0:{ *:[v4f32] } ?:{ *:[v4i32] }:$vA) |
| 21810 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCFSX_0), |
| 21811 | GIR_RootConstrainSelectedInstOperands, |
| 21812 | // GIR_Coverage, 1400, |
| 21813 | GIR_Done, |
| 21814 | // Label 1570: @54885 |
| 21815 | GIM_Reject, |
| 21816 | // Label 1568: @54886 |
| 21817 | GIM_Reject, |
| 21818 | // Label 1562: @54887 |
| 21819 | GIM_Reject, |
| 21820 | // Label 50: @54888 |
| 21821 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1576*/ GIMT_Encode4(55131), |
| 21822 | /*GILLT_s32*//*Label 1571*/ GIMT_Encode4(54919), |
| 21823 | /*GILLT_s64*//*Label 1572*/ GIMT_Encode4(54942), |
| 21824 | /*GILLT_s128*//*Label 1573*/ GIMT_Encode4(54965), |
| 21825 | /*GILLT_v2s64*//*Label 1574*/ GIMT_Encode4(55052), |
| 21826 | /*GILLT_v4s32*//*Label 1575*/ GIMT_Encode4(55079), |
| 21827 | // Label 1571: @54919 |
| 21828 | GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(54941), // Rule ID 582 // |
| 21829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21830 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21832 | // (uint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$RB) => (EFSCFUI:{ *:[f32] } i32:{ *:[i32] }:$RB) |
| 21833 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSCFUI), |
| 21834 | GIR_RootConstrainSelectedInstOperands, |
| 21835 | // GIR_Coverage, 582, |
| 21836 | GIR_Done, |
| 21837 | // Label 1577: @54941 |
| 21838 | GIM_Reject, |
| 21839 | // Label 1572: @54942 |
| 21840 | GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(54964), // Rule ID 561 // |
| 21841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21842 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 21844 | // (uint_to_fp:{ *:[f64] } i32:{ *:[i32] }:$RB) => (EFDCFUI:{ *:[f64] } i32:{ *:[i32] }:$RB) |
| 21845 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDCFUI), |
| 21846 | GIR_RootConstrainSelectedInstOperands, |
| 21847 | // GIR_Coverage, 561, |
| 21848 | GIR_Done, |
| 21849 | // Label 1578: @54964 |
| 21850 | GIM_Reject, |
| 21851 | // Label 1573: @54965 |
| 21852 | GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(55008), // Rule ID 2127 // |
| 21853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21854 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21856 | // (uint_to_fp:{ *:[f128] } i64:{ *:[i64] }:$src) => (XSCVUDQP:{ *:[f128] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[i64] }:$src, VFRC:{ *:[i32] })) |
| 21857 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21858 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21859 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21860 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21861 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUDQP), |
| 21863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21864 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21865 | GIR_RootConstrainSelectedInstOperands, |
| 21866 | // GIR_Coverage, 2127, |
| 21867 | GIR_EraseRootFromParent_Done, |
| 21868 | // Label 1579: @55008 |
| 21869 | GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(55051), // Rule ID 2135 // |
| 21870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 21871 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21873 | // (uint_to_fp:{ *:[f128] } i32:{ *:[i32] }:$src) => (XSCVUDQP:{ *:[f128] } (MTVSRWZ:{ *:[f64] } ?:{ *:[i32] }:$src)) |
| 21874 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21875 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::MTVSRWZ), |
| 21876 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21877 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 21878 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCVUDQP), |
| 21880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 21881 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21882 | GIR_RootConstrainSelectedInstOperands, |
| 21883 | // GIR_Coverage, 2135, |
| 21884 | GIR_EraseRootFromParent_Done, |
| 21885 | // Label 1580: @55051 |
| 21886 | GIM_Reject, |
| 21887 | // Label 1574: @55052 |
| 21888 | GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(55078), // Rule ID 886 // |
| 21889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21890 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21892 | // (uint_to_fp:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) => (XVCVUXDDP:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$XB) |
| 21893 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVUXDDP), |
| 21894 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21895 | GIR_RootConstrainSelectedInstOperands, |
| 21896 | // GIR_Coverage, 886, |
| 21897 | GIR_Done, |
| 21898 | // Label 1581: @55078 |
| 21899 | GIM_Reject, |
| 21900 | // Label 1575: @55079 |
| 21901 | GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(55130), |
| 21902 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21903 | GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(55110), // Rule ID 889 // |
| 21904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 21906 | // (uint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) => (XVCVUXWSP:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$XB) |
| 21907 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVCVUXWSP), |
| 21908 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21909 | GIR_RootConstrainSelectedInstOperands, |
| 21910 | // GIR_Coverage, 889, |
| 21911 | GIR_Done, |
| 21912 | // Label 1583: @55110 |
| 21913 | GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(55129), // Rule ID 1401 // |
| 21914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 21915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 21916 | // (uint_to_fp:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$vA) => (VCFUX_0:{ *:[v4f32] } ?:{ *:[v4i32] }:$vA) |
| 21917 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCFUX_0), |
| 21918 | GIR_RootConstrainSelectedInstOperands, |
| 21919 | // GIR_Coverage, 1401, |
| 21920 | GIR_Done, |
| 21921 | // Label 1584: @55129 |
| 21922 | GIM_Reject, |
| 21923 | // Label 1582: @55130 |
| 21924 | GIM_Reject, |
| 21925 | // Label 1576: @55131 |
| 21926 | GIM_Reject, |
| 21927 | // Label 51: @55132 |
| 21928 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1590*/ GIMT_Encode4(55420), |
| 21929 | /*GILLT_s32*//*Label 1585*/ GIMT_Encode4(55163), |
| 21930 | /*GILLT_s64*//*Label 1586*/ GIMT_Encode4(55272), |
| 21931 | /*GILLT_s128*//*Label 1587*/ GIMT_Encode4(55343), |
| 21932 | /*GILLT_v2s64*//*Label 1588*/ GIMT_Encode4(55366), |
| 21933 | /*GILLT_v4s32*//*Label 1589*/ GIMT_Encode4(55393), |
| 21934 | // Label 1585: @55163 |
| 21935 | GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(55271), |
| 21936 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 21937 | GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(55232), // Rule ID 1666 // |
| 21938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 21940 | // (fabs:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSABSDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 21941 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21942 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 21943 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21944 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21945 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 21946 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21947 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSABSDP), |
| 21948 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 21949 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 21950 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 21952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 21953 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 21954 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 21955 | // GIR_Coverage, 1666, |
| 21956 | GIR_EraseRootFromParent_Done, |
| 21957 | // Label 1592: @55232 |
| 21958 | GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(55251), // Rule ID 160 // |
| 21959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 21960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 21961 | // (fabs:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FABSS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 21962 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FABSS), |
| 21963 | GIR_RootConstrainSelectedInstOperands, |
| 21964 | // GIR_Coverage, 160, |
| 21965 | GIR_Done, |
| 21966 | // Label 1593: @55251 |
| 21967 | GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(55270), // Rule ID 574 // |
| 21968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 21969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 21970 | // (fabs:{ *:[f32] } f32:{ *:[f32] }:$RA) => (EFSABS:{ *:[f32] } f32:{ *:[f32] }:$RA) |
| 21971 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSABS), |
| 21972 | GIR_RootConstrainSelectedInstOperands, |
| 21973 | // GIR_Coverage, 574, |
| 21974 | GIR_Done, |
| 21975 | // Label 1594: @55270 |
| 21976 | GIM_Reject, |
| 21977 | // Label 1591: @55271 |
| 21978 | GIM_Reject, |
| 21979 | // Label 1586: @55272 |
| 21980 | GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(55342), |
| 21981 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 21982 | GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(55303), // Rule ID 833 // |
| 21983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 21984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 21985 | // (fabs:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSABSDP:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 21986 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSABSDP), |
| 21987 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 21988 | GIR_RootConstrainSelectedInstOperands, |
| 21989 | // GIR_Coverage, 833, |
| 21990 | GIR_Done, |
| 21991 | // Label 1596: @55303 |
| 21992 | GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(55322), // Rule ID 161 // |
| 21993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 21994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 21995 | // (fabs:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FABSD:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 21996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FABSD), |
| 21997 | GIR_RootConstrainSelectedInstOperands, |
| 21998 | // GIR_Coverage, 161, |
| 21999 | GIR_Done, |
| 22000 | // Label 1597: @55322 |
| 22001 | GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(55341), // Rule ID 553 // |
| 22002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 22003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 22004 | // (fabs:{ *:[f64] } f64:{ *:[f64] }:$RA) => (EFDABS:{ *:[f64] } f64:{ *:[f64] }:$RA) |
| 22005 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDABS), |
| 22006 | GIR_RootConstrainSelectedInstOperands, |
| 22007 | // GIR_Coverage, 553, |
| 22008 | GIR_Done, |
| 22009 | // Label 1598: @55341 |
| 22010 | GIM_Reject, |
| 22011 | // Label 1595: @55342 |
| 22012 | GIM_Reject, |
| 22013 | // Label 1587: @55343 |
| 22014 | GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(55365), // Rule ID 974 // |
| 22015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 22016 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 22017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22018 | // (fabs:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSABSQP:{ *:[f128] } f128:{ *:[f128] }:$RB) |
| 22019 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSABSQP), |
| 22020 | GIR_RootConstrainSelectedInstOperands, |
| 22021 | // GIR_Coverage, 974, |
| 22022 | GIR_Done, |
| 22023 | // Label 1599: @55365 |
| 22024 | GIM_Reject, |
| 22025 | // Label 1588: @55366 |
| 22026 | GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(55392), // Rule ID 838 // |
| 22027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22030 | // (fabs:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVABSDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 22031 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVABSDP), |
| 22032 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22033 | GIR_RootConstrainSelectedInstOperands, |
| 22034 | // GIR_Coverage, 838, |
| 22035 | GIR_Done, |
| 22036 | // Label 1600: @55392 |
| 22037 | GIM_Reject, |
| 22038 | // Label 1589: @55393 |
| 22039 | GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(55419), // Rule ID 839 // |
| 22040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22041 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22043 | // (fabs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVABSSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 22044 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVABSSP), |
| 22045 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22046 | GIR_RootConstrainSelectedInstOperands, |
| 22047 | // GIR_Coverage, 839, |
| 22048 | GIR_Done, |
| 22049 | // Label 1601: @55419 |
| 22050 | GIM_Reject, |
| 22051 | // Label 1590: @55420 |
| 22052 | GIM_Reject, |
| 22053 | // Label 52: @55421 |
| 22054 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1607*/ GIMT_Encode4(55730), |
| 22055 | /*GILLT_s32*//*Label 1602*/ GIMT_Encode4(55452), |
| 22056 | /*GILLT_s64*//*Label 1603*/ GIMT_Encode4(55533), |
| 22057 | /*GILLT_s128*//*Label 1604*/ GIMT_Encode4(55640), |
| 22058 | /*GILLT_v2s64*//*Label 1605*/ GIMT_Encode4(55670), |
| 22059 | /*GILLT_v4s32*//*Label 1606*/ GIMT_Encode4(55700), |
| 22060 | // Label 1602: @55452 |
| 22061 | GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(55532), |
| 22062 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 22063 | GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(55486), // Rule ID 166 // |
| 22064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 22065 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 22067 | // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$RB, f32:{ *:[f32] }:$RA) => (FCPSGNS:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 22068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGNS), |
| 22069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 22070 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 22071 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 22072 | GIR_RootConstrainSelectedInstOperands, |
| 22073 | // GIR_Coverage, 166, |
| 22074 | GIR_EraseRootFromParent_Done, |
| 22075 | // Label 1609: @55486 |
| 22076 | GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(55531), // Rule ID 1264 // |
| 22077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 22078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 22080 | // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$frB, f64:{ *:[f64] }:$frA) => (FCPSGNS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } ?:{ *:[f64] }:$frA, F4RC:{ *:[i32] }), ?:{ *:[f32] }:$frB) |
| 22081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22084 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // frA |
| 22085 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGNS), |
| 22087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 22088 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22089 | GIR_RootToRootCopy, /*OpIdx*/1, // frB |
| 22090 | GIR_RootConstrainSelectedInstOperands, |
| 22091 | // GIR_Coverage, 1264, |
| 22092 | GIR_EraseRootFromParent_Done, |
| 22093 | // Label 1610: @55531 |
| 22094 | GIM_Reject, |
| 22095 | // Label 1608: @55532 |
| 22096 | GIM_Reject, |
| 22097 | // Label 1603: @55533 |
| 22098 | GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(55639), |
| 22099 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 22100 | GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(55567), // Rule ID 837 // |
| 22101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22102 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 22104 | // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XA) => (XSCPSGNDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 22105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCPSGNDP), |
| 22106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 22107 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 22108 | GIR_RootToRootCopy, /*OpIdx*/1, // XB |
| 22109 | GIR_RootConstrainSelectedInstOperands, |
| 22110 | // GIR_Coverage, 837, |
| 22111 | GIR_EraseRootFromParent_Done, |
| 22112 | // Label 1612: @55567 |
| 22113 | GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(55593), // Rule ID 167 // |
| 22114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 22115 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 22117 | // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$RB, f64:{ *:[f64] }:$RA) => (FCPSGND:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 22118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGND), |
| 22119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 22120 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 22121 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 22122 | GIR_RootConstrainSelectedInstOperands, |
| 22123 | // GIR_Coverage, 167, |
| 22124 | GIR_EraseRootFromParent_Done, |
| 22125 | // Label 1613: @55593 |
| 22126 | GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(55638), // Rule ID 1263 // |
| 22127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 22128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 22130 | // (fcopysign:{ *:[f64] } f64:{ *:[f64] }:$frB, f32:{ *:[f32] }:$frA) => (FCPSGND:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$frA, F8RC:{ *:[i32] }), ?:{ *:[f64] }:$frB) |
| 22131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22134 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // frA |
| 22135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FCPSGND), |
| 22137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 22138 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22139 | GIR_RootToRootCopy, /*OpIdx*/1, // frB |
| 22140 | GIR_RootConstrainSelectedInstOperands, |
| 22141 | // GIR_Coverage, 1263, |
| 22142 | GIR_EraseRootFromParent_Done, |
| 22143 | // Label 1614: @55638 |
| 22144 | GIM_Reject, |
| 22145 | // Label 1611: @55639 |
| 22146 | GIM_Reject, |
| 22147 | // Label 1604: @55640 |
| 22148 | GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(55669), // Rule ID 973 // |
| 22149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 22150 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 22151 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 22152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22153 | // (fcopysign:{ *:[f128] } f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RA) => (XSCPSGNQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 22154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSCPSGNQP), |
| 22155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 22156 | GIR_RootToRootCopy, /*OpIdx*/2, // RA |
| 22157 | GIR_RootToRootCopy, /*OpIdx*/1, // RB |
| 22158 | GIR_RootConstrainSelectedInstOperands, |
| 22159 | // GIR_Coverage, 973, |
| 22160 | GIR_EraseRootFromParent_Done, |
| 22161 | // Label 1615: @55669 |
| 22162 | GIM_Reject, |
| 22163 | // Label 1605: @55670 |
| 22164 | GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(55699), // Rule ID 840 // |
| 22165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22166 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22167 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22169 | // (fcopysign:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XA) => (XVCPSGNDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 22170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCPSGNDP), |
| 22171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 22172 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 22173 | GIR_RootToRootCopy, /*OpIdx*/1, // XB |
| 22174 | GIR_RootConstrainSelectedInstOperands, |
| 22175 | // GIR_Coverage, 840, |
| 22176 | GIR_EraseRootFromParent_Done, |
| 22177 | // Label 1616: @55699 |
| 22178 | GIM_Reject, |
| 22179 | // Label 1606: @55700 |
| 22180 | GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(55729), // Rule ID 841 // |
| 22181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22182 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22183 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22185 | // (fcopysign:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XA) => (XVCPSGNSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 22186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVCPSGNSP), |
| 22187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 22188 | GIR_RootToRootCopy, /*OpIdx*/2, // XA |
| 22189 | GIR_RootToRootCopy, /*OpIdx*/1, // XB |
| 22190 | GIR_RootConstrainSelectedInstOperands, |
| 22191 | // GIR_Coverage, 841, |
| 22192 | GIR_EraseRootFromParent_Done, |
| 22193 | // Label 1617: @55729 |
| 22194 | GIM_Reject, |
| 22195 | // Label 1607: @55730 |
| 22196 | GIM_Reject, |
| 22197 | // Label 53: @55731 |
| 22198 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 1620*/ GIMT_Encode4(55810), |
| 22199 | /*GILLT_v2s64*//*Label 1618*/ GIMT_Encode4(55750), |
| 22200 | /*GILLT_v4s32*//*Label 1619*/ GIMT_Encode4(55780), |
| 22201 | // Label 1618: @55750 |
| 22202 | GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(55779), // Rule ID 1665 // |
| 22203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22204 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22207 | // (fminnum:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$src1, v2f64:{ *:[v2f64] }:$src2) => (XVMINDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$src1, ?:{ *:[v2f64] }:$src2) |
| 22208 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMINDP), |
| 22209 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22210 | GIR_RootConstrainSelectedInstOperands, |
| 22211 | // GIR_Coverage, 1665, |
| 22212 | GIR_Done, |
| 22213 | // Label 1621: @55779 |
| 22214 | GIM_Reject, |
| 22215 | // Label 1619: @55780 |
| 22216 | GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(55809), // Rule ID 1661 // |
| 22217 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22218 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22219 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22221 | // (fminnum:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src1, v4f32:{ *:[v4f32] }:$src2) => (XVMINSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$src1, ?:{ *:[v4f32] }:$src2) |
| 22222 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMINSP), |
| 22223 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22224 | GIR_RootConstrainSelectedInstOperands, |
| 22225 | // GIR_Coverage, 1661, |
| 22226 | GIR_Done, |
| 22227 | // Label 1622: @55809 |
| 22228 | GIM_Reject, |
| 22229 | // Label 1620: @55810 |
| 22230 | GIM_Reject, |
| 22231 | // Label 54: @55811 |
| 22232 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 1625*/ GIMT_Encode4(55890), |
| 22233 | /*GILLT_v2s64*//*Label 1623*/ GIMT_Encode4(55830), |
| 22234 | /*GILLT_v4s32*//*Label 1624*/ GIMT_Encode4(55860), |
| 22235 | // Label 1623: @55830 |
| 22236 | GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(55859), // Rule ID 1663 // |
| 22237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22238 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22239 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22241 | // (fmaxnum:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$src1, v2f64:{ *:[v2f64] }:$src2) => (XVMAXDP:{ *:[v2f64] } ?:{ *:[v2f64] }:$src1, ?:{ *:[v2f64] }:$src2) |
| 22242 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMAXDP), |
| 22243 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22244 | GIR_RootConstrainSelectedInstOperands, |
| 22245 | // GIR_Coverage, 1663, |
| 22246 | GIR_Done, |
| 22247 | // Label 1626: @55859 |
| 22248 | GIM_Reject, |
| 22249 | // Label 1624: @55860 |
| 22250 | GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(55889), // Rule ID 1659 // |
| 22251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22252 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22253 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 22255 | // (fmaxnum:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src1, v4f32:{ *:[v4f32] }:$src2) => (XVMAXSP:{ *:[v4f32] } ?:{ *:[v4f32] }:$src1, ?:{ *:[v4f32] }:$src2) |
| 22256 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMAXSP), |
| 22257 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22258 | GIR_RootConstrainSelectedInstOperands, |
| 22259 | // GIR_Coverage, 1659, |
| 22260 | GIR_Done, |
| 22261 | // Label 1627: @55889 |
| 22262 | GIM_Reject, |
| 22263 | // Label 1625: @55890 |
| 22264 | GIM_Reject, |
| 22265 | // Label 55: @55891 |
| 22266 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1630*/ GIMT_Encode4(56029), |
| 22267 | /*GILLT_s32*//*Label 1628*/ GIMT_Encode4(55910), |
| 22268 | /*GILLT_s64*//*Label 1629*/ GIMT_Encode4(55999), |
| 22269 | // Label 1628: @55910 |
| 22270 | GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(55998), // Rule ID 1668 // |
| 22271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22272 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 22273 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 22275 | // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMINDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 22276 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22277 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 22278 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 22279 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22280 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22281 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // B |
| 22282 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 22283 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22284 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22285 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 22286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22287 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMINDP), |
| 22288 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22289 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22290 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 22291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22294 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22295 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 22296 | // GIR_Coverage, 1668, |
| 22297 | GIR_EraseRootFromParent_Done, |
| 22298 | // Label 1631: @55998 |
| 22299 | GIM_Reject, |
| 22300 | // Label 1629: @55999 |
| 22301 | GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(56028), // Rule ID 1676 // |
| 22302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22303 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 22304 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 22306 | // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B) => (XSMINDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B) |
| 22307 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMINDP), |
| 22308 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22309 | GIR_RootConstrainSelectedInstOperands, |
| 22310 | // GIR_Coverage, 1676, |
| 22311 | GIR_Done, |
| 22312 | // Label 1632: @56028 |
| 22313 | GIM_Reject, |
| 22314 | // Label 1630: @56029 |
| 22315 | GIM_Reject, |
| 22316 | // Label 56: @56030 |
| 22317 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1635*/ GIMT_Encode4(56168), |
| 22318 | /*GILLT_s32*//*Label 1633*/ GIMT_Encode4(56049), |
| 22319 | /*GILLT_s64*//*Label 1634*/ GIMT_Encode4(56138), |
| 22320 | // Label 1633: @56049 |
| 22321 | GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(56137), // Rule ID 1672 // |
| 22322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22323 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 22324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 22326 | // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$A, f32:{ *:[f32] }:$B) => (COPY_TO_REGCLASS:{ *:[f32] } (XSMAXDP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$A, VSFRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$B, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 22327 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22328 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 22329 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 22330 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22331 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22332 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // B |
| 22333 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 22334 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22335 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22336 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 22337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22338 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP), |
| 22339 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22340 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22341 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 22342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 22345 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22346 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 22347 | // GIR_Coverage, 1672, |
| 22348 | GIR_EraseRootFromParent_Done, |
| 22349 | // Label 1636: @56137 |
| 22350 | GIM_Reject, |
| 22351 | // Label 1634: @56138 |
| 22352 | GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(56167), // Rule ID 1680 // |
| 22353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 22354 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 22355 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 22357 | // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$A, f64:{ *:[f64] }:$B) => (XSMAXDP:{ *:[f64] } ?:{ *:[f64] }:$A, ?:{ *:[f64] }:$B) |
| 22358 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMAXDP), |
| 22359 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 22360 | GIR_RootConstrainSelectedInstOperands, |
| 22361 | // GIR_Coverage, 1680, |
| 22362 | GIR_Done, |
| 22363 | // Label 1637: @56167 |
| 22364 | GIM_Reject, |
| 22365 | // Label 1635: @56168 |
| 22366 | GIM_Reject, |
| 22367 | // Label 57: @56169 |
| 22368 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 1642*/ GIMT_Encode4(56342), |
| 22369 | /*GILLT_v2s64*//*Label 1638*/ GIMT_Encode4(56196), |
| 22370 | /*GILLT_v4s32*//*Label 1639*/ GIMT_Encode4(56264), |
| 22371 | /*GILLT_v8s16*//*Label 1640*/ GIMT_Encode4(56290), |
| 22372 | /*GILLT_v16s8*//*Label 1641*/ GIMT_Encode4(56316), |
| 22373 | // Label 1638: @56196 |
| 22374 | GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(56263), // Rule ID 1915 // |
| 22375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 22376 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22377 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22379 | // (smin:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMINSD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] })) |
| 22380 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22381 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22382 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22383 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22384 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 22385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22386 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22388 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1 |
| 22389 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINSD), |
| 22391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 22392 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 22394 | GIR_RootConstrainSelectedInstOperands, |
| 22395 | // GIR_Coverage, 1915, |
| 22396 | GIR_EraseRootFromParent_Done, |
| 22397 | // Label 1643: @56263 |
| 22398 | GIM_Reject, |
| 22399 | // Label 1639: @56264 |
| 22400 | GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(56289), // Rule ID 1345 // |
| 22401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22402 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22403 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22405 | // (smin:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMINSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 22406 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINSW), |
| 22407 | GIR_RootConstrainSelectedInstOperands, |
| 22408 | // GIR_Coverage, 1345, |
| 22409 | GIR_Done, |
| 22410 | // Label 1644: @56289 |
| 22411 | GIM_Reject, |
| 22412 | // Label 1640: @56290 |
| 22413 | GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(56315), // Rule ID 1343 // |
| 22414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22415 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22416 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22418 | // (smin:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMINSH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 22419 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINSH), |
| 22420 | GIR_RootConstrainSelectedInstOperands, |
| 22421 | // GIR_Coverage, 1343, |
| 22422 | GIR_Done, |
| 22423 | // Label 1645: @56315 |
| 22424 | GIM_Reject, |
| 22425 | // Label 1641: @56316 |
| 22426 | GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(56341), // Rule ID 1341 // |
| 22427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22428 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22429 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22431 | // (smin:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMINSB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 22432 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINSB), |
| 22433 | GIR_RootConstrainSelectedInstOperands, |
| 22434 | // GIR_Coverage, 1341, |
| 22435 | GIR_Done, |
| 22436 | // Label 1646: @56341 |
| 22437 | GIM_Reject, |
| 22438 | // Label 1642: @56342 |
| 22439 | GIM_Reject, |
| 22440 | // Label 58: @56343 |
| 22441 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 1651*/ GIMT_Encode4(56516), |
| 22442 | /*GILLT_v2s64*//*Label 1647*/ GIMT_Encode4(56370), |
| 22443 | /*GILLT_v4s32*//*Label 1648*/ GIMT_Encode4(56438), |
| 22444 | /*GILLT_v8s16*//*Label 1649*/ GIMT_Encode4(56464), |
| 22445 | /*GILLT_v16s8*//*Label 1650*/ GIMT_Encode4(56490), |
| 22446 | // Label 1647: @56370 |
| 22447 | GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(56437), // Rule ID 1913 // |
| 22448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 22449 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22452 | // (smax:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMAXSD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] })) |
| 22453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22454 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22455 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22456 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22457 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 22458 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22459 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22460 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22461 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1 |
| 22462 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXSD), |
| 22464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 22465 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22466 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 22467 | GIR_RootConstrainSelectedInstOperands, |
| 22468 | // GIR_Coverage, 1913, |
| 22469 | GIR_EraseRootFromParent_Done, |
| 22470 | // Label 1652: @56437 |
| 22471 | GIM_Reject, |
| 22472 | // Label 1648: @56438 |
| 22473 | GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(56463), // Rule ID 1339 // |
| 22474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22475 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22476 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22478 | // (smax:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMAXSW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 22479 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXSW), |
| 22480 | GIR_RootConstrainSelectedInstOperands, |
| 22481 | // GIR_Coverage, 1339, |
| 22482 | GIR_Done, |
| 22483 | // Label 1653: @56463 |
| 22484 | GIM_Reject, |
| 22485 | // Label 1649: @56464 |
| 22486 | GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(56489), // Rule ID 1337 // |
| 22487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22488 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22489 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22491 | // (smax:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMAXSH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 22492 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXSH), |
| 22493 | GIR_RootConstrainSelectedInstOperands, |
| 22494 | // GIR_Coverage, 1337, |
| 22495 | GIR_Done, |
| 22496 | // Label 1654: @56489 |
| 22497 | GIM_Reject, |
| 22498 | // Label 1650: @56490 |
| 22499 | GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(56515), // Rule ID 1335 // |
| 22500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22501 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22502 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22504 | // (smax:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMAXSB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 22505 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXSB), |
| 22506 | GIR_RootConstrainSelectedInstOperands, |
| 22507 | // GIR_Coverage, 1335, |
| 22508 | GIR_Done, |
| 22509 | // Label 1655: @56515 |
| 22510 | GIM_Reject, |
| 22511 | // Label 1651: @56516 |
| 22512 | GIM_Reject, |
| 22513 | // Label 59: @56517 |
| 22514 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 1660*/ GIMT_Encode4(56690), |
| 22515 | /*GILLT_v2s64*//*Label 1656*/ GIMT_Encode4(56544), |
| 22516 | /*GILLT_v4s32*//*Label 1657*/ GIMT_Encode4(56612), |
| 22517 | /*GILLT_v8s16*//*Label 1658*/ GIMT_Encode4(56638), |
| 22518 | /*GILLT_v16s8*//*Label 1659*/ GIMT_Encode4(56664), |
| 22519 | // Label 1656: @56544 |
| 22520 | GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(56611), // Rule ID 1916 // |
| 22521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 22522 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22525 | // (umin:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMINUD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] })) |
| 22526 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22527 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22528 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22529 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22530 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 22531 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22532 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22533 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22534 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1 |
| 22535 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMINUD), |
| 22537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 22538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22539 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 22540 | GIR_RootConstrainSelectedInstOperands, |
| 22541 | // GIR_Coverage, 1916, |
| 22542 | GIR_EraseRootFromParent_Done, |
| 22543 | // Label 1661: @56611 |
| 22544 | GIM_Reject, |
| 22545 | // Label 1657: @56612 |
| 22546 | GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(56637), // Rule ID 1344 // |
| 22547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22548 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22549 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22551 | // (umin:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMINUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 22552 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINUW), |
| 22553 | GIR_RootConstrainSelectedInstOperands, |
| 22554 | // GIR_Coverage, 1344, |
| 22555 | GIR_Done, |
| 22556 | // Label 1662: @56637 |
| 22557 | GIM_Reject, |
| 22558 | // Label 1658: @56638 |
| 22559 | GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(56663), // Rule ID 1342 // |
| 22560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22561 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22562 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22564 | // (umin:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMINUH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 22565 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINUH), |
| 22566 | GIR_RootConstrainSelectedInstOperands, |
| 22567 | // GIR_Coverage, 1342, |
| 22568 | GIR_Done, |
| 22569 | // Label 1663: @56663 |
| 22570 | GIM_Reject, |
| 22571 | // Label 1659: @56664 |
| 22572 | GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(56689), // Rule ID 1340 // |
| 22573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22574 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22577 | // (umin:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMINUB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 22578 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMINUB), |
| 22579 | GIR_RootConstrainSelectedInstOperands, |
| 22580 | // GIR_Coverage, 1340, |
| 22581 | GIR_Done, |
| 22582 | // Label 1664: @56689 |
| 22583 | GIM_Reject, |
| 22584 | // Label 1660: @56690 |
| 22585 | GIM_Reject, |
| 22586 | // Label 60: @56691 |
| 22587 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(8), /*)*//*default:*//*Label 1669*/ GIMT_Encode4(56864), |
| 22588 | /*GILLT_v2s64*//*Label 1665*/ GIMT_Encode4(56718), |
| 22589 | /*GILLT_v4s32*//*Label 1666*/ GIMT_Encode4(56786), |
| 22590 | /*GILLT_v8s16*//*Label 1667*/ GIMT_Encode4(56812), |
| 22591 | /*GILLT_v16s8*//*Label 1668*/ GIMT_Encode4(56838), |
| 22592 | // Label 1665: @56718 |
| 22593 | GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(56785), // Rule ID 1914 // |
| 22594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 22595 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22596 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22597 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22598 | // (umax:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src1, v2i64:{ *:[v2i64] }:$src2) => (VMAXUD:{ *:[v2i64] } (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src1, VRRC:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[f128] } ?:{ *:[v2i64] }:$src2, VRRC:{ *:[i32] })) |
| 22599 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128, |
| 22600 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128, |
| 22601 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22602 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22603 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 22604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22605 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22606 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22607 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src1 |
| 22608 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VMAXUD), |
| 22610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 22611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 22613 | GIR_RootConstrainSelectedInstOperands, |
| 22614 | // GIR_Coverage, 1914, |
| 22615 | GIR_EraseRootFromParent_Done, |
| 22616 | // Label 1670: @56785 |
| 22617 | GIM_Reject, |
| 22618 | // Label 1666: @56786 |
| 22619 | GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(56811), // Rule ID 1338 // |
| 22620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22621 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22622 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22623 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22624 | // (umax:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (VMAXUW:{ *:[v4i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 22625 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXUW), |
| 22626 | GIR_RootConstrainSelectedInstOperands, |
| 22627 | // GIR_Coverage, 1338, |
| 22628 | GIR_Done, |
| 22629 | // Label 1671: @56811 |
| 22630 | GIM_Reject, |
| 22631 | // Label 1667: @56812 |
| 22632 | GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(56837), // Rule ID 1336 // |
| 22633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22634 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22635 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22637 | // (umax:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2) => (VMAXUH:{ *:[v8i16] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 22638 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXUH), |
| 22639 | GIR_RootConstrainSelectedInstOperands, |
| 22640 | // GIR_Coverage, 1336, |
| 22641 | GIR_Done, |
| 22642 | // Label 1672: @56837 |
| 22643 | GIM_Reject, |
| 22644 | // Label 1668: @56838 |
| 22645 | GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(56863), // Rule ID 1334 // |
| 22646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 22647 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22648 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22650 | // (umax:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src1, v16i8:{ *:[v16i8] }:$src2) => (VMAXUB:{ *:[v16i8] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 22651 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VMAXUB), |
| 22652 | GIR_RootConstrainSelectedInstOperands, |
| 22653 | // GIR_Coverage, 1334, |
| 22654 | GIR_Done, |
| 22655 | // Label 1673: @56863 |
| 22656 | GIM_Reject, |
| 22657 | // Label 1669: @56864 |
| 22658 | GIM_Reject, |
| 22659 | // Label 61: @56865 |
| 22660 | GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(57026), |
| 22661 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22662 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1677*/ GIMT_Encode4(57025), |
| 22663 | /*GILLT_s32*//*Label 1675*/ GIMT_Encode4(56892), |
| 22664 | /*GILLT_s64*//*Label 1676*/ GIMT_Encode4(56967), |
| 22665 | // Label 1675: @56892 |
| 22666 | GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(56966), // Rule ID 2020 // |
| 22667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 22668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 22669 | // (lround:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })))) |
| 22670 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22671 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 22672 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 22673 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22674 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22675 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 22676 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 22677 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), |
| 22678 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22679 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 22680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22681 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 22682 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22683 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22684 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 22686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 22687 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22688 | GIR_RootConstrainSelectedInstOperands, |
| 22689 | // GIR_Coverage, 2020, |
| 22690 | GIR_EraseRootFromParent_Done, |
| 22691 | // Label 1678: @56966 |
| 22692 | GIM_Reject, |
| 22693 | // Label 1676: @56967 |
| 22694 | GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(57024), // Rule ID 2019 // |
| 22695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 22696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 22697 | // (lround:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } ?:{ *:[f64] }:$S))) |
| 22698 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22699 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 22700 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), |
| 22701 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22702 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 22703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22704 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 22705 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22706 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 22709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 22710 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22711 | GIR_RootConstrainSelectedInstOperands, |
| 22712 | // GIR_Coverage, 2019, |
| 22713 | GIR_EraseRootFromParent_Done, |
| 22714 | // Label 1679: @57024 |
| 22715 | GIM_Reject, |
| 22716 | // Label 1677: @57025 |
| 22717 | GIM_Reject, |
| 22718 | // Label 1674: @57026 |
| 22719 | GIM_Reject, |
| 22720 | // Label 62: @57027 |
| 22721 | GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(57188), |
| 22722 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 22723 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1683*/ GIMT_Encode4(57187), |
| 22724 | /*GILLT_s32*//*Label 1681*/ GIMT_Encode4(57054), |
| 22725 | /*GILLT_s64*//*Label 1682*/ GIMT_Encode4(57129), |
| 22726 | // Label 1681: @57054 |
| 22727 | GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(57128), // Rule ID 2022 // |
| 22728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 22729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 22730 | // (llround:{ *:[i64] } f32:{ *:[f32] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })))) |
| 22731 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22732 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 22733 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 22734 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 22735 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22736 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 22737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 22738 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), |
| 22739 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22740 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 22741 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22742 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 22743 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22744 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22745 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 22747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 22748 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22749 | GIR_RootConstrainSelectedInstOperands, |
| 22750 | // GIR_Coverage, 2022, |
| 22751 | GIR_EraseRootFromParent_Done, |
| 22752 | // Label 1684: @57128 |
| 22753 | GIM_Reject, |
| 22754 | // Label 1682: @57129 |
| 22755 | GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(57186), // Rule ID 2021 // |
| 22756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDirectMove_HasVSX), |
| 22757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 22758 | // (llround:{ *:[i64] } f64:{ *:[f64] }:$S) => (MFVSRD:{ *:[i64] } (FCTID:{ *:[f64] } (XSRDPI:{ *:[f64] } ?:{ *:[f64] }:$S))) |
| 22759 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 22760 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 22761 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::XSRDPI), |
| 22762 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22763 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 22764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 22765 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::FCTID), |
| 22766 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22767 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 22768 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::MFVSRD), |
| 22770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 22771 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22772 | GIR_RootConstrainSelectedInstOperands, |
| 22773 | // GIR_Coverage, 2021, |
| 22774 | GIR_EraseRootFromParent_Done, |
| 22775 | // Label 1685: @57186 |
| 22776 | GIM_Reject, |
| 22777 | // Label 1683: @57187 |
| 22778 | GIM_Reject, |
| 22779 | // Label 1680: @57188 |
| 22780 | GIM_Reject, |
| 22781 | // Label 63: @57189 |
| 22782 | GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(57204), // Rule ID 15 // |
| 22783 | // MIs[0] LI |
| 22784 | GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 22785 | // (br (bb:{ *:[Other] }):$LI) => (B (bb:{ *:[Other] }):$LI) |
| 22786 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::B), |
| 22787 | GIR_RootConstrainSelectedInstOperands, |
| 22788 | // GIR_Coverage, 15, |
| 22789 | GIR_Done, |
| 22790 | // Label 1686: @57204 |
| 22791 | GIM_Reject, |
| 22792 | // Label 64: @57205 |
| 22793 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(8), /*)*//*default:*//*Label 1689*/ GIMT_Encode4(57322), |
| 22794 | /*GILLT_v8s16*//*Label 1687*/ GIMT_Encode4(57224), |
| 22795 | /*GILLT_v16s8*//*Label 1688*/ GIMT_Encode4(57287), |
| 22796 | // Label 1687: @57224 |
| 22797 | GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(57286), // Rule ID 3468 // |
| 22798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32), |
| 22799 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22803 | // (vector_insert:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSHLX:{ *:[v8i16] } ?:{ *:[v8i16] }:$vDi, (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$rB, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), ?:{ *:[i32] }:$rA) |
| 22804 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 22805 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 22806 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 22807 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rB |
| 22808 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 22809 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 22810 | GIR_AddImm8, /*InsnID*/1, /*Imm*/30, |
| 22811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 22812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSHLX), |
| 22813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 22814 | GIR_RootToRootCopy, /*OpIdx*/1, // vDi |
| 22815 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 22816 | GIR_RootToRootCopy, /*OpIdx*/2, // rA |
| 22817 | GIR_RootConstrainSelectedInstOperands, |
| 22818 | // GIR_Coverage, 3468, |
| 22819 | GIR_EraseRootFromParent_Done, |
| 22820 | // Label 1690: @57286 |
| 22821 | GIM_Reject, |
| 22822 | // Label 1688: @57287 |
| 22823 | GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(57321), // Rule ID 3467 // |
| 22824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX_IsBigEndian_IsISA3_1_IsPPC32), |
| 22825 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22827 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22829 | // (vector_insert:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$vDi, i32:{ *:[i32] }:$rA, i32:{ *:[i32] }:$rB) => (VINSBLX:{ *:[v16i8] } ?:{ *:[v16i8] }:$vDi, ?:{ *:[i32] }:$rB, ?:{ *:[i32] }:$rA) |
| 22830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::VINSBLX), |
| 22831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VD] |
| 22832 | GIR_RootToRootCopy, /*OpIdx*/1, // vDi |
| 22833 | GIR_RootToRootCopy, /*OpIdx*/3, // rB |
| 22834 | GIR_RootToRootCopy, /*OpIdx*/2, // rA |
| 22835 | GIR_RootConstrainSelectedInstOperands, |
| 22836 | // GIR_Coverage, 3467, |
| 22837 | GIR_EraseRootFromParent_Done, |
| 22838 | // Label 1691: @57321 |
| 22839 | GIM_Reject, |
| 22840 | // Label 1689: @57322 |
| 22841 | GIM_Reject, |
| 22842 | // Label 65: @57323 |
| 22843 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1698*/ GIMT_Encode4(57500), |
| 22844 | /*GILLT_s32*//*Label 1692*/ GIMT_Encode4(57362), |
| 22845 | /*GILLT_s64*//*Label 1693*/ GIMT_Encode4(57385), GIMT_Encode4(0), |
| 22846 | /*GILLT_v2s64*//*Label 1694*/ GIMT_Encode4(57408), |
| 22847 | /*GILLT_v4s32*//*Label 1695*/ GIMT_Encode4(57431), |
| 22848 | /*GILLT_v8s16*//*Label 1696*/ GIMT_Encode4(57454), |
| 22849 | /*GILLT_v16s8*//*Label 1697*/ GIMT_Encode4(57477), |
| 22850 | // Label 1692: @57362 |
| 22851 | GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(57384), // Rule ID 131 // |
| 22852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 22853 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 22854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 22855 | // (cttz:{ *:[i32] } i32:{ *:[i32] }:$RST) => (CNTTZW:{ *:[i32] } i32:{ *:[i32] }:$RST) |
| 22856 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTTZW), |
| 22857 | GIR_RootConstrainSelectedInstOperands, |
| 22858 | // GIR_Coverage, 131, |
| 22859 | GIR_Done, |
| 22860 | // Label 1699: @57384 |
| 22861 | GIM_Reject, |
| 22862 | // Label 1693: @57385 |
| 22863 | GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(57407), // Rule ID 681 // |
| 22864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_0), |
| 22865 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 22866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 22867 | // (cttz:{ *:[i64] } i64:{ *:[i64] }:$RST) => (CNTTZD:{ *:[i64] } i64:{ *:[i64] }:$RST) |
| 22868 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTTZD), |
| 22869 | GIR_RootConstrainSelectedInstOperands, |
| 22870 | // GIR_Coverage, 681, |
| 22871 | GIR_Done, |
| 22872 | // Label 1700: @57407 |
| 22873 | GIM_Reject, |
| 22874 | // Label 1694: @57408 |
| 22875 | GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(57430), // Rule ID 532 // |
| 22876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 22877 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22879 | // (cttz:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) => (VCTZD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) |
| 22880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZD), |
| 22881 | GIR_RootConstrainSelectedInstOperands, |
| 22882 | // GIR_Coverage, 532, |
| 22883 | GIR_Done, |
| 22884 | // Label 1701: @57430 |
| 22885 | GIM_Reject, |
| 22886 | // Label 1695: @57431 |
| 22887 | GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(57453), // Rule ID 531 // |
| 22888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 22889 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22891 | // (cttz:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) => (VCTZW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) |
| 22892 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZW), |
| 22893 | GIR_RootConstrainSelectedInstOperands, |
| 22894 | // GIR_Coverage, 531, |
| 22895 | GIR_Done, |
| 22896 | // Label 1702: @57453 |
| 22897 | GIM_Reject, |
| 22898 | // Label 1696: @57454 |
| 22899 | GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(57476), // Rule ID 530 // |
| 22900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 22901 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22903 | // (cttz:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) => (VCTZH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) |
| 22904 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZH), |
| 22905 | GIR_RootConstrainSelectedInstOperands, |
| 22906 | // GIR_Coverage, 530, |
| 22907 | GIR_Done, |
| 22908 | // Label 1703: @57476 |
| 22909 | GIM_Reject, |
| 22910 | // Label 1697: @57477 |
| 22911 | GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(57499), // Rule ID 529 // |
| 22912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Altivec), |
| 22913 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22915 | // (cttz:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) => (VCTZB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 22916 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCTZB), |
| 22917 | GIR_RootConstrainSelectedInstOperands, |
| 22918 | // GIR_Coverage, 529, |
| 22919 | GIR_Done, |
| 22920 | // Label 1704: @57499 |
| 22921 | GIM_Reject, |
| 22922 | // Label 1698: @57500 |
| 22923 | GIM_Reject, |
| 22924 | // Label 66: @57501 |
| 22925 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1711*/ GIMT_Encode4(57672), |
| 22926 | /*GILLT_s32*//*Label 1705*/ GIMT_Encode4(57540), |
| 22927 | /*GILLT_s64*//*Label 1706*/ GIMT_Encode4(57560), GIMT_Encode4(0), |
| 22928 | /*GILLT_v2s64*//*Label 1707*/ GIMT_Encode4(57580), |
| 22929 | /*GILLT_v4s32*//*Label 1708*/ GIMT_Encode4(57603), |
| 22930 | /*GILLT_v8s16*//*Label 1709*/ GIMT_Encode4(57626), |
| 22931 | /*GILLT_v16s8*//*Label 1710*/ GIMT_Encode4(57649), |
| 22932 | // Label 1705: @57540 |
| 22933 | GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(57559), // Rule ID 130 // |
| 22934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 22935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 22936 | // (ctlz:{ *:[i32] } i32:{ *:[i32] }:$RST) => (CNTLZW:{ *:[i32] } i32:{ *:[i32] }:$RST) |
| 22937 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTLZW), |
| 22938 | GIR_RootConstrainSelectedInstOperands, |
| 22939 | // GIR_Coverage, 130, |
| 22940 | GIR_Done, |
| 22941 | // Label 1712: @57559 |
| 22942 | GIM_Reject, |
| 22943 | // Label 1706: @57560 |
| 22944 | GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(57579), // Rule ID 680 // |
| 22945 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 22946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 22947 | // (ctlz:{ *:[i64] } i64:{ *:[i64] }:$RST) => (CNTLZD:{ *:[i64] } i64:{ *:[i64] }:$RST) |
| 22948 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::CNTLZD), |
| 22949 | GIR_RootConstrainSelectedInstOperands, |
| 22950 | // GIR_Coverage, 680, |
| 22951 | GIR_Done, |
| 22952 | // Label 1713: @57579 |
| 22953 | GIM_Reject, |
| 22954 | // Label 1707: @57580 |
| 22955 | GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(57602), // Rule ID 479 // |
| 22956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 22957 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22959 | // (ctlz:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) => (VCLZD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) |
| 22960 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZD), |
| 22961 | GIR_RootConstrainSelectedInstOperands, |
| 22962 | // GIR_Coverage, 479, |
| 22963 | GIR_Done, |
| 22964 | // Label 1714: @57602 |
| 22965 | GIM_Reject, |
| 22966 | // Label 1708: @57603 |
| 22967 | GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(57625), // Rule ID 478 // |
| 22968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 22969 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22971 | // (ctlz:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) => (VCLZW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) |
| 22972 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZW), |
| 22973 | GIR_RootConstrainSelectedInstOperands, |
| 22974 | // GIR_Coverage, 478, |
| 22975 | GIR_Done, |
| 22976 | // Label 1715: @57625 |
| 22977 | GIM_Reject, |
| 22978 | // Label 1709: @57626 |
| 22979 | GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(57648), // Rule ID 477 // |
| 22980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 22981 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 22982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22983 | // (ctlz:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) => (VCLZH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) |
| 22984 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZH), |
| 22985 | GIR_RootConstrainSelectedInstOperands, |
| 22986 | // GIR_Coverage, 477, |
| 22987 | GIR_Done, |
| 22988 | // Label 1716: @57648 |
| 22989 | GIM_Reject, |
| 22990 | // Label 1710: @57649 |
| 22991 | GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(57671), // Rule ID 476 // |
| 22992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 22993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 22994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 22995 | // (ctlz:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) => (VCLZB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 22996 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VCLZB), |
| 22997 | GIR_RootConstrainSelectedInstOperands, |
| 22998 | // GIR_Coverage, 476, |
| 22999 | GIR_Done, |
| 23000 | // Label 1717: @57671 |
| 23001 | GIM_Reject, |
| 23002 | // Label 1711: @57672 |
| 23003 | GIM_Reject, |
| 23004 | // Label 67: @57673 |
| 23005 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 1724*/ GIMT_Encode4(57844), |
| 23006 | /*GILLT_s32*//*Label 1718*/ GIMT_Encode4(57712), |
| 23007 | /*GILLT_s64*//*Label 1719*/ GIMT_Encode4(57732), GIMT_Encode4(0), |
| 23008 | /*GILLT_v2s64*//*Label 1720*/ GIMT_Encode4(57752), |
| 23009 | /*GILLT_v4s32*//*Label 1721*/ GIMT_Encode4(57775), |
| 23010 | /*GILLT_v8s16*//*Label 1722*/ GIMT_Encode4(57798), |
| 23011 | /*GILLT_v16s8*//*Label 1723*/ GIMT_Encode4(57821), |
| 23012 | // Label 1718: @57712 |
| 23013 | GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(57731), // Rule ID 685 // |
| 23014 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 23015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 23016 | // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$RST) => (POPCNTW:{ *:[i32] } i32:{ *:[i32] }:$RST) |
| 23017 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::POPCNTW), |
| 23018 | GIR_RootConstrainSelectedInstOperands, |
| 23019 | // GIR_Coverage, 685, |
| 23020 | GIR_Done, |
| 23021 | // Label 1725: @57731 |
| 23022 | GIM_Reject, |
| 23023 | // Label 1719: @57732 |
| 23024 | GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(57751), // Rule ID 682 // |
| 23025 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 23026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 23027 | // (ctpop:{ *:[i64] } i64:{ *:[i64] }:$RST) => (POPCNTD:{ *:[i64] } i64:{ *:[i64] }:$RST) |
| 23028 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::POPCNTD), |
| 23029 | GIR_RootConstrainSelectedInstOperands, |
| 23030 | // GIR_Coverage, 682, |
| 23031 | GIR_Done, |
| 23032 | // Label 1726: @57751 |
| 23033 | GIM_Reject, |
| 23034 | // Label 1720: @57752 |
| 23035 | GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(57774), // Rule ID 483 // |
| 23036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 23037 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 23039 | // (ctpop:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) => (VPOPCNTD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$VB) |
| 23040 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTD), |
| 23041 | GIR_RootConstrainSelectedInstOperands, |
| 23042 | // GIR_Coverage, 483, |
| 23043 | GIR_Done, |
| 23044 | // Label 1727: @57774 |
| 23045 | GIM_Reject, |
| 23046 | // Label 1721: @57775 |
| 23047 | GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(57797), // Rule ID 482 // |
| 23048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 23049 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 23051 | // (ctpop:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) => (VPOPCNTW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$VB) |
| 23052 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTW), |
| 23053 | GIR_RootConstrainSelectedInstOperands, |
| 23054 | // GIR_Coverage, 482, |
| 23055 | GIR_Done, |
| 23056 | // Label 1728: @57797 |
| 23057 | GIM_Reject, |
| 23058 | // Label 1722: @57798 |
| 23059 | GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(57820), // Rule ID 481 // |
| 23060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 23061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 23062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 23063 | // (ctpop:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) => (VPOPCNTH:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$VB) |
| 23064 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTH), |
| 23065 | GIR_RootConstrainSelectedInstOperands, |
| 23066 | // GIR_Coverage, 481, |
| 23067 | GIR_Done, |
| 23068 | // Label 1729: @57820 |
| 23069 | GIM_Reject, |
| 23070 | // Label 1723: @57821 |
| 23071 | GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(57843), // Rule ID 480 // |
| 23072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Altivec), |
| 23073 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 23074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 23075 | // (ctpop:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) => (VPOPCNTB:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$VB) |
| 23076 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VPOPCNTB), |
| 23077 | GIR_RootConstrainSelectedInstOperands, |
| 23078 | // GIR_Coverage, 480, |
| 23079 | GIR_Done, |
| 23080 | // Label 1730: @57843 |
| 23081 | GIM_Reject, |
| 23082 | // Label 1724: @57844 |
| 23083 | GIM_Reject, |
| 23084 | // Label 68: @57845 |
| 23085 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1737*/ GIMT_Encode4(58102), |
| 23086 | /*GILLT_s32*//*Label 1731*/ GIMT_Encode4(57880), |
| 23087 | /*GILLT_s64*//*Label 1732*/ GIMT_Encode4(57903), |
| 23088 | /*GILLT_s128*//*Label 1733*/ GIMT_Encode4(57926), |
| 23089 | /*GILLT_v2s64*//*Label 1734*/ GIMT_Encode4(57991), |
| 23090 | /*GILLT_v4s32*//*Label 1735*/ GIMT_Encode4(58014), |
| 23091 | /*GILLT_v8s16*//*Label 1736*/ GIMT_Encode4(58037), |
| 23092 | // Label 1731: @57880 |
| 23093 | GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(57902), // Rule ID 1129 // |
| 23094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 23095 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 23096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 23097 | // (bswap:{ *:[i32] } i32:{ *:[i32] }:$RST) => (BRW:{ *:[i32] } i32:{ *:[i32] }:$RST) |
| 23098 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BRW), |
| 23099 | GIR_RootConstrainSelectedInstOperands, |
| 23100 | // GIR_Coverage, 1129, |
| 23101 | GIR_Done, |
| 23102 | // Label 1738: @57902 |
| 23103 | GIM_Reject, |
| 23104 | // Label 1732: @57903 |
| 23105 | GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(57925), // Rule ID 1130 // |
| 23106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsISA3_1), |
| 23107 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 23108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 23109 | // (bswap:{ *:[i64] } i64:{ *:[i64] }:$RST) => (BRD:{ *:[i64] } i64:{ *:[i64] }:$RST) |
| 23110 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::BRD), |
| 23111 | GIR_RootConstrainSelectedInstOperands, |
| 23112 | // GIR_Coverage, 1130, |
| 23113 | GIR_Done, |
| 23114 | // Label 1739: @57925 |
| 23115 | GIM_Reject, |
| 23116 | // Label 1733: @57926 |
| 23117 | GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(57990), // Rule ID 2156 // |
| 23118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 23119 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 23120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 23121 | // (bswap:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$A) => (COPY_TO_REGCLASS:{ *:[v1i128] } (XXBRQ:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v1i128] }:$A, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 23122 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23123 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 23124 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23125 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23126 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 23128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBRQ), |
| 23129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23130 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23134 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23135 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 23136 | // GIR_Coverage, 2156, |
| 23137 | GIR_EraseRootFromParent_Done, |
| 23138 | // Label 1740: @57990 |
| 23139 | GIM_Reject, |
| 23140 | // Label 1734: @57991 |
| 23141 | GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(58013), // Rule ID 1028 // |
| 23142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 23143 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 23145 | // (bswap:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XB) => (XXBRD:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$XB) |
| 23146 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXBRD), |
| 23147 | GIR_RootConstrainSelectedInstOperands, |
| 23148 | // GIR_Coverage, 1028, |
| 23149 | GIR_Done, |
| 23150 | // Label 1741: @58013 |
| 23151 | GIM_Reject, |
| 23152 | // Label 1735: @58014 |
| 23153 | GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(58036), // Rule ID 1027 // |
| 23154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 23155 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 23157 | // (bswap:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB) => (XXBRW:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$XB) |
| 23158 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XXBRW), |
| 23159 | GIR_RootConstrainSelectedInstOperands, |
| 23160 | // GIR_Coverage, 1027, |
| 23161 | GIR_Done, |
| 23162 | // Label 1742: @58036 |
| 23163 | GIM_Reject, |
| 23164 | // Label 1736: @58037 |
| 23165 | GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(58101), // Rule ID 2155 // |
| 23166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 23167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 23168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 23169 | // (bswap:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$A) => (COPY_TO_REGCLASS:{ *:[v8i16] } (XXBRH:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$A, VSRC:{ *:[i32] })), VRRC:{ *:[i32] }) |
| 23170 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23171 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 23172 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23173 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23174 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23175 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 23176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XXBRH), |
| 23177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23178 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23179 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23182 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23183 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VRRCRegClassID), |
| 23184 | // GIR_Coverage, 2155, |
| 23185 | GIR_EraseRootFromParent_Done, |
| 23186 | // Label 1743: @58101 |
| 23187 | GIM_Reject, |
| 23188 | // Label 1737: @58102 |
| 23189 | GIM_Reject, |
| 23190 | // Label 69: @58103 |
| 23191 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1746*/ GIMT_Encode4(94108), |
| 23192 | /*GILLT_s32*//*Label 1744*/ GIMT_Encode4(58122), |
| 23193 | /*GILLT_s64*//*Label 1745*/ GIMT_Encode4(68417), |
| 23194 | // Label 1744: @58122 |
| 23195 | GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(68416), |
| 23196 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 23197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 23198 | GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(63290), // Rule ID 4832 // |
| 23199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In64BitMode), |
| 23200 | // (bitreverse:{ *:[i32] } i32:{ *:[i32] }:$A) => (RLDICL_32:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 24:{ *:[i32] }, 0:{ *:[i32] }, 31:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 8:{ *:[i32] }, 15:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 24:{ *:[i32] }, 31:{ *:[i32] }), 0:{ *:[i32] }, 32:{ *:[i32] }) |
| 23201 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23202 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23203 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 23204 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 23205 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 23206 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 23207 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 23208 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 23209 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 23210 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 23211 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 23212 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 23213 | GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s32, |
| 23214 | GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s32, |
| 23215 | GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s32, |
| 23216 | GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s32, |
| 23217 | GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s32, |
| 23218 | GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s32, |
| 23219 | GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_s32, |
| 23220 | GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s32, |
| 23221 | GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s32, |
| 23222 | GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s32, |
| 23223 | GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s32, |
| 23224 | GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s32, |
| 23225 | GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_s32, |
| 23226 | GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_s32, |
| 23227 | GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_s32, |
| 23228 | GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s32, |
| 23229 | GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s32, |
| 23230 | GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s32, |
| 23231 | GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s32, |
| 23232 | GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s32, |
| 23233 | GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s32, |
| 23234 | GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s32, |
| 23235 | GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s32, |
| 23236 | GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s32, |
| 23237 | GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_s32, |
| 23238 | GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s32, |
| 23239 | GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s32, |
| 23240 | GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_s32, |
| 23241 | GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_s32, |
| 23242 | GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_s32, |
| 23243 | GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s32, |
| 23244 | GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s32, |
| 23245 | GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s32, |
| 23246 | GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s32, |
| 23247 | GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s32, |
| 23248 | GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_s32, |
| 23249 | GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_s32, |
| 23250 | GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_s32, |
| 23251 | GIR_MakeTempReg, /*TempRegID*/50, /*TypeID*/GILLT_s32, |
| 23252 | GIR_MakeTempReg, /*TempRegID*/51, /*TypeID*/GILLT_s32, |
| 23253 | GIR_MakeTempReg, /*TempRegID*/52, /*TypeID*/GILLT_s32, |
| 23254 | GIR_MakeTempReg, /*TempRegID*/53, /*TypeID*/GILLT_s32, |
| 23255 | GIR_MakeTempReg, /*TempRegID*/54, /*TypeID*/GILLT_s32, |
| 23256 | GIR_MakeTempReg, /*TempRegID*/55, /*TypeID*/GILLT_s32, |
| 23257 | GIR_MakeTempReg, /*TempRegID*/56, /*TypeID*/GILLT_s32, |
| 23258 | GIR_MakeTempReg, /*TempRegID*/57, /*TypeID*/GILLT_s32, |
| 23259 | GIR_MakeTempReg, /*TempRegID*/58, /*TypeID*/GILLT_s32, |
| 23260 | GIR_MakeTempReg, /*TempRegID*/59, /*TypeID*/GILLT_s32, |
| 23261 | GIR_MakeTempReg, /*TempRegID*/60, /*TypeID*/GILLT_s32, |
| 23262 | GIR_MakeTempReg, /*TempRegID*/61, /*TypeID*/GILLT_s32, |
| 23263 | GIR_MakeTempReg, /*TempRegID*/62, /*TypeID*/GILLT_s32, |
| 23264 | GIR_MakeTempReg, /*TempRegID*/63, /*TypeID*/GILLT_s32, |
| 23265 | GIR_MakeTempReg, /*TempRegID*/64, /*TypeID*/GILLT_s32, |
| 23266 | GIR_MakeTempReg, /*TempRegID*/65, /*TypeID*/GILLT_s32, |
| 23267 | GIR_MakeTempReg, /*TempRegID*/66, /*TypeID*/GILLT_s32, |
| 23268 | GIR_MakeTempReg, /*TempRegID*/67, /*TypeID*/GILLT_s32, |
| 23269 | GIR_MakeTempReg, /*TempRegID*/68, /*TypeID*/GILLT_s32, |
| 23270 | GIR_MakeTempReg, /*TempRegID*/69, /*TypeID*/GILLT_s32, |
| 23271 | GIR_MakeTempReg, /*TempRegID*/70, /*TypeID*/GILLT_s32, |
| 23272 | GIR_MakeTempReg, /*TempRegID*/71, /*TypeID*/GILLT_s32, |
| 23273 | GIR_MakeTempReg, /*TempRegID*/72, /*TypeID*/GILLT_s32, |
| 23274 | GIR_MakeTempReg, /*TempRegID*/73, /*TypeID*/GILLT_s32, |
| 23275 | GIR_MakeTempReg, /*TempRegID*/74, /*TypeID*/GILLT_s32, |
| 23276 | GIR_MakeTempReg, /*TempRegID*/75, /*TypeID*/GILLT_s32, |
| 23277 | GIR_MakeTempReg, /*TempRegID*/76, /*TypeID*/GILLT_s32, |
| 23278 | GIR_MakeTempReg, /*TempRegID*/77, /*TypeID*/GILLT_s32, |
| 23279 | GIR_MakeTempReg, /*TempRegID*/78, /*TypeID*/GILLT_s32, |
| 23280 | GIR_MakeTempReg, /*TempRegID*/79, /*TypeID*/GILLT_s32, |
| 23281 | GIR_MakeTempReg, /*TempRegID*/80, /*TypeID*/GILLT_s32, |
| 23282 | GIR_MakeTempReg, /*TempRegID*/81, /*TypeID*/GILLT_s32, |
| 23283 | GIR_MakeTempReg, /*TempRegID*/82, /*TypeID*/GILLT_s32, |
| 23284 | GIR_MakeTempReg, /*TempRegID*/83, /*TypeID*/GILLT_s32, |
| 23285 | GIR_MakeTempReg, /*TempRegID*/84, /*TypeID*/GILLT_s32, |
| 23286 | GIR_MakeTempReg, /*TempRegID*/85, /*TypeID*/GILLT_s32, |
| 23287 | GIR_MakeTempReg, /*TempRegID*/86, /*TypeID*/GILLT_s32, |
| 23288 | GIR_MakeTempReg, /*TempRegID*/87, /*TypeID*/GILLT_s32, |
| 23289 | GIR_MakeTempReg, /*TempRegID*/88, /*TypeID*/GILLT_s32, |
| 23290 | GIR_MakeTempReg, /*TempRegID*/89, /*TypeID*/GILLT_s32, |
| 23291 | GIR_MakeTempReg, /*TempRegID*/90, /*TypeID*/GILLT_s32, |
| 23292 | GIR_MakeTempReg, /*TempRegID*/91, /*TypeID*/GILLT_s32, |
| 23293 | GIR_MakeTempReg, /*TempRegID*/92, /*TypeID*/GILLT_s32, |
| 23294 | GIR_MakeTempReg, /*TempRegID*/93, /*TypeID*/GILLT_s32, |
| 23295 | GIR_MakeTempReg, /*TempRegID*/94, /*TypeID*/GILLT_s32, |
| 23296 | GIR_MakeTempReg, /*TempRegID*/95, /*TypeID*/GILLT_s32, |
| 23297 | GIR_MakeTempReg, /*TempRegID*/96, /*TypeID*/GILLT_s32, |
| 23298 | GIR_MakeTempReg, /*TempRegID*/97, /*TypeID*/GILLT_s32, |
| 23299 | GIR_MakeTempReg, /*TempRegID*/98, /*TypeID*/GILLT_s32, |
| 23300 | GIR_MakeTempReg, /*TempRegID*/99, /*TypeID*/GILLT_s32, |
| 23301 | GIR_MakeTempReg, /*TempRegID*/100, /*TypeID*/GILLT_s32, |
| 23302 | GIR_MakeTempReg, /*TempRegID*/101, /*TypeID*/GILLT_s32, |
| 23303 | GIR_MakeTempReg, /*TempRegID*/102, /*TypeID*/GILLT_s32, |
| 23304 | GIR_MakeTempReg, /*TempRegID*/103, /*TypeID*/GILLT_s32, |
| 23305 | GIR_MakeTempReg, /*TempRegID*/104, /*TypeID*/GILLT_s32, |
| 23306 | GIR_MakeTempReg, /*TempRegID*/105, /*TypeID*/GILLT_s32, |
| 23307 | GIR_MakeTempReg, /*TempRegID*/106, /*TypeID*/GILLT_s32, |
| 23308 | GIR_MakeTempReg, /*TempRegID*/107, /*TypeID*/GILLT_s32, |
| 23309 | GIR_MakeTempReg, /*TempRegID*/108, /*TypeID*/GILLT_s32, |
| 23310 | GIR_MakeTempReg, /*TempRegID*/109, /*TypeID*/GILLT_s32, |
| 23311 | GIR_MakeTempReg, /*TempRegID*/110, /*TypeID*/GILLT_s32, |
| 23312 | GIR_MakeTempReg, /*TempRegID*/111, /*TypeID*/GILLT_s32, |
| 23313 | GIR_MakeTempReg, /*TempRegID*/112, /*TypeID*/GILLT_s32, |
| 23314 | GIR_MakeTempReg, /*TempRegID*/113, /*TypeID*/GILLT_s32, |
| 23315 | GIR_MakeTempReg, /*TempRegID*/114, /*TypeID*/GILLT_s32, |
| 23316 | GIR_MakeTempReg, /*TempRegID*/115, /*TypeID*/GILLT_s32, |
| 23317 | GIR_MakeTempReg, /*TempRegID*/116, /*TypeID*/GILLT_s32, |
| 23318 | GIR_MakeTempReg, /*TempRegID*/117, /*TypeID*/GILLT_s32, |
| 23319 | GIR_MakeTempReg, /*TempRegID*/118, /*TypeID*/GILLT_s32, |
| 23320 | GIR_MakeTempReg, /*TempRegID*/119, /*TypeID*/GILLT_s32, |
| 23321 | GIR_MakeTempReg, /*TempRegID*/120, /*TypeID*/GILLT_s32, |
| 23322 | GIR_MakeTempReg, /*TempRegID*/121, /*TypeID*/GILLT_s32, |
| 23323 | GIR_MakeTempReg, /*TempRegID*/122, /*TypeID*/GILLT_s32, |
| 23324 | GIR_MakeTempReg, /*TempRegID*/123, /*TypeID*/GILLT_s32, |
| 23325 | GIR_MakeTempReg, /*TempRegID*/124, /*TypeID*/GILLT_s32, |
| 23326 | GIR_MakeTempReg, /*TempRegID*/125, /*TypeID*/GILLT_s32, |
| 23327 | GIR_MakeTempReg, /*TempRegID*/126, /*TypeID*/GILLT_s32, |
| 23328 | GIR_MakeTempReg, /*TempRegID*/127, /*TypeID*/GILLT_s32, |
| 23329 | GIR_MakeTempReg, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23330 | GIR_MakeTempReg, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23331 | GIR_MakeTempReg, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23332 | GIR_MakeTempReg, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23333 | GIR_MakeTempReg, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23334 | GIR_MakeTempReg, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23335 | GIR_MakeTempReg, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23336 | GIR_MakeTempReg, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23337 | GIR_MakeTempReg, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23338 | GIR_MakeTempReg, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23339 | GIR_MakeTempReg, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23340 | GIR_MakeTempReg, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23341 | GIR_MakeTempReg, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23342 | GIR_MakeTempReg, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23343 | GIR_MakeTempReg, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23344 | GIR_MakeTempReg, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23345 | GIR_MakeTempReg, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23346 | GIR_MakeTempReg, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23347 | GIR_MakeTempReg, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23348 | GIR_MakeTempReg, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23349 | GIR_MakeTempReg, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23350 | GIR_MakeTempReg, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23351 | GIR_MakeTempReg, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23352 | GIR_MakeTempReg, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23353 | GIR_MakeTempReg, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23354 | GIR_MakeTempReg, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23355 | GIR_MakeTempReg, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23356 | GIR_MakeTempReg, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23357 | GIR_MakeTempReg, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23358 | GIR_MakeTempReg, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23359 | GIR_MakeTempReg, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23360 | GIR_MakeTempReg, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23361 | GIR_MakeTempReg, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23362 | GIR_MakeTempReg, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23363 | GIR_MakeTempReg, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23364 | GIR_MakeTempReg, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23365 | GIR_MakeTempReg, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23366 | GIR_MakeTempReg, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23367 | GIR_MakeTempReg, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23368 | GIR_MakeTempReg, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23369 | GIR_MakeTempReg, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23370 | GIR_MakeTempReg, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23371 | GIR_MakeTempReg, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23372 | GIR_MakeTempReg, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23373 | GIR_MakeTempReg, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23374 | GIR_MakeTempReg, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23375 | GIR_MakeTempReg, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23376 | GIR_MakeTempReg, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23377 | GIR_MakeTempReg, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23378 | GIR_MakeTempReg, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23379 | GIR_MakeTempReg, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23380 | GIR_MakeTempReg, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23381 | GIR_MakeTempReg, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23382 | GIR_MakeTempReg, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23383 | GIR_MakeTempReg, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23384 | GIR_MakeTempReg, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23385 | GIR_MakeTempReg, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23386 | GIR_MakeTempReg, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23387 | GIR_MakeTempReg, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23388 | GIR_MakeTempReg, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23389 | GIR_MakeTempReg, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23390 | GIR_MakeTempReg, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23391 | GIR_MakeTempReg, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23392 | GIR_MakeTempReg, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 23393 | GIR_BuildMI, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23394 | GIR_AddTempRegister, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23395 | GIR_AddImm, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 23396 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, |
| 23397 | GIR_BuildMI, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23398 | GIR_AddTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23399 | GIR_AddSimpleTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, |
| 23400 | GIR_AddImm, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 23401 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, |
| 23402 | GIR_BuildMI, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23403 | GIR_AddTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23404 | GIR_AddImm, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 23405 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, |
| 23406 | GIR_BuildMI, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23407 | GIR_AddTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23408 | GIR_AddSimpleTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, |
| 23409 | GIR_AddImm, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 23410 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, |
| 23411 | GIR_BuildMI, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23412 | GIR_AddTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23413 | GIR_AddImm, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23414 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, |
| 23415 | GIR_BuildMI, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23416 | GIR_AddTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23417 | GIR_AddSimpleTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, |
| 23418 | GIR_AddImm, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23419 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, |
| 23420 | GIR_BuildMI, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23421 | GIR_AddTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23422 | GIR_Copy, /*NewInsnID*//* 186(*/0xBA, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23423 | GIR_AddImm8, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/1, |
| 23424 | GIR_AddImm8, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/0, |
| 23425 | GIR_AddImm8, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/30, |
| 23426 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, |
| 23427 | GIR_BuildMI, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23428 | GIR_AddTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23429 | GIR_AddSimpleTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, |
| 23430 | GIR_AddSimpleTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, |
| 23431 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, |
| 23432 | GIR_BuildMI, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23433 | GIR_AddTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23434 | GIR_AddImm, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23435 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, |
| 23436 | GIR_BuildMI, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23437 | GIR_AddTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23438 | GIR_AddSimpleTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, |
| 23439 | GIR_AddImm, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23440 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, |
| 23441 | GIR_BuildMI, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23442 | GIR_AddTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23443 | GIR_Copy, /*NewInsnID*//* 182(*/0xB6, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23444 | GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/31, |
| 23445 | GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/1, |
| 23446 | GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/31, |
| 23447 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, |
| 23448 | GIR_BuildMI, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23449 | GIR_AddTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23450 | GIR_AddSimpleTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, |
| 23451 | GIR_AddSimpleTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, |
| 23452 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, |
| 23453 | GIR_BuildMI, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23454 | GIR_AddTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23455 | GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, |
| 23456 | GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, |
| 23457 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, |
| 23458 | GIR_BuildMI, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23459 | GIR_AddTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23460 | GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, |
| 23461 | GIR_AddImm8, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/2, |
| 23462 | GIR_AddImm8, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/0, |
| 23463 | GIR_AddImm8, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/29, |
| 23464 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, |
| 23465 | GIR_BuildMI, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23466 | GIR_AddTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23467 | GIR_AddSimpleTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, |
| 23468 | GIR_AddSimpleTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, |
| 23469 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, |
| 23470 | GIR_BuildMI, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23471 | GIR_AddTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23472 | GIR_AddImm, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 23473 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, |
| 23474 | GIR_BuildMI, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23475 | GIR_AddTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23476 | GIR_AddSimpleTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, |
| 23477 | GIR_AddImm, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 23478 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, |
| 23479 | GIR_BuildMI, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23480 | GIR_AddTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23481 | GIR_AddImm, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23482 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, |
| 23483 | GIR_BuildMI, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23484 | GIR_AddTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23485 | GIR_AddSimpleTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, |
| 23486 | GIR_AddImm, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23487 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, |
| 23488 | GIR_BuildMI, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23489 | GIR_AddTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23490 | GIR_Copy, /*NewInsnID*//* 173(*/0xAD, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23491 | GIR_AddImm8, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/1, |
| 23492 | GIR_AddImm8, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/0, |
| 23493 | GIR_AddImm8, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/30, |
| 23494 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, |
| 23495 | GIR_BuildMI, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23496 | GIR_AddTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23497 | GIR_AddSimpleTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, |
| 23498 | GIR_AddSimpleTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, |
| 23499 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, |
| 23500 | GIR_BuildMI, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23501 | GIR_AddTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23502 | GIR_AddImm, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23503 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, |
| 23504 | GIR_BuildMI, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23505 | GIR_AddTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23506 | GIR_AddSimpleTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, |
| 23507 | GIR_AddImm, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23508 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, |
| 23509 | GIR_BuildMI, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23510 | GIR_AddTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23511 | GIR_Copy, /*NewInsnID*//* 169(*/0xA9, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23512 | GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/31, |
| 23513 | GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/1, |
| 23514 | GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/31, |
| 23515 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, |
| 23516 | GIR_BuildMI, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23517 | GIR_AddTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23518 | GIR_AddSimpleTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, |
| 23519 | GIR_AddSimpleTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, |
| 23520 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, |
| 23521 | GIR_BuildMI, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23522 | GIR_AddTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23523 | GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, |
| 23524 | GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, |
| 23525 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, |
| 23526 | GIR_BuildMI, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23527 | GIR_AddTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23528 | GIR_AddSimpleTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, |
| 23529 | GIR_AddImm8, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/30, |
| 23530 | GIR_AddImm8, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/2, |
| 23531 | GIR_AddImm8, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/31, |
| 23532 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, |
| 23533 | GIR_BuildMI, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23534 | GIR_AddTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23535 | GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, |
| 23536 | GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, |
| 23537 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, |
| 23538 | GIR_BuildMI, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23539 | GIR_AddTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23540 | GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, |
| 23541 | GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, |
| 23542 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, |
| 23543 | GIR_BuildMI, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23544 | GIR_AddTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23545 | GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, |
| 23546 | GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/4, |
| 23547 | GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/0, |
| 23548 | GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/27, |
| 23549 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, |
| 23550 | GIR_BuildMI, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23551 | GIR_AddTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23552 | GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, |
| 23553 | GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, |
| 23554 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, |
| 23555 | GIR_BuildMI, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23556 | GIR_AddTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23557 | GIR_AddImm, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 23558 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, |
| 23559 | GIR_BuildMI, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23560 | GIR_AddTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23561 | GIR_AddSimpleTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, |
| 23562 | GIR_AddImm, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 23563 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, |
| 23564 | GIR_BuildMI, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23565 | GIR_AddTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23566 | GIR_AddImm, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 23567 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, |
| 23568 | GIR_BuildMI, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23569 | GIR_AddTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23570 | GIR_AddSimpleTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, |
| 23571 | GIR_AddImm, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 23572 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, |
| 23573 | GIR_BuildMI, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23574 | GIR_AddTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23575 | GIR_AddImm, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23576 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, |
| 23577 | GIR_BuildMI, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23578 | GIR_AddTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23579 | GIR_AddSimpleTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, |
| 23580 | GIR_AddImm, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23581 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, |
| 23582 | GIR_BuildMI, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23583 | GIR_AddTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23584 | GIR_Copy, /*NewInsnID*//* 155(*/0x9B, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23585 | GIR_AddImm8, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/1, |
| 23586 | GIR_AddImm8, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/0, |
| 23587 | GIR_AddImm8, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/30, |
| 23588 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, |
| 23589 | GIR_BuildMI, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23590 | GIR_AddTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23591 | GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, |
| 23592 | GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, |
| 23593 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, |
| 23594 | GIR_BuildMI, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23595 | GIR_AddTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23596 | GIR_AddImm, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23597 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 153(*/0x99, 0x01/*)*/, |
| 23598 | GIR_BuildMI, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23599 | GIR_AddTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23600 | GIR_AddSimpleTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, |
| 23601 | GIR_AddImm, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23602 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 152(*/0x98, 0x01/*)*/, |
| 23603 | GIR_BuildMI, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23604 | GIR_AddTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23605 | GIR_Copy, /*NewInsnID*//* 151(*/0x97, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23606 | GIR_AddImm8, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/31, |
| 23607 | GIR_AddImm8, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/1, |
| 23608 | GIR_AddImm8, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/31, |
| 23609 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 151(*/0x97, 0x01/*)*/, |
| 23610 | GIR_BuildMI, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23611 | GIR_AddTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23612 | GIR_AddSimpleTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, |
| 23613 | GIR_AddSimpleTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, |
| 23614 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 150(*/0x96, 0x01/*)*/, |
| 23615 | GIR_BuildMI, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23616 | GIR_AddTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23617 | GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, |
| 23618 | GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, |
| 23619 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 149(*/0x95, 0x01/*)*/, |
| 23620 | GIR_BuildMI, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23621 | GIR_AddTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23622 | GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, |
| 23623 | GIR_AddImm8, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Imm*/2, |
| 23624 | GIR_AddImm8, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Imm*/0, |
| 23625 | GIR_AddImm8, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Imm*/29, |
| 23626 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 148(*/0x94, 0x01/*)*/, |
| 23627 | GIR_BuildMI, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23628 | GIR_AddTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23629 | GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, |
| 23630 | GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, |
| 23631 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 147(*/0x93, 0x01/*)*/, |
| 23632 | GIR_BuildMI, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23633 | GIR_AddTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23634 | GIR_AddImm, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 23635 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 146(*/0x92, 0x01/*)*/, |
| 23636 | GIR_BuildMI, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23637 | GIR_AddTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23638 | GIR_AddSimpleTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, |
| 23639 | GIR_AddImm, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 23640 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 145(*/0x91, 0x01/*)*/, |
| 23641 | GIR_BuildMI, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23642 | GIR_AddTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23643 | GIR_AddImm, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23644 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 144(*/0x90, 0x01/*)*/, |
| 23645 | GIR_BuildMI, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23646 | GIR_AddTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23647 | GIR_AddSimpleTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, |
| 23648 | GIR_AddImm, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 23649 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, |
| 23650 | GIR_BuildMI, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23651 | GIR_AddTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23652 | GIR_Copy, /*NewInsnID*//* 142(*/0x8E, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23653 | GIR_AddImm8, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/1, |
| 23654 | GIR_AddImm8, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/0, |
| 23655 | GIR_AddImm8, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/30, |
| 23656 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, |
| 23657 | GIR_BuildMI, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23658 | GIR_AddTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23659 | GIR_AddSimpleTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, |
| 23660 | GIR_AddSimpleTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, |
| 23661 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, |
| 23662 | GIR_BuildMI, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23663 | GIR_AddTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23664 | GIR_AddImm, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23665 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, |
| 23666 | GIR_BuildMI, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23667 | GIR_AddTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23668 | GIR_AddSimpleTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, |
| 23669 | GIR_AddImm, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 23670 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, |
| 23671 | GIR_BuildMI, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23672 | GIR_AddTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23673 | GIR_Copy, /*NewInsnID*//* 138(*/0x8A, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23674 | GIR_AddImm8, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/31, |
| 23675 | GIR_AddImm8, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/1, |
| 23676 | GIR_AddImm8, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/31, |
| 23677 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, |
| 23678 | GIR_BuildMI, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23679 | GIR_AddTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23680 | GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, |
| 23681 | GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, |
| 23682 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 137(*/0x89, 0x01/*)*/, |
| 23683 | GIR_BuildMI, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23684 | GIR_AddTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23685 | GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, |
| 23686 | GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, |
| 23687 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 136(*/0x88, 0x01/*)*/, |
| 23688 | GIR_BuildMI, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23689 | GIR_AddTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23690 | GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, |
| 23691 | GIR_AddImm8, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/30, |
| 23692 | GIR_AddImm8, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/2, |
| 23693 | GIR_AddImm8, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/31, |
| 23694 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 135(*/0x87, 0x01/*)*/, |
| 23695 | GIR_BuildMI, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23696 | GIR_AddTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23697 | GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, |
| 23698 | GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, |
| 23699 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 134(*/0x86, 0x01/*)*/, |
| 23700 | GIR_BuildMI, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23701 | GIR_AddTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23702 | GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, |
| 23703 | GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, |
| 23704 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 133(*/0x85, 0x01/*)*/, |
| 23705 | GIR_BuildMI, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23706 | GIR_AddTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23707 | GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, |
| 23708 | GIR_AddImm8, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/28, |
| 23709 | GIR_AddImm8, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/4, |
| 23710 | GIR_AddImm8, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/31, |
| 23711 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 132(*/0x84, 0x01/*)*/, |
| 23712 | GIR_BuildMI, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23713 | GIR_AddTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23714 | GIR_AddSimpleTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, |
| 23715 | GIR_AddSimpleTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, |
| 23716 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 131(*/0x83, 0x01/*)*/, |
| 23717 | GIR_BuildMI, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23718 | GIR_AddTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23719 | GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, |
| 23720 | GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, |
| 23721 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 130(*/0x82, 0x01/*)*/, |
| 23722 | GIR_BuildMI, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23723 | GIR_AddTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23724 | GIR_AddImm, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 23725 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 129(*/0x81, 0x01/*)*/, |
| 23726 | GIR_BuildMI, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23727 | GIR_AddTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*/127, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23728 | GIR_AddSimpleTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, |
| 23729 | GIR_AddImm, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 23730 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 128(*/0x80, 0x01/*)*/, |
| 23731 | GIR_BuildMI, /*InsnID*/127, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23732 | GIR_AddTempRegister, /*InsnID*/127, /*TempRegID*/126, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23733 | GIR_AddImm, /*InsnID*/127, /*Imm*/GIMT_Encode8(52428), |
| 23734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/127, |
| 23735 | GIR_BuildMI, /*InsnID*/126, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23736 | GIR_AddTempRegister, /*InsnID*/126, /*TempRegID*/125, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23737 | GIR_AddSimpleTempRegister, /*InsnID*/126, /*TempRegID*/126, |
| 23738 | GIR_AddImm, /*InsnID*/126, /*Imm*/GIMT_Encode8(52428), |
| 23739 | GIR_ConstrainSelectedInstOperands, /*InsnID*/126, |
| 23740 | GIR_BuildMI, /*InsnID*/125, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23741 | GIR_AddTempRegister, /*InsnID*/125, /*TempRegID*/124, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23742 | GIR_AddImm, /*InsnID*/125, /*Imm*/GIMT_Encode8(43690), |
| 23743 | GIR_ConstrainSelectedInstOperands, /*InsnID*/125, |
| 23744 | GIR_BuildMI, /*InsnID*/124, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23745 | GIR_AddTempRegister, /*InsnID*/124, /*TempRegID*/123, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23746 | GIR_AddSimpleTempRegister, /*InsnID*/124, /*TempRegID*/124, |
| 23747 | GIR_AddImm, /*InsnID*/124, /*Imm*/GIMT_Encode8(43690), |
| 23748 | GIR_ConstrainSelectedInstOperands, /*InsnID*/124, |
| 23749 | GIR_BuildMI, /*InsnID*/123, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23750 | GIR_AddTempRegister, /*InsnID*/123, /*TempRegID*/122, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23751 | GIR_Copy, /*NewInsnID*/123, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23752 | GIR_AddImm8, /*InsnID*/123, /*Imm*/1, |
| 23753 | GIR_AddImm8, /*InsnID*/123, /*Imm*/0, |
| 23754 | GIR_AddImm8, /*InsnID*/123, /*Imm*/30, |
| 23755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/123, |
| 23756 | GIR_BuildMI, /*InsnID*/122, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23757 | GIR_AddTempRegister, /*InsnID*/122, /*TempRegID*/121, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23758 | GIR_AddSimpleTempRegister, /*InsnID*/122, /*TempRegID*/122, |
| 23759 | GIR_AddSimpleTempRegister, /*InsnID*/122, /*TempRegID*/123, |
| 23760 | GIR_ConstrainSelectedInstOperands, /*InsnID*/122, |
| 23761 | GIR_BuildMI, /*InsnID*/121, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23762 | GIR_AddTempRegister, /*InsnID*/121, /*TempRegID*/120, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23763 | GIR_AddImm, /*InsnID*/121, /*Imm*/GIMT_Encode8(21845), |
| 23764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/121, |
| 23765 | GIR_BuildMI, /*InsnID*/120, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23766 | GIR_AddTempRegister, /*InsnID*/120, /*TempRegID*/119, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23767 | GIR_AddSimpleTempRegister, /*InsnID*/120, /*TempRegID*/120, |
| 23768 | GIR_AddImm, /*InsnID*/120, /*Imm*/GIMT_Encode8(21845), |
| 23769 | GIR_ConstrainSelectedInstOperands, /*InsnID*/120, |
| 23770 | GIR_BuildMI, /*InsnID*/119, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23771 | GIR_AddTempRegister, /*InsnID*/119, /*TempRegID*/118, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23772 | GIR_Copy, /*NewInsnID*/119, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23773 | GIR_AddImm8, /*InsnID*/119, /*Imm*/31, |
| 23774 | GIR_AddImm8, /*InsnID*/119, /*Imm*/1, |
| 23775 | GIR_AddImm8, /*InsnID*/119, /*Imm*/31, |
| 23776 | GIR_ConstrainSelectedInstOperands, /*InsnID*/119, |
| 23777 | GIR_BuildMI, /*InsnID*/118, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23778 | GIR_AddTempRegister, /*InsnID*/118, /*TempRegID*/117, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23779 | GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/118, |
| 23780 | GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/119, |
| 23781 | GIR_ConstrainSelectedInstOperands, /*InsnID*/118, |
| 23782 | GIR_BuildMI, /*InsnID*/117, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23783 | GIR_AddTempRegister, /*InsnID*/117, /*TempRegID*/116, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23784 | GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/117, |
| 23785 | GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/121, |
| 23786 | GIR_ConstrainSelectedInstOperands, /*InsnID*/117, |
| 23787 | GIR_BuildMI, /*InsnID*/116, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23788 | GIR_AddTempRegister, /*InsnID*/116, /*TempRegID*/115, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23789 | GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/116, |
| 23790 | GIR_AddImm8, /*InsnID*/116, /*Imm*/2, |
| 23791 | GIR_AddImm8, /*InsnID*/116, /*Imm*/0, |
| 23792 | GIR_AddImm8, /*InsnID*/116, /*Imm*/29, |
| 23793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/116, |
| 23794 | GIR_BuildMI, /*InsnID*/115, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23795 | GIR_AddTempRegister, /*InsnID*/115, /*TempRegID*/114, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23796 | GIR_AddSimpleTempRegister, /*InsnID*/115, /*TempRegID*/115, |
| 23797 | GIR_AddSimpleTempRegister, /*InsnID*/115, /*TempRegID*/125, |
| 23798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/115, |
| 23799 | GIR_BuildMI, /*InsnID*/114, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23800 | GIR_AddTempRegister, /*InsnID*/114, /*TempRegID*/113, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23801 | GIR_AddImm, /*InsnID*/114, /*Imm*/GIMT_Encode8(13107), |
| 23802 | GIR_ConstrainSelectedInstOperands, /*InsnID*/114, |
| 23803 | GIR_BuildMI, /*InsnID*/113, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23804 | GIR_AddTempRegister, /*InsnID*/113, /*TempRegID*/112, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23805 | GIR_AddSimpleTempRegister, /*InsnID*/113, /*TempRegID*/113, |
| 23806 | GIR_AddImm, /*InsnID*/113, /*Imm*/GIMT_Encode8(13107), |
| 23807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/113, |
| 23808 | GIR_BuildMI, /*InsnID*/112, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23809 | GIR_AddTempRegister, /*InsnID*/112, /*TempRegID*/111, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23810 | GIR_AddImm, /*InsnID*/112, /*Imm*/GIMT_Encode8(43690), |
| 23811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/112, |
| 23812 | GIR_BuildMI, /*InsnID*/111, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23813 | GIR_AddTempRegister, /*InsnID*/111, /*TempRegID*/110, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23814 | GIR_AddSimpleTempRegister, /*InsnID*/111, /*TempRegID*/111, |
| 23815 | GIR_AddImm, /*InsnID*/111, /*Imm*/GIMT_Encode8(43690), |
| 23816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/111, |
| 23817 | GIR_BuildMI, /*InsnID*/110, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23818 | GIR_AddTempRegister, /*InsnID*/110, /*TempRegID*/109, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23819 | GIR_Copy, /*NewInsnID*/110, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23820 | GIR_AddImm8, /*InsnID*/110, /*Imm*/1, |
| 23821 | GIR_AddImm8, /*InsnID*/110, /*Imm*/0, |
| 23822 | GIR_AddImm8, /*InsnID*/110, /*Imm*/30, |
| 23823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/110, |
| 23824 | GIR_BuildMI, /*InsnID*/109, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23825 | GIR_AddTempRegister, /*InsnID*/109, /*TempRegID*/108, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23826 | GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/109, |
| 23827 | GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/110, |
| 23828 | GIR_ConstrainSelectedInstOperands, /*InsnID*/109, |
| 23829 | GIR_BuildMI, /*InsnID*/108, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23830 | GIR_AddTempRegister, /*InsnID*/108, /*TempRegID*/107, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23831 | GIR_AddImm, /*InsnID*/108, /*Imm*/GIMT_Encode8(21845), |
| 23832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/108, |
| 23833 | GIR_BuildMI, /*InsnID*/107, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23834 | GIR_AddTempRegister, /*InsnID*/107, /*TempRegID*/106, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23835 | GIR_AddSimpleTempRegister, /*InsnID*/107, /*TempRegID*/107, |
| 23836 | GIR_AddImm, /*InsnID*/107, /*Imm*/GIMT_Encode8(21845), |
| 23837 | GIR_ConstrainSelectedInstOperands, /*InsnID*/107, |
| 23838 | GIR_BuildMI, /*InsnID*/106, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23839 | GIR_AddTempRegister, /*InsnID*/106, /*TempRegID*/105, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23840 | GIR_Copy, /*NewInsnID*/106, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23841 | GIR_AddImm8, /*InsnID*/106, /*Imm*/31, |
| 23842 | GIR_AddImm8, /*InsnID*/106, /*Imm*/1, |
| 23843 | GIR_AddImm8, /*InsnID*/106, /*Imm*/31, |
| 23844 | GIR_ConstrainSelectedInstOperands, /*InsnID*/106, |
| 23845 | GIR_BuildMI, /*InsnID*/105, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23846 | GIR_AddTempRegister, /*InsnID*/105, /*TempRegID*/104, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23847 | GIR_AddSimpleTempRegister, /*InsnID*/105, /*TempRegID*/105, |
| 23848 | GIR_AddSimpleTempRegister, /*InsnID*/105, /*TempRegID*/106, |
| 23849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/105, |
| 23850 | GIR_BuildMI, /*InsnID*/104, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23851 | GIR_AddTempRegister, /*InsnID*/104, /*TempRegID*/103, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23852 | GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/104, |
| 23853 | GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/108, |
| 23854 | GIR_ConstrainSelectedInstOperands, /*InsnID*/104, |
| 23855 | GIR_BuildMI, /*InsnID*/103, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23856 | GIR_AddTempRegister, /*InsnID*/103, /*TempRegID*/102, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23857 | GIR_AddSimpleTempRegister, /*InsnID*/103, /*TempRegID*/103, |
| 23858 | GIR_AddImm8, /*InsnID*/103, /*Imm*/30, |
| 23859 | GIR_AddImm8, /*InsnID*/103, /*Imm*/2, |
| 23860 | GIR_AddImm8, /*InsnID*/103, /*Imm*/31, |
| 23861 | GIR_ConstrainSelectedInstOperands, /*InsnID*/103, |
| 23862 | GIR_BuildMI, /*InsnID*/102, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23863 | GIR_AddTempRegister, /*InsnID*/102, /*TempRegID*/101, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23864 | GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/102, |
| 23865 | GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/112, |
| 23866 | GIR_ConstrainSelectedInstOperands, /*InsnID*/102, |
| 23867 | GIR_BuildMI, /*InsnID*/101, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23868 | GIR_AddTempRegister, /*InsnID*/101, /*TempRegID*/100, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23869 | GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/101, |
| 23870 | GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/114, |
| 23871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/101, |
| 23872 | GIR_BuildMI, /*InsnID*/100, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23873 | GIR_AddTempRegister, /*InsnID*/100, /*TempRegID*/99, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23874 | GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/100, |
| 23875 | GIR_AddImm8, /*InsnID*/100, /*Imm*/4, |
| 23876 | GIR_AddImm8, /*InsnID*/100, /*Imm*/0, |
| 23877 | GIR_AddImm8, /*InsnID*/100, /*Imm*/27, |
| 23878 | GIR_ConstrainSelectedInstOperands, /*InsnID*/100, |
| 23879 | GIR_BuildMI, /*InsnID*/99, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23880 | GIR_AddTempRegister, /*InsnID*/99, /*TempRegID*/98, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23881 | GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/99, |
| 23882 | GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/127, |
| 23883 | GIR_ConstrainSelectedInstOperands, /*InsnID*/99, |
| 23884 | GIR_BuildMI, /*InsnID*/98, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23885 | GIR_AddTempRegister, /*InsnID*/98, /*TempRegID*/97, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23886 | GIR_AddImm, /*InsnID*/98, /*Imm*/GIMT_Encode8(3855), |
| 23887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/98, |
| 23888 | GIR_BuildMI, /*InsnID*/97, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23889 | GIR_AddTempRegister, /*InsnID*/97, /*TempRegID*/96, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23890 | GIR_AddSimpleTempRegister, /*InsnID*/97, /*TempRegID*/97, |
| 23891 | GIR_AddImm, /*InsnID*/97, /*Imm*/GIMT_Encode8(3855), |
| 23892 | GIR_ConstrainSelectedInstOperands, /*InsnID*/97, |
| 23893 | GIR_BuildMI, /*InsnID*/96, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23894 | GIR_AddTempRegister, /*InsnID*/96, /*TempRegID*/95, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23895 | GIR_AddImm, /*InsnID*/96, /*Imm*/GIMT_Encode8(52428), |
| 23896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/96, |
| 23897 | GIR_BuildMI, /*InsnID*/95, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23898 | GIR_AddTempRegister, /*InsnID*/95, /*TempRegID*/94, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23899 | GIR_AddSimpleTempRegister, /*InsnID*/95, /*TempRegID*/95, |
| 23900 | GIR_AddImm, /*InsnID*/95, /*Imm*/GIMT_Encode8(52428), |
| 23901 | GIR_ConstrainSelectedInstOperands, /*InsnID*/95, |
| 23902 | GIR_BuildMI, /*InsnID*/94, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23903 | GIR_AddTempRegister, /*InsnID*/94, /*TempRegID*/93, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23904 | GIR_AddImm, /*InsnID*/94, /*Imm*/GIMT_Encode8(43690), |
| 23905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/94, |
| 23906 | GIR_BuildMI, /*InsnID*/93, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23907 | GIR_AddTempRegister, /*InsnID*/93, /*TempRegID*/92, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23908 | GIR_AddSimpleTempRegister, /*InsnID*/93, /*TempRegID*/93, |
| 23909 | GIR_AddImm, /*InsnID*/93, /*Imm*/GIMT_Encode8(43690), |
| 23910 | GIR_ConstrainSelectedInstOperands, /*InsnID*/93, |
| 23911 | GIR_BuildMI, /*InsnID*/92, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23912 | GIR_AddTempRegister, /*InsnID*/92, /*TempRegID*/91, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23913 | GIR_Copy, /*NewInsnID*/92, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23914 | GIR_AddImm8, /*InsnID*/92, /*Imm*/1, |
| 23915 | GIR_AddImm8, /*InsnID*/92, /*Imm*/0, |
| 23916 | GIR_AddImm8, /*InsnID*/92, /*Imm*/30, |
| 23917 | GIR_ConstrainSelectedInstOperands, /*InsnID*/92, |
| 23918 | GIR_BuildMI, /*InsnID*/91, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23919 | GIR_AddTempRegister, /*InsnID*/91, /*TempRegID*/90, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23920 | GIR_AddSimpleTempRegister, /*InsnID*/91, /*TempRegID*/91, |
| 23921 | GIR_AddSimpleTempRegister, /*InsnID*/91, /*TempRegID*/92, |
| 23922 | GIR_ConstrainSelectedInstOperands, /*InsnID*/91, |
| 23923 | GIR_BuildMI, /*InsnID*/90, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23924 | GIR_AddTempRegister, /*InsnID*/90, /*TempRegID*/89, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23925 | GIR_AddImm, /*InsnID*/90, /*Imm*/GIMT_Encode8(21845), |
| 23926 | GIR_ConstrainSelectedInstOperands, /*InsnID*/90, |
| 23927 | GIR_BuildMI, /*InsnID*/89, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23928 | GIR_AddTempRegister, /*InsnID*/89, /*TempRegID*/88, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23929 | GIR_AddSimpleTempRegister, /*InsnID*/89, /*TempRegID*/89, |
| 23930 | GIR_AddImm, /*InsnID*/89, /*Imm*/GIMT_Encode8(21845), |
| 23931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/89, |
| 23932 | GIR_BuildMI, /*InsnID*/88, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23933 | GIR_AddTempRegister, /*InsnID*/88, /*TempRegID*/87, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23934 | GIR_Copy, /*NewInsnID*/88, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23935 | GIR_AddImm8, /*InsnID*/88, /*Imm*/31, |
| 23936 | GIR_AddImm8, /*InsnID*/88, /*Imm*/1, |
| 23937 | GIR_AddImm8, /*InsnID*/88, /*Imm*/31, |
| 23938 | GIR_ConstrainSelectedInstOperands, /*InsnID*/88, |
| 23939 | GIR_BuildMI, /*InsnID*/87, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23940 | GIR_AddTempRegister, /*InsnID*/87, /*TempRegID*/86, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23941 | GIR_AddSimpleTempRegister, /*InsnID*/87, /*TempRegID*/87, |
| 23942 | GIR_AddSimpleTempRegister, /*InsnID*/87, /*TempRegID*/88, |
| 23943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/87, |
| 23944 | GIR_BuildMI, /*InsnID*/86, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 23945 | GIR_AddTempRegister, /*InsnID*/86, /*TempRegID*/85, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23946 | GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/86, |
| 23947 | GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/90, |
| 23948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/86, |
| 23949 | GIR_BuildMI, /*InsnID*/85, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23950 | GIR_AddTempRegister, /*InsnID*/85, /*TempRegID*/84, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23951 | GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/85, |
| 23952 | GIR_AddImm8, /*InsnID*/85, /*Imm*/2, |
| 23953 | GIR_AddImm8, /*InsnID*/85, /*Imm*/0, |
| 23954 | GIR_AddImm8, /*InsnID*/85, /*Imm*/29, |
| 23955 | GIR_ConstrainSelectedInstOperands, /*InsnID*/85, |
| 23956 | GIR_BuildMI, /*InsnID*/84, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23957 | GIR_AddTempRegister, /*InsnID*/84, /*TempRegID*/83, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23958 | GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/84, |
| 23959 | GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/94, |
| 23960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/84, |
| 23961 | GIR_BuildMI, /*InsnID*/83, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23962 | GIR_AddTempRegister, /*InsnID*/83, /*TempRegID*/82, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23963 | GIR_AddImm, /*InsnID*/83, /*Imm*/GIMT_Encode8(13107), |
| 23964 | GIR_ConstrainSelectedInstOperands, /*InsnID*/83, |
| 23965 | GIR_BuildMI, /*InsnID*/82, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23966 | GIR_AddTempRegister, /*InsnID*/82, /*TempRegID*/81, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23967 | GIR_AddSimpleTempRegister, /*InsnID*/82, /*TempRegID*/82, |
| 23968 | GIR_AddImm, /*InsnID*/82, /*Imm*/GIMT_Encode8(13107), |
| 23969 | GIR_ConstrainSelectedInstOperands, /*InsnID*/82, |
| 23970 | GIR_BuildMI, /*InsnID*/81, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23971 | GIR_AddTempRegister, /*InsnID*/81, /*TempRegID*/80, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23972 | GIR_AddImm, /*InsnID*/81, /*Imm*/GIMT_Encode8(43690), |
| 23973 | GIR_ConstrainSelectedInstOperands, /*InsnID*/81, |
| 23974 | GIR_BuildMI, /*InsnID*/80, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23975 | GIR_AddTempRegister, /*InsnID*/80, /*TempRegID*/79, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23976 | GIR_AddSimpleTempRegister, /*InsnID*/80, /*TempRegID*/80, |
| 23977 | GIR_AddImm, /*InsnID*/80, /*Imm*/GIMT_Encode8(43690), |
| 23978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/80, |
| 23979 | GIR_BuildMI, /*InsnID*/79, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 23980 | GIR_AddTempRegister, /*InsnID*/79, /*TempRegID*/78, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23981 | GIR_Copy, /*NewInsnID*/79, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 23982 | GIR_AddImm8, /*InsnID*/79, /*Imm*/1, |
| 23983 | GIR_AddImm8, /*InsnID*/79, /*Imm*/0, |
| 23984 | GIR_AddImm8, /*InsnID*/79, /*Imm*/30, |
| 23985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/79, |
| 23986 | GIR_BuildMI, /*InsnID*/78, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 23987 | GIR_AddTempRegister, /*InsnID*/78, /*TempRegID*/77, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23988 | GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/78, |
| 23989 | GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/79, |
| 23990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/78, |
| 23991 | GIR_BuildMI, /*InsnID*/77, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 23992 | GIR_AddTempRegister, /*InsnID*/77, /*TempRegID*/76, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23993 | GIR_AddImm, /*InsnID*/77, /*Imm*/GIMT_Encode8(21845), |
| 23994 | GIR_ConstrainSelectedInstOperands, /*InsnID*/77, |
| 23995 | GIR_BuildMI, /*InsnID*/76, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 23996 | GIR_AddTempRegister, /*InsnID*/76, /*TempRegID*/75, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 23997 | GIR_AddSimpleTempRegister, /*InsnID*/76, /*TempRegID*/76, |
| 23998 | GIR_AddImm, /*InsnID*/76, /*Imm*/GIMT_Encode8(21845), |
| 23999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/76, |
| 24000 | GIR_BuildMI, /*InsnID*/75, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24001 | GIR_AddTempRegister, /*InsnID*/75, /*TempRegID*/74, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24002 | GIR_Copy, /*NewInsnID*/75, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24003 | GIR_AddImm8, /*InsnID*/75, /*Imm*/31, |
| 24004 | GIR_AddImm8, /*InsnID*/75, /*Imm*/1, |
| 24005 | GIR_AddImm8, /*InsnID*/75, /*Imm*/31, |
| 24006 | GIR_ConstrainSelectedInstOperands, /*InsnID*/75, |
| 24007 | GIR_BuildMI, /*InsnID*/74, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24008 | GIR_AddTempRegister, /*InsnID*/74, /*TempRegID*/73, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24009 | GIR_AddSimpleTempRegister, /*InsnID*/74, /*TempRegID*/74, |
| 24010 | GIR_AddSimpleTempRegister, /*InsnID*/74, /*TempRegID*/75, |
| 24011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/74, |
| 24012 | GIR_BuildMI, /*InsnID*/73, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24013 | GIR_AddTempRegister, /*InsnID*/73, /*TempRegID*/72, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24014 | GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/73, |
| 24015 | GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/77, |
| 24016 | GIR_ConstrainSelectedInstOperands, /*InsnID*/73, |
| 24017 | GIR_BuildMI, /*InsnID*/72, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24018 | GIR_AddTempRegister, /*InsnID*/72, /*TempRegID*/71, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24019 | GIR_AddSimpleTempRegister, /*InsnID*/72, /*TempRegID*/72, |
| 24020 | GIR_AddImm8, /*InsnID*/72, /*Imm*/30, |
| 24021 | GIR_AddImm8, /*InsnID*/72, /*Imm*/2, |
| 24022 | GIR_AddImm8, /*InsnID*/72, /*Imm*/31, |
| 24023 | GIR_ConstrainSelectedInstOperands, /*InsnID*/72, |
| 24024 | GIR_BuildMI, /*InsnID*/71, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24025 | GIR_AddTempRegister, /*InsnID*/71, /*TempRegID*/70, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24026 | GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/71, |
| 24027 | GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/81, |
| 24028 | GIR_ConstrainSelectedInstOperands, /*InsnID*/71, |
| 24029 | GIR_BuildMI, /*InsnID*/70, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24030 | GIR_AddTempRegister, /*InsnID*/70, /*TempRegID*/69, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24031 | GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/70, |
| 24032 | GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/83, |
| 24033 | GIR_ConstrainSelectedInstOperands, /*InsnID*/70, |
| 24034 | GIR_BuildMI, /*InsnID*/69, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24035 | GIR_AddTempRegister, /*InsnID*/69, /*TempRegID*/68, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24036 | GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/69, |
| 24037 | GIR_AddImm8, /*InsnID*/69, /*Imm*/28, |
| 24038 | GIR_AddImm8, /*InsnID*/69, /*Imm*/4, |
| 24039 | GIR_AddImm8, /*InsnID*/69, /*Imm*/31, |
| 24040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/69, |
| 24041 | GIR_BuildMI, /*InsnID*/68, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24042 | GIR_AddTempRegister, /*InsnID*/68, /*TempRegID*/67, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24043 | GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/68, |
| 24044 | GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/96, |
| 24045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/68, |
| 24046 | GIR_BuildMI, /*InsnID*/67, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24047 | GIR_AddTempRegister, /*InsnID*/67, /*TempRegID*/66, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24048 | GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/67, |
| 24049 | GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/98, |
| 24050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/67, |
| 24051 | GIR_BuildMI, /*InsnID*/66, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24052 | GIR_AddTempRegister, /*InsnID*/66, /*TempRegID*/65, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24053 | GIR_AddImm, /*InsnID*/66, /*Imm*/GIMT_Encode8(61680), |
| 24054 | GIR_ConstrainSelectedInstOperands, /*InsnID*/66, |
| 24055 | GIR_BuildMI, /*InsnID*/65, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24056 | GIR_AddTempRegister, /*InsnID*/65, /*TempRegID*/64, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24057 | GIR_AddSimpleTempRegister, /*InsnID*/65, /*TempRegID*/65, |
| 24058 | GIR_AddImm, /*InsnID*/65, /*Imm*/GIMT_Encode8(61680), |
| 24059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/65, |
| 24060 | GIR_BuildMI, /*InsnID*/64, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24061 | GIR_AddTempRegister, /*InsnID*/64, /*TempRegID*/63, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24062 | GIR_AddImm, /*InsnID*/64, /*Imm*/GIMT_Encode8(52428), |
| 24063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/64, |
| 24064 | GIR_BuildMI, /*InsnID*/63, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24065 | GIR_AddTempRegister, /*InsnID*/63, /*TempRegID*/62, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24066 | GIR_AddSimpleTempRegister, /*InsnID*/63, /*TempRegID*/63, |
| 24067 | GIR_AddImm, /*InsnID*/63, /*Imm*/GIMT_Encode8(52428), |
| 24068 | GIR_ConstrainSelectedInstOperands, /*InsnID*/63, |
| 24069 | GIR_BuildMI, /*InsnID*/62, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24070 | GIR_AddTempRegister, /*InsnID*/62, /*TempRegID*/61, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24071 | GIR_AddImm, /*InsnID*/62, /*Imm*/GIMT_Encode8(43690), |
| 24072 | GIR_ConstrainSelectedInstOperands, /*InsnID*/62, |
| 24073 | GIR_BuildMI, /*InsnID*/61, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24074 | GIR_AddTempRegister, /*InsnID*/61, /*TempRegID*/60, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24075 | GIR_AddSimpleTempRegister, /*InsnID*/61, /*TempRegID*/61, |
| 24076 | GIR_AddImm, /*InsnID*/61, /*Imm*/GIMT_Encode8(43690), |
| 24077 | GIR_ConstrainSelectedInstOperands, /*InsnID*/61, |
| 24078 | GIR_BuildMI, /*InsnID*/60, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24079 | GIR_AddTempRegister, /*InsnID*/60, /*TempRegID*/59, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24080 | GIR_Copy, /*NewInsnID*/60, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24081 | GIR_AddImm8, /*InsnID*/60, /*Imm*/1, |
| 24082 | GIR_AddImm8, /*InsnID*/60, /*Imm*/0, |
| 24083 | GIR_AddImm8, /*InsnID*/60, /*Imm*/30, |
| 24084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/60, |
| 24085 | GIR_BuildMI, /*InsnID*/59, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24086 | GIR_AddTempRegister, /*InsnID*/59, /*TempRegID*/58, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24087 | GIR_AddSimpleTempRegister, /*InsnID*/59, /*TempRegID*/59, |
| 24088 | GIR_AddSimpleTempRegister, /*InsnID*/59, /*TempRegID*/60, |
| 24089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/59, |
| 24090 | GIR_BuildMI, /*InsnID*/58, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24091 | GIR_AddTempRegister, /*InsnID*/58, /*TempRegID*/57, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24092 | GIR_AddImm, /*InsnID*/58, /*Imm*/GIMT_Encode8(21845), |
| 24093 | GIR_ConstrainSelectedInstOperands, /*InsnID*/58, |
| 24094 | GIR_BuildMI, /*InsnID*/57, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24095 | GIR_AddTempRegister, /*InsnID*/57, /*TempRegID*/56, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24096 | GIR_AddSimpleTempRegister, /*InsnID*/57, /*TempRegID*/57, |
| 24097 | GIR_AddImm, /*InsnID*/57, /*Imm*/GIMT_Encode8(21845), |
| 24098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/57, |
| 24099 | GIR_BuildMI, /*InsnID*/56, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24100 | GIR_AddTempRegister, /*InsnID*/56, /*TempRegID*/55, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24101 | GIR_Copy, /*NewInsnID*/56, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24102 | GIR_AddImm8, /*InsnID*/56, /*Imm*/31, |
| 24103 | GIR_AddImm8, /*InsnID*/56, /*Imm*/1, |
| 24104 | GIR_AddImm8, /*InsnID*/56, /*Imm*/31, |
| 24105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/56, |
| 24106 | GIR_BuildMI, /*InsnID*/55, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24107 | GIR_AddTempRegister, /*InsnID*/55, /*TempRegID*/54, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24108 | GIR_AddSimpleTempRegister, /*InsnID*/55, /*TempRegID*/55, |
| 24109 | GIR_AddSimpleTempRegister, /*InsnID*/55, /*TempRegID*/56, |
| 24110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/55, |
| 24111 | GIR_BuildMI, /*InsnID*/54, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24112 | GIR_AddTempRegister, /*InsnID*/54, /*TempRegID*/53, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24113 | GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/54, |
| 24114 | GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/58, |
| 24115 | GIR_ConstrainSelectedInstOperands, /*InsnID*/54, |
| 24116 | GIR_BuildMI, /*InsnID*/53, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24117 | GIR_AddTempRegister, /*InsnID*/53, /*TempRegID*/52, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24118 | GIR_AddSimpleTempRegister, /*InsnID*/53, /*TempRegID*/53, |
| 24119 | GIR_AddImm8, /*InsnID*/53, /*Imm*/2, |
| 24120 | GIR_AddImm8, /*InsnID*/53, /*Imm*/0, |
| 24121 | GIR_AddImm8, /*InsnID*/53, /*Imm*/29, |
| 24122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/53, |
| 24123 | GIR_BuildMI, /*InsnID*/52, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24124 | GIR_AddTempRegister, /*InsnID*/52, /*TempRegID*/51, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24125 | GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/52, |
| 24126 | GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/62, |
| 24127 | GIR_ConstrainSelectedInstOperands, /*InsnID*/52, |
| 24128 | GIR_BuildMI, /*InsnID*/51, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24129 | GIR_AddTempRegister, /*InsnID*/51, /*TempRegID*/50, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24130 | GIR_AddImm, /*InsnID*/51, /*Imm*/GIMT_Encode8(13107), |
| 24131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/51, |
| 24132 | GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24133 | GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24134 | GIR_AddSimpleTempRegister, /*InsnID*/50, /*TempRegID*/50, |
| 24135 | GIR_AddImm, /*InsnID*/50, /*Imm*/GIMT_Encode8(13107), |
| 24136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/50, |
| 24137 | GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24138 | GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24139 | GIR_AddImm, /*InsnID*/49, /*Imm*/GIMT_Encode8(43690), |
| 24140 | GIR_ConstrainSelectedInstOperands, /*InsnID*/49, |
| 24141 | GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24142 | GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24143 | GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48, |
| 24144 | GIR_AddImm, /*InsnID*/48, /*Imm*/GIMT_Encode8(43690), |
| 24145 | GIR_ConstrainSelectedInstOperands, /*InsnID*/48, |
| 24146 | GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24147 | GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24148 | GIR_Copy, /*NewInsnID*/47, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24149 | GIR_AddImm8, /*InsnID*/47, /*Imm*/1, |
| 24150 | GIR_AddImm8, /*InsnID*/47, /*Imm*/0, |
| 24151 | GIR_AddImm8, /*InsnID*/47, /*Imm*/30, |
| 24152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/47, |
| 24153 | GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24154 | GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24155 | GIR_AddSimpleTempRegister, /*InsnID*/46, /*TempRegID*/46, |
| 24156 | GIR_AddSimpleTempRegister, /*InsnID*/46, /*TempRegID*/47, |
| 24157 | GIR_ConstrainSelectedInstOperands, /*InsnID*/46, |
| 24158 | GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24159 | GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24160 | GIR_AddImm, /*InsnID*/45, /*Imm*/GIMT_Encode8(21845), |
| 24161 | GIR_ConstrainSelectedInstOperands, /*InsnID*/45, |
| 24162 | GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24163 | GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24164 | GIR_AddSimpleTempRegister, /*InsnID*/44, /*TempRegID*/44, |
| 24165 | GIR_AddImm, /*InsnID*/44, /*Imm*/GIMT_Encode8(21845), |
| 24166 | GIR_ConstrainSelectedInstOperands, /*InsnID*/44, |
| 24167 | GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24168 | GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24169 | GIR_Copy, /*NewInsnID*/43, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24170 | GIR_AddImm8, /*InsnID*/43, /*Imm*/31, |
| 24171 | GIR_AddImm8, /*InsnID*/43, /*Imm*/1, |
| 24172 | GIR_AddImm8, /*InsnID*/43, /*Imm*/31, |
| 24173 | GIR_ConstrainSelectedInstOperands, /*InsnID*/43, |
| 24174 | GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24175 | GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24176 | GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/42, |
| 24177 | GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/43, |
| 24178 | GIR_ConstrainSelectedInstOperands, /*InsnID*/42, |
| 24179 | GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24180 | GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24181 | GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/41, |
| 24182 | GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/45, |
| 24183 | GIR_ConstrainSelectedInstOperands, /*InsnID*/41, |
| 24184 | GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24185 | GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24186 | GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40, |
| 24187 | GIR_AddImm8, /*InsnID*/40, /*Imm*/30, |
| 24188 | GIR_AddImm8, /*InsnID*/40, /*Imm*/2, |
| 24189 | GIR_AddImm8, /*InsnID*/40, /*Imm*/31, |
| 24190 | GIR_ConstrainSelectedInstOperands, /*InsnID*/40, |
| 24191 | GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24192 | GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24193 | GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39, |
| 24194 | GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/49, |
| 24195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/39, |
| 24196 | GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24197 | GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24198 | GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38, |
| 24199 | GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/51, |
| 24200 | GIR_ConstrainSelectedInstOperands, /*InsnID*/38, |
| 24201 | GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24202 | GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24203 | GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37, |
| 24204 | GIR_AddImm8, /*InsnID*/37, /*Imm*/4, |
| 24205 | GIR_AddImm8, /*InsnID*/37, /*Imm*/0, |
| 24206 | GIR_AddImm8, /*InsnID*/37, /*Imm*/27, |
| 24207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/37, |
| 24208 | GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24209 | GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24210 | GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36, |
| 24211 | GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/64, |
| 24212 | GIR_ConstrainSelectedInstOperands, /*InsnID*/36, |
| 24213 | GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24214 | GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24215 | GIR_AddImm, /*InsnID*/35, /*Imm*/GIMT_Encode8(3855), |
| 24216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/35, |
| 24217 | GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24218 | GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24219 | GIR_AddSimpleTempRegister, /*InsnID*/34, /*TempRegID*/34, |
| 24220 | GIR_AddImm, /*InsnID*/34, /*Imm*/GIMT_Encode8(3855), |
| 24221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/34, |
| 24222 | GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24223 | GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24224 | GIR_AddImm, /*InsnID*/33, /*Imm*/GIMT_Encode8(52428), |
| 24225 | GIR_ConstrainSelectedInstOperands, /*InsnID*/33, |
| 24226 | GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24227 | GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24228 | GIR_AddSimpleTempRegister, /*InsnID*/32, /*TempRegID*/32, |
| 24229 | GIR_AddImm, /*InsnID*/32, /*Imm*/GIMT_Encode8(52428), |
| 24230 | GIR_ConstrainSelectedInstOperands, /*InsnID*/32, |
| 24231 | GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24232 | GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24233 | GIR_AddImm, /*InsnID*/31, /*Imm*/GIMT_Encode8(43690), |
| 24234 | GIR_ConstrainSelectedInstOperands, /*InsnID*/31, |
| 24235 | GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24236 | GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24237 | GIR_AddSimpleTempRegister, /*InsnID*/30, /*TempRegID*/30, |
| 24238 | GIR_AddImm, /*InsnID*/30, /*Imm*/GIMT_Encode8(43690), |
| 24239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/30, |
| 24240 | GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24241 | GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24242 | GIR_Copy, /*NewInsnID*/29, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24243 | GIR_AddImm8, /*InsnID*/29, /*Imm*/1, |
| 24244 | GIR_AddImm8, /*InsnID*/29, /*Imm*/0, |
| 24245 | GIR_AddImm8, /*InsnID*/29, /*Imm*/30, |
| 24246 | GIR_ConstrainSelectedInstOperands, /*InsnID*/29, |
| 24247 | GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24248 | GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24249 | GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28, |
| 24250 | GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/29, |
| 24251 | GIR_ConstrainSelectedInstOperands, /*InsnID*/28, |
| 24252 | GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24253 | GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24254 | GIR_AddImm, /*InsnID*/27, /*Imm*/GIMT_Encode8(21845), |
| 24255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/27, |
| 24256 | GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24257 | GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24258 | GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26, |
| 24259 | GIR_AddImm, /*InsnID*/26, /*Imm*/GIMT_Encode8(21845), |
| 24260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/26, |
| 24261 | GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24262 | GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24263 | GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24264 | GIR_AddImm8, /*InsnID*/25, /*Imm*/31, |
| 24265 | GIR_AddImm8, /*InsnID*/25, /*Imm*/1, |
| 24266 | GIR_AddImm8, /*InsnID*/25, /*Imm*/31, |
| 24267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/25, |
| 24268 | GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24269 | GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24270 | GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24, |
| 24271 | GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/25, |
| 24272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/24, |
| 24273 | GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24274 | GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24275 | GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23, |
| 24276 | GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/27, |
| 24277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/23, |
| 24278 | GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24279 | GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24280 | GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22, |
| 24281 | GIR_AddImm8, /*InsnID*/22, /*Imm*/2, |
| 24282 | GIR_AddImm8, /*InsnID*/22, /*Imm*/0, |
| 24283 | GIR_AddImm8, /*InsnID*/22, /*Imm*/29, |
| 24284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/22, |
| 24285 | GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24286 | GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24287 | GIR_AddSimpleTempRegister, /*InsnID*/21, /*TempRegID*/21, |
| 24288 | GIR_AddSimpleTempRegister, /*InsnID*/21, /*TempRegID*/31, |
| 24289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/21, |
| 24290 | GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24291 | GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24292 | GIR_AddImm, /*InsnID*/20, /*Imm*/GIMT_Encode8(13107), |
| 24293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/20, |
| 24294 | GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24295 | GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24296 | GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19, |
| 24297 | GIR_AddImm, /*InsnID*/19, /*Imm*/GIMT_Encode8(13107), |
| 24298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/19, |
| 24299 | GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24300 | GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24301 | GIR_AddImm, /*InsnID*/18, /*Imm*/GIMT_Encode8(43690), |
| 24302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/18, |
| 24303 | GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24304 | GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24305 | GIR_AddSimpleTempRegister, /*InsnID*/17, /*TempRegID*/17, |
| 24306 | GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(43690), |
| 24307 | GIR_ConstrainSelectedInstOperands, /*InsnID*/17, |
| 24308 | GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24309 | GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24310 | GIR_Copy, /*NewInsnID*/16, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24311 | GIR_AddImm8, /*InsnID*/16, /*Imm*/1, |
| 24312 | GIR_AddImm8, /*InsnID*/16, /*Imm*/0, |
| 24313 | GIR_AddImm8, /*InsnID*/16, /*Imm*/30, |
| 24314 | GIR_ConstrainSelectedInstOperands, /*InsnID*/16, |
| 24315 | GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24316 | GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24317 | GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15, |
| 24318 | GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/16, |
| 24319 | GIR_ConstrainSelectedInstOperands, /*InsnID*/15, |
| 24320 | GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24321 | GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24322 | GIR_AddImm, /*InsnID*/14, /*Imm*/GIMT_Encode8(21845), |
| 24323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/14, |
| 24324 | GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24325 | GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24326 | GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13, |
| 24327 | GIR_AddImm, /*InsnID*/13, /*Imm*/GIMT_Encode8(21845), |
| 24328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/13, |
| 24329 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24330 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24331 | GIR_Copy, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24332 | GIR_AddImm8, /*InsnID*/12, /*Imm*/31, |
| 24333 | GIR_AddImm8, /*InsnID*/12, /*Imm*/1, |
| 24334 | GIR_AddImm8, /*InsnID*/12, /*Imm*/31, |
| 24335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/12, |
| 24336 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24337 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24338 | GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11, |
| 24339 | GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/12, |
| 24340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 24341 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24342 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24343 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 24344 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/14, |
| 24345 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 24346 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24347 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24348 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 24349 | GIR_AddImm8, /*InsnID*/9, /*Imm*/30, |
| 24350 | GIR_AddImm8, /*InsnID*/9, /*Imm*/2, |
| 24351 | GIR_AddImm8, /*InsnID*/9, /*Imm*/31, |
| 24352 | GIR_ConstrainSelectedInstOperands, /*InsnID*/9, |
| 24353 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24354 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24355 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 24356 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/18, |
| 24357 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 24358 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24359 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24360 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 24361 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/20, |
| 24362 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 24363 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24364 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24365 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 24366 | GIR_AddImm8, /*InsnID*/6, /*Imm*/28, |
| 24367 | GIR_AddImm8, /*InsnID*/6, /*Imm*/4, |
| 24368 | GIR_AddImm8, /*InsnID*/6, /*Imm*/31, |
| 24369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 24370 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24371 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24372 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 24373 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/33, |
| 24374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 24375 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24376 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24377 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 24378 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/35, |
| 24379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 24380 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24381 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24382 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 24383 | GIR_AddImm8, /*InsnID*/3, /*Imm*/24, |
| 24384 | GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 24385 | GIR_AddImm8, /*InsnID*/3, /*Imm*/31, |
| 24386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 24387 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 24388 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24389 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 24390 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/66, |
| 24391 | GIR_AddImm8, /*InsnID*/2, /*Imm*/8, |
| 24392 | GIR_AddImm8, /*InsnID*/2, /*Imm*/8, |
| 24393 | GIR_AddImm8, /*InsnID*/2, /*Imm*/15, |
| 24394 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 24395 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 24396 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24397 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 24398 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, |
| 24399 | GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 24400 | GIR_AddImm8, /*InsnID*/1, /*Imm*/24, |
| 24401 | GIR_AddImm8, /*InsnID*/1, /*Imm*/31, |
| 24402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLDICL_32), |
| 24404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 24405 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/32, |
| 24408 | GIR_RootConstrainSelectedInstOperands, |
| 24409 | // GIR_Coverage, 4832, |
| 24410 | GIR_EraseRootFromParent_Done, |
| 24411 | // Label 1748: @63290 |
| 24412 | GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(68415), // Rule ID 4833 // |
| 24413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_In32BitMode), |
| 24414 | // (bitreverse:{ *:[i32] } i32:{ *:[i32] }:$A) => (RLWIMI:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 24:{ *:[i32] }, 0:{ *:[i32] }, 31:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 8:{ *:[i32] }, 15:{ *:[i32] }), (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 28:{ *:[i32] }, 4:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 30:{ *:[i32] }, 2:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } (OR:{ *:[i32] } (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 31:{ *:[i32] }, 1:{ *:[i32] }, 31:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] })), (AND:{ *:[i32] } (RLWINM:{ *:[i32] } ?:{ *:[i32] }:$A, 1:{ *:[i32] }, 0:{ *:[i32] }, 30:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }))), 2:{ *:[i32] }, 0:{ *:[i32] }, 29:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }))), 4:{ *:[i32] }, 0:{ *:[i32] }, 27:{ *:[i32] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }))), 8:{ *:[i32] }, 24:{ *:[i32] }, 31:{ *:[i32] }) |
| 24415 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24416 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 24417 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 24418 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 24419 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 24420 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 24421 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 24422 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 24423 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 24424 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 24425 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 24426 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 24427 | GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s32, |
| 24428 | GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s32, |
| 24429 | GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s32, |
| 24430 | GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s32, |
| 24431 | GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s32, |
| 24432 | GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s32, |
| 24433 | GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_s32, |
| 24434 | GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s32, |
| 24435 | GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s32, |
| 24436 | GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s32, |
| 24437 | GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s32, |
| 24438 | GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s32, |
| 24439 | GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_s32, |
| 24440 | GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_s32, |
| 24441 | GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_s32, |
| 24442 | GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s32, |
| 24443 | GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s32, |
| 24444 | GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s32, |
| 24445 | GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s32, |
| 24446 | GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s32, |
| 24447 | GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s32, |
| 24448 | GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s32, |
| 24449 | GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s32, |
| 24450 | GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s32, |
| 24451 | GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_s32, |
| 24452 | GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s32, |
| 24453 | GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s32, |
| 24454 | GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_s32, |
| 24455 | GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_s32, |
| 24456 | GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_s32, |
| 24457 | GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s32, |
| 24458 | GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s32, |
| 24459 | GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s32, |
| 24460 | GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s32, |
| 24461 | GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s32, |
| 24462 | GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_s32, |
| 24463 | GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_s32, |
| 24464 | GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_s32, |
| 24465 | GIR_MakeTempReg, /*TempRegID*/50, /*TypeID*/GILLT_s32, |
| 24466 | GIR_MakeTempReg, /*TempRegID*/51, /*TypeID*/GILLT_s32, |
| 24467 | GIR_MakeTempReg, /*TempRegID*/52, /*TypeID*/GILLT_s32, |
| 24468 | GIR_MakeTempReg, /*TempRegID*/53, /*TypeID*/GILLT_s32, |
| 24469 | GIR_MakeTempReg, /*TempRegID*/54, /*TypeID*/GILLT_s32, |
| 24470 | GIR_MakeTempReg, /*TempRegID*/55, /*TypeID*/GILLT_s32, |
| 24471 | GIR_MakeTempReg, /*TempRegID*/56, /*TypeID*/GILLT_s32, |
| 24472 | GIR_MakeTempReg, /*TempRegID*/57, /*TypeID*/GILLT_s32, |
| 24473 | GIR_MakeTempReg, /*TempRegID*/58, /*TypeID*/GILLT_s32, |
| 24474 | GIR_MakeTempReg, /*TempRegID*/59, /*TypeID*/GILLT_s32, |
| 24475 | GIR_MakeTempReg, /*TempRegID*/60, /*TypeID*/GILLT_s32, |
| 24476 | GIR_MakeTempReg, /*TempRegID*/61, /*TypeID*/GILLT_s32, |
| 24477 | GIR_MakeTempReg, /*TempRegID*/62, /*TypeID*/GILLT_s32, |
| 24478 | GIR_MakeTempReg, /*TempRegID*/63, /*TypeID*/GILLT_s32, |
| 24479 | GIR_MakeTempReg, /*TempRegID*/64, /*TypeID*/GILLT_s32, |
| 24480 | GIR_MakeTempReg, /*TempRegID*/65, /*TypeID*/GILLT_s32, |
| 24481 | GIR_MakeTempReg, /*TempRegID*/66, /*TypeID*/GILLT_s32, |
| 24482 | GIR_MakeTempReg, /*TempRegID*/67, /*TypeID*/GILLT_s32, |
| 24483 | GIR_MakeTempReg, /*TempRegID*/68, /*TypeID*/GILLT_s32, |
| 24484 | GIR_MakeTempReg, /*TempRegID*/69, /*TypeID*/GILLT_s32, |
| 24485 | GIR_MakeTempReg, /*TempRegID*/70, /*TypeID*/GILLT_s32, |
| 24486 | GIR_MakeTempReg, /*TempRegID*/71, /*TypeID*/GILLT_s32, |
| 24487 | GIR_MakeTempReg, /*TempRegID*/72, /*TypeID*/GILLT_s32, |
| 24488 | GIR_MakeTempReg, /*TempRegID*/73, /*TypeID*/GILLT_s32, |
| 24489 | GIR_MakeTempReg, /*TempRegID*/74, /*TypeID*/GILLT_s32, |
| 24490 | GIR_MakeTempReg, /*TempRegID*/75, /*TypeID*/GILLT_s32, |
| 24491 | GIR_MakeTempReg, /*TempRegID*/76, /*TypeID*/GILLT_s32, |
| 24492 | GIR_MakeTempReg, /*TempRegID*/77, /*TypeID*/GILLT_s32, |
| 24493 | GIR_MakeTempReg, /*TempRegID*/78, /*TypeID*/GILLT_s32, |
| 24494 | GIR_MakeTempReg, /*TempRegID*/79, /*TypeID*/GILLT_s32, |
| 24495 | GIR_MakeTempReg, /*TempRegID*/80, /*TypeID*/GILLT_s32, |
| 24496 | GIR_MakeTempReg, /*TempRegID*/81, /*TypeID*/GILLT_s32, |
| 24497 | GIR_MakeTempReg, /*TempRegID*/82, /*TypeID*/GILLT_s32, |
| 24498 | GIR_MakeTempReg, /*TempRegID*/83, /*TypeID*/GILLT_s32, |
| 24499 | GIR_MakeTempReg, /*TempRegID*/84, /*TypeID*/GILLT_s32, |
| 24500 | GIR_MakeTempReg, /*TempRegID*/85, /*TypeID*/GILLT_s32, |
| 24501 | GIR_MakeTempReg, /*TempRegID*/86, /*TypeID*/GILLT_s32, |
| 24502 | GIR_MakeTempReg, /*TempRegID*/87, /*TypeID*/GILLT_s32, |
| 24503 | GIR_MakeTempReg, /*TempRegID*/88, /*TypeID*/GILLT_s32, |
| 24504 | GIR_MakeTempReg, /*TempRegID*/89, /*TypeID*/GILLT_s32, |
| 24505 | GIR_MakeTempReg, /*TempRegID*/90, /*TypeID*/GILLT_s32, |
| 24506 | GIR_MakeTempReg, /*TempRegID*/91, /*TypeID*/GILLT_s32, |
| 24507 | GIR_MakeTempReg, /*TempRegID*/92, /*TypeID*/GILLT_s32, |
| 24508 | GIR_MakeTempReg, /*TempRegID*/93, /*TypeID*/GILLT_s32, |
| 24509 | GIR_MakeTempReg, /*TempRegID*/94, /*TypeID*/GILLT_s32, |
| 24510 | GIR_MakeTempReg, /*TempRegID*/95, /*TypeID*/GILLT_s32, |
| 24511 | GIR_MakeTempReg, /*TempRegID*/96, /*TypeID*/GILLT_s32, |
| 24512 | GIR_MakeTempReg, /*TempRegID*/97, /*TypeID*/GILLT_s32, |
| 24513 | GIR_MakeTempReg, /*TempRegID*/98, /*TypeID*/GILLT_s32, |
| 24514 | GIR_MakeTempReg, /*TempRegID*/99, /*TypeID*/GILLT_s32, |
| 24515 | GIR_MakeTempReg, /*TempRegID*/100, /*TypeID*/GILLT_s32, |
| 24516 | GIR_MakeTempReg, /*TempRegID*/101, /*TypeID*/GILLT_s32, |
| 24517 | GIR_MakeTempReg, /*TempRegID*/102, /*TypeID*/GILLT_s32, |
| 24518 | GIR_MakeTempReg, /*TempRegID*/103, /*TypeID*/GILLT_s32, |
| 24519 | GIR_MakeTempReg, /*TempRegID*/104, /*TypeID*/GILLT_s32, |
| 24520 | GIR_MakeTempReg, /*TempRegID*/105, /*TypeID*/GILLT_s32, |
| 24521 | GIR_MakeTempReg, /*TempRegID*/106, /*TypeID*/GILLT_s32, |
| 24522 | GIR_MakeTempReg, /*TempRegID*/107, /*TypeID*/GILLT_s32, |
| 24523 | GIR_MakeTempReg, /*TempRegID*/108, /*TypeID*/GILLT_s32, |
| 24524 | GIR_MakeTempReg, /*TempRegID*/109, /*TypeID*/GILLT_s32, |
| 24525 | GIR_MakeTempReg, /*TempRegID*/110, /*TypeID*/GILLT_s32, |
| 24526 | GIR_MakeTempReg, /*TempRegID*/111, /*TypeID*/GILLT_s32, |
| 24527 | GIR_MakeTempReg, /*TempRegID*/112, /*TypeID*/GILLT_s32, |
| 24528 | GIR_MakeTempReg, /*TempRegID*/113, /*TypeID*/GILLT_s32, |
| 24529 | GIR_MakeTempReg, /*TempRegID*/114, /*TypeID*/GILLT_s32, |
| 24530 | GIR_MakeTempReg, /*TempRegID*/115, /*TypeID*/GILLT_s32, |
| 24531 | GIR_MakeTempReg, /*TempRegID*/116, /*TypeID*/GILLT_s32, |
| 24532 | GIR_MakeTempReg, /*TempRegID*/117, /*TypeID*/GILLT_s32, |
| 24533 | GIR_MakeTempReg, /*TempRegID*/118, /*TypeID*/GILLT_s32, |
| 24534 | GIR_MakeTempReg, /*TempRegID*/119, /*TypeID*/GILLT_s32, |
| 24535 | GIR_MakeTempReg, /*TempRegID*/120, /*TypeID*/GILLT_s32, |
| 24536 | GIR_MakeTempReg, /*TempRegID*/121, /*TypeID*/GILLT_s32, |
| 24537 | GIR_MakeTempReg, /*TempRegID*/122, /*TypeID*/GILLT_s32, |
| 24538 | GIR_MakeTempReg, /*TempRegID*/123, /*TypeID*/GILLT_s32, |
| 24539 | GIR_MakeTempReg, /*TempRegID*/124, /*TypeID*/GILLT_s32, |
| 24540 | GIR_MakeTempReg, /*TempRegID*/125, /*TypeID*/GILLT_s32, |
| 24541 | GIR_MakeTempReg, /*TempRegID*/126, /*TypeID*/GILLT_s32, |
| 24542 | GIR_MakeTempReg, /*TempRegID*/127, /*TypeID*/GILLT_s32, |
| 24543 | GIR_MakeTempReg, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24544 | GIR_MakeTempReg, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24545 | GIR_MakeTempReg, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24546 | GIR_MakeTempReg, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24547 | GIR_MakeTempReg, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24548 | GIR_MakeTempReg, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24549 | GIR_MakeTempReg, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24550 | GIR_MakeTempReg, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24551 | GIR_MakeTempReg, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24552 | GIR_MakeTempReg, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24553 | GIR_MakeTempReg, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24554 | GIR_MakeTempReg, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24555 | GIR_MakeTempReg, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24556 | GIR_MakeTempReg, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24557 | GIR_MakeTempReg, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24558 | GIR_MakeTempReg, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24559 | GIR_MakeTempReg, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24560 | GIR_MakeTempReg, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24561 | GIR_MakeTempReg, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24562 | GIR_MakeTempReg, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24563 | GIR_MakeTempReg, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24564 | GIR_MakeTempReg, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24565 | GIR_MakeTempReg, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24566 | GIR_MakeTempReg, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24567 | GIR_MakeTempReg, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24568 | GIR_MakeTempReg, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24569 | GIR_MakeTempReg, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24570 | GIR_MakeTempReg, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24571 | GIR_MakeTempReg, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24572 | GIR_MakeTempReg, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24573 | GIR_MakeTempReg, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24574 | GIR_MakeTempReg, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24575 | GIR_MakeTempReg, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24576 | GIR_MakeTempReg, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24577 | GIR_MakeTempReg, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24578 | GIR_MakeTempReg, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24579 | GIR_MakeTempReg, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24580 | GIR_MakeTempReg, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24581 | GIR_MakeTempReg, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24582 | GIR_MakeTempReg, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24583 | GIR_MakeTempReg, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24584 | GIR_MakeTempReg, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24585 | GIR_MakeTempReg, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24586 | GIR_MakeTempReg, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24587 | GIR_MakeTempReg, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24588 | GIR_MakeTempReg, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24589 | GIR_MakeTempReg, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24590 | GIR_MakeTempReg, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24591 | GIR_MakeTempReg, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24592 | GIR_MakeTempReg, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24593 | GIR_MakeTempReg, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24594 | GIR_MakeTempReg, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24595 | GIR_MakeTempReg, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24596 | GIR_MakeTempReg, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24597 | GIR_MakeTempReg, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24598 | GIR_MakeTempReg, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24599 | GIR_MakeTempReg, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24600 | GIR_MakeTempReg, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24601 | GIR_MakeTempReg, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24602 | GIR_MakeTempReg, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24603 | GIR_MakeTempReg, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24604 | GIR_MakeTempReg, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24605 | GIR_MakeTempReg, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 24606 | GIR_BuildMI, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24607 | GIR_AddTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24608 | GIR_AddImm, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 24609 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, |
| 24610 | GIR_BuildMI, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24611 | GIR_AddTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24612 | GIR_AddSimpleTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, |
| 24613 | GIR_AddImm, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 24614 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, |
| 24615 | GIR_BuildMI, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24616 | GIR_AddTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24617 | GIR_AddImm, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 24618 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, |
| 24619 | GIR_BuildMI, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24620 | GIR_AddTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24621 | GIR_AddSimpleTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, |
| 24622 | GIR_AddImm, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 24623 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, |
| 24624 | GIR_BuildMI, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24625 | GIR_AddTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24626 | GIR_AddImm, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24627 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, |
| 24628 | GIR_BuildMI, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24629 | GIR_AddTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24630 | GIR_AddSimpleTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, |
| 24631 | GIR_AddImm, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24632 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, |
| 24633 | GIR_BuildMI, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24634 | GIR_AddTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24635 | GIR_Copy, /*NewInsnID*//* 185(*/0xB9, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24636 | GIR_AddImm8, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/1, |
| 24637 | GIR_AddImm8, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/0, |
| 24638 | GIR_AddImm8, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/30, |
| 24639 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, |
| 24640 | GIR_BuildMI, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24641 | GIR_AddTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24642 | GIR_AddSimpleTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, |
| 24643 | GIR_AddSimpleTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, |
| 24644 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, |
| 24645 | GIR_BuildMI, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24646 | GIR_AddTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24647 | GIR_AddImm, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24648 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, |
| 24649 | GIR_BuildMI, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24650 | GIR_AddTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24651 | GIR_AddSimpleTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, |
| 24652 | GIR_AddImm, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24653 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, |
| 24654 | GIR_BuildMI, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24655 | GIR_AddTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24656 | GIR_Copy, /*NewInsnID*//* 181(*/0xB5, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24657 | GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/31, |
| 24658 | GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/1, |
| 24659 | GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/31, |
| 24660 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, |
| 24661 | GIR_BuildMI, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24662 | GIR_AddTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24663 | GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, |
| 24664 | GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, |
| 24665 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, |
| 24666 | GIR_BuildMI, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24667 | GIR_AddTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24668 | GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, |
| 24669 | GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, |
| 24670 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, |
| 24671 | GIR_BuildMI, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24672 | GIR_AddTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24673 | GIR_AddSimpleTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, |
| 24674 | GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/2, |
| 24675 | GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/0, |
| 24676 | GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/29, |
| 24677 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, |
| 24678 | GIR_BuildMI, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24679 | GIR_AddTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24680 | GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, |
| 24681 | GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, |
| 24682 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, |
| 24683 | GIR_BuildMI, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24684 | GIR_AddTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24685 | GIR_AddImm, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 24686 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, |
| 24687 | GIR_BuildMI, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24688 | GIR_AddTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24689 | GIR_AddSimpleTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, |
| 24690 | GIR_AddImm, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 24691 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, |
| 24692 | GIR_BuildMI, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24693 | GIR_AddTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24694 | GIR_AddImm, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24695 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, |
| 24696 | GIR_BuildMI, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24697 | GIR_AddTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24698 | GIR_AddSimpleTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, |
| 24699 | GIR_AddImm, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24700 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, |
| 24701 | GIR_BuildMI, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24702 | GIR_AddTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24703 | GIR_Copy, /*NewInsnID*//* 172(*/0xAC, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24704 | GIR_AddImm8, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/1, |
| 24705 | GIR_AddImm8, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/0, |
| 24706 | GIR_AddImm8, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/30, |
| 24707 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, |
| 24708 | GIR_BuildMI, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24709 | GIR_AddTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24710 | GIR_AddSimpleTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, |
| 24711 | GIR_AddSimpleTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, |
| 24712 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, |
| 24713 | GIR_BuildMI, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24714 | GIR_AddTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24715 | GIR_AddImm, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24716 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, |
| 24717 | GIR_BuildMI, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24718 | GIR_AddTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24719 | GIR_AddSimpleTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, |
| 24720 | GIR_AddImm, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24721 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, |
| 24722 | GIR_BuildMI, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24723 | GIR_AddTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24724 | GIR_Copy, /*NewInsnID*//* 168(*/0xA8, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24725 | GIR_AddImm8, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/31, |
| 24726 | GIR_AddImm8, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/1, |
| 24727 | GIR_AddImm8, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/31, |
| 24728 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, |
| 24729 | GIR_BuildMI, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24730 | GIR_AddTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24731 | GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, |
| 24732 | GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, |
| 24733 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, |
| 24734 | GIR_BuildMI, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24735 | GIR_AddTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24736 | GIR_AddSimpleTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, |
| 24737 | GIR_AddSimpleTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, |
| 24738 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, |
| 24739 | GIR_BuildMI, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24740 | GIR_AddTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24741 | GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, |
| 24742 | GIR_AddImm8, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/30, |
| 24743 | GIR_AddImm8, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/2, |
| 24744 | GIR_AddImm8, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/31, |
| 24745 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, |
| 24746 | GIR_BuildMI, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24747 | GIR_AddTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24748 | GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, |
| 24749 | GIR_AddSimpleTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, |
| 24750 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, |
| 24751 | GIR_BuildMI, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24752 | GIR_AddTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24753 | GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, |
| 24754 | GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, |
| 24755 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, |
| 24756 | GIR_BuildMI, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24757 | GIR_AddTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24758 | GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, |
| 24759 | GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/4, |
| 24760 | GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/0, |
| 24761 | GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/27, |
| 24762 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, |
| 24763 | GIR_BuildMI, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24764 | GIR_AddTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24765 | GIR_AddSimpleTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, |
| 24766 | GIR_AddSimpleTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, |
| 24767 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, |
| 24768 | GIR_BuildMI, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24769 | GIR_AddTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24770 | GIR_AddImm, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 24771 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, |
| 24772 | GIR_BuildMI, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24773 | GIR_AddTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24774 | GIR_AddSimpleTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, |
| 24775 | GIR_AddImm, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 24776 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, |
| 24777 | GIR_BuildMI, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24778 | GIR_AddTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24779 | GIR_AddImm, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 24780 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, |
| 24781 | GIR_BuildMI, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24782 | GIR_AddTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24783 | GIR_AddSimpleTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, |
| 24784 | GIR_AddImm, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 24785 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, |
| 24786 | GIR_BuildMI, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24787 | GIR_AddTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24788 | GIR_AddImm, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24789 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, |
| 24790 | GIR_BuildMI, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24791 | GIR_AddTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24792 | GIR_AddSimpleTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, |
| 24793 | GIR_AddImm, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24794 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, |
| 24795 | GIR_BuildMI, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24796 | GIR_AddTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24797 | GIR_Copy, /*NewInsnID*//* 154(*/0x9A, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24798 | GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/1, |
| 24799 | GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/0, |
| 24800 | GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/30, |
| 24801 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, |
| 24802 | GIR_BuildMI, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24803 | GIR_AddTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24804 | GIR_AddSimpleTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, |
| 24805 | GIR_AddSimpleTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, |
| 24806 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 153(*/0x99, 0x01/*)*/, |
| 24807 | GIR_BuildMI, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24808 | GIR_AddTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24809 | GIR_AddImm, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24810 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 152(*/0x98, 0x01/*)*/, |
| 24811 | GIR_BuildMI, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24812 | GIR_AddTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24813 | GIR_AddSimpleTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, |
| 24814 | GIR_AddImm, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24815 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 151(*/0x97, 0x01/*)*/, |
| 24816 | GIR_BuildMI, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24817 | GIR_AddTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24818 | GIR_Copy, /*NewInsnID*//* 150(*/0x96, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24819 | GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/31, |
| 24820 | GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/1, |
| 24821 | GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/31, |
| 24822 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 150(*/0x96, 0x01/*)*/, |
| 24823 | GIR_BuildMI, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24824 | GIR_AddTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24825 | GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, |
| 24826 | GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, |
| 24827 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 149(*/0x95, 0x01/*)*/, |
| 24828 | GIR_BuildMI, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24829 | GIR_AddTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24830 | GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, |
| 24831 | GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, |
| 24832 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 148(*/0x94, 0x01/*)*/, |
| 24833 | GIR_BuildMI, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24834 | GIR_AddTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24835 | GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, |
| 24836 | GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/2, |
| 24837 | GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/0, |
| 24838 | GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/29, |
| 24839 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 147(*/0x93, 0x01/*)*/, |
| 24840 | GIR_BuildMI, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24841 | GIR_AddTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24842 | GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, |
| 24843 | GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, |
| 24844 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 146(*/0x92, 0x01/*)*/, |
| 24845 | GIR_BuildMI, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24846 | GIR_AddTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24847 | GIR_AddImm, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 24848 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 145(*/0x91, 0x01/*)*/, |
| 24849 | GIR_BuildMI, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24850 | GIR_AddTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24851 | GIR_AddSimpleTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, |
| 24852 | GIR_AddImm, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 24853 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 144(*/0x90, 0x01/*)*/, |
| 24854 | GIR_BuildMI, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24855 | GIR_AddTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24856 | GIR_AddImm, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24857 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, |
| 24858 | GIR_BuildMI, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24859 | GIR_AddTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24860 | GIR_AddSimpleTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, |
| 24861 | GIR_AddImm, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 24862 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, |
| 24863 | GIR_BuildMI, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24864 | GIR_AddTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24865 | GIR_Copy, /*NewInsnID*//* 141(*/0x8D, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24866 | GIR_AddImm8, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Imm*/1, |
| 24867 | GIR_AddImm8, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Imm*/0, |
| 24868 | GIR_AddImm8, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Imm*/30, |
| 24869 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, |
| 24870 | GIR_BuildMI, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24871 | GIR_AddTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24872 | GIR_AddSimpleTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, |
| 24873 | GIR_AddSimpleTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, |
| 24874 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, |
| 24875 | GIR_BuildMI, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24876 | GIR_AddTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24877 | GIR_AddImm, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24878 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, |
| 24879 | GIR_BuildMI, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24880 | GIR_AddTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24881 | GIR_AddSimpleTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, |
| 24882 | GIR_AddImm, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 24883 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, |
| 24884 | GIR_BuildMI, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24885 | GIR_AddTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24886 | GIR_Copy, /*NewInsnID*//* 137(*/0x89, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24887 | GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/31, |
| 24888 | GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/1, |
| 24889 | GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/31, |
| 24890 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 137(*/0x89, 0x01/*)*/, |
| 24891 | GIR_BuildMI, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24892 | GIR_AddTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24893 | GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, |
| 24894 | GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, |
| 24895 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 136(*/0x88, 0x01/*)*/, |
| 24896 | GIR_BuildMI, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24897 | GIR_AddTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24898 | GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, |
| 24899 | GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, |
| 24900 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 135(*/0x87, 0x01/*)*/, |
| 24901 | GIR_BuildMI, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24902 | GIR_AddTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24903 | GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, |
| 24904 | GIR_AddImm8, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/30, |
| 24905 | GIR_AddImm8, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/2, |
| 24906 | GIR_AddImm8, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/31, |
| 24907 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 134(*/0x86, 0x01/*)*/, |
| 24908 | GIR_BuildMI, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24909 | GIR_AddTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24910 | GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, |
| 24911 | GIR_AddSimpleTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, |
| 24912 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 133(*/0x85, 0x01/*)*/, |
| 24913 | GIR_BuildMI, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24914 | GIR_AddTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24915 | GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, |
| 24916 | GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, |
| 24917 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 132(*/0x84, 0x01/*)*/, |
| 24918 | GIR_BuildMI, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24919 | GIR_AddTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24920 | GIR_AddSimpleTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, |
| 24921 | GIR_AddImm8, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Imm*/28, |
| 24922 | GIR_AddImm8, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Imm*/4, |
| 24923 | GIR_AddImm8, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Imm*/31, |
| 24924 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 131(*/0x83, 0x01/*)*/, |
| 24925 | GIR_BuildMI, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24926 | GIR_AddTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24927 | GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, |
| 24928 | GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, |
| 24929 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 130(*/0x82, 0x01/*)*/, |
| 24930 | GIR_BuildMI, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24931 | GIR_AddTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24932 | GIR_AddSimpleTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, |
| 24933 | GIR_AddSimpleTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, |
| 24934 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 129(*/0x81, 0x01/*)*/, |
| 24935 | GIR_BuildMI, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24936 | GIR_AddTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*/127, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24937 | GIR_AddImm, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 24938 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 128(*/0x80, 0x01/*)*/, |
| 24939 | GIR_BuildMI, /*InsnID*/127, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24940 | GIR_AddTempRegister, /*InsnID*/127, /*TempRegID*/126, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24941 | GIR_AddSimpleTempRegister, /*InsnID*/127, /*TempRegID*/127, |
| 24942 | GIR_AddImm, /*InsnID*/127, /*Imm*/GIMT_Encode8(61680), |
| 24943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/127, |
| 24944 | GIR_BuildMI, /*InsnID*/126, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24945 | GIR_AddTempRegister, /*InsnID*/126, /*TempRegID*/125, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24946 | GIR_AddImm, /*InsnID*/126, /*Imm*/GIMT_Encode8(52428), |
| 24947 | GIR_ConstrainSelectedInstOperands, /*InsnID*/126, |
| 24948 | GIR_BuildMI, /*InsnID*/125, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24949 | GIR_AddTempRegister, /*InsnID*/125, /*TempRegID*/124, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24950 | GIR_AddSimpleTempRegister, /*InsnID*/125, /*TempRegID*/125, |
| 24951 | GIR_AddImm, /*InsnID*/125, /*Imm*/GIMT_Encode8(52428), |
| 24952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/125, |
| 24953 | GIR_BuildMI, /*InsnID*/124, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24954 | GIR_AddTempRegister, /*InsnID*/124, /*TempRegID*/123, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24955 | GIR_AddImm, /*InsnID*/124, /*Imm*/GIMT_Encode8(43690), |
| 24956 | GIR_ConstrainSelectedInstOperands, /*InsnID*/124, |
| 24957 | GIR_BuildMI, /*InsnID*/123, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24958 | GIR_AddTempRegister, /*InsnID*/123, /*TempRegID*/122, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24959 | GIR_AddSimpleTempRegister, /*InsnID*/123, /*TempRegID*/123, |
| 24960 | GIR_AddImm, /*InsnID*/123, /*Imm*/GIMT_Encode8(43690), |
| 24961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/123, |
| 24962 | GIR_BuildMI, /*InsnID*/122, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24963 | GIR_AddTempRegister, /*InsnID*/122, /*TempRegID*/121, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24964 | GIR_Copy, /*NewInsnID*/122, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24965 | GIR_AddImm8, /*InsnID*/122, /*Imm*/1, |
| 24966 | GIR_AddImm8, /*InsnID*/122, /*Imm*/0, |
| 24967 | GIR_AddImm8, /*InsnID*/122, /*Imm*/30, |
| 24968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/122, |
| 24969 | GIR_BuildMI, /*InsnID*/121, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24970 | GIR_AddTempRegister, /*InsnID*/121, /*TempRegID*/120, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24971 | GIR_AddSimpleTempRegister, /*InsnID*/121, /*TempRegID*/121, |
| 24972 | GIR_AddSimpleTempRegister, /*InsnID*/121, /*TempRegID*/122, |
| 24973 | GIR_ConstrainSelectedInstOperands, /*InsnID*/121, |
| 24974 | GIR_BuildMI, /*InsnID*/120, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 24975 | GIR_AddTempRegister, /*InsnID*/120, /*TempRegID*/119, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24976 | GIR_AddImm, /*InsnID*/120, /*Imm*/GIMT_Encode8(21845), |
| 24977 | GIR_ConstrainSelectedInstOperands, /*InsnID*/120, |
| 24978 | GIR_BuildMI, /*InsnID*/119, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 24979 | GIR_AddTempRegister, /*InsnID*/119, /*TempRegID*/118, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24980 | GIR_AddSimpleTempRegister, /*InsnID*/119, /*TempRegID*/119, |
| 24981 | GIR_AddImm, /*InsnID*/119, /*Imm*/GIMT_Encode8(21845), |
| 24982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/119, |
| 24983 | GIR_BuildMI, /*InsnID*/118, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 24984 | GIR_AddTempRegister, /*InsnID*/118, /*TempRegID*/117, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24985 | GIR_Copy, /*NewInsnID*/118, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 24986 | GIR_AddImm8, /*InsnID*/118, /*Imm*/31, |
| 24987 | GIR_AddImm8, /*InsnID*/118, /*Imm*/1, |
| 24988 | GIR_AddImm8, /*InsnID*/118, /*Imm*/31, |
| 24989 | GIR_ConstrainSelectedInstOperands, /*InsnID*/118, |
| 24990 | GIR_BuildMI, /*InsnID*/117, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 24991 | GIR_AddTempRegister, /*InsnID*/117, /*TempRegID*/116, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24992 | GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/117, |
| 24993 | GIR_AddSimpleTempRegister, /*InsnID*/117, /*TempRegID*/118, |
| 24994 | GIR_ConstrainSelectedInstOperands, /*InsnID*/117, |
| 24995 | GIR_BuildMI, /*InsnID*/116, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 24996 | GIR_AddTempRegister, /*InsnID*/116, /*TempRegID*/115, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 24997 | GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/116, |
| 24998 | GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/120, |
| 24999 | GIR_ConstrainSelectedInstOperands, /*InsnID*/116, |
| 25000 | GIR_BuildMI, /*InsnID*/115, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25001 | GIR_AddTempRegister, /*InsnID*/115, /*TempRegID*/114, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25002 | GIR_AddSimpleTempRegister, /*InsnID*/115, /*TempRegID*/115, |
| 25003 | GIR_AddImm8, /*InsnID*/115, /*Imm*/2, |
| 25004 | GIR_AddImm8, /*InsnID*/115, /*Imm*/0, |
| 25005 | GIR_AddImm8, /*InsnID*/115, /*Imm*/29, |
| 25006 | GIR_ConstrainSelectedInstOperands, /*InsnID*/115, |
| 25007 | GIR_BuildMI, /*InsnID*/114, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25008 | GIR_AddTempRegister, /*InsnID*/114, /*TempRegID*/113, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25009 | GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/114, |
| 25010 | GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/124, |
| 25011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/114, |
| 25012 | GIR_BuildMI, /*InsnID*/113, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25013 | GIR_AddTempRegister, /*InsnID*/113, /*TempRegID*/112, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25014 | GIR_AddImm, /*InsnID*/113, /*Imm*/GIMT_Encode8(13107), |
| 25015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/113, |
| 25016 | GIR_BuildMI, /*InsnID*/112, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25017 | GIR_AddTempRegister, /*InsnID*/112, /*TempRegID*/111, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25018 | GIR_AddSimpleTempRegister, /*InsnID*/112, /*TempRegID*/112, |
| 25019 | GIR_AddImm, /*InsnID*/112, /*Imm*/GIMT_Encode8(13107), |
| 25020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/112, |
| 25021 | GIR_BuildMI, /*InsnID*/111, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25022 | GIR_AddTempRegister, /*InsnID*/111, /*TempRegID*/110, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25023 | GIR_AddImm, /*InsnID*/111, /*Imm*/GIMT_Encode8(43690), |
| 25024 | GIR_ConstrainSelectedInstOperands, /*InsnID*/111, |
| 25025 | GIR_BuildMI, /*InsnID*/110, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25026 | GIR_AddTempRegister, /*InsnID*/110, /*TempRegID*/109, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25027 | GIR_AddSimpleTempRegister, /*InsnID*/110, /*TempRegID*/110, |
| 25028 | GIR_AddImm, /*InsnID*/110, /*Imm*/GIMT_Encode8(43690), |
| 25029 | GIR_ConstrainSelectedInstOperands, /*InsnID*/110, |
| 25030 | GIR_BuildMI, /*InsnID*/109, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25031 | GIR_AddTempRegister, /*InsnID*/109, /*TempRegID*/108, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25032 | GIR_Copy, /*NewInsnID*/109, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25033 | GIR_AddImm8, /*InsnID*/109, /*Imm*/1, |
| 25034 | GIR_AddImm8, /*InsnID*/109, /*Imm*/0, |
| 25035 | GIR_AddImm8, /*InsnID*/109, /*Imm*/30, |
| 25036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/109, |
| 25037 | GIR_BuildMI, /*InsnID*/108, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25038 | GIR_AddTempRegister, /*InsnID*/108, /*TempRegID*/107, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25039 | GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/108, |
| 25040 | GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/109, |
| 25041 | GIR_ConstrainSelectedInstOperands, /*InsnID*/108, |
| 25042 | GIR_BuildMI, /*InsnID*/107, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25043 | GIR_AddTempRegister, /*InsnID*/107, /*TempRegID*/106, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25044 | GIR_AddImm, /*InsnID*/107, /*Imm*/GIMT_Encode8(21845), |
| 25045 | GIR_ConstrainSelectedInstOperands, /*InsnID*/107, |
| 25046 | GIR_BuildMI, /*InsnID*/106, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25047 | GIR_AddTempRegister, /*InsnID*/106, /*TempRegID*/105, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25048 | GIR_AddSimpleTempRegister, /*InsnID*/106, /*TempRegID*/106, |
| 25049 | GIR_AddImm, /*InsnID*/106, /*Imm*/GIMT_Encode8(21845), |
| 25050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/106, |
| 25051 | GIR_BuildMI, /*InsnID*/105, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25052 | GIR_AddTempRegister, /*InsnID*/105, /*TempRegID*/104, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25053 | GIR_Copy, /*NewInsnID*/105, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25054 | GIR_AddImm8, /*InsnID*/105, /*Imm*/31, |
| 25055 | GIR_AddImm8, /*InsnID*/105, /*Imm*/1, |
| 25056 | GIR_AddImm8, /*InsnID*/105, /*Imm*/31, |
| 25057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/105, |
| 25058 | GIR_BuildMI, /*InsnID*/104, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25059 | GIR_AddTempRegister, /*InsnID*/104, /*TempRegID*/103, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25060 | GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/104, |
| 25061 | GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/105, |
| 25062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/104, |
| 25063 | GIR_BuildMI, /*InsnID*/103, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25064 | GIR_AddTempRegister, /*InsnID*/103, /*TempRegID*/102, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25065 | GIR_AddSimpleTempRegister, /*InsnID*/103, /*TempRegID*/103, |
| 25066 | GIR_AddSimpleTempRegister, /*InsnID*/103, /*TempRegID*/107, |
| 25067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/103, |
| 25068 | GIR_BuildMI, /*InsnID*/102, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25069 | GIR_AddTempRegister, /*InsnID*/102, /*TempRegID*/101, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25070 | GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/102, |
| 25071 | GIR_AddImm8, /*InsnID*/102, /*Imm*/30, |
| 25072 | GIR_AddImm8, /*InsnID*/102, /*Imm*/2, |
| 25073 | GIR_AddImm8, /*InsnID*/102, /*Imm*/31, |
| 25074 | GIR_ConstrainSelectedInstOperands, /*InsnID*/102, |
| 25075 | GIR_BuildMI, /*InsnID*/101, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25076 | GIR_AddTempRegister, /*InsnID*/101, /*TempRegID*/100, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25077 | GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/101, |
| 25078 | GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/111, |
| 25079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/101, |
| 25080 | GIR_BuildMI, /*InsnID*/100, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25081 | GIR_AddTempRegister, /*InsnID*/100, /*TempRegID*/99, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25082 | GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/100, |
| 25083 | GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/113, |
| 25084 | GIR_ConstrainSelectedInstOperands, /*InsnID*/100, |
| 25085 | GIR_BuildMI, /*InsnID*/99, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25086 | GIR_AddTempRegister, /*InsnID*/99, /*TempRegID*/98, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25087 | GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/99, |
| 25088 | GIR_AddImm8, /*InsnID*/99, /*Imm*/4, |
| 25089 | GIR_AddImm8, /*InsnID*/99, /*Imm*/0, |
| 25090 | GIR_AddImm8, /*InsnID*/99, /*Imm*/27, |
| 25091 | GIR_ConstrainSelectedInstOperands, /*InsnID*/99, |
| 25092 | GIR_BuildMI, /*InsnID*/98, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25093 | GIR_AddTempRegister, /*InsnID*/98, /*TempRegID*/97, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25094 | GIR_AddSimpleTempRegister, /*InsnID*/98, /*TempRegID*/98, |
| 25095 | GIR_AddSimpleTempRegister, /*InsnID*/98, /*TempRegID*/126, |
| 25096 | GIR_ConstrainSelectedInstOperands, /*InsnID*/98, |
| 25097 | GIR_BuildMI, /*InsnID*/97, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25098 | GIR_AddTempRegister, /*InsnID*/97, /*TempRegID*/96, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25099 | GIR_AddImm, /*InsnID*/97, /*Imm*/GIMT_Encode8(3855), |
| 25100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/97, |
| 25101 | GIR_BuildMI, /*InsnID*/96, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25102 | GIR_AddTempRegister, /*InsnID*/96, /*TempRegID*/95, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25103 | GIR_AddSimpleTempRegister, /*InsnID*/96, /*TempRegID*/96, |
| 25104 | GIR_AddImm, /*InsnID*/96, /*Imm*/GIMT_Encode8(3855), |
| 25105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/96, |
| 25106 | GIR_BuildMI, /*InsnID*/95, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25107 | GIR_AddTempRegister, /*InsnID*/95, /*TempRegID*/94, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25108 | GIR_AddImm, /*InsnID*/95, /*Imm*/GIMT_Encode8(52428), |
| 25109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/95, |
| 25110 | GIR_BuildMI, /*InsnID*/94, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25111 | GIR_AddTempRegister, /*InsnID*/94, /*TempRegID*/93, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25112 | GIR_AddSimpleTempRegister, /*InsnID*/94, /*TempRegID*/94, |
| 25113 | GIR_AddImm, /*InsnID*/94, /*Imm*/GIMT_Encode8(52428), |
| 25114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/94, |
| 25115 | GIR_BuildMI, /*InsnID*/93, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25116 | GIR_AddTempRegister, /*InsnID*/93, /*TempRegID*/92, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25117 | GIR_AddImm, /*InsnID*/93, /*Imm*/GIMT_Encode8(43690), |
| 25118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/93, |
| 25119 | GIR_BuildMI, /*InsnID*/92, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25120 | GIR_AddTempRegister, /*InsnID*/92, /*TempRegID*/91, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25121 | GIR_AddSimpleTempRegister, /*InsnID*/92, /*TempRegID*/92, |
| 25122 | GIR_AddImm, /*InsnID*/92, /*Imm*/GIMT_Encode8(43690), |
| 25123 | GIR_ConstrainSelectedInstOperands, /*InsnID*/92, |
| 25124 | GIR_BuildMI, /*InsnID*/91, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25125 | GIR_AddTempRegister, /*InsnID*/91, /*TempRegID*/90, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25126 | GIR_Copy, /*NewInsnID*/91, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25127 | GIR_AddImm8, /*InsnID*/91, /*Imm*/1, |
| 25128 | GIR_AddImm8, /*InsnID*/91, /*Imm*/0, |
| 25129 | GIR_AddImm8, /*InsnID*/91, /*Imm*/30, |
| 25130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/91, |
| 25131 | GIR_BuildMI, /*InsnID*/90, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25132 | GIR_AddTempRegister, /*InsnID*/90, /*TempRegID*/89, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25133 | GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/90, |
| 25134 | GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/91, |
| 25135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/90, |
| 25136 | GIR_BuildMI, /*InsnID*/89, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25137 | GIR_AddTempRegister, /*InsnID*/89, /*TempRegID*/88, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25138 | GIR_AddImm, /*InsnID*/89, /*Imm*/GIMT_Encode8(21845), |
| 25139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/89, |
| 25140 | GIR_BuildMI, /*InsnID*/88, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25141 | GIR_AddTempRegister, /*InsnID*/88, /*TempRegID*/87, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25142 | GIR_AddSimpleTempRegister, /*InsnID*/88, /*TempRegID*/88, |
| 25143 | GIR_AddImm, /*InsnID*/88, /*Imm*/GIMT_Encode8(21845), |
| 25144 | GIR_ConstrainSelectedInstOperands, /*InsnID*/88, |
| 25145 | GIR_BuildMI, /*InsnID*/87, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25146 | GIR_AddTempRegister, /*InsnID*/87, /*TempRegID*/86, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25147 | GIR_Copy, /*NewInsnID*/87, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25148 | GIR_AddImm8, /*InsnID*/87, /*Imm*/31, |
| 25149 | GIR_AddImm8, /*InsnID*/87, /*Imm*/1, |
| 25150 | GIR_AddImm8, /*InsnID*/87, /*Imm*/31, |
| 25151 | GIR_ConstrainSelectedInstOperands, /*InsnID*/87, |
| 25152 | GIR_BuildMI, /*InsnID*/86, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25153 | GIR_AddTempRegister, /*InsnID*/86, /*TempRegID*/85, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25154 | GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/86, |
| 25155 | GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/87, |
| 25156 | GIR_ConstrainSelectedInstOperands, /*InsnID*/86, |
| 25157 | GIR_BuildMI, /*InsnID*/85, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25158 | GIR_AddTempRegister, /*InsnID*/85, /*TempRegID*/84, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25159 | GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/85, |
| 25160 | GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/89, |
| 25161 | GIR_ConstrainSelectedInstOperands, /*InsnID*/85, |
| 25162 | GIR_BuildMI, /*InsnID*/84, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25163 | GIR_AddTempRegister, /*InsnID*/84, /*TempRegID*/83, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25164 | GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/84, |
| 25165 | GIR_AddImm8, /*InsnID*/84, /*Imm*/2, |
| 25166 | GIR_AddImm8, /*InsnID*/84, /*Imm*/0, |
| 25167 | GIR_AddImm8, /*InsnID*/84, /*Imm*/29, |
| 25168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/84, |
| 25169 | GIR_BuildMI, /*InsnID*/83, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25170 | GIR_AddTempRegister, /*InsnID*/83, /*TempRegID*/82, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25171 | GIR_AddSimpleTempRegister, /*InsnID*/83, /*TempRegID*/83, |
| 25172 | GIR_AddSimpleTempRegister, /*InsnID*/83, /*TempRegID*/93, |
| 25173 | GIR_ConstrainSelectedInstOperands, /*InsnID*/83, |
| 25174 | GIR_BuildMI, /*InsnID*/82, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25175 | GIR_AddTempRegister, /*InsnID*/82, /*TempRegID*/81, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25176 | GIR_AddImm, /*InsnID*/82, /*Imm*/GIMT_Encode8(13107), |
| 25177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/82, |
| 25178 | GIR_BuildMI, /*InsnID*/81, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25179 | GIR_AddTempRegister, /*InsnID*/81, /*TempRegID*/80, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25180 | GIR_AddSimpleTempRegister, /*InsnID*/81, /*TempRegID*/81, |
| 25181 | GIR_AddImm, /*InsnID*/81, /*Imm*/GIMT_Encode8(13107), |
| 25182 | GIR_ConstrainSelectedInstOperands, /*InsnID*/81, |
| 25183 | GIR_BuildMI, /*InsnID*/80, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25184 | GIR_AddTempRegister, /*InsnID*/80, /*TempRegID*/79, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25185 | GIR_AddImm, /*InsnID*/80, /*Imm*/GIMT_Encode8(43690), |
| 25186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/80, |
| 25187 | GIR_BuildMI, /*InsnID*/79, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25188 | GIR_AddTempRegister, /*InsnID*/79, /*TempRegID*/78, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25189 | GIR_AddSimpleTempRegister, /*InsnID*/79, /*TempRegID*/79, |
| 25190 | GIR_AddImm, /*InsnID*/79, /*Imm*/GIMT_Encode8(43690), |
| 25191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/79, |
| 25192 | GIR_BuildMI, /*InsnID*/78, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25193 | GIR_AddTempRegister, /*InsnID*/78, /*TempRegID*/77, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25194 | GIR_Copy, /*NewInsnID*/78, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25195 | GIR_AddImm8, /*InsnID*/78, /*Imm*/1, |
| 25196 | GIR_AddImm8, /*InsnID*/78, /*Imm*/0, |
| 25197 | GIR_AddImm8, /*InsnID*/78, /*Imm*/30, |
| 25198 | GIR_ConstrainSelectedInstOperands, /*InsnID*/78, |
| 25199 | GIR_BuildMI, /*InsnID*/77, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25200 | GIR_AddTempRegister, /*InsnID*/77, /*TempRegID*/76, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25201 | GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/77, |
| 25202 | GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/78, |
| 25203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/77, |
| 25204 | GIR_BuildMI, /*InsnID*/76, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25205 | GIR_AddTempRegister, /*InsnID*/76, /*TempRegID*/75, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25206 | GIR_AddImm, /*InsnID*/76, /*Imm*/GIMT_Encode8(21845), |
| 25207 | GIR_ConstrainSelectedInstOperands, /*InsnID*/76, |
| 25208 | GIR_BuildMI, /*InsnID*/75, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25209 | GIR_AddTempRegister, /*InsnID*/75, /*TempRegID*/74, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25210 | GIR_AddSimpleTempRegister, /*InsnID*/75, /*TempRegID*/75, |
| 25211 | GIR_AddImm, /*InsnID*/75, /*Imm*/GIMT_Encode8(21845), |
| 25212 | GIR_ConstrainSelectedInstOperands, /*InsnID*/75, |
| 25213 | GIR_BuildMI, /*InsnID*/74, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25214 | GIR_AddTempRegister, /*InsnID*/74, /*TempRegID*/73, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25215 | GIR_Copy, /*NewInsnID*/74, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25216 | GIR_AddImm8, /*InsnID*/74, /*Imm*/31, |
| 25217 | GIR_AddImm8, /*InsnID*/74, /*Imm*/1, |
| 25218 | GIR_AddImm8, /*InsnID*/74, /*Imm*/31, |
| 25219 | GIR_ConstrainSelectedInstOperands, /*InsnID*/74, |
| 25220 | GIR_BuildMI, /*InsnID*/73, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25221 | GIR_AddTempRegister, /*InsnID*/73, /*TempRegID*/72, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25222 | GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/73, |
| 25223 | GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/74, |
| 25224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/73, |
| 25225 | GIR_BuildMI, /*InsnID*/72, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25226 | GIR_AddTempRegister, /*InsnID*/72, /*TempRegID*/71, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25227 | GIR_AddSimpleTempRegister, /*InsnID*/72, /*TempRegID*/72, |
| 25228 | GIR_AddSimpleTempRegister, /*InsnID*/72, /*TempRegID*/76, |
| 25229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/72, |
| 25230 | GIR_BuildMI, /*InsnID*/71, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25231 | GIR_AddTempRegister, /*InsnID*/71, /*TempRegID*/70, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25232 | GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/71, |
| 25233 | GIR_AddImm8, /*InsnID*/71, /*Imm*/30, |
| 25234 | GIR_AddImm8, /*InsnID*/71, /*Imm*/2, |
| 25235 | GIR_AddImm8, /*InsnID*/71, /*Imm*/31, |
| 25236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/71, |
| 25237 | GIR_BuildMI, /*InsnID*/70, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25238 | GIR_AddTempRegister, /*InsnID*/70, /*TempRegID*/69, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25239 | GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/70, |
| 25240 | GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/80, |
| 25241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/70, |
| 25242 | GIR_BuildMI, /*InsnID*/69, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25243 | GIR_AddTempRegister, /*InsnID*/69, /*TempRegID*/68, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25244 | GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/69, |
| 25245 | GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/82, |
| 25246 | GIR_ConstrainSelectedInstOperands, /*InsnID*/69, |
| 25247 | GIR_BuildMI, /*InsnID*/68, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25248 | GIR_AddTempRegister, /*InsnID*/68, /*TempRegID*/67, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25249 | GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/68, |
| 25250 | GIR_AddImm8, /*InsnID*/68, /*Imm*/28, |
| 25251 | GIR_AddImm8, /*InsnID*/68, /*Imm*/4, |
| 25252 | GIR_AddImm8, /*InsnID*/68, /*Imm*/31, |
| 25253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/68, |
| 25254 | GIR_BuildMI, /*InsnID*/67, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25255 | GIR_AddTempRegister, /*InsnID*/67, /*TempRegID*/66, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25256 | GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/67, |
| 25257 | GIR_AddSimpleTempRegister, /*InsnID*/67, /*TempRegID*/95, |
| 25258 | GIR_ConstrainSelectedInstOperands, /*InsnID*/67, |
| 25259 | GIR_BuildMI, /*InsnID*/66, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25260 | GIR_AddTempRegister, /*InsnID*/66, /*TempRegID*/65, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25261 | GIR_AddSimpleTempRegister, /*InsnID*/66, /*TempRegID*/66, |
| 25262 | GIR_AddSimpleTempRegister, /*InsnID*/66, /*TempRegID*/97, |
| 25263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/66, |
| 25264 | GIR_BuildMI, /*InsnID*/65, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25265 | GIR_AddTempRegister, /*InsnID*/65, /*TempRegID*/64, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25266 | GIR_AddImm, /*InsnID*/65, /*Imm*/GIMT_Encode8(61680), |
| 25267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/65, |
| 25268 | GIR_BuildMI, /*InsnID*/64, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25269 | GIR_AddTempRegister, /*InsnID*/64, /*TempRegID*/63, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25270 | GIR_AddSimpleTempRegister, /*InsnID*/64, /*TempRegID*/64, |
| 25271 | GIR_AddImm, /*InsnID*/64, /*Imm*/GIMT_Encode8(61680), |
| 25272 | GIR_ConstrainSelectedInstOperands, /*InsnID*/64, |
| 25273 | GIR_BuildMI, /*InsnID*/63, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25274 | GIR_AddTempRegister, /*InsnID*/63, /*TempRegID*/62, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25275 | GIR_AddImm, /*InsnID*/63, /*Imm*/GIMT_Encode8(52428), |
| 25276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/63, |
| 25277 | GIR_BuildMI, /*InsnID*/62, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25278 | GIR_AddTempRegister, /*InsnID*/62, /*TempRegID*/61, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25279 | GIR_AddSimpleTempRegister, /*InsnID*/62, /*TempRegID*/62, |
| 25280 | GIR_AddImm, /*InsnID*/62, /*Imm*/GIMT_Encode8(52428), |
| 25281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/62, |
| 25282 | GIR_BuildMI, /*InsnID*/61, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25283 | GIR_AddTempRegister, /*InsnID*/61, /*TempRegID*/60, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25284 | GIR_AddImm, /*InsnID*/61, /*Imm*/GIMT_Encode8(43690), |
| 25285 | GIR_ConstrainSelectedInstOperands, /*InsnID*/61, |
| 25286 | GIR_BuildMI, /*InsnID*/60, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25287 | GIR_AddTempRegister, /*InsnID*/60, /*TempRegID*/59, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25288 | GIR_AddSimpleTempRegister, /*InsnID*/60, /*TempRegID*/60, |
| 25289 | GIR_AddImm, /*InsnID*/60, /*Imm*/GIMT_Encode8(43690), |
| 25290 | GIR_ConstrainSelectedInstOperands, /*InsnID*/60, |
| 25291 | GIR_BuildMI, /*InsnID*/59, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25292 | GIR_AddTempRegister, /*InsnID*/59, /*TempRegID*/58, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25293 | GIR_Copy, /*NewInsnID*/59, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25294 | GIR_AddImm8, /*InsnID*/59, /*Imm*/1, |
| 25295 | GIR_AddImm8, /*InsnID*/59, /*Imm*/0, |
| 25296 | GIR_AddImm8, /*InsnID*/59, /*Imm*/30, |
| 25297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/59, |
| 25298 | GIR_BuildMI, /*InsnID*/58, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25299 | GIR_AddTempRegister, /*InsnID*/58, /*TempRegID*/57, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25300 | GIR_AddSimpleTempRegister, /*InsnID*/58, /*TempRegID*/58, |
| 25301 | GIR_AddSimpleTempRegister, /*InsnID*/58, /*TempRegID*/59, |
| 25302 | GIR_ConstrainSelectedInstOperands, /*InsnID*/58, |
| 25303 | GIR_BuildMI, /*InsnID*/57, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25304 | GIR_AddTempRegister, /*InsnID*/57, /*TempRegID*/56, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25305 | GIR_AddImm, /*InsnID*/57, /*Imm*/GIMT_Encode8(21845), |
| 25306 | GIR_ConstrainSelectedInstOperands, /*InsnID*/57, |
| 25307 | GIR_BuildMI, /*InsnID*/56, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25308 | GIR_AddTempRegister, /*InsnID*/56, /*TempRegID*/55, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25309 | GIR_AddSimpleTempRegister, /*InsnID*/56, /*TempRegID*/56, |
| 25310 | GIR_AddImm, /*InsnID*/56, /*Imm*/GIMT_Encode8(21845), |
| 25311 | GIR_ConstrainSelectedInstOperands, /*InsnID*/56, |
| 25312 | GIR_BuildMI, /*InsnID*/55, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25313 | GIR_AddTempRegister, /*InsnID*/55, /*TempRegID*/54, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25314 | GIR_Copy, /*NewInsnID*/55, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25315 | GIR_AddImm8, /*InsnID*/55, /*Imm*/31, |
| 25316 | GIR_AddImm8, /*InsnID*/55, /*Imm*/1, |
| 25317 | GIR_AddImm8, /*InsnID*/55, /*Imm*/31, |
| 25318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/55, |
| 25319 | GIR_BuildMI, /*InsnID*/54, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25320 | GIR_AddTempRegister, /*InsnID*/54, /*TempRegID*/53, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25321 | GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/54, |
| 25322 | GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/55, |
| 25323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/54, |
| 25324 | GIR_BuildMI, /*InsnID*/53, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25325 | GIR_AddTempRegister, /*InsnID*/53, /*TempRegID*/52, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25326 | GIR_AddSimpleTempRegister, /*InsnID*/53, /*TempRegID*/53, |
| 25327 | GIR_AddSimpleTempRegister, /*InsnID*/53, /*TempRegID*/57, |
| 25328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/53, |
| 25329 | GIR_BuildMI, /*InsnID*/52, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25330 | GIR_AddTempRegister, /*InsnID*/52, /*TempRegID*/51, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25331 | GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/52, |
| 25332 | GIR_AddImm8, /*InsnID*/52, /*Imm*/2, |
| 25333 | GIR_AddImm8, /*InsnID*/52, /*Imm*/0, |
| 25334 | GIR_AddImm8, /*InsnID*/52, /*Imm*/29, |
| 25335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/52, |
| 25336 | GIR_BuildMI, /*InsnID*/51, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25337 | GIR_AddTempRegister, /*InsnID*/51, /*TempRegID*/50, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25338 | GIR_AddSimpleTempRegister, /*InsnID*/51, /*TempRegID*/51, |
| 25339 | GIR_AddSimpleTempRegister, /*InsnID*/51, /*TempRegID*/61, |
| 25340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/51, |
| 25341 | GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25342 | GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25343 | GIR_AddImm, /*InsnID*/50, /*Imm*/GIMT_Encode8(13107), |
| 25344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/50, |
| 25345 | GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25346 | GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25347 | GIR_AddSimpleTempRegister, /*InsnID*/49, /*TempRegID*/49, |
| 25348 | GIR_AddImm, /*InsnID*/49, /*Imm*/GIMT_Encode8(13107), |
| 25349 | GIR_ConstrainSelectedInstOperands, /*InsnID*/49, |
| 25350 | GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25351 | GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25352 | GIR_AddImm, /*InsnID*/48, /*Imm*/GIMT_Encode8(43690), |
| 25353 | GIR_ConstrainSelectedInstOperands, /*InsnID*/48, |
| 25354 | GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25355 | GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25356 | GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47, |
| 25357 | GIR_AddImm, /*InsnID*/47, /*Imm*/GIMT_Encode8(43690), |
| 25358 | GIR_ConstrainSelectedInstOperands, /*InsnID*/47, |
| 25359 | GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25360 | GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25361 | GIR_Copy, /*NewInsnID*/46, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25362 | GIR_AddImm8, /*InsnID*/46, /*Imm*/1, |
| 25363 | GIR_AddImm8, /*InsnID*/46, /*Imm*/0, |
| 25364 | GIR_AddImm8, /*InsnID*/46, /*Imm*/30, |
| 25365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/46, |
| 25366 | GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25367 | GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25368 | GIR_AddSimpleTempRegister, /*InsnID*/45, /*TempRegID*/45, |
| 25369 | GIR_AddSimpleTempRegister, /*InsnID*/45, /*TempRegID*/46, |
| 25370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/45, |
| 25371 | GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25372 | GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25373 | GIR_AddImm, /*InsnID*/44, /*Imm*/GIMT_Encode8(21845), |
| 25374 | GIR_ConstrainSelectedInstOperands, /*InsnID*/44, |
| 25375 | GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25376 | GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25377 | GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43, |
| 25378 | GIR_AddImm, /*InsnID*/43, /*Imm*/GIMT_Encode8(21845), |
| 25379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/43, |
| 25380 | GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25381 | GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25382 | GIR_Copy, /*NewInsnID*/42, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25383 | GIR_AddImm8, /*InsnID*/42, /*Imm*/31, |
| 25384 | GIR_AddImm8, /*InsnID*/42, /*Imm*/1, |
| 25385 | GIR_AddImm8, /*InsnID*/42, /*Imm*/31, |
| 25386 | GIR_ConstrainSelectedInstOperands, /*InsnID*/42, |
| 25387 | GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25388 | GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25389 | GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/41, |
| 25390 | GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/42, |
| 25391 | GIR_ConstrainSelectedInstOperands, /*InsnID*/41, |
| 25392 | GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25393 | GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25394 | GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40, |
| 25395 | GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/44, |
| 25396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/40, |
| 25397 | GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25398 | GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25399 | GIR_AddSimpleTempRegister, /*InsnID*/39, /*TempRegID*/39, |
| 25400 | GIR_AddImm8, /*InsnID*/39, /*Imm*/30, |
| 25401 | GIR_AddImm8, /*InsnID*/39, /*Imm*/2, |
| 25402 | GIR_AddImm8, /*InsnID*/39, /*Imm*/31, |
| 25403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/39, |
| 25404 | GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25405 | GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25406 | GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38, |
| 25407 | GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/48, |
| 25408 | GIR_ConstrainSelectedInstOperands, /*InsnID*/38, |
| 25409 | GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25410 | GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25411 | GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/37, |
| 25412 | GIR_AddSimpleTempRegister, /*InsnID*/37, /*TempRegID*/50, |
| 25413 | GIR_ConstrainSelectedInstOperands, /*InsnID*/37, |
| 25414 | GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25415 | GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25416 | GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36, |
| 25417 | GIR_AddImm8, /*InsnID*/36, /*Imm*/4, |
| 25418 | GIR_AddImm8, /*InsnID*/36, /*Imm*/0, |
| 25419 | GIR_AddImm8, /*InsnID*/36, /*Imm*/27, |
| 25420 | GIR_ConstrainSelectedInstOperands, /*InsnID*/36, |
| 25421 | GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25422 | GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25423 | GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35, |
| 25424 | GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/63, |
| 25425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/35, |
| 25426 | GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25427 | GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25428 | GIR_AddImm, /*InsnID*/34, /*Imm*/GIMT_Encode8(3855), |
| 25429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/34, |
| 25430 | GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25431 | GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25432 | GIR_AddSimpleTempRegister, /*InsnID*/33, /*TempRegID*/33, |
| 25433 | GIR_AddImm, /*InsnID*/33, /*Imm*/GIMT_Encode8(3855), |
| 25434 | GIR_ConstrainSelectedInstOperands, /*InsnID*/33, |
| 25435 | GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25436 | GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25437 | GIR_AddImm, /*InsnID*/32, /*Imm*/GIMT_Encode8(52428), |
| 25438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/32, |
| 25439 | GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25440 | GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25441 | GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31, |
| 25442 | GIR_AddImm, /*InsnID*/31, /*Imm*/GIMT_Encode8(52428), |
| 25443 | GIR_ConstrainSelectedInstOperands, /*InsnID*/31, |
| 25444 | GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25445 | GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25446 | GIR_AddImm, /*InsnID*/30, /*Imm*/GIMT_Encode8(43690), |
| 25447 | GIR_ConstrainSelectedInstOperands, /*InsnID*/30, |
| 25448 | GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25449 | GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25450 | GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29, |
| 25451 | GIR_AddImm, /*InsnID*/29, /*Imm*/GIMT_Encode8(43690), |
| 25452 | GIR_ConstrainSelectedInstOperands, /*InsnID*/29, |
| 25453 | GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25454 | GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25455 | GIR_Copy, /*NewInsnID*/28, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25456 | GIR_AddImm8, /*InsnID*/28, /*Imm*/1, |
| 25457 | GIR_AddImm8, /*InsnID*/28, /*Imm*/0, |
| 25458 | GIR_AddImm8, /*InsnID*/28, /*Imm*/30, |
| 25459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/28, |
| 25460 | GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25461 | GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25462 | GIR_AddSimpleTempRegister, /*InsnID*/27, /*TempRegID*/27, |
| 25463 | GIR_AddSimpleTempRegister, /*InsnID*/27, /*TempRegID*/28, |
| 25464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/27, |
| 25465 | GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25466 | GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25467 | GIR_AddImm, /*InsnID*/26, /*Imm*/GIMT_Encode8(21845), |
| 25468 | GIR_ConstrainSelectedInstOperands, /*InsnID*/26, |
| 25469 | GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25470 | GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25471 | GIR_AddSimpleTempRegister, /*InsnID*/25, /*TempRegID*/25, |
| 25472 | GIR_AddImm, /*InsnID*/25, /*Imm*/GIMT_Encode8(21845), |
| 25473 | GIR_ConstrainSelectedInstOperands, /*InsnID*/25, |
| 25474 | GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25475 | GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25476 | GIR_Copy, /*NewInsnID*/24, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25477 | GIR_AddImm8, /*InsnID*/24, /*Imm*/31, |
| 25478 | GIR_AddImm8, /*InsnID*/24, /*Imm*/1, |
| 25479 | GIR_AddImm8, /*InsnID*/24, /*Imm*/31, |
| 25480 | GIR_ConstrainSelectedInstOperands, /*InsnID*/24, |
| 25481 | GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25482 | GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25483 | GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/23, |
| 25484 | GIR_AddSimpleTempRegister, /*InsnID*/23, /*TempRegID*/24, |
| 25485 | GIR_ConstrainSelectedInstOperands, /*InsnID*/23, |
| 25486 | GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25487 | GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25488 | GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22, |
| 25489 | GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/26, |
| 25490 | GIR_ConstrainSelectedInstOperands, /*InsnID*/22, |
| 25491 | GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25492 | GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25493 | GIR_AddSimpleTempRegister, /*InsnID*/21, /*TempRegID*/21, |
| 25494 | GIR_AddImm8, /*InsnID*/21, /*Imm*/2, |
| 25495 | GIR_AddImm8, /*InsnID*/21, /*Imm*/0, |
| 25496 | GIR_AddImm8, /*InsnID*/21, /*Imm*/29, |
| 25497 | GIR_ConstrainSelectedInstOperands, /*InsnID*/21, |
| 25498 | GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25499 | GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25500 | GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20, |
| 25501 | GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/30, |
| 25502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/20, |
| 25503 | GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25504 | GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25505 | GIR_AddImm, /*InsnID*/19, /*Imm*/GIMT_Encode8(13107), |
| 25506 | GIR_ConstrainSelectedInstOperands, /*InsnID*/19, |
| 25507 | GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25508 | GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25509 | GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18, |
| 25510 | GIR_AddImm, /*InsnID*/18, /*Imm*/GIMT_Encode8(13107), |
| 25511 | GIR_ConstrainSelectedInstOperands, /*InsnID*/18, |
| 25512 | GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25513 | GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25514 | GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(43690), |
| 25515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/17, |
| 25516 | GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25517 | GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25518 | GIR_AddSimpleTempRegister, /*InsnID*/16, /*TempRegID*/16, |
| 25519 | GIR_AddImm, /*InsnID*/16, /*Imm*/GIMT_Encode8(43690), |
| 25520 | GIR_ConstrainSelectedInstOperands, /*InsnID*/16, |
| 25521 | GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25522 | GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25523 | GIR_Copy, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25524 | GIR_AddImm8, /*InsnID*/15, /*Imm*/1, |
| 25525 | GIR_AddImm8, /*InsnID*/15, /*Imm*/0, |
| 25526 | GIR_AddImm8, /*InsnID*/15, /*Imm*/30, |
| 25527 | GIR_ConstrainSelectedInstOperands, /*InsnID*/15, |
| 25528 | GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25529 | GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25530 | GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14, |
| 25531 | GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15, |
| 25532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/14, |
| 25533 | GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25534 | GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25535 | GIR_AddImm, /*InsnID*/13, /*Imm*/GIMT_Encode8(21845), |
| 25536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/13, |
| 25537 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25538 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25539 | GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12, |
| 25540 | GIR_AddImm, /*InsnID*/12, /*Imm*/GIMT_Encode8(21845), |
| 25541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/12, |
| 25542 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25543 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25544 | GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25545 | GIR_AddImm8, /*InsnID*/11, /*Imm*/31, |
| 25546 | GIR_AddImm8, /*InsnID*/11, /*Imm*/1, |
| 25547 | GIR_AddImm8, /*InsnID*/11, /*Imm*/31, |
| 25548 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 25549 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25550 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25551 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 25552 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/11, |
| 25553 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 25554 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25555 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25556 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 25557 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/13, |
| 25558 | GIR_ConstrainSelectedInstOperands, /*InsnID*/9, |
| 25559 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25560 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25561 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 25562 | GIR_AddImm8, /*InsnID*/8, /*Imm*/30, |
| 25563 | GIR_AddImm8, /*InsnID*/8, /*Imm*/2, |
| 25564 | GIR_AddImm8, /*InsnID*/8, /*Imm*/31, |
| 25565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 25566 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25567 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25568 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 25569 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/17, |
| 25570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 25571 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25572 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25573 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 25574 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/19, |
| 25575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 25576 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25577 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25578 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 25579 | GIR_AddImm8, /*InsnID*/5, /*Imm*/28, |
| 25580 | GIR_AddImm8, /*InsnID*/5, /*Imm*/4, |
| 25581 | GIR_AddImm8, /*InsnID*/5, /*Imm*/31, |
| 25582 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 25583 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::AND), |
| 25584 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25585 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 25586 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/32, |
| 25587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 25588 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(PPC::OR), |
| 25589 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25590 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 25591 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/34, |
| 25592 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 25593 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 25594 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25595 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 25596 | GIR_AddImm8, /*InsnID*/2, /*Imm*/24, |
| 25597 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 25598 | GIR_AddImm8, /*InsnID*/2, /*Imm*/31, |
| 25599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 25600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 25601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25602 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 25603 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/65, |
| 25604 | GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 25605 | GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 25606 | GIR_AddImm8, /*InsnID*/1, /*Imm*/15, |
| 25607 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 25608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 25609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 25610 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, |
| 25612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 25613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/24, |
| 25614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/31, |
| 25615 | GIR_RootConstrainSelectedInstOperands, |
| 25616 | // GIR_Coverage, 4833, |
| 25617 | GIR_EraseRootFromParent_Done, |
| 25618 | // Label 1749: @68415 |
| 25619 | GIM_Reject, |
| 25620 | // Label 1747: @68416 |
| 25621 | GIM_Reject, |
| 25622 | // Label 1745: @68417 |
| 25623 | GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(94107), // Rule ID 4834 // |
| 25624 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 25625 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::G8RCRegClassID), |
| 25626 | // (bitreverse:{ *:[i64] } i64:{ *:[i64] }:$A) => (OR8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (RLWIMI:{ *:[i32] } (RLWIMI:{ *:[i32] } (RLWINM:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 60:{ *:[i32] }, 4:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 3855:{ *:[i64] }), 3855:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 4:{ *:[i32] }, 59:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 61680:{ *:[i64] }), 61680:{ *:[i64] }))), sub_32:{ *:[i32] }), 24:{ *:[i32] }, 0:{ *:[i32] }, 31:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 60:{ *:[i32] }, 4:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 3855:{ *:[i64] }), 3855:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 4:{ *:[i32] }, 59:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 61680:{ *:[i64] }), 61680:{ *:[i64] }))), sub_32:{ *:[i32] }), 8:{ *:[i32] }, 8:{ *:[i32] }, 15:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 60:{ *:[i32] }, 4:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 3855:{ *:[i64] }), 3855:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 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*:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 4:{ *:[i32] }, 59:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 61680:{ *:[i64] }), 61680:{ *:[i64] }))), 32:{ *:[i32] }, 32:{ *:[i32] }), sub_32:{ *:[i32] }), 8:{ *:[i32] }, 8:{ *:[i32] }, 15:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 60:{ *:[i32] }, 4:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 3855:{ *:[i32] }), 3855:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 3855:{ *:[i64] }), 3855:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 62:{ *:[i32] }, 2:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 13107:{ *:[i32] }), 13107:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 13107:{ *:[i64] }), 13107:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } (OR8:{ *:[i64] } (AND8:{ *:[i64] } (RLDICL:{ *:[i64] } ?:{ *:[i64] }:$A, 63:{ *:[i32] }, 1:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 21845:{ *:[i32] }), 21845:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 21845:{ *:[i64] }), 21845:{ *:[i64] })), (AND8:{ *:[i64] } (RLDICR:{ *:[i64] } ?:{ *:[i64] }:$A, 1:{ *:[i32] }, 62:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 43690:{ *:[i32] }), 43690:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 43690:{ *:[i64] }), 43690:{ *:[i64] }))), 2:{ *:[i32] }, 61:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 52428:{ *:[i32] }), 52428:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 52428:{ *:[i64] }), 52428:{ *:[i64] }))), 4:{ *:[i32] }, 59:{ *:[i32] }), (ORI8:{ *:[i64] } (ORIS8:{ *:[i64] } (RLDICR:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ORI:{ *:[i32] } (LIS:{ *:[i32] } 61680:{ *:[i32] }), 61680:{ *:[i32] }), sub_32:{ *:[i32] }), 32:{ *:[i32] }, 31:{ *:[i32] }), 61680:{ *:[i64] }), 61680:{ *:[i64] }))), 32:{ *:[i32] }, 32:{ *:[i32] }), sub_32:{ *:[i32] }), 8:{ *:[i32] }, 24:{ *:[i32] }, 31:{ *:[i32] }), sub_32:{ *:[i32] })) |
| 25627 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 25628 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 25629 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 25630 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 25631 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 25632 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 25633 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 25634 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s64, |
| 25635 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s64, |
| 25636 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s64, |
| 25637 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s64, |
| 25638 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s64, |
| 25639 | GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s64, |
| 25640 | GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s64, |
| 25641 | GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s64, |
| 25642 | GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s64, |
| 25643 | GIR_MakeTempReg, /*TempRegID*/16, /*TypeID*/GILLT_s64, |
| 25644 | GIR_MakeTempReg, /*TempRegID*/17, /*TypeID*/GILLT_s64, |
| 25645 | GIR_MakeTempReg, /*TempRegID*/18, /*TypeID*/GILLT_s64, |
| 25646 | GIR_MakeTempReg, /*TempRegID*/19, /*TypeID*/GILLT_s64, |
| 25647 | GIR_MakeTempReg, /*TempRegID*/20, /*TypeID*/GILLT_s64, |
| 25648 | GIR_MakeTempReg, /*TempRegID*/21, /*TypeID*/GILLT_s32, |
| 25649 | GIR_MakeTempReg, /*TempRegID*/22, /*TypeID*/GILLT_s32, |
| 25650 | GIR_MakeTempReg, /*TempRegID*/23, /*TypeID*/GILLT_s64, |
| 25651 | GIR_MakeTempReg, /*TempRegID*/24, /*TypeID*/GILLT_s64, |
| 25652 | GIR_MakeTempReg, /*TempRegID*/25, /*TypeID*/GILLT_s64, |
| 25653 | GIR_MakeTempReg, /*TempRegID*/26, /*TypeID*/GILLT_s64, |
| 25654 | GIR_MakeTempReg, /*TempRegID*/27, /*TypeID*/GILLT_s64, |
| 25655 | GIR_MakeTempReg, /*TempRegID*/28, /*TypeID*/GILLT_s64, |
| 25656 | GIR_MakeTempReg, /*TempRegID*/29, /*TypeID*/GILLT_s64, |
| 25657 | GIR_MakeTempReg, /*TempRegID*/30, /*TypeID*/GILLT_s32, |
| 25658 | GIR_MakeTempReg, /*TempRegID*/31, /*TypeID*/GILLT_s32, |
| 25659 | GIR_MakeTempReg, /*TempRegID*/32, /*TypeID*/GILLT_s64, |
| 25660 | GIR_MakeTempReg, /*TempRegID*/33, /*TypeID*/GILLT_s64, |
| 25661 | GIR_MakeTempReg, /*TempRegID*/34, /*TypeID*/GILLT_s64, |
| 25662 | GIR_MakeTempReg, /*TempRegID*/35, /*TypeID*/GILLT_s64, |
| 25663 | GIR_MakeTempReg, /*TempRegID*/36, /*TypeID*/GILLT_s64, |
| 25664 | GIR_MakeTempReg, /*TempRegID*/37, /*TypeID*/GILLT_s32, |
| 25665 | GIR_MakeTempReg, /*TempRegID*/38, /*TypeID*/GILLT_s32, |
| 25666 | GIR_MakeTempReg, /*TempRegID*/39, /*TypeID*/GILLT_s64, |
| 25667 | GIR_MakeTempReg, /*TempRegID*/40, /*TypeID*/GILLT_s64, |
| 25668 | GIR_MakeTempReg, /*TempRegID*/41, /*TypeID*/GILLT_s64, |
| 25669 | GIR_MakeTempReg, /*TempRegID*/42, /*TypeID*/GILLT_s64, |
| 25670 | GIR_MakeTempReg, /*TempRegID*/43, /*TypeID*/GILLT_s64, |
| 25671 | GIR_MakeTempReg, /*TempRegID*/44, /*TypeID*/GILLT_s64, |
| 25672 | GIR_MakeTempReg, /*TempRegID*/45, /*TypeID*/GILLT_s64, |
| 25673 | GIR_MakeTempReg, /*TempRegID*/46, /*TypeID*/GILLT_s64, |
| 25674 | GIR_MakeTempReg, /*TempRegID*/47, /*TypeID*/GILLT_s64, |
| 25675 | GIR_MakeTempReg, /*TempRegID*/48, /*TypeID*/GILLT_s64, |
| 25676 | GIR_MakeTempReg, /*TempRegID*/49, /*TypeID*/GILLT_s32, |
| 25677 | GIR_MakeTempReg, /*TempRegID*/50, /*TypeID*/GILLT_s32, |
| 25678 | GIR_MakeTempReg, /*TempRegID*/51, /*TypeID*/GILLT_s64, |
| 25679 | GIR_MakeTempReg, /*TempRegID*/52, /*TypeID*/GILLT_s64, |
| 25680 | GIR_MakeTempReg, /*TempRegID*/53, /*TypeID*/GILLT_s64, |
| 25681 | GIR_MakeTempReg, /*TempRegID*/54, /*TypeID*/GILLT_s64, |
| 25682 | GIR_MakeTempReg, /*TempRegID*/55, /*TypeID*/GILLT_s64, |
| 25683 | GIR_MakeTempReg, /*TempRegID*/56, /*TypeID*/GILLT_s64, |
| 25684 | GIR_MakeTempReg, /*TempRegID*/57, /*TypeID*/GILLT_s64, |
| 25685 | GIR_MakeTempReg, /*TempRegID*/58, /*TypeID*/GILLT_s32, |
| 25686 | GIR_MakeTempReg, /*TempRegID*/59, /*TypeID*/GILLT_s32, |
| 25687 | GIR_MakeTempReg, /*TempRegID*/60, /*TypeID*/GILLT_s64, |
| 25688 | GIR_MakeTempReg, /*TempRegID*/61, /*TypeID*/GILLT_s64, |
| 25689 | GIR_MakeTempReg, /*TempRegID*/62, /*TypeID*/GILLT_s64, |
| 25690 | GIR_MakeTempReg, /*TempRegID*/63, /*TypeID*/GILLT_s64, |
| 25691 | GIR_MakeTempReg, /*TempRegID*/64, /*TypeID*/GILLT_s64, |
| 25692 | GIR_MakeTempReg, /*TempRegID*/65, /*TypeID*/GILLT_s32, |
| 25693 | GIR_MakeTempReg, /*TempRegID*/66, /*TypeID*/GILLT_s32, |
| 25694 | GIR_MakeTempReg, /*TempRegID*/67, /*TypeID*/GILLT_s64, |
| 25695 | GIR_MakeTempReg, /*TempRegID*/68, /*TypeID*/GILLT_s64, |
| 25696 | GIR_MakeTempReg, /*TempRegID*/69, /*TypeID*/GILLT_s64, |
| 25697 | GIR_MakeTempReg, /*TempRegID*/70, /*TypeID*/GILLT_s64, |
| 25698 | GIR_MakeTempReg, /*TempRegID*/71, /*TypeID*/GILLT_s64, |
| 25699 | GIR_MakeTempReg, /*TempRegID*/72, /*TypeID*/GILLT_s32, |
| 25700 | GIR_MakeTempReg, /*TempRegID*/73, /*TypeID*/GILLT_s32, |
| 25701 | GIR_MakeTempReg, /*TempRegID*/74, /*TypeID*/GILLT_s64, |
| 25702 | GIR_MakeTempReg, /*TempRegID*/75, /*TypeID*/GILLT_s64, |
| 25703 | GIR_MakeTempReg, /*TempRegID*/76, /*TypeID*/GILLT_s64, |
| 25704 | GIR_MakeTempReg, /*TempRegID*/77, /*TypeID*/GILLT_s64, |
| 25705 | GIR_MakeTempReg, /*TempRegID*/78, /*TypeID*/GILLT_s64, |
| 25706 | GIR_MakeTempReg, /*TempRegID*/79, /*TypeID*/GILLT_s64, |
| 25707 | GIR_MakeTempReg, /*TempRegID*/80, /*TypeID*/GILLT_s64, |
| 25708 | GIR_MakeTempReg, /*TempRegID*/81, /*TypeID*/GILLT_s64, |
| 25709 | GIR_MakeTempReg, /*TempRegID*/82, /*TypeID*/GILLT_s64, |
| 25710 | GIR_MakeTempReg, /*TempRegID*/83, /*TypeID*/GILLT_s64, |
| 25711 | GIR_MakeTempReg, /*TempRegID*/84, /*TypeID*/GILLT_s64, |
| 25712 | GIR_MakeTempReg, /*TempRegID*/85, /*TypeID*/GILLT_s64, |
| 25713 | GIR_MakeTempReg, /*TempRegID*/86, /*TypeID*/GILLT_s64, |
| 25714 | GIR_MakeTempReg, /*TempRegID*/87, /*TypeID*/GILLT_s32, |
| 25715 | GIR_MakeTempReg, /*TempRegID*/88, /*TypeID*/GILLT_s32, |
| 25716 | GIR_MakeTempReg, /*TempRegID*/89, /*TypeID*/GILLT_s64, |
| 25717 | GIR_MakeTempReg, /*TempRegID*/90, /*TypeID*/GILLT_s64, |
| 25718 | GIR_MakeTempReg, /*TempRegID*/91, /*TypeID*/GILLT_s64, |
| 25719 | GIR_MakeTempReg, /*TempRegID*/92, /*TypeID*/GILLT_s64, |
| 25720 | GIR_MakeTempReg, /*TempRegID*/93, /*TypeID*/GILLT_s64, |
| 25721 | GIR_MakeTempReg, /*TempRegID*/94, /*TypeID*/GILLT_s64, |
| 25722 | GIR_MakeTempReg, /*TempRegID*/95, /*TypeID*/GILLT_s64, |
| 25723 | GIR_MakeTempReg, /*TempRegID*/96, /*TypeID*/GILLT_s32, |
| 25724 | GIR_MakeTempReg, /*TempRegID*/97, /*TypeID*/GILLT_s32, |
| 25725 | GIR_MakeTempReg, /*TempRegID*/98, /*TypeID*/GILLT_s64, |
| 25726 | GIR_MakeTempReg, /*TempRegID*/99, /*TypeID*/GILLT_s64, |
| 25727 | GIR_MakeTempReg, /*TempRegID*/100, /*TypeID*/GILLT_s64, |
| 25728 | GIR_MakeTempReg, /*TempRegID*/101, /*TypeID*/GILLT_s64, |
| 25729 | GIR_MakeTempReg, /*TempRegID*/102, /*TypeID*/GILLT_s64, |
| 25730 | GIR_MakeTempReg, /*TempRegID*/103, /*TypeID*/GILLT_s32, |
| 25731 | GIR_MakeTempReg, /*TempRegID*/104, /*TypeID*/GILLT_s32, |
| 25732 | GIR_MakeTempReg, /*TempRegID*/105, /*TypeID*/GILLT_s64, |
| 25733 | GIR_MakeTempReg, /*TempRegID*/106, /*TypeID*/GILLT_s64, |
| 25734 | GIR_MakeTempReg, /*TempRegID*/107, /*TypeID*/GILLT_s64, |
| 25735 | GIR_MakeTempReg, /*TempRegID*/108, /*TypeID*/GILLT_s64, |
| 25736 | GIR_MakeTempReg, /*TempRegID*/109, /*TypeID*/GILLT_s64, |
| 25737 | GIR_MakeTempReg, /*TempRegID*/110, /*TypeID*/GILLT_s64, |
| 25738 | GIR_MakeTempReg, /*TempRegID*/111, /*TypeID*/GILLT_s64, |
| 25739 | GIR_MakeTempReg, /*TempRegID*/112, /*TypeID*/GILLT_s64, |
| 25740 | GIR_MakeTempReg, /*TempRegID*/113, /*TypeID*/GILLT_s64, |
| 25741 | GIR_MakeTempReg, /*TempRegID*/114, /*TypeID*/GILLT_s64, |
| 25742 | GIR_MakeTempReg, /*TempRegID*/115, /*TypeID*/GILLT_s32, |
| 25743 | GIR_MakeTempReg, /*TempRegID*/116, /*TypeID*/GILLT_s32, |
| 25744 | GIR_MakeTempReg, /*TempRegID*/117, /*TypeID*/GILLT_s64, |
| 25745 | GIR_MakeTempReg, /*TempRegID*/118, /*TypeID*/GILLT_s64, |
| 25746 | GIR_MakeTempReg, /*TempRegID*/119, /*TypeID*/GILLT_s64, |
| 25747 | GIR_MakeTempReg, /*TempRegID*/120, /*TypeID*/GILLT_s64, |
| 25748 | GIR_MakeTempReg, /*TempRegID*/121, /*TypeID*/GILLT_s64, |
| 25749 | GIR_MakeTempReg, /*TempRegID*/122, /*TypeID*/GILLT_s64, |
| 25750 | GIR_MakeTempReg, /*TempRegID*/123, /*TypeID*/GILLT_s64, |
| 25751 | GIR_MakeTempReg, /*TempRegID*/124, /*TypeID*/GILLT_s32, |
| 25752 | GIR_MakeTempReg, /*TempRegID*/125, /*TypeID*/GILLT_s32, |
| 25753 | GIR_MakeTempReg, /*TempRegID*/126, /*TypeID*/GILLT_s64, |
| 25754 | GIR_MakeTempReg, /*TempRegID*/127, /*TypeID*/GILLT_s64, |
| 25755 | GIR_MakeTempReg, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25756 | GIR_MakeTempReg, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25757 | GIR_MakeTempReg, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25758 | GIR_MakeTempReg, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 25759 | GIR_MakeTempReg, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 25760 | GIR_MakeTempReg, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25761 | GIR_MakeTempReg, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25762 | GIR_MakeTempReg, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25763 | GIR_MakeTempReg, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25764 | GIR_MakeTempReg, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 25765 | GIR_MakeTempReg, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 25766 | GIR_MakeTempReg, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 25767 | GIR_BuildMI, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25768 | GIR_AddTempRegister, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25769 | GIR_AddImm, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 25770 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 140(*/0x8C, 0x01/*)*/, |
| 25771 | GIR_BuildMI, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25772 | GIR_AddTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25773 | GIR_AddSimpleTempRegister, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*TempRegID*//* 139(*/0x8B, 0x01/*)*/, |
| 25774 | GIR_AddImm, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 25775 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 139(*/0x8B, 0x01/*)*/, |
| 25776 | GIR_BuildMI, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25777 | GIR_AddTempRegister, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25778 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 138(*/0x8A, 0x01/*)*/, |
| 25779 | GIR_BuildMI, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 25780 | GIR_AddTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25781 | GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 137(*/0x89, 0x01/*)*/, |
| 25782 | GIR_AddSimpleTempRegister, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*TempRegID*//* 138(*/0x8A, 0x01/*)*/, |
| 25783 | GIR_AddImm8, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Imm*/1, |
| 25784 | GIR_ConstrainOperandRC, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25785 | GIR_ConstrainOperandRC, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25786 | GIR_ConstrainOperandRC, /*InsnID*//* 137(*/0x89, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 25787 | GIR_BuildMI, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25788 | GIR_AddTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25789 | GIR_AddSimpleTempRegister, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*TempRegID*//* 136(*/0x88, 0x01/*)*/, |
| 25790 | GIR_AddImm8, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Imm*/32, |
| 25791 | GIR_AddImm8, /*InsnID*//* 136(*/0x88, 0x01/*)*/, /*Imm*/31, |
| 25792 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 136(*/0x88, 0x01/*)*/, |
| 25793 | GIR_BuildMI, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 25794 | GIR_AddTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25795 | GIR_AddSimpleTempRegister, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*TempRegID*//* 135(*/0x87, 0x01/*)*/, |
| 25796 | GIR_AddImm, /*InsnID*//* 135(*/0x87, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 25797 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 135(*/0x87, 0x01/*)*/, |
| 25798 | GIR_BuildMI, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 25799 | GIR_AddTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25800 | GIR_AddSimpleTempRegister, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*TempRegID*//* 134(*/0x86, 0x01/*)*/, |
| 25801 | GIR_AddImm, /*InsnID*//* 134(*/0x86, 0x01/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 25802 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 134(*/0x86, 0x01/*)*/, |
| 25803 | GIR_BuildMI, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25804 | GIR_AddTempRegister, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25805 | GIR_AddImm, /*InsnID*//* 133(*/0x85, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 25806 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 133(*/0x85, 0x01/*)*/, |
| 25807 | GIR_BuildMI, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25808 | GIR_AddTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25809 | GIR_AddSimpleTempRegister, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*TempRegID*//* 132(*/0x84, 0x01/*)*/, |
| 25810 | GIR_AddImm, /*InsnID*//* 132(*/0x84, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 25811 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 132(*/0x84, 0x01/*)*/, |
| 25812 | GIR_BuildMI, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25813 | GIR_AddTempRegister, /*InsnID*//* 131(*/0x83, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25814 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 131(*/0x83, 0x01/*)*/, |
| 25815 | GIR_BuildMI, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 25816 | GIR_AddTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25817 | GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 130(*/0x82, 0x01/*)*/, |
| 25818 | GIR_AddSimpleTempRegister, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*TempRegID*//* 131(*/0x83, 0x01/*)*/, |
| 25819 | GIR_AddImm8, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Imm*/1, |
| 25820 | GIR_ConstrainOperandRC, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25821 | GIR_ConstrainOperandRC, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25822 | GIR_ConstrainOperandRC, /*InsnID*//* 130(*/0x82, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 25823 | GIR_BuildMI, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25824 | GIR_AddTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25825 | GIR_AddSimpleTempRegister, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*TempRegID*//* 129(*/0x81, 0x01/*)*/, |
| 25826 | GIR_AddImm8, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Imm*/32, |
| 25827 | GIR_AddImm8, /*InsnID*//* 129(*/0x81, 0x01/*)*/, /*Imm*/31, |
| 25828 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 129(*/0x81, 0x01/*)*/, |
| 25829 | GIR_BuildMI, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 25830 | GIR_AddTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*/127, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25831 | GIR_AddSimpleTempRegister, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*TempRegID*//* 128(*/0x80, 0x01/*)*/, |
| 25832 | GIR_AddImm, /*InsnID*//* 128(*/0x80, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 25833 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 128(*/0x80, 0x01/*)*/, |
| 25834 | GIR_BuildMI, /*InsnID*/127, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 25835 | GIR_AddTempRegister, /*InsnID*/127, /*TempRegID*/126, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25836 | GIR_AddSimpleTempRegister, /*InsnID*/127, /*TempRegID*/127, |
| 25837 | GIR_AddImm, /*InsnID*/127, /*Imm*/GIMT_Encode8(52428), |
| 25838 | GIR_ConstrainSelectedInstOperands, /*InsnID*/127, |
| 25839 | GIR_BuildMI, /*InsnID*/126, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25840 | GIR_AddTempRegister, /*InsnID*/126, /*TempRegID*/125, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25841 | GIR_AddImm, /*InsnID*/126, /*Imm*/GIMT_Encode8(43690), |
| 25842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/126, |
| 25843 | GIR_BuildMI, /*InsnID*/125, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25844 | GIR_AddTempRegister, /*InsnID*/125, /*TempRegID*/124, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25845 | GIR_AddSimpleTempRegister, /*InsnID*/125, /*TempRegID*/125, |
| 25846 | GIR_AddImm, /*InsnID*/125, /*Imm*/GIMT_Encode8(43690), |
| 25847 | GIR_ConstrainSelectedInstOperands, /*InsnID*/125, |
| 25848 | GIR_BuildMI, /*InsnID*/124, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25849 | GIR_AddTempRegister, /*InsnID*/124, /*TempRegID*/123, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25850 | GIR_ConstrainSelectedInstOperands, /*InsnID*/124, |
| 25851 | GIR_BuildMI, /*InsnID*/123, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 25852 | GIR_AddTempRegister, /*InsnID*/123, /*TempRegID*/122, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25853 | GIR_AddSimpleTempRegister, /*InsnID*/123, /*TempRegID*/123, |
| 25854 | GIR_AddSimpleTempRegister, /*InsnID*/123, /*TempRegID*/124, |
| 25855 | GIR_AddImm8, /*InsnID*/123, /*Imm*/1, |
| 25856 | GIR_ConstrainOperandRC, /*InsnID*/123, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25857 | GIR_ConstrainOperandRC, /*InsnID*/123, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25858 | GIR_ConstrainOperandRC, /*InsnID*/123, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 25859 | GIR_BuildMI, /*InsnID*/122, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25860 | GIR_AddTempRegister, /*InsnID*/122, /*TempRegID*/121, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25861 | GIR_AddSimpleTempRegister, /*InsnID*/122, /*TempRegID*/122, |
| 25862 | GIR_AddImm8, /*InsnID*/122, /*Imm*/32, |
| 25863 | GIR_AddImm8, /*InsnID*/122, /*Imm*/31, |
| 25864 | GIR_ConstrainSelectedInstOperands, /*InsnID*/122, |
| 25865 | GIR_BuildMI, /*InsnID*/121, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 25866 | GIR_AddTempRegister, /*InsnID*/121, /*TempRegID*/120, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25867 | GIR_AddSimpleTempRegister, /*InsnID*/121, /*TempRegID*/121, |
| 25868 | GIR_AddImm, /*InsnID*/121, /*Imm*/GIMT_Encode8(43690), |
| 25869 | GIR_ConstrainSelectedInstOperands, /*InsnID*/121, |
| 25870 | GIR_BuildMI, /*InsnID*/120, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 25871 | GIR_AddTempRegister, /*InsnID*/120, /*TempRegID*/119, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25872 | GIR_AddSimpleTempRegister, /*InsnID*/120, /*TempRegID*/120, |
| 25873 | GIR_AddImm, /*InsnID*/120, /*Imm*/GIMT_Encode8(43690), |
| 25874 | GIR_ConstrainSelectedInstOperands, /*InsnID*/120, |
| 25875 | GIR_BuildMI, /*InsnID*/119, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25876 | GIR_AddTempRegister, /*InsnID*/119, /*TempRegID*/118, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25877 | GIR_Copy, /*NewInsnID*/119, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25878 | GIR_AddImm8, /*InsnID*/119, /*Imm*/1, |
| 25879 | GIR_AddImm8, /*InsnID*/119, /*Imm*/62, |
| 25880 | GIR_ConstrainSelectedInstOperands, /*InsnID*/119, |
| 25881 | GIR_BuildMI, /*InsnID*/118, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 25882 | GIR_AddTempRegister, /*InsnID*/118, /*TempRegID*/117, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25883 | GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/118, |
| 25884 | GIR_AddSimpleTempRegister, /*InsnID*/118, /*TempRegID*/119, |
| 25885 | GIR_ConstrainSelectedInstOperands, /*InsnID*/118, |
| 25886 | GIR_BuildMI, /*InsnID*/117, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25887 | GIR_AddTempRegister, /*InsnID*/117, /*TempRegID*/116, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25888 | GIR_AddImm, /*InsnID*/117, /*Imm*/GIMT_Encode8(21845), |
| 25889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/117, |
| 25890 | GIR_BuildMI, /*InsnID*/116, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25891 | GIR_AddTempRegister, /*InsnID*/116, /*TempRegID*/115, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25892 | GIR_AddSimpleTempRegister, /*InsnID*/116, /*TempRegID*/116, |
| 25893 | GIR_AddImm, /*InsnID*/116, /*Imm*/GIMT_Encode8(21845), |
| 25894 | GIR_ConstrainSelectedInstOperands, /*InsnID*/116, |
| 25895 | GIR_BuildMI, /*InsnID*/115, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25896 | GIR_AddTempRegister, /*InsnID*/115, /*TempRegID*/114, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25897 | GIR_ConstrainSelectedInstOperands, /*InsnID*/115, |
| 25898 | GIR_BuildMI, /*InsnID*/114, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 25899 | GIR_AddTempRegister, /*InsnID*/114, /*TempRegID*/113, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25900 | GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/114, |
| 25901 | GIR_AddSimpleTempRegister, /*InsnID*/114, /*TempRegID*/115, |
| 25902 | GIR_AddImm8, /*InsnID*/114, /*Imm*/1, |
| 25903 | GIR_ConstrainOperandRC, /*InsnID*/114, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25904 | GIR_ConstrainOperandRC, /*InsnID*/114, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25905 | GIR_ConstrainOperandRC, /*InsnID*/114, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 25906 | GIR_BuildMI, /*InsnID*/113, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25907 | GIR_AddTempRegister, /*InsnID*/113, /*TempRegID*/112, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25908 | GIR_AddSimpleTempRegister, /*InsnID*/113, /*TempRegID*/113, |
| 25909 | GIR_AddImm8, /*InsnID*/113, /*Imm*/32, |
| 25910 | GIR_AddImm8, /*InsnID*/113, /*Imm*/31, |
| 25911 | GIR_ConstrainSelectedInstOperands, /*InsnID*/113, |
| 25912 | GIR_BuildMI, /*InsnID*/112, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 25913 | GIR_AddTempRegister, /*InsnID*/112, /*TempRegID*/111, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25914 | GIR_AddSimpleTempRegister, /*InsnID*/112, /*TempRegID*/112, |
| 25915 | GIR_AddImm, /*InsnID*/112, /*Imm*/GIMT_Encode8(21845), |
| 25916 | GIR_ConstrainSelectedInstOperands, /*InsnID*/112, |
| 25917 | GIR_BuildMI, /*InsnID*/111, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 25918 | GIR_AddTempRegister, /*InsnID*/111, /*TempRegID*/110, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25919 | GIR_AddSimpleTempRegister, /*InsnID*/111, /*TempRegID*/111, |
| 25920 | GIR_AddImm, /*InsnID*/111, /*Imm*/GIMT_Encode8(21845), |
| 25921 | GIR_ConstrainSelectedInstOperands, /*InsnID*/111, |
| 25922 | GIR_BuildMI, /*InsnID*/110, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 25923 | GIR_AddTempRegister, /*InsnID*/110, /*TempRegID*/109, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25924 | GIR_Copy, /*NewInsnID*/110, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 25925 | GIR_AddImm8, /*InsnID*/110, /*Imm*/63, |
| 25926 | GIR_AddImm8, /*InsnID*/110, /*Imm*/1, |
| 25927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/110, |
| 25928 | GIR_BuildMI, /*InsnID*/109, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 25929 | GIR_AddTempRegister, /*InsnID*/109, /*TempRegID*/108, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25930 | GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/109, |
| 25931 | GIR_AddSimpleTempRegister, /*InsnID*/109, /*TempRegID*/110, |
| 25932 | GIR_ConstrainSelectedInstOperands, /*InsnID*/109, |
| 25933 | GIR_BuildMI, /*InsnID*/108, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 25934 | GIR_AddTempRegister, /*InsnID*/108, /*TempRegID*/107, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25935 | GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/108, |
| 25936 | GIR_AddSimpleTempRegister, /*InsnID*/108, /*TempRegID*/117, |
| 25937 | GIR_ConstrainSelectedInstOperands, /*InsnID*/108, |
| 25938 | GIR_BuildMI, /*InsnID*/107, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25939 | GIR_AddTempRegister, /*InsnID*/107, /*TempRegID*/106, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25940 | GIR_AddSimpleTempRegister, /*InsnID*/107, /*TempRegID*/107, |
| 25941 | GIR_AddImm8, /*InsnID*/107, /*Imm*/2, |
| 25942 | GIR_AddImm8, /*InsnID*/107, /*Imm*/61, |
| 25943 | GIR_ConstrainSelectedInstOperands, /*InsnID*/107, |
| 25944 | GIR_BuildMI, /*InsnID*/106, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 25945 | GIR_AddTempRegister, /*InsnID*/106, /*TempRegID*/105, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25946 | GIR_AddSimpleTempRegister, /*InsnID*/106, /*TempRegID*/106, |
| 25947 | GIR_AddSimpleTempRegister, /*InsnID*/106, /*TempRegID*/126, |
| 25948 | GIR_ConstrainSelectedInstOperands, /*InsnID*/106, |
| 25949 | GIR_BuildMI, /*InsnID*/105, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25950 | GIR_AddTempRegister, /*InsnID*/105, /*TempRegID*/104, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25951 | GIR_AddImm, /*InsnID*/105, /*Imm*/GIMT_Encode8(13107), |
| 25952 | GIR_ConstrainSelectedInstOperands, /*InsnID*/105, |
| 25953 | GIR_BuildMI, /*InsnID*/104, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25954 | GIR_AddTempRegister, /*InsnID*/104, /*TempRegID*/103, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25955 | GIR_AddSimpleTempRegister, /*InsnID*/104, /*TempRegID*/104, |
| 25956 | GIR_AddImm, /*InsnID*/104, /*Imm*/GIMT_Encode8(13107), |
| 25957 | GIR_ConstrainSelectedInstOperands, /*InsnID*/104, |
| 25958 | GIR_BuildMI, /*InsnID*/103, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25959 | GIR_AddTempRegister, /*InsnID*/103, /*TempRegID*/102, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25960 | GIR_ConstrainSelectedInstOperands, /*InsnID*/103, |
| 25961 | GIR_BuildMI, /*InsnID*/102, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 25962 | GIR_AddTempRegister, /*InsnID*/102, /*TempRegID*/101, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25963 | GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/102, |
| 25964 | GIR_AddSimpleTempRegister, /*InsnID*/102, /*TempRegID*/103, |
| 25965 | GIR_AddImm8, /*InsnID*/102, /*Imm*/1, |
| 25966 | GIR_ConstrainOperandRC, /*InsnID*/102, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25967 | GIR_ConstrainOperandRC, /*InsnID*/102, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 25968 | GIR_ConstrainOperandRC, /*InsnID*/102, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 25969 | GIR_BuildMI, /*InsnID*/101, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 25970 | GIR_AddTempRegister, /*InsnID*/101, /*TempRegID*/100, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25971 | GIR_AddSimpleTempRegister, /*InsnID*/101, /*TempRegID*/101, |
| 25972 | GIR_AddImm8, /*InsnID*/101, /*Imm*/32, |
| 25973 | GIR_AddImm8, /*InsnID*/101, /*Imm*/31, |
| 25974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/101, |
| 25975 | GIR_BuildMI, /*InsnID*/100, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 25976 | GIR_AddTempRegister, /*InsnID*/100, /*TempRegID*/99, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25977 | GIR_AddSimpleTempRegister, /*InsnID*/100, /*TempRegID*/100, |
| 25978 | GIR_AddImm, /*InsnID*/100, /*Imm*/GIMT_Encode8(13107), |
| 25979 | GIR_ConstrainSelectedInstOperands, /*InsnID*/100, |
| 25980 | GIR_BuildMI, /*InsnID*/99, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 25981 | GIR_AddTempRegister, /*InsnID*/99, /*TempRegID*/98, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25982 | GIR_AddSimpleTempRegister, /*InsnID*/99, /*TempRegID*/99, |
| 25983 | GIR_AddImm, /*InsnID*/99, /*Imm*/GIMT_Encode8(13107), |
| 25984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/99, |
| 25985 | GIR_BuildMI, /*InsnID*/98, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 25986 | GIR_AddTempRegister, /*InsnID*/98, /*TempRegID*/97, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25987 | GIR_AddImm, /*InsnID*/98, /*Imm*/GIMT_Encode8(43690), |
| 25988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/98, |
| 25989 | GIR_BuildMI, /*InsnID*/97, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 25990 | GIR_AddTempRegister, /*InsnID*/97, /*TempRegID*/96, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25991 | GIR_AddSimpleTempRegister, /*InsnID*/97, /*TempRegID*/97, |
| 25992 | GIR_AddImm, /*InsnID*/97, /*Imm*/GIMT_Encode8(43690), |
| 25993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/97, |
| 25994 | GIR_BuildMI, /*InsnID*/96, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25995 | GIR_AddTempRegister, /*InsnID*/96, /*TempRegID*/95, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25996 | GIR_ConstrainSelectedInstOperands, /*InsnID*/96, |
| 25997 | GIR_BuildMI, /*InsnID*/95, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 25998 | GIR_AddTempRegister, /*InsnID*/95, /*TempRegID*/94, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 25999 | GIR_AddSimpleTempRegister, /*InsnID*/95, /*TempRegID*/95, |
| 26000 | GIR_AddSimpleTempRegister, /*InsnID*/95, /*TempRegID*/96, |
| 26001 | GIR_AddImm8, /*InsnID*/95, /*Imm*/1, |
| 26002 | GIR_ConstrainOperandRC, /*InsnID*/95, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26003 | GIR_ConstrainOperandRC, /*InsnID*/95, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26004 | GIR_ConstrainOperandRC, /*InsnID*/95, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26005 | GIR_BuildMI, /*InsnID*/94, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26006 | GIR_AddTempRegister, /*InsnID*/94, /*TempRegID*/93, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26007 | GIR_AddSimpleTempRegister, /*InsnID*/94, /*TempRegID*/94, |
| 26008 | GIR_AddImm8, /*InsnID*/94, /*Imm*/32, |
| 26009 | GIR_AddImm8, /*InsnID*/94, /*Imm*/31, |
| 26010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/94, |
| 26011 | GIR_BuildMI, /*InsnID*/93, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26012 | GIR_AddTempRegister, /*InsnID*/93, /*TempRegID*/92, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26013 | GIR_AddSimpleTempRegister, /*InsnID*/93, /*TempRegID*/93, |
| 26014 | GIR_AddImm, /*InsnID*/93, /*Imm*/GIMT_Encode8(43690), |
| 26015 | GIR_ConstrainSelectedInstOperands, /*InsnID*/93, |
| 26016 | GIR_BuildMI, /*InsnID*/92, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26017 | GIR_AddTempRegister, /*InsnID*/92, /*TempRegID*/91, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26018 | GIR_AddSimpleTempRegister, /*InsnID*/92, /*TempRegID*/92, |
| 26019 | GIR_AddImm, /*InsnID*/92, /*Imm*/GIMT_Encode8(43690), |
| 26020 | GIR_ConstrainSelectedInstOperands, /*InsnID*/92, |
| 26021 | GIR_BuildMI, /*InsnID*/91, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26022 | GIR_AddTempRegister, /*InsnID*/91, /*TempRegID*/90, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26023 | GIR_Copy, /*NewInsnID*/91, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26024 | GIR_AddImm8, /*InsnID*/91, /*Imm*/1, |
| 26025 | GIR_AddImm8, /*InsnID*/91, /*Imm*/62, |
| 26026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/91, |
| 26027 | GIR_BuildMI, /*InsnID*/90, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26028 | GIR_AddTempRegister, /*InsnID*/90, /*TempRegID*/89, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26029 | GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/90, |
| 26030 | GIR_AddSimpleTempRegister, /*InsnID*/90, /*TempRegID*/91, |
| 26031 | GIR_ConstrainSelectedInstOperands, /*InsnID*/90, |
| 26032 | GIR_BuildMI, /*InsnID*/89, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26033 | GIR_AddTempRegister, /*InsnID*/89, /*TempRegID*/88, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26034 | GIR_AddImm, /*InsnID*/89, /*Imm*/GIMT_Encode8(21845), |
| 26035 | GIR_ConstrainSelectedInstOperands, /*InsnID*/89, |
| 26036 | GIR_BuildMI, /*InsnID*/88, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26037 | GIR_AddTempRegister, /*InsnID*/88, /*TempRegID*/87, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26038 | GIR_AddSimpleTempRegister, /*InsnID*/88, /*TempRegID*/88, |
| 26039 | GIR_AddImm, /*InsnID*/88, /*Imm*/GIMT_Encode8(21845), |
| 26040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/88, |
| 26041 | GIR_BuildMI, /*InsnID*/87, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26042 | GIR_AddTempRegister, /*InsnID*/87, /*TempRegID*/86, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/87, |
| 26044 | GIR_BuildMI, /*InsnID*/86, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26045 | GIR_AddTempRegister, /*InsnID*/86, /*TempRegID*/85, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26046 | GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/86, |
| 26047 | GIR_AddSimpleTempRegister, /*InsnID*/86, /*TempRegID*/87, |
| 26048 | GIR_AddImm8, /*InsnID*/86, /*Imm*/1, |
| 26049 | GIR_ConstrainOperandRC, /*InsnID*/86, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26050 | GIR_ConstrainOperandRC, /*InsnID*/86, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26051 | GIR_ConstrainOperandRC, /*InsnID*/86, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26052 | GIR_BuildMI, /*InsnID*/85, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26053 | GIR_AddTempRegister, /*InsnID*/85, /*TempRegID*/84, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26054 | GIR_AddSimpleTempRegister, /*InsnID*/85, /*TempRegID*/85, |
| 26055 | GIR_AddImm8, /*InsnID*/85, /*Imm*/32, |
| 26056 | GIR_AddImm8, /*InsnID*/85, /*Imm*/31, |
| 26057 | GIR_ConstrainSelectedInstOperands, /*InsnID*/85, |
| 26058 | GIR_BuildMI, /*InsnID*/84, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26059 | GIR_AddTempRegister, /*InsnID*/84, /*TempRegID*/83, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26060 | GIR_AddSimpleTempRegister, /*InsnID*/84, /*TempRegID*/84, |
| 26061 | GIR_AddImm, /*InsnID*/84, /*Imm*/GIMT_Encode8(21845), |
| 26062 | GIR_ConstrainSelectedInstOperands, /*InsnID*/84, |
| 26063 | GIR_BuildMI, /*InsnID*/83, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26064 | GIR_AddTempRegister, /*InsnID*/83, /*TempRegID*/82, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26065 | GIR_AddSimpleTempRegister, /*InsnID*/83, /*TempRegID*/83, |
| 26066 | GIR_AddImm, /*InsnID*/83, /*Imm*/GIMT_Encode8(21845), |
| 26067 | GIR_ConstrainSelectedInstOperands, /*InsnID*/83, |
| 26068 | GIR_BuildMI, /*InsnID*/82, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26069 | GIR_AddTempRegister, /*InsnID*/82, /*TempRegID*/81, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26070 | GIR_Copy, /*NewInsnID*/82, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26071 | GIR_AddImm8, /*InsnID*/82, /*Imm*/63, |
| 26072 | GIR_AddImm8, /*InsnID*/82, /*Imm*/1, |
| 26073 | GIR_ConstrainSelectedInstOperands, /*InsnID*/82, |
| 26074 | GIR_BuildMI, /*InsnID*/81, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26075 | GIR_AddTempRegister, /*InsnID*/81, /*TempRegID*/80, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26076 | GIR_AddSimpleTempRegister, /*InsnID*/81, /*TempRegID*/81, |
| 26077 | GIR_AddSimpleTempRegister, /*InsnID*/81, /*TempRegID*/82, |
| 26078 | GIR_ConstrainSelectedInstOperands, /*InsnID*/81, |
| 26079 | GIR_BuildMI, /*InsnID*/80, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26080 | GIR_AddTempRegister, /*InsnID*/80, /*TempRegID*/79, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26081 | GIR_AddSimpleTempRegister, /*InsnID*/80, /*TempRegID*/80, |
| 26082 | GIR_AddSimpleTempRegister, /*InsnID*/80, /*TempRegID*/89, |
| 26083 | GIR_ConstrainSelectedInstOperands, /*InsnID*/80, |
| 26084 | GIR_BuildMI, /*InsnID*/79, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26085 | GIR_AddTempRegister, /*InsnID*/79, /*TempRegID*/78, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26086 | GIR_AddSimpleTempRegister, /*InsnID*/79, /*TempRegID*/79, |
| 26087 | GIR_AddImm8, /*InsnID*/79, /*Imm*/62, |
| 26088 | GIR_AddImm8, /*InsnID*/79, /*Imm*/2, |
| 26089 | GIR_ConstrainSelectedInstOperands, /*InsnID*/79, |
| 26090 | GIR_BuildMI, /*InsnID*/78, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26091 | GIR_AddTempRegister, /*InsnID*/78, /*TempRegID*/77, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26092 | GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/78, |
| 26093 | GIR_AddSimpleTempRegister, /*InsnID*/78, /*TempRegID*/98, |
| 26094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/78, |
| 26095 | GIR_BuildMI, /*InsnID*/77, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26096 | GIR_AddTempRegister, /*InsnID*/77, /*TempRegID*/76, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26097 | GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/77, |
| 26098 | GIR_AddSimpleTempRegister, /*InsnID*/77, /*TempRegID*/105, |
| 26099 | GIR_ConstrainSelectedInstOperands, /*InsnID*/77, |
| 26100 | GIR_BuildMI, /*InsnID*/76, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26101 | GIR_AddTempRegister, /*InsnID*/76, /*TempRegID*/75, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26102 | GIR_AddSimpleTempRegister, /*InsnID*/76, /*TempRegID*/76, |
| 26103 | GIR_AddImm8, /*InsnID*/76, /*Imm*/4, |
| 26104 | GIR_AddImm8, /*InsnID*/76, /*Imm*/59, |
| 26105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/76, |
| 26106 | GIR_BuildMI, /*InsnID*/75, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26107 | GIR_AddTempRegister, /*InsnID*/75, /*TempRegID*/74, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26108 | GIR_AddSimpleTempRegister, /*InsnID*/75, /*TempRegID*/75, |
| 26109 | GIR_AddSimpleTempRegister, /*InsnID*/75, /*TempRegID*//* 133(*/0x85, 0x01/*)*/, |
| 26110 | GIR_ConstrainSelectedInstOperands, /*InsnID*/75, |
| 26111 | GIR_BuildMI, /*InsnID*/74, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26112 | GIR_AddTempRegister, /*InsnID*/74, /*TempRegID*/73, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26113 | GIR_AddImm, /*InsnID*/74, /*Imm*/GIMT_Encode8(3855), |
| 26114 | GIR_ConstrainSelectedInstOperands, /*InsnID*/74, |
| 26115 | GIR_BuildMI, /*InsnID*/73, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26116 | GIR_AddTempRegister, /*InsnID*/73, /*TempRegID*/72, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26117 | GIR_AddSimpleTempRegister, /*InsnID*/73, /*TempRegID*/73, |
| 26118 | GIR_AddImm, /*InsnID*/73, /*Imm*/GIMT_Encode8(3855), |
| 26119 | GIR_ConstrainSelectedInstOperands, /*InsnID*/73, |
| 26120 | GIR_BuildMI, /*InsnID*/72, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26121 | GIR_AddTempRegister, /*InsnID*/72, /*TempRegID*/71, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26122 | GIR_ConstrainSelectedInstOperands, /*InsnID*/72, |
| 26123 | GIR_BuildMI, /*InsnID*/71, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26124 | GIR_AddTempRegister, /*InsnID*/71, /*TempRegID*/70, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26125 | GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/71, |
| 26126 | GIR_AddSimpleTempRegister, /*InsnID*/71, /*TempRegID*/72, |
| 26127 | GIR_AddImm8, /*InsnID*/71, /*Imm*/1, |
| 26128 | GIR_ConstrainOperandRC, /*InsnID*/71, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26129 | GIR_ConstrainOperandRC, /*InsnID*/71, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26130 | GIR_ConstrainOperandRC, /*InsnID*/71, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26131 | GIR_BuildMI, /*InsnID*/70, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26132 | GIR_AddTempRegister, /*InsnID*/70, /*TempRegID*/69, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26133 | GIR_AddSimpleTempRegister, /*InsnID*/70, /*TempRegID*/70, |
| 26134 | GIR_AddImm8, /*InsnID*/70, /*Imm*/32, |
| 26135 | GIR_AddImm8, /*InsnID*/70, /*Imm*/31, |
| 26136 | GIR_ConstrainSelectedInstOperands, /*InsnID*/70, |
| 26137 | GIR_BuildMI, /*InsnID*/69, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26138 | GIR_AddTempRegister, /*InsnID*/69, /*TempRegID*/68, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26139 | GIR_AddSimpleTempRegister, /*InsnID*/69, /*TempRegID*/69, |
| 26140 | GIR_AddImm, /*InsnID*/69, /*Imm*/GIMT_Encode8(3855), |
| 26141 | GIR_ConstrainSelectedInstOperands, /*InsnID*/69, |
| 26142 | GIR_BuildMI, /*InsnID*/68, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26143 | GIR_AddTempRegister, /*InsnID*/68, /*TempRegID*/67, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26144 | GIR_AddSimpleTempRegister, /*InsnID*/68, /*TempRegID*/68, |
| 26145 | GIR_AddImm, /*InsnID*/68, /*Imm*/GIMT_Encode8(3855), |
| 26146 | GIR_ConstrainSelectedInstOperands, /*InsnID*/68, |
| 26147 | GIR_BuildMI, /*InsnID*/67, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26148 | GIR_AddTempRegister, /*InsnID*/67, /*TempRegID*/66, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26149 | GIR_AddImm, /*InsnID*/67, /*Imm*/GIMT_Encode8(52428), |
| 26150 | GIR_ConstrainSelectedInstOperands, /*InsnID*/67, |
| 26151 | GIR_BuildMI, /*InsnID*/66, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26152 | GIR_AddTempRegister, /*InsnID*/66, /*TempRegID*/65, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26153 | GIR_AddSimpleTempRegister, /*InsnID*/66, /*TempRegID*/66, |
| 26154 | GIR_AddImm, /*InsnID*/66, /*Imm*/GIMT_Encode8(52428), |
| 26155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/66, |
| 26156 | GIR_BuildMI, /*InsnID*/65, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26157 | GIR_AddTempRegister, /*InsnID*/65, /*TempRegID*/64, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26158 | GIR_ConstrainSelectedInstOperands, /*InsnID*/65, |
| 26159 | GIR_BuildMI, /*InsnID*/64, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26160 | GIR_AddTempRegister, /*InsnID*/64, /*TempRegID*/63, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26161 | GIR_AddSimpleTempRegister, /*InsnID*/64, /*TempRegID*/64, |
| 26162 | GIR_AddSimpleTempRegister, /*InsnID*/64, /*TempRegID*/65, |
| 26163 | GIR_AddImm8, /*InsnID*/64, /*Imm*/1, |
| 26164 | GIR_ConstrainOperandRC, /*InsnID*/64, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26165 | GIR_ConstrainOperandRC, /*InsnID*/64, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26166 | GIR_ConstrainOperandRC, /*InsnID*/64, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26167 | GIR_BuildMI, /*InsnID*/63, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26168 | GIR_AddTempRegister, /*InsnID*/63, /*TempRegID*/62, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26169 | GIR_AddSimpleTempRegister, /*InsnID*/63, /*TempRegID*/63, |
| 26170 | GIR_AddImm8, /*InsnID*/63, /*Imm*/32, |
| 26171 | GIR_AddImm8, /*InsnID*/63, /*Imm*/31, |
| 26172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/63, |
| 26173 | GIR_BuildMI, /*InsnID*/62, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26174 | GIR_AddTempRegister, /*InsnID*/62, /*TempRegID*/61, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26175 | GIR_AddSimpleTempRegister, /*InsnID*/62, /*TempRegID*/62, |
| 26176 | GIR_AddImm, /*InsnID*/62, /*Imm*/GIMT_Encode8(52428), |
| 26177 | GIR_ConstrainSelectedInstOperands, /*InsnID*/62, |
| 26178 | GIR_BuildMI, /*InsnID*/61, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26179 | GIR_AddTempRegister, /*InsnID*/61, /*TempRegID*/60, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26180 | GIR_AddSimpleTempRegister, /*InsnID*/61, /*TempRegID*/61, |
| 26181 | GIR_AddImm, /*InsnID*/61, /*Imm*/GIMT_Encode8(52428), |
| 26182 | GIR_ConstrainSelectedInstOperands, /*InsnID*/61, |
| 26183 | GIR_BuildMI, /*InsnID*/60, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26184 | GIR_AddTempRegister, /*InsnID*/60, /*TempRegID*/59, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26185 | GIR_AddImm, /*InsnID*/60, /*Imm*/GIMT_Encode8(43690), |
| 26186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/60, |
| 26187 | GIR_BuildMI, /*InsnID*/59, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26188 | GIR_AddTempRegister, /*InsnID*/59, /*TempRegID*/58, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26189 | GIR_AddSimpleTempRegister, /*InsnID*/59, /*TempRegID*/59, |
| 26190 | GIR_AddImm, /*InsnID*/59, /*Imm*/GIMT_Encode8(43690), |
| 26191 | GIR_ConstrainSelectedInstOperands, /*InsnID*/59, |
| 26192 | GIR_BuildMI, /*InsnID*/58, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26193 | GIR_AddTempRegister, /*InsnID*/58, /*TempRegID*/57, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26194 | GIR_ConstrainSelectedInstOperands, /*InsnID*/58, |
| 26195 | GIR_BuildMI, /*InsnID*/57, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26196 | GIR_AddTempRegister, /*InsnID*/57, /*TempRegID*/56, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26197 | GIR_AddSimpleTempRegister, /*InsnID*/57, /*TempRegID*/57, |
| 26198 | GIR_AddSimpleTempRegister, /*InsnID*/57, /*TempRegID*/58, |
| 26199 | GIR_AddImm8, /*InsnID*/57, /*Imm*/1, |
| 26200 | GIR_ConstrainOperandRC, /*InsnID*/57, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26201 | GIR_ConstrainOperandRC, /*InsnID*/57, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26202 | GIR_ConstrainOperandRC, /*InsnID*/57, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26203 | GIR_BuildMI, /*InsnID*/56, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26204 | GIR_AddTempRegister, /*InsnID*/56, /*TempRegID*/55, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26205 | GIR_AddSimpleTempRegister, /*InsnID*/56, /*TempRegID*/56, |
| 26206 | GIR_AddImm8, /*InsnID*/56, /*Imm*/32, |
| 26207 | GIR_AddImm8, /*InsnID*/56, /*Imm*/31, |
| 26208 | GIR_ConstrainSelectedInstOperands, /*InsnID*/56, |
| 26209 | GIR_BuildMI, /*InsnID*/55, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26210 | GIR_AddTempRegister, /*InsnID*/55, /*TempRegID*/54, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26211 | GIR_AddSimpleTempRegister, /*InsnID*/55, /*TempRegID*/55, |
| 26212 | GIR_AddImm, /*InsnID*/55, /*Imm*/GIMT_Encode8(43690), |
| 26213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/55, |
| 26214 | GIR_BuildMI, /*InsnID*/54, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26215 | GIR_AddTempRegister, /*InsnID*/54, /*TempRegID*/53, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26216 | GIR_AddSimpleTempRegister, /*InsnID*/54, /*TempRegID*/54, |
| 26217 | GIR_AddImm, /*InsnID*/54, /*Imm*/GIMT_Encode8(43690), |
| 26218 | GIR_ConstrainSelectedInstOperands, /*InsnID*/54, |
| 26219 | GIR_BuildMI, /*InsnID*/53, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26220 | GIR_AddTempRegister, /*InsnID*/53, /*TempRegID*/52, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26221 | GIR_Copy, /*NewInsnID*/53, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26222 | GIR_AddImm8, /*InsnID*/53, /*Imm*/1, |
| 26223 | GIR_AddImm8, /*InsnID*/53, /*Imm*/62, |
| 26224 | GIR_ConstrainSelectedInstOperands, /*InsnID*/53, |
| 26225 | GIR_BuildMI, /*InsnID*/52, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26226 | GIR_AddTempRegister, /*InsnID*/52, /*TempRegID*/51, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26227 | GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/52, |
| 26228 | GIR_AddSimpleTempRegister, /*InsnID*/52, /*TempRegID*/53, |
| 26229 | GIR_ConstrainSelectedInstOperands, /*InsnID*/52, |
| 26230 | GIR_BuildMI, /*InsnID*/51, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26231 | GIR_AddTempRegister, /*InsnID*/51, /*TempRegID*/50, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26232 | GIR_AddImm, /*InsnID*/51, /*Imm*/GIMT_Encode8(21845), |
| 26233 | GIR_ConstrainSelectedInstOperands, /*InsnID*/51, |
| 26234 | GIR_BuildMI, /*InsnID*/50, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26235 | GIR_AddTempRegister, /*InsnID*/50, /*TempRegID*/49, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26236 | GIR_AddSimpleTempRegister, /*InsnID*/50, /*TempRegID*/50, |
| 26237 | GIR_AddImm, /*InsnID*/50, /*Imm*/GIMT_Encode8(21845), |
| 26238 | GIR_ConstrainSelectedInstOperands, /*InsnID*/50, |
| 26239 | GIR_BuildMI, /*InsnID*/49, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26240 | GIR_AddTempRegister, /*InsnID*/49, /*TempRegID*/48, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/49, |
| 26242 | GIR_BuildMI, /*InsnID*/48, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26243 | GIR_AddTempRegister, /*InsnID*/48, /*TempRegID*/47, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26244 | GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/48, |
| 26245 | GIR_AddSimpleTempRegister, /*InsnID*/48, /*TempRegID*/49, |
| 26246 | GIR_AddImm8, /*InsnID*/48, /*Imm*/1, |
| 26247 | GIR_ConstrainOperandRC, /*InsnID*/48, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26248 | GIR_ConstrainOperandRC, /*InsnID*/48, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26249 | GIR_ConstrainOperandRC, /*InsnID*/48, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26250 | GIR_BuildMI, /*InsnID*/47, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26251 | GIR_AddTempRegister, /*InsnID*/47, /*TempRegID*/46, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26252 | GIR_AddSimpleTempRegister, /*InsnID*/47, /*TempRegID*/47, |
| 26253 | GIR_AddImm8, /*InsnID*/47, /*Imm*/32, |
| 26254 | GIR_AddImm8, /*InsnID*/47, /*Imm*/31, |
| 26255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/47, |
| 26256 | GIR_BuildMI, /*InsnID*/46, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26257 | GIR_AddTempRegister, /*InsnID*/46, /*TempRegID*/45, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26258 | GIR_AddSimpleTempRegister, /*InsnID*/46, /*TempRegID*/46, |
| 26259 | GIR_AddImm, /*InsnID*/46, /*Imm*/GIMT_Encode8(21845), |
| 26260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/46, |
| 26261 | GIR_BuildMI, /*InsnID*/45, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26262 | GIR_AddTempRegister, /*InsnID*/45, /*TempRegID*/44, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26263 | GIR_AddSimpleTempRegister, /*InsnID*/45, /*TempRegID*/45, |
| 26264 | GIR_AddImm, /*InsnID*/45, /*Imm*/GIMT_Encode8(21845), |
| 26265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/45, |
| 26266 | GIR_BuildMI, /*InsnID*/44, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26267 | GIR_AddTempRegister, /*InsnID*/44, /*TempRegID*/43, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26268 | GIR_Copy, /*NewInsnID*/44, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26269 | GIR_AddImm8, /*InsnID*/44, /*Imm*/63, |
| 26270 | GIR_AddImm8, /*InsnID*/44, /*Imm*/1, |
| 26271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/44, |
| 26272 | GIR_BuildMI, /*InsnID*/43, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26273 | GIR_AddTempRegister, /*InsnID*/43, /*TempRegID*/42, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26274 | GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/43, |
| 26275 | GIR_AddSimpleTempRegister, /*InsnID*/43, /*TempRegID*/44, |
| 26276 | GIR_ConstrainSelectedInstOperands, /*InsnID*/43, |
| 26277 | GIR_BuildMI, /*InsnID*/42, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26278 | GIR_AddTempRegister, /*InsnID*/42, /*TempRegID*/41, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26279 | GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/42, |
| 26280 | GIR_AddSimpleTempRegister, /*InsnID*/42, /*TempRegID*/51, |
| 26281 | GIR_ConstrainSelectedInstOperands, /*InsnID*/42, |
| 26282 | GIR_BuildMI, /*InsnID*/41, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26283 | GIR_AddTempRegister, /*InsnID*/41, /*TempRegID*/40, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26284 | GIR_AddSimpleTempRegister, /*InsnID*/41, /*TempRegID*/41, |
| 26285 | GIR_AddImm8, /*InsnID*/41, /*Imm*/2, |
| 26286 | GIR_AddImm8, /*InsnID*/41, /*Imm*/61, |
| 26287 | GIR_ConstrainSelectedInstOperands, /*InsnID*/41, |
| 26288 | GIR_BuildMI, /*InsnID*/40, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26289 | GIR_AddTempRegister, /*InsnID*/40, /*TempRegID*/39, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26290 | GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/40, |
| 26291 | GIR_AddSimpleTempRegister, /*InsnID*/40, /*TempRegID*/60, |
| 26292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/40, |
| 26293 | GIR_BuildMI, /*InsnID*/39, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26294 | GIR_AddTempRegister, /*InsnID*/39, /*TempRegID*/38, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26295 | GIR_AddImm, /*InsnID*/39, /*Imm*/GIMT_Encode8(13107), |
| 26296 | GIR_ConstrainSelectedInstOperands, /*InsnID*/39, |
| 26297 | GIR_BuildMI, /*InsnID*/38, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26298 | GIR_AddTempRegister, /*InsnID*/38, /*TempRegID*/37, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26299 | GIR_AddSimpleTempRegister, /*InsnID*/38, /*TempRegID*/38, |
| 26300 | GIR_AddImm, /*InsnID*/38, /*Imm*/GIMT_Encode8(13107), |
| 26301 | GIR_ConstrainSelectedInstOperands, /*InsnID*/38, |
| 26302 | GIR_BuildMI, /*InsnID*/37, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26303 | GIR_AddTempRegister, /*InsnID*/37, /*TempRegID*/36, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26304 | GIR_ConstrainSelectedInstOperands, /*InsnID*/37, |
| 26305 | GIR_BuildMI, /*InsnID*/36, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26306 | GIR_AddTempRegister, /*InsnID*/36, /*TempRegID*/35, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26307 | GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/36, |
| 26308 | GIR_AddSimpleTempRegister, /*InsnID*/36, /*TempRegID*/37, |
| 26309 | GIR_AddImm8, /*InsnID*/36, /*Imm*/1, |
| 26310 | GIR_ConstrainOperandRC, /*InsnID*/36, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26311 | GIR_ConstrainOperandRC, /*InsnID*/36, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26312 | GIR_ConstrainOperandRC, /*InsnID*/36, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26313 | GIR_BuildMI, /*InsnID*/35, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26314 | GIR_AddTempRegister, /*InsnID*/35, /*TempRegID*/34, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26315 | GIR_AddSimpleTempRegister, /*InsnID*/35, /*TempRegID*/35, |
| 26316 | GIR_AddImm8, /*InsnID*/35, /*Imm*/32, |
| 26317 | GIR_AddImm8, /*InsnID*/35, /*Imm*/31, |
| 26318 | GIR_ConstrainSelectedInstOperands, /*InsnID*/35, |
| 26319 | GIR_BuildMI, /*InsnID*/34, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26320 | GIR_AddTempRegister, /*InsnID*/34, /*TempRegID*/33, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26321 | GIR_AddSimpleTempRegister, /*InsnID*/34, /*TempRegID*/34, |
| 26322 | GIR_AddImm, /*InsnID*/34, /*Imm*/GIMT_Encode8(13107), |
| 26323 | GIR_ConstrainSelectedInstOperands, /*InsnID*/34, |
| 26324 | GIR_BuildMI, /*InsnID*/33, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26325 | GIR_AddTempRegister, /*InsnID*/33, /*TempRegID*/32, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26326 | GIR_AddSimpleTempRegister, /*InsnID*/33, /*TempRegID*/33, |
| 26327 | GIR_AddImm, /*InsnID*/33, /*Imm*/GIMT_Encode8(13107), |
| 26328 | GIR_ConstrainSelectedInstOperands, /*InsnID*/33, |
| 26329 | GIR_BuildMI, /*InsnID*/32, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26330 | GIR_AddTempRegister, /*InsnID*/32, /*TempRegID*/31, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26331 | GIR_AddImm, /*InsnID*/32, /*Imm*/GIMT_Encode8(43690), |
| 26332 | GIR_ConstrainSelectedInstOperands, /*InsnID*/32, |
| 26333 | GIR_BuildMI, /*InsnID*/31, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26334 | GIR_AddTempRegister, /*InsnID*/31, /*TempRegID*/30, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26335 | GIR_AddSimpleTempRegister, /*InsnID*/31, /*TempRegID*/31, |
| 26336 | GIR_AddImm, /*InsnID*/31, /*Imm*/GIMT_Encode8(43690), |
| 26337 | GIR_ConstrainSelectedInstOperands, /*InsnID*/31, |
| 26338 | GIR_BuildMI, /*InsnID*/30, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26339 | GIR_AddTempRegister, /*InsnID*/30, /*TempRegID*/29, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26340 | GIR_ConstrainSelectedInstOperands, /*InsnID*/30, |
| 26341 | GIR_BuildMI, /*InsnID*/29, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26342 | GIR_AddTempRegister, /*InsnID*/29, /*TempRegID*/28, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26343 | GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/29, |
| 26344 | GIR_AddSimpleTempRegister, /*InsnID*/29, /*TempRegID*/30, |
| 26345 | GIR_AddImm8, /*InsnID*/29, /*Imm*/1, |
| 26346 | GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26347 | GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26348 | GIR_ConstrainOperandRC, /*InsnID*/29, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26349 | GIR_BuildMI, /*InsnID*/28, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26350 | GIR_AddTempRegister, /*InsnID*/28, /*TempRegID*/27, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26351 | GIR_AddSimpleTempRegister, /*InsnID*/28, /*TempRegID*/28, |
| 26352 | GIR_AddImm8, /*InsnID*/28, /*Imm*/32, |
| 26353 | GIR_AddImm8, /*InsnID*/28, /*Imm*/31, |
| 26354 | GIR_ConstrainSelectedInstOperands, /*InsnID*/28, |
| 26355 | GIR_BuildMI, /*InsnID*/27, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26356 | GIR_AddTempRegister, /*InsnID*/27, /*TempRegID*/26, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26357 | GIR_AddSimpleTempRegister, /*InsnID*/27, /*TempRegID*/27, |
| 26358 | GIR_AddImm, /*InsnID*/27, /*Imm*/GIMT_Encode8(43690), |
| 26359 | GIR_ConstrainSelectedInstOperands, /*InsnID*/27, |
| 26360 | GIR_BuildMI, /*InsnID*/26, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26361 | GIR_AddTempRegister, /*InsnID*/26, /*TempRegID*/25, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26362 | GIR_AddSimpleTempRegister, /*InsnID*/26, /*TempRegID*/26, |
| 26363 | GIR_AddImm, /*InsnID*/26, /*Imm*/GIMT_Encode8(43690), |
| 26364 | GIR_ConstrainSelectedInstOperands, /*InsnID*/26, |
| 26365 | GIR_BuildMI, /*InsnID*/25, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26366 | GIR_AddTempRegister, /*InsnID*/25, /*TempRegID*/24, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26367 | GIR_Copy, /*NewInsnID*/25, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26368 | GIR_AddImm8, /*InsnID*/25, /*Imm*/1, |
| 26369 | GIR_AddImm8, /*InsnID*/25, /*Imm*/62, |
| 26370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/25, |
| 26371 | GIR_BuildMI, /*InsnID*/24, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26372 | GIR_AddTempRegister, /*InsnID*/24, /*TempRegID*/23, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26373 | GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/24, |
| 26374 | GIR_AddSimpleTempRegister, /*InsnID*/24, /*TempRegID*/25, |
| 26375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/24, |
| 26376 | GIR_BuildMI, /*InsnID*/23, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26377 | GIR_AddTempRegister, /*InsnID*/23, /*TempRegID*/22, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26378 | GIR_AddImm, /*InsnID*/23, /*Imm*/GIMT_Encode8(21845), |
| 26379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/23, |
| 26380 | GIR_BuildMI, /*InsnID*/22, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26381 | GIR_AddTempRegister, /*InsnID*/22, /*TempRegID*/21, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26382 | GIR_AddSimpleTempRegister, /*InsnID*/22, /*TempRegID*/22, |
| 26383 | GIR_AddImm, /*InsnID*/22, /*Imm*/GIMT_Encode8(21845), |
| 26384 | GIR_ConstrainSelectedInstOperands, /*InsnID*/22, |
| 26385 | GIR_BuildMI, /*InsnID*/21, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26386 | GIR_AddTempRegister, /*InsnID*/21, /*TempRegID*/20, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26387 | GIR_ConstrainSelectedInstOperands, /*InsnID*/21, |
| 26388 | GIR_BuildMI, /*InsnID*/20, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26389 | GIR_AddTempRegister, /*InsnID*/20, /*TempRegID*/19, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26390 | GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/20, |
| 26391 | GIR_AddSimpleTempRegister, /*InsnID*/20, /*TempRegID*/21, |
| 26392 | GIR_AddImm8, /*InsnID*/20, /*Imm*/1, |
| 26393 | GIR_ConstrainOperandRC, /*InsnID*/20, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26394 | GIR_ConstrainOperandRC, /*InsnID*/20, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26395 | GIR_ConstrainOperandRC, /*InsnID*/20, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26396 | GIR_BuildMI, /*InsnID*/19, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26397 | GIR_AddTempRegister, /*InsnID*/19, /*TempRegID*/18, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26398 | GIR_AddSimpleTempRegister, /*InsnID*/19, /*TempRegID*/19, |
| 26399 | GIR_AddImm8, /*InsnID*/19, /*Imm*/32, |
| 26400 | GIR_AddImm8, /*InsnID*/19, /*Imm*/31, |
| 26401 | GIR_ConstrainSelectedInstOperands, /*InsnID*/19, |
| 26402 | GIR_BuildMI, /*InsnID*/18, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26403 | GIR_AddTempRegister, /*InsnID*/18, /*TempRegID*/17, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26404 | GIR_AddSimpleTempRegister, /*InsnID*/18, /*TempRegID*/18, |
| 26405 | GIR_AddImm, /*InsnID*/18, /*Imm*/GIMT_Encode8(21845), |
| 26406 | GIR_ConstrainSelectedInstOperands, /*InsnID*/18, |
| 26407 | GIR_BuildMI, /*InsnID*/17, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26408 | GIR_AddTempRegister, /*InsnID*/17, /*TempRegID*/16, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26409 | GIR_AddSimpleTempRegister, /*InsnID*/17, /*TempRegID*/17, |
| 26410 | GIR_AddImm, /*InsnID*/17, /*Imm*/GIMT_Encode8(21845), |
| 26411 | GIR_ConstrainSelectedInstOperands, /*InsnID*/17, |
| 26412 | GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26413 | GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26414 | GIR_Copy, /*NewInsnID*/16, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26415 | GIR_AddImm8, /*InsnID*/16, /*Imm*/63, |
| 26416 | GIR_AddImm8, /*InsnID*/16, /*Imm*/1, |
| 26417 | GIR_ConstrainSelectedInstOperands, /*InsnID*/16, |
| 26418 | GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26419 | GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26420 | GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/15, |
| 26421 | GIR_AddSimpleTempRegister, /*InsnID*/15, /*TempRegID*/16, |
| 26422 | GIR_ConstrainSelectedInstOperands, /*InsnID*/15, |
| 26423 | GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26424 | GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26425 | GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14, |
| 26426 | GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/23, |
| 26427 | GIR_ConstrainSelectedInstOperands, /*InsnID*/14, |
| 26428 | GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26429 | GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26430 | GIR_AddSimpleTempRegister, /*InsnID*/13, /*TempRegID*/13, |
| 26431 | GIR_AddImm8, /*InsnID*/13, /*Imm*/62, |
| 26432 | GIR_AddImm8, /*InsnID*/13, /*Imm*/2, |
| 26433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/13, |
| 26434 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26435 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26436 | GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/12, |
| 26437 | GIR_AddSimpleTempRegister, /*InsnID*/12, /*TempRegID*/32, |
| 26438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/12, |
| 26439 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26440 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26441 | GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11, |
| 26442 | GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/39, |
| 26443 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 26444 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26445 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26446 | GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 26447 | GIR_AddImm8, /*InsnID*/10, /*Imm*/60, |
| 26448 | GIR_AddImm8, /*InsnID*/10, /*Imm*/4, |
| 26449 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 26450 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26451 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26452 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 26453 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/67, |
| 26454 | GIR_ConstrainSelectedInstOperands, /*InsnID*/9, |
| 26455 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26456 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26457 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 26458 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/74, |
| 26459 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 26460 | GIR_MakeTempReg, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26461 | GIR_MakeTempReg, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26462 | GIR_MakeTempReg, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26463 | GIR_MakeTempReg, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26464 | GIR_MakeTempReg, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26465 | GIR_MakeTempReg, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26466 | GIR_MakeTempReg, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26467 | GIR_MakeTempReg, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26468 | GIR_MakeTempReg, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26469 | GIR_MakeTempReg, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26470 | GIR_MakeTempReg, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26471 | GIR_MakeTempReg, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26472 | GIR_MakeTempReg, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26473 | GIR_MakeTempReg, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26474 | GIR_MakeTempReg, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26475 | GIR_MakeTempReg, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26476 | GIR_MakeTempReg, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26477 | GIR_MakeTempReg, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26478 | GIR_MakeTempReg, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26479 | GIR_MakeTempReg, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26480 | GIR_MakeTempReg, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26481 | GIR_MakeTempReg, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26482 | GIR_MakeTempReg, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26483 | GIR_MakeTempReg, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26484 | GIR_MakeTempReg, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26485 | GIR_MakeTempReg, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26486 | GIR_MakeTempReg, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26487 | GIR_MakeTempReg, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26488 | GIR_MakeTempReg, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26489 | GIR_MakeTempReg, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26490 | GIR_MakeTempReg, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26491 | GIR_MakeTempReg, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26492 | GIR_MakeTempReg, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26493 | GIR_MakeTempReg, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26494 | GIR_MakeTempReg, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26495 | GIR_MakeTempReg, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26496 | GIR_MakeTempReg, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26497 | GIR_MakeTempReg, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26498 | GIR_MakeTempReg, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26499 | GIR_MakeTempReg, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26500 | GIR_MakeTempReg, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26501 | GIR_MakeTempReg, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26502 | GIR_MakeTempReg, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26503 | GIR_MakeTempReg, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26504 | GIR_MakeTempReg, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26505 | GIR_MakeTempReg, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26506 | GIR_MakeTempReg, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26507 | GIR_MakeTempReg, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26508 | GIR_MakeTempReg, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26509 | GIR_MakeTempReg, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26510 | GIR_MakeTempReg, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26511 | GIR_MakeTempReg, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26512 | GIR_MakeTempReg, /*TempRegID*//* 192(*/0xC0, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26513 | GIR_MakeTempReg, /*TempRegID*//* 193(*/0xC1, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26514 | GIR_MakeTempReg, /*TempRegID*//* 194(*/0xC2, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26515 | GIR_MakeTempReg, /*TempRegID*//* 195(*/0xC3, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26516 | GIR_MakeTempReg, /*TempRegID*//* 196(*/0xC4, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26517 | GIR_MakeTempReg, /*TempRegID*//* 197(*/0xC5, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26518 | GIR_MakeTempReg, /*TempRegID*//* 198(*/0xC6, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26519 | GIR_MakeTempReg, /*TempRegID*//* 199(*/0xC7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26520 | GIR_MakeTempReg, /*TempRegID*//* 200(*/0xC8, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26521 | GIR_MakeTempReg, /*TempRegID*//* 201(*/0xC9, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26522 | GIR_MakeTempReg, /*TempRegID*//* 202(*/0xCA, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26523 | GIR_MakeTempReg, /*TempRegID*//* 203(*/0xCB, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26524 | GIR_MakeTempReg, /*TempRegID*//* 204(*/0xCC, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26525 | GIR_MakeTempReg, /*TempRegID*//* 205(*/0xCD, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26526 | GIR_MakeTempReg, /*TempRegID*//* 206(*/0xCE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26527 | GIR_MakeTempReg, /*TempRegID*//* 207(*/0xCF, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26528 | GIR_MakeTempReg, /*TempRegID*//* 208(*/0xD0, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26529 | GIR_MakeTempReg, /*TempRegID*//* 209(*/0xD1, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26530 | GIR_MakeTempReg, /*TempRegID*//* 210(*/0xD2, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26531 | GIR_MakeTempReg, /*TempRegID*//* 211(*/0xD3, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26532 | GIR_MakeTempReg, /*TempRegID*//* 212(*/0xD4, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26533 | GIR_MakeTempReg, /*TempRegID*//* 213(*/0xD5, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26534 | GIR_MakeTempReg, /*TempRegID*//* 214(*/0xD6, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26535 | GIR_MakeTempReg, /*TempRegID*//* 215(*/0xD7, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26536 | GIR_MakeTempReg, /*TempRegID*//* 216(*/0xD8, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26537 | GIR_MakeTempReg, /*TempRegID*//* 217(*/0xD9, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26538 | GIR_MakeTempReg, /*TempRegID*//* 218(*/0xDA, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26539 | GIR_MakeTempReg, /*TempRegID*//* 219(*/0xDB, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26540 | GIR_MakeTempReg, /*TempRegID*//* 220(*/0xDC, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26541 | GIR_MakeTempReg, /*TempRegID*//* 221(*/0xDD, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26542 | GIR_MakeTempReg, /*TempRegID*//* 222(*/0xDE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26543 | GIR_MakeTempReg, /*TempRegID*//* 223(*/0xDF, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26544 | GIR_MakeTempReg, /*TempRegID*//* 224(*/0xE0, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26545 | GIR_MakeTempReg, /*TempRegID*//* 225(*/0xE1, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26546 | GIR_MakeTempReg, /*TempRegID*//* 226(*/0xE2, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26547 | GIR_MakeTempReg, /*TempRegID*//* 227(*/0xE3, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26548 | GIR_MakeTempReg, /*TempRegID*//* 228(*/0xE4, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26549 | GIR_MakeTempReg, /*TempRegID*//* 229(*/0xE5, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26550 | GIR_MakeTempReg, /*TempRegID*//* 230(*/0xE6, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26551 | GIR_MakeTempReg, /*TempRegID*//* 231(*/0xE7, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26552 | GIR_MakeTempReg, /*TempRegID*//* 232(*/0xE8, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26553 | GIR_MakeTempReg, /*TempRegID*//* 233(*/0xE9, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26554 | GIR_MakeTempReg, /*TempRegID*//* 234(*/0xEA, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26555 | GIR_MakeTempReg, /*TempRegID*//* 235(*/0xEB, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26556 | GIR_MakeTempReg, /*TempRegID*//* 236(*/0xEC, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26557 | GIR_MakeTempReg, /*TempRegID*//* 237(*/0xED, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26558 | GIR_MakeTempReg, /*TempRegID*//* 238(*/0xEE, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26559 | GIR_MakeTempReg, /*TempRegID*//* 239(*/0xEF, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26560 | GIR_MakeTempReg, /*TempRegID*//* 240(*/0xF0, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26561 | GIR_MakeTempReg, /*TempRegID*//* 241(*/0xF1, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26562 | GIR_MakeTempReg, /*TempRegID*//* 242(*/0xF2, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26563 | GIR_MakeTempReg, /*TempRegID*//* 243(*/0xF3, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26564 | GIR_MakeTempReg, /*TempRegID*//* 244(*/0xF4, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26565 | GIR_MakeTempReg, /*TempRegID*//* 245(*/0xF5, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26566 | GIR_MakeTempReg, /*TempRegID*//* 246(*/0xF6, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26567 | GIR_MakeTempReg, /*TempRegID*//* 247(*/0xF7, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26568 | GIR_MakeTempReg, /*TempRegID*//* 248(*/0xF8, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26569 | GIR_MakeTempReg, /*TempRegID*//* 249(*/0xF9, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26570 | GIR_MakeTempReg, /*TempRegID*//* 250(*/0xFA, 0x01/*)*/, /*TypeID*/GILLT_s32, |
| 26571 | GIR_MakeTempReg, /*TempRegID*//* 251(*/0xFB, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26572 | GIR_MakeTempReg, /*TempRegID*//* 252(*/0xFC, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26573 | GIR_MakeTempReg, /*TempRegID*//* 253(*/0xFD, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26574 | GIR_MakeTempReg, /*TempRegID*//* 254(*/0xFE, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26575 | GIR_MakeTempReg, /*TempRegID*//* 255(*/0xFF, 0x01/*)*/, /*TypeID*/GILLT_s64, |
| 26576 | GIR_MakeTempReg, /*TempRegID*//* 256(*/0x80, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26577 | GIR_MakeTempReg, /*TempRegID*//* 257(*/0x81, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26578 | GIR_MakeTempReg, /*TempRegID*//* 258(*/0x82, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 26579 | GIR_MakeTempReg, /*TempRegID*//* 259(*/0x83, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 26580 | GIR_MakeTempReg, /*TempRegID*//* 260(*/0x84, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26581 | GIR_MakeTempReg, /*TempRegID*//* 261(*/0x85, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26582 | GIR_MakeTempReg, /*TempRegID*//* 262(*/0x86, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26583 | GIR_MakeTempReg, /*TempRegID*//* 263(*/0x87, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26584 | GIR_MakeTempReg, /*TempRegID*//* 264(*/0x88, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26585 | GIR_MakeTempReg, /*TempRegID*//* 265(*/0x89, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 26586 | GIR_MakeTempReg, /*TempRegID*//* 266(*/0x8A, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 26587 | GIR_MakeTempReg, /*TempRegID*//* 267(*/0x8B, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26588 | GIR_MakeTempReg, /*TempRegID*//* 268(*/0x8C, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26589 | GIR_MakeTempReg, /*TempRegID*//* 269(*/0x8D, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26590 | GIR_MakeTempReg, /*TempRegID*//* 270(*/0x8E, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26591 | GIR_MakeTempReg, /*TempRegID*//* 271(*/0x8F, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 26592 | GIR_MakeTempReg, /*TempRegID*//* 272(*/0x90, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 26593 | GIR_MakeTempReg, /*TempRegID*//* 273(*/0x91, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 26594 | GIR_BuildMI, /*InsnID*//* 274(*/0x92, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26595 | GIR_AddTempRegister, /*InsnID*//* 274(*/0x92, 0x02/*)*/, /*TempRegID*//* 273(*/0x91, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26596 | GIR_AddImm, /*InsnID*//* 274(*/0x92, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 26597 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 274(*/0x92, 0x02/*)*/, |
| 26598 | GIR_BuildMI, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26599 | GIR_AddTempRegister, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*TempRegID*//* 272(*/0x90, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26600 | GIR_AddSimpleTempRegister, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*TempRegID*//* 273(*/0x91, 0x02/*)*/, |
| 26601 | GIR_AddImm, /*InsnID*//* 273(*/0x91, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 26602 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 273(*/0x91, 0x02/*)*/, |
| 26603 | GIR_BuildMI, /*InsnID*//* 272(*/0x90, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26604 | GIR_AddTempRegister, /*InsnID*//* 272(*/0x90, 0x02/*)*/, /*TempRegID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26605 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 272(*/0x90, 0x02/*)*/, |
| 26606 | GIR_BuildMI, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26607 | GIR_AddTempRegister, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegID*//* 270(*/0x8E, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26608 | GIR_AddSimpleTempRegister, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegID*//* 271(*/0x8F, 0x02/*)*/, |
| 26609 | GIR_AddSimpleTempRegister, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*TempRegID*//* 272(*/0x90, 0x02/*)*/, |
| 26610 | GIR_AddImm8, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Imm*/1, |
| 26611 | GIR_ConstrainOperandRC, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26612 | GIR_ConstrainOperandRC, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26613 | GIR_ConstrainOperandRC, /*InsnID*//* 271(*/0x8F, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26614 | GIR_BuildMI, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26615 | GIR_AddTempRegister, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*TempRegID*//* 269(*/0x8D, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26616 | GIR_AddSimpleTempRegister, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*TempRegID*//* 270(*/0x8E, 0x02/*)*/, |
| 26617 | GIR_AddImm8, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*Imm*/32, |
| 26618 | GIR_AddImm8, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, /*Imm*/31, |
| 26619 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 270(*/0x8E, 0x02/*)*/, |
| 26620 | GIR_BuildMI, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26621 | GIR_AddTempRegister, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*TempRegID*//* 268(*/0x8C, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26622 | GIR_AddSimpleTempRegister, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*TempRegID*//* 269(*/0x8D, 0x02/*)*/, |
| 26623 | GIR_AddImm, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 26624 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 269(*/0x8D, 0x02/*)*/, |
| 26625 | GIR_BuildMI, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26626 | GIR_AddTempRegister, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*TempRegID*//* 267(*/0x8B, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26627 | GIR_AddSimpleTempRegister, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*TempRegID*//* 268(*/0x8C, 0x02/*)*/, |
| 26628 | GIR_AddImm, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 26629 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 268(*/0x8C, 0x02/*)*/, |
| 26630 | GIR_BuildMI, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26631 | GIR_AddTempRegister, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, /*TempRegID*//* 266(*/0x8A, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26632 | GIR_AddImm, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 26633 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 267(*/0x8B, 0x02/*)*/, |
| 26634 | GIR_BuildMI, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26635 | GIR_AddTempRegister, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*TempRegID*//* 265(*/0x89, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26636 | GIR_AddSimpleTempRegister, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*TempRegID*//* 266(*/0x8A, 0x02/*)*/, |
| 26637 | GIR_AddImm, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 26638 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 266(*/0x8A, 0x02/*)*/, |
| 26639 | GIR_BuildMI, /*InsnID*//* 265(*/0x89, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26640 | GIR_AddTempRegister, /*InsnID*//* 265(*/0x89, 0x02/*)*/, /*TempRegID*//* 264(*/0x88, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26641 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 265(*/0x89, 0x02/*)*/, |
| 26642 | GIR_BuildMI, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26643 | GIR_AddTempRegister, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*TempRegID*//* 263(*/0x87, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26644 | GIR_AddSimpleTempRegister, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*TempRegID*//* 264(*/0x88, 0x02/*)*/, |
| 26645 | GIR_AddSimpleTempRegister, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*TempRegID*//* 265(*/0x89, 0x02/*)*/, |
| 26646 | GIR_AddImm8, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Imm*/1, |
| 26647 | GIR_ConstrainOperandRC, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26648 | GIR_ConstrainOperandRC, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26649 | GIR_ConstrainOperandRC, /*InsnID*//* 264(*/0x88, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26650 | GIR_BuildMI, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26651 | GIR_AddTempRegister, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*TempRegID*//* 262(*/0x86, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26652 | GIR_AddSimpleTempRegister, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*TempRegID*//* 263(*/0x87, 0x02/*)*/, |
| 26653 | GIR_AddImm8, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*Imm*/32, |
| 26654 | GIR_AddImm8, /*InsnID*//* 263(*/0x87, 0x02/*)*/, /*Imm*/31, |
| 26655 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 263(*/0x87, 0x02/*)*/, |
| 26656 | GIR_BuildMI, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26657 | GIR_AddTempRegister, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*TempRegID*//* 261(*/0x85, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26658 | GIR_AddSimpleTempRegister, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*TempRegID*//* 262(*/0x86, 0x02/*)*/, |
| 26659 | GIR_AddImm, /*InsnID*//* 262(*/0x86, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 26660 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 262(*/0x86, 0x02/*)*/, |
| 26661 | GIR_BuildMI, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26662 | GIR_AddTempRegister, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*TempRegID*//* 260(*/0x84, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26663 | GIR_AddSimpleTempRegister, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*TempRegID*//* 261(*/0x85, 0x02/*)*/, |
| 26664 | GIR_AddImm, /*InsnID*//* 261(*/0x85, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 26665 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 261(*/0x85, 0x02/*)*/, |
| 26666 | GIR_BuildMI, /*InsnID*//* 260(*/0x84, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26667 | GIR_AddTempRegister, /*InsnID*//* 260(*/0x84, 0x02/*)*/, /*TempRegID*//* 259(*/0x83, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26668 | GIR_AddImm, /*InsnID*//* 260(*/0x84, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26669 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 260(*/0x84, 0x02/*)*/, |
| 26670 | GIR_BuildMI, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26671 | GIR_AddTempRegister, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*TempRegID*//* 258(*/0x82, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26672 | GIR_AddSimpleTempRegister, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*TempRegID*//* 259(*/0x83, 0x02/*)*/, |
| 26673 | GIR_AddImm, /*InsnID*//* 259(*/0x83, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26674 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 259(*/0x83, 0x02/*)*/, |
| 26675 | GIR_BuildMI, /*InsnID*//* 258(*/0x82, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26676 | GIR_AddTempRegister, /*InsnID*//* 258(*/0x82, 0x02/*)*/, /*TempRegID*//* 257(*/0x81, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26677 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 258(*/0x82, 0x02/*)*/, |
| 26678 | GIR_BuildMI, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26679 | GIR_AddTempRegister, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*TempRegID*//* 256(*/0x80, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26680 | GIR_AddSimpleTempRegister, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*TempRegID*//* 257(*/0x81, 0x02/*)*/, |
| 26681 | GIR_AddSimpleTempRegister, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*TempRegID*//* 258(*/0x82, 0x02/*)*/, |
| 26682 | GIR_AddImm8, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Imm*/1, |
| 26683 | GIR_ConstrainOperandRC, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26684 | GIR_ConstrainOperandRC, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26685 | GIR_ConstrainOperandRC, /*InsnID*//* 257(*/0x81, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26686 | GIR_BuildMI, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26687 | GIR_AddTempRegister, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*TempRegID*//* 255(*/0xFF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26688 | GIR_AddSimpleTempRegister, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*TempRegID*//* 256(*/0x80, 0x02/*)*/, |
| 26689 | GIR_AddImm8, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*Imm*/32, |
| 26690 | GIR_AddImm8, /*InsnID*//* 256(*/0x80, 0x02/*)*/, /*Imm*/31, |
| 26691 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 256(*/0x80, 0x02/*)*/, |
| 26692 | GIR_BuildMI, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26693 | GIR_AddTempRegister, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*TempRegID*//* 254(*/0xFE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26694 | GIR_AddSimpleTempRegister, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*TempRegID*//* 255(*/0xFF, 0x01/*)*/, |
| 26695 | GIR_AddImm, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26696 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 255(*/0xFF, 0x01/*)*/, |
| 26697 | GIR_BuildMI, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26698 | GIR_AddTempRegister, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*TempRegID*//* 253(*/0xFD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26699 | GIR_AddSimpleTempRegister, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*TempRegID*//* 254(*/0xFE, 0x01/*)*/, |
| 26700 | GIR_AddImm, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26701 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 254(*/0xFE, 0x01/*)*/, |
| 26702 | GIR_BuildMI, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26703 | GIR_AddTempRegister, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*TempRegID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26704 | GIR_Copy, /*NewInsnID*//* 253(*/0xFD, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26705 | GIR_AddImm8, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*Imm*/1, |
| 26706 | GIR_AddImm8, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, /*Imm*/62, |
| 26707 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 253(*/0xFD, 0x01/*)*/, |
| 26708 | GIR_BuildMI, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26709 | GIR_AddTempRegister, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegID*//* 251(*/0xFB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26710 | GIR_AddSimpleTempRegister, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegID*//* 252(*/0xFC, 0x01/*)*/, |
| 26711 | GIR_AddSimpleTempRegister, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, /*TempRegID*//* 253(*/0xFD, 0x01/*)*/, |
| 26712 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 252(*/0xFC, 0x01/*)*/, |
| 26713 | GIR_BuildMI, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26714 | GIR_AddTempRegister, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, /*TempRegID*//* 250(*/0xFA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26715 | GIR_AddImm, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26716 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 251(*/0xFB, 0x01/*)*/, |
| 26717 | GIR_BuildMI, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26718 | GIR_AddTempRegister, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*TempRegID*//* 249(*/0xF9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26719 | GIR_AddSimpleTempRegister, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*TempRegID*//* 250(*/0xFA, 0x01/*)*/, |
| 26720 | GIR_AddImm, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26721 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 250(*/0xFA, 0x01/*)*/, |
| 26722 | GIR_BuildMI, /*InsnID*//* 249(*/0xF9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26723 | GIR_AddTempRegister, /*InsnID*//* 249(*/0xF9, 0x01/*)*/, /*TempRegID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26724 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 249(*/0xF9, 0x01/*)*/, |
| 26725 | GIR_BuildMI, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26726 | GIR_AddTempRegister, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegID*//* 247(*/0xF7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26727 | GIR_AddSimpleTempRegister, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegID*//* 248(*/0xF8, 0x01/*)*/, |
| 26728 | GIR_AddSimpleTempRegister, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*TempRegID*//* 249(*/0xF9, 0x01/*)*/, |
| 26729 | GIR_AddImm8, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Imm*/1, |
| 26730 | GIR_ConstrainOperandRC, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26731 | GIR_ConstrainOperandRC, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26732 | GIR_ConstrainOperandRC, /*InsnID*//* 248(*/0xF8, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26733 | GIR_BuildMI, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26734 | GIR_AddTempRegister, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*TempRegID*//* 246(*/0xF6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26735 | GIR_AddSimpleTempRegister, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*TempRegID*//* 247(*/0xF7, 0x01/*)*/, |
| 26736 | GIR_AddImm8, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*Imm*/32, |
| 26737 | GIR_AddImm8, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, /*Imm*/31, |
| 26738 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 247(*/0xF7, 0x01/*)*/, |
| 26739 | GIR_BuildMI, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26740 | GIR_AddTempRegister, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*TempRegID*//* 245(*/0xF5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26741 | GIR_AddSimpleTempRegister, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*TempRegID*//* 246(*/0xF6, 0x01/*)*/, |
| 26742 | GIR_AddImm, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26743 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 246(*/0xF6, 0x01/*)*/, |
| 26744 | GIR_BuildMI, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26745 | GIR_AddTempRegister, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*TempRegID*//* 244(*/0xF4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26746 | GIR_AddSimpleTempRegister, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*TempRegID*//* 245(*/0xF5, 0x01/*)*/, |
| 26747 | GIR_AddImm, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26748 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 245(*/0xF5, 0x01/*)*/, |
| 26749 | GIR_BuildMI, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26750 | GIR_AddTempRegister, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*TempRegID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26751 | GIR_Copy, /*NewInsnID*//* 244(*/0xF4, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26752 | GIR_AddImm8, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*Imm*/63, |
| 26753 | GIR_AddImm8, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, /*Imm*/1, |
| 26754 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 244(*/0xF4, 0x01/*)*/, |
| 26755 | GIR_BuildMI, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26756 | GIR_AddTempRegister, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26757 | GIR_AddSimpleTempRegister, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegID*//* 243(*/0xF3, 0x01/*)*/, |
| 26758 | GIR_AddSimpleTempRegister, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, /*TempRegID*//* 244(*/0xF4, 0x01/*)*/, |
| 26759 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 243(*/0xF3, 0x01/*)*/, |
| 26760 | GIR_BuildMI, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26761 | GIR_AddTempRegister, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegID*//* 241(*/0xF1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26762 | GIR_AddSimpleTempRegister, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegID*//* 242(*/0xF2, 0x01/*)*/, |
| 26763 | GIR_AddSimpleTempRegister, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, /*TempRegID*//* 251(*/0xFB, 0x01/*)*/, |
| 26764 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 242(*/0xF2, 0x01/*)*/, |
| 26765 | GIR_BuildMI, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26766 | GIR_AddTempRegister, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*TempRegID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26767 | GIR_AddSimpleTempRegister, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*TempRegID*//* 241(*/0xF1, 0x01/*)*/, |
| 26768 | GIR_AddImm8, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*Imm*/2, |
| 26769 | GIR_AddImm8, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, /*Imm*/61, |
| 26770 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 241(*/0xF1, 0x01/*)*/, |
| 26771 | GIR_BuildMI, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26772 | GIR_AddTempRegister, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegID*//* 239(*/0xEF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26773 | GIR_AddSimpleTempRegister, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegID*//* 240(*/0xF0, 0x01/*)*/, |
| 26774 | GIR_AddSimpleTempRegister, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, /*TempRegID*//* 260(*/0x84, 0x02/*)*/, |
| 26775 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 240(*/0xF0, 0x01/*)*/, |
| 26776 | GIR_BuildMI, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26777 | GIR_AddTempRegister, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, /*TempRegID*//* 238(*/0xEE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26778 | GIR_AddImm, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 26779 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 239(*/0xEF, 0x01/*)*/, |
| 26780 | GIR_BuildMI, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26781 | GIR_AddTempRegister, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*TempRegID*//* 237(*/0xED, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26782 | GIR_AddSimpleTempRegister, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*TempRegID*//* 238(*/0xEE, 0x01/*)*/, |
| 26783 | GIR_AddImm, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 26784 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 238(*/0xEE, 0x01/*)*/, |
| 26785 | GIR_BuildMI, /*InsnID*//* 237(*/0xED, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26786 | GIR_AddTempRegister, /*InsnID*//* 237(*/0xED, 0x01/*)*/, /*TempRegID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26787 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 237(*/0xED, 0x01/*)*/, |
| 26788 | GIR_BuildMI, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26789 | GIR_AddTempRegister, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegID*//* 235(*/0xEB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26790 | GIR_AddSimpleTempRegister, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegID*//* 236(*/0xEC, 0x01/*)*/, |
| 26791 | GIR_AddSimpleTempRegister, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*TempRegID*//* 237(*/0xED, 0x01/*)*/, |
| 26792 | GIR_AddImm8, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Imm*/1, |
| 26793 | GIR_ConstrainOperandRC, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26794 | GIR_ConstrainOperandRC, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26795 | GIR_ConstrainOperandRC, /*InsnID*//* 236(*/0xEC, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26796 | GIR_BuildMI, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26797 | GIR_AddTempRegister, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*TempRegID*//* 234(*/0xEA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26798 | GIR_AddSimpleTempRegister, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*TempRegID*//* 235(*/0xEB, 0x01/*)*/, |
| 26799 | GIR_AddImm8, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*Imm*/32, |
| 26800 | GIR_AddImm8, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, /*Imm*/31, |
| 26801 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 235(*/0xEB, 0x01/*)*/, |
| 26802 | GIR_BuildMI, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26803 | GIR_AddTempRegister, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*TempRegID*//* 233(*/0xE9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26804 | GIR_AddSimpleTempRegister, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*TempRegID*//* 234(*/0xEA, 0x01/*)*/, |
| 26805 | GIR_AddImm, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 26806 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 234(*/0xEA, 0x01/*)*/, |
| 26807 | GIR_BuildMI, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26808 | GIR_AddTempRegister, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*TempRegID*//* 232(*/0xE8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26809 | GIR_AddSimpleTempRegister, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*TempRegID*//* 233(*/0xE9, 0x01/*)*/, |
| 26810 | GIR_AddImm, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 26811 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 233(*/0xE9, 0x01/*)*/, |
| 26812 | GIR_BuildMI, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26813 | GIR_AddTempRegister, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, /*TempRegID*//* 231(*/0xE7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26814 | GIR_AddImm, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26815 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 232(*/0xE8, 0x01/*)*/, |
| 26816 | GIR_BuildMI, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26817 | GIR_AddTempRegister, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*TempRegID*//* 230(*/0xE6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26818 | GIR_AddSimpleTempRegister, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*TempRegID*//* 231(*/0xE7, 0x01/*)*/, |
| 26819 | GIR_AddImm, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26820 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 231(*/0xE7, 0x01/*)*/, |
| 26821 | GIR_BuildMI, /*InsnID*//* 230(*/0xE6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26822 | GIR_AddTempRegister, /*InsnID*//* 230(*/0xE6, 0x01/*)*/, /*TempRegID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26823 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 230(*/0xE6, 0x01/*)*/, |
| 26824 | GIR_BuildMI, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26825 | GIR_AddTempRegister, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegID*//* 228(*/0xE4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26826 | GIR_AddSimpleTempRegister, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegID*//* 229(*/0xE5, 0x01/*)*/, |
| 26827 | GIR_AddSimpleTempRegister, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*TempRegID*//* 230(*/0xE6, 0x01/*)*/, |
| 26828 | GIR_AddImm8, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Imm*/1, |
| 26829 | GIR_ConstrainOperandRC, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26830 | GIR_ConstrainOperandRC, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26831 | GIR_ConstrainOperandRC, /*InsnID*//* 229(*/0xE5, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26832 | GIR_BuildMI, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26833 | GIR_AddTempRegister, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*TempRegID*//* 227(*/0xE3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26834 | GIR_AddSimpleTempRegister, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*TempRegID*//* 228(*/0xE4, 0x01/*)*/, |
| 26835 | GIR_AddImm8, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*Imm*/32, |
| 26836 | GIR_AddImm8, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, /*Imm*/31, |
| 26837 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 228(*/0xE4, 0x01/*)*/, |
| 26838 | GIR_BuildMI, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26839 | GIR_AddTempRegister, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*TempRegID*//* 226(*/0xE2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26840 | GIR_AddSimpleTempRegister, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*TempRegID*//* 227(*/0xE3, 0x01/*)*/, |
| 26841 | GIR_AddImm, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26842 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 227(*/0xE3, 0x01/*)*/, |
| 26843 | GIR_BuildMI, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26844 | GIR_AddTempRegister, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*TempRegID*//* 225(*/0xE1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26845 | GIR_AddSimpleTempRegister, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*TempRegID*//* 226(*/0xE2, 0x01/*)*/, |
| 26846 | GIR_AddImm, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 26847 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 226(*/0xE2, 0x01/*)*/, |
| 26848 | GIR_BuildMI, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26849 | GIR_AddTempRegister, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*TempRegID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26850 | GIR_Copy, /*NewInsnID*//* 225(*/0xE1, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26851 | GIR_AddImm8, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*Imm*/1, |
| 26852 | GIR_AddImm8, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, /*Imm*/62, |
| 26853 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 225(*/0xE1, 0x01/*)*/, |
| 26854 | GIR_BuildMI, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26855 | GIR_AddTempRegister, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegID*//* 223(*/0xDF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26856 | GIR_AddSimpleTempRegister, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegID*//* 224(*/0xE0, 0x01/*)*/, |
| 26857 | GIR_AddSimpleTempRegister, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, /*TempRegID*//* 225(*/0xE1, 0x01/*)*/, |
| 26858 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 224(*/0xE0, 0x01/*)*/, |
| 26859 | GIR_BuildMI, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26860 | GIR_AddTempRegister, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, /*TempRegID*//* 222(*/0xDE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26861 | GIR_AddImm, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26862 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 223(*/0xDF, 0x01/*)*/, |
| 26863 | GIR_BuildMI, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26864 | GIR_AddTempRegister, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*TempRegID*//* 221(*/0xDD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26865 | GIR_AddSimpleTempRegister, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*TempRegID*//* 222(*/0xDE, 0x01/*)*/, |
| 26866 | GIR_AddImm, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26867 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 222(*/0xDE, 0x01/*)*/, |
| 26868 | GIR_BuildMI, /*InsnID*//* 221(*/0xDD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26869 | GIR_AddTempRegister, /*InsnID*//* 221(*/0xDD, 0x01/*)*/, /*TempRegID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26870 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 221(*/0xDD, 0x01/*)*/, |
| 26871 | GIR_BuildMI, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26872 | GIR_AddTempRegister, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegID*//* 219(*/0xDB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26873 | GIR_AddSimpleTempRegister, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegID*//* 220(*/0xDC, 0x01/*)*/, |
| 26874 | GIR_AddSimpleTempRegister, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*TempRegID*//* 221(*/0xDD, 0x01/*)*/, |
| 26875 | GIR_AddImm8, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Imm*/1, |
| 26876 | GIR_ConstrainOperandRC, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26877 | GIR_ConstrainOperandRC, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26878 | GIR_ConstrainOperandRC, /*InsnID*//* 220(*/0xDC, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26879 | GIR_BuildMI, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26880 | GIR_AddTempRegister, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*TempRegID*//* 218(*/0xDA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26881 | GIR_AddSimpleTempRegister, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*TempRegID*//* 219(*/0xDB, 0x01/*)*/, |
| 26882 | GIR_AddImm8, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*Imm*/32, |
| 26883 | GIR_AddImm8, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, /*Imm*/31, |
| 26884 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 219(*/0xDB, 0x01/*)*/, |
| 26885 | GIR_BuildMI, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26886 | GIR_AddTempRegister, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*TempRegID*//* 217(*/0xD9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26887 | GIR_AddSimpleTempRegister, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*TempRegID*//* 218(*/0xDA, 0x01/*)*/, |
| 26888 | GIR_AddImm, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26889 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 218(*/0xDA, 0x01/*)*/, |
| 26890 | GIR_BuildMI, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26891 | GIR_AddTempRegister, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*TempRegID*//* 216(*/0xD8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26892 | GIR_AddSimpleTempRegister, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*TempRegID*//* 217(*/0xD9, 0x01/*)*/, |
| 26893 | GIR_AddImm, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 26894 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 217(*/0xD9, 0x01/*)*/, |
| 26895 | GIR_BuildMI, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26896 | GIR_AddTempRegister, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*TempRegID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26897 | GIR_Copy, /*NewInsnID*//* 216(*/0xD8, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 26898 | GIR_AddImm8, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*Imm*/63, |
| 26899 | GIR_AddImm8, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, /*Imm*/1, |
| 26900 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 216(*/0xD8, 0x01/*)*/, |
| 26901 | GIR_BuildMI, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26902 | GIR_AddTempRegister, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26903 | GIR_AddSimpleTempRegister, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegID*//* 215(*/0xD7, 0x01/*)*/, |
| 26904 | GIR_AddSimpleTempRegister, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, /*TempRegID*//* 216(*/0xD8, 0x01/*)*/, |
| 26905 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 215(*/0xD7, 0x01/*)*/, |
| 26906 | GIR_BuildMI, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26907 | GIR_AddTempRegister, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegID*//* 213(*/0xD5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26908 | GIR_AddSimpleTempRegister, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegID*//* 214(*/0xD6, 0x01/*)*/, |
| 26909 | GIR_AddSimpleTempRegister, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, /*TempRegID*//* 223(*/0xDF, 0x01/*)*/, |
| 26910 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 214(*/0xD6, 0x01/*)*/, |
| 26911 | GIR_BuildMI, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 26912 | GIR_AddTempRegister, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*TempRegID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26913 | GIR_AddSimpleTempRegister, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*TempRegID*//* 213(*/0xD5, 0x01/*)*/, |
| 26914 | GIR_AddImm8, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*Imm*/62, |
| 26915 | GIR_AddImm8, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, /*Imm*/2, |
| 26916 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 213(*/0xD5, 0x01/*)*/, |
| 26917 | GIR_BuildMI, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26918 | GIR_AddTempRegister, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26919 | GIR_AddSimpleTempRegister, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegID*//* 212(*/0xD4, 0x01/*)*/, |
| 26920 | GIR_AddSimpleTempRegister, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, /*TempRegID*//* 232(*/0xE8, 0x01/*)*/, |
| 26921 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 212(*/0xD4, 0x01/*)*/, |
| 26922 | GIR_BuildMI, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 26923 | GIR_AddTempRegister, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegID*//* 210(*/0xD2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26924 | GIR_AddSimpleTempRegister, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegID*//* 211(*/0xD3, 0x01/*)*/, |
| 26925 | GIR_AddSimpleTempRegister, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, /*TempRegID*//* 239(*/0xEF, 0x01/*)*/, |
| 26926 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 211(*/0xD3, 0x01/*)*/, |
| 26927 | GIR_BuildMI, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26928 | GIR_AddTempRegister, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*TempRegID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26929 | GIR_AddSimpleTempRegister, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*TempRegID*//* 210(*/0xD2, 0x01/*)*/, |
| 26930 | GIR_AddImm8, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*Imm*/4, |
| 26931 | GIR_AddImm8, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, /*Imm*/59, |
| 26932 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 210(*/0xD2, 0x01/*)*/, |
| 26933 | GIR_BuildMI, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 26934 | GIR_AddTempRegister, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegID*//* 208(*/0xD0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26935 | GIR_AddSimpleTempRegister, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegID*//* 209(*/0xD1, 0x01/*)*/, |
| 26936 | GIR_AddSimpleTempRegister, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, /*TempRegID*//* 267(*/0x8B, 0x02/*)*/, |
| 26937 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 209(*/0xD1, 0x01/*)*/, |
| 26938 | GIR_BuildMI, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26939 | GIR_AddTempRegister, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, /*TempRegID*//* 207(*/0xCF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26940 | GIR_AddImm, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 26941 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 208(*/0xD0, 0x01/*)*/, |
| 26942 | GIR_BuildMI, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26943 | GIR_AddTempRegister, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*TempRegID*//* 206(*/0xCE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26944 | GIR_AddSimpleTempRegister, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*TempRegID*//* 207(*/0xCF, 0x01/*)*/, |
| 26945 | GIR_AddImm, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 26946 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 207(*/0xCF, 0x01/*)*/, |
| 26947 | GIR_BuildMI, /*InsnID*//* 206(*/0xCE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26948 | GIR_AddTempRegister, /*InsnID*//* 206(*/0xCE, 0x01/*)*/, /*TempRegID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26949 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 206(*/0xCE, 0x01/*)*/, |
| 26950 | GIR_BuildMI, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26951 | GIR_AddTempRegister, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegID*//* 204(*/0xCC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26952 | GIR_AddSimpleTempRegister, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegID*//* 205(*/0xCD, 0x01/*)*/, |
| 26953 | GIR_AddSimpleTempRegister, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*TempRegID*//* 206(*/0xCE, 0x01/*)*/, |
| 26954 | GIR_AddImm8, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Imm*/1, |
| 26955 | GIR_ConstrainOperandRC, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26956 | GIR_ConstrainOperandRC, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26957 | GIR_ConstrainOperandRC, /*InsnID*//* 205(*/0xCD, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26958 | GIR_BuildMI, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26959 | GIR_AddTempRegister, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*TempRegID*//* 203(*/0xCB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26960 | GIR_AddSimpleTempRegister, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*TempRegID*//* 204(*/0xCC, 0x01/*)*/, |
| 26961 | GIR_AddImm8, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*Imm*/32, |
| 26962 | GIR_AddImm8, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, /*Imm*/31, |
| 26963 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 204(*/0xCC, 0x01/*)*/, |
| 26964 | GIR_BuildMI, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 26965 | GIR_AddTempRegister, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*TempRegID*//* 202(*/0xCA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26966 | GIR_AddSimpleTempRegister, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*TempRegID*//* 203(*/0xCB, 0x01/*)*/, |
| 26967 | GIR_AddImm, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 26968 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 203(*/0xCB, 0x01/*)*/, |
| 26969 | GIR_BuildMI, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 26970 | GIR_AddTempRegister, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*TempRegID*//* 201(*/0xC9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26971 | GIR_AddSimpleTempRegister, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*TempRegID*//* 202(*/0xCA, 0x01/*)*/, |
| 26972 | GIR_AddImm, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 26973 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 202(*/0xCA, 0x01/*)*/, |
| 26974 | GIR_BuildMI, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 26975 | GIR_AddTempRegister, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, /*TempRegID*//* 200(*/0xC8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26976 | GIR_AddImm, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 26977 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 201(*/0xC9, 0x01/*)*/, |
| 26978 | GIR_BuildMI, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 26979 | GIR_AddTempRegister, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*TempRegID*//* 199(*/0xC7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26980 | GIR_AddSimpleTempRegister, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*TempRegID*//* 200(*/0xC8, 0x01/*)*/, |
| 26981 | GIR_AddImm, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 26982 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 200(*/0xC8, 0x01/*)*/, |
| 26983 | GIR_BuildMI, /*InsnID*//* 199(*/0xC7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26984 | GIR_AddTempRegister, /*InsnID*//* 199(*/0xC7, 0x01/*)*/, /*TempRegID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26985 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 199(*/0xC7, 0x01/*)*/, |
| 26986 | GIR_BuildMI, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 26987 | GIR_AddTempRegister, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegID*//* 197(*/0xC5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26988 | GIR_AddSimpleTempRegister, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegID*//* 198(*/0xC6, 0x01/*)*/, |
| 26989 | GIR_AddSimpleTempRegister, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*TempRegID*//* 199(*/0xC7, 0x01/*)*/, |
| 26990 | GIR_AddImm8, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Imm*/1, |
| 26991 | GIR_ConstrainOperandRC, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26992 | GIR_ConstrainOperandRC, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 26993 | GIR_ConstrainOperandRC, /*InsnID*//* 198(*/0xC6, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 26994 | GIR_BuildMI, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 26995 | GIR_AddTempRegister, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*TempRegID*//* 196(*/0xC4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 26996 | GIR_AddSimpleTempRegister, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*TempRegID*//* 197(*/0xC5, 0x01/*)*/, |
| 26997 | GIR_AddImm8, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*Imm*/32, |
| 26998 | GIR_AddImm8, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, /*Imm*/31, |
| 26999 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 197(*/0xC5, 0x01/*)*/, |
| 27000 | GIR_BuildMI, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27001 | GIR_AddTempRegister, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*TempRegID*//* 195(*/0xC3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27002 | GIR_AddSimpleTempRegister, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*TempRegID*//* 196(*/0xC4, 0x01/*)*/, |
| 27003 | GIR_AddImm, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27004 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 196(*/0xC4, 0x01/*)*/, |
| 27005 | GIR_BuildMI, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27006 | GIR_AddTempRegister, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*TempRegID*//* 194(*/0xC2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27007 | GIR_AddSimpleTempRegister, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*TempRegID*//* 195(*/0xC3, 0x01/*)*/, |
| 27008 | GIR_AddImm, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27009 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 195(*/0xC3, 0x01/*)*/, |
| 27010 | GIR_BuildMI, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27011 | GIR_AddTempRegister, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, /*TempRegID*//* 193(*/0xC1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27012 | GIR_AddImm, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27013 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 194(*/0xC2, 0x01/*)*/, |
| 27014 | GIR_BuildMI, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27015 | GIR_AddTempRegister, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*TempRegID*//* 192(*/0xC0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27016 | GIR_AddSimpleTempRegister, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*TempRegID*//* 193(*/0xC1, 0x01/*)*/, |
| 27017 | GIR_AddImm, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27018 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 193(*/0xC1, 0x01/*)*/, |
| 27019 | GIR_BuildMI, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27020 | GIR_AddTempRegister, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27021 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 192(*/0xC0, 0x01/*)*/, |
| 27022 | GIR_BuildMI, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27023 | GIR_AddTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27024 | GIR_AddSimpleTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 191(*/0xBF, 0x01/*)*/, |
| 27025 | GIR_AddSimpleTempRegister, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*TempRegID*//* 192(*/0xC0, 0x01/*)*/, |
| 27026 | GIR_AddImm8, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Imm*/1, |
| 27027 | GIR_ConstrainOperandRC, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27028 | GIR_ConstrainOperandRC, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27029 | GIR_ConstrainOperandRC, /*InsnID*//* 191(*/0xBF, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27030 | GIR_BuildMI, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27031 | GIR_AddTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27032 | GIR_AddSimpleTempRegister, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*TempRegID*//* 190(*/0xBE, 0x01/*)*/, |
| 27033 | GIR_AddImm8, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/32, |
| 27034 | GIR_AddImm8, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, /*Imm*/31, |
| 27035 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 190(*/0xBE, 0x01/*)*/, |
| 27036 | GIR_BuildMI, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27037 | GIR_AddTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27038 | GIR_AddSimpleTempRegister, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*TempRegID*//* 189(*/0xBD, 0x01/*)*/, |
| 27039 | GIR_AddImm, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27040 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 189(*/0xBD, 0x01/*)*/, |
| 27041 | GIR_BuildMI, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27042 | GIR_AddTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27043 | GIR_AddSimpleTempRegister, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*TempRegID*//* 188(*/0xBC, 0x01/*)*/, |
| 27044 | GIR_AddImm, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27045 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 188(*/0xBC, 0x01/*)*/, |
| 27046 | GIR_BuildMI, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27047 | GIR_AddTempRegister, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27048 | GIR_Copy, /*NewInsnID*//* 187(*/0xBB, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27049 | GIR_AddImm8, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/1, |
| 27050 | GIR_AddImm8, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, /*Imm*/62, |
| 27051 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 187(*/0xBB, 0x01/*)*/, |
| 27052 | GIR_BuildMI, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27053 | GIR_AddTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27054 | GIR_AddSimpleTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 186(*/0xBA, 0x01/*)*/, |
| 27055 | GIR_AddSimpleTempRegister, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, /*TempRegID*//* 187(*/0xBB, 0x01/*)*/, |
| 27056 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 186(*/0xBA, 0x01/*)*/, |
| 27057 | GIR_BuildMI, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27058 | GIR_AddTempRegister, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27059 | GIR_AddImm, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27060 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 185(*/0xB9, 0x01/*)*/, |
| 27061 | GIR_BuildMI, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27062 | GIR_AddTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27063 | GIR_AddSimpleTempRegister, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*TempRegID*//* 184(*/0xB8, 0x01/*)*/, |
| 27064 | GIR_AddImm, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27065 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 184(*/0xB8, 0x01/*)*/, |
| 27066 | GIR_BuildMI, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27067 | GIR_AddTempRegister, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27068 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 183(*/0xB7, 0x01/*)*/, |
| 27069 | GIR_BuildMI, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27070 | GIR_AddTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27071 | GIR_AddSimpleTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 182(*/0xB6, 0x01/*)*/, |
| 27072 | GIR_AddSimpleTempRegister, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*TempRegID*//* 183(*/0xB7, 0x01/*)*/, |
| 27073 | GIR_AddImm8, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Imm*/1, |
| 27074 | GIR_ConstrainOperandRC, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27075 | GIR_ConstrainOperandRC, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27076 | GIR_ConstrainOperandRC, /*InsnID*//* 182(*/0xB6, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27077 | GIR_BuildMI, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27078 | GIR_AddTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27079 | GIR_AddSimpleTempRegister, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*TempRegID*//* 181(*/0xB5, 0x01/*)*/, |
| 27080 | GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/32, |
| 27081 | GIR_AddImm8, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, /*Imm*/31, |
| 27082 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 181(*/0xB5, 0x01/*)*/, |
| 27083 | GIR_BuildMI, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27084 | GIR_AddTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27085 | GIR_AddSimpleTempRegister, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*TempRegID*//* 180(*/0xB4, 0x01/*)*/, |
| 27086 | GIR_AddImm, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27087 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 180(*/0xB4, 0x01/*)*/, |
| 27088 | GIR_BuildMI, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27089 | GIR_AddTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27090 | GIR_AddSimpleTempRegister, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*TempRegID*//* 179(*/0xB3, 0x01/*)*/, |
| 27091 | GIR_AddImm, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27092 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 179(*/0xB3, 0x01/*)*/, |
| 27093 | GIR_BuildMI, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27094 | GIR_AddTempRegister, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27095 | GIR_Copy, /*NewInsnID*//* 178(*/0xB2, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27096 | GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/63, |
| 27097 | GIR_AddImm8, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, /*Imm*/1, |
| 27098 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 178(*/0xB2, 0x01/*)*/, |
| 27099 | GIR_BuildMI, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27100 | GIR_AddTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27101 | GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 177(*/0xB1, 0x01/*)*/, |
| 27102 | GIR_AddSimpleTempRegister, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, /*TempRegID*//* 178(*/0xB2, 0x01/*)*/, |
| 27103 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 177(*/0xB1, 0x01/*)*/, |
| 27104 | GIR_BuildMI, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27105 | GIR_AddTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27106 | GIR_AddSimpleTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 176(*/0xB0, 0x01/*)*/, |
| 27107 | GIR_AddSimpleTempRegister, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, /*TempRegID*//* 185(*/0xB9, 0x01/*)*/, |
| 27108 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 176(*/0xB0, 0x01/*)*/, |
| 27109 | GIR_BuildMI, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27110 | GIR_AddTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27111 | GIR_AddSimpleTempRegister, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*TempRegID*//* 175(*/0xAF, 0x01/*)*/, |
| 27112 | GIR_AddImm8, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/2, |
| 27113 | GIR_AddImm8, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, /*Imm*/61, |
| 27114 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 175(*/0xAF, 0x01/*)*/, |
| 27115 | GIR_BuildMI, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27116 | GIR_AddTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27117 | GIR_AddSimpleTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 174(*/0xAE, 0x01/*)*/, |
| 27118 | GIR_AddSimpleTempRegister, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, /*TempRegID*//* 194(*/0xC2, 0x01/*)*/, |
| 27119 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 174(*/0xAE, 0x01/*)*/, |
| 27120 | GIR_BuildMI, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27121 | GIR_AddTempRegister, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27122 | GIR_AddImm, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27123 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 173(*/0xAD, 0x01/*)*/, |
| 27124 | GIR_BuildMI, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27125 | GIR_AddTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27126 | GIR_AddSimpleTempRegister, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*TempRegID*//* 172(*/0xAC, 0x01/*)*/, |
| 27127 | GIR_AddImm, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27128 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 172(*/0xAC, 0x01/*)*/, |
| 27129 | GIR_BuildMI, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27130 | GIR_AddTempRegister, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27131 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 171(*/0xAB, 0x01/*)*/, |
| 27132 | GIR_BuildMI, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27133 | GIR_AddTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27134 | GIR_AddSimpleTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 170(*/0xAA, 0x01/*)*/, |
| 27135 | GIR_AddSimpleTempRegister, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*TempRegID*//* 171(*/0xAB, 0x01/*)*/, |
| 27136 | GIR_AddImm8, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Imm*/1, |
| 27137 | GIR_ConstrainOperandRC, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27138 | GIR_ConstrainOperandRC, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27139 | GIR_ConstrainOperandRC, /*InsnID*//* 170(*/0xAA, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27140 | GIR_BuildMI, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27141 | GIR_AddTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27142 | GIR_AddSimpleTempRegister, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*TempRegID*//* 169(*/0xA9, 0x01/*)*/, |
| 27143 | GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/32, |
| 27144 | GIR_AddImm8, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, /*Imm*/31, |
| 27145 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 169(*/0xA9, 0x01/*)*/, |
| 27146 | GIR_BuildMI, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27147 | GIR_AddTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27148 | GIR_AddSimpleTempRegister, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*TempRegID*//* 168(*/0xA8, 0x01/*)*/, |
| 27149 | GIR_AddImm, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27150 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 168(*/0xA8, 0x01/*)*/, |
| 27151 | GIR_BuildMI, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27152 | GIR_AddTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27153 | GIR_AddSimpleTempRegister, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*TempRegID*//* 167(*/0xA7, 0x01/*)*/, |
| 27154 | GIR_AddImm, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27155 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 167(*/0xA7, 0x01/*)*/, |
| 27156 | GIR_BuildMI, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27157 | GIR_AddTempRegister, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27158 | GIR_AddImm, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27159 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 166(*/0xA6, 0x01/*)*/, |
| 27160 | GIR_BuildMI, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27161 | GIR_AddTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27162 | GIR_AddSimpleTempRegister, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*TempRegID*//* 165(*/0xA5, 0x01/*)*/, |
| 27163 | GIR_AddImm, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27164 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 165(*/0xA5, 0x01/*)*/, |
| 27165 | GIR_BuildMI, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27166 | GIR_AddTempRegister, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27167 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 164(*/0xA4, 0x01/*)*/, |
| 27168 | GIR_BuildMI, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27169 | GIR_AddTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27170 | GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 163(*/0xA3, 0x01/*)*/, |
| 27171 | GIR_AddSimpleTempRegister, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*TempRegID*//* 164(*/0xA4, 0x01/*)*/, |
| 27172 | GIR_AddImm8, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Imm*/1, |
| 27173 | GIR_ConstrainOperandRC, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27174 | GIR_ConstrainOperandRC, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27175 | GIR_ConstrainOperandRC, /*InsnID*//* 163(*/0xA3, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27176 | GIR_BuildMI, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27177 | GIR_AddTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27178 | GIR_AddSimpleTempRegister, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*TempRegID*//* 162(*/0xA2, 0x01/*)*/, |
| 27179 | GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/32, |
| 27180 | GIR_AddImm8, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, /*Imm*/31, |
| 27181 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 162(*/0xA2, 0x01/*)*/, |
| 27182 | GIR_BuildMI, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27183 | GIR_AddTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27184 | GIR_AddSimpleTempRegister, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*TempRegID*//* 161(*/0xA1, 0x01/*)*/, |
| 27185 | GIR_AddImm, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27186 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 161(*/0xA1, 0x01/*)*/, |
| 27187 | GIR_BuildMI, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27188 | GIR_AddTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27189 | GIR_AddSimpleTempRegister, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*TempRegID*//* 160(*/0xA0, 0x01/*)*/, |
| 27190 | GIR_AddImm, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27191 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 160(*/0xA0, 0x01/*)*/, |
| 27192 | GIR_BuildMI, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27193 | GIR_AddTempRegister, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27194 | GIR_Copy, /*NewInsnID*//* 159(*/0x9F, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27195 | GIR_AddImm8, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/1, |
| 27196 | GIR_AddImm8, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, /*Imm*/62, |
| 27197 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 159(*/0x9F, 0x01/*)*/, |
| 27198 | GIR_BuildMI, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27199 | GIR_AddTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27200 | GIR_AddSimpleTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 158(*/0x9E, 0x01/*)*/, |
| 27201 | GIR_AddSimpleTempRegister, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, /*TempRegID*//* 159(*/0x9F, 0x01/*)*/, |
| 27202 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 158(*/0x9E, 0x01/*)*/, |
| 27203 | GIR_BuildMI, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27204 | GIR_AddTempRegister, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27205 | GIR_AddImm, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27206 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 157(*/0x9D, 0x01/*)*/, |
| 27207 | GIR_BuildMI, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27208 | GIR_AddTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27209 | GIR_AddSimpleTempRegister, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*TempRegID*//* 156(*/0x9C, 0x01/*)*/, |
| 27210 | GIR_AddImm, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27211 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 156(*/0x9C, 0x01/*)*/, |
| 27212 | GIR_BuildMI, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27213 | GIR_AddTempRegister, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27214 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 155(*/0x9B, 0x01/*)*/, |
| 27215 | GIR_BuildMI, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27216 | GIR_AddTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27217 | GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 154(*/0x9A, 0x01/*)*/, |
| 27218 | GIR_AddSimpleTempRegister, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*TempRegID*//* 155(*/0x9B, 0x01/*)*/, |
| 27219 | GIR_AddImm8, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Imm*/1, |
| 27220 | GIR_ConstrainOperandRC, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27221 | GIR_ConstrainOperandRC, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27222 | GIR_ConstrainOperandRC, /*InsnID*//* 154(*/0x9A, 0x01/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27223 | GIR_BuildMI, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27224 | GIR_AddTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27225 | GIR_AddSimpleTempRegister, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*TempRegID*//* 153(*/0x99, 0x01/*)*/, |
| 27226 | GIR_AddImm8, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Imm*/32, |
| 27227 | GIR_AddImm8, /*InsnID*//* 153(*/0x99, 0x01/*)*/, /*Imm*/31, |
| 27228 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 153(*/0x99, 0x01/*)*/, |
| 27229 | GIR_BuildMI, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27230 | GIR_AddTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27231 | GIR_AddSimpleTempRegister, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*TempRegID*//* 152(*/0x98, 0x01/*)*/, |
| 27232 | GIR_AddImm, /*InsnID*//* 152(*/0x98, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27233 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 152(*/0x98, 0x01/*)*/, |
| 27234 | GIR_BuildMI, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27235 | GIR_AddTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27236 | GIR_AddSimpleTempRegister, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*TempRegID*//* 151(*/0x97, 0x01/*)*/, |
| 27237 | GIR_AddImm, /*InsnID*//* 151(*/0x97, 0x01/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27238 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 151(*/0x97, 0x01/*)*/, |
| 27239 | GIR_BuildMI, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27240 | GIR_AddTempRegister, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27241 | GIR_Copy, /*NewInsnID*//* 150(*/0x96, 0x01/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27242 | GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/63, |
| 27243 | GIR_AddImm8, /*InsnID*//* 150(*/0x96, 0x01/*)*/, /*Imm*/1, |
| 27244 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 150(*/0x96, 0x01/*)*/, |
| 27245 | GIR_BuildMI, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27246 | GIR_AddTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27247 | GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 149(*/0x95, 0x01/*)*/, |
| 27248 | GIR_AddSimpleTempRegister, /*InsnID*//* 149(*/0x95, 0x01/*)*/, /*TempRegID*//* 150(*/0x96, 0x01/*)*/, |
| 27249 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 149(*/0x95, 0x01/*)*/, |
| 27250 | GIR_BuildMI, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27251 | GIR_AddTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27252 | GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 148(*/0x94, 0x01/*)*/, |
| 27253 | GIR_AddSimpleTempRegister, /*InsnID*//* 148(*/0x94, 0x01/*)*/, /*TempRegID*//* 157(*/0x9D, 0x01/*)*/, |
| 27254 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 148(*/0x94, 0x01/*)*/, |
| 27255 | GIR_BuildMI, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27256 | GIR_AddTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27257 | GIR_AddSimpleTempRegister, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*TempRegID*//* 147(*/0x93, 0x01/*)*/, |
| 27258 | GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/62, |
| 27259 | GIR_AddImm8, /*InsnID*//* 147(*/0x93, 0x01/*)*/, /*Imm*/2, |
| 27260 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 147(*/0x93, 0x01/*)*/, |
| 27261 | GIR_BuildMI, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27262 | GIR_AddTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27263 | GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 146(*/0x92, 0x01/*)*/, |
| 27264 | GIR_AddSimpleTempRegister, /*InsnID*//* 146(*/0x92, 0x01/*)*/, /*TempRegID*//* 166(*/0xA6, 0x01/*)*/, |
| 27265 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 146(*/0x92, 0x01/*)*/, |
| 27266 | GIR_BuildMI, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27267 | GIR_AddTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27268 | GIR_AddSimpleTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 145(*/0x91, 0x01/*)*/, |
| 27269 | GIR_AddSimpleTempRegister, /*InsnID*//* 145(*/0x91, 0x01/*)*/, /*TempRegID*//* 173(*/0xAD, 0x01/*)*/, |
| 27270 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 145(*/0x91, 0x01/*)*/, |
| 27271 | GIR_BuildMI, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27272 | GIR_AddTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27273 | GIR_AddSimpleTempRegister, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*TempRegID*//* 144(*/0x90, 0x01/*)*/, |
| 27274 | GIR_AddImm8, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/60, |
| 27275 | GIR_AddImm8, /*InsnID*//* 144(*/0x90, 0x01/*)*/, /*Imm*/4, |
| 27276 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 144(*/0x90, 0x01/*)*/, |
| 27277 | GIR_BuildMI, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27278 | GIR_AddTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27279 | GIR_AddSimpleTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 143(*/0x8F, 0x01/*)*/, |
| 27280 | GIR_AddSimpleTempRegister, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, /*TempRegID*//* 201(*/0xC9, 0x01/*)*/, |
| 27281 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 143(*/0x8F, 0x01/*)*/, |
| 27282 | GIR_BuildMI, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27283 | GIR_AddTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27284 | GIR_AddSimpleTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 142(*/0x8E, 0x01/*)*/, |
| 27285 | GIR_AddSimpleTempRegister, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, /*TempRegID*//* 208(*/0xD0, 0x01/*)*/, |
| 27286 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 142(*/0x8E, 0x01/*)*/, |
| 27287 | GIR_MakeTempReg, /*TempRegID*//* 274(*/0x92, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27288 | GIR_MakeTempReg, /*TempRegID*//* 275(*/0x93, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27289 | GIR_MakeTempReg, /*TempRegID*//* 276(*/0x94, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27290 | GIR_MakeTempReg, /*TempRegID*//* 277(*/0x95, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27291 | GIR_MakeTempReg, /*TempRegID*//* 278(*/0x96, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27292 | GIR_MakeTempReg, /*TempRegID*//* 279(*/0x97, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27293 | GIR_MakeTempReg, /*TempRegID*//* 280(*/0x98, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27294 | GIR_MakeTempReg, /*TempRegID*//* 281(*/0x99, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27295 | GIR_MakeTempReg, /*TempRegID*//* 282(*/0x9A, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27296 | GIR_MakeTempReg, /*TempRegID*//* 283(*/0x9B, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27297 | GIR_MakeTempReg, /*TempRegID*//* 284(*/0x9C, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27298 | GIR_MakeTempReg, /*TempRegID*//* 285(*/0x9D, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27299 | GIR_MakeTempReg, /*TempRegID*//* 286(*/0x9E, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27300 | GIR_MakeTempReg, /*TempRegID*//* 287(*/0x9F, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27301 | GIR_MakeTempReg, /*TempRegID*//* 288(*/0xA0, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27302 | GIR_MakeTempReg, /*TempRegID*//* 289(*/0xA1, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27303 | GIR_MakeTempReg, /*TempRegID*//* 290(*/0xA2, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27304 | GIR_MakeTempReg, /*TempRegID*//* 291(*/0xA3, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27305 | GIR_MakeTempReg, /*TempRegID*//* 292(*/0xA4, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27306 | GIR_MakeTempReg, /*TempRegID*//* 293(*/0xA5, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27307 | GIR_MakeTempReg, /*TempRegID*//* 294(*/0xA6, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27308 | GIR_MakeTempReg, /*TempRegID*//* 295(*/0xA7, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27309 | GIR_MakeTempReg, /*TempRegID*//* 296(*/0xA8, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27310 | GIR_MakeTempReg, /*TempRegID*//* 297(*/0xA9, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27311 | GIR_MakeTempReg, /*TempRegID*//* 298(*/0xAA, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27312 | GIR_MakeTempReg, /*TempRegID*//* 299(*/0xAB, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27313 | GIR_MakeTempReg, /*TempRegID*//* 300(*/0xAC, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27314 | GIR_MakeTempReg, /*TempRegID*//* 301(*/0xAD, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27315 | GIR_MakeTempReg, /*TempRegID*//* 302(*/0xAE, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27316 | GIR_MakeTempReg, /*TempRegID*//* 303(*/0xAF, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27317 | GIR_MakeTempReg, /*TempRegID*//* 304(*/0xB0, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27318 | GIR_MakeTempReg, /*TempRegID*//* 305(*/0xB1, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27319 | GIR_MakeTempReg, /*TempRegID*//* 306(*/0xB2, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27320 | GIR_MakeTempReg, /*TempRegID*//* 307(*/0xB3, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27321 | GIR_MakeTempReg, /*TempRegID*//* 308(*/0xB4, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27322 | GIR_MakeTempReg, /*TempRegID*//* 309(*/0xB5, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27323 | GIR_MakeTempReg, /*TempRegID*//* 310(*/0xB6, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27324 | GIR_MakeTempReg, /*TempRegID*//* 311(*/0xB7, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27325 | GIR_MakeTempReg, /*TempRegID*//* 312(*/0xB8, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27326 | GIR_MakeTempReg, /*TempRegID*//* 313(*/0xB9, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27327 | GIR_MakeTempReg, /*TempRegID*//* 314(*/0xBA, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27328 | GIR_MakeTempReg, /*TempRegID*//* 315(*/0xBB, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27329 | GIR_MakeTempReg, /*TempRegID*//* 316(*/0xBC, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27330 | GIR_MakeTempReg, /*TempRegID*//* 317(*/0xBD, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27331 | GIR_MakeTempReg, /*TempRegID*//* 318(*/0xBE, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27332 | GIR_MakeTempReg, /*TempRegID*//* 319(*/0xBF, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27333 | GIR_MakeTempReg, /*TempRegID*//* 320(*/0xC0, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27334 | GIR_MakeTempReg, /*TempRegID*//* 321(*/0xC1, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27335 | GIR_MakeTempReg, /*TempRegID*//* 322(*/0xC2, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27336 | GIR_MakeTempReg, /*TempRegID*//* 323(*/0xC3, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27337 | GIR_MakeTempReg, /*TempRegID*//* 324(*/0xC4, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27338 | GIR_MakeTempReg, /*TempRegID*//* 325(*/0xC5, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27339 | GIR_MakeTempReg, /*TempRegID*//* 326(*/0xC6, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27340 | GIR_MakeTempReg, /*TempRegID*//* 327(*/0xC7, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27341 | GIR_MakeTempReg, /*TempRegID*//* 328(*/0xC8, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27342 | GIR_MakeTempReg, /*TempRegID*//* 329(*/0xC9, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27343 | GIR_MakeTempReg, /*TempRegID*//* 330(*/0xCA, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27344 | GIR_MakeTempReg, /*TempRegID*//* 331(*/0xCB, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27345 | GIR_MakeTempReg, /*TempRegID*//* 332(*/0xCC, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27346 | GIR_MakeTempReg, /*TempRegID*//* 333(*/0xCD, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27347 | GIR_MakeTempReg, /*TempRegID*//* 334(*/0xCE, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27348 | GIR_MakeTempReg, /*TempRegID*//* 335(*/0xCF, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27349 | GIR_MakeTempReg, /*TempRegID*//* 336(*/0xD0, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27350 | GIR_MakeTempReg, /*TempRegID*//* 337(*/0xD1, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27351 | GIR_MakeTempReg, /*TempRegID*//* 338(*/0xD2, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27352 | GIR_MakeTempReg, /*TempRegID*//* 339(*/0xD3, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27353 | GIR_MakeTempReg, /*TempRegID*//* 340(*/0xD4, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27354 | GIR_MakeTempReg, /*TempRegID*//* 341(*/0xD5, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27355 | GIR_MakeTempReg, /*TempRegID*//* 342(*/0xD6, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27356 | GIR_MakeTempReg, /*TempRegID*//* 343(*/0xD7, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27357 | GIR_MakeTempReg, /*TempRegID*//* 344(*/0xD8, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27358 | GIR_MakeTempReg, /*TempRegID*//* 345(*/0xD9, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27359 | GIR_MakeTempReg, /*TempRegID*//* 346(*/0xDA, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27360 | GIR_MakeTempReg, /*TempRegID*//* 347(*/0xDB, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27361 | GIR_MakeTempReg, /*TempRegID*//* 348(*/0xDC, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27362 | GIR_MakeTempReg, /*TempRegID*//* 349(*/0xDD, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27363 | GIR_MakeTempReg, /*TempRegID*//* 350(*/0xDE, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27364 | GIR_MakeTempReg, /*TempRegID*//* 351(*/0xDF, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27365 | GIR_MakeTempReg, /*TempRegID*//* 352(*/0xE0, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27366 | GIR_MakeTempReg, /*TempRegID*//* 353(*/0xE1, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27367 | GIR_MakeTempReg, /*TempRegID*//* 354(*/0xE2, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27368 | GIR_MakeTempReg, /*TempRegID*//* 355(*/0xE3, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27369 | GIR_MakeTempReg, /*TempRegID*//* 356(*/0xE4, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27370 | GIR_MakeTempReg, /*TempRegID*//* 357(*/0xE5, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27371 | GIR_MakeTempReg, /*TempRegID*//* 358(*/0xE6, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27372 | GIR_MakeTempReg, /*TempRegID*//* 359(*/0xE7, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27373 | GIR_MakeTempReg, /*TempRegID*//* 360(*/0xE8, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27374 | GIR_MakeTempReg, /*TempRegID*//* 361(*/0xE9, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27375 | GIR_MakeTempReg, /*TempRegID*//* 362(*/0xEA, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27376 | GIR_MakeTempReg, /*TempRegID*//* 363(*/0xEB, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27377 | GIR_MakeTempReg, /*TempRegID*//* 364(*/0xEC, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27378 | GIR_MakeTempReg, /*TempRegID*//* 365(*/0xED, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27379 | GIR_MakeTempReg, /*TempRegID*//* 366(*/0xEE, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27380 | GIR_MakeTempReg, /*TempRegID*//* 367(*/0xEF, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27381 | GIR_MakeTempReg, /*TempRegID*//* 368(*/0xF0, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27382 | GIR_MakeTempReg, /*TempRegID*//* 369(*/0xF1, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27383 | GIR_MakeTempReg, /*TempRegID*//* 370(*/0xF2, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27384 | GIR_MakeTempReg, /*TempRegID*//* 371(*/0xF3, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27385 | GIR_MakeTempReg, /*TempRegID*//* 372(*/0xF4, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27386 | GIR_MakeTempReg, /*TempRegID*//* 373(*/0xF5, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27387 | GIR_MakeTempReg, /*TempRegID*//* 374(*/0xF6, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27388 | GIR_MakeTempReg, /*TempRegID*//* 375(*/0xF7, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27389 | GIR_MakeTempReg, /*TempRegID*//* 376(*/0xF8, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27390 | GIR_MakeTempReg, /*TempRegID*//* 377(*/0xF9, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27391 | GIR_MakeTempReg, /*TempRegID*//* 378(*/0xFA, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27392 | GIR_MakeTempReg, /*TempRegID*//* 379(*/0xFB, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27393 | GIR_MakeTempReg, /*TempRegID*//* 380(*/0xFC, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27394 | GIR_MakeTempReg, /*TempRegID*//* 381(*/0xFD, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27395 | GIR_MakeTempReg, /*TempRegID*//* 382(*/0xFE, 0x02/*)*/, /*TypeID*/GILLT_s64, |
| 27396 | GIR_MakeTempReg, /*TempRegID*//* 383(*/0xFF, 0x02/*)*/, /*TypeID*/GILLT_s32, |
| 27397 | GIR_MakeTempReg, /*TempRegID*//* 384(*/0x80, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27398 | GIR_MakeTempReg, /*TempRegID*//* 385(*/0x81, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27399 | GIR_MakeTempReg, /*TempRegID*//* 386(*/0x82, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27400 | GIR_MakeTempReg, /*TempRegID*//* 387(*/0x83, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27401 | GIR_MakeTempReg, /*TempRegID*//* 388(*/0x84, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27402 | GIR_MakeTempReg, /*TempRegID*//* 389(*/0x85, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27403 | GIR_MakeTempReg, /*TempRegID*//* 390(*/0x86, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27404 | GIR_MakeTempReg, /*TempRegID*//* 391(*/0x87, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27405 | GIR_MakeTempReg, /*TempRegID*//* 392(*/0x88, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27406 | GIR_MakeTempReg, /*TempRegID*//* 393(*/0x89, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27407 | GIR_MakeTempReg, /*TempRegID*//* 394(*/0x8A, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27408 | GIR_MakeTempReg, /*TempRegID*//* 395(*/0x8B, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27409 | GIR_MakeTempReg, /*TempRegID*//* 396(*/0x8C, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27410 | GIR_MakeTempReg, /*TempRegID*//* 397(*/0x8D, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27411 | GIR_MakeTempReg, /*TempRegID*//* 398(*/0x8E, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27412 | GIR_MakeTempReg, /*TempRegID*//* 399(*/0x8F, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27413 | GIR_MakeTempReg, /*TempRegID*//* 400(*/0x90, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27414 | GIR_MakeTempReg, /*TempRegID*//* 401(*/0x91, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27415 | GIR_MakeTempReg, /*TempRegID*//* 402(*/0x92, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27416 | GIR_MakeTempReg, /*TempRegID*//* 403(*/0x93, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27417 | GIR_MakeTempReg, /*TempRegID*//* 404(*/0x94, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27418 | GIR_MakeTempReg, /*TempRegID*//* 405(*/0x95, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 27419 | GIR_MakeTempReg, /*TempRegID*//* 406(*/0x96, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27420 | GIR_MakeTempReg, /*TempRegID*//* 407(*/0x97, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 27421 | GIR_BuildMI, /*InsnID*//* 408(*/0x98, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27422 | GIR_AddTempRegister, /*InsnID*//* 408(*/0x98, 0x03/*)*/, /*TempRegID*//* 407(*/0x97, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27423 | GIR_AddImm, /*InsnID*//* 408(*/0x98, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 27424 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 408(*/0x98, 0x03/*)*/, |
| 27425 | GIR_BuildMI, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27426 | GIR_AddTempRegister, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*TempRegID*//* 406(*/0x96, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27427 | GIR_AddSimpleTempRegister, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*TempRegID*//* 407(*/0x97, 0x03/*)*/, |
| 27428 | GIR_AddImm, /*InsnID*//* 407(*/0x97, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 27429 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 407(*/0x97, 0x03/*)*/, |
| 27430 | GIR_BuildMI, /*InsnID*//* 406(*/0x96, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27431 | GIR_AddTempRegister, /*InsnID*//* 406(*/0x96, 0x03/*)*/, /*TempRegID*//* 405(*/0x95, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27432 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 406(*/0x96, 0x03/*)*/, |
| 27433 | GIR_BuildMI, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27434 | GIR_AddTempRegister, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*TempRegID*//* 404(*/0x94, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27435 | GIR_AddSimpleTempRegister, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*TempRegID*//* 405(*/0x95, 0x03/*)*/, |
| 27436 | GIR_AddSimpleTempRegister, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*TempRegID*//* 406(*/0x96, 0x03/*)*/, |
| 27437 | GIR_AddImm8, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Imm*/1, |
| 27438 | GIR_ConstrainOperandRC, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27439 | GIR_ConstrainOperandRC, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27440 | GIR_ConstrainOperandRC, /*InsnID*//* 405(*/0x95, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27441 | GIR_BuildMI, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27442 | GIR_AddTempRegister, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*TempRegID*//* 403(*/0x93, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27443 | GIR_AddSimpleTempRegister, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*TempRegID*//* 404(*/0x94, 0x03/*)*/, |
| 27444 | GIR_AddImm8, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*Imm*/32, |
| 27445 | GIR_AddImm8, /*InsnID*//* 404(*/0x94, 0x03/*)*/, /*Imm*/31, |
| 27446 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 404(*/0x94, 0x03/*)*/, |
| 27447 | GIR_BuildMI, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27448 | GIR_AddTempRegister, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*TempRegID*//* 402(*/0x92, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27449 | GIR_AddSimpleTempRegister, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*TempRegID*//* 403(*/0x93, 0x03/*)*/, |
| 27450 | GIR_AddImm, /*InsnID*//* 403(*/0x93, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 27451 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 403(*/0x93, 0x03/*)*/, |
| 27452 | GIR_BuildMI, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27453 | GIR_AddTempRegister, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*TempRegID*//* 401(*/0x91, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27454 | GIR_AddSimpleTempRegister, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*TempRegID*//* 402(*/0x92, 0x03/*)*/, |
| 27455 | GIR_AddImm, /*InsnID*//* 402(*/0x92, 0x03/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 27456 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 402(*/0x92, 0x03/*)*/, |
| 27457 | GIR_BuildMI, /*InsnID*//* 401(*/0x91, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27458 | GIR_AddTempRegister, /*InsnID*//* 401(*/0x91, 0x03/*)*/, /*TempRegID*//* 400(*/0x90, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27459 | GIR_AddImm, /*InsnID*//* 401(*/0x91, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27460 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 401(*/0x91, 0x03/*)*/, |
| 27461 | GIR_BuildMI, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27462 | GIR_AddTempRegister, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*TempRegID*//* 399(*/0x8F, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27463 | GIR_AddSimpleTempRegister, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*TempRegID*//* 400(*/0x90, 0x03/*)*/, |
| 27464 | GIR_AddImm, /*InsnID*//* 400(*/0x90, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27465 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 400(*/0x90, 0x03/*)*/, |
| 27466 | GIR_BuildMI, /*InsnID*//* 399(*/0x8F, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27467 | GIR_AddTempRegister, /*InsnID*//* 399(*/0x8F, 0x03/*)*/, /*TempRegID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27468 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 399(*/0x8F, 0x03/*)*/, |
| 27469 | GIR_BuildMI, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27470 | GIR_AddTempRegister, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegID*//* 397(*/0x8D, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27471 | GIR_AddSimpleTempRegister, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegID*//* 398(*/0x8E, 0x03/*)*/, |
| 27472 | GIR_AddSimpleTempRegister, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*TempRegID*//* 399(*/0x8F, 0x03/*)*/, |
| 27473 | GIR_AddImm8, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Imm*/1, |
| 27474 | GIR_ConstrainOperandRC, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27475 | GIR_ConstrainOperandRC, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27476 | GIR_ConstrainOperandRC, /*InsnID*//* 398(*/0x8E, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27477 | GIR_BuildMI, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27478 | GIR_AddTempRegister, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*TempRegID*//* 396(*/0x8C, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27479 | GIR_AddSimpleTempRegister, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*TempRegID*//* 397(*/0x8D, 0x03/*)*/, |
| 27480 | GIR_AddImm8, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*Imm*/32, |
| 27481 | GIR_AddImm8, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, /*Imm*/31, |
| 27482 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 397(*/0x8D, 0x03/*)*/, |
| 27483 | GIR_BuildMI, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27484 | GIR_AddTempRegister, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*TempRegID*//* 395(*/0x8B, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27485 | GIR_AddSimpleTempRegister, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*TempRegID*//* 396(*/0x8C, 0x03/*)*/, |
| 27486 | GIR_AddImm, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27487 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 396(*/0x8C, 0x03/*)*/, |
| 27488 | GIR_BuildMI, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27489 | GIR_AddTempRegister, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*TempRegID*//* 394(*/0x8A, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27490 | GIR_AddSimpleTempRegister, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*TempRegID*//* 395(*/0x8B, 0x03/*)*/, |
| 27491 | GIR_AddImm, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27492 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 395(*/0x8B, 0x03/*)*/, |
| 27493 | GIR_BuildMI, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27494 | GIR_AddTempRegister, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, /*TempRegID*//* 393(*/0x89, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27495 | GIR_AddImm, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27496 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 394(*/0x8A, 0x03/*)*/, |
| 27497 | GIR_BuildMI, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27498 | GIR_AddTempRegister, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*TempRegID*//* 392(*/0x88, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27499 | GIR_AddSimpleTempRegister, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*TempRegID*//* 393(*/0x89, 0x03/*)*/, |
| 27500 | GIR_AddImm, /*InsnID*//* 393(*/0x89, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27501 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 393(*/0x89, 0x03/*)*/, |
| 27502 | GIR_BuildMI, /*InsnID*//* 392(*/0x88, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27503 | GIR_AddTempRegister, /*InsnID*//* 392(*/0x88, 0x03/*)*/, /*TempRegID*//* 391(*/0x87, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27504 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 392(*/0x88, 0x03/*)*/, |
| 27505 | GIR_BuildMI, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27506 | GIR_AddTempRegister, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*TempRegID*//* 390(*/0x86, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27507 | GIR_AddSimpleTempRegister, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*TempRegID*//* 391(*/0x87, 0x03/*)*/, |
| 27508 | GIR_AddSimpleTempRegister, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*TempRegID*//* 392(*/0x88, 0x03/*)*/, |
| 27509 | GIR_AddImm8, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Imm*/1, |
| 27510 | GIR_ConstrainOperandRC, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27511 | GIR_ConstrainOperandRC, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27512 | GIR_ConstrainOperandRC, /*InsnID*//* 391(*/0x87, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27513 | GIR_BuildMI, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27514 | GIR_AddTempRegister, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*TempRegID*//* 389(*/0x85, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27515 | GIR_AddSimpleTempRegister, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*TempRegID*//* 390(*/0x86, 0x03/*)*/, |
| 27516 | GIR_AddImm8, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*Imm*/32, |
| 27517 | GIR_AddImm8, /*InsnID*//* 390(*/0x86, 0x03/*)*/, /*Imm*/31, |
| 27518 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 390(*/0x86, 0x03/*)*/, |
| 27519 | GIR_BuildMI, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27520 | GIR_AddTempRegister, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*TempRegID*//* 388(*/0x84, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27521 | GIR_AddSimpleTempRegister, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*TempRegID*//* 389(*/0x85, 0x03/*)*/, |
| 27522 | GIR_AddImm, /*InsnID*//* 389(*/0x85, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27523 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 389(*/0x85, 0x03/*)*/, |
| 27524 | GIR_BuildMI, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27525 | GIR_AddTempRegister, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*TempRegID*//* 387(*/0x83, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27526 | GIR_AddSimpleTempRegister, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*TempRegID*//* 388(*/0x84, 0x03/*)*/, |
| 27527 | GIR_AddImm, /*InsnID*//* 388(*/0x84, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27528 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 388(*/0x84, 0x03/*)*/, |
| 27529 | GIR_BuildMI, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27530 | GIR_AddTempRegister, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*TempRegID*//* 386(*/0x82, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27531 | GIR_Copy, /*NewInsnID*//* 387(*/0x83, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27532 | GIR_AddImm8, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*Imm*/1, |
| 27533 | GIR_AddImm8, /*InsnID*//* 387(*/0x83, 0x03/*)*/, /*Imm*/62, |
| 27534 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 387(*/0x83, 0x03/*)*/, |
| 27535 | GIR_BuildMI, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27536 | GIR_AddTempRegister, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*TempRegID*//* 385(*/0x81, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27537 | GIR_AddSimpleTempRegister, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*TempRegID*//* 386(*/0x82, 0x03/*)*/, |
| 27538 | GIR_AddSimpleTempRegister, /*InsnID*//* 386(*/0x82, 0x03/*)*/, /*TempRegID*//* 387(*/0x83, 0x03/*)*/, |
| 27539 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 386(*/0x82, 0x03/*)*/, |
| 27540 | GIR_BuildMI, /*InsnID*//* 385(*/0x81, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27541 | GIR_AddTempRegister, /*InsnID*//* 385(*/0x81, 0x03/*)*/, /*TempRegID*//* 384(*/0x80, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27542 | GIR_AddImm, /*InsnID*//* 385(*/0x81, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27543 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 385(*/0x81, 0x03/*)*/, |
| 27544 | GIR_BuildMI, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27545 | GIR_AddTempRegister, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*TempRegID*//* 383(*/0xFF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27546 | GIR_AddSimpleTempRegister, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*TempRegID*//* 384(*/0x80, 0x03/*)*/, |
| 27547 | GIR_AddImm, /*InsnID*//* 384(*/0x80, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27548 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 384(*/0x80, 0x03/*)*/, |
| 27549 | GIR_BuildMI, /*InsnID*//* 383(*/0xFF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27550 | GIR_AddTempRegister, /*InsnID*//* 383(*/0xFF, 0x02/*)*/, /*TempRegID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27551 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 383(*/0xFF, 0x02/*)*/, |
| 27552 | GIR_BuildMI, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27553 | GIR_AddTempRegister, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegID*//* 381(*/0xFD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27554 | GIR_AddSimpleTempRegister, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegID*//* 382(*/0xFE, 0x02/*)*/, |
| 27555 | GIR_AddSimpleTempRegister, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*TempRegID*//* 383(*/0xFF, 0x02/*)*/, |
| 27556 | GIR_AddImm8, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Imm*/1, |
| 27557 | GIR_ConstrainOperandRC, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27558 | GIR_ConstrainOperandRC, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27559 | GIR_ConstrainOperandRC, /*InsnID*//* 382(*/0xFE, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27560 | GIR_BuildMI, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27561 | GIR_AddTempRegister, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*TempRegID*//* 380(*/0xFC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27562 | GIR_AddSimpleTempRegister, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*TempRegID*//* 381(*/0xFD, 0x02/*)*/, |
| 27563 | GIR_AddImm8, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*Imm*/32, |
| 27564 | GIR_AddImm8, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, /*Imm*/31, |
| 27565 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 381(*/0xFD, 0x02/*)*/, |
| 27566 | GIR_BuildMI, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27567 | GIR_AddTempRegister, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*TempRegID*//* 379(*/0xFB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27568 | GIR_AddSimpleTempRegister, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*TempRegID*//* 380(*/0xFC, 0x02/*)*/, |
| 27569 | GIR_AddImm, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27570 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 380(*/0xFC, 0x02/*)*/, |
| 27571 | GIR_BuildMI, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27572 | GIR_AddTempRegister, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*TempRegID*//* 378(*/0xFA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27573 | GIR_AddSimpleTempRegister, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*TempRegID*//* 379(*/0xFB, 0x02/*)*/, |
| 27574 | GIR_AddImm, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27575 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 379(*/0xFB, 0x02/*)*/, |
| 27576 | GIR_BuildMI, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27577 | GIR_AddTempRegister, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*TempRegID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27578 | GIR_Copy, /*NewInsnID*//* 378(*/0xFA, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27579 | GIR_AddImm8, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*Imm*/63, |
| 27580 | GIR_AddImm8, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, /*Imm*/1, |
| 27581 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 378(*/0xFA, 0x02/*)*/, |
| 27582 | GIR_BuildMI, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27583 | GIR_AddTempRegister, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27584 | GIR_AddSimpleTempRegister, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegID*//* 377(*/0xF9, 0x02/*)*/, |
| 27585 | GIR_AddSimpleTempRegister, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, /*TempRegID*//* 378(*/0xFA, 0x02/*)*/, |
| 27586 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 377(*/0xF9, 0x02/*)*/, |
| 27587 | GIR_BuildMI, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27588 | GIR_AddTempRegister, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegID*//* 375(*/0xF7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27589 | GIR_AddSimpleTempRegister, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegID*//* 376(*/0xF8, 0x02/*)*/, |
| 27590 | GIR_AddSimpleTempRegister, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, /*TempRegID*//* 385(*/0x81, 0x03/*)*/, |
| 27591 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 376(*/0xF8, 0x02/*)*/, |
| 27592 | GIR_BuildMI, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27593 | GIR_AddTempRegister, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*TempRegID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27594 | GIR_AddSimpleTempRegister, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*TempRegID*//* 375(*/0xF7, 0x02/*)*/, |
| 27595 | GIR_AddImm8, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*Imm*/2, |
| 27596 | GIR_AddImm8, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, /*Imm*/61, |
| 27597 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 375(*/0xF7, 0x02/*)*/, |
| 27598 | GIR_BuildMI, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27599 | GIR_AddTempRegister, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegID*//* 373(*/0xF5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27600 | GIR_AddSimpleTempRegister, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegID*//* 374(*/0xF6, 0x02/*)*/, |
| 27601 | GIR_AddSimpleTempRegister, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, /*TempRegID*//* 394(*/0x8A, 0x03/*)*/, |
| 27602 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 374(*/0xF6, 0x02/*)*/, |
| 27603 | GIR_BuildMI, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27604 | GIR_AddTempRegister, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, /*TempRegID*//* 372(*/0xF4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27605 | GIR_AddImm, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27606 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 373(*/0xF5, 0x02/*)*/, |
| 27607 | GIR_BuildMI, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27608 | GIR_AddTempRegister, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*TempRegID*//* 371(*/0xF3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27609 | GIR_AddSimpleTempRegister, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*TempRegID*//* 372(*/0xF4, 0x02/*)*/, |
| 27610 | GIR_AddImm, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27611 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 372(*/0xF4, 0x02/*)*/, |
| 27612 | GIR_BuildMI, /*InsnID*//* 371(*/0xF3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27613 | GIR_AddTempRegister, /*InsnID*//* 371(*/0xF3, 0x02/*)*/, /*TempRegID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27614 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 371(*/0xF3, 0x02/*)*/, |
| 27615 | GIR_BuildMI, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27616 | GIR_AddTempRegister, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegID*//* 369(*/0xF1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27617 | GIR_AddSimpleTempRegister, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegID*//* 370(*/0xF2, 0x02/*)*/, |
| 27618 | GIR_AddSimpleTempRegister, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*TempRegID*//* 371(*/0xF3, 0x02/*)*/, |
| 27619 | GIR_AddImm8, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Imm*/1, |
| 27620 | GIR_ConstrainOperandRC, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27621 | GIR_ConstrainOperandRC, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27622 | GIR_ConstrainOperandRC, /*InsnID*//* 370(*/0xF2, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27623 | GIR_BuildMI, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27624 | GIR_AddTempRegister, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*TempRegID*//* 368(*/0xF0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27625 | GIR_AddSimpleTempRegister, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*TempRegID*//* 369(*/0xF1, 0x02/*)*/, |
| 27626 | GIR_AddImm8, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*Imm*/32, |
| 27627 | GIR_AddImm8, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, /*Imm*/31, |
| 27628 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 369(*/0xF1, 0x02/*)*/, |
| 27629 | GIR_BuildMI, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27630 | GIR_AddTempRegister, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*TempRegID*//* 367(*/0xEF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27631 | GIR_AddSimpleTempRegister, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*TempRegID*//* 368(*/0xF0, 0x02/*)*/, |
| 27632 | GIR_AddImm, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27633 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 368(*/0xF0, 0x02/*)*/, |
| 27634 | GIR_BuildMI, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27635 | GIR_AddTempRegister, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*TempRegID*//* 366(*/0xEE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27636 | GIR_AddSimpleTempRegister, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*TempRegID*//* 367(*/0xEF, 0x02/*)*/, |
| 27637 | GIR_AddImm, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27638 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 367(*/0xEF, 0x02/*)*/, |
| 27639 | GIR_BuildMI, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27640 | GIR_AddTempRegister, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, /*TempRegID*//* 365(*/0xED, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27641 | GIR_AddImm, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27642 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 366(*/0xEE, 0x02/*)*/, |
| 27643 | GIR_BuildMI, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27644 | GIR_AddTempRegister, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*TempRegID*//* 364(*/0xEC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27645 | GIR_AddSimpleTempRegister, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*TempRegID*//* 365(*/0xED, 0x02/*)*/, |
| 27646 | GIR_AddImm, /*InsnID*//* 365(*/0xED, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27647 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 365(*/0xED, 0x02/*)*/, |
| 27648 | GIR_BuildMI, /*InsnID*//* 364(*/0xEC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27649 | GIR_AddTempRegister, /*InsnID*//* 364(*/0xEC, 0x02/*)*/, /*TempRegID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27650 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 364(*/0xEC, 0x02/*)*/, |
| 27651 | GIR_BuildMI, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27652 | GIR_AddTempRegister, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegID*//* 362(*/0xEA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27653 | GIR_AddSimpleTempRegister, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegID*//* 363(*/0xEB, 0x02/*)*/, |
| 27654 | GIR_AddSimpleTempRegister, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*TempRegID*//* 364(*/0xEC, 0x02/*)*/, |
| 27655 | GIR_AddImm8, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Imm*/1, |
| 27656 | GIR_ConstrainOperandRC, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27657 | GIR_ConstrainOperandRC, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27658 | GIR_ConstrainOperandRC, /*InsnID*//* 363(*/0xEB, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27659 | GIR_BuildMI, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27660 | GIR_AddTempRegister, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*TempRegID*//* 361(*/0xE9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27661 | GIR_AddSimpleTempRegister, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*TempRegID*//* 362(*/0xEA, 0x02/*)*/, |
| 27662 | GIR_AddImm8, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*Imm*/32, |
| 27663 | GIR_AddImm8, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, /*Imm*/31, |
| 27664 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 362(*/0xEA, 0x02/*)*/, |
| 27665 | GIR_BuildMI, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27666 | GIR_AddTempRegister, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*TempRegID*//* 360(*/0xE8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27667 | GIR_AddSimpleTempRegister, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*TempRegID*//* 361(*/0xE9, 0x02/*)*/, |
| 27668 | GIR_AddImm, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27669 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 361(*/0xE9, 0x02/*)*/, |
| 27670 | GIR_BuildMI, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27671 | GIR_AddTempRegister, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*TempRegID*//* 359(*/0xE7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27672 | GIR_AddSimpleTempRegister, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*TempRegID*//* 360(*/0xE8, 0x02/*)*/, |
| 27673 | GIR_AddImm, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27674 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 360(*/0xE8, 0x02/*)*/, |
| 27675 | GIR_BuildMI, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27676 | GIR_AddTempRegister, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*TempRegID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27677 | GIR_Copy, /*NewInsnID*//* 359(*/0xE7, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27678 | GIR_AddImm8, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*Imm*/1, |
| 27679 | GIR_AddImm8, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, /*Imm*/62, |
| 27680 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 359(*/0xE7, 0x02/*)*/, |
| 27681 | GIR_BuildMI, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27682 | GIR_AddTempRegister, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegID*//* 357(*/0xE5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27683 | GIR_AddSimpleTempRegister, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegID*//* 358(*/0xE6, 0x02/*)*/, |
| 27684 | GIR_AddSimpleTempRegister, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, /*TempRegID*//* 359(*/0xE7, 0x02/*)*/, |
| 27685 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 358(*/0xE6, 0x02/*)*/, |
| 27686 | GIR_BuildMI, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27687 | GIR_AddTempRegister, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, /*TempRegID*//* 356(*/0xE4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27688 | GIR_AddImm, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27689 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 357(*/0xE5, 0x02/*)*/, |
| 27690 | GIR_BuildMI, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27691 | GIR_AddTempRegister, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*TempRegID*//* 355(*/0xE3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27692 | GIR_AddSimpleTempRegister, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*TempRegID*//* 356(*/0xE4, 0x02/*)*/, |
| 27693 | GIR_AddImm, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27694 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 356(*/0xE4, 0x02/*)*/, |
| 27695 | GIR_BuildMI, /*InsnID*//* 355(*/0xE3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27696 | GIR_AddTempRegister, /*InsnID*//* 355(*/0xE3, 0x02/*)*/, /*TempRegID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27697 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 355(*/0xE3, 0x02/*)*/, |
| 27698 | GIR_BuildMI, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27699 | GIR_AddTempRegister, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegID*//* 353(*/0xE1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27700 | GIR_AddSimpleTempRegister, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegID*//* 354(*/0xE2, 0x02/*)*/, |
| 27701 | GIR_AddSimpleTempRegister, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*TempRegID*//* 355(*/0xE3, 0x02/*)*/, |
| 27702 | GIR_AddImm8, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Imm*/1, |
| 27703 | GIR_ConstrainOperandRC, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27704 | GIR_ConstrainOperandRC, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27705 | GIR_ConstrainOperandRC, /*InsnID*//* 354(*/0xE2, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27706 | GIR_BuildMI, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27707 | GIR_AddTempRegister, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*TempRegID*//* 352(*/0xE0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27708 | GIR_AddSimpleTempRegister, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*TempRegID*//* 353(*/0xE1, 0x02/*)*/, |
| 27709 | GIR_AddImm8, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*Imm*/32, |
| 27710 | GIR_AddImm8, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, /*Imm*/31, |
| 27711 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 353(*/0xE1, 0x02/*)*/, |
| 27712 | GIR_BuildMI, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27713 | GIR_AddTempRegister, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*TempRegID*//* 351(*/0xDF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27714 | GIR_AddSimpleTempRegister, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*TempRegID*//* 352(*/0xE0, 0x02/*)*/, |
| 27715 | GIR_AddImm, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27716 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 352(*/0xE0, 0x02/*)*/, |
| 27717 | GIR_BuildMI, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27718 | GIR_AddTempRegister, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*TempRegID*//* 350(*/0xDE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27719 | GIR_AddSimpleTempRegister, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*TempRegID*//* 351(*/0xDF, 0x02/*)*/, |
| 27720 | GIR_AddImm, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27721 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 351(*/0xDF, 0x02/*)*/, |
| 27722 | GIR_BuildMI, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27723 | GIR_AddTempRegister, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*TempRegID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27724 | GIR_Copy, /*NewInsnID*//* 350(*/0xDE, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27725 | GIR_AddImm8, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*Imm*/63, |
| 27726 | GIR_AddImm8, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, /*Imm*/1, |
| 27727 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 350(*/0xDE, 0x02/*)*/, |
| 27728 | GIR_BuildMI, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27729 | GIR_AddTempRegister, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27730 | GIR_AddSimpleTempRegister, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegID*//* 349(*/0xDD, 0x02/*)*/, |
| 27731 | GIR_AddSimpleTempRegister, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, /*TempRegID*//* 350(*/0xDE, 0x02/*)*/, |
| 27732 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 349(*/0xDD, 0x02/*)*/, |
| 27733 | GIR_BuildMI, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27734 | GIR_AddTempRegister, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegID*//* 347(*/0xDB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27735 | GIR_AddSimpleTempRegister, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegID*//* 348(*/0xDC, 0x02/*)*/, |
| 27736 | GIR_AddSimpleTempRegister, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, /*TempRegID*//* 357(*/0xE5, 0x02/*)*/, |
| 27737 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 348(*/0xDC, 0x02/*)*/, |
| 27738 | GIR_BuildMI, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27739 | GIR_AddTempRegister, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*TempRegID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27740 | GIR_AddSimpleTempRegister, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*TempRegID*//* 347(*/0xDB, 0x02/*)*/, |
| 27741 | GIR_AddImm8, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*Imm*/62, |
| 27742 | GIR_AddImm8, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, /*Imm*/2, |
| 27743 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 347(*/0xDB, 0x02/*)*/, |
| 27744 | GIR_BuildMI, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27745 | GIR_AddTempRegister, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27746 | GIR_AddSimpleTempRegister, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegID*//* 346(*/0xDA, 0x02/*)*/, |
| 27747 | GIR_AddSimpleTempRegister, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, /*TempRegID*//* 366(*/0xEE, 0x02/*)*/, |
| 27748 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 346(*/0xDA, 0x02/*)*/, |
| 27749 | GIR_BuildMI, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27750 | GIR_AddTempRegister, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegID*//* 344(*/0xD8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27751 | GIR_AddSimpleTempRegister, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegID*//* 345(*/0xD9, 0x02/*)*/, |
| 27752 | GIR_AddSimpleTempRegister, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, /*TempRegID*//* 373(*/0xF5, 0x02/*)*/, |
| 27753 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 345(*/0xD9, 0x02/*)*/, |
| 27754 | GIR_BuildMI, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27755 | GIR_AddTempRegister, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*TempRegID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27756 | GIR_AddSimpleTempRegister, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*TempRegID*//* 344(*/0xD8, 0x02/*)*/, |
| 27757 | GIR_AddImm8, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*Imm*/4, |
| 27758 | GIR_AddImm8, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, /*Imm*/59, |
| 27759 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 344(*/0xD8, 0x02/*)*/, |
| 27760 | GIR_BuildMI, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27761 | GIR_AddTempRegister, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegID*//* 342(*/0xD6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27762 | GIR_AddSimpleTempRegister, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegID*//* 343(*/0xD7, 0x02/*)*/, |
| 27763 | GIR_AddSimpleTempRegister, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, /*TempRegID*//* 401(*/0x91, 0x03/*)*/, |
| 27764 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 343(*/0xD7, 0x02/*)*/, |
| 27765 | GIR_BuildMI, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27766 | GIR_AddTempRegister, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, /*TempRegID*//* 341(*/0xD5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27767 | GIR_AddImm, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 27768 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 342(*/0xD6, 0x02/*)*/, |
| 27769 | GIR_BuildMI, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27770 | GIR_AddTempRegister, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*TempRegID*//* 340(*/0xD4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27771 | GIR_AddSimpleTempRegister, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*TempRegID*//* 341(*/0xD5, 0x02/*)*/, |
| 27772 | GIR_AddImm, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 27773 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 341(*/0xD5, 0x02/*)*/, |
| 27774 | GIR_BuildMI, /*InsnID*//* 340(*/0xD4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27775 | GIR_AddTempRegister, /*InsnID*//* 340(*/0xD4, 0x02/*)*/, /*TempRegID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27776 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 340(*/0xD4, 0x02/*)*/, |
| 27777 | GIR_BuildMI, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27778 | GIR_AddTempRegister, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegID*//* 338(*/0xD2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27779 | GIR_AddSimpleTempRegister, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegID*//* 339(*/0xD3, 0x02/*)*/, |
| 27780 | GIR_AddSimpleTempRegister, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*TempRegID*//* 340(*/0xD4, 0x02/*)*/, |
| 27781 | GIR_AddImm8, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Imm*/1, |
| 27782 | GIR_ConstrainOperandRC, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27783 | GIR_ConstrainOperandRC, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27784 | GIR_ConstrainOperandRC, /*InsnID*//* 339(*/0xD3, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27785 | GIR_BuildMI, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27786 | GIR_AddTempRegister, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*TempRegID*//* 337(*/0xD1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27787 | GIR_AddSimpleTempRegister, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*TempRegID*//* 338(*/0xD2, 0x02/*)*/, |
| 27788 | GIR_AddImm8, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*Imm*/32, |
| 27789 | GIR_AddImm8, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, /*Imm*/31, |
| 27790 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 338(*/0xD2, 0x02/*)*/, |
| 27791 | GIR_BuildMI, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27792 | GIR_AddTempRegister, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*TempRegID*//* 336(*/0xD0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27793 | GIR_AddSimpleTempRegister, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*TempRegID*//* 337(*/0xD1, 0x02/*)*/, |
| 27794 | GIR_AddImm, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 27795 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 337(*/0xD1, 0x02/*)*/, |
| 27796 | GIR_BuildMI, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27797 | GIR_AddTempRegister, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*TempRegID*//* 335(*/0xCF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27798 | GIR_AddSimpleTempRegister, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*TempRegID*//* 336(*/0xD0, 0x02/*)*/, |
| 27799 | GIR_AddImm, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 27800 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 336(*/0xD0, 0x02/*)*/, |
| 27801 | GIR_BuildMI, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27802 | GIR_AddTempRegister, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, /*TempRegID*//* 334(*/0xCE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27803 | GIR_AddImm, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27804 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 335(*/0xCF, 0x02/*)*/, |
| 27805 | GIR_BuildMI, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27806 | GIR_AddTempRegister, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*TempRegID*//* 333(*/0xCD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27807 | GIR_AddSimpleTempRegister, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*TempRegID*//* 334(*/0xCE, 0x02/*)*/, |
| 27808 | GIR_AddImm, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27809 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 334(*/0xCE, 0x02/*)*/, |
| 27810 | GIR_BuildMI, /*InsnID*//* 333(*/0xCD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27811 | GIR_AddTempRegister, /*InsnID*//* 333(*/0xCD, 0x02/*)*/, /*TempRegID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27812 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 333(*/0xCD, 0x02/*)*/, |
| 27813 | GIR_BuildMI, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27814 | GIR_AddTempRegister, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegID*//* 331(*/0xCB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27815 | GIR_AddSimpleTempRegister, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegID*//* 332(*/0xCC, 0x02/*)*/, |
| 27816 | GIR_AddSimpleTempRegister, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*TempRegID*//* 333(*/0xCD, 0x02/*)*/, |
| 27817 | GIR_AddImm8, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Imm*/1, |
| 27818 | GIR_ConstrainOperandRC, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27819 | GIR_ConstrainOperandRC, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27820 | GIR_ConstrainOperandRC, /*InsnID*//* 332(*/0xCC, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27821 | GIR_BuildMI, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27822 | GIR_AddTempRegister, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*TempRegID*//* 330(*/0xCA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27823 | GIR_AddSimpleTempRegister, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*TempRegID*//* 331(*/0xCB, 0x02/*)*/, |
| 27824 | GIR_AddImm8, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*Imm*/32, |
| 27825 | GIR_AddImm8, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, /*Imm*/31, |
| 27826 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 331(*/0xCB, 0x02/*)*/, |
| 27827 | GIR_BuildMI, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27828 | GIR_AddTempRegister, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*TempRegID*//* 329(*/0xC9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27829 | GIR_AddSimpleTempRegister, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*TempRegID*//* 330(*/0xCA, 0x02/*)*/, |
| 27830 | GIR_AddImm, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27831 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 330(*/0xCA, 0x02/*)*/, |
| 27832 | GIR_BuildMI, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27833 | GIR_AddTempRegister, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*TempRegID*//* 328(*/0xC8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27834 | GIR_AddSimpleTempRegister, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*TempRegID*//* 329(*/0xC9, 0x02/*)*/, |
| 27835 | GIR_AddImm, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 27836 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 329(*/0xC9, 0x02/*)*/, |
| 27837 | GIR_BuildMI, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27838 | GIR_AddTempRegister, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, /*TempRegID*//* 327(*/0xC7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27839 | GIR_AddImm, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27840 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 328(*/0xC8, 0x02/*)*/, |
| 27841 | GIR_BuildMI, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27842 | GIR_AddTempRegister, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*TempRegID*//* 326(*/0xC6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27843 | GIR_AddSimpleTempRegister, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*TempRegID*//* 327(*/0xC7, 0x02/*)*/, |
| 27844 | GIR_AddImm, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27845 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 327(*/0xC7, 0x02/*)*/, |
| 27846 | GIR_BuildMI, /*InsnID*//* 326(*/0xC6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27847 | GIR_AddTempRegister, /*InsnID*//* 326(*/0xC6, 0x02/*)*/, /*TempRegID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27848 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 326(*/0xC6, 0x02/*)*/, |
| 27849 | GIR_BuildMI, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27850 | GIR_AddTempRegister, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegID*//* 324(*/0xC4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27851 | GIR_AddSimpleTempRegister, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegID*//* 325(*/0xC5, 0x02/*)*/, |
| 27852 | GIR_AddSimpleTempRegister, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*TempRegID*//* 326(*/0xC6, 0x02/*)*/, |
| 27853 | GIR_AddImm8, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Imm*/1, |
| 27854 | GIR_ConstrainOperandRC, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27855 | GIR_ConstrainOperandRC, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27856 | GIR_ConstrainOperandRC, /*InsnID*//* 325(*/0xC5, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27857 | GIR_BuildMI, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27858 | GIR_AddTempRegister, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*TempRegID*//* 323(*/0xC3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27859 | GIR_AddSimpleTempRegister, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*TempRegID*//* 324(*/0xC4, 0x02/*)*/, |
| 27860 | GIR_AddImm8, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*Imm*/32, |
| 27861 | GIR_AddImm8, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, /*Imm*/31, |
| 27862 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 324(*/0xC4, 0x02/*)*/, |
| 27863 | GIR_BuildMI, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27864 | GIR_AddTempRegister, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*TempRegID*//* 322(*/0xC2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27865 | GIR_AddSimpleTempRegister, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*TempRegID*//* 323(*/0xC3, 0x02/*)*/, |
| 27866 | GIR_AddImm, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27867 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 323(*/0xC3, 0x02/*)*/, |
| 27868 | GIR_BuildMI, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27869 | GIR_AddTempRegister, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*TempRegID*//* 321(*/0xC1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27870 | GIR_AddSimpleTempRegister, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*TempRegID*//* 322(*/0xC2, 0x02/*)*/, |
| 27871 | GIR_AddImm, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27872 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 322(*/0xC2, 0x02/*)*/, |
| 27873 | GIR_BuildMI, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27874 | GIR_AddTempRegister, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*TempRegID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27875 | GIR_Copy, /*NewInsnID*//* 321(*/0xC1, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27876 | GIR_AddImm8, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*Imm*/1, |
| 27877 | GIR_AddImm8, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, /*Imm*/62, |
| 27878 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 321(*/0xC1, 0x02/*)*/, |
| 27879 | GIR_BuildMI, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27880 | GIR_AddTempRegister, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegID*//* 319(*/0xBF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27881 | GIR_AddSimpleTempRegister, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegID*//* 320(*/0xC0, 0x02/*)*/, |
| 27882 | GIR_AddSimpleTempRegister, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, /*TempRegID*//* 321(*/0xC1, 0x02/*)*/, |
| 27883 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 320(*/0xC0, 0x02/*)*/, |
| 27884 | GIR_BuildMI, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27885 | GIR_AddTempRegister, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, /*TempRegID*//* 318(*/0xBE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27886 | GIR_AddImm, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27887 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 319(*/0xBF, 0x02/*)*/, |
| 27888 | GIR_BuildMI, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27889 | GIR_AddTempRegister, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*TempRegID*//* 317(*/0xBD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27890 | GIR_AddSimpleTempRegister, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*TempRegID*//* 318(*/0xBE, 0x02/*)*/, |
| 27891 | GIR_AddImm, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27892 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 318(*/0xBE, 0x02/*)*/, |
| 27893 | GIR_BuildMI, /*InsnID*//* 317(*/0xBD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27894 | GIR_AddTempRegister, /*InsnID*//* 317(*/0xBD, 0x02/*)*/, /*TempRegID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27895 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 317(*/0xBD, 0x02/*)*/, |
| 27896 | GIR_BuildMI, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27897 | GIR_AddTempRegister, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegID*//* 315(*/0xBB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27898 | GIR_AddSimpleTempRegister, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegID*//* 316(*/0xBC, 0x02/*)*/, |
| 27899 | GIR_AddSimpleTempRegister, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*TempRegID*//* 317(*/0xBD, 0x02/*)*/, |
| 27900 | GIR_AddImm8, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Imm*/1, |
| 27901 | GIR_ConstrainOperandRC, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27902 | GIR_ConstrainOperandRC, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27903 | GIR_ConstrainOperandRC, /*InsnID*//* 316(*/0xBC, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27904 | GIR_BuildMI, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27905 | GIR_AddTempRegister, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*TempRegID*//* 314(*/0xBA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27906 | GIR_AddSimpleTempRegister, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*TempRegID*//* 315(*/0xBB, 0x02/*)*/, |
| 27907 | GIR_AddImm8, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*Imm*/32, |
| 27908 | GIR_AddImm8, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, /*Imm*/31, |
| 27909 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 315(*/0xBB, 0x02/*)*/, |
| 27910 | GIR_BuildMI, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27911 | GIR_AddTempRegister, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*TempRegID*//* 313(*/0xB9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27912 | GIR_AddSimpleTempRegister, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*TempRegID*//* 314(*/0xBA, 0x02/*)*/, |
| 27913 | GIR_AddImm, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27914 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 314(*/0xBA, 0x02/*)*/, |
| 27915 | GIR_BuildMI, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27916 | GIR_AddTempRegister, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*TempRegID*//* 312(*/0xB8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27917 | GIR_AddSimpleTempRegister, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*TempRegID*//* 313(*/0xB9, 0x02/*)*/, |
| 27918 | GIR_AddImm, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 27919 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 313(*/0xB9, 0x02/*)*/, |
| 27920 | GIR_BuildMI, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 27921 | GIR_AddTempRegister, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*TempRegID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27922 | GIR_Copy, /*NewInsnID*//* 312(*/0xB8, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 27923 | GIR_AddImm8, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*Imm*/63, |
| 27924 | GIR_AddImm8, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, /*Imm*/1, |
| 27925 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 312(*/0xB8, 0x02/*)*/, |
| 27926 | GIR_BuildMI, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27927 | GIR_AddTempRegister, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27928 | GIR_AddSimpleTempRegister, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegID*//* 311(*/0xB7, 0x02/*)*/, |
| 27929 | GIR_AddSimpleTempRegister, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, /*TempRegID*//* 312(*/0xB8, 0x02/*)*/, |
| 27930 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 311(*/0xB7, 0x02/*)*/, |
| 27931 | GIR_BuildMI, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 27932 | GIR_AddTempRegister, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegID*//* 309(*/0xB5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27933 | GIR_AddSimpleTempRegister, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegID*//* 310(*/0xB6, 0x02/*)*/, |
| 27934 | GIR_AddSimpleTempRegister, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, /*TempRegID*//* 319(*/0xBF, 0x02/*)*/, |
| 27935 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 310(*/0xB6, 0x02/*)*/, |
| 27936 | GIR_BuildMI, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27937 | GIR_AddTempRegister, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*TempRegID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27938 | GIR_AddSimpleTempRegister, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*TempRegID*//* 309(*/0xB5, 0x02/*)*/, |
| 27939 | GIR_AddImm8, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*Imm*/2, |
| 27940 | GIR_AddImm8, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, /*Imm*/61, |
| 27941 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 309(*/0xB5, 0x02/*)*/, |
| 27942 | GIR_BuildMI, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 27943 | GIR_AddTempRegister, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegID*//* 307(*/0xB3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27944 | GIR_AddSimpleTempRegister, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegID*//* 308(*/0xB4, 0x02/*)*/, |
| 27945 | GIR_AddSimpleTempRegister, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, /*TempRegID*//* 328(*/0xC8, 0x02/*)*/, |
| 27946 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 308(*/0xB4, 0x02/*)*/, |
| 27947 | GIR_BuildMI, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27948 | GIR_AddTempRegister, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, /*TempRegID*//* 306(*/0xB2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27949 | GIR_AddImm, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27950 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 307(*/0xB3, 0x02/*)*/, |
| 27951 | GIR_BuildMI, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27952 | GIR_AddTempRegister, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*TempRegID*//* 305(*/0xB1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27953 | GIR_AddSimpleTempRegister, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*TempRegID*//* 306(*/0xB2, 0x02/*)*/, |
| 27954 | GIR_AddImm, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27955 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 306(*/0xB2, 0x02/*)*/, |
| 27956 | GIR_BuildMI, /*InsnID*//* 305(*/0xB1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27957 | GIR_AddTempRegister, /*InsnID*//* 305(*/0xB1, 0x02/*)*/, /*TempRegID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27958 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 305(*/0xB1, 0x02/*)*/, |
| 27959 | GIR_BuildMI, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27960 | GIR_AddTempRegister, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegID*//* 303(*/0xAF, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27961 | GIR_AddSimpleTempRegister, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegID*//* 304(*/0xB0, 0x02/*)*/, |
| 27962 | GIR_AddSimpleTempRegister, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*TempRegID*//* 305(*/0xB1, 0x02/*)*/, |
| 27963 | GIR_AddImm8, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Imm*/1, |
| 27964 | GIR_ConstrainOperandRC, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27965 | GIR_ConstrainOperandRC, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 27966 | GIR_ConstrainOperandRC, /*InsnID*//* 304(*/0xB0, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 27967 | GIR_BuildMI, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 27968 | GIR_AddTempRegister, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*TempRegID*//* 302(*/0xAE, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27969 | GIR_AddSimpleTempRegister, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*TempRegID*//* 303(*/0xAF, 0x02/*)*/, |
| 27970 | GIR_AddImm8, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*Imm*/32, |
| 27971 | GIR_AddImm8, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, /*Imm*/31, |
| 27972 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 303(*/0xAF, 0x02/*)*/, |
| 27973 | GIR_BuildMI, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 27974 | GIR_AddTempRegister, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*TempRegID*//* 301(*/0xAD, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27975 | GIR_AddSimpleTempRegister, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*TempRegID*//* 302(*/0xAE, 0x02/*)*/, |
| 27976 | GIR_AddImm, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27977 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 302(*/0xAE, 0x02/*)*/, |
| 27978 | GIR_BuildMI, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 27979 | GIR_AddTempRegister, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*TempRegID*//* 300(*/0xAC, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27980 | GIR_AddSimpleTempRegister, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*TempRegID*//* 301(*/0xAD, 0x02/*)*/, |
| 27981 | GIR_AddImm, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 27982 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 301(*/0xAD, 0x02/*)*/, |
| 27983 | GIR_BuildMI, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 27984 | GIR_AddTempRegister, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, /*TempRegID*//* 299(*/0xAB, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27985 | GIR_AddImm, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27986 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 300(*/0xAC, 0x02/*)*/, |
| 27987 | GIR_BuildMI, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 27988 | GIR_AddTempRegister, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*TempRegID*//* 298(*/0xAA, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27989 | GIR_AddSimpleTempRegister, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*TempRegID*//* 299(*/0xAB, 0x02/*)*/, |
| 27990 | GIR_AddImm, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 27991 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 299(*/0xAB, 0x02/*)*/, |
| 27992 | GIR_BuildMI, /*InsnID*//* 298(*/0xAA, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 27993 | GIR_AddTempRegister, /*InsnID*//* 298(*/0xAA, 0x02/*)*/, /*TempRegID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27994 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 298(*/0xAA, 0x02/*)*/, |
| 27995 | GIR_BuildMI, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 27996 | GIR_AddTempRegister, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegID*//* 296(*/0xA8, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 27997 | GIR_AddSimpleTempRegister, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegID*//* 297(*/0xA9, 0x02/*)*/, |
| 27998 | GIR_AddSimpleTempRegister, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*TempRegID*//* 298(*/0xAA, 0x02/*)*/, |
| 27999 | GIR_AddImm8, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Imm*/1, |
| 28000 | GIR_ConstrainOperandRC, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28001 | GIR_ConstrainOperandRC, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28002 | GIR_ConstrainOperandRC, /*InsnID*//* 297(*/0xA9, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28003 | GIR_BuildMI, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28004 | GIR_AddTempRegister, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*TempRegID*//* 295(*/0xA7, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28005 | GIR_AddSimpleTempRegister, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*TempRegID*//* 296(*/0xA8, 0x02/*)*/, |
| 28006 | GIR_AddImm8, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*Imm*/32, |
| 28007 | GIR_AddImm8, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, /*Imm*/31, |
| 28008 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 296(*/0xA8, 0x02/*)*/, |
| 28009 | GIR_BuildMI, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28010 | GIR_AddTempRegister, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*TempRegID*//* 294(*/0xA6, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28011 | GIR_AddSimpleTempRegister, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*TempRegID*//* 295(*/0xA7, 0x02/*)*/, |
| 28012 | GIR_AddImm, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28013 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 295(*/0xA7, 0x02/*)*/, |
| 28014 | GIR_BuildMI, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28015 | GIR_AddTempRegister, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*TempRegID*//* 293(*/0xA5, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28016 | GIR_AddSimpleTempRegister, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*TempRegID*//* 294(*/0xA6, 0x02/*)*/, |
| 28017 | GIR_AddImm, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28018 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 294(*/0xA6, 0x02/*)*/, |
| 28019 | GIR_BuildMI, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28020 | GIR_AddTempRegister, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*TempRegID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28021 | GIR_Copy, /*NewInsnID*//* 293(*/0xA5, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28022 | GIR_AddImm8, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*Imm*/1, |
| 28023 | GIR_AddImm8, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, /*Imm*/62, |
| 28024 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 293(*/0xA5, 0x02/*)*/, |
| 28025 | GIR_BuildMI, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28026 | GIR_AddTempRegister, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegID*//* 291(*/0xA3, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28027 | GIR_AddSimpleTempRegister, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegID*//* 292(*/0xA4, 0x02/*)*/, |
| 28028 | GIR_AddSimpleTempRegister, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, /*TempRegID*//* 293(*/0xA5, 0x02/*)*/, |
| 28029 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 292(*/0xA4, 0x02/*)*/, |
| 28030 | GIR_BuildMI, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28031 | GIR_AddTempRegister, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, /*TempRegID*//* 290(*/0xA2, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28032 | GIR_AddImm, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28033 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 291(*/0xA3, 0x02/*)*/, |
| 28034 | GIR_BuildMI, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28035 | GIR_AddTempRegister, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*TempRegID*//* 289(*/0xA1, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28036 | GIR_AddSimpleTempRegister, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*TempRegID*//* 290(*/0xA2, 0x02/*)*/, |
| 28037 | GIR_AddImm, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28038 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 290(*/0xA2, 0x02/*)*/, |
| 28039 | GIR_BuildMI, /*InsnID*//* 289(*/0xA1, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28040 | GIR_AddTempRegister, /*InsnID*//* 289(*/0xA1, 0x02/*)*/, /*TempRegID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28041 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 289(*/0xA1, 0x02/*)*/, |
| 28042 | GIR_BuildMI, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28043 | GIR_AddTempRegister, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegID*//* 287(*/0x9F, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28044 | GIR_AddSimpleTempRegister, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegID*//* 288(*/0xA0, 0x02/*)*/, |
| 28045 | GIR_AddSimpleTempRegister, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*TempRegID*//* 289(*/0xA1, 0x02/*)*/, |
| 28046 | GIR_AddImm8, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Imm*/1, |
| 28047 | GIR_ConstrainOperandRC, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28048 | GIR_ConstrainOperandRC, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28049 | GIR_ConstrainOperandRC, /*InsnID*//* 288(*/0xA0, 0x02/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28050 | GIR_BuildMI, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28051 | GIR_AddTempRegister, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*TempRegID*//* 286(*/0x9E, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28052 | GIR_AddSimpleTempRegister, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*TempRegID*//* 287(*/0x9F, 0x02/*)*/, |
| 28053 | GIR_AddImm8, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*Imm*/32, |
| 28054 | GIR_AddImm8, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, /*Imm*/31, |
| 28055 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 287(*/0x9F, 0x02/*)*/, |
| 28056 | GIR_BuildMI, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28057 | GIR_AddTempRegister, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*TempRegID*//* 285(*/0x9D, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28058 | GIR_AddSimpleTempRegister, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*TempRegID*//* 286(*/0x9E, 0x02/*)*/, |
| 28059 | GIR_AddImm, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28060 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 286(*/0x9E, 0x02/*)*/, |
| 28061 | GIR_BuildMI, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28062 | GIR_AddTempRegister, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*TempRegID*//* 284(*/0x9C, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28063 | GIR_AddSimpleTempRegister, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*TempRegID*//* 285(*/0x9D, 0x02/*)*/, |
| 28064 | GIR_AddImm, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28065 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 285(*/0x9D, 0x02/*)*/, |
| 28066 | GIR_BuildMI, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28067 | GIR_AddTempRegister, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*TempRegID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28068 | GIR_Copy, /*NewInsnID*//* 284(*/0x9C, 0x02/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28069 | GIR_AddImm8, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*Imm*/63, |
| 28070 | GIR_AddImm8, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, /*Imm*/1, |
| 28071 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 284(*/0x9C, 0x02/*)*/, |
| 28072 | GIR_BuildMI, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28073 | GIR_AddTempRegister, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28074 | GIR_AddSimpleTempRegister, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegID*//* 283(*/0x9B, 0x02/*)*/, |
| 28075 | GIR_AddSimpleTempRegister, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, /*TempRegID*//* 284(*/0x9C, 0x02/*)*/, |
| 28076 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 283(*/0x9B, 0x02/*)*/, |
| 28077 | GIR_BuildMI, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28078 | GIR_AddTempRegister, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegID*//* 281(*/0x99, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28079 | GIR_AddSimpleTempRegister, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegID*//* 282(*/0x9A, 0x02/*)*/, |
| 28080 | GIR_AddSimpleTempRegister, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, /*TempRegID*//* 291(*/0xA3, 0x02/*)*/, |
| 28081 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 282(*/0x9A, 0x02/*)*/, |
| 28082 | GIR_BuildMI, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28083 | GIR_AddTempRegister, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*TempRegID*//* 280(*/0x98, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28084 | GIR_AddSimpleTempRegister, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*TempRegID*//* 281(*/0x99, 0x02/*)*/, |
| 28085 | GIR_AddImm8, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*Imm*/62, |
| 28086 | GIR_AddImm8, /*InsnID*//* 281(*/0x99, 0x02/*)*/, /*Imm*/2, |
| 28087 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 281(*/0x99, 0x02/*)*/, |
| 28088 | GIR_BuildMI, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28089 | GIR_AddTempRegister, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*TempRegID*//* 279(*/0x97, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28090 | GIR_AddSimpleTempRegister, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*TempRegID*//* 280(*/0x98, 0x02/*)*/, |
| 28091 | GIR_AddSimpleTempRegister, /*InsnID*//* 280(*/0x98, 0x02/*)*/, /*TempRegID*//* 300(*/0xAC, 0x02/*)*/, |
| 28092 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 280(*/0x98, 0x02/*)*/, |
| 28093 | GIR_BuildMI, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28094 | GIR_AddTempRegister, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*TempRegID*//* 278(*/0x96, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28095 | GIR_AddSimpleTempRegister, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*TempRegID*//* 279(*/0x97, 0x02/*)*/, |
| 28096 | GIR_AddSimpleTempRegister, /*InsnID*//* 279(*/0x97, 0x02/*)*/, /*TempRegID*//* 307(*/0xB3, 0x02/*)*/, |
| 28097 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 279(*/0x97, 0x02/*)*/, |
| 28098 | GIR_BuildMI, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28099 | GIR_AddTempRegister, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*TempRegID*//* 277(*/0x95, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28100 | GIR_AddSimpleTempRegister, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*TempRegID*//* 278(*/0x96, 0x02/*)*/, |
| 28101 | GIR_AddImm8, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*Imm*/60, |
| 28102 | GIR_AddImm8, /*InsnID*//* 278(*/0x96, 0x02/*)*/, /*Imm*/4, |
| 28103 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 278(*/0x96, 0x02/*)*/, |
| 28104 | GIR_BuildMI, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28105 | GIR_AddTempRegister, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*TempRegID*//* 276(*/0x94, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28106 | GIR_AddSimpleTempRegister, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*TempRegID*//* 277(*/0x95, 0x02/*)*/, |
| 28107 | GIR_AddSimpleTempRegister, /*InsnID*//* 277(*/0x95, 0x02/*)*/, /*TempRegID*//* 335(*/0xCF, 0x02/*)*/, |
| 28108 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 277(*/0x95, 0x02/*)*/, |
| 28109 | GIR_BuildMI, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28110 | GIR_AddTempRegister, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*TempRegID*//* 275(*/0x93, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28111 | GIR_AddSimpleTempRegister, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*TempRegID*//* 276(*/0x94, 0x02/*)*/, |
| 28112 | GIR_AddSimpleTempRegister, /*InsnID*//* 276(*/0x94, 0x02/*)*/, /*TempRegID*//* 342(*/0xD6, 0x02/*)*/, |
| 28113 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 276(*/0x94, 0x02/*)*/, |
| 28114 | GIR_MakeTempReg, /*TempRegID*//* 408(*/0x98, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28115 | GIR_MakeTempReg, /*TempRegID*//* 409(*/0x99, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28116 | GIR_MakeTempReg, /*TempRegID*//* 410(*/0x9A, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28117 | GIR_MakeTempReg, /*TempRegID*//* 411(*/0x9B, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28118 | GIR_MakeTempReg, /*TempRegID*//* 412(*/0x9C, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28119 | GIR_MakeTempReg, /*TempRegID*//* 413(*/0x9D, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28120 | GIR_MakeTempReg, /*TempRegID*//* 414(*/0x9E, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28121 | GIR_MakeTempReg, /*TempRegID*//* 415(*/0x9F, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28122 | GIR_MakeTempReg, /*TempRegID*//* 416(*/0xA0, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28123 | GIR_MakeTempReg, /*TempRegID*//* 417(*/0xA1, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28124 | GIR_MakeTempReg, /*TempRegID*//* 418(*/0xA2, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28125 | GIR_MakeTempReg, /*TempRegID*//* 419(*/0xA3, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28126 | GIR_MakeTempReg, /*TempRegID*//* 420(*/0xA4, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28127 | GIR_MakeTempReg, /*TempRegID*//* 421(*/0xA5, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28128 | GIR_MakeTempReg, /*TempRegID*//* 422(*/0xA6, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28129 | GIR_MakeTempReg, /*TempRegID*//* 423(*/0xA7, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28130 | GIR_MakeTempReg, /*TempRegID*//* 424(*/0xA8, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28131 | GIR_MakeTempReg, /*TempRegID*//* 425(*/0xA9, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28132 | GIR_MakeTempReg, /*TempRegID*//* 426(*/0xAA, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28133 | GIR_MakeTempReg, /*TempRegID*//* 427(*/0xAB, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28134 | GIR_MakeTempReg, /*TempRegID*//* 428(*/0xAC, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28135 | GIR_MakeTempReg, /*TempRegID*//* 429(*/0xAD, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28136 | GIR_MakeTempReg, /*TempRegID*//* 430(*/0xAE, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28137 | GIR_MakeTempReg, /*TempRegID*//* 431(*/0xAF, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28138 | GIR_MakeTempReg, /*TempRegID*//* 432(*/0xB0, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28139 | GIR_MakeTempReg, /*TempRegID*//* 433(*/0xB1, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28140 | GIR_MakeTempReg, /*TempRegID*//* 434(*/0xB2, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28141 | GIR_MakeTempReg, /*TempRegID*//* 435(*/0xB3, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28142 | GIR_MakeTempReg, /*TempRegID*//* 436(*/0xB4, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28143 | GIR_MakeTempReg, /*TempRegID*//* 437(*/0xB5, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28144 | GIR_MakeTempReg, /*TempRegID*//* 438(*/0xB6, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28145 | GIR_MakeTempReg, /*TempRegID*//* 439(*/0xB7, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28146 | GIR_MakeTempReg, /*TempRegID*//* 440(*/0xB8, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28147 | GIR_MakeTempReg, /*TempRegID*//* 441(*/0xB9, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28148 | GIR_MakeTempReg, /*TempRegID*//* 442(*/0xBA, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28149 | GIR_MakeTempReg, /*TempRegID*//* 443(*/0xBB, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28150 | GIR_MakeTempReg, /*TempRegID*//* 444(*/0xBC, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28151 | GIR_MakeTempReg, /*TempRegID*//* 445(*/0xBD, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28152 | GIR_MakeTempReg, /*TempRegID*//* 446(*/0xBE, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28153 | GIR_MakeTempReg, /*TempRegID*//* 447(*/0xBF, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28154 | GIR_MakeTempReg, /*TempRegID*//* 448(*/0xC0, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28155 | GIR_MakeTempReg, /*TempRegID*//* 449(*/0xC1, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28156 | GIR_MakeTempReg, /*TempRegID*//* 450(*/0xC2, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28157 | GIR_MakeTempReg, /*TempRegID*//* 451(*/0xC3, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28158 | GIR_MakeTempReg, /*TempRegID*//* 452(*/0xC4, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28159 | GIR_MakeTempReg, /*TempRegID*//* 453(*/0xC5, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28160 | GIR_MakeTempReg, /*TempRegID*//* 454(*/0xC6, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28161 | GIR_MakeTempReg, /*TempRegID*//* 455(*/0xC7, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28162 | GIR_MakeTempReg, /*TempRegID*//* 456(*/0xC8, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28163 | GIR_MakeTempReg, /*TempRegID*//* 457(*/0xC9, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28164 | GIR_MakeTempReg, /*TempRegID*//* 458(*/0xCA, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28165 | GIR_MakeTempReg, /*TempRegID*//* 459(*/0xCB, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28166 | GIR_MakeTempReg, /*TempRegID*//* 460(*/0xCC, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28167 | GIR_MakeTempReg, /*TempRegID*//* 461(*/0xCD, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28168 | GIR_MakeTempReg, /*TempRegID*//* 462(*/0xCE, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28169 | GIR_MakeTempReg, /*TempRegID*//* 463(*/0xCF, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28170 | GIR_MakeTempReg, /*TempRegID*//* 464(*/0xD0, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28171 | GIR_MakeTempReg, /*TempRegID*//* 465(*/0xD1, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28172 | GIR_MakeTempReg, /*TempRegID*//* 466(*/0xD2, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28173 | GIR_MakeTempReg, /*TempRegID*//* 467(*/0xD3, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28174 | GIR_MakeTempReg, /*TempRegID*//* 468(*/0xD4, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28175 | GIR_MakeTempReg, /*TempRegID*//* 469(*/0xD5, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28176 | GIR_MakeTempReg, /*TempRegID*//* 470(*/0xD6, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28177 | GIR_MakeTempReg, /*TempRegID*//* 471(*/0xD7, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28178 | GIR_MakeTempReg, /*TempRegID*//* 472(*/0xD8, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28179 | GIR_MakeTempReg, /*TempRegID*//* 473(*/0xD9, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28180 | GIR_MakeTempReg, /*TempRegID*//* 474(*/0xDA, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28181 | GIR_MakeTempReg, /*TempRegID*//* 475(*/0xDB, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28182 | GIR_MakeTempReg, /*TempRegID*//* 476(*/0xDC, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28183 | GIR_MakeTempReg, /*TempRegID*//* 477(*/0xDD, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28184 | GIR_MakeTempReg, /*TempRegID*//* 478(*/0xDE, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28185 | GIR_MakeTempReg, /*TempRegID*//* 479(*/0xDF, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28186 | GIR_MakeTempReg, /*TempRegID*//* 480(*/0xE0, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28187 | GIR_MakeTempReg, /*TempRegID*//* 481(*/0xE1, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28188 | GIR_MakeTempReg, /*TempRegID*//* 482(*/0xE2, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28189 | GIR_MakeTempReg, /*TempRegID*//* 483(*/0xE3, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28190 | GIR_MakeTempReg, /*TempRegID*//* 484(*/0xE4, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28191 | GIR_MakeTempReg, /*TempRegID*//* 485(*/0xE5, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28192 | GIR_MakeTempReg, /*TempRegID*//* 486(*/0xE6, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28193 | GIR_MakeTempReg, /*TempRegID*//* 487(*/0xE7, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28194 | GIR_MakeTempReg, /*TempRegID*//* 488(*/0xE8, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28195 | GIR_MakeTempReg, /*TempRegID*//* 489(*/0xE9, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28196 | GIR_MakeTempReg, /*TempRegID*//* 490(*/0xEA, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28197 | GIR_MakeTempReg, /*TempRegID*//* 491(*/0xEB, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28198 | GIR_MakeTempReg, /*TempRegID*//* 492(*/0xEC, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28199 | GIR_MakeTempReg, /*TempRegID*//* 493(*/0xED, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28200 | GIR_MakeTempReg, /*TempRegID*//* 494(*/0xEE, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28201 | GIR_MakeTempReg, /*TempRegID*//* 495(*/0xEF, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28202 | GIR_MakeTempReg, /*TempRegID*//* 496(*/0xF0, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28203 | GIR_MakeTempReg, /*TempRegID*//* 497(*/0xF1, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28204 | GIR_MakeTempReg, /*TempRegID*//* 498(*/0xF2, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28205 | GIR_MakeTempReg, /*TempRegID*//* 499(*/0xF3, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28206 | GIR_MakeTempReg, /*TempRegID*//* 500(*/0xF4, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28207 | GIR_MakeTempReg, /*TempRegID*//* 501(*/0xF5, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28208 | GIR_MakeTempReg, /*TempRegID*//* 502(*/0xF6, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28209 | GIR_MakeTempReg, /*TempRegID*//* 503(*/0xF7, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28210 | GIR_MakeTempReg, /*TempRegID*//* 504(*/0xF8, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28211 | GIR_MakeTempReg, /*TempRegID*//* 505(*/0xF9, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28212 | GIR_MakeTempReg, /*TempRegID*//* 506(*/0xFA, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28213 | GIR_MakeTempReg, /*TempRegID*//* 507(*/0xFB, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28214 | GIR_MakeTempReg, /*TempRegID*//* 508(*/0xFC, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28215 | GIR_MakeTempReg, /*TempRegID*//* 509(*/0xFD, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28216 | GIR_MakeTempReg, /*TempRegID*//* 510(*/0xFE, 0x03/*)*/, /*TypeID*/GILLT_s64, |
| 28217 | GIR_MakeTempReg, /*TempRegID*//* 511(*/0xFF, 0x03/*)*/, /*TypeID*/GILLT_s32, |
| 28218 | GIR_MakeTempReg, /*TempRegID*//* 512(*/0x80, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28219 | GIR_MakeTempReg, /*TempRegID*//* 513(*/0x81, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28220 | GIR_MakeTempReg, /*TempRegID*//* 514(*/0x82, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28221 | GIR_MakeTempReg, /*TempRegID*//* 515(*/0x83, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28222 | GIR_MakeTempReg, /*TempRegID*//* 516(*/0x84, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28223 | GIR_MakeTempReg, /*TempRegID*//* 517(*/0x85, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28224 | GIR_MakeTempReg, /*TempRegID*//* 518(*/0x86, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28225 | GIR_MakeTempReg, /*TempRegID*//* 519(*/0x87, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28226 | GIR_MakeTempReg, /*TempRegID*//* 520(*/0x88, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28227 | GIR_MakeTempReg, /*TempRegID*//* 521(*/0x89, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28228 | GIR_MakeTempReg, /*TempRegID*//* 522(*/0x8A, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28229 | GIR_MakeTempReg, /*TempRegID*//* 523(*/0x8B, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28230 | GIR_MakeTempReg, /*TempRegID*//* 524(*/0x8C, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28231 | GIR_MakeTempReg, /*TempRegID*//* 525(*/0x8D, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28232 | GIR_MakeTempReg, /*TempRegID*//* 526(*/0x8E, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28233 | GIR_MakeTempReg, /*TempRegID*//* 527(*/0x8F, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28234 | GIR_MakeTempReg, /*TempRegID*//* 528(*/0x90, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28235 | GIR_MakeTempReg, /*TempRegID*//* 529(*/0x91, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28236 | GIR_MakeTempReg, /*TempRegID*//* 530(*/0x92, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28237 | GIR_MakeTempReg, /*TempRegID*//* 531(*/0x93, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28238 | GIR_MakeTempReg, /*TempRegID*//* 532(*/0x94, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28239 | GIR_MakeTempReg, /*TempRegID*//* 533(*/0x95, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28240 | GIR_MakeTempReg, /*TempRegID*//* 534(*/0x96, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28241 | GIR_MakeTempReg, /*TempRegID*//* 535(*/0x97, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28242 | GIR_MakeTempReg, /*TempRegID*//* 536(*/0x98, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28243 | GIR_MakeTempReg, /*TempRegID*//* 537(*/0x99, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28244 | GIR_MakeTempReg, /*TempRegID*//* 538(*/0x9A, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28245 | GIR_MakeTempReg, /*TempRegID*//* 539(*/0x9B, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28246 | GIR_MakeTempReg, /*TempRegID*//* 540(*/0x9C, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28247 | GIR_MakeTempReg, /*TempRegID*//* 541(*/0x9D, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28248 | GIR_MakeTempReg, /*TempRegID*//* 542(*/0x9E, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28249 | GIR_MakeTempReg, /*TempRegID*//* 543(*/0x9F, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28250 | GIR_MakeTempReg, /*TempRegID*//* 544(*/0xA0, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28251 | GIR_MakeTempReg, /*TempRegID*//* 545(*/0xA1, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28252 | GIR_MakeTempReg, /*TempRegID*//* 546(*/0xA2, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28253 | GIR_MakeTempReg, /*TempRegID*//* 547(*/0xA3, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28254 | GIR_BuildMI, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28255 | GIR_AddTempRegister, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, /*TempRegID*//* 547(*/0xA3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28256 | GIR_AddImm, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 28257 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 548(*/0xA4, 0x04/*)*/, |
| 28258 | GIR_BuildMI, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28259 | GIR_AddTempRegister, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*TempRegID*//* 546(*/0xA2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28260 | GIR_AddSimpleTempRegister, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*TempRegID*//* 547(*/0xA3, 0x04/*)*/, |
| 28261 | GIR_AddImm, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 28262 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 547(*/0xA3, 0x04/*)*/, |
| 28263 | GIR_BuildMI, /*InsnID*//* 546(*/0xA2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28264 | GIR_AddTempRegister, /*InsnID*//* 546(*/0xA2, 0x04/*)*/, /*TempRegID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28265 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 546(*/0xA2, 0x04/*)*/, |
| 28266 | GIR_BuildMI, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28267 | GIR_AddTempRegister, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegID*//* 544(*/0xA0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28268 | GIR_AddSimpleTempRegister, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegID*//* 545(*/0xA1, 0x04/*)*/, |
| 28269 | GIR_AddSimpleTempRegister, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*TempRegID*//* 546(*/0xA2, 0x04/*)*/, |
| 28270 | GIR_AddImm8, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Imm*/1, |
| 28271 | GIR_ConstrainOperandRC, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28272 | GIR_ConstrainOperandRC, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28273 | GIR_ConstrainOperandRC, /*InsnID*//* 545(*/0xA1, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28274 | GIR_BuildMI, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28275 | GIR_AddTempRegister, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*TempRegID*//* 543(*/0x9F, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28276 | GIR_AddSimpleTempRegister, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*TempRegID*//* 544(*/0xA0, 0x04/*)*/, |
| 28277 | GIR_AddImm8, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*Imm*/32, |
| 28278 | GIR_AddImm8, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, /*Imm*/31, |
| 28279 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 544(*/0xA0, 0x04/*)*/, |
| 28280 | GIR_BuildMI, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28281 | GIR_AddTempRegister, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*TempRegID*//* 542(*/0x9E, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28282 | GIR_AddSimpleTempRegister, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*TempRegID*//* 543(*/0x9F, 0x04/*)*/, |
| 28283 | GIR_AddImm, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 28284 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 543(*/0x9F, 0x04/*)*/, |
| 28285 | GIR_BuildMI, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28286 | GIR_AddTempRegister, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*TempRegID*//* 541(*/0x9D, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28287 | GIR_AddSimpleTempRegister, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*TempRegID*//* 542(*/0x9E, 0x04/*)*/, |
| 28288 | GIR_AddImm, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 28289 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 542(*/0x9E, 0x04/*)*/, |
| 28290 | GIR_BuildMI, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28291 | GIR_AddTempRegister, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, /*TempRegID*//* 540(*/0x9C, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28292 | GIR_AddImm, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28293 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 541(*/0x9D, 0x04/*)*/, |
| 28294 | GIR_BuildMI, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28295 | GIR_AddTempRegister, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*TempRegID*//* 539(*/0x9B, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28296 | GIR_AddSimpleTempRegister, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*TempRegID*//* 540(*/0x9C, 0x04/*)*/, |
| 28297 | GIR_AddImm, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28298 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 540(*/0x9C, 0x04/*)*/, |
| 28299 | GIR_BuildMI, /*InsnID*//* 539(*/0x9B, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28300 | GIR_AddTempRegister, /*InsnID*//* 539(*/0x9B, 0x04/*)*/, /*TempRegID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28301 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 539(*/0x9B, 0x04/*)*/, |
| 28302 | GIR_BuildMI, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28303 | GIR_AddTempRegister, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegID*//* 537(*/0x99, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28304 | GIR_AddSimpleTempRegister, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegID*//* 538(*/0x9A, 0x04/*)*/, |
| 28305 | GIR_AddSimpleTempRegister, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*TempRegID*//* 539(*/0x9B, 0x04/*)*/, |
| 28306 | GIR_AddImm8, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Imm*/1, |
| 28307 | GIR_ConstrainOperandRC, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28308 | GIR_ConstrainOperandRC, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28309 | GIR_ConstrainOperandRC, /*InsnID*//* 538(*/0x9A, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28310 | GIR_BuildMI, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28311 | GIR_AddTempRegister, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*TempRegID*//* 536(*/0x98, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28312 | GIR_AddSimpleTempRegister, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*TempRegID*//* 537(*/0x99, 0x04/*)*/, |
| 28313 | GIR_AddImm8, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*Imm*/32, |
| 28314 | GIR_AddImm8, /*InsnID*//* 537(*/0x99, 0x04/*)*/, /*Imm*/31, |
| 28315 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 537(*/0x99, 0x04/*)*/, |
| 28316 | GIR_BuildMI, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28317 | GIR_AddTempRegister, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*TempRegID*//* 535(*/0x97, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28318 | GIR_AddSimpleTempRegister, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*TempRegID*//* 536(*/0x98, 0x04/*)*/, |
| 28319 | GIR_AddImm, /*InsnID*//* 536(*/0x98, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28320 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 536(*/0x98, 0x04/*)*/, |
| 28321 | GIR_BuildMI, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28322 | GIR_AddTempRegister, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*TempRegID*//* 534(*/0x96, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28323 | GIR_AddSimpleTempRegister, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*TempRegID*//* 535(*/0x97, 0x04/*)*/, |
| 28324 | GIR_AddImm, /*InsnID*//* 535(*/0x97, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28325 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 535(*/0x97, 0x04/*)*/, |
| 28326 | GIR_BuildMI, /*InsnID*//* 534(*/0x96, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28327 | GIR_AddTempRegister, /*InsnID*//* 534(*/0x96, 0x04/*)*/, /*TempRegID*//* 533(*/0x95, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28328 | GIR_AddImm, /*InsnID*//* 534(*/0x96, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28329 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 534(*/0x96, 0x04/*)*/, |
| 28330 | GIR_BuildMI, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28331 | GIR_AddTempRegister, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*TempRegID*//* 532(*/0x94, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28332 | GIR_AddSimpleTempRegister, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*TempRegID*//* 533(*/0x95, 0x04/*)*/, |
| 28333 | GIR_AddImm, /*InsnID*//* 533(*/0x95, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28334 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 533(*/0x95, 0x04/*)*/, |
| 28335 | GIR_BuildMI, /*InsnID*//* 532(*/0x94, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28336 | GIR_AddTempRegister, /*InsnID*//* 532(*/0x94, 0x04/*)*/, /*TempRegID*//* 531(*/0x93, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28337 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 532(*/0x94, 0x04/*)*/, |
| 28338 | GIR_BuildMI, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28339 | GIR_AddTempRegister, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*TempRegID*//* 530(*/0x92, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28340 | GIR_AddSimpleTempRegister, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*TempRegID*//* 531(*/0x93, 0x04/*)*/, |
| 28341 | GIR_AddSimpleTempRegister, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*TempRegID*//* 532(*/0x94, 0x04/*)*/, |
| 28342 | GIR_AddImm8, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Imm*/1, |
| 28343 | GIR_ConstrainOperandRC, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28344 | GIR_ConstrainOperandRC, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28345 | GIR_ConstrainOperandRC, /*InsnID*//* 531(*/0x93, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28346 | GIR_BuildMI, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28347 | GIR_AddTempRegister, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*TempRegID*//* 529(*/0x91, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28348 | GIR_AddSimpleTempRegister, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*TempRegID*//* 530(*/0x92, 0x04/*)*/, |
| 28349 | GIR_AddImm8, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*Imm*/32, |
| 28350 | GIR_AddImm8, /*InsnID*//* 530(*/0x92, 0x04/*)*/, /*Imm*/31, |
| 28351 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 530(*/0x92, 0x04/*)*/, |
| 28352 | GIR_BuildMI, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28353 | GIR_AddTempRegister, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*TempRegID*//* 528(*/0x90, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28354 | GIR_AddSimpleTempRegister, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*TempRegID*//* 529(*/0x91, 0x04/*)*/, |
| 28355 | GIR_AddImm, /*InsnID*//* 529(*/0x91, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28356 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 529(*/0x91, 0x04/*)*/, |
| 28357 | GIR_BuildMI, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28358 | GIR_AddTempRegister, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*TempRegID*//* 527(*/0x8F, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28359 | GIR_AddSimpleTempRegister, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*TempRegID*//* 528(*/0x90, 0x04/*)*/, |
| 28360 | GIR_AddImm, /*InsnID*//* 528(*/0x90, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28361 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 528(*/0x90, 0x04/*)*/, |
| 28362 | GIR_BuildMI, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28363 | GIR_AddTempRegister, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*TempRegID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28364 | GIR_Copy, /*NewInsnID*//* 527(*/0x8F, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28365 | GIR_AddImm8, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*Imm*/1, |
| 28366 | GIR_AddImm8, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, /*Imm*/62, |
| 28367 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 527(*/0x8F, 0x04/*)*/, |
| 28368 | GIR_BuildMI, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28369 | GIR_AddTempRegister, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegID*//* 525(*/0x8D, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28370 | GIR_AddSimpleTempRegister, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegID*//* 526(*/0x8E, 0x04/*)*/, |
| 28371 | GIR_AddSimpleTempRegister, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, /*TempRegID*//* 527(*/0x8F, 0x04/*)*/, |
| 28372 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 526(*/0x8E, 0x04/*)*/, |
| 28373 | GIR_BuildMI, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28374 | GIR_AddTempRegister, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, /*TempRegID*//* 524(*/0x8C, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28375 | GIR_AddImm, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28376 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 525(*/0x8D, 0x04/*)*/, |
| 28377 | GIR_BuildMI, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28378 | GIR_AddTempRegister, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*TempRegID*//* 523(*/0x8B, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28379 | GIR_AddSimpleTempRegister, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*TempRegID*//* 524(*/0x8C, 0x04/*)*/, |
| 28380 | GIR_AddImm, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28381 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 524(*/0x8C, 0x04/*)*/, |
| 28382 | GIR_BuildMI, /*InsnID*//* 523(*/0x8B, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28383 | GIR_AddTempRegister, /*InsnID*//* 523(*/0x8B, 0x04/*)*/, /*TempRegID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28384 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 523(*/0x8B, 0x04/*)*/, |
| 28385 | GIR_BuildMI, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28386 | GIR_AddTempRegister, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegID*//* 521(*/0x89, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28387 | GIR_AddSimpleTempRegister, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegID*//* 522(*/0x8A, 0x04/*)*/, |
| 28388 | GIR_AddSimpleTempRegister, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*TempRegID*//* 523(*/0x8B, 0x04/*)*/, |
| 28389 | GIR_AddImm8, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Imm*/1, |
| 28390 | GIR_ConstrainOperandRC, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28391 | GIR_ConstrainOperandRC, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28392 | GIR_ConstrainOperandRC, /*InsnID*//* 522(*/0x8A, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28393 | GIR_BuildMI, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28394 | GIR_AddTempRegister, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*TempRegID*//* 520(*/0x88, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28395 | GIR_AddSimpleTempRegister, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*TempRegID*//* 521(*/0x89, 0x04/*)*/, |
| 28396 | GIR_AddImm8, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*Imm*/32, |
| 28397 | GIR_AddImm8, /*InsnID*//* 521(*/0x89, 0x04/*)*/, /*Imm*/31, |
| 28398 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 521(*/0x89, 0x04/*)*/, |
| 28399 | GIR_BuildMI, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28400 | GIR_AddTempRegister, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*TempRegID*//* 519(*/0x87, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28401 | GIR_AddSimpleTempRegister, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*TempRegID*//* 520(*/0x88, 0x04/*)*/, |
| 28402 | GIR_AddImm, /*InsnID*//* 520(*/0x88, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28403 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 520(*/0x88, 0x04/*)*/, |
| 28404 | GIR_BuildMI, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28405 | GIR_AddTempRegister, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*TempRegID*//* 518(*/0x86, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28406 | GIR_AddSimpleTempRegister, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*TempRegID*//* 519(*/0x87, 0x04/*)*/, |
| 28407 | GIR_AddImm, /*InsnID*//* 519(*/0x87, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28408 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 519(*/0x87, 0x04/*)*/, |
| 28409 | GIR_BuildMI, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28410 | GIR_AddTempRegister, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*TempRegID*//* 517(*/0x85, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28411 | GIR_Copy, /*NewInsnID*//* 518(*/0x86, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28412 | GIR_AddImm8, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*Imm*/63, |
| 28413 | GIR_AddImm8, /*InsnID*//* 518(*/0x86, 0x04/*)*/, /*Imm*/1, |
| 28414 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 518(*/0x86, 0x04/*)*/, |
| 28415 | GIR_BuildMI, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28416 | GIR_AddTempRegister, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*TempRegID*//* 516(*/0x84, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28417 | GIR_AddSimpleTempRegister, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*TempRegID*//* 517(*/0x85, 0x04/*)*/, |
| 28418 | GIR_AddSimpleTempRegister, /*InsnID*//* 517(*/0x85, 0x04/*)*/, /*TempRegID*//* 518(*/0x86, 0x04/*)*/, |
| 28419 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 517(*/0x85, 0x04/*)*/, |
| 28420 | GIR_BuildMI, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28421 | GIR_AddTempRegister, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*TempRegID*//* 515(*/0x83, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28422 | GIR_AddSimpleTempRegister, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*TempRegID*//* 516(*/0x84, 0x04/*)*/, |
| 28423 | GIR_AddSimpleTempRegister, /*InsnID*//* 516(*/0x84, 0x04/*)*/, /*TempRegID*//* 525(*/0x8D, 0x04/*)*/, |
| 28424 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 516(*/0x84, 0x04/*)*/, |
| 28425 | GIR_BuildMI, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28426 | GIR_AddTempRegister, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*TempRegID*//* 514(*/0x82, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28427 | GIR_AddSimpleTempRegister, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*TempRegID*//* 515(*/0x83, 0x04/*)*/, |
| 28428 | GIR_AddImm8, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*Imm*/2, |
| 28429 | GIR_AddImm8, /*InsnID*//* 515(*/0x83, 0x04/*)*/, /*Imm*/61, |
| 28430 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 515(*/0x83, 0x04/*)*/, |
| 28431 | GIR_BuildMI, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28432 | GIR_AddTempRegister, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*TempRegID*//* 513(*/0x81, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28433 | GIR_AddSimpleTempRegister, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*TempRegID*//* 514(*/0x82, 0x04/*)*/, |
| 28434 | GIR_AddSimpleTempRegister, /*InsnID*//* 514(*/0x82, 0x04/*)*/, /*TempRegID*//* 534(*/0x96, 0x04/*)*/, |
| 28435 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 514(*/0x82, 0x04/*)*/, |
| 28436 | GIR_BuildMI, /*InsnID*//* 513(*/0x81, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28437 | GIR_AddTempRegister, /*InsnID*//* 513(*/0x81, 0x04/*)*/, /*TempRegID*//* 512(*/0x80, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28438 | GIR_AddImm, /*InsnID*//* 513(*/0x81, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28439 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 513(*/0x81, 0x04/*)*/, |
| 28440 | GIR_BuildMI, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28441 | GIR_AddTempRegister, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*TempRegID*//* 511(*/0xFF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28442 | GIR_AddSimpleTempRegister, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*TempRegID*//* 512(*/0x80, 0x04/*)*/, |
| 28443 | GIR_AddImm, /*InsnID*//* 512(*/0x80, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28444 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 512(*/0x80, 0x04/*)*/, |
| 28445 | GIR_BuildMI, /*InsnID*//* 511(*/0xFF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28446 | GIR_AddTempRegister, /*InsnID*//* 511(*/0xFF, 0x03/*)*/, /*TempRegID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28447 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 511(*/0xFF, 0x03/*)*/, |
| 28448 | GIR_BuildMI, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28449 | GIR_AddTempRegister, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegID*//* 509(*/0xFD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28450 | GIR_AddSimpleTempRegister, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegID*//* 510(*/0xFE, 0x03/*)*/, |
| 28451 | GIR_AddSimpleTempRegister, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*TempRegID*//* 511(*/0xFF, 0x03/*)*/, |
| 28452 | GIR_AddImm8, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Imm*/1, |
| 28453 | GIR_ConstrainOperandRC, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28454 | GIR_ConstrainOperandRC, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28455 | GIR_ConstrainOperandRC, /*InsnID*//* 510(*/0xFE, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28456 | GIR_BuildMI, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28457 | GIR_AddTempRegister, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*TempRegID*//* 508(*/0xFC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28458 | GIR_AddSimpleTempRegister, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*TempRegID*//* 509(*/0xFD, 0x03/*)*/, |
| 28459 | GIR_AddImm8, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*Imm*/32, |
| 28460 | GIR_AddImm8, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, /*Imm*/31, |
| 28461 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 509(*/0xFD, 0x03/*)*/, |
| 28462 | GIR_BuildMI, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28463 | GIR_AddTempRegister, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*TempRegID*//* 507(*/0xFB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28464 | GIR_AddSimpleTempRegister, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*TempRegID*//* 508(*/0xFC, 0x03/*)*/, |
| 28465 | GIR_AddImm, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28466 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 508(*/0xFC, 0x03/*)*/, |
| 28467 | GIR_BuildMI, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28468 | GIR_AddTempRegister, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*TempRegID*//* 506(*/0xFA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28469 | GIR_AddSimpleTempRegister, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*TempRegID*//* 507(*/0xFB, 0x03/*)*/, |
| 28470 | GIR_AddImm, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28471 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 507(*/0xFB, 0x03/*)*/, |
| 28472 | GIR_BuildMI, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28473 | GIR_AddTempRegister, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, /*TempRegID*//* 505(*/0xF9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28474 | GIR_AddImm, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28475 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 506(*/0xFA, 0x03/*)*/, |
| 28476 | GIR_BuildMI, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28477 | GIR_AddTempRegister, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*TempRegID*//* 504(*/0xF8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28478 | GIR_AddSimpleTempRegister, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*TempRegID*//* 505(*/0xF9, 0x03/*)*/, |
| 28479 | GIR_AddImm, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28480 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 505(*/0xF9, 0x03/*)*/, |
| 28481 | GIR_BuildMI, /*InsnID*//* 504(*/0xF8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28482 | GIR_AddTempRegister, /*InsnID*//* 504(*/0xF8, 0x03/*)*/, /*TempRegID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28483 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 504(*/0xF8, 0x03/*)*/, |
| 28484 | GIR_BuildMI, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28485 | GIR_AddTempRegister, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegID*//* 502(*/0xF6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28486 | GIR_AddSimpleTempRegister, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegID*//* 503(*/0xF7, 0x03/*)*/, |
| 28487 | GIR_AddSimpleTempRegister, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*TempRegID*//* 504(*/0xF8, 0x03/*)*/, |
| 28488 | GIR_AddImm8, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Imm*/1, |
| 28489 | GIR_ConstrainOperandRC, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28490 | GIR_ConstrainOperandRC, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28491 | GIR_ConstrainOperandRC, /*InsnID*//* 503(*/0xF7, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28492 | GIR_BuildMI, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28493 | GIR_AddTempRegister, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*TempRegID*//* 501(*/0xF5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28494 | GIR_AddSimpleTempRegister, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*TempRegID*//* 502(*/0xF6, 0x03/*)*/, |
| 28495 | GIR_AddImm8, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*Imm*/32, |
| 28496 | GIR_AddImm8, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, /*Imm*/31, |
| 28497 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 502(*/0xF6, 0x03/*)*/, |
| 28498 | GIR_BuildMI, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28499 | GIR_AddTempRegister, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*TempRegID*//* 500(*/0xF4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28500 | GIR_AddSimpleTempRegister, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*TempRegID*//* 501(*/0xF5, 0x03/*)*/, |
| 28501 | GIR_AddImm, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28502 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 501(*/0xF5, 0x03/*)*/, |
| 28503 | GIR_BuildMI, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28504 | GIR_AddTempRegister, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*TempRegID*//* 499(*/0xF3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28505 | GIR_AddSimpleTempRegister, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*TempRegID*//* 500(*/0xF4, 0x03/*)*/, |
| 28506 | GIR_AddImm, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28507 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 500(*/0xF4, 0x03/*)*/, |
| 28508 | GIR_BuildMI, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28509 | GIR_AddTempRegister, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*TempRegID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28510 | GIR_Copy, /*NewInsnID*//* 499(*/0xF3, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28511 | GIR_AddImm8, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*Imm*/1, |
| 28512 | GIR_AddImm8, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, /*Imm*/62, |
| 28513 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 499(*/0xF3, 0x03/*)*/, |
| 28514 | GIR_BuildMI, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28515 | GIR_AddTempRegister, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegID*//* 497(*/0xF1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28516 | GIR_AddSimpleTempRegister, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegID*//* 498(*/0xF2, 0x03/*)*/, |
| 28517 | GIR_AddSimpleTempRegister, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, /*TempRegID*//* 499(*/0xF3, 0x03/*)*/, |
| 28518 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 498(*/0xF2, 0x03/*)*/, |
| 28519 | GIR_BuildMI, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28520 | GIR_AddTempRegister, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, /*TempRegID*//* 496(*/0xF0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28521 | GIR_AddImm, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28522 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 497(*/0xF1, 0x03/*)*/, |
| 28523 | GIR_BuildMI, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28524 | GIR_AddTempRegister, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*TempRegID*//* 495(*/0xEF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28525 | GIR_AddSimpleTempRegister, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*TempRegID*//* 496(*/0xF0, 0x03/*)*/, |
| 28526 | GIR_AddImm, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28527 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 496(*/0xF0, 0x03/*)*/, |
| 28528 | GIR_BuildMI, /*InsnID*//* 495(*/0xEF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28529 | GIR_AddTempRegister, /*InsnID*//* 495(*/0xEF, 0x03/*)*/, /*TempRegID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28530 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 495(*/0xEF, 0x03/*)*/, |
| 28531 | GIR_BuildMI, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28532 | GIR_AddTempRegister, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegID*//* 493(*/0xED, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28533 | GIR_AddSimpleTempRegister, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegID*//* 494(*/0xEE, 0x03/*)*/, |
| 28534 | GIR_AddSimpleTempRegister, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*TempRegID*//* 495(*/0xEF, 0x03/*)*/, |
| 28535 | GIR_AddImm8, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Imm*/1, |
| 28536 | GIR_ConstrainOperandRC, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28537 | GIR_ConstrainOperandRC, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28538 | GIR_ConstrainOperandRC, /*InsnID*//* 494(*/0xEE, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28539 | GIR_BuildMI, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28540 | GIR_AddTempRegister, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*TempRegID*//* 492(*/0xEC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28541 | GIR_AddSimpleTempRegister, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*TempRegID*//* 493(*/0xED, 0x03/*)*/, |
| 28542 | GIR_AddImm8, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*Imm*/32, |
| 28543 | GIR_AddImm8, /*InsnID*//* 493(*/0xED, 0x03/*)*/, /*Imm*/31, |
| 28544 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 493(*/0xED, 0x03/*)*/, |
| 28545 | GIR_BuildMI, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28546 | GIR_AddTempRegister, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*TempRegID*//* 491(*/0xEB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28547 | GIR_AddSimpleTempRegister, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*TempRegID*//* 492(*/0xEC, 0x03/*)*/, |
| 28548 | GIR_AddImm, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28549 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 492(*/0xEC, 0x03/*)*/, |
| 28550 | GIR_BuildMI, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28551 | GIR_AddTempRegister, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*TempRegID*//* 490(*/0xEA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28552 | GIR_AddSimpleTempRegister, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*TempRegID*//* 491(*/0xEB, 0x03/*)*/, |
| 28553 | GIR_AddImm, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28554 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 491(*/0xEB, 0x03/*)*/, |
| 28555 | GIR_BuildMI, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28556 | GIR_AddTempRegister, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*TempRegID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28557 | GIR_Copy, /*NewInsnID*//* 490(*/0xEA, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28558 | GIR_AddImm8, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*Imm*/63, |
| 28559 | GIR_AddImm8, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, /*Imm*/1, |
| 28560 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 490(*/0xEA, 0x03/*)*/, |
| 28561 | GIR_BuildMI, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28562 | GIR_AddTempRegister, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28563 | GIR_AddSimpleTempRegister, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegID*//* 489(*/0xE9, 0x03/*)*/, |
| 28564 | GIR_AddSimpleTempRegister, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, /*TempRegID*//* 490(*/0xEA, 0x03/*)*/, |
| 28565 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 489(*/0xE9, 0x03/*)*/, |
| 28566 | GIR_BuildMI, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28567 | GIR_AddTempRegister, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegID*//* 487(*/0xE7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28568 | GIR_AddSimpleTempRegister, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegID*//* 488(*/0xE8, 0x03/*)*/, |
| 28569 | GIR_AddSimpleTempRegister, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, /*TempRegID*//* 497(*/0xF1, 0x03/*)*/, |
| 28570 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 488(*/0xE8, 0x03/*)*/, |
| 28571 | GIR_BuildMI, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28572 | GIR_AddTempRegister, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*TempRegID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28573 | GIR_AddSimpleTempRegister, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*TempRegID*//* 487(*/0xE7, 0x03/*)*/, |
| 28574 | GIR_AddImm8, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*Imm*/62, |
| 28575 | GIR_AddImm8, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, /*Imm*/2, |
| 28576 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 487(*/0xE7, 0x03/*)*/, |
| 28577 | GIR_BuildMI, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28578 | GIR_AddTempRegister, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28579 | GIR_AddSimpleTempRegister, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegID*//* 486(*/0xE6, 0x03/*)*/, |
| 28580 | GIR_AddSimpleTempRegister, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, /*TempRegID*//* 506(*/0xFA, 0x03/*)*/, |
| 28581 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 486(*/0xE6, 0x03/*)*/, |
| 28582 | GIR_BuildMI, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28583 | GIR_AddTempRegister, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegID*//* 484(*/0xE4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28584 | GIR_AddSimpleTempRegister, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegID*//* 485(*/0xE5, 0x03/*)*/, |
| 28585 | GIR_AddSimpleTempRegister, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, /*TempRegID*//* 513(*/0x81, 0x04/*)*/, |
| 28586 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 485(*/0xE5, 0x03/*)*/, |
| 28587 | GIR_BuildMI, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28588 | GIR_AddTempRegister, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*TempRegID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28589 | GIR_AddSimpleTempRegister, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*TempRegID*//* 484(*/0xE4, 0x03/*)*/, |
| 28590 | GIR_AddImm8, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*Imm*/4, |
| 28591 | GIR_AddImm8, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, /*Imm*/59, |
| 28592 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 484(*/0xE4, 0x03/*)*/, |
| 28593 | GIR_BuildMI, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28594 | GIR_AddTempRegister, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegID*//* 482(*/0xE2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28595 | GIR_AddSimpleTempRegister, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegID*//* 483(*/0xE3, 0x03/*)*/, |
| 28596 | GIR_AddSimpleTempRegister, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, /*TempRegID*//* 541(*/0x9D, 0x04/*)*/, |
| 28597 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 483(*/0xE3, 0x03/*)*/, |
| 28598 | GIR_BuildMI, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28599 | GIR_AddTempRegister, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, /*TempRegID*//* 481(*/0xE1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28600 | GIR_AddImm, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 28601 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 482(*/0xE2, 0x03/*)*/, |
| 28602 | GIR_BuildMI, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28603 | GIR_AddTempRegister, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*TempRegID*//* 480(*/0xE0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28604 | GIR_AddSimpleTempRegister, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*TempRegID*//* 481(*/0xE1, 0x03/*)*/, |
| 28605 | GIR_AddImm, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 28606 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 481(*/0xE1, 0x03/*)*/, |
| 28607 | GIR_BuildMI, /*InsnID*//* 480(*/0xE0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28608 | GIR_AddTempRegister, /*InsnID*//* 480(*/0xE0, 0x03/*)*/, /*TempRegID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28609 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 480(*/0xE0, 0x03/*)*/, |
| 28610 | GIR_BuildMI, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28611 | GIR_AddTempRegister, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegID*//* 478(*/0xDE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28612 | GIR_AddSimpleTempRegister, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegID*//* 479(*/0xDF, 0x03/*)*/, |
| 28613 | GIR_AddSimpleTempRegister, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*TempRegID*//* 480(*/0xE0, 0x03/*)*/, |
| 28614 | GIR_AddImm8, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Imm*/1, |
| 28615 | GIR_ConstrainOperandRC, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28616 | GIR_ConstrainOperandRC, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28617 | GIR_ConstrainOperandRC, /*InsnID*//* 479(*/0xDF, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28618 | GIR_BuildMI, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28619 | GIR_AddTempRegister, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*TempRegID*//* 477(*/0xDD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28620 | GIR_AddSimpleTempRegister, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*TempRegID*//* 478(*/0xDE, 0x03/*)*/, |
| 28621 | GIR_AddImm8, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*Imm*/32, |
| 28622 | GIR_AddImm8, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, /*Imm*/31, |
| 28623 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 478(*/0xDE, 0x03/*)*/, |
| 28624 | GIR_BuildMI, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28625 | GIR_AddTempRegister, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*TempRegID*//* 476(*/0xDC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28626 | GIR_AddSimpleTempRegister, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*TempRegID*//* 477(*/0xDD, 0x03/*)*/, |
| 28627 | GIR_AddImm, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 28628 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 477(*/0xDD, 0x03/*)*/, |
| 28629 | GIR_BuildMI, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28630 | GIR_AddTempRegister, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*TempRegID*//* 475(*/0xDB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28631 | GIR_AddSimpleTempRegister, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*TempRegID*//* 476(*/0xDC, 0x03/*)*/, |
| 28632 | GIR_AddImm, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 28633 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 476(*/0xDC, 0x03/*)*/, |
| 28634 | GIR_BuildMI, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28635 | GIR_AddTempRegister, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, /*TempRegID*//* 474(*/0xDA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28636 | GIR_AddImm, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28637 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 475(*/0xDB, 0x03/*)*/, |
| 28638 | GIR_BuildMI, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28639 | GIR_AddTempRegister, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*TempRegID*//* 473(*/0xD9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28640 | GIR_AddSimpleTempRegister, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*TempRegID*//* 474(*/0xDA, 0x03/*)*/, |
| 28641 | GIR_AddImm, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28642 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 474(*/0xDA, 0x03/*)*/, |
| 28643 | GIR_BuildMI, /*InsnID*//* 473(*/0xD9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28644 | GIR_AddTempRegister, /*InsnID*//* 473(*/0xD9, 0x03/*)*/, /*TempRegID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28645 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 473(*/0xD9, 0x03/*)*/, |
| 28646 | GIR_BuildMI, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28647 | GIR_AddTempRegister, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegID*//* 471(*/0xD7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28648 | GIR_AddSimpleTempRegister, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegID*//* 472(*/0xD8, 0x03/*)*/, |
| 28649 | GIR_AddSimpleTempRegister, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*TempRegID*//* 473(*/0xD9, 0x03/*)*/, |
| 28650 | GIR_AddImm8, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Imm*/1, |
| 28651 | GIR_ConstrainOperandRC, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28652 | GIR_ConstrainOperandRC, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28653 | GIR_ConstrainOperandRC, /*InsnID*//* 472(*/0xD8, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28654 | GIR_BuildMI, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28655 | GIR_AddTempRegister, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*TempRegID*//* 470(*/0xD6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28656 | GIR_AddSimpleTempRegister, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*TempRegID*//* 471(*/0xD7, 0x03/*)*/, |
| 28657 | GIR_AddImm8, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*Imm*/32, |
| 28658 | GIR_AddImm8, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, /*Imm*/31, |
| 28659 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 471(*/0xD7, 0x03/*)*/, |
| 28660 | GIR_BuildMI, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28661 | GIR_AddTempRegister, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*TempRegID*//* 469(*/0xD5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28662 | GIR_AddSimpleTempRegister, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*TempRegID*//* 470(*/0xD6, 0x03/*)*/, |
| 28663 | GIR_AddImm, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28664 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 470(*/0xD6, 0x03/*)*/, |
| 28665 | GIR_BuildMI, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28666 | GIR_AddTempRegister, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*TempRegID*//* 468(*/0xD4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28667 | GIR_AddSimpleTempRegister, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*TempRegID*//* 469(*/0xD5, 0x03/*)*/, |
| 28668 | GIR_AddImm, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 28669 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 469(*/0xD5, 0x03/*)*/, |
| 28670 | GIR_BuildMI, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28671 | GIR_AddTempRegister, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, /*TempRegID*//* 467(*/0xD3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28672 | GIR_AddImm, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28673 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 468(*/0xD4, 0x03/*)*/, |
| 28674 | GIR_BuildMI, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28675 | GIR_AddTempRegister, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*TempRegID*//* 466(*/0xD2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28676 | GIR_AddSimpleTempRegister, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*TempRegID*//* 467(*/0xD3, 0x03/*)*/, |
| 28677 | GIR_AddImm, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28678 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 467(*/0xD3, 0x03/*)*/, |
| 28679 | GIR_BuildMI, /*InsnID*//* 466(*/0xD2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28680 | GIR_AddTempRegister, /*InsnID*//* 466(*/0xD2, 0x03/*)*/, /*TempRegID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28681 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 466(*/0xD2, 0x03/*)*/, |
| 28682 | GIR_BuildMI, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28683 | GIR_AddTempRegister, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegID*//* 464(*/0xD0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28684 | GIR_AddSimpleTempRegister, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegID*//* 465(*/0xD1, 0x03/*)*/, |
| 28685 | GIR_AddSimpleTempRegister, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*TempRegID*//* 466(*/0xD2, 0x03/*)*/, |
| 28686 | GIR_AddImm8, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Imm*/1, |
| 28687 | GIR_ConstrainOperandRC, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28688 | GIR_ConstrainOperandRC, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28689 | GIR_ConstrainOperandRC, /*InsnID*//* 465(*/0xD1, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28690 | GIR_BuildMI, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28691 | GIR_AddTempRegister, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*TempRegID*//* 463(*/0xCF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28692 | GIR_AddSimpleTempRegister, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*TempRegID*//* 464(*/0xD0, 0x03/*)*/, |
| 28693 | GIR_AddImm8, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*Imm*/32, |
| 28694 | GIR_AddImm8, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, /*Imm*/31, |
| 28695 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 464(*/0xD0, 0x03/*)*/, |
| 28696 | GIR_BuildMI, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28697 | GIR_AddTempRegister, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*TempRegID*//* 462(*/0xCE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28698 | GIR_AddSimpleTempRegister, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*TempRegID*//* 463(*/0xCF, 0x03/*)*/, |
| 28699 | GIR_AddImm, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28700 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 463(*/0xCF, 0x03/*)*/, |
| 28701 | GIR_BuildMI, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28702 | GIR_AddTempRegister, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*TempRegID*//* 461(*/0xCD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28703 | GIR_AddSimpleTempRegister, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*TempRegID*//* 462(*/0xCE, 0x03/*)*/, |
| 28704 | GIR_AddImm, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28705 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 462(*/0xCE, 0x03/*)*/, |
| 28706 | GIR_BuildMI, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28707 | GIR_AddTempRegister, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*TempRegID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28708 | GIR_Copy, /*NewInsnID*//* 461(*/0xCD, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28709 | GIR_AddImm8, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*Imm*/1, |
| 28710 | GIR_AddImm8, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, /*Imm*/62, |
| 28711 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 461(*/0xCD, 0x03/*)*/, |
| 28712 | GIR_BuildMI, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28713 | GIR_AddTempRegister, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegID*//* 459(*/0xCB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28714 | GIR_AddSimpleTempRegister, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegID*//* 460(*/0xCC, 0x03/*)*/, |
| 28715 | GIR_AddSimpleTempRegister, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, /*TempRegID*//* 461(*/0xCD, 0x03/*)*/, |
| 28716 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 460(*/0xCC, 0x03/*)*/, |
| 28717 | GIR_BuildMI, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28718 | GIR_AddTempRegister, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, /*TempRegID*//* 458(*/0xCA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28719 | GIR_AddImm, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28720 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 459(*/0xCB, 0x03/*)*/, |
| 28721 | GIR_BuildMI, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28722 | GIR_AddTempRegister, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*TempRegID*//* 457(*/0xC9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28723 | GIR_AddSimpleTempRegister, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*TempRegID*//* 458(*/0xCA, 0x03/*)*/, |
| 28724 | GIR_AddImm, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28725 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 458(*/0xCA, 0x03/*)*/, |
| 28726 | GIR_BuildMI, /*InsnID*//* 457(*/0xC9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28727 | GIR_AddTempRegister, /*InsnID*//* 457(*/0xC9, 0x03/*)*/, /*TempRegID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28728 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 457(*/0xC9, 0x03/*)*/, |
| 28729 | GIR_BuildMI, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28730 | GIR_AddTempRegister, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegID*//* 455(*/0xC7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28731 | GIR_AddSimpleTempRegister, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegID*//* 456(*/0xC8, 0x03/*)*/, |
| 28732 | GIR_AddSimpleTempRegister, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*TempRegID*//* 457(*/0xC9, 0x03/*)*/, |
| 28733 | GIR_AddImm8, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Imm*/1, |
| 28734 | GIR_ConstrainOperandRC, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28735 | GIR_ConstrainOperandRC, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28736 | GIR_ConstrainOperandRC, /*InsnID*//* 456(*/0xC8, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28737 | GIR_BuildMI, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28738 | GIR_AddTempRegister, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*TempRegID*//* 454(*/0xC6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28739 | GIR_AddSimpleTempRegister, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*TempRegID*//* 455(*/0xC7, 0x03/*)*/, |
| 28740 | GIR_AddImm8, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*Imm*/32, |
| 28741 | GIR_AddImm8, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, /*Imm*/31, |
| 28742 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 455(*/0xC7, 0x03/*)*/, |
| 28743 | GIR_BuildMI, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28744 | GIR_AddTempRegister, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*TempRegID*//* 453(*/0xC5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28745 | GIR_AddSimpleTempRegister, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*TempRegID*//* 454(*/0xC6, 0x03/*)*/, |
| 28746 | GIR_AddImm, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28747 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 454(*/0xC6, 0x03/*)*/, |
| 28748 | GIR_BuildMI, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28749 | GIR_AddTempRegister, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*TempRegID*//* 452(*/0xC4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28750 | GIR_AddSimpleTempRegister, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*TempRegID*//* 453(*/0xC5, 0x03/*)*/, |
| 28751 | GIR_AddImm, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28752 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 453(*/0xC5, 0x03/*)*/, |
| 28753 | GIR_BuildMI, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28754 | GIR_AddTempRegister, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*TempRegID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28755 | GIR_Copy, /*NewInsnID*//* 452(*/0xC4, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28756 | GIR_AddImm8, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*Imm*/63, |
| 28757 | GIR_AddImm8, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, /*Imm*/1, |
| 28758 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 452(*/0xC4, 0x03/*)*/, |
| 28759 | GIR_BuildMI, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28760 | GIR_AddTempRegister, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28761 | GIR_AddSimpleTempRegister, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegID*//* 451(*/0xC3, 0x03/*)*/, |
| 28762 | GIR_AddSimpleTempRegister, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, /*TempRegID*//* 452(*/0xC4, 0x03/*)*/, |
| 28763 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 451(*/0xC3, 0x03/*)*/, |
| 28764 | GIR_BuildMI, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28765 | GIR_AddTempRegister, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegID*//* 449(*/0xC1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28766 | GIR_AddSimpleTempRegister, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegID*//* 450(*/0xC2, 0x03/*)*/, |
| 28767 | GIR_AddSimpleTempRegister, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, /*TempRegID*//* 459(*/0xCB, 0x03/*)*/, |
| 28768 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 450(*/0xC2, 0x03/*)*/, |
| 28769 | GIR_BuildMI, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28770 | GIR_AddTempRegister, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*TempRegID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28771 | GIR_AddSimpleTempRegister, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*TempRegID*//* 449(*/0xC1, 0x03/*)*/, |
| 28772 | GIR_AddImm8, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*Imm*/2, |
| 28773 | GIR_AddImm8, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, /*Imm*/61, |
| 28774 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 449(*/0xC1, 0x03/*)*/, |
| 28775 | GIR_BuildMI, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28776 | GIR_AddTempRegister, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegID*//* 447(*/0xBF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28777 | GIR_AddSimpleTempRegister, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegID*//* 448(*/0xC0, 0x03/*)*/, |
| 28778 | GIR_AddSimpleTempRegister, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, /*TempRegID*//* 468(*/0xD4, 0x03/*)*/, |
| 28779 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 448(*/0xC0, 0x03/*)*/, |
| 28780 | GIR_BuildMI, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28781 | GIR_AddTempRegister, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, /*TempRegID*//* 446(*/0xBE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28782 | GIR_AddImm, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28783 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 447(*/0xBF, 0x03/*)*/, |
| 28784 | GIR_BuildMI, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28785 | GIR_AddTempRegister, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*TempRegID*//* 445(*/0xBD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28786 | GIR_AddSimpleTempRegister, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*TempRegID*//* 446(*/0xBE, 0x03/*)*/, |
| 28787 | GIR_AddImm, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28788 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 446(*/0xBE, 0x03/*)*/, |
| 28789 | GIR_BuildMI, /*InsnID*//* 445(*/0xBD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28790 | GIR_AddTempRegister, /*InsnID*//* 445(*/0xBD, 0x03/*)*/, /*TempRegID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28791 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 445(*/0xBD, 0x03/*)*/, |
| 28792 | GIR_BuildMI, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28793 | GIR_AddTempRegister, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegID*//* 443(*/0xBB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28794 | GIR_AddSimpleTempRegister, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegID*//* 444(*/0xBC, 0x03/*)*/, |
| 28795 | GIR_AddSimpleTempRegister, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*TempRegID*//* 445(*/0xBD, 0x03/*)*/, |
| 28796 | GIR_AddImm8, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Imm*/1, |
| 28797 | GIR_ConstrainOperandRC, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28798 | GIR_ConstrainOperandRC, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28799 | GIR_ConstrainOperandRC, /*InsnID*//* 444(*/0xBC, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28800 | GIR_BuildMI, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28801 | GIR_AddTempRegister, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*TempRegID*//* 442(*/0xBA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28802 | GIR_AddSimpleTempRegister, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*TempRegID*//* 443(*/0xBB, 0x03/*)*/, |
| 28803 | GIR_AddImm8, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*Imm*/32, |
| 28804 | GIR_AddImm8, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, /*Imm*/31, |
| 28805 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 443(*/0xBB, 0x03/*)*/, |
| 28806 | GIR_BuildMI, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28807 | GIR_AddTempRegister, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*TempRegID*//* 441(*/0xB9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28808 | GIR_AddSimpleTempRegister, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*TempRegID*//* 442(*/0xBA, 0x03/*)*/, |
| 28809 | GIR_AddImm, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28810 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 442(*/0xBA, 0x03/*)*/, |
| 28811 | GIR_BuildMI, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28812 | GIR_AddTempRegister, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*TempRegID*//* 440(*/0xB8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28813 | GIR_AddSimpleTempRegister, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*TempRegID*//* 441(*/0xB9, 0x03/*)*/, |
| 28814 | GIR_AddImm, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 28815 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 441(*/0xB9, 0x03/*)*/, |
| 28816 | GIR_BuildMI, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28817 | GIR_AddTempRegister, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, /*TempRegID*//* 439(*/0xB7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28818 | GIR_AddImm, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28819 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 440(*/0xB8, 0x03/*)*/, |
| 28820 | GIR_BuildMI, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28821 | GIR_AddTempRegister, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*TempRegID*//* 438(*/0xB6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28822 | GIR_AddSimpleTempRegister, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*TempRegID*//* 439(*/0xB7, 0x03/*)*/, |
| 28823 | GIR_AddImm, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28824 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 439(*/0xB7, 0x03/*)*/, |
| 28825 | GIR_BuildMI, /*InsnID*//* 438(*/0xB6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28826 | GIR_AddTempRegister, /*InsnID*//* 438(*/0xB6, 0x03/*)*/, /*TempRegID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28827 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 438(*/0xB6, 0x03/*)*/, |
| 28828 | GIR_BuildMI, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28829 | GIR_AddTempRegister, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegID*//* 436(*/0xB4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28830 | GIR_AddSimpleTempRegister, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegID*//* 437(*/0xB5, 0x03/*)*/, |
| 28831 | GIR_AddSimpleTempRegister, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*TempRegID*//* 438(*/0xB6, 0x03/*)*/, |
| 28832 | GIR_AddImm8, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Imm*/1, |
| 28833 | GIR_ConstrainOperandRC, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28834 | GIR_ConstrainOperandRC, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28835 | GIR_ConstrainOperandRC, /*InsnID*//* 437(*/0xB5, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28836 | GIR_BuildMI, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28837 | GIR_AddTempRegister, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*TempRegID*//* 435(*/0xB3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28838 | GIR_AddSimpleTempRegister, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*TempRegID*//* 436(*/0xB4, 0x03/*)*/, |
| 28839 | GIR_AddImm8, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*Imm*/32, |
| 28840 | GIR_AddImm8, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, /*Imm*/31, |
| 28841 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 436(*/0xB4, 0x03/*)*/, |
| 28842 | GIR_BuildMI, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28843 | GIR_AddTempRegister, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*TempRegID*//* 434(*/0xB2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28844 | GIR_AddSimpleTempRegister, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*TempRegID*//* 435(*/0xB3, 0x03/*)*/, |
| 28845 | GIR_AddImm, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28846 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 435(*/0xB3, 0x03/*)*/, |
| 28847 | GIR_BuildMI, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28848 | GIR_AddTempRegister, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*TempRegID*//* 433(*/0xB1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28849 | GIR_AddSimpleTempRegister, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*TempRegID*//* 434(*/0xB2, 0x03/*)*/, |
| 28850 | GIR_AddImm, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 28851 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 434(*/0xB2, 0x03/*)*/, |
| 28852 | GIR_BuildMI, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28853 | GIR_AddTempRegister, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*TempRegID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28854 | GIR_Copy, /*NewInsnID*//* 433(*/0xB1, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28855 | GIR_AddImm8, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*Imm*/1, |
| 28856 | GIR_AddImm8, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, /*Imm*/62, |
| 28857 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 433(*/0xB1, 0x03/*)*/, |
| 28858 | GIR_BuildMI, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28859 | GIR_AddTempRegister, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegID*//* 431(*/0xAF, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28860 | GIR_AddSimpleTempRegister, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegID*//* 432(*/0xB0, 0x03/*)*/, |
| 28861 | GIR_AddSimpleTempRegister, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, /*TempRegID*//* 433(*/0xB1, 0x03/*)*/, |
| 28862 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 432(*/0xB0, 0x03/*)*/, |
| 28863 | GIR_BuildMI, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 28864 | GIR_AddTempRegister, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, /*TempRegID*//* 430(*/0xAE, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28865 | GIR_AddImm, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28866 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 431(*/0xAF, 0x03/*)*/, |
| 28867 | GIR_BuildMI, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 28868 | GIR_AddTempRegister, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*TempRegID*//* 429(*/0xAD, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28869 | GIR_AddSimpleTempRegister, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*TempRegID*//* 430(*/0xAE, 0x03/*)*/, |
| 28870 | GIR_AddImm, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28871 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 430(*/0xAE, 0x03/*)*/, |
| 28872 | GIR_BuildMI, /*InsnID*//* 429(*/0xAD, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28873 | GIR_AddTempRegister, /*InsnID*//* 429(*/0xAD, 0x03/*)*/, /*TempRegID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28874 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 429(*/0xAD, 0x03/*)*/, |
| 28875 | GIR_BuildMI, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28876 | GIR_AddTempRegister, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegID*//* 427(*/0xAB, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28877 | GIR_AddSimpleTempRegister, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegID*//* 428(*/0xAC, 0x03/*)*/, |
| 28878 | GIR_AddSimpleTempRegister, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*TempRegID*//* 429(*/0xAD, 0x03/*)*/, |
| 28879 | GIR_AddImm8, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Imm*/1, |
| 28880 | GIR_ConstrainOperandRC, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28881 | GIR_ConstrainOperandRC, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 28882 | GIR_ConstrainOperandRC, /*InsnID*//* 428(*/0xAC, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 28883 | GIR_BuildMI, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 28884 | GIR_AddTempRegister, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*TempRegID*//* 426(*/0xAA, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28885 | GIR_AddSimpleTempRegister, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*TempRegID*//* 427(*/0xAB, 0x03/*)*/, |
| 28886 | GIR_AddImm8, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*Imm*/32, |
| 28887 | GIR_AddImm8, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, /*Imm*/31, |
| 28888 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 427(*/0xAB, 0x03/*)*/, |
| 28889 | GIR_BuildMI, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 28890 | GIR_AddTempRegister, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*TempRegID*//* 425(*/0xA9, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28891 | GIR_AddSimpleTempRegister, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*TempRegID*//* 426(*/0xAA, 0x03/*)*/, |
| 28892 | GIR_AddImm, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28893 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 426(*/0xAA, 0x03/*)*/, |
| 28894 | GIR_BuildMI, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 28895 | GIR_AddTempRegister, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*TempRegID*//* 424(*/0xA8, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28896 | GIR_AddSimpleTempRegister, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*TempRegID*//* 425(*/0xA9, 0x03/*)*/, |
| 28897 | GIR_AddImm, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 28898 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 425(*/0xA9, 0x03/*)*/, |
| 28899 | GIR_BuildMI, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28900 | GIR_AddTempRegister, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*TempRegID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28901 | GIR_Copy, /*NewInsnID*//* 424(*/0xA8, 0x03/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 28902 | GIR_AddImm8, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*Imm*/63, |
| 28903 | GIR_AddImm8, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, /*Imm*/1, |
| 28904 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 424(*/0xA8, 0x03/*)*/, |
| 28905 | GIR_BuildMI, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28906 | GIR_AddTempRegister, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28907 | GIR_AddSimpleTempRegister, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegID*//* 423(*/0xA7, 0x03/*)*/, |
| 28908 | GIR_AddSimpleTempRegister, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, /*TempRegID*//* 424(*/0xA8, 0x03/*)*/, |
| 28909 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 423(*/0xA7, 0x03/*)*/, |
| 28910 | GIR_BuildMI, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28911 | GIR_AddTempRegister, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegID*//* 421(*/0xA5, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28912 | GIR_AddSimpleTempRegister, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegID*//* 422(*/0xA6, 0x03/*)*/, |
| 28913 | GIR_AddSimpleTempRegister, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, /*TempRegID*//* 431(*/0xAF, 0x03/*)*/, |
| 28914 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 422(*/0xA6, 0x03/*)*/, |
| 28915 | GIR_BuildMI, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28916 | GIR_AddTempRegister, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*TempRegID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28917 | GIR_AddSimpleTempRegister, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*TempRegID*//* 421(*/0xA5, 0x03/*)*/, |
| 28918 | GIR_AddImm8, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*Imm*/62, |
| 28919 | GIR_AddImm8, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, /*Imm*/2, |
| 28920 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 421(*/0xA5, 0x03/*)*/, |
| 28921 | GIR_BuildMI, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28922 | GIR_AddTempRegister, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28923 | GIR_AddSimpleTempRegister, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegID*//* 420(*/0xA4, 0x03/*)*/, |
| 28924 | GIR_AddSimpleTempRegister, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, /*TempRegID*//* 440(*/0xB8, 0x03/*)*/, |
| 28925 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 420(*/0xA4, 0x03/*)*/, |
| 28926 | GIR_BuildMI, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28927 | GIR_AddTempRegister, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegID*//* 418(*/0xA2, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28928 | GIR_AddSimpleTempRegister, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegID*//* 419(*/0xA3, 0x03/*)*/, |
| 28929 | GIR_AddSimpleTempRegister, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, /*TempRegID*//* 447(*/0xBF, 0x03/*)*/, |
| 28930 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 419(*/0xA3, 0x03/*)*/, |
| 28931 | GIR_BuildMI, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28932 | GIR_AddTempRegister, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*TempRegID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28933 | GIR_AddSimpleTempRegister, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*TempRegID*//* 418(*/0xA2, 0x03/*)*/, |
| 28934 | GIR_AddImm8, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*Imm*/60, |
| 28935 | GIR_AddImm8, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, /*Imm*/4, |
| 28936 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 418(*/0xA2, 0x03/*)*/, |
| 28937 | GIR_BuildMI, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 28938 | GIR_AddTempRegister, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28939 | GIR_AddSimpleTempRegister, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegID*//* 417(*/0xA1, 0x03/*)*/, |
| 28940 | GIR_AddSimpleTempRegister, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, /*TempRegID*//* 475(*/0xDB, 0x03/*)*/, |
| 28941 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 417(*/0xA1, 0x03/*)*/, |
| 28942 | GIR_BuildMI, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 28943 | GIR_AddTempRegister, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegID*//* 415(*/0x9F, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28944 | GIR_AddSimpleTempRegister, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegID*//* 416(*/0xA0, 0x03/*)*/, |
| 28945 | GIR_AddSimpleTempRegister, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, /*TempRegID*//* 482(*/0xE2, 0x03/*)*/, |
| 28946 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 416(*/0xA0, 0x03/*)*/, |
| 28947 | GIR_BuildMI, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 28948 | GIR_AddTempRegister, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*TempRegID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 28949 | GIR_AddSimpleTempRegister, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*TempRegID*//* 415(*/0x9F, 0x03/*)*/, |
| 28950 | GIR_AddImm8, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*Imm*/32, |
| 28951 | GIR_AddImm8, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, /*Imm*/32, |
| 28952 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 415(*/0x9F, 0x03/*)*/, |
| 28953 | GIR_MakeTempReg, /*TempRegID*//* 548(*/0xA4, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28954 | GIR_MakeTempReg, /*TempRegID*//* 549(*/0xA5, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28955 | GIR_MakeTempReg, /*TempRegID*//* 550(*/0xA6, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28956 | GIR_MakeTempReg, /*TempRegID*//* 551(*/0xA7, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28957 | GIR_MakeTempReg, /*TempRegID*//* 552(*/0xA8, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28958 | GIR_MakeTempReg, /*TempRegID*//* 553(*/0xA9, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28959 | GIR_MakeTempReg, /*TempRegID*//* 554(*/0xAA, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28960 | GIR_MakeTempReg, /*TempRegID*//* 555(*/0xAB, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28961 | GIR_MakeTempReg, /*TempRegID*//* 556(*/0xAC, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28962 | GIR_MakeTempReg, /*TempRegID*//* 557(*/0xAD, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28963 | GIR_MakeTempReg, /*TempRegID*//* 558(*/0xAE, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28964 | GIR_MakeTempReg, /*TempRegID*//* 559(*/0xAF, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28965 | GIR_MakeTempReg, /*TempRegID*//* 560(*/0xB0, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28966 | GIR_MakeTempReg, /*TempRegID*//* 561(*/0xB1, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28967 | GIR_MakeTempReg, /*TempRegID*//* 562(*/0xB2, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28968 | GIR_MakeTempReg, /*TempRegID*//* 563(*/0xB3, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28969 | GIR_MakeTempReg, /*TempRegID*//* 564(*/0xB4, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28970 | GIR_MakeTempReg, /*TempRegID*//* 565(*/0xB5, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28971 | GIR_MakeTempReg, /*TempRegID*//* 566(*/0xB6, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28972 | GIR_MakeTempReg, /*TempRegID*//* 567(*/0xB7, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28973 | GIR_MakeTempReg, /*TempRegID*//* 568(*/0xB8, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28974 | GIR_MakeTempReg, /*TempRegID*//* 569(*/0xB9, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28975 | GIR_MakeTempReg, /*TempRegID*//* 570(*/0xBA, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28976 | GIR_MakeTempReg, /*TempRegID*//* 571(*/0xBB, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28977 | GIR_MakeTempReg, /*TempRegID*//* 572(*/0xBC, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28978 | GIR_MakeTempReg, /*TempRegID*//* 573(*/0xBD, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28979 | GIR_MakeTempReg, /*TempRegID*//* 574(*/0xBE, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28980 | GIR_MakeTempReg, /*TempRegID*//* 575(*/0xBF, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28981 | GIR_MakeTempReg, /*TempRegID*//* 576(*/0xC0, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28982 | GIR_MakeTempReg, /*TempRegID*//* 577(*/0xC1, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28983 | GIR_MakeTempReg, /*TempRegID*//* 578(*/0xC2, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28984 | GIR_MakeTempReg, /*TempRegID*//* 579(*/0xC3, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28985 | GIR_MakeTempReg, /*TempRegID*//* 580(*/0xC4, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28986 | GIR_MakeTempReg, /*TempRegID*//* 581(*/0xC5, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28987 | GIR_MakeTempReg, /*TempRegID*//* 582(*/0xC6, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28988 | GIR_MakeTempReg, /*TempRegID*//* 583(*/0xC7, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28989 | GIR_MakeTempReg, /*TempRegID*//* 584(*/0xC8, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28990 | GIR_MakeTempReg, /*TempRegID*//* 585(*/0xC9, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28991 | GIR_MakeTempReg, /*TempRegID*//* 586(*/0xCA, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28992 | GIR_MakeTempReg, /*TempRegID*//* 587(*/0xCB, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28993 | GIR_MakeTempReg, /*TempRegID*//* 588(*/0xCC, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28994 | GIR_MakeTempReg, /*TempRegID*//* 589(*/0xCD, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28995 | GIR_MakeTempReg, /*TempRegID*//* 590(*/0xCE, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28996 | GIR_MakeTempReg, /*TempRegID*//* 591(*/0xCF, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 28997 | GIR_MakeTempReg, /*TempRegID*//* 592(*/0xD0, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28998 | GIR_MakeTempReg, /*TempRegID*//* 593(*/0xD1, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 28999 | GIR_MakeTempReg, /*TempRegID*//* 594(*/0xD2, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29000 | GIR_MakeTempReg, /*TempRegID*//* 595(*/0xD3, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29001 | GIR_MakeTempReg, /*TempRegID*//* 596(*/0xD4, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29002 | GIR_MakeTempReg, /*TempRegID*//* 597(*/0xD5, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29003 | GIR_MakeTempReg, /*TempRegID*//* 598(*/0xD6, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29004 | GIR_MakeTempReg, /*TempRegID*//* 599(*/0xD7, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29005 | GIR_MakeTempReg, /*TempRegID*//* 600(*/0xD8, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29006 | GIR_MakeTempReg, /*TempRegID*//* 601(*/0xD9, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29007 | GIR_MakeTempReg, /*TempRegID*//* 602(*/0xDA, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29008 | GIR_MakeTempReg, /*TempRegID*//* 603(*/0xDB, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29009 | GIR_MakeTempReg, /*TempRegID*//* 604(*/0xDC, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29010 | GIR_MakeTempReg, /*TempRegID*//* 605(*/0xDD, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29011 | GIR_MakeTempReg, /*TempRegID*//* 606(*/0xDE, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29012 | GIR_MakeTempReg, /*TempRegID*//* 607(*/0xDF, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29013 | GIR_MakeTempReg, /*TempRegID*//* 608(*/0xE0, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29014 | GIR_MakeTempReg, /*TempRegID*//* 609(*/0xE1, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29015 | GIR_MakeTempReg, /*TempRegID*//* 610(*/0xE2, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29016 | GIR_MakeTempReg, /*TempRegID*//* 611(*/0xE3, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29017 | GIR_MakeTempReg, /*TempRegID*//* 612(*/0xE4, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29018 | GIR_MakeTempReg, /*TempRegID*//* 613(*/0xE5, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29019 | GIR_MakeTempReg, /*TempRegID*//* 614(*/0xE6, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29020 | GIR_MakeTempReg, /*TempRegID*//* 615(*/0xE7, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29021 | GIR_MakeTempReg, /*TempRegID*//* 616(*/0xE8, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29022 | GIR_MakeTempReg, /*TempRegID*//* 617(*/0xE9, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29023 | GIR_MakeTempReg, /*TempRegID*//* 618(*/0xEA, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29024 | GIR_MakeTempReg, /*TempRegID*//* 619(*/0xEB, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29025 | GIR_MakeTempReg, /*TempRegID*//* 620(*/0xEC, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29026 | GIR_MakeTempReg, /*TempRegID*//* 621(*/0xED, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29027 | GIR_MakeTempReg, /*TempRegID*//* 622(*/0xEE, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29028 | GIR_MakeTempReg, /*TempRegID*//* 623(*/0xEF, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29029 | GIR_MakeTempReg, /*TempRegID*//* 624(*/0xF0, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29030 | GIR_MakeTempReg, /*TempRegID*//* 625(*/0xF1, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29031 | GIR_MakeTempReg, /*TempRegID*//* 626(*/0xF2, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29032 | GIR_MakeTempReg, /*TempRegID*//* 627(*/0xF3, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29033 | GIR_MakeTempReg, /*TempRegID*//* 628(*/0xF4, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29034 | GIR_MakeTempReg, /*TempRegID*//* 629(*/0xF5, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29035 | GIR_MakeTempReg, /*TempRegID*//* 630(*/0xF6, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29036 | GIR_MakeTempReg, /*TempRegID*//* 631(*/0xF7, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29037 | GIR_MakeTempReg, /*TempRegID*//* 632(*/0xF8, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29038 | GIR_MakeTempReg, /*TempRegID*//* 633(*/0xF9, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29039 | GIR_MakeTempReg, /*TempRegID*//* 634(*/0xFA, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29040 | GIR_MakeTempReg, /*TempRegID*//* 635(*/0xFB, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29041 | GIR_MakeTempReg, /*TempRegID*//* 636(*/0xFC, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29042 | GIR_MakeTempReg, /*TempRegID*//* 637(*/0xFD, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29043 | GIR_MakeTempReg, /*TempRegID*//* 638(*/0xFE, 0x04/*)*/, /*TypeID*/GILLT_s64, |
| 29044 | GIR_MakeTempReg, /*TempRegID*//* 639(*/0xFF, 0x04/*)*/, /*TypeID*/GILLT_s32, |
| 29045 | GIR_MakeTempReg, /*TempRegID*//* 640(*/0x80, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29046 | GIR_MakeTempReg, /*TempRegID*//* 641(*/0x81, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29047 | GIR_MakeTempReg, /*TempRegID*//* 642(*/0x82, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29048 | GIR_MakeTempReg, /*TempRegID*//* 643(*/0x83, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29049 | GIR_MakeTempReg, /*TempRegID*//* 644(*/0x84, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29050 | GIR_MakeTempReg, /*TempRegID*//* 645(*/0x85, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29051 | GIR_MakeTempReg, /*TempRegID*//* 646(*/0x86, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29052 | GIR_MakeTempReg, /*TempRegID*//* 647(*/0x87, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29053 | GIR_MakeTempReg, /*TempRegID*//* 648(*/0x88, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29054 | GIR_MakeTempReg, /*TempRegID*//* 649(*/0x89, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29055 | GIR_MakeTempReg, /*TempRegID*//* 650(*/0x8A, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29056 | GIR_MakeTempReg, /*TempRegID*//* 651(*/0x8B, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29057 | GIR_MakeTempReg, /*TempRegID*//* 652(*/0x8C, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29058 | GIR_MakeTempReg, /*TempRegID*//* 653(*/0x8D, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29059 | GIR_MakeTempReg, /*TempRegID*//* 654(*/0x8E, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29060 | GIR_MakeTempReg, /*TempRegID*//* 655(*/0x8F, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29061 | GIR_MakeTempReg, /*TempRegID*//* 656(*/0x90, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29062 | GIR_MakeTempReg, /*TempRegID*//* 657(*/0x91, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29063 | GIR_MakeTempReg, /*TempRegID*//* 658(*/0x92, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29064 | GIR_MakeTempReg, /*TempRegID*//* 659(*/0x93, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29065 | GIR_MakeTempReg, /*TempRegID*//* 660(*/0x94, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29066 | GIR_MakeTempReg, /*TempRegID*//* 661(*/0x95, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29067 | GIR_MakeTempReg, /*TempRegID*//* 662(*/0x96, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29068 | GIR_MakeTempReg, /*TempRegID*//* 663(*/0x97, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29069 | GIR_MakeTempReg, /*TempRegID*//* 664(*/0x98, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29070 | GIR_MakeTempReg, /*TempRegID*//* 665(*/0x99, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29071 | GIR_MakeTempReg, /*TempRegID*//* 666(*/0x9A, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29072 | GIR_MakeTempReg, /*TempRegID*//* 667(*/0x9B, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29073 | GIR_MakeTempReg, /*TempRegID*//* 668(*/0x9C, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29074 | GIR_MakeTempReg, /*TempRegID*//* 669(*/0x9D, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29075 | GIR_MakeTempReg, /*TempRegID*//* 670(*/0x9E, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29076 | GIR_MakeTempReg, /*TempRegID*//* 671(*/0x9F, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29077 | GIR_MakeTempReg, /*TempRegID*//* 672(*/0xA0, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29078 | GIR_MakeTempReg, /*TempRegID*//* 673(*/0xA1, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29079 | GIR_MakeTempReg, /*TempRegID*//* 674(*/0xA2, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29080 | GIR_MakeTempReg, /*TempRegID*//* 675(*/0xA3, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29081 | GIR_MakeTempReg, /*TempRegID*//* 676(*/0xA4, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29082 | GIR_MakeTempReg, /*TempRegID*//* 677(*/0xA5, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29083 | GIR_MakeTempReg, /*TempRegID*//* 678(*/0xA6, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29084 | GIR_MakeTempReg, /*TempRegID*//* 679(*/0xA7, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29085 | GIR_MakeTempReg, /*TempRegID*//* 680(*/0xA8, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29086 | GIR_MakeTempReg, /*TempRegID*//* 681(*/0xA9, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29087 | GIR_MakeTempReg, /*TempRegID*//* 682(*/0xAA, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29088 | GIR_BuildMI, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29089 | GIR_AddTempRegister, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, /*TempRegID*//* 682(*/0xAA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29090 | GIR_AddImm, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29091 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 683(*/0xAB, 0x05/*)*/, |
| 29092 | GIR_BuildMI, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29093 | GIR_AddTempRegister, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*TempRegID*//* 681(*/0xA9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29094 | GIR_AddSimpleTempRegister, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*TempRegID*//* 682(*/0xAA, 0x05/*)*/, |
| 29095 | GIR_AddImm, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29096 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 682(*/0xAA, 0x05/*)*/, |
| 29097 | GIR_BuildMI, /*InsnID*//* 681(*/0xA9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29098 | GIR_AddTempRegister, /*InsnID*//* 681(*/0xA9, 0x05/*)*/, /*TempRegID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29099 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 681(*/0xA9, 0x05/*)*/, |
| 29100 | GIR_BuildMI, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29101 | GIR_AddTempRegister, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegID*//* 679(*/0xA7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29102 | GIR_AddSimpleTempRegister, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegID*//* 680(*/0xA8, 0x05/*)*/, |
| 29103 | GIR_AddSimpleTempRegister, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*TempRegID*//* 681(*/0xA9, 0x05/*)*/, |
| 29104 | GIR_AddImm8, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Imm*/1, |
| 29105 | GIR_ConstrainOperandRC, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29106 | GIR_ConstrainOperandRC, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29107 | GIR_ConstrainOperandRC, /*InsnID*//* 680(*/0xA8, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29108 | GIR_BuildMI, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29109 | GIR_AddTempRegister, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*TempRegID*//* 678(*/0xA6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29110 | GIR_AddSimpleTempRegister, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*TempRegID*//* 679(*/0xA7, 0x05/*)*/, |
| 29111 | GIR_AddImm8, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*Imm*/32, |
| 29112 | GIR_AddImm8, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, /*Imm*/31, |
| 29113 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 679(*/0xA7, 0x05/*)*/, |
| 29114 | GIR_BuildMI, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29115 | GIR_AddTempRegister, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*TempRegID*//* 677(*/0xA5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29116 | GIR_AddSimpleTempRegister, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*TempRegID*//* 678(*/0xA6, 0x05/*)*/, |
| 29117 | GIR_AddImm, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29118 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 678(*/0xA6, 0x05/*)*/, |
| 29119 | GIR_BuildMI, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29120 | GIR_AddTempRegister, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*TempRegID*//* 676(*/0xA4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29121 | GIR_AddSimpleTempRegister, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*TempRegID*//* 677(*/0xA5, 0x05/*)*/, |
| 29122 | GIR_AddImm, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29123 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 677(*/0xA5, 0x05/*)*/, |
| 29124 | GIR_BuildMI, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29125 | GIR_AddTempRegister, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, /*TempRegID*//* 675(*/0xA3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29126 | GIR_AddImm, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29127 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 676(*/0xA4, 0x05/*)*/, |
| 29128 | GIR_BuildMI, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29129 | GIR_AddTempRegister, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*TempRegID*//* 674(*/0xA2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29130 | GIR_AddSimpleTempRegister, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*TempRegID*//* 675(*/0xA3, 0x05/*)*/, |
| 29131 | GIR_AddImm, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29132 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 675(*/0xA3, 0x05/*)*/, |
| 29133 | GIR_BuildMI, /*InsnID*//* 674(*/0xA2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29134 | GIR_AddTempRegister, /*InsnID*//* 674(*/0xA2, 0x05/*)*/, /*TempRegID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29135 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 674(*/0xA2, 0x05/*)*/, |
| 29136 | GIR_BuildMI, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29137 | GIR_AddTempRegister, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegID*//* 672(*/0xA0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29138 | GIR_AddSimpleTempRegister, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegID*//* 673(*/0xA1, 0x05/*)*/, |
| 29139 | GIR_AddSimpleTempRegister, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*TempRegID*//* 674(*/0xA2, 0x05/*)*/, |
| 29140 | GIR_AddImm8, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Imm*/1, |
| 29141 | GIR_ConstrainOperandRC, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29142 | GIR_ConstrainOperandRC, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29143 | GIR_ConstrainOperandRC, /*InsnID*//* 673(*/0xA1, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29144 | GIR_BuildMI, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29145 | GIR_AddTempRegister, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*TempRegID*//* 671(*/0x9F, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29146 | GIR_AddSimpleTempRegister, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*TempRegID*//* 672(*/0xA0, 0x05/*)*/, |
| 29147 | GIR_AddImm8, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*Imm*/32, |
| 29148 | GIR_AddImm8, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, /*Imm*/31, |
| 29149 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 672(*/0xA0, 0x05/*)*/, |
| 29150 | GIR_BuildMI, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29151 | GIR_AddTempRegister, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*TempRegID*//* 670(*/0x9E, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29152 | GIR_AddSimpleTempRegister, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*TempRegID*//* 671(*/0x9F, 0x05/*)*/, |
| 29153 | GIR_AddImm, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29154 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 671(*/0x9F, 0x05/*)*/, |
| 29155 | GIR_BuildMI, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29156 | GIR_AddTempRegister, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*TempRegID*//* 669(*/0x9D, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29157 | GIR_AddSimpleTempRegister, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*TempRegID*//* 670(*/0x9E, 0x05/*)*/, |
| 29158 | GIR_AddImm, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29159 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 670(*/0x9E, 0x05/*)*/, |
| 29160 | GIR_BuildMI, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29161 | GIR_AddTempRegister, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, /*TempRegID*//* 668(*/0x9C, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29162 | GIR_AddImm, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29163 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 669(*/0x9D, 0x05/*)*/, |
| 29164 | GIR_BuildMI, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29165 | GIR_AddTempRegister, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*TempRegID*//* 667(*/0x9B, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29166 | GIR_AddSimpleTempRegister, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*TempRegID*//* 668(*/0x9C, 0x05/*)*/, |
| 29167 | GIR_AddImm, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29168 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 668(*/0x9C, 0x05/*)*/, |
| 29169 | GIR_BuildMI, /*InsnID*//* 667(*/0x9B, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29170 | GIR_AddTempRegister, /*InsnID*//* 667(*/0x9B, 0x05/*)*/, /*TempRegID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29171 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 667(*/0x9B, 0x05/*)*/, |
| 29172 | GIR_BuildMI, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29173 | GIR_AddTempRegister, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegID*//* 665(*/0x99, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29174 | GIR_AddSimpleTempRegister, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegID*//* 666(*/0x9A, 0x05/*)*/, |
| 29175 | GIR_AddSimpleTempRegister, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*TempRegID*//* 667(*/0x9B, 0x05/*)*/, |
| 29176 | GIR_AddImm8, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Imm*/1, |
| 29177 | GIR_ConstrainOperandRC, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29178 | GIR_ConstrainOperandRC, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29179 | GIR_ConstrainOperandRC, /*InsnID*//* 666(*/0x9A, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29180 | GIR_BuildMI, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29181 | GIR_AddTempRegister, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*TempRegID*//* 664(*/0x98, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29182 | GIR_AddSimpleTempRegister, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*TempRegID*//* 665(*/0x99, 0x05/*)*/, |
| 29183 | GIR_AddImm8, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*Imm*/32, |
| 29184 | GIR_AddImm8, /*InsnID*//* 665(*/0x99, 0x05/*)*/, /*Imm*/31, |
| 29185 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 665(*/0x99, 0x05/*)*/, |
| 29186 | GIR_BuildMI, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29187 | GIR_AddTempRegister, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*TempRegID*//* 663(*/0x97, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29188 | GIR_AddSimpleTempRegister, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*TempRegID*//* 664(*/0x98, 0x05/*)*/, |
| 29189 | GIR_AddImm, /*InsnID*//* 664(*/0x98, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29190 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 664(*/0x98, 0x05/*)*/, |
| 29191 | GIR_BuildMI, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29192 | GIR_AddTempRegister, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*TempRegID*//* 662(*/0x96, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29193 | GIR_AddSimpleTempRegister, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*TempRegID*//* 663(*/0x97, 0x05/*)*/, |
| 29194 | GIR_AddImm, /*InsnID*//* 663(*/0x97, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29195 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 663(*/0x97, 0x05/*)*/, |
| 29196 | GIR_BuildMI, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29197 | GIR_AddTempRegister, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*TempRegID*//* 661(*/0x95, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29198 | GIR_Copy, /*NewInsnID*//* 662(*/0x96, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29199 | GIR_AddImm8, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*Imm*/1, |
| 29200 | GIR_AddImm8, /*InsnID*//* 662(*/0x96, 0x05/*)*/, /*Imm*/62, |
| 29201 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 662(*/0x96, 0x05/*)*/, |
| 29202 | GIR_BuildMI, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29203 | GIR_AddTempRegister, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*TempRegID*//* 660(*/0x94, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29204 | GIR_AddSimpleTempRegister, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*TempRegID*//* 661(*/0x95, 0x05/*)*/, |
| 29205 | GIR_AddSimpleTempRegister, /*InsnID*//* 661(*/0x95, 0x05/*)*/, /*TempRegID*//* 662(*/0x96, 0x05/*)*/, |
| 29206 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 661(*/0x95, 0x05/*)*/, |
| 29207 | GIR_BuildMI, /*InsnID*//* 660(*/0x94, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29208 | GIR_AddTempRegister, /*InsnID*//* 660(*/0x94, 0x05/*)*/, /*TempRegID*//* 659(*/0x93, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29209 | GIR_AddImm, /*InsnID*//* 660(*/0x94, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29210 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 660(*/0x94, 0x05/*)*/, |
| 29211 | GIR_BuildMI, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29212 | GIR_AddTempRegister, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*TempRegID*//* 658(*/0x92, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29213 | GIR_AddSimpleTempRegister, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*TempRegID*//* 659(*/0x93, 0x05/*)*/, |
| 29214 | GIR_AddImm, /*InsnID*//* 659(*/0x93, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29215 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 659(*/0x93, 0x05/*)*/, |
| 29216 | GIR_BuildMI, /*InsnID*//* 658(*/0x92, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29217 | GIR_AddTempRegister, /*InsnID*//* 658(*/0x92, 0x05/*)*/, /*TempRegID*//* 657(*/0x91, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29218 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 658(*/0x92, 0x05/*)*/, |
| 29219 | GIR_BuildMI, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29220 | GIR_AddTempRegister, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*TempRegID*//* 656(*/0x90, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29221 | GIR_AddSimpleTempRegister, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*TempRegID*//* 657(*/0x91, 0x05/*)*/, |
| 29222 | GIR_AddSimpleTempRegister, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*TempRegID*//* 658(*/0x92, 0x05/*)*/, |
| 29223 | GIR_AddImm8, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Imm*/1, |
| 29224 | GIR_ConstrainOperandRC, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29225 | GIR_ConstrainOperandRC, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29226 | GIR_ConstrainOperandRC, /*InsnID*//* 657(*/0x91, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29227 | GIR_BuildMI, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29228 | GIR_AddTempRegister, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*TempRegID*//* 655(*/0x8F, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29229 | GIR_AddSimpleTempRegister, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*TempRegID*//* 656(*/0x90, 0x05/*)*/, |
| 29230 | GIR_AddImm8, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*Imm*/32, |
| 29231 | GIR_AddImm8, /*InsnID*//* 656(*/0x90, 0x05/*)*/, /*Imm*/31, |
| 29232 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 656(*/0x90, 0x05/*)*/, |
| 29233 | GIR_BuildMI, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29234 | GIR_AddTempRegister, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*TempRegID*//* 654(*/0x8E, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29235 | GIR_AddSimpleTempRegister, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*TempRegID*//* 655(*/0x8F, 0x05/*)*/, |
| 29236 | GIR_AddImm, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29237 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 655(*/0x8F, 0x05/*)*/, |
| 29238 | GIR_BuildMI, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29239 | GIR_AddTempRegister, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*TempRegID*//* 653(*/0x8D, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29240 | GIR_AddSimpleTempRegister, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*TempRegID*//* 654(*/0x8E, 0x05/*)*/, |
| 29241 | GIR_AddImm, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29242 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 654(*/0x8E, 0x05/*)*/, |
| 29243 | GIR_BuildMI, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29244 | GIR_AddTempRegister, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*TempRegID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29245 | GIR_Copy, /*NewInsnID*//* 653(*/0x8D, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29246 | GIR_AddImm8, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*Imm*/63, |
| 29247 | GIR_AddImm8, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, /*Imm*/1, |
| 29248 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 653(*/0x8D, 0x05/*)*/, |
| 29249 | GIR_BuildMI, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29250 | GIR_AddTempRegister, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29251 | GIR_AddSimpleTempRegister, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegID*//* 652(*/0x8C, 0x05/*)*/, |
| 29252 | GIR_AddSimpleTempRegister, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, /*TempRegID*//* 653(*/0x8D, 0x05/*)*/, |
| 29253 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 652(*/0x8C, 0x05/*)*/, |
| 29254 | GIR_BuildMI, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29255 | GIR_AddTempRegister, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegID*//* 650(*/0x8A, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29256 | GIR_AddSimpleTempRegister, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegID*//* 651(*/0x8B, 0x05/*)*/, |
| 29257 | GIR_AddSimpleTempRegister, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, /*TempRegID*//* 660(*/0x94, 0x05/*)*/, |
| 29258 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 651(*/0x8B, 0x05/*)*/, |
| 29259 | GIR_BuildMI, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29260 | GIR_AddTempRegister, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*TempRegID*//* 649(*/0x89, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29261 | GIR_AddSimpleTempRegister, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*TempRegID*//* 650(*/0x8A, 0x05/*)*/, |
| 29262 | GIR_AddImm8, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*Imm*/2, |
| 29263 | GIR_AddImm8, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, /*Imm*/61, |
| 29264 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 650(*/0x8A, 0x05/*)*/, |
| 29265 | GIR_BuildMI, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29266 | GIR_AddTempRegister, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*TempRegID*//* 648(*/0x88, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29267 | GIR_AddSimpleTempRegister, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*TempRegID*//* 649(*/0x89, 0x05/*)*/, |
| 29268 | GIR_AddSimpleTempRegister, /*InsnID*//* 649(*/0x89, 0x05/*)*/, /*TempRegID*//* 669(*/0x9D, 0x05/*)*/, |
| 29269 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 649(*/0x89, 0x05/*)*/, |
| 29270 | GIR_BuildMI, /*InsnID*//* 648(*/0x88, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29271 | GIR_AddTempRegister, /*InsnID*//* 648(*/0x88, 0x05/*)*/, /*TempRegID*//* 647(*/0x87, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29272 | GIR_AddImm, /*InsnID*//* 648(*/0x88, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29273 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 648(*/0x88, 0x05/*)*/, |
| 29274 | GIR_BuildMI, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29275 | GIR_AddTempRegister, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*TempRegID*//* 646(*/0x86, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29276 | GIR_AddSimpleTempRegister, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*TempRegID*//* 647(*/0x87, 0x05/*)*/, |
| 29277 | GIR_AddImm, /*InsnID*//* 647(*/0x87, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29278 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 647(*/0x87, 0x05/*)*/, |
| 29279 | GIR_BuildMI, /*InsnID*//* 646(*/0x86, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29280 | GIR_AddTempRegister, /*InsnID*//* 646(*/0x86, 0x05/*)*/, /*TempRegID*//* 645(*/0x85, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29281 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 646(*/0x86, 0x05/*)*/, |
| 29282 | GIR_BuildMI, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29283 | GIR_AddTempRegister, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*TempRegID*//* 644(*/0x84, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29284 | GIR_AddSimpleTempRegister, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*TempRegID*//* 645(*/0x85, 0x05/*)*/, |
| 29285 | GIR_AddSimpleTempRegister, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*TempRegID*//* 646(*/0x86, 0x05/*)*/, |
| 29286 | GIR_AddImm8, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Imm*/1, |
| 29287 | GIR_ConstrainOperandRC, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29288 | GIR_ConstrainOperandRC, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29289 | GIR_ConstrainOperandRC, /*InsnID*//* 645(*/0x85, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29290 | GIR_BuildMI, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29291 | GIR_AddTempRegister, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*TempRegID*//* 643(*/0x83, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29292 | GIR_AddSimpleTempRegister, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*TempRegID*//* 644(*/0x84, 0x05/*)*/, |
| 29293 | GIR_AddImm8, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*Imm*/32, |
| 29294 | GIR_AddImm8, /*InsnID*//* 644(*/0x84, 0x05/*)*/, /*Imm*/31, |
| 29295 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 644(*/0x84, 0x05/*)*/, |
| 29296 | GIR_BuildMI, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29297 | GIR_AddTempRegister, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*TempRegID*//* 642(*/0x82, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29298 | GIR_AddSimpleTempRegister, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*TempRegID*//* 643(*/0x83, 0x05/*)*/, |
| 29299 | GIR_AddImm, /*InsnID*//* 643(*/0x83, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29300 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 643(*/0x83, 0x05/*)*/, |
| 29301 | GIR_BuildMI, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29302 | GIR_AddTempRegister, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*TempRegID*//* 641(*/0x81, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29303 | GIR_AddSimpleTempRegister, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*TempRegID*//* 642(*/0x82, 0x05/*)*/, |
| 29304 | GIR_AddImm, /*InsnID*//* 642(*/0x82, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29305 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 642(*/0x82, 0x05/*)*/, |
| 29306 | GIR_BuildMI, /*InsnID*//* 641(*/0x81, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29307 | GIR_AddTempRegister, /*InsnID*//* 641(*/0x81, 0x05/*)*/, /*TempRegID*//* 640(*/0x80, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29308 | GIR_AddImm, /*InsnID*//* 641(*/0x81, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29309 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 641(*/0x81, 0x05/*)*/, |
| 29310 | GIR_BuildMI, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29311 | GIR_AddTempRegister, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*TempRegID*//* 639(*/0xFF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29312 | GIR_AddSimpleTempRegister, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*TempRegID*//* 640(*/0x80, 0x05/*)*/, |
| 29313 | GIR_AddImm, /*InsnID*//* 640(*/0x80, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29314 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 640(*/0x80, 0x05/*)*/, |
| 29315 | GIR_BuildMI, /*InsnID*//* 639(*/0xFF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29316 | GIR_AddTempRegister, /*InsnID*//* 639(*/0xFF, 0x04/*)*/, /*TempRegID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29317 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 639(*/0xFF, 0x04/*)*/, |
| 29318 | GIR_BuildMI, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29319 | GIR_AddTempRegister, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegID*//* 637(*/0xFD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29320 | GIR_AddSimpleTempRegister, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegID*//* 638(*/0xFE, 0x04/*)*/, |
| 29321 | GIR_AddSimpleTempRegister, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*TempRegID*//* 639(*/0xFF, 0x04/*)*/, |
| 29322 | GIR_AddImm8, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Imm*/1, |
| 29323 | GIR_ConstrainOperandRC, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29324 | GIR_ConstrainOperandRC, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29325 | GIR_ConstrainOperandRC, /*InsnID*//* 638(*/0xFE, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29326 | GIR_BuildMI, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29327 | GIR_AddTempRegister, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*TempRegID*//* 636(*/0xFC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29328 | GIR_AddSimpleTempRegister, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*TempRegID*//* 637(*/0xFD, 0x04/*)*/, |
| 29329 | GIR_AddImm8, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*Imm*/32, |
| 29330 | GIR_AddImm8, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, /*Imm*/31, |
| 29331 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 637(*/0xFD, 0x04/*)*/, |
| 29332 | GIR_BuildMI, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29333 | GIR_AddTempRegister, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*TempRegID*//* 635(*/0xFB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29334 | GIR_AddSimpleTempRegister, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*TempRegID*//* 636(*/0xFC, 0x04/*)*/, |
| 29335 | GIR_AddImm, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29336 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 636(*/0xFC, 0x04/*)*/, |
| 29337 | GIR_BuildMI, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29338 | GIR_AddTempRegister, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*TempRegID*//* 634(*/0xFA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29339 | GIR_AddSimpleTempRegister, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*TempRegID*//* 635(*/0xFB, 0x04/*)*/, |
| 29340 | GIR_AddImm, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29341 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 635(*/0xFB, 0x04/*)*/, |
| 29342 | GIR_BuildMI, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29343 | GIR_AddTempRegister, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*TempRegID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29344 | GIR_Copy, /*NewInsnID*//* 634(*/0xFA, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29345 | GIR_AddImm8, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*Imm*/1, |
| 29346 | GIR_AddImm8, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, /*Imm*/62, |
| 29347 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 634(*/0xFA, 0x04/*)*/, |
| 29348 | GIR_BuildMI, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29349 | GIR_AddTempRegister, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegID*//* 632(*/0xF8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29350 | GIR_AddSimpleTempRegister, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegID*//* 633(*/0xF9, 0x04/*)*/, |
| 29351 | GIR_AddSimpleTempRegister, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, /*TempRegID*//* 634(*/0xFA, 0x04/*)*/, |
| 29352 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 633(*/0xF9, 0x04/*)*/, |
| 29353 | GIR_BuildMI, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29354 | GIR_AddTempRegister, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, /*TempRegID*//* 631(*/0xF7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29355 | GIR_AddImm, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29356 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 632(*/0xF8, 0x04/*)*/, |
| 29357 | GIR_BuildMI, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29358 | GIR_AddTempRegister, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*TempRegID*//* 630(*/0xF6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29359 | GIR_AddSimpleTempRegister, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*TempRegID*//* 631(*/0xF7, 0x04/*)*/, |
| 29360 | GIR_AddImm, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29361 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 631(*/0xF7, 0x04/*)*/, |
| 29362 | GIR_BuildMI, /*InsnID*//* 630(*/0xF6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29363 | GIR_AddTempRegister, /*InsnID*//* 630(*/0xF6, 0x04/*)*/, /*TempRegID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29364 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 630(*/0xF6, 0x04/*)*/, |
| 29365 | GIR_BuildMI, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29366 | GIR_AddTempRegister, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegID*//* 628(*/0xF4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29367 | GIR_AddSimpleTempRegister, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegID*//* 629(*/0xF5, 0x04/*)*/, |
| 29368 | GIR_AddSimpleTempRegister, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*TempRegID*//* 630(*/0xF6, 0x04/*)*/, |
| 29369 | GIR_AddImm8, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Imm*/1, |
| 29370 | GIR_ConstrainOperandRC, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29371 | GIR_ConstrainOperandRC, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29372 | GIR_ConstrainOperandRC, /*InsnID*//* 629(*/0xF5, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29373 | GIR_BuildMI, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29374 | GIR_AddTempRegister, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*TempRegID*//* 627(*/0xF3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29375 | GIR_AddSimpleTempRegister, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*TempRegID*//* 628(*/0xF4, 0x04/*)*/, |
| 29376 | GIR_AddImm8, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*Imm*/32, |
| 29377 | GIR_AddImm8, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, /*Imm*/31, |
| 29378 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 628(*/0xF4, 0x04/*)*/, |
| 29379 | GIR_BuildMI, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29380 | GIR_AddTempRegister, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*TempRegID*//* 626(*/0xF2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29381 | GIR_AddSimpleTempRegister, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*TempRegID*//* 627(*/0xF3, 0x04/*)*/, |
| 29382 | GIR_AddImm, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29383 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 627(*/0xF3, 0x04/*)*/, |
| 29384 | GIR_BuildMI, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29385 | GIR_AddTempRegister, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*TempRegID*//* 625(*/0xF1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29386 | GIR_AddSimpleTempRegister, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*TempRegID*//* 626(*/0xF2, 0x04/*)*/, |
| 29387 | GIR_AddImm, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29388 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 626(*/0xF2, 0x04/*)*/, |
| 29389 | GIR_BuildMI, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29390 | GIR_AddTempRegister, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*TempRegID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29391 | GIR_Copy, /*NewInsnID*//* 625(*/0xF1, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29392 | GIR_AddImm8, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*Imm*/63, |
| 29393 | GIR_AddImm8, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, /*Imm*/1, |
| 29394 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 625(*/0xF1, 0x04/*)*/, |
| 29395 | GIR_BuildMI, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29396 | GIR_AddTempRegister, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29397 | GIR_AddSimpleTempRegister, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegID*//* 624(*/0xF0, 0x04/*)*/, |
| 29398 | GIR_AddSimpleTempRegister, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, /*TempRegID*//* 625(*/0xF1, 0x04/*)*/, |
| 29399 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 624(*/0xF0, 0x04/*)*/, |
| 29400 | GIR_BuildMI, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29401 | GIR_AddTempRegister, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegID*//* 622(*/0xEE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29402 | GIR_AddSimpleTempRegister, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegID*//* 623(*/0xEF, 0x04/*)*/, |
| 29403 | GIR_AddSimpleTempRegister, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, /*TempRegID*//* 632(*/0xF8, 0x04/*)*/, |
| 29404 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 623(*/0xEF, 0x04/*)*/, |
| 29405 | GIR_BuildMI, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29406 | GIR_AddTempRegister, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*TempRegID*//* 621(*/0xED, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29407 | GIR_AddSimpleTempRegister, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*TempRegID*//* 622(*/0xEE, 0x04/*)*/, |
| 29408 | GIR_AddImm8, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*Imm*/62, |
| 29409 | GIR_AddImm8, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, /*Imm*/2, |
| 29410 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 622(*/0xEE, 0x04/*)*/, |
| 29411 | GIR_BuildMI, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29412 | GIR_AddTempRegister, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*TempRegID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29413 | GIR_AddSimpleTempRegister, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*TempRegID*//* 621(*/0xED, 0x04/*)*/, |
| 29414 | GIR_AddSimpleTempRegister, /*InsnID*//* 621(*/0xED, 0x04/*)*/, /*TempRegID*//* 641(*/0x81, 0x05/*)*/, |
| 29415 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 621(*/0xED, 0x04/*)*/, |
| 29416 | GIR_BuildMI, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29417 | GIR_AddTempRegister, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegID*//* 619(*/0xEB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29418 | GIR_AddSimpleTempRegister, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegID*//* 620(*/0xEC, 0x04/*)*/, |
| 29419 | GIR_AddSimpleTempRegister, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, /*TempRegID*//* 648(*/0x88, 0x05/*)*/, |
| 29420 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 620(*/0xEC, 0x04/*)*/, |
| 29421 | GIR_BuildMI, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29422 | GIR_AddTempRegister, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*TempRegID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29423 | GIR_AddSimpleTempRegister, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*TempRegID*//* 619(*/0xEB, 0x04/*)*/, |
| 29424 | GIR_AddImm8, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*Imm*/4, |
| 29425 | GIR_AddImm8, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, /*Imm*/59, |
| 29426 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 619(*/0xEB, 0x04/*)*/, |
| 29427 | GIR_BuildMI, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29428 | GIR_AddTempRegister, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegID*//* 617(*/0xE9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29429 | GIR_AddSimpleTempRegister, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegID*//* 618(*/0xEA, 0x04/*)*/, |
| 29430 | GIR_AddSimpleTempRegister, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, /*TempRegID*//* 676(*/0xA4, 0x05/*)*/, |
| 29431 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 618(*/0xEA, 0x04/*)*/, |
| 29432 | GIR_BuildMI, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29433 | GIR_AddTempRegister, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, /*TempRegID*//* 616(*/0xE8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29434 | GIR_AddImm, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 29435 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 617(*/0xE9, 0x04/*)*/, |
| 29436 | GIR_BuildMI, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29437 | GIR_AddTempRegister, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*TempRegID*//* 615(*/0xE7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29438 | GIR_AddSimpleTempRegister, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*TempRegID*//* 616(*/0xE8, 0x04/*)*/, |
| 29439 | GIR_AddImm, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 29440 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 616(*/0xE8, 0x04/*)*/, |
| 29441 | GIR_BuildMI, /*InsnID*//* 615(*/0xE7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29442 | GIR_AddTempRegister, /*InsnID*//* 615(*/0xE7, 0x04/*)*/, /*TempRegID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29443 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 615(*/0xE7, 0x04/*)*/, |
| 29444 | GIR_BuildMI, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29445 | GIR_AddTempRegister, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegID*//* 613(*/0xE5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29446 | GIR_AddSimpleTempRegister, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegID*//* 614(*/0xE6, 0x04/*)*/, |
| 29447 | GIR_AddSimpleTempRegister, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*TempRegID*//* 615(*/0xE7, 0x04/*)*/, |
| 29448 | GIR_AddImm8, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Imm*/1, |
| 29449 | GIR_ConstrainOperandRC, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29450 | GIR_ConstrainOperandRC, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29451 | GIR_ConstrainOperandRC, /*InsnID*//* 614(*/0xE6, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29452 | GIR_BuildMI, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29453 | GIR_AddTempRegister, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*TempRegID*//* 612(*/0xE4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29454 | GIR_AddSimpleTempRegister, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*TempRegID*//* 613(*/0xE5, 0x04/*)*/, |
| 29455 | GIR_AddImm8, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*Imm*/32, |
| 29456 | GIR_AddImm8, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, /*Imm*/31, |
| 29457 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 613(*/0xE5, 0x04/*)*/, |
| 29458 | GIR_BuildMI, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29459 | GIR_AddTempRegister, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*TempRegID*//* 611(*/0xE3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29460 | GIR_AddSimpleTempRegister, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*TempRegID*//* 612(*/0xE4, 0x04/*)*/, |
| 29461 | GIR_AddImm, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 29462 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 612(*/0xE4, 0x04/*)*/, |
| 29463 | GIR_BuildMI, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29464 | GIR_AddTempRegister, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*TempRegID*//* 610(*/0xE2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29465 | GIR_AddSimpleTempRegister, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*TempRegID*//* 611(*/0xE3, 0x04/*)*/, |
| 29466 | GIR_AddImm, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 29467 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 611(*/0xE3, 0x04/*)*/, |
| 29468 | GIR_BuildMI, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29469 | GIR_AddTempRegister, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, /*TempRegID*//* 609(*/0xE1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29470 | GIR_AddImm, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29471 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 610(*/0xE2, 0x04/*)*/, |
| 29472 | GIR_BuildMI, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29473 | GIR_AddTempRegister, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*TempRegID*//* 608(*/0xE0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29474 | GIR_AddSimpleTempRegister, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*TempRegID*//* 609(*/0xE1, 0x04/*)*/, |
| 29475 | GIR_AddImm, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29476 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 609(*/0xE1, 0x04/*)*/, |
| 29477 | GIR_BuildMI, /*InsnID*//* 608(*/0xE0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29478 | GIR_AddTempRegister, /*InsnID*//* 608(*/0xE0, 0x04/*)*/, /*TempRegID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29479 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 608(*/0xE0, 0x04/*)*/, |
| 29480 | GIR_BuildMI, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29481 | GIR_AddTempRegister, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegID*//* 606(*/0xDE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29482 | GIR_AddSimpleTempRegister, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegID*//* 607(*/0xDF, 0x04/*)*/, |
| 29483 | GIR_AddSimpleTempRegister, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*TempRegID*//* 608(*/0xE0, 0x04/*)*/, |
| 29484 | GIR_AddImm8, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Imm*/1, |
| 29485 | GIR_ConstrainOperandRC, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29486 | GIR_ConstrainOperandRC, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29487 | GIR_ConstrainOperandRC, /*InsnID*//* 607(*/0xDF, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29488 | GIR_BuildMI, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29489 | GIR_AddTempRegister, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*TempRegID*//* 605(*/0xDD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29490 | GIR_AddSimpleTempRegister, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*TempRegID*//* 606(*/0xDE, 0x04/*)*/, |
| 29491 | GIR_AddImm8, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*Imm*/32, |
| 29492 | GIR_AddImm8, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, /*Imm*/31, |
| 29493 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 606(*/0xDE, 0x04/*)*/, |
| 29494 | GIR_BuildMI, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29495 | GIR_AddTempRegister, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*TempRegID*//* 604(*/0xDC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29496 | GIR_AddSimpleTempRegister, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*TempRegID*//* 605(*/0xDD, 0x04/*)*/, |
| 29497 | GIR_AddImm, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29498 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 605(*/0xDD, 0x04/*)*/, |
| 29499 | GIR_BuildMI, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29500 | GIR_AddTempRegister, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*TempRegID*//* 603(*/0xDB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29501 | GIR_AddSimpleTempRegister, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*TempRegID*//* 604(*/0xDC, 0x04/*)*/, |
| 29502 | GIR_AddImm, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29503 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 604(*/0xDC, 0x04/*)*/, |
| 29504 | GIR_BuildMI, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29505 | GIR_AddTempRegister, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, /*TempRegID*//* 602(*/0xDA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29506 | GIR_AddImm, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29507 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 603(*/0xDB, 0x04/*)*/, |
| 29508 | GIR_BuildMI, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29509 | GIR_AddTempRegister, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*TempRegID*//* 601(*/0xD9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29510 | GIR_AddSimpleTempRegister, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*TempRegID*//* 602(*/0xDA, 0x04/*)*/, |
| 29511 | GIR_AddImm, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29512 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 602(*/0xDA, 0x04/*)*/, |
| 29513 | GIR_BuildMI, /*InsnID*//* 601(*/0xD9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29514 | GIR_AddTempRegister, /*InsnID*//* 601(*/0xD9, 0x04/*)*/, /*TempRegID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29515 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 601(*/0xD9, 0x04/*)*/, |
| 29516 | GIR_BuildMI, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29517 | GIR_AddTempRegister, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegID*//* 599(*/0xD7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29518 | GIR_AddSimpleTempRegister, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegID*//* 600(*/0xD8, 0x04/*)*/, |
| 29519 | GIR_AddSimpleTempRegister, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*TempRegID*//* 601(*/0xD9, 0x04/*)*/, |
| 29520 | GIR_AddImm8, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Imm*/1, |
| 29521 | GIR_ConstrainOperandRC, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29522 | GIR_ConstrainOperandRC, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29523 | GIR_ConstrainOperandRC, /*InsnID*//* 600(*/0xD8, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29524 | GIR_BuildMI, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29525 | GIR_AddTempRegister, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*TempRegID*//* 598(*/0xD6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29526 | GIR_AddSimpleTempRegister, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*TempRegID*//* 599(*/0xD7, 0x04/*)*/, |
| 29527 | GIR_AddImm8, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*Imm*/32, |
| 29528 | GIR_AddImm8, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, /*Imm*/31, |
| 29529 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 599(*/0xD7, 0x04/*)*/, |
| 29530 | GIR_BuildMI, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29531 | GIR_AddTempRegister, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*TempRegID*//* 597(*/0xD5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29532 | GIR_AddSimpleTempRegister, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*TempRegID*//* 598(*/0xD6, 0x04/*)*/, |
| 29533 | GIR_AddImm, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29534 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 598(*/0xD6, 0x04/*)*/, |
| 29535 | GIR_BuildMI, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29536 | GIR_AddTempRegister, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*TempRegID*//* 596(*/0xD4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29537 | GIR_AddSimpleTempRegister, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*TempRegID*//* 597(*/0xD5, 0x04/*)*/, |
| 29538 | GIR_AddImm, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29539 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 597(*/0xD5, 0x04/*)*/, |
| 29540 | GIR_BuildMI, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29541 | GIR_AddTempRegister, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*TempRegID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29542 | GIR_Copy, /*NewInsnID*//* 596(*/0xD4, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29543 | GIR_AddImm8, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*Imm*/1, |
| 29544 | GIR_AddImm8, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, /*Imm*/62, |
| 29545 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 596(*/0xD4, 0x04/*)*/, |
| 29546 | GIR_BuildMI, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29547 | GIR_AddTempRegister, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegID*//* 594(*/0xD2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29548 | GIR_AddSimpleTempRegister, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegID*//* 595(*/0xD3, 0x04/*)*/, |
| 29549 | GIR_AddSimpleTempRegister, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, /*TempRegID*//* 596(*/0xD4, 0x04/*)*/, |
| 29550 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 595(*/0xD3, 0x04/*)*/, |
| 29551 | GIR_BuildMI, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29552 | GIR_AddTempRegister, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, /*TempRegID*//* 593(*/0xD1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29553 | GIR_AddImm, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29554 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 594(*/0xD2, 0x04/*)*/, |
| 29555 | GIR_BuildMI, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29556 | GIR_AddTempRegister, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*TempRegID*//* 592(*/0xD0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29557 | GIR_AddSimpleTempRegister, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*TempRegID*//* 593(*/0xD1, 0x04/*)*/, |
| 29558 | GIR_AddImm, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29559 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 593(*/0xD1, 0x04/*)*/, |
| 29560 | GIR_BuildMI, /*InsnID*//* 592(*/0xD0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29561 | GIR_AddTempRegister, /*InsnID*//* 592(*/0xD0, 0x04/*)*/, /*TempRegID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29562 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 592(*/0xD0, 0x04/*)*/, |
| 29563 | GIR_BuildMI, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29564 | GIR_AddTempRegister, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegID*//* 590(*/0xCE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29565 | GIR_AddSimpleTempRegister, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegID*//* 591(*/0xCF, 0x04/*)*/, |
| 29566 | GIR_AddSimpleTempRegister, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*TempRegID*//* 592(*/0xD0, 0x04/*)*/, |
| 29567 | GIR_AddImm8, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Imm*/1, |
| 29568 | GIR_ConstrainOperandRC, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29569 | GIR_ConstrainOperandRC, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29570 | GIR_ConstrainOperandRC, /*InsnID*//* 591(*/0xCF, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29571 | GIR_BuildMI, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29572 | GIR_AddTempRegister, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*TempRegID*//* 589(*/0xCD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29573 | GIR_AddSimpleTempRegister, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*TempRegID*//* 590(*/0xCE, 0x04/*)*/, |
| 29574 | GIR_AddImm8, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*Imm*/32, |
| 29575 | GIR_AddImm8, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, /*Imm*/31, |
| 29576 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 590(*/0xCE, 0x04/*)*/, |
| 29577 | GIR_BuildMI, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29578 | GIR_AddTempRegister, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*TempRegID*//* 588(*/0xCC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29579 | GIR_AddSimpleTempRegister, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*TempRegID*//* 589(*/0xCD, 0x04/*)*/, |
| 29580 | GIR_AddImm, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29581 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 589(*/0xCD, 0x04/*)*/, |
| 29582 | GIR_BuildMI, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29583 | GIR_AddTempRegister, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*TempRegID*//* 587(*/0xCB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29584 | GIR_AddSimpleTempRegister, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*TempRegID*//* 588(*/0xCC, 0x04/*)*/, |
| 29585 | GIR_AddImm, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29586 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 588(*/0xCC, 0x04/*)*/, |
| 29587 | GIR_BuildMI, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29588 | GIR_AddTempRegister, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*TempRegID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29589 | GIR_Copy, /*NewInsnID*//* 587(*/0xCB, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29590 | GIR_AddImm8, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*Imm*/63, |
| 29591 | GIR_AddImm8, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, /*Imm*/1, |
| 29592 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 587(*/0xCB, 0x04/*)*/, |
| 29593 | GIR_BuildMI, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29594 | GIR_AddTempRegister, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29595 | GIR_AddSimpleTempRegister, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegID*//* 586(*/0xCA, 0x04/*)*/, |
| 29596 | GIR_AddSimpleTempRegister, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, /*TempRegID*//* 587(*/0xCB, 0x04/*)*/, |
| 29597 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 586(*/0xCA, 0x04/*)*/, |
| 29598 | GIR_BuildMI, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29599 | GIR_AddTempRegister, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegID*//* 584(*/0xC8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29600 | GIR_AddSimpleTempRegister, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegID*//* 585(*/0xC9, 0x04/*)*/, |
| 29601 | GIR_AddSimpleTempRegister, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, /*TempRegID*//* 594(*/0xD2, 0x04/*)*/, |
| 29602 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 585(*/0xC9, 0x04/*)*/, |
| 29603 | GIR_BuildMI, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29604 | GIR_AddTempRegister, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*TempRegID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29605 | GIR_AddSimpleTempRegister, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*TempRegID*//* 584(*/0xC8, 0x04/*)*/, |
| 29606 | GIR_AddImm8, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*Imm*/2, |
| 29607 | GIR_AddImm8, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, /*Imm*/61, |
| 29608 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 584(*/0xC8, 0x04/*)*/, |
| 29609 | GIR_BuildMI, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29610 | GIR_AddTempRegister, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegID*//* 582(*/0xC6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29611 | GIR_AddSimpleTempRegister, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegID*//* 583(*/0xC7, 0x04/*)*/, |
| 29612 | GIR_AddSimpleTempRegister, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, /*TempRegID*//* 603(*/0xDB, 0x04/*)*/, |
| 29613 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 583(*/0xC7, 0x04/*)*/, |
| 29614 | GIR_BuildMI, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29615 | GIR_AddTempRegister, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, /*TempRegID*//* 581(*/0xC5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29616 | GIR_AddImm, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29617 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 582(*/0xC6, 0x04/*)*/, |
| 29618 | GIR_BuildMI, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29619 | GIR_AddTempRegister, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*TempRegID*//* 580(*/0xC4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29620 | GIR_AddSimpleTempRegister, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*TempRegID*//* 581(*/0xC5, 0x04/*)*/, |
| 29621 | GIR_AddImm, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29622 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 581(*/0xC5, 0x04/*)*/, |
| 29623 | GIR_BuildMI, /*InsnID*//* 580(*/0xC4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29624 | GIR_AddTempRegister, /*InsnID*//* 580(*/0xC4, 0x04/*)*/, /*TempRegID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29625 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 580(*/0xC4, 0x04/*)*/, |
| 29626 | GIR_BuildMI, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29627 | GIR_AddTempRegister, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegID*//* 578(*/0xC2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29628 | GIR_AddSimpleTempRegister, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegID*//* 579(*/0xC3, 0x04/*)*/, |
| 29629 | GIR_AddSimpleTempRegister, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*TempRegID*//* 580(*/0xC4, 0x04/*)*/, |
| 29630 | GIR_AddImm8, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Imm*/1, |
| 29631 | GIR_ConstrainOperandRC, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29632 | GIR_ConstrainOperandRC, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29633 | GIR_ConstrainOperandRC, /*InsnID*//* 579(*/0xC3, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29634 | GIR_BuildMI, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29635 | GIR_AddTempRegister, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*TempRegID*//* 577(*/0xC1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29636 | GIR_AddSimpleTempRegister, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*TempRegID*//* 578(*/0xC2, 0x04/*)*/, |
| 29637 | GIR_AddImm8, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*Imm*/32, |
| 29638 | GIR_AddImm8, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, /*Imm*/31, |
| 29639 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 578(*/0xC2, 0x04/*)*/, |
| 29640 | GIR_BuildMI, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29641 | GIR_AddTempRegister, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*TempRegID*//* 576(*/0xC0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29642 | GIR_AddSimpleTempRegister, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*TempRegID*//* 577(*/0xC1, 0x04/*)*/, |
| 29643 | GIR_AddImm, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29644 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 577(*/0xC1, 0x04/*)*/, |
| 29645 | GIR_BuildMI, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29646 | GIR_AddTempRegister, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*TempRegID*//* 575(*/0xBF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29647 | GIR_AddSimpleTempRegister, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*TempRegID*//* 576(*/0xC0, 0x04/*)*/, |
| 29648 | GIR_AddImm, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 29649 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 576(*/0xC0, 0x04/*)*/, |
| 29650 | GIR_BuildMI, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29651 | GIR_AddTempRegister, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, /*TempRegID*//* 574(*/0xBE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29652 | GIR_AddImm, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29653 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 575(*/0xBF, 0x04/*)*/, |
| 29654 | GIR_BuildMI, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29655 | GIR_AddTempRegister, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*TempRegID*//* 573(*/0xBD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29656 | GIR_AddSimpleTempRegister, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*TempRegID*//* 574(*/0xBE, 0x04/*)*/, |
| 29657 | GIR_AddImm, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29658 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 574(*/0xBE, 0x04/*)*/, |
| 29659 | GIR_BuildMI, /*InsnID*//* 573(*/0xBD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29660 | GIR_AddTempRegister, /*InsnID*//* 573(*/0xBD, 0x04/*)*/, /*TempRegID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29661 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 573(*/0xBD, 0x04/*)*/, |
| 29662 | GIR_BuildMI, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29663 | GIR_AddTempRegister, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegID*//* 571(*/0xBB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29664 | GIR_AddSimpleTempRegister, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegID*//* 572(*/0xBC, 0x04/*)*/, |
| 29665 | GIR_AddSimpleTempRegister, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*TempRegID*//* 573(*/0xBD, 0x04/*)*/, |
| 29666 | GIR_AddImm8, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Imm*/1, |
| 29667 | GIR_ConstrainOperandRC, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29668 | GIR_ConstrainOperandRC, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29669 | GIR_ConstrainOperandRC, /*InsnID*//* 572(*/0xBC, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29670 | GIR_BuildMI, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29671 | GIR_AddTempRegister, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*TempRegID*//* 570(*/0xBA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29672 | GIR_AddSimpleTempRegister, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*TempRegID*//* 571(*/0xBB, 0x04/*)*/, |
| 29673 | GIR_AddImm8, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*Imm*/32, |
| 29674 | GIR_AddImm8, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, /*Imm*/31, |
| 29675 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 571(*/0xBB, 0x04/*)*/, |
| 29676 | GIR_BuildMI, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29677 | GIR_AddTempRegister, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*TempRegID*//* 569(*/0xB9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29678 | GIR_AddSimpleTempRegister, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*TempRegID*//* 570(*/0xBA, 0x04/*)*/, |
| 29679 | GIR_AddImm, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29680 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 570(*/0xBA, 0x04/*)*/, |
| 29681 | GIR_BuildMI, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29682 | GIR_AddTempRegister, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*TempRegID*//* 568(*/0xB8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29683 | GIR_AddSimpleTempRegister, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*TempRegID*//* 569(*/0xB9, 0x04/*)*/, |
| 29684 | GIR_AddImm, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29685 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 569(*/0xB9, 0x04/*)*/, |
| 29686 | GIR_BuildMI, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29687 | GIR_AddTempRegister, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*TempRegID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29688 | GIR_Copy, /*NewInsnID*//* 568(*/0xB8, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29689 | GIR_AddImm8, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*Imm*/1, |
| 29690 | GIR_AddImm8, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, /*Imm*/62, |
| 29691 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 568(*/0xB8, 0x04/*)*/, |
| 29692 | GIR_BuildMI, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29693 | GIR_AddTempRegister, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegID*//* 566(*/0xB6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29694 | GIR_AddSimpleTempRegister, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegID*//* 567(*/0xB7, 0x04/*)*/, |
| 29695 | GIR_AddSimpleTempRegister, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, /*TempRegID*//* 568(*/0xB8, 0x04/*)*/, |
| 29696 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 567(*/0xB7, 0x04/*)*/, |
| 29697 | GIR_BuildMI, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29698 | GIR_AddTempRegister, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, /*TempRegID*//* 565(*/0xB5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29699 | GIR_AddImm, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29700 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 566(*/0xB6, 0x04/*)*/, |
| 29701 | GIR_BuildMI, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29702 | GIR_AddTempRegister, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*TempRegID*//* 564(*/0xB4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29703 | GIR_AddSimpleTempRegister, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*TempRegID*//* 565(*/0xB5, 0x04/*)*/, |
| 29704 | GIR_AddImm, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29705 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 565(*/0xB5, 0x04/*)*/, |
| 29706 | GIR_BuildMI, /*InsnID*//* 564(*/0xB4, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29707 | GIR_AddTempRegister, /*InsnID*//* 564(*/0xB4, 0x04/*)*/, /*TempRegID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29708 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 564(*/0xB4, 0x04/*)*/, |
| 29709 | GIR_BuildMI, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29710 | GIR_AddTempRegister, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegID*//* 562(*/0xB2, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29711 | GIR_AddSimpleTempRegister, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegID*//* 563(*/0xB3, 0x04/*)*/, |
| 29712 | GIR_AddSimpleTempRegister, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*TempRegID*//* 564(*/0xB4, 0x04/*)*/, |
| 29713 | GIR_AddImm8, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Imm*/1, |
| 29714 | GIR_ConstrainOperandRC, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29715 | GIR_ConstrainOperandRC, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29716 | GIR_ConstrainOperandRC, /*InsnID*//* 563(*/0xB3, 0x04/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29717 | GIR_BuildMI, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29718 | GIR_AddTempRegister, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*TempRegID*//* 561(*/0xB1, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29719 | GIR_AddSimpleTempRegister, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*TempRegID*//* 562(*/0xB2, 0x04/*)*/, |
| 29720 | GIR_AddImm8, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*Imm*/32, |
| 29721 | GIR_AddImm8, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, /*Imm*/31, |
| 29722 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 562(*/0xB2, 0x04/*)*/, |
| 29723 | GIR_BuildMI, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29724 | GIR_AddTempRegister, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*TempRegID*//* 560(*/0xB0, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29725 | GIR_AddSimpleTempRegister, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*TempRegID*//* 561(*/0xB1, 0x04/*)*/, |
| 29726 | GIR_AddImm, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29727 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 561(*/0xB1, 0x04/*)*/, |
| 29728 | GIR_BuildMI, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29729 | GIR_AddTempRegister, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*TempRegID*//* 559(*/0xAF, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29730 | GIR_AddSimpleTempRegister, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*TempRegID*//* 560(*/0xB0, 0x04/*)*/, |
| 29731 | GIR_AddImm, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 29732 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 560(*/0xB0, 0x04/*)*/, |
| 29733 | GIR_BuildMI, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29734 | GIR_AddTempRegister, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*TempRegID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29735 | GIR_Copy, /*NewInsnID*//* 559(*/0xAF, 0x04/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 29736 | GIR_AddImm8, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*Imm*/63, |
| 29737 | GIR_AddImm8, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, /*Imm*/1, |
| 29738 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 559(*/0xAF, 0x04/*)*/, |
| 29739 | GIR_BuildMI, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29740 | GIR_AddTempRegister, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29741 | GIR_AddSimpleTempRegister, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegID*//* 558(*/0xAE, 0x04/*)*/, |
| 29742 | GIR_AddSimpleTempRegister, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, /*TempRegID*//* 559(*/0xAF, 0x04/*)*/, |
| 29743 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 558(*/0xAE, 0x04/*)*/, |
| 29744 | GIR_BuildMI, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29745 | GIR_AddTempRegister, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegID*//* 556(*/0xAC, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29746 | GIR_AddSimpleTempRegister, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegID*//* 557(*/0xAD, 0x04/*)*/, |
| 29747 | GIR_AddSimpleTempRegister, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, /*TempRegID*//* 566(*/0xB6, 0x04/*)*/, |
| 29748 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 557(*/0xAD, 0x04/*)*/, |
| 29749 | GIR_BuildMI, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29750 | GIR_AddTempRegister, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*TempRegID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29751 | GIR_AddSimpleTempRegister, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*TempRegID*//* 556(*/0xAC, 0x04/*)*/, |
| 29752 | GIR_AddImm8, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*Imm*/62, |
| 29753 | GIR_AddImm8, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, /*Imm*/2, |
| 29754 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 556(*/0xAC, 0x04/*)*/, |
| 29755 | GIR_BuildMI, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29756 | GIR_AddTempRegister, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29757 | GIR_AddSimpleTempRegister, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegID*//* 555(*/0xAB, 0x04/*)*/, |
| 29758 | GIR_AddSimpleTempRegister, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, /*TempRegID*//* 575(*/0xBF, 0x04/*)*/, |
| 29759 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 555(*/0xAB, 0x04/*)*/, |
| 29760 | GIR_BuildMI, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29761 | GIR_AddTempRegister, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegID*//* 553(*/0xA9, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29762 | GIR_AddSimpleTempRegister, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegID*//* 554(*/0xAA, 0x04/*)*/, |
| 29763 | GIR_AddSimpleTempRegister, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, /*TempRegID*//* 582(*/0xC6, 0x04/*)*/, |
| 29764 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 554(*/0xAA, 0x04/*)*/, |
| 29765 | GIR_BuildMI, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29766 | GIR_AddTempRegister, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*TempRegID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29767 | GIR_AddSimpleTempRegister, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*TempRegID*//* 553(*/0xA9, 0x04/*)*/, |
| 29768 | GIR_AddImm8, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*Imm*/60, |
| 29769 | GIR_AddImm8, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, /*Imm*/4, |
| 29770 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 553(*/0xA9, 0x04/*)*/, |
| 29771 | GIR_BuildMI, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 29772 | GIR_AddTempRegister, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29773 | GIR_AddSimpleTempRegister, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegID*//* 552(*/0xA8, 0x04/*)*/, |
| 29774 | GIR_AddSimpleTempRegister, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, /*TempRegID*//* 610(*/0xE2, 0x04/*)*/, |
| 29775 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 552(*/0xA8, 0x04/*)*/, |
| 29776 | GIR_BuildMI, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 29777 | GIR_AddTempRegister, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegID*//* 550(*/0xA6, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29778 | GIR_AddSimpleTempRegister, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegID*//* 551(*/0xA7, 0x04/*)*/, |
| 29779 | GIR_AddSimpleTempRegister, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, /*TempRegID*//* 617(*/0xE9, 0x04/*)*/, |
| 29780 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 551(*/0xA7, 0x04/*)*/, |
| 29781 | GIR_BuildMI, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 29782 | GIR_AddTempRegister, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*TempRegID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29783 | GIR_AddSimpleTempRegister, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*TempRegID*//* 550(*/0xA6, 0x04/*)*/, |
| 29784 | GIR_AddImm8, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*Imm*/32, |
| 29785 | GIR_AddImm8, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, /*Imm*/32, |
| 29786 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 550(*/0xA6, 0x04/*)*/, |
| 29787 | GIR_MakeTempReg, /*TempRegID*//* 683(*/0xAB, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29788 | GIR_MakeTempReg, /*TempRegID*//* 684(*/0xAC, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29789 | GIR_MakeTempReg, /*TempRegID*//* 685(*/0xAD, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29790 | GIR_MakeTempReg, /*TempRegID*//* 686(*/0xAE, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29791 | GIR_MakeTempReg, /*TempRegID*//* 687(*/0xAF, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29792 | GIR_MakeTempReg, /*TempRegID*//* 688(*/0xB0, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29793 | GIR_MakeTempReg, /*TempRegID*//* 689(*/0xB1, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29794 | GIR_MakeTempReg, /*TempRegID*//* 690(*/0xB2, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29795 | GIR_MakeTempReg, /*TempRegID*//* 691(*/0xB3, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29796 | GIR_MakeTempReg, /*TempRegID*//* 692(*/0xB4, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29797 | GIR_MakeTempReg, /*TempRegID*//* 693(*/0xB5, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29798 | GIR_MakeTempReg, /*TempRegID*//* 694(*/0xB6, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29799 | GIR_MakeTempReg, /*TempRegID*//* 695(*/0xB7, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29800 | GIR_MakeTempReg, /*TempRegID*//* 696(*/0xB8, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29801 | GIR_MakeTempReg, /*TempRegID*//* 697(*/0xB9, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29802 | GIR_MakeTempReg, /*TempRegID*//* 698(*/0xBA, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29803 | GIR_MakeTempReg, /*TempRegID*//* 699(*/0xBB, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29804 | GIR_MakeTempReg, /*TempRegID*//* 700(*/0xBC, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29805 | GIR_MakeTempReg, /*TempRegID*//* 701(*/0xBD, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29806 | GIR_MakeTempReg, /*TempRegID*//* 702(*/0xBE, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29807 | GIR_MakeTempReg, /*TempRegID*//* 703(*/0xBF, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29808 | GIR_MakeTempReg, /*TempRegID*//* 704(*/0xC0, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29809 | GIR_MakeTempReg, /*TempRegID*//* 705(*/0xC1, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29810 | GIR_MakeTempReg, /*TempRegID*//* 706(*/0xC2, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29811 | GIR_MakeTempReg, /*TempRegID*//* 707(*/0xC3, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29812 | GIR_MakeTempReg, /*TempRegID*//* 708(*/0xC4, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29813 | GIR_MakeTempReg, /*TempRegID*//* 709(*/0xC5, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29814 | GIR_MakeTempReg, /*TempRegID*//* 710(*/0xC6, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29815 | GIR_MakeTempReg, /*TempRegID*//* 711(*/0xC7, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29816 | GIR_MakeTempReg, /*TempRegID*//* 712(*/0xC8, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29817 | GIR_MakeTempReg, /*TempRegID*//* 713(*/0xC9, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29818 | GIR_MakeTempReg, /*TempRegID*//* 714(*/0xCA, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29819 | GIR_MakeTempReg, /*TempRegID*//* 715(*/0xCB, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29820 | GIR_MakeTempReg, /*TempRegID*//* 716(*/0xCC, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29821 | GIR_MakeTempReg, /*TempRegID*//* 717(*/0xCD, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29822 | GIR_MakeTempReg, /*TempRegID*//* 718(*/0xCE, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29823 | GIR_MakeTempReg, /*TempRegID*//* 719(*/0xCF, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29824 | GIR_MakeTempReg, /*TempRegID*//* 720(*/0xD0, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29825 | GIR_MakeTempReg, /*TempRegID*//* 721(*/0xD1, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29826 | GIR_MakeTempReg, /*TempRegID*//* 722(*/0xD2, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29827 | GIR_MakeTempReg, /*TempRegID*//* 723(*/0xD3, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29828 | GIR_MakeTempReg, /*TempRegID*//* 724(*/0xD4, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29829 | GIR_MakeTempReg, /*TempRegID*//* 725(*/0xD5, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29830 | GIR_MakeTempReg, /*TempRegID*//* 726(*/0xD6, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29831 | GIR_MakeTempReg, /*TempRegID*//* 727(*/0xD7, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29832 | GIR_MakeTempReg, /*TempRegID*//* 728(*/0xD8, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29833 | GIR_MakeTempReg, /*TempRegID*//* 729(*/0xD9, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29834 | GIR_MakeTempReg, /*TempRegID*//* 730(*/0xDA, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29835 | GIR_MakeTempReg, /*TempRegID*//* 731(*/0xDB, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29836 | GIR_MakeTempReg, /*TempRegID*//* 732(*/0xDC, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29837 | GIR_MakeTempReg, /*TempRegID*//* 733(*/0xDD, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29838 | GIR_MakeTempReg, /*TempRegID*//* 734(*/0xDE, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29839 | GIR_MakeTempReg, /*TempRegID*//* 735(*/0xDF, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29840 | GIR_MakeTempReg, /*TempRegID*//* 736(*/0xE0, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29841 | GIR_MakeTempReg, /*TempRegID*//* 737(*/0xE1, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29842 | GIR_MakeTempReg, /*TempRegID*//* 738(*/0xE2, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29843 | GIR_MakeTempReg, /*TempRegID*//* 739(*/0xE3, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29844 | GIR_MakeTempReg, /*TempRegID*//* 740(*/0xE4, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29845 | GIR_MakeTempReg, /*TempRegID*//* 741(*/0xE5, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29846 | GIR_MakeTempReg, /*TempRegID*//* 742(*/0xE6, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29847 | GIR_MakeTempReg, /*TempRegID*//* 743(*/0xE7, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29848 | GIR_MakeTempReg, /*TempRegID*//* 744(*/0xE8, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29849 | GIR_MakeTempReg, /*TempRegID*//* 745(*/0xE9, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29850 | GIR_MakeTempReg, /*TempRegID*//* 746(*/0xEA, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29851 | GIR_MakeTempReg, /*TempRegID*//* 747(*/0xEB, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29852 | GIR_MakeTempReg, /*TempRegID*//* 748(*/0xEC, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29853 | GIR_MakeTempReg, /*TempRegID*//* 749(*/0xED, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29854 | GIR_MakeTempReg, /*TempRegID*//* 750(*/0xEE, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29855 | GIR_MakeTempReg, /*TempRegID*//* 751(*/0xEF, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29856 | GIR_MakeTempReg, /*TempRegID*//* 752(*/0xF0, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29857 | GIR_MakeTempReg, /*TempRegID*//* 753(*/0xF1, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29858 | GIR_MakeTempReg, /*TempRegID*//* 754(*/0xF2, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29859 | GIR_MakeTempReg, /*TempRegID*//* 755(*/0xF3, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29860 | GIR_MakeTempReg, /*TempRegID*//* 756(*/0xF4, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29861 | GIR_MakeTempReg, /*TempRegID*//* 757(*/0xF5, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29862 | GIR_MakeTempReg, /*TempRegID*//* 758(*/0xF6, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29863 | GIR_MakeTempReg, /*TempRegID*//* 759(*/0xF7, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29864 | GIR_MakeTempReg, /*TempRegID*//* 760(*/0xF8, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29865 | GIR_MakeTempReg, /*TempRegID*//* 761(*/0xF9, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29866 | GIR_MakeTempReg, /*TempRegID*//* 762(*/0xFA, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29867 | GIR_MakeTempReg, /*TempRegID*//* 763(*/0xFB, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29868 | GIR_MakeTempReg, /*TempRegID*//* 764(*/0xFC, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29869 | GIR_MakeTempReg, /*TempRegID*//* 765(*/0xFD, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29870 | GIR_MakeTempReg, /*TempRegID*//* 766(*/0xFE, 0x05/*)*/, /*TypeID*/GILLT_s32, |
| 29871 | GIR_MakeTempReg, /*TempRegID*//* 767(*/0xFF, 0x05/*)*/, /*TypeID*/GILLT_s64, |
| 29872 | GIR_MakeTempReg, /*TempRegID*//* 768(*/0x80, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29873 | GIR_MakeTempReg, /*TempRegID*//* 769(*/0x81, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29874 | GIR_MakeTempReg, /*TempRegID*//* 770(*/0x82, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29875 | GIR_MakeTempReg, /*TempRegID*//* 771(*/0x83, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29876 | GIR_MakeTempReg, /*TempRegID*//* 772(*/0x84, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29877 | GIR_MakeTempReg, /*TempRegID*//* 773(*/0x85, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29878 | GIR_MakeTempReg, /*TempRegID*//* 774(*/0x86, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29879 | GIR_MakeTempReg, /*TempRegID*//* 775(*/0x87, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29880 | GIR_MakeTempReg, /*TempRegID*//* 776(*/0x88, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29881 | GIR_MakeTempReg, /*TempRegID*//* 777(*/0x89, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29882 | GIR_MakeTempReg, /*TempRegID*//* 778(*/0x8A, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29883 | GIR_MakeTempReg, /*TempRegID*//* 779(*/0x8B, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29884 | GIR_MakeTempReg, /*TempRegID*//* 780(*/0x8C, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29885 | GIR_MakeTempReg, /*TempRegID*//* 781(*/0x8D, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29886 | GIR_MakeTempReg, /*TempRegID*//* 782(*/0x8E, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29887 | GIR_MakeTempReg, /*TempRegID*//* 783(*/0x8F, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29888 | GIR_MakeTempReg, /*TempRegID*//* 784(*/0x90, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29889 | GIR_MakeTempReg, /*TempRegID*//* 785(*/0x91, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29890 | GIR_MakeTempReg, /*TempRegID*//* 786(*/0x92, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29891 | GIR_MakeTempReg, /*TempRegID*//* 787(*/0x93, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29892 | GIR_MakeTempReg, /*TempRegID*//* 788(*/0x94, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29893 | GIR_MakeTempReg, /*TempRegID*//* 789(*/0x95, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29894 | GIR_MakeTempReg, /*TempRegID*//* 790(*/0x96, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29895 | GIR_MakeTempReg, /*TempRegID*//* 791(*/0x97, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29896 | GIR_MakeTempReg, /*TempRegID*//* 792(*/0x98, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29897 | GIR_MakeTempReg, /*TempRegID*//* 793(*/0x99, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29898 | GIR_MakeTempReg, /*TempRegID*//* 794(*/0x9A, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29899 | GIR_MakeTempReg, /*TempRegID*//* 795(*/0x9B, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29900 | GIR_MakeTempReg, /*TempRegID*//* 796(*/0x9C, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29901 | GIR_MakeTempReg, /*TempRegID*//* 797(*/0x9D, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29902 | GIR_MakeTempReg, /*TempRegID*//* 798(*/0x9E, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29903 | GIR_MakeTempReg, /*TempRegID*//* 799(*/0x9F, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29904 | GIR_MakeTempReg, /*TempRegID*//* 800(*/0xA0, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29905 | GIR_MakeTempReg, /*TempRegID*//* 801(*/0xA1, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29906 | GIR_MakeTempReg, /*TempRegID*//* 802(*/0xA2, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29907 | GIR_MakeTempReg, /*TempRegID*//* 803(*/0xA3, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29908 | GIR_MakeTempReg, /*TempRegID*//* 804(*/0xA4, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29909 | GIR_MakeTempReg, /*TempRegID*//* 805(*/0xA5, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29910 | GIR_MakeTempReg, /*TempRegID*//* 806(*/0xA6, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29911 | GIR_MakeTempReg, /*TempRegID*//* 807(*/0xA7, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29912 | GIR_MakeTempReg, /*TempRegID*//* 808(*/0xA8, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29913 | GIR_MakeTempReg, /*TempRegID*//* 809(*/0xA9, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29914 | GIR_MakeTempReg, /*TempRegID*//* 810(*/0xAA, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29915 | GIR_MakeTempReg, /*TempRegID*//* 811(*/0xAB, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29916 | GIR_MakeTempReg, /*TempRegID*//* 812(*/0xAC, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29917 | GIR_MakeTempReg, /*TempRegID*//* 813(*/0xAD, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29918 | GIR_MakeTempReg, /*TempRegID*//* 814(*/0xAE, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29919 | GIR_MakeTempReg, /*TempRegID*//* 815(*/0xAF, 0x06/*)*/, /*TypeID*/GILLT_s64, |
| 29920 | GIR_MakeTempReg, /*TempRegID*//* 816(*/0xB0, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29921 | GIR_MakeTempReg, /*TempRegID*//* 817(*/0xB1, 0x06/*)*/, /*TypeID*/GILLT_s32, |
| 29922 | GIR_BuildMI, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29923 | GIR_AddTempRegister, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, /*TempRegID*//* 817(*/0xB1, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29924 | GIR_AddImm, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29925 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 818(*/0xB2, 0x06/*)*/, |
| 29926 | GIR_BuildMI, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29927 | GIR_AddTempRegister, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*TempRegID*//* 816(*/0xB0, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29928 | GIR_AddSimpleTempRegister, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*TempRegID*//* 817(*/0xB1, 0x06/*)*/, |
| 29929 | GIR_AddImm, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29930 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 817(*/0xB1, 0x06/*)*/, |
| 29931 | GIR_BuildMI, /*InsnID*//* 816(*/0xB0, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29932 | GIR_AddTempRegister, /*InsnID*//* 816(*/0xB0, 0x06/*)*/, /*TempRegID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29933 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 816(*/0xB0, 0x06/*)*/, |
| 29934 | GIR_BuildMI, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29935 | GIR_AddTempRegister, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegID*//* 814(*/0xAE, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29936 | GIR_AddSimpleTempRegister, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegID*//* 815(*/0xAF, 0x06/*)*/, |
| 29937 | GIR_AddSimpleTempRegister, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*TempRegID*//* 816(*/0xB0, 0x06/*)*/, |
| 29938 | GIR_AddImm8, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Imm*/1, |
| 29939 | GIR_ConstrainOperandRC, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29940 | GIR_ConstrainOperandRC, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29941 | GIR_ConstrainOperandRC, /*InsnID*//* 815(*/0xAF, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29942 | GIR_BuildMI, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29943 | GIR_AddTempRegister, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*TempRegID*//* 813(*/0xAD, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29944 | GIR_AddSimpleTempRegister, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*TempRegID*//* 814(*/0xAE, 0x06/*)*/, |
| 29945 | GIR_AddImm8, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*Imm*/32, |
| 29946 | GIR_AddImm8, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, /*Imm*/31, |
| 29947 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 814(*/0xAE, 0x06/*)*/, |
| 29948 | GIR_BuildMI, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29949 | GIR_AddTempRegister, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*TempRegID*//* 812(*/0xAC, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29950 | GIR_AddSimpleTempRegister, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*TempRegID*//* 813(*/0xAD, 0x06/*)*/, |
| 29951 | GIR_AddImm, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29952 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 813(*/0xAD, 0x06/*)*/, |
| 29953 | GIR_BuildMI, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29954 | GIR_AddTempRegister, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*TempRegID*//* 811(*/0xAB, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29955 | GIR_AddSimpleTempRegister, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*TempRegID*//* 812(*/0xAC, 0x06/*)*/, |
| 29956 | GIR_AddImm, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, /*Imm*/GIMT_Encode8(61680), |
| 29957 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 812(*/0xAC, 0x06/*)*/, |
| 29958 | GIR_BuildMI, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29959 | GIR_AddTempRegister, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, /*TempRegID*//* 810(*/0xAA, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29960 | GIR_AddImm, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29961 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 811(*/0xAB, 0x06/*)*/, |
| 29962 | GIR_BuildMI, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29963 | GIR_AddTempRegister, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*TempRegID*//* 809(*/0xA9, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29964 | GIR_AddSimpleTempRegister, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*TempRegID*//* 810(*/0xAA, 0x06/*)*/, |
| 29965 | GIR_AddImm, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29966 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 810(*/0xAA, 0x06/*)*/, |
| 29967 | GIR_BuildMI, /*InsnID*//* 809(*/0xA9, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29968 | GIR_AddTempRegister, /*InsnID*//* 809(*/0xA9, 0x06/*)*/, /*TempRegID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29969 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 809(*/0xA9, 0x06/*)*/, |
| 29970 | GIR_BuildMI, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 29971 | GIR_AddTempRegister, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegID*//* 807(*/0xA7, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29972 | GIR_AddSimpleTempRegister, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegID*//* 808(*/0xA8, 0x06/*)*/, |
| 29973 | GIR_AddSimpleTempRegister, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*TempRegID*//* 809(*/0xA9, 0x06/*)*/, |
| 29974 | GIR_AddImm8, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Imm*/1, |
| 29975 | GIR_ConstrainOperandRC, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29976 | GIR_ConstrainOperandRC, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 29977 | GIR_ConstrainOperandRC, /*InsnID*//* 808(*/0xA8, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 29978 | GIR_BuildMI, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 29979 | GIR_AddTempRegister, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*TempRegID*//* 806(*/0xA6, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29980 | GIR_AddSimpleTempRegister, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*TempRegID*//* 807(*/0xA7, 0x06/*)*/, |
| 29981 | GIR_AddImm8, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*Imm*/32, |
| 29982 | GIR_AddImm8, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, /*Imm*/31, |
| 29983 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 807(*/0xA7, 0x06/*)*/, |
| 29984 | GIR_BuildMI, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 29985 | GIR_AddTempRegister, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*TempRegID*//* 805(*/0xA5, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29986 | GIR_AddSimpleTempRegister, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*TempRegID*//* 806(*/0xA6, 0x06/*)*/, |
| 29987 | GIR_AddImm, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29988 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 806(*/0xA6, 0x06/*)*/, |
| 29989 | GIR_BuildMI, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 29990 | GIR_AddTempRegister, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*TempRegID*//* 804(*/0xA4, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29991 | GIR_AddSimpleTempRegister, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*TempRegID*//* 805(*/0xA5, 0x06/*)*/, |
| 29992 | GIR_AddImm, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 29993 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 805(*/0xA5, 0x06/*)*/, |
| 29994 | GIR_BuildMI, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 29995 | GIR_AddTempRegister, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, /*TempRegID*//* 803(*/0xA3, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 29996 | GIR_AddImm, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 29997 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 804(*/0xA4, 0x06/*)*/, |
| 29998 | GIR_BuildMI, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 29999 | GIR_AddTempRegister, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*TempRegID*//* 802(*/0xA2, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30000 | GIR_AddSimpleTempRegister, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*TempRegID*//* 803(*/0xA3, 0x06/*)*/, |
| 30001 | GIR_AddImm, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30002 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 803(*/0xA3, 0x06/*)*/, |
| 30003 | GIR_BuildMI, /*InsnID*//* 802(*/0xA2, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30004 | GIR_AddTempRegister, /*InsnID*//* 802(*/0xA2, 0x06/*)*/, /*TempRegID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30005 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 802(*/0xA2, 0x06/*)*/, |
| 30006 | GIR_BuildMI, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30007 | GIR_AddTempRegister, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegID*//* 800(*/0xA0, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30008 | GIR_AddSimpleTempRegister, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegID*//* 801(*/0xA1, 0x06/*)*/, |
| 30009 | GIR_AddSimpleTempRegister, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*TempRegID*//* 802(*/0xA2, 0x06/*)*/, |
| 30010 | GIR_AddImm8, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Imm*/1, |
| 30011 | GIR_ConstrainOperandRC, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30012 | GIR_ConstrainOperandRC, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30013 | GIR_ConstrainOperandRC, /*InsnID*//* 801(*/0xA1, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30014 | GIR_BuildMI, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30015 | GIR_AddTempRegister, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*TempRegID*//* 799(*/0x9F, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30016 | GIR_AddSimpleTempRegister, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*TempRegID*//* 800(*/0xA0, 0x06/*)*/, |
| 30017 | GIR_AddImm8, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*Imm*/32, |
| 30018 | GIR_AddImm8, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, /*Imm*/31, |
| 30019 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 800(*/0xA0, 0x06/*)*/, |
| 30020 | GIR_BuildMI, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30021 | GIR_AddTempRegister, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*TempRegID*//* 798(*/0x9E, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30022 | GIR_AddSimpleTempRegister, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*TempRegID*//* 799(*/0x9F, 0x06/*)*/, |
| 30023 | GIR_AddImm, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30024 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 799(*/0x9F, 0x06/*)*/, |
| 30025 | GIR_BuildMI, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30026 | GIR_AddTempRegister, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*TempRegID*//* 797(*/0x9D, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30027 | GIR_AddSimpleTempRegister, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*TempRegID*//* 798(*/0x9E, 0x06/*)*/, |
| 30028 | GIR_AddImm, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30029 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 798(*/0x9E, 0x06/*)*/, |
| 30030 | GIR_BuildMI, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30031 | GIR_AddTempRegister, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*TempRegID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30032 | GIR_Copy, /*NewInsnID*//* 797(*/0x9D, 0x06/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30033 | GIR_AddImm8, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*Imm*/1, |
| 30034 | GIR_AddImm8, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, /*Imm*/62, |
| 30035 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 797(*/0x9D, 0x06/*)*/, |
| 30036 | GIR_BuildMI, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30037 | GIR_AddTempRegister, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegID*//* 795(*/0x9B, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30038 | GIR_AddSimpleTempRegister, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegID*//* 796(*/0x9C, 0x06/*)*/, |
| 30039 | GIR_AddSimpleTempRegister, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, /*TempRegID*//* 797(*/0x9D, 0x06/*)*/, |
| 30040 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 796(*/0x9C, 0x06/*)*/, |
| 30041 | GIR_BuildMI, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30042 | GIR_AddTempRegister, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, /*TempRegID*//* 794(*/0x9A, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30043 | GIR_AddImm, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30044 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 795(*/0x9B, 0x06/*)*/, |
| 30045 | GIR_BuildMI, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30046 | GIR_AddTempRegister, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*TempRegID*//* 793(*/0x99, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30047 | GIR_AddSimpleTempRegister, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*TempRegID*//* 794(*/0x9A, 0x06/*)*/, |
| 30048 | GIR_AddImm, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30049 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 794(*/0x9A, 0x06/*)*/, |
| 30050 | GIR_BuildMI, /*InsnID*//* 793(*/0x99, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30051 | GIR_AddTempRegister, /*InsnID*//* 793(*/0x99, 0x06/*)*/, /*TempRegID*//* 792(*/0x98, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30052 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 793(*/0x99, 0x06/*)*/, |
| 30053 | GIR_BuildMI, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30054 | GIR_AddTempRegister, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*TempRegID*//* 791(*/0x97, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30055 | GIR_AddSimpleTempRegister, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*TempRegID*//* 792(*/0x98, 0x06/*)*/, |
| 30056 | GIR_AddSimpleTempRegister, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*TempRegID*//* 793(*/0x99, 0x06/*)*/, |
| 30057 | GIR_AddImm8, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Imm*/1, |
| 30058 | GIR_ConstrainOperandRC, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30059 | GIR_ConstrainOperandRC, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30060 | GIR_ConstrainOperandRC, /*InsnID*//* 792(*/0x98, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30061 | GIR_BuildMI, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30062 | GIR_AddTempRegister, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*TempRegID*//* 790(*/0x96, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30063 | GIR_AddSimpleTempRegister, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*TempRegID*//* 791(*/0x97, 0x06/*)*/, |
| 30064 | GIR_AddImm8, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*Imm*/32, |
| 30065 | GIR_AddImm8, /*InsnID*//* 791(*/0x97, 0x06/*)*/, /*Imm*/31, |
| 30066 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 791(*/0x97, 0x06/*)*/, |
| 30067 | GIR_BuildMI, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30068 | GIR_AddTempRegister, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*TempRegID*//* 789(*/0x95, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30069 | GIR_AddSimpleTempRegister, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*TempRegID*//* 790(*/0x96, 0x06/*)*/, |
| 30070 | GIR_AddImm, /*InsnID*//* 790(*/0x96, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30071 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 790(*/0x96, 0x06/*)*/, |
| 30072 | GIR_BuildMI, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30073 | GIR_AddTempRegister, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*TempRegID*//* 788(*/0x94, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30074 | GIR_AddSimpleTempRegister, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*TempRegID*//* 789(*/0x95, 0x06/*)*/, |
| 30075 | GIR_AddImm, /*InsnID*//* 789(*/0x95, 0x06/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30076 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 789(*/0x95, 0x06/*)*/, |
| 30077 | GIR_BuildMI, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30078 | GIR_AddTempRegister, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*TempRegID*//* 787(*/0x93, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30079 | GIR_Copy, /*NewInsnID*//* 788(*/0x94, 0x06/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30080 | GIR_AddImm8, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*Imm*/63, |
| 30081 | GIR_AddImm8, /*InsnID*//* 788(*/0x94, 0x06/*)*/, /*Imm*/1, |
| 30082 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 788(*/0x94, 0x06/*)*/, |
| 30083 | GIR_BuildMI, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30084 | GIR_AddTempRegister, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*TempRegID*//* 786(*/0x92, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30085 | GIR_AddSimpleTempRegister, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*TempRegID*//* 787(*/0x93, 0x06/*)*/, |
| 30086 | GIR_AddSimpleTempRegister, /*InsnID*//* 787(*/0x93, 0x06/*)*/, /*TempRegID*//* 788(*/0x94, 0x06/*)*/, |
| 30087 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 787(*/0x93, 0x06/*)*/, |
| 30088 | GIR_BuildMI, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30089 | GIR_AddTempRegister, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*TempRegID*//* 785(*/0x91, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30090 | GIR_AddSimpleTempRegister, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*TempRegID*//* 786(*/0x92, 0x06/*)*/, |
| 30091 | GIR_AddSimpleTempRegister, /*InsnID*//* 786(*/0x92, 0x06/*)*/, /*TempRegID*//* 795(*/0x9B, 0x06/*)*/, |
| 30092 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 786(*/0x92, 0x06/*)*/, |
| 30093 | GIR_BuildMI, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30094 | GIR_AddTempRegister, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*TempRegID*//* 784(*/0x90, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30095 | GIR_AddSimpleTempRegister, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*TempRegID*//* 785(*/0x91, 0x06/*)*/, |
| 30096 | GIR_AddImm8, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*Imm*/2, |
| 30097 | GIR_AddImm8, /*InsnID*//* 785(*/0x91, 0x06/*)*/, /*Imm*/61, |
| 30098 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 785(*/0x91, 0x06/*)*/, |
| 30099 | GIR_BuildMI, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30100 | GIR_AddTempRegister, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*TempRegID*//* 783(*/0x8F, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30101 | GIR_AddSimpleTempRegister, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*TempRegID*//* 784(*/0x90, 0x06/*)*/, |
| 30102 | GIR_AddSimpleTempRegister, /*InsnID*//* 784(*/0x90, 0x06/*)*/, /*TempRegID*//* 804(*/0xA4, 0x06/*)*/, |
| 30103 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 784(*/0x90, 0x06/*)*/, |
| 30104 | GIR_BuildMI, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30105 | GIR_AddTempRegister, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, /*TempRegID*//* 782(*/0x8E, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30106 | GIR_AddImm, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30107 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 783(*/0x8F, 0x06/*)*/, |
| 30108 | GIR_BuildMI, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30109 | GIR_AddTempRegister, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*TempRegID*//* 781(*/0x8D, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30110 | GIR_AddSimpleTempRegister, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*TempRegID*//* 782(*/0x8E, 0x06/*)*/, |
| 30111 | GIR_AddImm, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30112 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 782(*/0x8E, 0x06/*)*/, |
| 30113 | GIR_BuildMI, /*InsnID*//* 781(*/0x8D, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30114 | GIR_AddTempRegister, /*InsnID*//* 781(*/0x8D, 0x06/*)*/, /*TempRegID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30115 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 781(*/0x8D, 0x06/*)*/, |
| 30116 | GIR_BuildMI, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30117 | GIR_AddTempRegister, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegID*//* 779(*/0x8B, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30118 | GIR_AddSimpleTempRegister, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegID*//* 780(*/0x8C, 0x06/*)*/, |
| 30119 | GIR_AddSimpleTempRegister, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*TempRegID*//* 781(*/0x8D, 0x06/*)*/, |
| 30120 | GIR_AddImm8, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Imm*/1, |
| 30121 | GIR_ConstrainOperandRC, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30122 | GIR_ConstrainOperandRC, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30123 | GIR_ConstrainOperandRC, /*InsnID*//* 780(*/0x8C, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30124 | GIR_BuildMI, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30125 | GIR_AddTempRegister, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*TempRegID*//* 778(*/0x8A, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30126 | GIR_AddSimpleTempRegister, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*TempRegID*//* 779(*/0x8B, 0x06/*)*/, |
| 30127 | GIR_AddImm8, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*Imm*/32, |
| 30128 | GIR_AddImm8, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, /*Imm*/31, |
| 30129 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 779(*/0x8B, 0x06/*)*/, |
| 30130 | GIR_BuildMI, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30131 | GIR_AddTempRegister, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*TempRegID*//* 777(*/0x89, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30132 | GIR_AddSimpleTempRegister, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*TempRegID*//* 778(*/0x8A, 0x06/*)*/, |
| 30133 | GIR_AddImm, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30134 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 778(*/0x8A, 0x06/*)*/, |
| 30135 | GIR_BuildMI, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30136 | GIR_AddTempRegister, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*TempRegID*//* 776(*/0x88, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30137 | GIR_AddSimpleTempRegister, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*TempRegID*//* 777(*/0x89, 0x06/*)*/, |
| 30138 | GIR_AddImm, /*InsnID*//* 777(*/0x89, 0x06/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30139 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 777(*/0x89, 0x06/*)*/, |
| 30140 | GIR_BuildMI, /*InsnID*//* 776(*/0x88, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30141 | GIR_AddTempRegister, /*InsnID*//* 776(*/0x88, 0x06/*)*/, /*TempRegID*//* 775(*/0x87, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30142 | GIR_AddImm, /*InsnID*//* 776(*/0x88, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30143 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 776(*/0x88, 0x06/*)*/, |
| 30144 | GIR_BuildMI, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30145 | GIR_AddTempRegister, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*TempRegID*//* 774(*/0x86, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30146 | GIR_AddSimpleTempRegister, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*TempRegID*//* 775(*/0x87, 0x06/*)*/, |
| 30147 | GIR_AddImm, /*InsnID*//* 775(*/0x87, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30148 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 775(*/0x87, 0x06/*)*/, |
| 30149 | GIR_BuildMI, /*InsnID*//* 774(*/0x86, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30150 | GIR_AddTempRegister, /*InsnID*//* 774(*/0x86, 0x06/*)*/, /*TempRegID*//* 773(*/0x85, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30151 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 774(*/0x86, 0x06/*)*/, |
| 30152 | GIR_BuildMI, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30153 | GIR_AddTempRegister, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*TempRegID*//* 772(*/0x84, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30154 | GIR_AddSimpleTempRegister, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*TempRegID*//* 773(*/0x85, 0x06/*)*/, |
| 30155 | GIR_AddSimpleTempRegister, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*TempRegID*//* 774(*/0x86, 0x06/*)*/, |
| 30156 | GIR_AddImm8, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Imm*/1, |
| 30157 | GIR_ConstrainOperandRC, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30158 | GIR_ConstrainOperandRC, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30159 | GIR_ConstrainOperandRC, /*InsnID*//* 773(*/0x85, 0x06/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30160 | GIR_BuildMI, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30161 | GIR_AddTempRegister, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*TempRegID*//* 771(*/0x83, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30162 | GIR_AddSimpleTempRegister, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*TempRegID*//* 772(*/0x84, 0x06/*)*/, |
| 30163 | GIR_AddImm8, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*Imm*/32, |
| 30164 | GIR_AddImm8, /*InsnID*//* 772(*/0x84, 0x06/*)*/, /*Imm*/31, |
| 30165 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 772(*/0x84, 0x06/*)*/, |
| 30166 | GIR_BuildMI, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30167 | GIR_AddTempRegister, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*TempRegID*//* 770(*/0x82, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30168 | GIR_AddSimpleTempRegister, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*TempRegID*//* 771(*/0x83, 0x06/*)*/, |
| 30169 | GIR_AddImm, /*InsnID*//* 771(*/0x83, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30170 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 771(*/0x83, 0x06/*)*/, |
| 30171 | GIR_BuildMI, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30172 | GIR_AddTempRegister, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*TempRegID*//* 769(*/0x81, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30173 | GIR_AddSimpleTempRegister, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*TempRegID*//* 770(*/0x82, 0x06/*)*/, |
| 30174 | GIR_AddImm, /*InsnID*//* 770(*/0x82, 0x06/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30175 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 770(*/0x82, 0x06/*)*/, |
| 30176 | GIR_BuildMI, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30177 | GIR_AddTempRegister, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*TempRegID*//* 768(*/0x80, 0x06/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30178 | GIR_Copy, /*NewInsnID*//* 769(*/0x81, 0x06/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30179 | GIR_AddImm8, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*Imm*/1, |
| 30180 | GIR_AddImm8, /*InsnID*//* 769(*/0x81, 0x06/*)*/, /*Imm*/62, |
| 30181 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 769(*/0x81, 0x06/*)*/, |
| 30182 | GIR_BuildMI, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30183 | GIR_AddTempRegister, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*TempRegID*//* 767(*/0xFF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30184 | GIR_AddSimpleTempRegister, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*TempRegID*//* 768(*/0x80, 0x06/*)*/, |
| 30185 | GIR_AddSimpleTempRegister, /*InsnID*//* 768(*/0x80, 0x06/*)*/, /*TempRegID*//* 769(*/0x81, 0x06/*)*/, |
| 30186 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 768(*/0x80, 0x06/*)*/, |
| 30187 | GIR_BuildMI, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30188 | GIR_AddTempRegister, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, /*TempRegID*//* 766(*/0xFE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30189 | GIR_AddImm, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30190 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 767(*/0xFF, 0x05/*)*/, |
| 30191 | GIR_BuildMI, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30192 | GIR_AddTempRegister, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*TempRegID*//* 765(*/0xFD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30193 | GIR_AddSimpleTempRegister, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*TempRegID*//* 766(*/0xFE, 0x05/*)*/, |
| 30194 | GIR_AddImm, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30195 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 766(*/0xFE, 0x05/*)*/, |
| 30196 | GIR_BuildMI, /*InsnID*//* 765(*/0xFD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30197 | GIR_AddTempRegister, /*InsnID*//* 765(*/0xFD, 0x05/*)*/, /*TempRegID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30198 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 765(*/0xFD, 0x05/*)*/, |
| 30199 | GIR_BuildMI, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30200 | GIR_AddTempRegister, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegID*//* 763(*/0xFB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30201 | GIR_AddSimpleTempRegister, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegID*//* 764(*/0xFC, 0x05/*)*/, |
| 30202 | GIR_AddSimpleTempRegister, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*TempRegID*//* 765(*/0xFD, 0x05/*)*/, |
| 30203 | GIR_AddImm8, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Imm*/1, |
| 30204 | GIR_ConstrainOperandRC, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30205 | GIR_ConstrainOperandRC, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30206 | GIR_ConstrainOperandRC, /*InsnID*//* 764(*/0xFC, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30207 | GIR_BuildMI, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30208 | GIR_AddTempRegister, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*TempRegID*//* 762(*/0xFA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30209 | GIR_AddSimpleTempRegister, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*TempRegID*//* 763(*/0xFB, 0x05/*)*/, |
| 30210 | GIR_AddImm8, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*Imm*/32, |
| 30211 | GIR_AddImm8, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, /*Imm*/31, |
| 30212 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 763(*/0xFB, 0x05/*)*/, |
| 30213 | GIR_BuildMI, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30214 | GIR_AddTempRegister, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*TempRegID*//* 761(*/0xF9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30215 | GIR_AddSimpleTempRegister, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*TempRegID*//* 762(*/0xFA, 0x05/*)*/, |
| 30216 | GIR_AddImm, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30217 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 762(*/0xFA, 0x05/*)*/, |
| 30218 | GIR_BuildMI, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30219 | GIR_AddTempRegister, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*TempRegID*//* 760(*/0xF8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30220 | GIR_AddSimpleTempRegister, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*TempRegID*//* 761(*/0xF9, 0x05/*)*/, |
| 30221 | GIR_AddImm, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30222 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 761(*/0xF9, 0x05/*)*/, |
| 30223 | GIR_BuildMI, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30224 | GIR_AddTempRegister, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*TempRegID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30225 | GIR_Copy, /*NewInsnID*//* 760(*/0xF8, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30226 | GIR_AddImm8, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*Imm*/63, |
| 30227 | GIR_AddImm8, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, /*Imm*/1, |
| 30228 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 760(*/0xF8, 0x05/*)*/, |
| 30229 | GIR_BuildMI, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30230 | GIR_AddTempRegister, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30231 | GIR_AddSimpleTempRegister, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegID*//* 759(*/0xF7, 0x05/*)*/, |
| 30232 | GIR_AddSimpleTempRegister, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, /*TempRegID*//* 760(*/0xF8, 0x05/*)*/, |
| 30233 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 759(*/0xF7, 0x05/*)*/, |
| 30234 | GIR_BuildMI, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30235 | GIR_AddTempRegister, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegID*//* 757(*/0xF5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30236 | GIR_AddSimpleTempRegister, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegID*//* 758(*/0xF6, 0x05/*)*/, |
| 30237 | GIR_AddSimpleTempRegister, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, /*TempRegID*//* 767(*/0xFF, 0x05/*)*/, |
| 30238 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 758(*/0xF6, 0x05/*)*/, |
| 30239 | GIR_BuildMI, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30240 | GIR_AddTempRegister, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*TempRegID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30241 | GIR_AddSimpleTempRegister, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*TempRegID*//* 757(*/0xF5, 0x05/*)*/, |
| 30242 | GIR_AddImm8, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*Imm*/62, |
| 30243 | GIR_AddImm8, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, /*Imm*/2, |
| 30244 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 757(*/0xF5, 0x05/*)*/, |
| 30245 | GIR_BuildMI, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30246 | GIR_AddTempRegister, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30247 | GIR_AddSimpleTempRegister, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegID*//* 756(*/0xF4, 0x05/*)*/, |
| 30248 | GIR_AddSimpleTempRegister, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, /*TempRegID*//* 776(*/0x88, 0x06/*)*/, |
| 30249 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 756(*/0xF4, 0x05/*)*/, |
| 30250 | GIR_BuildMI, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30251 | GIR_AddTempRegister, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegID*//* 754(*/0xF2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30252 | GIR_AddSimpleTempRegister, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegID*//* 755(*/0xF3, 0x05/*)*/, |
| 30253 | GIR_AddSimpleTempRegister, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, /*TempRegID*//* 783(*/0x8F, 0x06/*)*/, |
| 30254 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 755(*/0xF3, 0x05/*)*/, |
| 30255 | GIR_BuildMI, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30256 | GIR_AddTempRegister, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*TempRegID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30257 | GIR_AddSimpleTempRegister, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*TempRegID*//* 754(*/0xF2, 0x05/*)*/, |
| 30258 | GIR_AddImm8, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*Imm*/4, |
| 30259 | GIR_AddImm8, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, /*Imm*/59, |
| 30260 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 754(*/0xF2, 0x05/*)*/, |
| 30261 | GIR_BuildMI, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30262 | GIR_AddTempRegister, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegID*//* 752(*/0xF0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30263 | GIR_AddSimpleTempRegister, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegID*//* 753(*/0xF1, 0x05/*)*/, |
| 30264 | GIR_AddSimpleTempRegister, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, /*TempRegID*//* 811(*/0xAB, 0x06/*)*/, |
| 30265 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 753(*/0xF1, 0x05/*)*/, |
| 30266 | GIR_BuildMI, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30267 | GIR_AddTempRegister, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, /*TempRegID*//* 751(*/0xEF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30268 | GIR_AddImm, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 30269 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 752(*/0xF0, 0x05/*)*/, |
| 30270 | GIR_BuildMI, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30271 | GIR_AddTempRegister, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*TempRegID*//* 750(*/0xEE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30272 | GIR_AddSimpleTempRegister, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*TempRegID*//* 751(*/0xEF, 0x05/*)*/, |
| 30273 | GIR_AddImm, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 30274 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 751(*/0xEF, 0x05/*)*/, |
| 30275 | GIR_BuildMI, /*InsnID*//* 750(*/0xEE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30276 | GIR_AddTempRegister, /*InsnID*//* 750(*/0xEE, 0x05/*)*/, /*TempRegID*//* 749(*/0xED, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30277 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 750(*/0xEE, 0x05/*)*/, |
| 30278 | GIR_BuildMI, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30279 | GIR_AddTempRegister, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*TempRegID*//* 748(*/0xEC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30280 | GIR_AddSimpleTempRegister, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*TempRegID*//* 749(*/0xED, 0x05/*)*/, |
| 30281 | GIR_AddSimpleTempRegister, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*TempRegID*//* 750(*/0xEE, 0x05/*)*/, |
| 30282 | GIR_AddImm8, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Imm*/1, |
| 30283 | GIR_ConstrainOperandRC, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30284 | GIR_ConstrainOperandRC, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30285 | GIR_ConstrainOperandRC, /*InsnID*//* 749(*/0xED, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30286 | GIR_BuildMI, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30287 | GIR_AddTempRegister, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*TempRegID*//* 747(*/0xEB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30288 | GIR_AddSimpleTempRegister, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*TempRegID*//* 748(*/0xEC, 0x05/*)*/, |
| 30289 | GIR_AddImm8, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*Imm*/32, |
| 30290 | GIR_AddImm8, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, /*Imm*/31, |
| 30291 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 748(*/0xEC, 0x05/*)*/, |
| 30292 | GIR_BuildMI, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30293 | GIR_AddTempRegister, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*TempRegID*//* 746(*/0xEA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30294 | GIR_AddSimpleTempRegister, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*TempRegID*//* 747(*/0xEB, 0x05/*)*/, |
| 30295 | GIR_AddImm, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 30296 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 747(*/0xEB, 0x05/*)*/, |
| 30297 | GIR_BuildMI, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30298 | GIR_AddTempRegister, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*TempRegID*//* 745(*/0xE9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30299 | GIR_AddSimpleTempRegister, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*TempRegID*//* 746(*/0xEA, 0x05/*)*/, |
| 30300 | GIR_AddImm, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, /*Imm*/GIMT_Encode8(3855), |
| 30301 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 746(*/0xEA, 0x05/*)*/, |
| 30302 | GIR_BuildMI, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30303 | GIR_AddTempRegister, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, /*TempRegID*//* 744(*/0xE8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30304 | GIR_AddImm, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 30305 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 745(*/0xE9, 0x05/*)*/, |
| 30306 | GIR_BuildMI, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30307 | GIR_AddTempRegister, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*TempRegID*//* 743(*/0xE7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30308 | GIR_AddSimpleTempRegister, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*TempRegID*//* 744(*/0xE8, 0x05/*)*/, |
| 30309 | GIR_AddImm, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 30310 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 744(*/0xE8, 0x05/*)*/, |
| 30311 | GIR_BuildMI, /*InsnID*//* 743(*/0xE7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30312 | GIR_AddTempRegister, /*InsnID*//* 743(*/0xE7, 0x05/*)*/, /*TempRegID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30313 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 743(*/0xE7, 0x05/*)*/, |
| 30314 | GIR_BuildMI, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30315 | GIR_AddTempRegister, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegID*//* 741(*/0xE5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30316 | GIR_AddSimpleTempRegister, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegID*//* 742(*/0xE6, 0x05/*)*/, |
| 30317 | GIR_AddSimpleTempRegister, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*TempRegID*//* 743(*/0xE7, 0x05/*)*/, |
| 30318 | GIR_AddImm8, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Imm*/1, |
| 30319 | GIR_ConstrainOperandRC, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30320 | GIR_ConstrainOperandRC, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30321 | GIR_ConstrainOperandRC, /*InsnID*//* 742(*/0xE6, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30322 | GIR_BuildMI, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30323 | GIR_AddTempRegister, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*TempRegID*//* 740(*/0xE4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30324 | GIR_AddSimpleTempRegister, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*TempRegID*//* 741(*/0xE5, 0x05/*)*/, |
| 30325 | GIR_AddImm8, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*Imm*/32, |
| 30326 | GIR_AddImm8, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, /*Imm*/31, |
| 30327 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 741(*/0xE5, 0x05/*)*/, |
| 30328 | GIR_BuildMI, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30329 | GIR_AddTempRegister, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*TempRegID*//* 739(*/0xE3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30330 | GIR_AddSimpleTempRegister, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*TempRegID*//* 740(*/0xE4, 0x05/*)*/, |
| 30331 | GIR_AddImm, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 30332 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 740(*/0xE4, 0x05/*)*/, |
| 30333 | GIR_BuildMI, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30334 | GIR_AddTempRegister, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*TempRegID*//* 738(*/0xE2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30335 | GIR_AddSimpleTempRegister, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*TempRegID*//* 739(*/0xE3, 0x05/*)*/, |
| 30336 | GIR_AddImm, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, /*Imm*/GIMT_Encode8(52428), |
| 30337 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 739(*/0xE3, 0x05/*)*/, |
| 30338 | GIR_BuildMI, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30339 | GIR_AddTempRegister, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, /*TempRegID*//* 737(*/0xE1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30340 | GIR_AddImm, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30341 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 738(*/0xE2, 0x05/*)*/, |
| 30342 | GIR_BuildMI, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30343 | GIR_AddTempRegister, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*TempRegID*//* 736(*/0xE0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30344 | GIR_AddSimpleTempRegister, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*TempRegID*//* 737(*/0xE1, 0x05/*)*/, |
| 30345 | GIR_AddImm, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30346 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 737(*/0xE1, 0x05/*)*/, |
| 30347 | GIR_BuildMI, /*InsnID*//* 736(*/0xE0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30348 | GIR_AddTempRegister, /*InsnID*//* 736(*/0xE0, 0x05/*)*/, /*TempRegID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30349 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 736(*/0xE0, 0x05/*)*/, |
| 30350 | GIR_BuildMI, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30351 | GIR_AddTempRegister, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegID*//* 734(*/0xDE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30352 | GIR_AddSimpleTempRegister, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegID*//* 735(*/0xDF, 0x05/*)*/, |
| 30353 | GIR_AddSimpleTempRegister, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*TempRegID*//* 736(*/0xE0, 0x05/*)*/, |
| 30354 | GIR_AddImm8, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Imm*/1, |
| 30355 | GIR_ConstrainOperandRC, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30356 | GIR_ConstrainOperandRC, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30357 | GIR_ConstrainOperandRC, /*InsnID*//* 735(*/0xDF, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30358 | GIR_BuildMI, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30359 | GIR_AddTempRegister, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*TempRegID*//* 733(*/0xDD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30360 | GIR_AddSimpleTempRegister, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*TempRegID*//* 734(*/0xDE, 0x05/*)*/, |
| 30361 | GIR_AddImm8, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*Imm*/32, |
| 30362 | GIR_AddImm8, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, /*Imm*/31, |
| 30363 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 734(*/0xDE, 0x05/*)*/, |
| 30364 | GIR_BuildMI, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30365 | GIR_AddTempRegister, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*TempRegID*//* 732(*/0xDC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30366 | GIR_AddSimpleTempRegister, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*TempRegID*//* 733(*/0xDD, 0x05/*)*/, |
| 30367 | GIR_AddImm, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30368 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 733(*/0xDD, 0x05/*)*/, |
| 30369 | GIR_BuildMI, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30370 | GIR_AddTempRegister, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*TempRegID*//* 731(*/0xDB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30371 | GIR_AddSimpleTempRegister, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*TempRegID*//* 732(*/0xDC, 0x05/*)*/, |
| 30372 | GIR_AddImm, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30373 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 732(*/0xDC, 0x05/*)*/, |
| 30374 | GIR_BuildMI, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30375 | GIR_AddTempRegister, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*TempRegID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30376 | GIR_Copy, /*NewInsnID*//* 731(*/0xDB, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30377 | GIR_AddImm8, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*Imm*/1, |
| 30378 | GIR_AddImm8, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, /*Imm*/62, |
| 30379 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 731(*/0xDB, 0x05/*)*/, |
| 30380 | GIR_BuildMI, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30381 | GIR_AddTempRegister, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegID*//* 729(*/0xD9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30382 | GIR_AddSimpleTempRegister, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegID*//* 730(*/0xDA, 0x05/*)*/, |
| 30383 | GIR_AddSimpleTempRegister, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, /*TempRegID*//* 731(*/0xDB, 0x05/*)*/, |
| 30384 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 730(*/0xDA, 0x05/*)*/, |
| 30385 | GIR_BuildMI, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30386 | GIR_AddTempRegister, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, /*TempRegID*//* 728(*/0xD8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30387 | GIR_AddImm, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30388 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 729(*/0xD9, 0x05/*)*/, |
| 30389 | GIR_BuildMI, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30390 | GIR_AddTempRegister, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*TempRegID*//* 727(*/0xD7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30391 | GIR_AddSimpleTempRegister, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*TempRegID*//* 728(*/0xD8, 0x05/*)*/, |
| 30392 | GIR_AddImm, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30393 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 728(*/0xD8, 0x05/*)*/, |
| 30394 | GIR_BuildMI, /*InsnID*//* 727(*/0xD7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30395 | GIR_AddTempRegister, /*InsnID*//* 727(*/0xD7, 0x05/*)*/, /*TempRegID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30396 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 727(*/0xD7, 0x05/*)*/, |
| 30397 | GIR_BuildMI, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30398 | GIR_AddTempRegister, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegID*//* 725(*/0xD5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30399 | GIR_AddSimpleTempRegister, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegID*//* 726(*/0xD6, 0x05/*)*/, |
| 30400 | GIR_AddSimpleTempRegister, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*TempRegID*//* 727(*/0xD7, 0x05/*)*/, |
| 30401 | GIR_AddImm8, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Imm*/1, |
| 30402 | GIR_ConstrainOperandRC, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30403 | GIR_ConstrainOperandRC, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30404 | GIR_ConstrainOperandRC, /*InsnID*//* 726(*/0xD6, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30405 | GIR_BuildMI, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30406 | GIR_AddTempRegister, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*TempRegID*//* 724(*/0xD4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30407 | GIR_AddSimpleTempRegister, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*TempRegID*//* 725(*/0xD5, 0x05/*)*/, |
| 30408 | GIR_AddImm8, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*Imm*/32, |
| 30409 | GIR_AddImm8, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, /*Imm*/31, |
| 30410 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 725(*/0xD5, 0x05/*)*/, |
| 30411 | GIR_BuildMI, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30412 | GIR_AddTempRegister, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*TempRegID*//* 723(*/0xD3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30413 | GIR_AddSimpleTempRegister, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*TempRegID*//* 724(*/0xD4, 0x05/*)*/, |
| 30414 | GIR_AddImm, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30415 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 724(*/0xD4, 0x05/*)*/, |
| 30416 | GIR_BuildMI, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30417 | GIR_AddTempRegister, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*TempRegID*//* 722(*/0xD2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30418 | GIR_AddSimpleTempRegister, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*TempRegID*//* 723(*/0xD3, 0x05/*)*/, |
| 30419 | GIR_AddImm, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30420 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 723(*/0xD3, 0x05/*)*/, |
| 30421 | GIR_BuildMI, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30422 | GIR_AddTempRegister, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*TempRegID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30423 | GIR_Copy, /*NewInsnID*//* 722(*/0xD2, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30424 | GIR_AddImm8, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*Imm*/63, |
| 30425 | GIR_AddImm8, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, /*Imm*/1, |
| 30426 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 722(*/0xD2, 0x05/*)*/, |
| 30427 | GIR_BuildMI, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30428 | GIR_AddTempRegister, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30429 | GIR_AddSimpleTempRegister, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegID*//* 721(*/0xD1, 0x05/*)*/, |
| 30430 | GIR_AddSimpleTempRegister, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, /*TempRegID*//* 722(*/0xD2, 0x05/*)*/, |
| 30431 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 721(*/0xD1, 0x05/*)*/, |
| 30432 | GIR_BuildMI, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30433 | GIR_AddTempRegister, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegID*//* 719(*/0xCF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30434 | GIR_AddSimpleTempRegister, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegID*//* 720(*/0xD0, 0x05/*)*/, |
| 30435 | GIR_AddSimpleTempRegister, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, /*TempRegID*//* 729(*/0xD9, 0x05/*)*/, |
| 30436 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 720(*/0xD0, 0x05/*)*/, |
| 30437 | GIR_BuildMI, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30438 | GIR_AddTempRegister, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*TempRegID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30439 | GIR_AddSimpleTempRegister, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*TempRegID*//* 719(*/0xCF, 0x05/*)*/, |
| 30440 | GIR_AddImm8, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*Imm*/2, |
| 30441 | GIR_AddImm8, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, /*Imm*/61, |
| 30442 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 719(*/0xCF, 0x05/*)*/, |
| 30443 | GIR_BuildMI, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30444 | GIR_AddTempRegister, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegID*//* 717(*/0xCD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30445 | GIR_AddSimpleTempRegister, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegID*//* 718(*/0xCE, 0x05/*)*/, |
| 30446 | GIR_AddSimpleTempRegister, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, /*TempRegID*//* 738(*/0xE2, 0x05/*)*/, |
| 30447 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 718(*/0xCE, 0x05/*)*/, |
| 30448 | GIR_BuildMI, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30449 | GIR_AddTempRegister, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, /*TempRegID*//* 716(*/0xCC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30450 | GIR_AddImm, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30451 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 717(*/0xCD, 0x05/*)*/, |
| 30452 | GIR_BuildMI, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30453 | GIR_AddTempRegister, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*TempRegID*//* 715(*/0xCB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30454 | GIR_AddSimpleTempRegister, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*TempRegID*//* 716(*/0xCC, 0x05/*)*/, |
| 30455 | GIR_AddImm, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30456 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 716(*/0xCC, 0x05/*)*/, |
| 30457 | GIR_BuildMI, /*InsnID*//* 715(*/0xCB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30458 | GIR_AddTempRegister, /*InsnID*//* 715(*/0xCB, 0x05/*)*/, /*TempRegID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30459 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 715(*/0xCB, 0x05/*)*/, |
| 30460 | GIR_BuildMI, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30461 | GIR_AddTempRegister, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegID*//* 713(*/0xC9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30462 | GIR_AddSimpleTempRegister, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegID*//* 714(*/0xCA, 0x05/*)*/, |
| 30463 | GIR_AddSimpleTempRegister, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*TempRegID*//* 715(*/0xCB, 0x05/*)*/, |
| 30464 | GIR_AddImm8, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Imm*/1, |
| 30465 | GIR_ConstrainOperandRC, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30466 | GIR_ConstrainOperandRC, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30467 | GIR_ConstrainOperandRC, /*InsnID*//* 714(*/0xCA, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30468 | GIR_BuildMI, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30469 | GIR_AddTempRegister, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*TempRegID*//* 712(*/0xC8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30470 | GIR_AddSimpleTempRegister, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*TempRegID*//* 713(*/0xC9, 0x05/*)*/, |
| 30471 | GIR_AddImm8, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*Imm*/32, |
| 30472 | GIR_AddImm8, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, /*Imm*/31, |
| 30473 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 713(*/0xC9, 0x05/*)*/, |
| 30474 | GIR_BuildMI, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30475 | GIR_AddTempRegister, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*TempRegID*//* 711(*/0xC7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30476 | GIR_AddSimpleTempRegister, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*TempRegID*//* 712(*/0xC8, 0x05/*)*/, |
| 30477 | GIR_AddImm, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30478 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 712(*/0xC8, 0x05/*)*/, |
| 30479 | GIR_BuildMI, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30480 | GIR_AddTempRegister, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*TempRegID*//* 710(*/0xC6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30481 | GIR_AddSimpleTempRegister, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*TempRegID*//* 711(*/0xC7, 0x05/*)*/, |
| 30482 | GIR_AddImm, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, /*Imm*/GIMT_Encode8(13107), |
| 30483 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 711(*/0xC7, 0x05/*)*/, |
| 30484 | GIR_BuildMI, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30485 | GIR_AddTempRegister, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, /*TempRegID*//* 709(*/0xC5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30486 | GIR_AddImm, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30487 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 710(*/0xC6, 0x05/*)*/, |
| 30488 | GIR_BuildMI, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30489 | GIR_AddTempRegister, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*TempRegID*//* 708(*/0xC4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30490 | GIR_AddSimpleTempRegister, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*TempRegID*//* 709(*/0xC5, 0x05/*)*/, |
| 30491 | GIR_AddImm, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30492 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 709(*/0xC5, 0x05/*)*/, |
| 30493 | GIR_BuildMI, /*InsnID*//* 708(*/0xC4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30494 | GIR_AddTempRegister, /*InsnID*//* 708(*/0xC4, 0x05/*)*/, /*TempRegID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30495 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 708(*/0xC4, 0x05/*)*/, |
| 30496 | GIR_BuildMI, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30497 | GIR_AddTempRegister, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegID*//* 706(*/0xC2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30498 | GIR_AddSimpleTempRegister, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegID*//* 707(*/0xC3, 0x05/*)*/, |
| 30499 | GIR_AddSimpleTempRegister, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*TempRegID*//* 708(*/0xC4, 0x05/*)*/, |
| 30500 | GIR_AddImm8, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Imm*/1, |
| 30501 | GIR_ConstrainOperandRC, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30502 | GIR_ConstrainOperandRC, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30503 | GIR_ConstrainOperandRC, /*InsnID*//* 707(*/0xC3, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30504 | GIR_BuildMI, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30505 | GIR_AddTempRegister, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*TempRegID*//* 705(*/0xC1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30506 | GIR_AddSimpleTempRegister, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*TempRegID*//* 706(*/0xC2, 0x05/*)*/, |
| 30507 | GIR_AddImm8, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*Imm*/32, |
| 30508 | GIR_AddImm8, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, /*Imm*/31, |
| 30509 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 706(*/0xC2, 0x05/*)*/, |
| 30510 | GIR_BuildMI, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30511 | GIR_AddTempRegister, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*TempRegID*//* 704(*/0xC0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30512 | GIR_AddSimpleTempRegister, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*TempRegID*//* 705(*/0xC1, 0x05/*)*/, |
| 30513 | GIR_AddImm, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30514 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 705(*/0xC1, 0x05/*)*/, |
| 30515 | GIR_BuildMI, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30516 | GIR_AddTempRegister, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*TempRegID*//* 703(*/0xBF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30517 | GIR_AddSimpleTempRegister, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*TempRegID*//* 704(*/0xC0, 0x05/*)*/, |
| 30518 | GIR_AddImm, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, /*Imm*/GIMT_Encode8(43690), |
| 30519 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 704(*/0xC0, 0x05/*)*/, |
| 30520 | GIR_BuildMI, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30521 | GIR_AddTempRegister, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*TempRegID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30522 | GIR_Copy, /*NewInsnID*//* 703(*/0xBF, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30523 | GIR_AddImm8, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*Imm*/1, |
| 30524 | GIR_AddImm8, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, /*Imm*/62, |
| 30525 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 703(*/0xBF, 0x05/*)*/, |
| 30526 | GIR_BuildMI, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30527 | GIR_AddTempRegister, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegID*//* 701(*/0xBD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30528 | GIR_AddSimpleTempRegister, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegID*//* 702(*/0xBE, 0x05/*)*/, |
| 30529 | GIR_AddSimpleTempRegister, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, /*TempRegID*//* 703(*/0xBF, 0x05/*)*/, |
| 30530 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 702(*/0xBE, 0x05/*)*/, |
| 30531 | GIR_BuildMI, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::LIS), |
| 30532 | GIR_AddTempRegister, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, /*TempRegID*//* 700(*/0xBC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30533 | GIR_AddImm, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30534 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 701(*/0xBD, 0x05/*)*/, |
| 30535 | GIR_BuildMI, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI), |
| 30536 | GIR_AddTempRegister, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*TempRegID*//* 699(*/0xBB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30537 | GIR_AddSimpleTempRegister, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*TempRegID*//* 700(*/0xBC, 0x05/*)*/, |
| 30538 | GIR_AddImm, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30539 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 700(*/0xBC, 0x05/*)*/, |
| 30540 | GIR_BuildMI, /*InsnID*//* 699(*/0xBB, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30541 | GIR_AddTempRegister, /*InsnID*//* 699(*/0xBB, 0x05/*)*/, /*TempRegID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30542 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 699(*/0xBB, 0x05/*)*/, |
| 30543 | GIR_BuildMI, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30544 | GIR_AddTempRegister, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegID*//* 697(*/0xB9, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30545 | GIR_AddSimpleTempRegister, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegID*//* 698(*/0xBA, 0x05/*)*/, |
| 30546 | GIR_AddSimpleTempRegister, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*TempRegID*//* 699(*/0xBB, 0x05/*)*/, |
| 30547 | GIR_AddImm8, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Imm*/1, |
| 30548 | GIR_ConstrainOperandRC, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30549 | GIR_ConstrainOperandRC, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30550 | GIR_ConstrainOperandRC, /*InsnID*//* 698(*/0xBA, 0x05/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30551 | GIR_BuildMI, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30552 | GIR_AddTempRegister, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*TempRegID*//* 696(*/0xB8, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30553 | GIR_AddSimpleTempRegister, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*TempRegID*//* 697(*/0xB9, 0x05/*)*/, |
| 30554 | GIR_AddImm8, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*Imm*/32, |
| 30555 | GIR_AddImm8, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, /*Imm*/31, |
| 30556 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 697(*/0xB9, 0x05/*)*/, |
| 30557 | GIR_BuildMI, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORIS8), |
| 30558 | GIR_AddTempRegister, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*TempRegID*//* 695(*/0xB7, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30559 | GIR_AddSimpleTempRegister, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*TempRegID*//* 696(*/0xB8, 0x05/*)*/, |
| 30560 | GIR_AddImm, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30561 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 696(*/0xB8, 0x05/*)*/, |
| 30562 | GIR_BuildMI, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::ORI8), |
| 30563 | GIR_AddTempRegister, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*TempRegID*//* 694(*/0xB6, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30564 | GIR_AddSimpleTempRegister, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*TempRegID*//* 695(*/0xB7, 0x05/*)*/, |
| 30565 | GIR_AddImm, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, /*Imm*/GIMT_Encode8(21845), |
| 30566 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 695(*/0xB7, 0x05/*)*/, |
| 30567 | GIR_BuildMI, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30568 | GIR_AddTempRegister, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*TempRegID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30569 | GIR_Copy, /*NewInsnID*//* 694(*/0xB6, 0x05/*)*/, /*OldInsnID*/0, /*OpIdx*/1, // A |
| 30570 | GIR_AddImm8, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*Imm*/63, |
| 30571 | GIR_AddImm8, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, /*Imm*/1, |
| 30572 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 694(*/0xB6, 0x05/*)*/, |
| 30573 | GIR_BuildMI, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30574 | GIR_AddTempRegister, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30575 | GIR_AddSimpleTempRegister, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegID*//* 693(*/0xB5, 0x05/*)*/, |
| 30576 | GIR_AddSimpleTempRegister, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, /*TempRegID*//* 694(*/0xB6, 0x05/*)*/, |
| 30577 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 693(*/0xB5, 0x05/*)*/, |
| 30578 | GIR_BuildMI, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30579 | GIR_AddTempRegister, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegID*//* 691(*/0xB3, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30580 | GIR_AddSimpleTempRegister, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegID*//* 692(*/0xB4, 0x05/*)*/, |
| 30581 | GIR_AddSimpleTempRegister, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, /*TempRegID*//* 701(*/0xBD, 0x05/*)*/, |
| 30582 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 692(*/0xB4, 0x05/*)*/, |
| 30583 | GIR_BuildMI, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30584 | GIR_AddTempRegister, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*TempRegID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30585 | GIR_AddSimpleTempRegister, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*TempRegID*//* 691(*/0xB3, 0x05/*)*/, |
| 30586 | GIR_AddImm8, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*Imm*/62, |
| 30587 | GIR_AddImm8, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, /*Imm*/2, |
| 30588 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 691(*/0xB3, 0x05/*)*/, |
| 30589 | GIR_BuildMI, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30590 | GIR_AddTempRegister, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30591 | GIR_AddSimpleTempRegister, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegID*//* 690(*/0xB2, 0x05/*)*/, |
| 30592 | GIR_AddSimpleTempRegister, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, /*TempRegID*//* 710(*/0xC6, 0x05/*)*/, |
| 30593 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 690(*/0xB2, 0x05/*)*/, |
| 30594 | GIR_BuildMI, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30595 | GIR_AddTempRegister, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegID*//* 688(*/0xB0, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30596 | GIR_AddSimpleTempRegister, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegID*//* 689(*/0xB1, 0x05/*)*/, |
| 30597 | GIR_AddSimpleTempRegister, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, /*TempRegID*//* 717(*/0xCD, 0x05/*)*/, |
| 30598 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 689(*/0xB1, 0x05/*)*/, |
| 30599 | GIR_BuildMI, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30600 | GIR_AddTempRegister, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*TempRegID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30601 | GIR_AddSimpleTempRegister, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*TempRegID*//* 688(*/0xB0, 0x05/*)*/, |
| 30602 | GIR_AddImm8, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*Imm*/60, |
| 30603 | GIR_AddImm8, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, /*Imm*/4, |
| 30604 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 688(*/0xB0, 0x05/*)*/, |
| 30605 | GIR_BuildMI, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::AND8), |
| 30606 | GIR_AddTempRegister, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30607 | GIR_AddSimpleTempRegister, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegID*//* 687(*/0xAF, 0x05/*)*/, |
| 30608 | GIR_AddSimpleTempRegister, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, /*TempRegID*//* 745(*/0xE9, 0x05/*)*/, |
| 30609 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 687(*/0xAF, 0x05/*)*/, |
| 30610 | GIR_BuildMI, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30611 | GIR_AddTempRegister, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegID*//* 685(*/0xAD, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30612 | GIR_AddSimpleTempRegister, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegID*//* 686(*/0xAE, 0x05/*)*/, |
| 30613 | GIR_AddSimpleTempRegister, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, /*TempRegID*//* 752(*/0xF0, 0x05/*)*/, |
| 30614 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 686(*/0xAE, 0x05/*)*/, |
| 30615 | GIR_BuildMI, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLDICL), |
| 30616 | GIR_AddTempRegister, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*TempRegID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30617 | GIR_AddSimpleTempRegister, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*TempRegID*//* 685(*/0xAD, 0x05/*)*/, |
| 30618 | GIR_AddImm8, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*Imm*/32, |
| 30619 | GIR_AddImm8, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, /*Imm*/32, |
| 30620 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 685(*/0xAD, 0x05/*)*/, |
| 30621 | GIR_BuildMI, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30622 | GIR_AddTempRegister, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegID*//* 683(*/0xAB, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30623 | GIR_AddTempSubRegister, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegID*//* 684(*/0xAC, 0x05/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 30624 | GIR_ConstrainOperandRC, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30625 | GIR_ConstrainOperandRC, /*InsnID*//* 684(*/0xAC, 0x05/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30626 | GIR_BuildMI, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30627 | GIR_AddTempRegister, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegID*//* 548(*/0xA4, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30628 | GIR_AddTempSubRegister, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegID*//* 549(*/0xA5, 0x04/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 30629 | GIR_ConstrainOperandRC, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30630 | GIR_ConstrainOperandRC, /*InsnID*//* 549(*/0xA5, 0x04/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30631 | GIR_BuildMI, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30632 | GIR_AddTempRegister, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegID*//* 413(*/0x9D, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30633 | GIR_AddTempSubRegister, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegID*//* 414(*/0x9E, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 30634 | GIR_ConstrainOperandRC, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30635 | GIR_ConstrainOperandRC, /*InsnID*//* 414(*/0x9E, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30636 | GIR_BuildMI, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 30637 | GIR_AddTempRegister, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*TempRegID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30638 | GIR_AddSimpleTempRegister, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*TempRegID*//* 413(*/0x9D, 0x03/*)*/, |
| 30639 | GIR_AddImm8, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Imm*/24, |
| 30640 | GIR_AddImm8, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Imm*/0, |
| 30641 | GIR_AddImm8, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, /*Imm*/31, |
| 30642 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 413(*/0x9D, 0x03/*)*/, |
| 30643 | GIR_BuildMI, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 30644 | GIR_AddTempRegister, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30645 | GIR_AddSimpleTempRegister, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegID*//* 412(*/0x9C, 0x03/*)*/, |
| 30646 | GIR_AddSimpleTempRegister, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*TempRegID*//* 548(*/0xA4, 0x04/*)*/, |
| 30647 | GIR_AddImm8, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Imm*/8, |
| 30648 | GIR_AddImm8, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Imm*/8, |
| 30649 | GIR_AddImm8, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, /*Imm*/15, |
| 30650 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 412(*/0x9C, 0x03/*)*/, |
| 30651 | GIR_BuildMI, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 30652 | GIR_AddTempRegister, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegID*//* 410(*/0x9A, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30653 | GIR_AddSimpleTempRegister, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegID*//* 411(*/0x9B, 0x03/*)*/, |
| 30654 | GIR_AddSimpleTempRegister, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*TempRegID*//* 683(*/0xAB, 0x05/*)*/, |
| 30655 | GIR_AddImm8, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Imm*/8, |
| 30656 | GIR_AddImm8, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Imm*/24, |
| 30657 | GIR_AddImm8, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, /*Imm*/31, |
| 30658 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 411(*/0x9B, 0x03/*)*/, |
| 30659 | GIR_BuildMI, /*InsnID*//* 410(*/0x9A, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30660 | GIR_AddTempRegister, /*InsnID*//* 410(*/0x9A, 0x03/*)*/, /*TempRegID*//* 409(*/0x99, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30661 | GIR_ConstrainSelectedInstOperands, /*InsnID*//* 410(*/0x9A, 0x03/*)*/, |
| 30662 | GIR_BuildMI, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30663 | GIR_AddTempRegister, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*TempRegID*//* 408(*/0x98, 0x03/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30664 | GIR_AddSimpleTempRegister, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*TempRegID*//* 409(*/0x99, 0x03/*)*/, |
| 30665 | GIR_AddSimpleTempRegister, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*TempRegID*//* 410(*/0x9A, 0x03/*)*/, |
| 30666 | GIR_AddImm8, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Imm*/1, |
| 30667 | GIR_ConstrainOperandRC, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30668 | GIR_ConstrainOperandRC, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30669 | GIR_ConstrainOperandRC, /*InsnID*//* 409(*/0x99, 0x03/*)*/, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30670 | GIR_BuildMI, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30671 | GIR_AddTempRegister, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*TempRegID*//* 274(*/0x92, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30672 | GIR_AddTempSubRegister, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*TempRegID*//* 275(*/0x93, 0x02/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 30673 | GIR_ConstrainOperandRC, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30674 | GIR_ConstrainOperandRC, /*InsnID*//* 275(*/0x93, 0x02/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30675 | GIR_BuildMI, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30676 | GIR_AddTempRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30677 | GIR_AddTempSubRegister, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegID*//* 141(*/0x8D, 0x01/*)*/, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 30678 | GIR_ConstrainOperandRC, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30679 | GIR_ConstrainOperandRC, /*InsnID*//* 141(*/0x8D, 0x01/*)*/, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30680 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30681 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30682 | GIR_AddTempSubRegister, /*InsnID*/7, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(PPC::sub_32), |
| 30683 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30684 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30685 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(PPC::RLWINM), |
| 30686 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30687 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 30688 | GIR_AddImm8, /*InsnID*/6, /*Imm*/24, |
| 30689 | GIR_AddImm8, /*InsnID*/6, /*Imm*/0, |
| 30690 | GIR_AddImm8, /*InsnID*/6, /*Imm*/31, |
| 30691 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 30692 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 30693 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30694 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 30695 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*//* 140(*/0x8C, 0x01/*)*/, |
| 30696 | GIR_AddImm8, /*InsnID*/5, /*Imm*/8, |
| 30697 | GIR_AddImm8, /*InsnID*/5, /*Imm*/8, |
| 30698 | GIR_AddImm8, /*InsnID*/5, /*Imm*/15, |
| 30699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 30700 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(PPC::RLWIMI), |
| 30701 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30702 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 30703 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*//* 274(*/0x92, 0x02/*)*/, |
| 30704 | GIR_AddImm8, /*InsnID*/4, /*Imm*/8, |
| 30705 | GIR_AddImm8, /*InsnID*/4, /*Imm*/24, |
| 30706 | GIR_AddImm8, /*InsnID*/4, /*Imm*/31, |
| 30707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 30708 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30709 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 30711 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 30712 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30713 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 30714 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 30715 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 30716 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30717 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(PPC::G8RCRegClassID), |
| 30718 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(PPC::GPRCRegClassID), |
| 30719 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::RLDICR), |
| 30720 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30721 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 30722 | GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 30723 | GIR_AddImm8, /*InsnID*/1, /*Imm*/31, |
| 30724 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::OR8), |
| 30726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RA] |
| 30727 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30728 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*//* 408(*/0x98, 0x03/*)*/, |
| 30729 | GIR_RootConstrainSelectedInstOperands, |
| 30730 | // GIR_Coverage, 4834, |
| 30731 | GIR_EraseRootFromParent_Done, |
| 30732 | // Label 1750: @94107 |
| 30733 | GIM_Reject, |
| 30734 | // Label 1746: @94108 |
| 30735 | GIM_Reject, |
| 30736 | // Label 70: @94109 |
| 30737 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1756*/ GIMT_Encode4(94380), |
| 30738 | /*GILLT_s32*//*Label 1751*/ GIMT_Encode4(94140), |
| 30739 | /*GILLT_s64*//*Label 1752*/ GIMT_Encode4(94230), |
| 30740 | /*GILLT_s128*//*Label 1753*/ GIMT_Encode4(94278), |
| 30741 | /*GILLT_v2s64*//*Label 1754*/ GIMT_Encode4(94309), |
| 30742 | /*GILLT_v4s32*//*Label 1755*/ GIMT_Encode4(94332), |
| 30743 | // Label 1751: @94140 |
| 30744 | GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(94229), |
| 30745 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 30746 | GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(94209), // Rule ID 1693 // |
| 30747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 30749 | // (fceil:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIP:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 30750 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30751 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 30752 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30753 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30754 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 30755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 30756 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIP), |
| 30757 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30758 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 30759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30762 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30763 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 30764 | // GIR_Coverage, 1693, |
| 30765 | GIR_EraseRootFromParent_Done, |
| 30766 | // Label 1758: @94209 |
| 30767 | GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(94228), // Rule ID 143 // |
| 30768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 30769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 30770 | // (fceil:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIPS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 30771 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIPS), |
| 30772 | GIR_RootConstrainSelectedInstOperands, |
| 30773 | // GIR_Coverage, 143, |
| 30774 | GIR_Done, |
| 30775 | // Label 1759: @94228 |
| 30776 | GIM_Reject, |
| 30777 | // Label 1757: @94229 |
| 30778 | GIM_Reject, |
| 30779 | // Label 1752: @94230 |
| 30780 | GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(94277), |
| 30781 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 30782 | GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(94257), // Rule ID 903 // |
| 30783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 30785 | // (fceil:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIP:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 30786 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIP), |
| 30787 | GIR_RootConstrainSelectedInstOperands, |
| 30788 | // GIR_Coverage, 903, |
| 30789 | GIR_Done, |
| 30790 | // Label 1761: @94257 |
| 30791 | GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(94276), // Rule ID 141 // |
| 30792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 30793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 30794 | // (fceil:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIPD:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 30795 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIPD), |
| 30796 | GIR_RootConstrainSelectedInstOperands, |
| 30797 | // GIR_Coverage, 141, |
| 30798 | GIR_Done, |
| 30799 | // Label 1762: @94276 |
| 30800 | GIM_Reject, |
| 30801 | // Label 1760: @94277 |
| 30802 | GIM_Reject, |
| 30803 | // Label 1753: @94278 |
| 30804 | GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(94308), // Rule ID 2146 // |
| 30805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 30806 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 30807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 30808 | // (fceil:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 2:{ *:[i32] }) |
| 30809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), |
| 30810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 30811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 30812 | GIR_RootToRootCopy, /*OpIdx*/1, // vB |
| 30813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 30814 | GIR_RootConstrainSelectedInstOperands, |
| 30815 | // GIR_Coverage, 2146, |
| 30816 | GIR_EraseRootFromParent_Done, |
| 30817 | // Label 1763: @94308 |
| 30818 | GIM_Reject, |
| 30819 | // Label 1754: @94309 |
| 30820 | GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(94331), // Rule ID 911 // |
| 30821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30822 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 30823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 30824 | // (fceil:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 30825 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIP), |
| 30826 | GIR_RootConstrainSelectedInstOperands, |
| 30827 | // GIR_Coverage, 911, |
| 30828 | GIR_Done, |
| 30829 | // Label 1764: @94331 |
| 30830 | GIM_Reject, |
| 30831 | // Label 1755: @94332 |
| 30832 | GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(94379), |
| 30833 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 30834 | GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(94359), // Rule ID 919 // |
| 30835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 30837 | // (fceil:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 30838 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIP), |
| 30839 | GIR_RootConstrainSelectedInstOperands, |
| 30840 | // GIR_Coverage, 919, |
| 30841 | GIR_Done, |
| 30842 | // Label 1766: @94359 |
| 30843 | GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(94378), // Rule ID 1403 // |
| 30844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 30845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 30846 | // (fceil:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIP:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA) |
| 30847 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIP), |
| 30848 | GIR_RootConstrainSelectedInstOperands, |
| 30849 | // GIR_Coverage, 1403, |
| 30850 | GIR_Done, |
| 30851 | // Label 1767: @94378 |
| 30852 | GIM_Reject, |
| 30853 | // Label 1765: @94379 |
| 30854 | GIM_Reject, |
| 30855 | // Label 1756: @94380 |
| 30856 | GIM_Reject, |
| 30857 | // Label 71: @94381 |
| 30858 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1773*/ GIMT_Encode4(94597), |
| 30859 | /*GILLT_s32*//*Label 1768*/ GIMT_Encode4(94412), |
| 30860 | /*GILLT_s64*//*Label 1769*/ GIMT_Encode4(94464), |
| 30861 | /*GILLT_s128*//*Label 1770*/ GIMT_Encode4(94520), |
| 30862 | /*GILLT_v2s64*//*Label 1771*/ GIMT_Encode4(94543), |
| 30863 | /*GILLT_v4s32*//*Label 1772*/ GIMT_Encode4(94570), |
| 30864 | // Label 1768: @94412 |
| 30865 | GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(94463), |
| 30866 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 30867 | GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(94439), // Rule ID 954 // |
| 30868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 30869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 30870 | // (fsqrt:{ *:[f32] } f32:{ *:[f32] }:$XB) => (XSSQRTSP:{ *:[f32] } f32:{ *:[f32] }:$XB) |
| 30871 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTSP), |
| 30872 | GIR_RootConstrainSelectedInstOperands, |
| 30873 | // GIR_Coverage, 954, |
| 30874 | GIR_Done, |
| 30875 | // Label 1775: @94439 |
| 30876 | GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(94462), // Rule ID 159 // |
| 30877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 30878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 30879 | // (fsqrt:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FSQRTS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 30880 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRTS), |
| 30881 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 30882 | GIR_RootConstrainSelectedInstOperands, |
| 30883 | // GIR_Coverage, 159, |
| 30884 | GIR_Done, |
| 30885 | // Label 1776: @94462 |
| 30886 | GIM_Reject, |
| 30887 | // Label 1774: @94463 |
| 30888 | GIM_Reject, |
| 30889 | // Label 1769: @94464 |
| 30890 | GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(94519), |
| 30891 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 30892 | GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(94495), // Rule ID 803 // |
| 30893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 30895 | // (fsqrt:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSSQRTDP:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 30896 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTDP), |
| 30897 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 30898 | GIR_RootConstrainSelectedInstOperands, |
| 30899 | // GIR_Coverage, 803, |
| 30900 | GIR_Done, |
| 30901 | // Label 1778: @94495 |
| 30902 | GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(94518), // Rule ID 157 // |
| 30903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 30904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 30905 | // (fsqrt:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FSQRT:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 30906 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRT), |
| 30907 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 30908 | GIR_RootConstrainSelectedInstOperands, |
| 30909 | // GIR_Coverage, 157, |
| 30910 | GIR_Done, |
| 30911 | // Label 1779: @94518 |
| 30912 | GIM_Reject, |
| 30913 | // Label 1777: @94519 |
| 30914 | GIM_Reject, |
| 30915 | // Label 1770: @94520 |
| 30916 | GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(94542), // Rule ID 986 // |
| 30917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 30918 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 30919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 30920 | // (fsqrt:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSSQRTQP:{ *:[f128] } f128:{ *:[f128] }:$RB) |
| 30921 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQP), |
| 30922 | GIR_RootConstrainSelectedInstOperands, |
| 30923 | // GIR_Coverage, 986, |
| 30924 | GIR_Done, |
| 30925 | // Label 1780: @94542 |
| 30926 | GIM_Reject, |
| 30927 | // Label 1771: @94543 |
| 30928 | GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(94569), // Rule ID 814 // |
| 30929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30930 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 30931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 30932 | // (fsqrt:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVSQRTDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 30933 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTDP), |
| 30934 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 30935 | GIR_RootConstrainSelectedInstOperands, |
| 30936 | // GIR_Coverage, 814, |
| 30937 | GIR_Done, |
| 30938 | // Label 1781: @94569 |
| 30939 | GIM_Reject, |
| 30940 | // Label 1772: @94570 |
| 30941 | GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(94596), // Rule ID 816 // |
| 30942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30943 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 30944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 30945 | // (fsqrt:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVSQRTSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 30946 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTSP), |
| 30947 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 30948 | GIR_RootConstrainSelectedInstOperands, |
| 30949 | // GIR_Coverage, 816, |
| 30950 | GIR_Done, |
| 30951 | // Label 1782: @94596 |
| 30952 | GIM_Reject, |
| 30953 | // Label 1773: @94597 |
| 30954 | GIM_Reject, |
| 30955 | // Label 72: @94598 |
| 30956 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1788*/ GIMT_Encode4(94869), |
| 30957 | /*GILLT_s32*//*Label 1783*/ GIMT_Encode4(94629), |
| 30958 | /*GILLT_s64*//*Label 1784*/ GIMT_Encode4(94719), |
| 30959 | /*GILLT_s128*//*Label 1785*/ GIMT_Encode4(94767), |
| 30960 | /*GILLT_v2s64*//*Label 1786*/ GIMT_Encode4(94798), |
| 30961 | /*GILLT_v4s32*//*Label 1787*/ GIMT_Encode4(94821), |
| 30962 | // Label 1783: @94629 |
| 30963 | GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(94718), |
| 30964 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 30965 | GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(94698), // Rule ID 1691 // |
| 30966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 30967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 30968 | // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIM:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 30969 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 30970 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 30971 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30972 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30973 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 30974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 30975 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIM), |
| 30976 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 30977 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 30978 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 30979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 30980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30981 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30982 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 30983 | // GIR_Coverage, 1691, |
| 30984 | GIR_EraseRootFromParent_Done, |
| 30985 | // Label 1790: @94698 |
| 30986 | GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(94717), // Rule ID 151 // |
| 30987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 30988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 30989 | // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FRIMS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 30990 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIMS), |
| 30991 | GIR_RootConstrainSelectedInstOperands, |
| 30992 | // GIR_Coverage, 151, |
| 30993 | GIR_Done, |
| 30994 | // Label 1791: @94717 |
| 30995 | GIM_Reject, |
| 30996 | // Label 1789: @94718 |
| 30997 | GIM_Reject, |
| 30998 | // Label 1784: @94719 |
| 30999 | GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(94766), |
| 31000 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31001 | GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(94746), // Rule ID 901 // |
| 31002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31004 | // (ffloor:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSRDPIM:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 31005 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIM), |
| 31006 | GIR_RootConstrainSelectedInstOperands, |
| 31007 | // GIR_Coverage, 901, |
| 31008 | GIR_Done, |
| 31009 | // Label 1793: @94746 |
| 31010 | GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(94765), // Rule ID 149 // |
| 31011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31013 | // (ffloor:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FRIMD:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 31014 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FRIMD), |
| 31015 | GIR_RootConstrainSelectedInstOperands, |
| 31016 | // GIR_Coverage, 149, |
| 31017 | GIR_Done, |
| 31018 | // Label 1794: @94765 |
| 31019 | GIM_Reject, |
| 31020 | // Label 1792: @94766 |
| 31021 | GIM_Reject, |
| 31022 | // Label 1785: @94767 |
| 31023 | GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(94797), // Rule ID 2148 // |
| 31024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31025 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31027 | // (ffloor:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 1:{ *:[i32] }, ?:{ *:[f128] }:$vB, 3:{ *:[i32] }) |
| 31028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), |
| 31029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 31030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 31031 | GIR_RootToRootCopy, /*OpIdx*/1, // vB |
| 31032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 31033 | GIR_RootConstrainSelectedInstOperands, |
| 31034 | // GIR_Coverage, 2148, |
| 31035 | GIR_EraseRootFromParent_Done, |
| 31036 | // Label 1795: @94797 |
| 31037 | GIM_Reject, |
| 31038 | // Label 1786: @94798 |
| 31039 | GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(94820), // Rule ID 909 // |
| 31040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31041 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31043 | // (ffloor:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVRDPIM:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 31044 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIM), |
| 31045 | GIR_RootConstrainSelectedInstOperands, |
| 31046 | // GIR_Coverage, 909, |
| 31047 | GIR_Done, |
| 31048 | // Label 1796: @94820 |
| 31049 | GIM_Reject, |
| 31050 | // Label 1787: @94821 |
| 31051 | GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(94868), |
| 31052 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31053 | GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(94848), // Rule ID 917 // |
| 31054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31056 | // (ffloor:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVRSPIM:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 31057 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIM), |
| 31058 | GIR_RootConstrainSelectedInstOperands, |
| 31059 | // GIR_Coverage, 917, |
| 31060 | GIR_Done, |
| 31061 | // Label 1798: @94848 |
| 31062 | GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(94867), // Rule ID 1402 // |
| 31063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 31064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31065 | // (ffloor:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIM:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA) |
| 31066 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIM), |
| 31067 | GIR_RootConstrainSelectedInstOperands, |
| 31068 | // GIR_Coverage, 1402, |
| 31069 | GIR_Done, |
| 31070 | // Label 1799: @94867 |
| 31071 | GIM_Reject, |
| 31072 | // Label 1797: @94868 |
| 31073 | GIM_Reject, |
| 31074 | // Label 1788: @94869 |
| 31075 | GIM_Reject, |
| 31076 | // Label 73: @94870 |
| 31077 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1805*/ GIMT_Encode4(95078), |
| 31078 | /*GILLT_s32*//*Label 1800*/ GIMT_Encode4(94901), |
| 31079 | /*GILLT_s64*//*Label 1801*/ GIMT_Encode4(94966), |
| 31080 | /*GILLT_s128*//*Label 1802*/ GIMT_Encode4(94993), |
| 31081 | /*GILLT_v2s64*//*Label 1803*/ GIMT_Encode4(95024), |
| 31082 | /*GILLT_v4s32*//*Label 1804*/ GIMT_Encode4(95051), |
| 31083 | // Label 1800: @94901 |
| 31084 | GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(94965), // Rule ID 1697 // |
| 31085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31086 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31088 | // (frint:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIC:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 31089 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31090 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 31091 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 31092 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 31093 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 31094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 31095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC), |
| 31096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 31097 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 31098 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 31100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 31101 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31102 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31103 | // GIR_Coverage, 1697, |
| 31104 | GIR_EraseRootFromParent_Done, |
| 31105 | // Label 1806: @94965 |
| 31106 | GIM_Reject, |
| 31107 | // Label 1801: @94966 |
| 31108 | GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(94992), // Rule ID 1701 // |
| 31109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31110 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31112 | // (frint:{ *:[f64] } f64:{ *:[f64] }:$S) => (XSRDPIC:{ *:[f64] } ?:{ *:[f64] }:$S) |
| 31113 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC), |
| 31114 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31115 | GIR_RootConstrainSelectedInstOperands, |
| 31116 | // GIR_Coverage, 1701, |
| 31117 | GIR_Done, |
| 31118 | // Label 1807: @94992 |
| 31119 | GIM_Reject, |
| 31120 | // Label 1802: @94993 |
| 31121 | GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(95023), // Rule ID 2150 // |
| 31122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31123 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31125 | // (frint:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPIX:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 3:{ *:[i32] }) |
| 31126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPIX), |
| 31127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 31128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31129 | GIR_RootToRootCopy, /*OpIdx*/1, // vB |
| 31130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 31131 | GIR_RootConstrainSelectedInstOperands, |
| 31132 | // GIR_Coverage, 2150, |
| 31133 | GIR_EraseRootFromParent_Done, |
| 31134 | // Label 1808: @95023 |
| 31135 | GIM_Reject, |
| 31136 | // Label 1803: @95024 |
| 31137 | GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(95050), // Rule ID 1703 // |
| 31138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31139 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31141 | // (frint:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$S) => (XVRDPIC:{ *:[v2f64] } ?:{ *:[v2f64] }:$S) |
| 31142 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIC), |
| 31143 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31144 | GIR_RootConstrainSelectedInstOperands, |
| 31145 | // GIR_Coverage, 1703, |
| 31146 | GIR_Done, |
| 31147 | // Label 1809: @95050 |
| 31148 | GIM_Reject, |
| 31149 | // Label 1804: @95051 |
| 31150 | GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(95077), // Rule ID 1699 // |
| 31151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31152 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31154 | // (frint:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$S) => (XVRSPIC:{ *:[v4f32] } ?:{ *:[v4f32] }:$S) |
| 31155 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIC), |
| 31156 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31157 | GIR_RootConstrainSelectedInstOperands, |
| 31158 | // GIR_Coverage, 1699, |
| 31159 | GIR_Done, |
| 31160 | // Label 1810: @95077 |
| 31161 | GIM_Reject, |
| 31162 | // Label 1805: @95078 |
| 31163 | GIM_Reject, |
| 31164 | // Label 74: @95079 |
| 31165 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1816*/ GIMT_Encode4(95312), |
| 31166 | /*GILLT_s32*//*Label 1811*/ GIMT_Encode4(95110), |
| 31167 | /*GILLT_s64*//*Label 1812*/ GIMT_Encode4(95175), |
| 31168 | /*GILLT_s128*//*Label 1813*/ GIMT_Encode4(95202), |
| 31169 | /*GILLT_v2s64*//*Label 1814*/ GIMT_Encode4(95233), |
| 31170 | /*GILLT_v4s32*//*Label 1815*/ GIMT_Encode4(95260), |
| 31171 | // Label 1811: @95110 |
| 31172 | GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(95174), // Rule ID 1704 // |
| 31173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31174 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31176 | // (fnearbyint:{ *:[f32] } f32:{ *:[f32] }:$S) => (COPY_TO_REGCLASS:{ *:[f32] } (XSRDPIC:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f64] } ?:{ *:[f32] }:$S, VSFRC:{ *:[i32] })), VSSRC:{ *:[i32] }) |
| 31177 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 31178 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 31179 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 31180 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 31181 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // S |
| 31182 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 31183 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC), |
| 31184 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 31185 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 31186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 31187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 31188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 31189 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31190 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31191 | // GIR_Coverage, 1704, |
| 31192 | GIR_EraseRootFromParent_Done, |
| 31193 | // Label 1817: @95174 |
| 31194 | GIM_Reject, |
| 31195 | // Label 1812: @95175 |
| 31196 | GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(95201), // Rule ID 1705 // |
| 31197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31198 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31200 | // (fnearbyint:{ *:[f64] } f64:{ *:[f64] }:$S) => (XSRDPIC:{ *:[f64] } ?:{ *:[f64] }:$S) |
| 31201 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSRDPIC), |
| 31202 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31203 | GIR_RootConstrainSelectedInstOperands, |
| 31204 | // GIR_Coverage, 1705, |
| 31205 | GIR_Done, |
| 31206 | // Label 1818: @95201 |
| 31207 | GIM_Reject, |
| 31208 | // Label 1813: @95202 |
| 31209 | GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(95232), // Rule ID 2140 // |
| 31210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31211 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31213 | // (fnearbyint:{ *:[f128] } f128:{ *:[f128] }:$vB) => (XSRQPI:{ *:[f128] } 0:{ *:[i32] }, ?:{ *:[f128] }:$vB, 3:{ *:[i32] }) |
| 31214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSRQPI), |
| 31215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[VRT] |
| 31216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31217 | GIR_RootToRootCopy, /*OpIdx*/1, // vB |
| 31218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 31219 | GIR_RootConstrainSelectedInstOperands, |
| 31220 | // GIR_Coverage, 2140, |
| 31221 | GIR_EraseRootFromParent_Done, |
| 31222 | // Label 1819: @95232 |
| 31223 | GIM_Reject, |
| 31224 | // Label 1814: @95233 |
| 31225 | GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(95259), // Rule ID 1706 // |
| 31226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31227 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31228 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31229 | // (fnearbyint:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$S) => (XVRDPIC:{ *:[v2f64] } ?:{ *:[v2f64] }:$S) |
| 31230 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRDPIC), |
| 31231 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31232 | GIR_RootConstrainSelectedInstOperands, |
| 31233 | // GIR_Coverage, 1706, |
| 31234 | GIR_Done, |
| 31235 | // Label 1820: @95259 |
| 31236 | GIM_Reject, |
| 31237 | // Label 1815: @95260 |
| 31238 | GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(95311), |
| 31239 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31240 | GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(95291), // Rule ID 1707 // |
| 31241 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31243 | // (fnearbyint:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$S) => (XVRSPIC:{ *:[v4f32] } ?:{ *:[v4f32] }:$S) |
| 31244 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVRSPIC), |
| 31245 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31246 | GIR_RootConstrainSelectedInstOperands, |
| 31247 | // GIR_Coverage, 1707, |
| 31248 | GIR_Done, |
| 31249 | // Label 1822: @95291 |
| 31250 | GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(95310), // Rule ID 1405 // |
| 31251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAltivec), |
| 31252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31253 | // (fnearbyint:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$vA) => (VRFIN:{ *:[v4f32] } ?:{ *:[v4f32] }:$vA) |
| 31254 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::VRFIN), |
| 31255 | GIR_RootConstrainSelectedInstOperands, |
| 31256 | // GIR_Coverage, 1405, |
| 31257 | GIR_Done, |
| 31258 | // Label 1823: @95310 |
| 31259 | GIM_Reject, |
| 31260 | // Label 1821: @95311 |
| 31261 | GIM_Reject, |
| 31262 | // Label 1816: @95312 |
| 31263 | GIM_Reject, |
| 31264 | // Label 75: @95313 |
| 31265 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1829*/ GIMT_Encode4(95582), |
| 31266 | /*GILLT_s32*//*Label 1824*/ GIMT_Encode4(95344), |
| 31267 | /*GILLT_s64*//*Label 1825*/ GIMT_Encode4(95418), |
| 31268 | /*GILLT_s128*//*Label 1826*/ GIMT_Encode4(95496), |
| 31269 | /*GILLT_v2s64*//*Label 1827*/ GIMT_Encode4(95522), |
| 31270 | /*GILLT_v4s32*//*Label 1828*/ GIMT_Encode4(95552), |
| 31271 | // Label 1824: @95344 |
| 31272 | GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(95417), |
| 31273 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31274 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 31275 | GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(95374), // Rule ID 942 // |
| 31276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 31277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31278 | // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSADDSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 31279 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDSP), |
| 31280 | GIR_RootConstrainSelectedInstOperands, |
| 31281 | // GIR_Coverage, 942, |
| 31282 | GIR_Done, |
| 31283 | // Label 1831: @95374 |
| 31284 | GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(95397), // Rule ID 235 // |
| 31285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 31287 | // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) |
| 31288 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADDS), |
| 31289 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31290 | GIR_RootConstrainSelectedInstOperands, |
| 31291 | // GIR_Coverage, 235, |
| 31292 | GIR_Done, |
| 31293 | // Label 1832: @95397 |
| 31294 | GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(95416), // Rule ID 575 // |
| 31295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 31297 | // (strict_fadd:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSADD:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 31298 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSADD), |
| 31299 | GIR_RootConstrainSelectedInstOperands, |
| 31300 | // GIR_Coverage, 575, |
| 31301 | GIR_Done, |
| 31302 | // Label 1833: @95416 |
| 31303 | GIM_Reject, |
| 31304 | // Label 1830: @95417 |
| 31305 | GIM_Reject, |
| 31306 | // Label 1825: @95418 |
| 31307 | GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(95495), |
| 31308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31309 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 31310 | GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(95452), // Rule ID 759 // |
| 31311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31313 | // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSADDDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 31314 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDDP), |
| 31315 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31316 | GIR_RootConstrainSelectedInstOperands, |
| 31317 | // GIR_Coverage, 759, |
| 31318 | GIR_Done, |
| 31319 | // Label 1835: @95452 |
| 31320 | GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(95475), // Rule ID 233 // |
| 31321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31323 | // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) |
| 31324 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FADD), |
| 31325 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31326 | GIR_RootConstrainSelectedInstOperands, |
| 31327 | // GIR_Coverage, 233, |
| 31328 | GIR_Done, |
| 31329 | // Label 1836: @95475 |
| 31330 | GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(95494), // Rule ID 554 // |
| 31331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 31333 | // (strict_fadd:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDADD:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 31334 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDADD), |
| 31335 | GIR_RootConstrainSelectedInstOperands, |
| 31336 | // GIR_Coverage, 554, |
| 31337 | GIR_Done, |
| 31338 | // Label 1837: @95494 |
| 31339 | GIM_Reject, |
| 31340 | // Label 1834: @95495 |
| 31341 | GIM_Reject, |
| 31342 | // Label 1826: @95496 |
| 31343 | GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(95521), // Rule ID 977 // |
| 31344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31345 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31346 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 31347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31348 | // (strict_fadd:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSADDQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 31349 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSADDQP), |
| 31350 | GIR_RootConstrainSelectedInstOperands, |
| 31351 | // GIR_Coverage, 977, |
| 31352 | GIR_Done, |
| 31353 | // Label 1838: @95521 |
| 31354 | GIM_Reject, |
| 31355 | // Label 1827: @95522 |
| 31356 | GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(95551), // Rule ID 763 // |
| 31357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31358 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31359 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 31360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31361 | // (strict_fadd:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVADDDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 31362 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDDP), |
| 31363 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31364 | GIR_RootConstrainSelectedInstOperands, |
| 31365 | // GIR_Coverage, 763, |
| 31366 | GIR_Done, |
| 31367 | // Label 1839: @95551 |
| 31368 | GIM_Reject, |
| 31369 | // Label 1828: @95552 |
| 31370 | GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(95581), // Rule ID 765 // |
| 31371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31372 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31373 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31375 | // (strict_fadd:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVADDSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 31376 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVADDSP), |
| 31377 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31378 | GIR_RootConstrainSelectedInstOperands, |
| 31379 | // GIR_Coverage, 765, |
| 31380 | GIR_Done, |
| 31381 | // Label 1840: @95581 |
| 31382 | GIM_Reject, |
| 31383 | // Label 1829: @95582 |
| 31384 | GIM_Reject, |
| 31385 | // Label 76: @95583 |
| 31386 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1846*/ GIMT_Encode4(95852), |
| 31387 | /*GILLT_s32*//*Label 1841*/ GIMT_Encode4(95614), |
| 31388 | /*GILLT_s64*//*Label 1842*/ GIMT_Encode4(95688), |
| 31389 | /*GILLT_s128*//*Label 1843*/ GIMT_Encode4(95766), |
| 31390 | /*GILLT_v2s64*//*Label 1844*/ GIMT_Encode4(95792), |
| 31391 | /*GILLT_v4s32*//*Label 1845*/ GIMT_Encode4(95822), |
| 31392 | // Label 1841: @95614 |
| 31393 | GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(95687), |
| 31394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 31396 | GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(95644), // Rule ID 946 // |
| 31397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 31398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31399 | // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSSUBSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 31400 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBSP), |
| 31401 | GIR_RootConstrainSelectedInstOperands, |
| 31402 | // GIR_Coverage, 946, |
| 31403 | GIR_Done, |
| 31404 | // Label 1848: @95644 |
| 31405 | GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(95667), // Rule ID 247 // |
| 31406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 31408 | // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) |
| 31409 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUBS), |
| 31410 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31411 | GIR_RootConstrainSelectedInstOperands, |
| 31412 | // GIR_Coverage, 247, |
| 31413 | GIR_Done, |
| 31414 | // Label 1849: @95667 |
| 31415 | GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(95686), // Rule ID 593 // |
| 31416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 31418 | // (strict_fsub:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSSUB:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 31419 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSSUB), |
| 31420 | GIR_RootConstrainSelectedInstOperands, |
| 31421 | // GIR_Coverage, 593, |
| 31422 | GIR_Done, |
| 31423 | // Label 1850: @95686 |
| 31424 | GIM_Reject, |
| 31425 | // Label 1847: @95687 |
| 31426 | GIM_Reject, |
| 31427 | // Label 1842: @95688 |
| 31428 | GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(95765), |
| 31429 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31430 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 31431 | GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(95722), // Rule ID 771 // |
| 31432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31434 | // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSSUBDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 31435 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBDP), |
| 31436 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31437 | GIR_RootConstrainSelectedInstOperands, |
| 31438 | // GIR_Coverage, 771, |
| 31439 | GIR_Done, |
| 31440 | // Label 1852: @95722 |
| 31441 | GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(95745), // Rule ID 245 // |
| 31442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31444 | // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) |
| 31445 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSUB), |
| 31446 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31447 | GIR_RootConstrainSelectedInstOperands, |
| 31448 | // GIR_Coverage, 245, |
| 31449 | GIR_Done, |
| 31450 | // Label 1853: @95745 |
| 31451 | GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(95764), // Rule ID 572 // |
| 31452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 31454 | // (strict_fsub:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDSUB:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 31455 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDSUB), |
| 31456 | GIR_RootConstrainSelectedInstOperands, |
| 31457 | // GIR_Coverage, 572, |
| 31458 | GIR_Done, |
| 31459 | // Label 1854: @95764 |
| 31460 | GIM_Reject, |
| 31461 | // Label 1851: @95765 |
| 31462 | GIM_Reject, |
| 31463 | // Label 1843: @95766 |
| 31464 | GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(95791), // Rule ID 981 // |
| 31465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31466 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31467 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 31468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31469 | // (strict_fsub:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 31470 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSUBQP), |
| 31471 | GIR_RootConstrainSelectedInstOperands, |
| 31472 | // GIR_Coverage, 981, |
| 31473 | GIR_Done, |
| 31474 | // Label 1855: @95791 |
| 31475 | GIM_Reject, |
| 31476 | // Label 1844: @95792 |
| 31477 | GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(95821), // Rule ID 773 // |
| 31478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31479 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31480 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 31481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31482 | // (strict_fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVSUBDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 31483 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBDP), |
| 31484 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31485 | GIR_RootConstrainSelectedInstOperands, |
| 31486 | // GIR_Coverage, 773, |
| 31487 | GIR_Done, |
| 31488 | // Label 1856: @95821 |
| 31489 | GIM_Reject, |
| 31490 | // Label 1845: @95822 |
| 31491 | GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(95851), // Rule ID 775 // |
| 31492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31493 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31496 | // (strict_fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVSUBSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 31497 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSUBSP), |
| 31498 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31499 | GIR_RootConstrainSelectedInstOperands, |
| 31500 | // GIR_Coverage, 775, |
| 31501 | GIR_Done, |
| 31502 | // Label 1857: @95851 |
| 31503 | GIM_Reject, |
| 31504 | // Label 1846: @95852 |
| 31505 | GIM_Reject, |
| 31506 | // Label 77: @95853 |
| 31507 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1863*/ GIMT_Encode4(96122), |
| 31508 | /*GILLT_s32*//*Label 1858*/ GIMT_Encode4(95884), |
| 31509 | /*GILLT_s64*//*Label 1859*/ GIMT_Encode4(95958), |
| 31510 | /*GILLT_s128*//*Label 1860*/ GIMT_Encode4(96036), |
| 31511 | /*GILLT_v2s64*//*Label 1861*/ GIMT_Encode4(96062), |
| 31512 | /*GILLT_v4s32*//*Label 1862*/ GIMT_Encode4(96092), |
| 31513 | // Label 1858: @95884 |
| 31514 | GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(95957), |
| 31515 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31516 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 31517 | GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(95914), // Rule ID 944 // |
| 31518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 31519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31520 | // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSMULSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 31521 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULSP), |
| 31522 | GIR_RootConstrainSelectedInstOperands, |
| 31523 | // GIR_Coverage, 944, |
| 31524 | GIR_Done, |
| 31525 | // Label 1865: @95914 |
| 31526 | GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(95937), // Rule ID 243 // |
| 31527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 31529 | // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) => (FMULS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC) |
| 31530 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMULS), |
| 31531 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31532 | GIR_RootConstrainSelectedInstOperands, |
| 31533 | // GIR_Coverage, 243, |
| 31534 | GIR_Done, |
| 31535 | // Label 1866: @95937 |
| 31536 | GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(95956), // Rule ID 589 // |
| 31537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 31539 | // (strict_fmul:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSMUL:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 31540 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSMUL), |
| 31541 | GIR_RootConstrainSelectedInstOperands, |
| 31542 | // GIR_Coverage, 589, |
| 31543 | GIR_Done, |
| 31544 | // Label 1867: @95956 |
| 31545 | GIM_Reject, |
| 31546 | // Label 1864: @95957 |
| 31547 | GIM_Reject, |
| 31548 | // Label 1859: @95958 |
| 31549 | GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(96035), |
| 31550 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31551 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 31552 | GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(95992), // Rule ID 761 // |
| 31553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31555 | // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSMULDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 31556 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULDP), |
| 31557 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31558 | GIR_RootConstrainSelectedInstOperands, |
| 31559 | // GIR_Coverage, 761, |
| 31560 | GIR_Done, |
| 31561 | // Label 1869: @95992 |
| 31562 | GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(96015), // Rule ID 241 // |
| 31563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31565 | // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) => (FMUL:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC) |
| 31566 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMUL), |
| 31567 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31568 | GIR_RootConstrainSelectedInstOperands, |
| 31569 | // GIR_Coverage, 241, |
| 31570 | GIR_Done, |
| 31571 | // Label 1870: @96015 |
| 31572 | GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(96034), // Rule ID 568 // |
| 31573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 31575 | // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDMUL:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 31576 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDMUL), |
| 31577 | GIR_RootConstrainSelectedInstOperands, |
| 31578 | // GIR_Coverage, 568, |
| 31579 | GIR_Done, |
| 31580 | // Label 1871: @96034 |
| 31581 | GIM_Reject, |
| 31582 | // Label 1868: @96035 |
| 31583 | GIM_Reject, |
| 31584 | // Label 1860: @96036 |
| 31585 | GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(96061), // Rule ID 979 // |
| 31586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31587 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 31589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31590 | // (strict_fmul:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSMULQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 31591 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSMULQP), |
| 31592 | GIR_RootConstrainSelectedInstOperands, |
| 31593 | // GIR_Coverage, 979, |
| 31594 | GIR_Done, |
| 31595 | // Label 1872: @96061 |
| 31596 | GIM_Reject, |
| 31597 | // Label 1861: @96062 |
| 31598 | GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(96091), // Rule ID 767 // |
| 31599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31600 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31601 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 31602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31603 | // (strict_fmul:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVMULDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 31604 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULDP), |
| 31605 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31606 | GIR_RootConstrainSelectedInstOperands, |
| 31607 | // GIR_Coverage, 767, |
| 31608 | GIR_Done, |
| 31609 | // Label 1873: @96091 |
| 31610 | GIM_Reject, |
| 31611 | // Label 1862: @96092 |
| 31612 | GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(96121), // Rule ID 769 // |
| 31613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31614 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31615 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31617 | // (strict_fmul:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVMULSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 31618 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVMULSP), |
| 31619 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31620 | GIR_RootConstrainSelectedInstOperands, |
| 31621 | // GIR_Coverage, 769, |
| 31622 | GIR_Done, |
| 31623 | // Label 1874: @96121 |
| 31624 | GIM_Reject, |
| 31625 | // Label 1863: @96122 |
| 31626 | GIM_Reject, |
| 31627 | // Label 78: @96123 |
| 31628 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1880*/ GIMT_Encode4(96392), |
| 31629 | /*GILLT_s32*//*Label 1875*/ GIMT_Encode4(96154), |
| 31630 | /*GILLT_s64*//*Label 1876*/ GIMT_Encode4(96228), |
| 31631 | /*GILLT_s128*//*Label 1877*/ GIMT_Encode4(96306), |
| 31632 | /*GILLT_v2s64*//*Label 1878*/ GIMT_Encode4(96332), |
| 31633 | /*GILLT_v4s32*//*Label 1879*/ GIMT_Encode4(96362), |
| 31634 | // Label 1875: @96154 |
| 31635 | GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(96227), |
| 31636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 31638 | GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(96184), // Rule ID 948 // |
| 31639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 31640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31641 | // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) => (XSDIVSP:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 31642 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVSP), |
| 31643 | GIR_RootConstrainSelectedInstOperands, |
| 31644 | // GIR_Coverage, 948, |
| 31645 | GIR_Done, |
| 31646 | // Label 1882: @96184 |
| 31647 | GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(96207), // Rule ID 239 // |
| 31648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 31650 | // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) => (FDIVS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRB) |
| 31651 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIVS), |
| 31652 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31653 | GIR_RootConstrainSelectedInstOperands, |
| 31654 | // GIR_Coverage, 239, |
| 31655 | GIR_Done, |
| 31656 | // Label 1883: @96207 |
| 31657 | GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(96226), // Rule ID 587 // |
| 31658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::GPRCRegClassID), |
| 31660 | // (strict_fdiv:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) => (EFSDIV:{ *:[f32] } f32:{ *:[f32] }:$RA, f32:{ *:[f32] }:$RB) |
| 31661 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFSDIV), |
| 31662 | GIR_RootConstrainSelectedInstOperands, |
| 31663 | // GIR_Coverage, 587, |
| 31664 | GIR_Done, |
| 31665 | // Label 1884: @96226 |
| 31666 | GIM_Reject, |
| 31667 | // Label 1881: @96227 |
| 31668 | GIM_Reject, |
| 31669 | // Label 1876: @96228 |
| 31670 | GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(96305), |
| 31671 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 31673 | GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(96262), // Rule ID 800 // |
| 31674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31676 | // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) => (XSDIVDP:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 31677 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVDP), |
| 31678 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31679 | GIR_RootConstrainSelectedInstOperands, |
| 31680 | // GIR_Coverage, 800, |
| 31681 | GIR_Done, |
| 31682 | // Label 1886: @96262 |
| 31683 | GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(96285), // Rule ID 237 // |
| 31684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31686 | // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) => (FDIV:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRB) |
| 31687 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FDIV), |
| 31688 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31689 | GIR_RootConstrainSelectedInstOperands, |
| 31690 | // GIR_Coverage, 237, |
| 31691 | GIR_Done, |
| 31692 | // Label 1887: @96285 |
| 31693 | GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(96304), // Rule ID 566 // |
| 31694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSPE), |
| 31695 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::SPERCRegClassID), |
| 31696 | // (strict_fdiv:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) => (EFDDIV:{ *:[f64] } f64:{ *:[f64] }:$RA, f64:{ *:[f64] }:$RB) |
| 31697 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::EFDDIV), |
| 31698 | GIR_RootConstrainSelectedInstOperands, |
| 31699 | // GIR_Coverage, 566, |
| 31700 | GIR_Done, |
| 31701 | // Label 1888: @96304 |
| 31702 | GIM_Reject, |
| 31703 | // Label 1885: @96305 |
| 31704 | GIM_Reject, |
| 31705 | // Label 1877: @96306 |
| 31706 | GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(96331), // Rule ID 983 // |
| 31707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31708 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31709 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 31710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31711 | // (strict_fdiv:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) => (XSDIVQP:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 31712 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSDIVQP), |
| 31713 | GIR_RootConstrainSelectedInstOperands, |
| 31714 | // GIR_Coverage, 983, |
| 31715 | GIR_Done, |
| 31716 | // Label 1889: @96331 |
| 31717 | GIM_Reject, |
| 31718 | // Label 1878: @96332 |
| 31719 | GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(96361), // Rule ID 809 // |
| 31720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31721 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31722 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 31723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31724 | // (strict_fdiv:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) => (XVDIVDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 31725 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVDP), |
| 31726 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31727 | GIR_RootConstrainSelectedInstOperands, |
| 31728 | // GIR_Coverage, 809, |
| 31729 | GIR_Done, |
| 31730 | // Label 1890: @96361 |
| 31731 | GIM_Reject, |
| 31732 | // Label 1879: @96362 |
| 31733 | GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(96391), // Rule ID 811 // |
| 31734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31735 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31738 | // (strict_fdiv:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) => (XVDIVSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 31739 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVDIVSP), |
| 31740 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31741 | GIR_RootConstrainSelectedInstOperands, |
| 31742 | // GIR_Coverage, 811, |
| 31743 | GIR_Done, |
| 31744 | // Label 1891: @96391 |
| 31745 | GIM_Reject, |
| 31746 | // Label 1880: @96392 |
| 31747 | GIM_Reject, |
| 31748 | // Label 79: @96393 |
| 31749 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1897*/ GIMT_Encode4(96950), |
| 31750 | /*GILLT_s32*//*Label 1892*/ GIMT_Encode4(96424), |
| 31751 | /*GILLT_s64*//*Label 1893*/ GIMT_Encode4(96570), |
| 31752 | /*GILLT_s128*//*Label 1894*/ GIMT_Encode4(96716), |
| 31753 | /*GILLT_v2s64*//*Label 1895*/ GIMT_Encode4(96794), |
| 31754 | /*GILLT_v4s32*//*Label 1896*/ GIMT_Encode4(96872), |
| 31755 | // Label 1892: @96424 |
| 31756 | GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(96569), |
| 31757 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 31758 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 31759 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 31760 | GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(96479), // Rule ID 958 // |
| 31761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 31762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31763 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31764 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31765 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 31766 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31767 | // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, (fneg:{ *:[f32] } f32:{ *:[f32] }:$XTi)) => (XSMSUBASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 31768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBASP), |
| 31769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31770 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 31771 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31772 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31773 | GIR_RootConstrainSelectedInstOperands, |
| 31774 | // GIR_Coverage, 958, |
| 31775 | GIR_EraseRootFromParent_Done, |
| 31776 | // Label 1899: @96479 |
| 31777 | GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(96504), // Rule ID 956 // |
| 31778 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 31779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 31780 | // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB, f32:{ *:[f32] }:$XTi) => (XSMADDASP:{ *:[f32] } f32:{ *:[f32] }:$XTi, f32:{ *:[f32] }:$XA, f32:{ *:[f32] }:$XB) |
| 31781 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDASP), |
| 31782 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31783 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 31784 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31785 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31786 | GIR_RootConstrainSelectedInstOperands, |
| 31787 | // GIR_Coverage, 956, |
| 31788 | GIR_EraseRootFromParent_Done, |
| 31789 | // Label 1900: @96504 |
| 31790 | GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(96545), // Rule ID 221 // |
| 31791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 31793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 31796 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31797 | // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, (fneg:{ *:[f32] } f32:{ *:[f32] }:$FRB)) => (FMSUBS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 31798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUBS), |
| 31799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 31800 | GIR_RootToRootCopy, /*OpIdx*/1, // FRA |
| 31801 | GIR_RootToRootCopy, /*OpIdx*/2, // FRC |
| 31802 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB |
| 31803 | GIR_RootConstrainSelectedInstOperands, |
| 31804 | // GIR_Coverage, 221, |
| 31805 | GIR_EraseRootFromParent_Done, |
| 31806 | // Label 1901: @96545 |
| 31807 | GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(96568), // Rule ID 217 // |
| 31808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 31810 | // (strict_fma:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) => (FMADDS:{ *:[f32] } f32:{ *:[f32] }:$FRA, f32:{ *:[f32] }:$FRC, f32:{ *:[f32] }:$FRB) |
| 31811 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADDS), |
| 31812 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31813 | GIR_RootConstrainSelectedInstOperands, |
| 31814 | // GIR_Coverage, 217, |
| 31815 | GIR_Done, |
| 31816 | // Label 1902: @96568 |
| 31817 | GIM_Reject, |
| 31818 | // Label 1898: @96569 |
| 31819 | GIM_Reject, |
| 31820 | // Label 1893: @96570 |
| 31821 | GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(96715), |
| 31822 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 31823 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 31824 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 31825 | GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(96625), // Rule ID 779 // |
| 31826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 31831 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31832 | // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, (fneg:{ *:[f64] } f64:{ *:[f64] }:$XTi)) => (XSMSUBADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 31833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBADP), |
| 31834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31835 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 31836 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31837 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31838 | GIR_RootConstrainSelectedInstOperands, |
| 31839 | // GIR_Coverage, 779, |
| 31840 | GIR_EraseRootFromParent_Done, |
| 31841 | // Label 1904: @96625 |
| 31842 | GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(96650), // Rule ID 777 // |
| 31843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 31845 | // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB, f64:{ *:[f64] }:$XTi) => (XSMADDADP:{ *:[f64] } f64:{ *:[f64] }:$XTi, f64:{ *:[f64] }:$XA, f64:{ *:[f64] }:$XB) |
| 31846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDADP), |
| 31847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31848 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 31849 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31850 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31851 | GIR_RootConstrainSelectedInstOperands, |
| 31852 | // GIR_Coverage, 777, |
| 31853 | GIR_EraseRootFromParent_Done, |
| 31854 | // Label 1905: @96650 |
| 31855 | GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(96691), // Rule ID 219 // |
| 31856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31858 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31859 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31860 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 31861 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31862 | // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, (fneg:{ *:[f64] } f64:{ *:[f64] }:$FRB)) => (FMSUB:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 31863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::FMSUB), |
| 31864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[FRT] |
| 31865 | GIR_RootToRootCopy, /*OpIdx*/1, // FRA |
| 31866 | GIR_RootToRootCopy, /*OpIdx*/2, // FRC |
| 31867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // FRB |
| 31868 | GIR_RootConstrainSelectedInstOperands, |
| 31869 | // GIR_Coverage, 219, |
| 31870 | GIR_EraseRootFromParent_Done, |
| 31871 | // Label 1906: @96691 |
| 31872 | GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(96714), // Rule ID 215 // |
| 31873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 31874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 31875 | // (strict_fma:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) => (FMADD:{ *:[f64] } f64:{ *:[f64] }:$FRA, f64:{ *:[f64] }:$FRC, f64:{ *:[f64] }:$FRB) |
| 31876 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FMADD), |
| 31877 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 31878 | GIR_RootConstrainSelectedInstOperands, |
| 31879 | // GIR_Coverage, 215, |
| 31880 | GIR_Done, |
| 31881 | // Label 1907: @96714 |
| 31882 | GIM_Reject, |
| 31883 | // Label 1903: @96715 |
| 31884 | GIM_Reject, |
| 31885 | // Label 1894: @96716 |
| 31886 | GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(96793), |
| 31887 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 31888 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s128, |
| 31889 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s128, |
| 31890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 31891 | GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(96771), // Rule ID 989 // |
| 31892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31894 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31895 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s128, |
| 31896 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31897 | // (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, (fneg:{ *:[f128] } f128:{ *:[f128] }:$RSTi)) => (XSMSUBQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 31898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMSUBQP), |
| 31899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 31900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RSTi |
| 31901 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 31902 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 31903 | GIR_RootConstrainSelectedInstOperands, |
| 31904 | // GIR_Coverage, 989, |
| 31905 | GIR_EraseRootFromParent_Done, |
| 31906 | // Label 1909: @96771 |
| 31907 | GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(96792), // Rule ID 987 // |
| 31908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 31909 | // (strict_fma:{ *:[f128] } f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB, f128:{ *:[f128] }:$RSTi) => (XSMADDQP:{ *:[f128] } f128:{ *:[f128] }:$RSTi, f128:{ *:[f128] }:$RA, f128:{ *:[f128] }:$RB) |
| 31910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XSMADDQP), |
| 31911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RST] |
| 31912 | GIR_RootToRootCopy, /*OpIdx*/3, // RSTi |
| 31913 | GIR_RootToRootCopy, /*OpIdx*/1, // RA |
| 31914 | GIR_RootToRootCopy, /*OpIdx*/2, // RB |
| 31915 | GIR_RootConstrainSelectedInstOperands, |
| 31916 | // GIR_Coverage, 987, |
| 31917 | GIR_EraseRootFromParent_Done, |
| 31918 | // Label 1910: @96792 |
| 31919 | GIM_Reject, |
| 31920 | // Label 1908: @96793 |
| 31921 | GIM_Reject, |
| 31922 | // Label 1895: @96794 |
| 31923 | GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(96871), |
| 31924 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31925 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 31926 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 31927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31928 | GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(96849), // Rule ID 789 // |
| 31929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31930 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31931 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31932 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 31933 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31934 | // (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, (fneg:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi)) => (XVMSUBADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 31935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBADP), |
| 31936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 31938 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31939 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31940 | GIR_RootConstrainSelectedInstOperands, |
| 31941 | // GIR_Coverage, 789, |
| 31942 | GIR_EraseRootFromParent_Done, |
| 31943 | // Label 1912: @96849 |
| 31944 | GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(96870), // Rule ID 785 // |
| 31945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31946 | // (strict_fma:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB, v2f64:{ *:[v2f64] }:$XTi) => (XVMADDADP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XTi, v2f64:{ *:[v2f64] }:$XA, v2f64:{ *:[v2f64] }:$XB) |
| 31947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDADP), |
| 31948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31949 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 31950 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31951 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31952 | GIR_RootConstrainSelectedInstOperands, |
| 31953 | // GIR_Coverage, 785, |
| 31954 | GIR_EraseRootFromParent_Done, |
| 31955 | // Label 1913: @96870 |
| 31956 | GIM_Reject, |
| 31957 | // Label 1911: @96871 |
| 31958 | GIM_Reject, |
| 31959 | // Label 1896: @96872 |
| 31960 | GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(96949), |
| 31961 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31962 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31963 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 31965 | GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(96927), // Rule ID 791 // |
| 31966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31967 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 31968 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 31969 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 31970 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31971 | // (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, (fneg:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi)) => (XVMSUBASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 31972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMSUBASP), |
| 31973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31974 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // XTi |
| 31975 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31976 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31977 | GIR_RootConstrainSelectedInstOperands, |
| 31978 | // GIR_Coverage, 791, |
| 31979 | GIR_EraseRootFromParent_Done, |
| 31980 | // Label 1915: @96927 |
| 31981 | GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(96948), // Rule ID 787 // |
| 31982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 31983 | // (strict_fma:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB, v4f32:{ *:[v4f32] }:$XTi) => (XVMADDASP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XTi, v4f32:{ *:[v4f32] }:$XA, v4f32:{ *:[v4f32] }:$XB) |
| 31984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(PPC::XVMADDASP), |
| 31985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[XT] |
| 31986 | GIR_RootToRootCopy, /*OpIdx*/3, // XTi |
| 31987 | GIR_RootToRootCopy, /*OpIdx*/1, // XA |
| 31988 | GIR_RootToRootCopy, /*OpIdx*/2, // XB |
| 31989 | GIR_RootConstrainSelectedInstOperands, |
| 31990 | // GIR_Coverage, 787, |
| 31991 | GIR_EraseRootFromParent_Done, |
| 31992 | // Label 1916: @96948 |
| 31993 | GIM_Reject, |
| 31994 | // Label 1914: @96949 |
| 31995 | GIM_Reject, |
| 31996 | // Label 1897: @96950 |
| 31997 | GIM_Reject, |
| 31998 | // Label 80: @96951 |
| 31999 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(6), /*)*//*default:*//*Label 1922*/ GIMT_Encode4(97167), |
| 32000 | /*GILLT_s32*//*Label 1917*/ GIMT_Encode4(96982), |
| 32001 | /*GILLT_s64*//*Label 1918*/ GIMT_Encode4(97034), |
| 32002 | /*GILLT_s128*//*Label 1919*/ GIMT_Encode4(97090), |
| 32003 | /*GILLT_v2s64*//*Label 1920*/ GIMT_Encode4(97113), |
| 32004 | /*GILLT_v4s32*//*Label 1921*/ GIMT_Encode4(97140), |
| 32005 | // Label 1917: @96982 |
| 32006 | GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(97033), |
| 32007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32008 | GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(97009), // Rule ID 953 // |
| 32009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP8Vector_HasVSX), |
| 32010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSSRCRegClassID), |
| 32011 | // (strict_fsqrt:{ *:[f32] } f32:{ *:[f32] }:$XB) => (XSSQRTSP:{ *:[f32] } f32:{ *:[f32] }:$XB) |
| 32012 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTSP), |
| 32013 | GIR_RootConstrainSelectedInstOperands, |
| 32014 | // GIR_Coverage, 953, |
| 32015 | GIR_Done, |
| 32016 | // Label 1924: @97009 |
| 32017 | GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(97032), // Rule ID 158 // |
| 32018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 32019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F4RCRegClassID), |
| 32020 | // (strict_fsqrt:{ *:[f32] } f32:{ *:[f32] }:$RB) => (FSQRTS:{ *:[f32] } f32:{ *:[f32] }:$RB) |
| 32021 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRTS), |
| 32022 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 32023 | GIR_RootConstrainSelectedInstOperands, |
| 32024 | // GIR_Coverage, 158, |
| 32025 | GIR_Done, |
| 32026 | // Label 1925: @97032 |
| 32027 | GIM_Reject, |
| 32028 | // Label 1923: @97033 |
| 32029 | GIM_Reject, |
| 32030 | // Label 1918: @97034 |
| 32031 | GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(97089), |
| 32032 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 32033 | GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(97065), // Rule ID 802 // |
| 32034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 32035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSFRCRegClassID), |
| 32036 | // (strict_fsqrt:{ *:[f64] } f64:{ *:[f64] }:$XB) => (XSSQRTDP:{ *:[f64] } f64:{ *:[f64] }:$XB) |
| 32037 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTDP), |
| 32038 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 32039 | GIR_RootConstrainSelectedInstOperands, |
| 32040 | // GIR_Coverage, 802, |
| 32041 | GIR_Done, |
| 32042 | // Label 1927: @97065 |
| 32043 | GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(97088), // Rule ID 156 // |
| 32044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPU), |
| 32045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::F8RCRegClassID), |
| 32046 | // (strict_fsqrt:{ *:[f64] } f64:{ *:[f64] }:$RB) => (FSQRT:{ *:[f64] } f64:{ *:[f64] }:$RB) |
| 32047 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::FSQRT), |
| 32048 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 32049 | GIR_RootConstrainSelectedInstOperands, |
| 32050 | // GIR_Coverage, 156, |
| 32051 | GIR_Done, |
| 32052 | // Label 1928: @97088 |
| 32053 | GIM_Reject, |
| 32054 | // Label 1926: @97089 |
| 32055 | GIM_Reject, |
| 32056 | // Label 1919: @97090 |
| 32057 | GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(97112), // Rule ID 985 // |
| 32058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasP9Vector_HasVSX), |
| 32059 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128, |
| 32060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VRRCRegClassID), |
| 32061 | // (strict_fsqrt:{ *:[f128] } f128:{ *:[f128] }:$RB) => (XSSQRTQP:{ *:[f128] } f128:{ *:[f128] }:$RB) |
| 32062 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XSSQRTQP), |
| 32063 | GIR_RootConstrainSelectedInstOperands, |
| 32064 | // GIR_Coverage, 985, |
| 32065 | GIR_Done, |
| 32066 | // Label 1929: @97112 |
| 32067 | GIM_Reject, |
| 32068 | // Label 1920: @97113 |
| 32069 | GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(97139), // Rule ID 813 // |
| 32070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 32071 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 32072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 32073 | // (strict_fsqrt:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) => (XVSQRTDP:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$XB) |
| 32074 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTDP), |
| 32075 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 32076 | GIR_RootConstrainSelectedInstOperands, |
| 32077 | // GIR_Coverage, 813, |
| 32078 | GIR_Done, |
| 32079 | // Label 1930: @97139 |
| 32080 | GIM_Reject, |
| 32081 | // Label 1921: @97140 |
| 32082 | GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(97166), // Rule ID 815 // |
| 32083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVSX), |
| 32084 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 32085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(PPC::VSRCRegClassID), |
| 32086 | // (strict_fsqrt:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) => (XVSQRTSP:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$XB) |
| 32087 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::XVSQRTSP), |
| 32088 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(PPC::RM), |
| 32089 | GIR_RootConstrainSelectedInstOperands, |
| 32090 | // GIR_Coverage, 815, |
| 32091 | GIR_Done, |
| 32092 | // Label 1931: @97166 |
| 32093 | GIM_Reject, |
| 32094 | // Label 1922: @97167 |
| 32095 | GIM_Reject, |
| 32096 | // Label 81: @97168 |
| 32097 | GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(97180), // Rule ID 72 // |
| 32098 | // (trap) => (TRAP) |
| 32099 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(PPC::TRAP), |
| 32100 | GIR_RootConstrainSelectedInstOperands, |
| 32101 | // GIR_Coverage, 72, |
| 32102 | GIR_Done, |
| 32103 | // Label 1932: @97180 |
| 32104 | GIM_Reject, |
| 32105 | // Label 82: @97181 |
| 32106 | GIM_Reject, |
| 32107 | }; // Size: 97182 bytes |
| 32108 | return MatchTable0; |
| 32109 | } |
| 32110 | #undef GIMT_Encode2 |
| 32111 | #undef GIMT_Encode4 |
| 32112 | #undef GIMT_Encode8 |
| 32113 | |
| 32114 | #endif // ifdef GET_GLOBALISEL_IMPL |
| 32115 | |
| 32116 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 32117 | PredicateBitset AvailableModuleFeatures; |
| 32118 | mutable PredicateBitset AvailableFunctionFeatures; |
| 32119 | PredicateBitset getAvailableFeatures() const { |
| 32120 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 32121 | } |
| 32122 | PredicateBitset |
| 32123 | computeAvailableModuleFeatures(const PPCSubtarget *Subtarget) const; |
| 32124 | PredicateBitset |
| 32125 | computeAvailableFunctionFeatures(const PPCSubtarget *Subtarget, |
| 32126 | const MachineFunction *MF) const; |
| 32127 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 32128 | #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 32129 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 32130 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 32131 | AvailableFunctionFeatures() |
| 32132 | #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 32133 |
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