1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Register Bank Source Fragments *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_REGBANK_DECLARATIONS
10#undef GET_REGBANK_DECLARATIONS
11namespace llvm {
12namespace PPC {
13enum : unsigned {
14 InvalidRegBankID = ~0u,
15 CRRegBankID = 0,
16 FPRRegBankID = 1,
17 GPRRegBankID = 2,
18 VECRegBankID = 3,
19 NumRegisterBanks,
20};
21} // end namespace PPC
22} // end namespace llvm
23#endif // GET_REGBANK_DECLARATIONS
24
25#ifdef GET_TARGET_REGBANK_CLASS
26#undef GET_TARGET_REGBANK_CLASS
27private:
28 static const RegisterBank *RegBanks[];
29 static const unsigned Sizes[];
30
31protected:
32 PPCGenRegisterBankInfo(unsigned HwMode = 0);
33
34#endif // GET_TARGET_REGBANK_CLASS
35
36#ifdef GET_TARGET_REGBANK_IMPL
37#undef GET_TARGET_REGBANK_IMPL
38namespace llvm {
39namespace PPC {
40const uint32_t CRRegBankCoverageData[] = {
41 // 0-31
42 (1u << (PPC::CRRCRegClassID - 0)) |
43 (1u << (PPC::CRBITRCRegClassID - 0)) |
44 0,
45 // 32-63
46 0,
47};
48const uint32_t FPRRegBankCoverageData[] = {
49 // 0-31
50 (1u << (PPC::VSSRCRegClassID - 0)) |
51 (1u << (PPC::F4RCRegClassID - 0)) |
52 (1u << (PPC::F8RCRegClassID - 0)) |
53 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
54 (1u << (PPC::VSFRCRegClassID - 0)) |
55 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
56 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
57 (1u << (PPC::VFRCRegClassID - 0)) |
58 0,
59 // 32-63
60 0,
61};
62const uint32_t GPRRegBankCoverageData[] = {
63 // 0-31
64 (1u << (PPC::G8RCRegClassID - 0)) |
65 (1u << (PPC::GPRCRegClassID - 0)) |
66 (1u << (PPC::G8RC_and_G8RC_NOX0RegClassID - 0)) |
67 (1u << (PPC::GPRC_NOR0RegClassID - 0)) |
68 (1u << (PPC::GPRC_and_GPRC_NOR0RegClassID - 0)) |
69 (1u << (PPC::G8RC_NOX0RegClassID - 0)) |
70 0,
71 // 32-63
72 0,
73};
74const uint32_t VECRegBankCoverageData[] = {
75 // 0-31
76 (1u << (PPC::VSRCRegClassID - 0)) |
77 (1u << (PPC::VSSRCRegClassID - 0)) |
78 (1u << (PPC::VSFRCRegClassID - 0)) |
79 (1u << (PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 0)) |
80 (1u << (PPC::SPILLTOVSRRCRegClassID - 0)) |
81 (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
82 (1u << (PPC::VFRCRegClassID - 0)) |
83 (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
84 (1u << (PPC::F4RCRegClassID - 0)) |
85 (1u << (PPC::F8RCRegClassID - 0)) |
86 (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
87 (1u << (PPC::VRRCRegClassID - 0)) |
88 0,
89 // 32-63
90 (1u << (PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
91 (1u << (PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
92 (1u << (PPC::VSLRCRegClassID - 32)) |
93 0,
94};
95
96constexpr RegisterBank CRRegBank(/* ID */ PPC::CRRegBankID, /* Name */ "CR", /* CoveredRegClasses */ CRRegBankCoverageData, /* NumRegClasses */ 56);
97constexpr RegisterBank FPRRegBank(/* ID */ PPC::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 56);
98constexpr RegisterBank GPRRegBank(/* ID */ PPC::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 56);
99constexpr RegisterBank VECRegBank(/* ID */ PPC::VECRegBankID, /* Name */ "VEC", /* CoveredRegClasses */ VECRegBankCoverageData, /* NumRegClasses */ 56);
100} // end namespace PPC
101
102const RegisterBank *PPCGenRegisterBankInfo::RegBanks[] = {
103 &PPC::CRRegBank,
104 &PPC::FPRRegBank,
105 &PPC::GPRRegBank,
106 &PPC::VECRegBank,
107};
108
109const unsigned PPCGenRegisterBankInfo::Sizes[] = {
110 // Mode = 0 (Default)
111 32,
112 64,
113 64,
114 128,
115};
116
117PPCGenRegisterBankInfo::PPCGenRegisterBankInfo(unsigned HwMode)
118 : RegisterBankInfo(RegBanks, PPC::NumRegisterBanks, Sizes, HwMode) {
119 // Assert that RegBank indices match their ID's
120#ifndef NDEBUG
121 for (auto RB : enumerate(RegBanks))
122 assert(RB.index() == RB.value()->getID() && "Index != ID");
123#endif // NDEBUG
124}
125} // end namespace llvm
126#endif // GET_TARGET_REGBANK_IMPL
127